1 /* Target-dependent code for GNU/Linux on RISC-V processors.
2 Copyright (C) 2018-2019 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 #include "riscv-tdep.h"
22 #include "glibc-tdep.h"
23 #include "linux-tdep.h"
24 #include "solib-svr4.h"
26 #include "tramp-frame.h"
27 #include "trad-frame.h"
29 /* Define the general register mapping. The kernel puts the PC at offset 0,
30 gdb puts it at offset 32. Register x0 is always 0 and can be ignored.
31 Registers x1 to x31 are in the same place. */
33 static const struct regcache_map_entry riscv_linux_gregmap
[] =
35 { 1, RISCV_PC_REGNUM
, 0 },
36 { 31, RISCV_RA_REGNUM
, 0 }, /* x1 to x31 */
40 /* Define the FP register mapping. The kernel puts the 32 FP regs first, and
43 static const struct regcache_map_entry riscv_linux_fregmap
[] =
45 { 32, RISCV_FIRST_FP_REGNUM
, 0 },
46 { 1, RISCV_CSR_FCSR_REGNUM
, 0 },
50 /* Define the general register regset. */
52 static const struct regset riscv_linux_gregset
=
54 riscv_linux_gregmap
, regcache_supply_regset
, regcache_collect_regset
57 /* Define the FP register regset. */
59 static const struct regset riscv_linux_fregset
=
61 riscv_linux_fregmap
, regcache_supply_regset
, regcache_collect_regset
64 /* Define hook for core file support. */
67 riscv_linux_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
68 iterate_over_regset_sections_cb
*cb
,
70 const struct regcache
*regcache
)
72 cb (".reg", (32 * riscv_isa_xlen (gdbarch
)), (32 * riscv_isa_xlen (gdbarch
)),
73 &riscv_linux_gregset
, NULL
, cb_data
);
74 /* The kernel is adding 8 bytes for FCSR. */
75 cb (".reg2", (32 * riscv_isa_flen (gdbarch
)) + 8,
76 (32 * riscv_isa_flen (gdbarch
)) + 8,
77 &riscv_linux_fregset
, NULL
, cb_data
);
80 /* Signal trampoline support. */
82 static void riscv_linux_sigframe_init (const struct tramp_frame
*self
,
83 struct frame_info
*this_frame
,
84 struct trad_frame_cache
*this_cache
,
87 #define RISCV_INST_LI_A7_SIGRETURN 0x08b00893
88 #define RISCV_INST_ECALL 0x00000073
90 static const struct tramp_frame riscv_linux_sigframe
= {
94 { RISCV_INST_LI_A7_SIGRETURN
, ULONGEST_MAX
},
95 { RISCV_INST_ECALL
, ULONGEST_MAX
},
96 { TRAMP_SENTINEL_INSN
}
98 riscv_linux_sigframe_init
,
102 /* Runtime signal frames look like this:
109 unsigned long __uc_flags;
110 struct ucontext *uclink;
113 char __glibc_reserved[1024 / 8 - sizeof (sigset_t)];
114 mcontext_t uc_mcontext;
117 #define SIGFRAME_SIGINFO_SIZE 128
118 #define UCONTEXT_MCONTEXT_OFFSET 176
121 riscv_linux_sigframe_init (const struct tramp_frame
*self
,
122 struct frame_info
*this_frame
,
123 struct trad_frame_cache
*this_cache
,
126 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
127 int xlen
= riscv_isa_xlen (gdbarch
);
128 int flen
= riscv_isa_flen (gdbarch
);
129 CORE_ADDR frame_sp
= get_frame_sp (this_frame
);
130 CORE_ADDR mcontext_base
;
133 mcontext_base
= frame_sp
+ SIGFRAME_SIGINFO_SIZE
+ UCONTEXT_MCONTEXT_OFFSET
;
135 /* Handle the integer registers. The first one is PC, followed by x1
137 regs_base
= mcontext_base
;
138 trad_frame_set_reg_addr (this_cache
, RISCV_PC_REGNUM
, regs_base
);
139 for (int i
= 1; i
< 32; i
++)
140 trad_frame_set_reg_addr (this_cache
, RISCV_ZERO_REGNUM
+ i
,
141 regs_base
+ (i
* xlen
));
143 /* Handle the FP registers. First comes the 32 FP registers, followed by
145 regs_base
+= 32 * xlen
;
146 for (int i
= 0; i
< 32; i
++)
147 trad_frame_set_reg_addr (this_cache
, RISCV_FIRST_FP_REGNUM
+ i
,
148 regs_base
+ (i
* flen
));
149 regs_base
+= 32 * flen
;
150 trad_frame_set_reg_addr (this_cache
, RISCV_CSR_FCSR_REGNUM
, regs_base
);
152 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
153 trad_frame_set_id (this_cache
, frame_id_build (frame_sp
, func
));
156 /* Initialize RISC-V Linux ABI info. */
159 riscv_linux_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
161 linux_init_abi (info
, gdbarch
);
163 set_gdbarch_software_single_step (gdbarch
, riscv_software_single_step
);
165 set_solib_svr4_fetch_link_map_offsets (gdbarch
,
166 (riscv_isa_xlen (gdbarch
) == 4
167 ? svr4_ilp32_fetch_link_map_offsets
168 : svr4_lp64_fetch_link_map_offsets
));
170 /* GNU/Linux uses SVR4-style shared libraries. */
171 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
173 /* GNU/Linux uses the dynamic linker included in the GNU C Library. */
174 set_gdbarch_skip_solib_resolver (gdbarch
, glibc_skip_solib_resolver
);
176 /* Enable TLS support. */
177 set_gdbarch_fetch_tls_load_module_address (gdbarch
,
178 svr4_fetch_objfile_link_map
);
180 set_gdbarch_iterate_over_regset_sections
181 (gdbarch
, riscv_linux_iterate_over_regset_sections
);
183 tramp_frame_prepend_unwinder (gdbarch
, &riscv_linux_sigframe
);
186 /* Initialize RISC-V Linux target support. */
189 _initialize_riscv_linux_tdep (void)
191 gdbarch_register_osabi (bfd_arch_riscv
, 0, GDB_OSABI_LINUX
,
192 riscv_linux_init_abi
);