gdb/testsuite/gdb.arch/arc-decode-insn.exp

   1 # This testcase is part of GDB, the GNU debugger.
   2
   3 # Copyright 2017-2019 Free Software Foundation, Inc.
   4
   5 # This program is free software; you can redistribute it and/or modify
   6 # it under the terms of the GNU General Public License as published by
   7 # the Free Software Foundation; either version 3 of the License, or
   8 # (at your option) any later version.
   9 #
  10 # This program is distributed in the hope that it will be useful,
  11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 # GNU General Public License for more details.
  14 #
  15 # You should have received a copy of the GNU General Public License
  16 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17
  18
  19 # These tests provides certain degree of testing for arc_insn functions,
  20 # however it is not a comprehensive testsuite that would go through all
  21 # possible ARC instructions - instead this particular test is focused on branch
  22 # instructions and whether branch targets are evaluated properly.  Most of the
  23 # non-branch aspects of instruction decoder are used during prologue analysis,
  24 # so are indirictly tested there.
  25
  26 # To maintain separation of test data and test logic, all of the information
  27 # about instructions, like if it has delay slot, condition code, branch target
  28 # address, is all specified in the test assembly file as a symbols, while this
  29 # test case reads those symbols to learn which values are right, then compares
  30 # values coming from decoder with those found in symbols.  More information
  31 # about requirements to actual test cases can be found in corresponding
  32 # assembly file of this test case (arc-decode-insn.S).
  33
  34 if {![istarget "arc*-*-*"]} then {
  35     verbose "Skipping ARC decoder test."
  36     return
  37 }
  38
  39 standard_testfile .S
  40
  41 if { [prepare_for_testing "failed to prepare" $testfile $srcfile] } {
  42     return -1
  43 }
  44
  45 if ![runto_main] {
  46     fail "can't run to main"
  47     return 0
  48 }
  49
  50 # Helper function that reads properties of instruction from the ELF file via
  51 # its symbols and then confirms that decoder output aligns to the expected
  52 # values.
  53 proc test_branch_insn { test_name } {
  54
  55     # Make messages for failed cases more clear, by using hex in them.
  56     set pc [get_hexadecimal_valueof &${test_name}_start -1]
  57
  58     # Calculate instruction length, based on ${test_name}_end symbol.
  59     set end_pc [get_hexadecimal_valueof &${test_name}_end -1]
  60     set length [expr $end_pc - $pc]
  61
  62     set target_address [get_hexadecimal_valueof &${test_name}_target -1]
  63
  64     # Figure out if there is a delay slot, using symbol
  65     # ${test_name}_has_delay_slot.  Note that it should be read via &,
  66     # otherwise it would try to print value at the address specified in
  67     # ${test_name}_has_delay_slot, while a symbol value itself is required.
  68     if { 0 == [get_integer_valueof &${test_name}_has_delay_slot 0] } {
  69         set has_delay_slot 0
  70     } else {
  71         set has_delay_slot 1
  72     }
  73
  74     set cc [get_hexadecimal_valueof &${test_name}_cc 0]
  75
  76     # Can't use {} to create a list of items, because variables will not be
  77     # evaluated inside the {}.
  78     gdb_test_sequence "mt print arc arc-instruction $pc" "" [list \
  79         "length_with_limm = $length" \
  80         "cc = $cc" \
  81         "is_control_flow = 1" \
  82         "has_delay_slot = $has_delay_slot" \
  83         "branch_target = $target_address"]
  84 }
  85
  86 set branch_test_list { }
  87
  88 # Add items in the same groups as they can be enabled/disabled in assembly
  89 # file.
  90 lappend branch_test_list \
  91     j_c j_blink j_limm j_u6 j_s12 j_d_c j_d_blink j_d_u6
  92 lappend branch_test_list \
  93     jcc_c jcc_blink jcc_limm jcc_u6 jcc_d_c jcc_d_blink jcc_d_u6 \
  94     jcc_eq_s_blink jcc_ne_s_blink
  95 lappend branch_test_list \
  96     jl_c jl_limm jl_u6 jl_s12 jl_d_c jl_d_u6 jl_d_s12 jl_s_b jl_s_d_b
  97 lappend branch_test_list \
  98     jlcc_c jlcc_limm jlcc_u6 jlcc_d_c jlcc_d_u6
  99 lappend branch_test_list \
 100     b_s25 b_d_s25 b_s_s10
 101 lappend branch_test_list \
 102     bbit0_nt_b_c_s9 bbit0_d_nt_b_c_s9 bbit0_t_b_c_s9 bbit0_d_t_b_c_s9 \
 103     bbit0_nt_b_u6_s9 bbit0_d_nt_b_u6_s9 bbit0_t_b_u6_s9 bbit0_d_t_b_u6_s9 \
 104     bbit0_nt_b_limm_s9 bbit0_t_b_limm_s9 bbit0_nt_limm_c_s9 bbit0_t_limm_c_s9 \
 105     bbit0_nt_limm_u6_s9 bbit0_t_limm_u6_s9 \
 106     bbit1_nt_b_c_s9 bbit1_d_nt_b_c_s9 bbit1_t_b_c_s9 bbit1_d_t_b_c_s9 \
 107     bbit1_nt_b_u6_s9 bbit1_d_nt_b_u6_s9 bbit1_t_b_u6_s9 bbit1_d_t_b_u6_s9 \
 108     bbit1_nt_b_limm_s9 bbit1_t_b_limm_s9 bbit1_nt_limm_c_s9 bbit1_t_limm_c_s9 \
 109     bbit1_nt_limm_u6_s9 bbit1_t_limm_u6_s9
 110 lappend branch_test_list \
 111     bcc_s21 bcc_d_s21 \
 112     beq_s_s10 bne_s_s10 bgt_s_s7 bge_s_s7 blt_s_s7 ble_s_s7 bhi_s_s7 bhs_s_s7 \
 113     blo_s_s7 bls_s_s7
 114 lappend branch_test_list \
 115     bi_c bih_c
 116 lappend branch_test_list \
 117     bl_s25 bl_d_s25 bl_s_s13 \
 118     blcc_s21 blcc_d_s21
 119 lappend branch_test_list \
 120      breq_nt_b_c_s9 breq_d_nt_b_c_s9 breq_t_b_c_s9 breq_d_t_b_c_s9 \
 121      breq_nt_b_u6_s9 breq_d_nt_b_u6_s9 breq_t_b_u6_s9 breq_d_t_b_u6_s9 \
 122      breq_nt_b_limm_s9 breq_t_b_limm_s9 breq_nt_limm_c_s9 breq_t_limm_c_s9 \
 123      breq_nt_limm_u6_s9 breq_t_limm_u6_s9
 124 # lappend branch_test_list jli_s_u10
 125 lappend branch_test_list leave_s
 126 lappend branch_test_list lpcc_u7
 127
 128 runto start_branch_tests
 129 foreach test $branch_test_list {
 130     test_branch_insn $test
 131 }
 132