1 /* Ravenscar RISC-V target support.
3 Copyright (C) 2019-2022 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "riscv-tdep.h"
26 #include "ravenscar-thread.h"
27 #include "riscv-ravenscar-thread.h"
29 struct riscv_ravenscar_ops
: public ravenscar_arch_ops
31 void fetch_registers (struct regcache
*regcache
, int regnum
) override
;
32 void store_registers (struct regcache
*regcache
, int regnum
) override
;
36 /* Return the offset of the register in the context buffer. */
37 int register_offset (struct gdbarch
*arch
, int regnum
);
41 riscv_ravenscar_ops::register_offset (struct gdbarch
*arch
, int regnum
)
44 if (regnum
== RISCV_RA_REGNUM
|| regnum
== RISCV_PC_REGNUM
)
46 else if (regnum
== RISCV_SP_REGNUM
)
48 else if (regnum
== RISCV_ZERO_REGNUM
+ 8) /* S0 */
50 else if (regnum
== RISCV_ZERO_REGNUM
+ 9) /* S1 */
52 else if (regnum
>= RISCV_ZERO_REGNUM
+ 19
53 && regnum
<= RISCV_ZERO_REGNUM
+ 27) /* S2..S11 */
54 offset
= regnum
- (RISCV_ZERO_REGNUM
+ 19) + 4;
55 else if (regnum
>= RISCV_FIRST_FP_REGNUM
56 && regnum
<= RISCV_FIRST_FP_REGNUM
+ 11)
57 offset
= regnum
- RISCV_FIRST_FP_REGNUM
+ 14; /* FS0..FS11 */
64 int size
= register_size (arch
, regnum
);
68 /* Supply register REGNUM, which has been saved on REGISTER_ADDR, to the
72 supply_register_at_address (struct regcache
*regcache
, int regnum
,
73 CORE_ADDR register_addr
)
75 struct gdbarch
*gdbarch
= regcache
->arch ();
76 int buf_size
= register_size (gdbarch
, regnum
);
79 buf
= (gdb_byte
*) alloca (buf_size
);
80 read_memory (register_addr
, buf
, buf_size
);
81 regcache
->raw_supply (regnum
, buf
);
85 riscv_ravenscar_ops::fetch_registers (struct regcache
*regcache
, int regnum
)
87 struct gdbarch
*gdbarch
= regcache
->arch ();
88 const int num_regs
= gdbarch_num_regs (gdbarch
);
90 CORE_ADDR current_address
;
91 CORE_ADDR thread_descriptor_address
;
93 /* The tid is the thread_id field, which is a pointer to the thread. */
94 thread_descriptor_address
= (CORE_ADDR
) inferior_ptid
.tid ();
97 for (current_regnum
= 0; current_regnum
< num_regs
; current_regnum
++)
99 int offset
= register_offset (gdbarch
, current_regnum
);
103 current_address
= thread_descriptor_address
+ offset
;
104 supply_register_at_address (regcache
, current_regnum
,
111 riscv_ravenscar_ops::store_registers (struct regcache
*regcache
, int regnum
)
113 struct gdbarch
*gdbarch
= regcache
->arch ();
114 int buf_size
= register_size (gdbarch
, regnum
);
115 gdb_byte buf
[buf_size
];
116 CORE_ADDR register_address
;
118 int offset
= register_offset (gdbarch
, regnum
);
121 register_address
= inferior_ptid
.tid () + offset
;
123 regcache
->raw_collect (regnum
, buf
);
124 write_memory (register_address
,
130 /* The ravenscar_arch_ops vector for most RISC-V targets. */
132 static struct riscv_ravenscar_ops riscv_ravenscar_ops
;
134 /* Register riscv_ravenscar_ops in GDBARCH. */
137 register_riscv_ravenscar_ops (struct gdbarch
*gdbarch
)
139 set_gdbarch_ravenscar_ops (gdbarch
, &riscv_ravenscar_ops
);