gdb/v850-tdep.c

   1 /* Target-dependent code for the NEC V850 for GDB, the GNU debugger.
   2
   3    Copyright (C) 1996-2022 Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #include "defs.h"
  21 #include "frame.h"
  22 #include "frame-base.h"
  23 #include "trad-frame.h"
  24 #include "frame-unwind.h"
  25 #include "dwarf2/frame.h"
  26 #include "gdbtypes.h"
  27 #include "inferior.h"
  28 #include "gdbcore.h"
  29 #include "arch-utils.h"
  30 #include "regcache.h"
  31 #include "dis-asm.h"
  32 #include "osabi.h"
  33 #include "elf-bfd.h"
  34 #include "elf/v850.h"
  35 #include "gdbarch.h"
  36
  37 enum
  38   {
  39     /* General purpose registers.  */
  40     E_R0_REGNUM,
  41     E_R1_REGNUM,
  42     E_R2_REGNUM,
  43     E_R3_REGNUM, E_SP_REGNUM = E_R3_REGNUM,
  44     E_R4_REGNUM,
  45     E_R5_REGNUM,
  46     E_R6_REGNUM, E_ARG0_REGNUM = E_R6_REGNUM,
  47     E_R7_REGNUM,
  48     E_R8_REGNUM,
  49     E_R9_REGNUM, E_ARGLAST_REGNUM = E_R9_REGNUM,
  50     E_R10_REGNUM, E_V0_REGNUM = E_R10_REGNUM,
  51     E_R11_REGNUM, E_V1_REGNUM = E_R11_REGNUM,
  52     E_R12_REGNUM,
  53     E_R13_REGNUM,
  54     E_R14_REGNUM,
  55     E_R15_REGNUM,
  56     E_R16_REGNUM,
  57     E_R17_REGNUM,
  58     E_R18_REGNUM,
  59     E_R19_REGNUM,
  60     E_R20_REGNUM,
  61     E_R21_REGNUM,
  62     E_R22_REGNUM,
  63     E_R23_REGNUM,
  64     E_R24_REGNUM,
  65     E_R25_REGNUM,
  66     E_R26_REGNUM,
  67     E_R27_REGNUM,
  68     E_R28_REGNUM,
  69     E_R29_REGNUM, E_FP_REGNUM = E_R29_REGNUM,
  70     E_R30_REGNUM, E_EP_REGNUM = E_R30_REGNUM,
  71     E_R31_REGNUM, E_LP_REGNUM = E_R31_REGNUM,
  72
  73     /* System registers - main banks.  */
  74     E_R32_REGNUM, E_SR0_REGNUM = E_R32_REGNUM,
  75     E_R33_REGNUM,
  76     E_R34_REGNUM,
  77     E_R35_REGNUM,
  78     E_R36_REGNUM,
  79     E_R37_REGNUM, E_PS_REGNUM = E_R37_REGNUM,
  80     E_R38_REGNUM,
  81     E_R39_REGNUM,
  82     E_R40_REGNUM,
  83     E_R41_REGNUM,
  84     E_R42_REGNUM,
  85     E_R43_REGNUM,
  86     E_R44_REGNUM,
  87     E_R45_REGNUM,
  88     E_R46_REGNUM,
  89     E_R47_REGNUM,
  90     E_R48_REGNUM,
  91     E_R49_REGNUM,
  92     E_R50_REGNUM,
  93     E_R51_REGNUM,
  94     E_R52_REGNUM, E_CTBP_REGNUM = E_R52_REGNUM,
  95     E_R53_REGNUM,
  96     E_R54_REGNUM,
  97     E_R55_REGNUM,
  98     E_R56_REGNUM,
  99     E_R57_REGNUM,
 100     E_R58_REGNUM,
 101     E_R59_REGNUM,
 102     E_R60_REGNUM,
 103     E_R61_REGNUM,
 104     E_R62_REGNUM,
 105     E_R63_REGNUM,
 106
 107     /* PC.  */
 108     E_R64_REGNUM, E_PC_REGNUM = E_R64_REGNUM,
 109     E_R65_REGNUM,
 110     E_NUM_OF_V850_REGS,
 111     E_NUM_OF_V850E_REGS = E_NUM_OF_V850_REGS,
 112
 113     /* System registers - MPV (PROT00) bank.  */
 114     E_R66_REGNUM = E_NUM_OF_V850_REGS,
 115     E_R67_REGNUM,
 116     E_R68_REGNUM,
 117     E_R69_REGNUM,
 118     E_R70_REGNUM,
 119     E_R71_REGNUM,
 120     E_R72_REGNUM,
 121     E_R73_REGNUM,
 122     E_R74_REGNUM,
 123     E_R75_REGNUM,
 124     E_R76_REGNUM,
 125     E_R77_REGNUM,
 126     E_R78_REGNUM,
 127     E_R79_REGNUM,
 128     E_R80_REGNUM,
 129     E_R81_REGNUM,
 130     E_R82_REGNUM,
 131     E_R83_REGNUM,
 132     E_R84_REGNUM,
 133     E_R85_REGNUM,
 134     E_R86_REGNUM,
 135     E_R87_REGNUM,
 136     E_R88_REGNUM,
 137     E_R89_REGNUM,
 138     E_R90_REGNUM,
 139     E_R91_REGNUM,
 140     E_R92_REGNUM,
 141     E_R93_REGNUM,
 142
 143     /* System registers - MPU (PROT01) bank.  */
 144     E_R94_REGNUM,
 145     E_R95_REGNUM,
 146     E_R96_REGNUM,
 147     E_R97_REGNUM,
 148     E_R98_REGNUM,
 149     E_R99_REGNUM,
 150     E_R100_REGNUM,
 151     E_R101_REGNUM,
 152     E_R102_REGNUM,
 153     E_R103_REGNUM,
 154     E_R104_REGNUM,
 155     E_R105_REGNUM,
 156     E_R106_REGNUM,
 157     E_R107_REGNUM,
 158     E_R108_REGNUM,
 159     E_R109_REGNUM,
 160     E_R110_REGNUM,
 161     E_R111_REGNUM,
 162     E_R112_REGNUM,
 163     E_R113_REGNUM,
 164     E_R114_REGNUM,
 165     E_R115_REGNUM,
 166     E_R116_REGNUM,
 167     E_R117_REGNUM,
 168     E_R118_REGNUM,
 169     E_R119_REGNUM,
 170     E_R120_REGNUM,
 171     E_R121_REGNUM,
 172
 173     /* FPU system registers.  */
 174     E_R122_REGNUM,
 175     E_R123_REGNUM,
 176     E_R124_REGNUM,
 177     E_R125_REGNUM,
 178     E_R126_REGNUM,
 179     E_R127_REGNUM,
 180     E_R128_REGNUM, E_FPSR_REGNUM = E_R128_REGNUM,
 181     E_R129_REGNUM, E_FPEPC_REGNUM = E_R129_REGNUM,
 182     E_R130_REGNUM, E_FPST_REGNUM = E_R130_REGNUM,
 183     E_R131_REGNUM, E_FPCC_REGNUM = E_R131_REGNUM,
 184     E_R132_REGNUM, E_FPCFG_REGNUM = E_R132_REGNUM,
 185     E_R133_REGNUM,
 186     E_R134_REGNUM,
 187     E_R135_REGNUM,
 188     E_R136_REGNUM,
 189     E_R137_REGNUM,
 190     E_R138_REGNUM,
 191     E_R139_REGNUM,
 192     E_R140_REGNUM,
 193     E_R141_REGNUM,
 194     E_R142_REGNUM,
 195     E_R143_REGNUM,
 196     E_R144_REGNUM,
 197     E_R145_REGNUM,
 198     E_R146_REGNUM,
 199     E_R147_REGNUM,
 200     E_R148_REGNUM,
 201     E_R149_REGNUM,
 202     E_NUM_OF_V850E2_REGS,
 203
 204     /* v850e3v5 system registers, selID 1 thru 7.  */
 205     E_SELID_1_R0_REGNUM = E_NUM_OF_V850E2_REGS,
 206     E_SELID_1_R31_REGNUM = E_SELID_1_R0_REGNUM + 31,
 207
 208     E_SELID_2_R0_REGNUM,
 209     E_SELID_2_R31_REGNUM = E_SELID_2_R0_REGNUM + 31,
 210
 211     E_SELID_3_R0_REGNUM,
 212     E_SELID_3_R31_REGNUM = E_SELID_3_R0_REGNUM + 31,
 213
 214     E_SELID_4_R0_REGNUM,
 215     E_SELID_4_R31_REGNUM = E_SELID_4_R0_REGNUM + 31,
 216
 217     E_SELID_5_R0_REGNUM,
 218     E_SELID_5_R31_REGNUM = E_SELID_5_R0_REGNUM + 31,
 219
 220     E_SELID_6_R0_REGNUM,
 221     E_SELID_6_R31_REGNUM = E_SELID_6_R0_REGNUM + 31,
 222
 223     E_SELID_7_R0_REGNUM,
 224     E_SELID_7_R31_REGNUM = E_SELID_7_R0_REGNUM + 31,
 225
 226     /* v850e3v5 vector registers.  */
 227     E_VR0_REGNUM,
 228     E_VR31_REGNUM = E_VR0_REGNUM + 31,
 229
 230     E_NUM_OF_V850E3V5_REGS,
 231
 232     /* Total number of possible registers.  */
 233     E_NUM_REGS = E_NUM_OF_V850E3V5_REGS
 234   };
 235
 236 enum
 237 {
 238   v850_reg_size = 4
 239 };
 240
 241 /* Size of return datatype which fits into all return registers.  */
 242 enum
 243 {
 244   E_MAX_RETTYPE_SIZE_IN_REGS = 2 * v850_reg_size
 245 };
 246
 247 /* When v850 support was added to GCC in the late nineties, the intention
 248    was to follow the Green Hills ABI for v850.  In fact, the authors of
 249    that support at the time thought that they were doing so.  As far as
 250    I can tell, the calling conventions are correct, but the return value
 251    conventions were not quite right.  Over time, the return value code
 252    in this file was modified to mostly reflect what GCC was actually
 253    doing instead of to actually follow the Green Hills ABI as it did
 254    when the code was first written.
 255
 256    Renesas defined the RH850 ABI which they use in their compiler.  It
 257    is similar to the original Green Hills ABI with some minor
 258    differences.  */
 259
 260 enum v850_abi
 261 {
 262   V850_ABI_GCC,
 263   V850_ABI_RH850
 264 };
 265
 266 /* Architecture specific data.  */
 267
 268 struct v850_gdbarch_tdep : gdbarch_tdep
 269 {
 270   /* Fields from the ELF header.  */
 271   int e_flags = 0;
 272   int e_machine = 0;
 273
 274   /* Which ABI are we using?  */
 275   enum v850_abi abi {};
 276   int eight_byte_align = 0;
 277 };
 278
 279 struct v850_frame_cache
 280 {
 281   /* Base address.  */
 282   CORE_ADDR base;
 283   LONGEST sp_offset;
 284   CORE_ADDR pc;
 285
 286   /* Flag showing that a frame has been created in the prologue code.  */
 287   int uses_fp;
 288
 289   /* Saved registers.  */
 290   trad_frame_saved_reg *saved_regs;
 291 };
 292
 293 /* Info gleaned from scanning a function's prologue.  */
 294 struct pifsr            /* Info about one saved register.  */
 295 {
 296   int offset;           /* Offset from sp or fp.  */
 297   int cur_frameoffset;  /* Current frameoffset.  */
 298   int reg;              /* Saved register number.  */
 299 };
 300
 301 static const char *
 302 v850_register_name (struct gdbarch *gdbarch, int regnum)
 303 {
 304   static const char *v850_reg_names[] =
 305   { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 306     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 307     "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
 308     "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
 309     "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7",
 310     "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
 311     "sr16", "sr17", "sr18", "sr19", "sr20", "sr21", "sr22", "sr23",
 312     "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31",
 313     "pc", "fp"
 314   };
 315   if (regnum < 0 || regnum > E_NUM_OF_V850_REGS)
 316     return NULL;
 317   return v850_reg_names[regnum];
 318 }
 319
 320 static const char *
 321 v850e_register_name (struct gdbarch *gdbarch, int regnum)
 322 {
 323   static const char *v850e_reg_names[] =
 324   {
 325     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 326     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 327     "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
 328     "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
 329     "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7",
 330     "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
 331     "ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "sr21", "sr22", "sr23",
 332     "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31",
 333     "pc", "fp"
 334   };
 335   if (regnum < 0 || regnum > E_NUM_OF_V850E_REGS)
 336     return NULL;
 337   return v850e_reg_names[regnum];
 338 }
 339
 340 static const char *
 341 v850e2_register_name (struct gdbarch *gdbarch, int regnum)
 342 {
 343   static const char *v850e2_reg_names[] =
 344   {
 345     /* General purpose registers.  */
 346     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 347     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 348     "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
 349     "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
 350
 351     /* System registers - main banks.  */
 352     "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "pid", "cfg",
 353     "", "", "", "sccfg", "scbp", "eiic", "feic", "dbic",
 354     "ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "dir", "", "",
 355     "", "", "", "", "eiwr", "fewr", "dbwr", "bsel",
 356
 357
 358     /* PC.  */
 359     "pc", "",
 360
 361     /* System registers - MPV (PROT00) bank.  */
 362     "vsecr", "vstid", "vsadr", "", "vmecr", "vmtid", "vmadr", "",
 363     "vpecr", "vptid", "vpadr", "", "", "", "", "",
 364     "", "", "", "", "", "", "", "",
 365     "mca", "mcs", "mcc", "mcr",
 366
 367     /* System registers - MPU (PROT01) bank.  */
 368     "mpm", "mpc", "tid", "", "", "", "ipa0l", "ipa0u",
 369     "ipa1l", "ipa1u", "ipa2l", "ipa2u", "ipa3l", "ipa3u", "ipa4l", "ipa4u",
 370     "dpa0l", "dpa0u", "dpa1l", "dpa1u", "dpa2l", "dpa2u", "dpa3l", "dpa3u",
 371     "dpa4l", "dpa4u", "dpa5l", "dpa5u",
 372
 373     /* FPU system registers.  */
 374     "", "", "", "", "", "", "fpsr", "fpepc",
 375     "fpst", "fpcc", "fpcfg", "fpec", "", "", "", "",
 376     "", "", "", "", "", "", "", "",
 377     "", "", "", "fpspc"
 378   };
 379   if (regnum < 0 || regnum >= E_NUM_OF_V850E2_REGS)
 380     return NULL;
 381   return v850e2_reg_names[regnum];
 382 }
 383
 384 /* Implement the "register_name" gdbarch method for v850e3v5.  */
 385
 386 static const char *
 387 v850e3v5_register_name (struct gdbarch *gdbarch, int regnum)
 388 {
 389   static const char *v850e3v5_reg_names[] =
 390   {
 391     /* General purpose registers.  */
 392     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 393     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 394     "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
 395     "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
 396
 397     /* selID 0, not including FPU registers.  The FPU registers are
 398        listed later on.  */
 399     "eipc", "eipsw", "fepc", "fepsw",
 400     "", "psw", "" /* fpsr */, "" /* fpepc */,
 401     "" /* fpst */, "" /* fpcc */, "" /* fpcfg */, "" /* fpec */,
 402     "sesr", "eiic", "feic", "",
 403     "ctpc", "ctpsw", "", "", "ctbp", "", "", "",
 404     "", "", "", "", "eiwr", "fewr", "", "bsel",
 405
 406
 407     /* PC.  */
 408     "pc", "",
 409
 410     /* v850e2 MPV bank.  */
 411     "", "", "", "", "", "", "", "",
 412     "", "", "", "", "", "", "", "",
 413     "", "", "", "", "", "", "", "",
 414     "", "", "", "",
 415
 416     /* Skip v850e2 MPU bank.  It's tempting to reuse these, but we need
 417        32 entries for this bank.  */
 418     "", "", "", "", "", "", "", "",
 419     "", "", "", "", "", "", "", "",
 420     "", "", "", "", "", "", "", "",
 421     "", "", "", "",
 422
 423     /* FPU system registers.  These are actually in selID 0, but
 424        are placed here to preserve register numbering compatibility
 425        with previous architectures.  */
 426     "", "", "", "", "", "", "fpsr", "fpepc",
 427     "fpst", "fpcc", "fpcfg", "fpec", "", "", "", "",
 428     "", "", "", "", "", "", "", "",
 429     "", "", "", "",
 430
 431     /* selID 1.  */
 432     "mcfg0", "mcfg1", "rbase", "ebase", "intbp", "mctl", "pid", "fpipr",
 433     "", "", "tcsel", "sccfg", "scbp", "hvccfg", "hvcbp", "vsel",
 434     "vmprt0", "vmprt1", "vmprt2", "", "", "", "", "vmscctl",
 435     "vmsctbl0", "vmsctbl1", "vmsctbl2", "vmsctbl3", "", "", "", "",
 436
 437     /* selID 2.  */
 438     "htcfg0", "", "", "", "", "htctl", "mea", "asid",
 439     "mei", "ispr", "pmr", "icsr", "intcfg", "", "", "",
 440     "tlbsch", "", "", "", "", "", "", "htscctl",
 441     "htsctbl0", "htsctbl1", "htsctbl2", "htsctbl3",
 442     "htsctbl4", "htsctbl5", "htsctbl6", "htsctbl7",
 443
 444     /* selID 3.  */
 445     "", "", "", "", "", "", "", "",
 446     "", "", "", "", "", "", "", "",
 447     "", "", "", "", "", "", "", "",
 448     "", "", "", "", "", "", "", "",
 449
 450     /* selID 4.  */
 451     "tlbidx", "", "", "", "telo0", "telo1", "tehi0", "tehi1",
 452     "", "", "tlbcfg", "", "bwerrl", "bwerrh", "brerrl", "brerrh",
 453     "ictagl", "ictagh", "icdatl", "icdath",
 454     "dctagl", "dctagh", "dcdatl", "dcdath",
 455     "icctrl", "dcctrl", "iccfg", "dccfg", "icerr", "dcerr", "", "",
 456
 457     /* selID 5.  */
 458     "mpm", "mprc", "", "", "mpbrgn", "mptrgn", "", "",
 459     "mca", "mcs", "mcc", "mcr", "", "", "", "",
 460     "", "", "", "", "mpprt0", "mpprt1", "mpprt2", "",
 461     "", "", "", "", "", "", "", "",
 462
 463     /* selID 6.  */
 464     "mpla0", "mpua0", "mpat0", "", "mpla1", "mpua1", "mpat1", "",
 465     "mpla2", "mpua2", "mpat2", "", "mpla3", "mpua3", "mpat3", "",
 466     "mpla4", "mpua4", "mpat4", "", "mpla5", "mpua5", "mpat5", "",
 467     "mpla6", "mpua6", "mpat6", "", "mpla7", "mpua7", "mpat7", "",
 468
 469     /* selID 7.  */
 470     "mpla8", "mpua8", "mpat8", "", "mpla9", "mpua9", "mpat9", "",
 471     "mpla10", "mpua10", "mpat10", "", "mpla11", "mpua11", "mpat11", "",
 472     "mpla12", "mpua12", "mpat12", "", "mpla13", "mpua13", "mpat13", "",
 473     "mpla14", "mpua14", "mpat14", "", "mpla15", "mpua15", "mpat15", "",
 474
 475     /* Vector Registers */
 476     "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
 477     "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
 478     "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
 479     "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31",
 480   };
 481
 482   if (regnum < 0 || regnum >= E_NUM_OF_V850E3V5_REGS)
 483     return NULL;
 484   return v850e3v5_reg_names[regnum];
 485 }
 486
 487 /* Returns the default type for register N.  */
 488
 489 static struct type *
 490 v850_register_type (struct gdbarch *gdbarch, int regnum)
 491 {
 492   if (regnum == E_PC_REGNUM)
 493     return builtin_type (gdbarch)->builtin_func_ptr;
 494   else if (E_VR0_REGNUM <= regnum && regnum <= E_VR31_REGNUM)
 495     return builtin_type (gdbarch)->builtin_uint64;
 496   return builtin_type (gdbarch)->builtin_int32;
 497 }
 498
 499 static int
 500 v850_type_is_scalar (struct type *t)
 501 {
 502   return (t->code () != TYPE_CODE_STRUCT
 503           && t->code () != TYPE_CODE_UNION
 504           && t->code () != TYPE_CODE_ARRAY);
 505 }
 506
 507 /* Should call_function allocate stack space for a struct return?  */
 508
 509 static int
 510 v850_use_struct_convention (struct gdbarch *gdbarch, struct type *type)
 511 {
 512   int i;
 513   struct type *fld_type, *tgt_type;
 514   v850_gdbarch_tdep *tdep = (v850_gdbarch_tdep *) gdbarch_tdep (gdbarch);
 515
 516   if (tdep->abi == V850_ABI_RH850)
 517     {
 518       if (v850_type_is_scalar (type) && TYPE_LENGTH(type) <= 8)
 519         return 0;
 520
 521       /* Structs are never returned in registers for this ABI.  */
 522       return 1;
 523     }
 524   /* 1. The value is greater than 8 bytes -> returned by copying.  */
 525   if (TYPE_LENGTH (type) > 8)
 526     return 1;
 527
 528   /* 2. The value is a single basic type -> returned in register.  */
 529   if (v850_type_is_scalar (type))
 530     return 0;
 531
 532   /* The value is a structure or union with a single element and that
 533      element is either a single basic type or an array of a single basic
 534      type whose size is greater than or equal to 4 -> returned in register.  */
 535   if ((type->code () == TYPE_CODE_STRUCT
 536        || type->code () == TYPE_CODE_UNION)
 537        && type->num_fields () == 1)
 538     {
 539       fld_type = type->field (0).type ();
 540       if (v850_type_is_scalar (fld_type) && TYPE_LENGTH (fld_type) >= 4)
 541         return 0;
 542
 543       if (fld_type->code () == TYPE_CODE_ARRAY)
 544         {
 545           tgt_type = TYPE_TARGET_TYPE (fld_type);
 546           if (v850_type_is_scalar (tgt_type) && TYPE_LENGTH (tgt_type) >= 4)
 547             return 0;
 548         }
 549     }
 550
 551   /* The value is a structure whose first element is an integer or a float,
 552      and which contains no arrays of more than two elements -> returned in
 553      register.  */
 554   if (type->code () == TYPE_CODE_STRUCT
 555       && v850_type_is_scalar (type->field (0).type ())
 556       && TYPE_LENGTH (type->field (0).type ()) == 4)
 557     {
 558       for (i = 1; i < type->num_fields (); ++i)
 559         {
 560           fld_type = type->field (0).type ();
 561           if (fld_type->code () == TYPE_CODE_ARRAY)
 562             {
 563               tgt_type = TYPE_TARGET_TYPE (fld_type);
 564               if (TYPE_LENGTH (tgt_type) > 0
 565                   && TYPE_LENGTH (fld_type) / TYPE_LENGTH (tgt_type) > 2)
 566                 return 1;
 567             }
 568         }
 569       return 0;
 570     }
 571
 572   /* The value is a union which contains at least one field which
 573      would be returned in registers according to these rules ->
 574      returned in register.  */
 575   if (type->code () == TYPE_CODE_UNION)
 576     {
 577       for (i = 0; i < type->num_fields (); ++i)
 578         {
 579           fld_type = type->field (0).type ();
 580           if (!v850_use_struct_convention (gdbarch, fld_type))
 581             return 0;
 582         }
 583     }
 584
 585   return 1;
 586 }
 587
 588 /* Structure for mapping bits in register lists to register numbers.  */
 589
 590 struct reg_list
 591 {
 592   long mask;
 593   int regno;
 594 };
 595
 596 /* Helper function for v850_scan_prologue to handle prepare instruction.  */
 597
 598 static void
 599 v850_handle_prepare (int insn, int insn2, CORE_ADDR * current_pc_ptr,
 600                      struct v850_frame_cache *pi, struct pifsr **pifsr_ptr)
 601 {
 602   CORE_ADDR current_pc = *current_pc_ptr;
 603   struct pifsr *pifsr = *pifsr_ptr;
 604   long next = insn2 & 0xffff;
 605   long list12 = ((insn & 1) << 16) + (next & 0xffe0);
 606   long offset = (insn & 0x3e) << 1;
 607   static struct reg_list reg_table[] =
 608   {
 609     {0x00800, 20},              /* r20 */
 610     {0x00400, 21},              /* r21 */
 611     {0x00200, 22},              /* r22 */
 612     {0x00100, 23},              /* r23 */
 613     {0x08000, 24},              /* r24 */
 614     {0x04000, 25},              /* r25 */
 615     {0x02000, 26},              /* r26 */
 616     {0x01000, 27},              /* r27 */
 617     {0x00080, 28},              /* r28 */
 618     {0x00040, 29},              /* r29 */
 619     {0x10000, 30},              /* ep */
 620     {0x00020, 31},              /* lp */
 621     {0, 0}                      /* end of table */
 622   };
 623   int i;
 624
 625   if ((next & 0x1f) == 0x0b)            /* skip imm16 argument */
 626     current_pc += 2;
 627   else if ((next & 0x1f) == 0x13)       /* skip imm16 argument */
 628     current_pc += 2;
 629   else if ((next & 0x1f) == 0x1b)       /* skip imm32 argument */
 630     current_pc += 4;
 631
 632   /* Calculate the total size of the saved registers, and add it to the
 633      immediate value used to adjust SP.  */
 634   for (i = 0; reg_table[i].mask != 0; i++)
 635     if (list12 & reg_table[i].mask)
 636       offset += v850_reg_size;
 637   pi->sp_offset -= offset;
 638
 639   /* Calculate the offsets of the registers relative to the value the SP
 640      will have after the registers have been pushed and the imm5 value has
 641      been subtracted from it.  */
 642   if (pifsr)
 643     {
 644       for (i = 0; reg_table[i].mask != 0; i++)
 645         {
 646           if (list12 & reg_table[i].mask)
 647             {
 648               int reg = reg_table[i].regno;
 649               offset -= v850_reg_size;
 650               pifsr->reg = reg;
 651               pifsr->offset = offset;
 652               pifsr->cur_frameoffset = pi->sp_offset;
 653               pifsr++;
 654             }
 655         }
 656     }
 657
 658   /* Set result parameters.  */
 659   *current_pc_ptr = current_pc;
 660   *pifsr_ptr = pifsr;
 661 }
 662
 663
 664 /* Helper function for v850_scan_prologue to handle pushm/pushl instructions.
 665    The SR bit of the register list is not supported.  gcc does not generate
 666    this bit.  */
 667
 668 static void
 669 v850_handle_pushm (int insn, int insn2, struct v850_frame_cache *pi,
 670                    struct pifsr **pifsr_ptr)
 671 {
 672   struct pifsr *pifsr = *pifsr_ptr;
 673   long list12 = ((insn & 0x0f) << 16) + (insn2 & 0xfff0);
 674   long offset = 0;
 675   static struct reg_list pushml_reg_table[] =
 676   {
 677     {0x80000, E_PS_REGNUM},     /* PSW */
 678     {0x40000, 1},               /* r1 */
 679     {0x20000, 2},               /* r2 */
 680     {0x10000, 3},               /* r3 */
 681     {0x00800, 4},               /* r4 */
 682     {0x00400, 5},               /* r5 */
 683     {0x00200, 6},               /* r6 */
 684     {0x00100, 7},               /* r7 */
 685     {0x08000, 8},               /* r8 */
 686     {0x04000, 9},               /* r9 */
 687     {0x02000, 10},              /* r10 */
 688     {0x01000, 11},              /* r11 */
 689     {0x00080, 12},              /* r12 */
 690     {0x00040, 13},              /* r13 */
 691     {0x00020, 14},              /* r14 */
 692     {0x00010, 15},              /* r15 */
 693     {0, 0}                      /* end of table */
 694   };
 695   static struct reg_list pushmh_reg_table[] =
 696   {
 697     {0x80000, 16},              /* r16 */
 698     {0x40000, 17},              /* r17 */
 699     {0x20000, 18},              /* r18 */
 700     {0x10000, 19},              /* r19 */
 701     {0x00800, 20},              /* r20 */
 702     {0x00400, 21},              /* r21 */
 703     {0x00200, 22},              /* r22 */
 704     {0x00100, 23},              /* r23 */
 705     {0x08000, 24},              /* r24 */
 706     {0x04000, 25},              /* r25 */
 707     {0x02000, 26},              /* r26 */
 708     {0x01000, 27},              /* r27 */
 709     {0x00080, 28},              /* r28 */
 710     {0x00040, 29},              /* r29 */
 711     {0x00010, 30},              /* r30 */
 712     {0x00020, 31},              /* r31 */
 713     {0, 0}                      /* end of table */
 714   };
 715   struct reg_list *reg_table;
 716   int i;
 717
 718   /* Is this a pushml or a pushmh?  */
 719   if ((insn2 & 7) == 1)
 720     reg_table = pushml_reg_table;
 721   else
 722     reg_table = pushmh_reg_table;
 723
 724   /* Calculate the total size of the saved registers, and add it to the
 725      immediate value used to adjust SP.  */
 726   for (i = 0; reg_table[i].mask != 0; i++)
 727     if (list12 & reg_table[i].mask)
 728       offset += v850_reg_size;
 729   pi->sp_offset -= offset;
 730
 731   /* Calculate the offsets of the registers relative to the value the SP
 732      will have after the registers have been pushed and the imm5 value is
 733      subtracted from it.  */
 734   if (pifsr)
 735     {
 736       for (i = 0; reg_table[i].mask != 0; i++)
 737         {
 738           if (list12 & reg_table[i].mask)
 739             {
 740               int reg = reg_table[i].regno;
 741               offset -= v850_reg_size;
 742               pifsr->reg = reg;
 743               pifsr->offset = offset;
 744               pifsr->cur_frameoffset = pi->sp_offset;
 745               pifsr++;
 746             }
 747         }
 748     }
 749
 750   /* Set result parameters.  */
 751   *pifsr_ptr = pifsr;
 752 }
 753
 754 /* Helper function to evaluate if register is one of the "save" registers.
 755    This allows to simplify conditionals in v850_analyze_prologue a lot.  */
 756
 757 static int
 758 v850_is_save_register (int reg)
 759 {
 760  /* The caller-save registers are R2, R20 - R29 and R31.  All other
 761     registers are either special purpose (PC, SP), argument registers,
 762     or just considered free for use in the caller.  */
 763  return reg == E_R2_REGNUM
 764         || (reg >= E_R20_REGNUM && reg <= E_R29_REGNUM)
 765         || reg == E_R31_REGNUM;
 766 }
 767
 768 /* Scan the prologue of the function that contains PC, and record what
 769    we find in PI.  Returns the pc after the prologue.  Note that the
 770    addresses saved in frame->saved_regs are just frame relative (negative
 771    offsets from the frame pointer).  This is because we don't know the
 772    actual value of the frame pointer yet.  In some circumstances, the
 773    frame pointer can't be determined till after we have scanned the
 774    prologue.  */
 775
 776 static CORE_ADDR
 777 v850_analyze_prologue (struct gdbarch *gdbarch,
 778                        CORE_ADDR func_addr, CORE_ADDR pc,
 779                        struct v850_frame_cache *pi, ULONGEST ctbp)
 780 {
 781   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 782   CORE_ADDR prologue_end, current_pc;
 783   struct pifsr pifsrs[E_NUM_REGS + 1];
 784   struct pifsr *pifsr, *pifsr_tmp;
 785   int ep_used;
 786   int reg;
 787   CORE_ADDR save_pc, save_end;
 788   int regsave_func_p;
 789   int r12_tmp;
 790
 791   memset (&pifsrs, 0, sizeof pifsrs);
 792   pifsr = &pifsrs[0];
 793
 794   prologue_end = pc;
 795
 796   /* Now, search the prologue looking for instructions that setup fp, save
 797      rp, adjust sp and such.  We also record the frame offset of any saved
 798      registers.  */
 799
 800   pi->sp_offset = 0;
 801   pi->uses_fp = 0;
 802   ep_used = 0;
 803   regsave_func_p = 0;
 804   save_pc = 0;
 805   save_end = 0;
 806   r12_tmp = 0;
 807
 808   for (current_pc = func_addr; current_pc < prologue_end;)
 809     {
 810       int insn;
 811       int insn2 = -1; /* dummy value */
 812
 813       insn = read_memory_integer (current_pc, 2, byte_order);
 814       current_pc += 2;
 815       if ((insn & 0x0780) >= 0x0600)    /* Four byte instruction?  */
 816         {
 817           insn2 = read_memory_integer (current_pc, 2, byte_order);
 818           current_pc += 2;
 819         }
 820
 821       if ((insn & 0xffc0) == ((10 << 11) | 0x0780) && !regsave_func_p)
 822         {                       /* jarl <func>,10 */
 823           long low_disp = insn2 & ~(long) 1;
 824           long disp = (((((insn & 0x3f) << 16) + low_disp)
 825                         & ~(long) 1) ^ 0x00200000) - 0x00200000;
 826
 827           save_pc = current_pc;
 828           save_end = prologue_end;
 829           regsave_func_p = 1;
 830           current_pc += disp - 4;
 831           prologue_end = (current_pc
 832                           + (2 * 3)     /* moves to/from ep */
 833                           + 4           /* addi <const>,sp,sp */
 834                           + 2           /* jmp [r10] */
 835                           + (2 * 12)    /* sst.w to save r2, r20-r29, r31 */
 836                           + 20);        /* slop area */
 837         }
 838       else if ((insn & 0xffc0) == 0x0200 && !regsave_func_p)
 839         {                       /* callt <imm6> */
 840           long adr = ctbp + ((insn & 0x3f) << 1);
 841
 842           save_pc = current_pc;
 843           save_end = prologue_end;
 844           regsave_func_p = 1;
 845           current_pc = ctbp + (read_memory_unsigned_integer (adr, 2, byte_order)
 846                                & 0xffff);
 847           prologue_end = (current_pc
 848                           + (2 * 3)     /* prepare list2,imm5,sp/imm */
 849                           + 4           /* ctret */
 850                           + 20);        /* slop area */
 851           continue;
 852         }
 853       else if ((insn & 0xffc0) == 0x0780)       /* prepare list2,imm5 */
 854         {
 855           v850_handle_prepare (insn, insn2, &current_pc, pi, &pifsr);
 856           continue;
 857         }
 858       else if (insn == 0x07e0 && regsave_func_p && insn2 == 0x0144)
 859         {                       /* ctret after processing register save.  */
 860           current_pc = save_pc;
 861           prologue_end = save_end;
 862           regsave_func_p = 0;
 863           continue;
 864         }
 865       else if ((insn & 0xfff0) == 0x07e0 && (insn2 & 5) == 1)
 866         {                       /* pushml, pushmh */
 867           v850_handle_pushm (insn, insn2, pi, &pifsr);
 868           continue;
 869         }
 870       else if ((insn & 0xffe0) == 0x0060 && regsave_func_p)
 871         {                       /* jmp after processing register save.  */
 872           current_pc = save_pc;
 873           prologue_end = save_end;
 874           regsave_func_p = 0;
 875           continue;
 876         }
 877       else if ((insn & 0x07c0) == 0x0780        /* jarl or jr */
 878                || (insn & 0xffe0) == 0x0060     /* jmp */
 879                || (insn & 0x0780) == 0x0580)    /* branch */
 880         {
 881           break;                /* Ran into end of prologue.  */
 882         }
 883
 884       else if ((insn & 0xffe0) == ((E_SP_REGNUM << 11) | 0x0240))
 885         /* add <imm>,sp */
 886         pi->sp_offset += ((insn & 0x1f) ^ 0x10) - 0x10;
 887       else if (insn == ((E_SP_REGNUM << 11) | 0x0600 | E_SP_REGNUM))
 888         /* addi <imm>,sp,sp */
 889         pi->sp_offset += insn2;
 890       else if (insn == ((E_FP_REGNUM << 11) | 0x0000 | E_SP_REGNUM))
 891         /* mov sp,fp */
 892         pi->uses_fp = 1;
 893       else if (insn == ((E_R12_REGNUM << 11) | 0x0640 | E_R0_REGNUM))
 894         /* movhi hi(const),r0,r12 */
 895         r12_tmp = insn2 << 16;
 896       else if (insn == ((E_R12_REGNUM << 11) | 0x0620 | E_R12_REGNUM))
 897         /* movea lo(const),r12,r12 */
 898         r12_tmp += insn2;
 899       else if (insn == ((E_SP_REGNUM << 11) | 0x01c0 | E_R12_REGNUM) && r12_tmp)
 900         /* add r12,sp */
 901         pi->sp_offset += r12_tmp;
 902       else if (insn == ((E_EP_REGNUM << 11) | 0x0000 | E_SP_REGNUM))
 903         /* mov sp,ep */
 904         ep_used = 1;
 905       else if (insn == ((E_EP_REGNUM << 11) | 0x0000 | E_R1_REGNUM))
 906         /* mov r1,ep */
 907         ep_used = 0;
 908       else if (((insn & 0x07ff) == (0x0760 | E_SP_REGNUM)
 909                 || (pi->uses_fp
 910                     && (insn & 0x07ff) == (0x0760 | E_FP_REGNUM)))
 911                && pifsr
 912                && v850_is_save_register (reg = (insn >> 11) & 0x1f))
 913         {
 914           /* st.w <reg>,<offset>[sp] or st.w <reg>,<offset>[fp] */
 915           pifsr->reg = reg;
 916           pifsr->offset = insn2 & ~1;
 917           pifsr->cur_frameoffset = pi->sp_offset;
 918           pifsr++;
 919         }
 920       else if (ep_used
 921                && ((insn & 0x0781) == 0x0501)
 922                && pifsr
 923                && v850_is_save_register (reg = (insn >> 11) & 0x1f))
 924         {
 925           /* sst.w <reg>,<offset>[ep] */
 926           pifsr->reg = reg;
 927           pifsr->offset = (insn & 0x007e) << 1;
 928           pifsr->cur_frameoffset = pi->sp_offset;
 929           pifsr++;
 930         }
 931     }
 932
 933   /* Fix up any offsets to the final offset.  If a frame pointer was created,
 934      use it instead of the stack pointer.  */
 935   for (pifsr_tmp = pifsrs; pifsr_tmp != pifsr; pifsr_tmp++)
 936     {
 937       pifsr_tmp->offset -= pi->sp_offset - pifsr_tmp->cur_frameoffset;
 938       pi->saved_regs[pifsr_tmp->reg].set_addr (pifsr_tmp->offset);
 939     }
 940
 941   return current_pc;
 942 }
 943
 944 /* Return the address of the first code past the prologue of the function.  */
 945
 946 static CORE_ADDR
 947 v850_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
 948 {
 949   CORE_ADDR func_addr, func_end;
 950
 951   /* See what the symbol table says.  */
 952
 953   if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
 954     {
 955       struct symtab_and_line sal;
 956
 957       sal = find_pc_line (func_addr, 0);
 958       if (sal.line != 0 && sal.end < func_end)
 959         return sal.end;
 960
 961       /* Either there's no line info, or the line after the prologue is after
 962          the end of the function.  In this case, there probably isn't a
 963          prologue.  */
 964       return pc;
 965     }
 966
 967   /* We can't find the start of this function, so there's nothing we
 968      can do.  */
 969   return pc;
 970 }
 971
 972 /* Return 1 if the data structure has any 8-byte fields that'll require
 973    the entire data structure to be aligned.  Otherwise, return 0.  */
 974
 975 static int
 976 v850_eight_byte_align_p (struct type *type)
 977 {
 978   type = check_typedef (type);
 979
 980   if (v850_type_is_scalar (type))
 981     return (TYPE_LENGTH (type) == 8);
 982   else
 983     {
 984       int i;
 985
 986       for (i = 0; i < type->num_fields (); i++)
 987         {
 988           if (v850_eight_byte_align_p (type->field (i).type ()))
 989             return 1;
 990         }
 991     }
 992   return 0;
 993 }
 994
 995 static CORE_ADDR
 996 v850_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
 997 {
 998   return sp & ~3;
 999 }
1000
1001 /* Setup arguments and LP for a call to the target.  First four args
1002    go in R6->R9, subsequent args go into sp + 16 -> sp + ...  Structs
1003    are passed by reference.  64 bit quantities (doubles and long longs)
1004    may be split between the regs and the stack.  When calling a function
1005    that returns a struct, a pointer to the struct is passed in as a secret
1006    first argument (always in R6).
1007
1008    Stack space for the args has NOT been allocated: that job is up to us.  */
1009
1010 static CORE_ADDR
1011 v850_push_dummy_call (struct gdbarch *gdbarch,
1012                       struct value *function,
1013                       struct regcache *regcache,
1014                       CORE_ADDR bp_addr,
1015                       int nargs,
1016                       struct value **args,
1017                       CORE_ADDR sp,
1018                       function_call_return_method return_method,
1019                       CORE_ADDR struct_addr)
1020 {
1021   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1022   int argreg;
1023   int argnum;
1024   int arg_space = 0;
1025   int stack_offset;
1026   v850_gdbarch_tdep *tdep = (v850_gdbarch_tdep *) gdbarch_tdep (gdbarch);
1027
1028   if (tdep->abi == V850_ABI_RH850)
1029     stack_offset = 0;
1030   else
1031     {
1032       /* The offset onto the stack at which we will start copying parameters
1033          (after the registers are used up) begins at 16 rather than at zero.
1034          That's how the ABI is defined, though there's no indication that these
1035          16 bytes are used for anything, not even for saving incoming
1036          argument registers.  */
1037       stack_offset = 16;
1038     }
1039
1040   /* Now make space on the stack for the args.  */
1041   for (argnum = 0; argnum < nargs; argnum++)
1042     arg_space += ((TYPE_LENGTH (value_type (args[argnum])) + 3) & ~3);
1043   sp -= arg_space + stack_offset;
1044
1045   argreg = E_ARG0_REGNUM;
1046   /* The struct_return pointer occupies the first parameter register.  */
1047   if (return_method == return_method_struct)
1048     regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
1049
1050   /* Now load as many as possible of the first arguments into
1051      registers, and push the rest onto the stack.  There are 16 bytes
1052      in four registers available.  Loop thru args from first to last.  */
1053   for (argnum = 0; argnum < nargs; argnum++)
1054     {
1055       int len;
1056       gdb_byte *val;
1057       gdb_byte valbuf[v850_reg_size];
1058
1059       if (!v850_type_is_scalar (value_type (*args))
1060           && tdep->abi == V850_ABI_GCC
1061           && TYPE_LENGTH (value_type (*args)) > E_MAX_RETTYPE_SIZE_IN_REGS)
1062         {
1063           store_unsigned_integer (valbuf, 4, byte_order,
1064                                   value_address (*args));
1065           len = 4;
1066           val = valbuf;
1067         }
1068       else
1069         {
1070           len = TYPE_LENGTH (value_type (*args));
1071           val = (gdb_byte *) value_contents (*args).data ();
1072         }
1073
1074       if (tdep->eight_byte_align
1075           && v850_eight_byte_align_p (value_type (*args)))
1076         {
1077           if (argreg <= E_ARGLAST_REGNUM && (argreg & 1))
1078             argreg++;
1079           else if (stack_offset & 0x4)
1080             stack_offset += 4;
1081         }
1082
1083       while (len > 0)
1084         if (argreg <= E_ARGLAST_REGNUM)
1085           {
1086             CORE_ADDR regval;
1087
1088             regval = extract_unsigned_integer (val, v850_reg_size, byte_order);
1089             regcache_cooked_write_unsigned (regcache, argreg, regval);
1090
1091             len -= v850_reg_size;
1092             val += v850_reg_size;
1093             argreg++;
1094           }
1095         else
1096           {
1097             write_memory (sp + stack_offset, val, 4);
1098
1099             len -= 4;
1100             val += 4;
1101             stack_offset += 4;
1102           }
1103       args++;
1104     }
1105
1106   /* Store return address.  */
1107   regcache_cooked_write_unsigned (regcache, E_LP_REGNUM, bp_addr);
1108
1109   /* Update stack pointer.  */
1110   regcache_cooked_write_unsigned (regcache, E_SP_REGNUM, sp);
1111
1112   return sp;
1113 }
1114
1115 static void
1116 v850_extract_return_value (struct type *type, struct regcache *regcache,
1117                            gdb_byte *valbuf)
1118 {
1119   struct gdbarch *gdbarch = regcache->arch ();
1120   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1121   int len = TYPE_LENGTH (type);
1122
1123   if (len <= v850_reg_size)
1124     {
1125       ULONGEST val;
1126
1127       regcache_cooked_read_unsigned (regcache, E_V0_REGNUM, &val);
1128       store_unsigned_integer (valbuf, len, byte_order, val);
1129     }
1130   else if (len <= 2 * v850_reg_size)
1131     {
1132       int i, regnum = E_V0_REGNUM;
1133       gdb_byte buf[v850_reg_size];
1134       for (i = 0; len > 0; i += 4, len -= 4)
1135         {
1136           regcache->raw_read (regnum++, buf);
1137           memcpy (valbuf + i, buf, len > 4 ? 4 : len);
1138         }
1139     }
1140 }
1141
1142 static void
1143 v850_store_return_value (struct type *type, struct regcache *regcache,
1144                          const gdb_byte *valbuf)
1145 {
1146   struct gdbarch *gdbarch = regcache->arch ();
1147   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1148   int len = TYPE_LENGTH (type);
1149
1150   if (len <= v850_reg_size)
1151       regcache_cooked_write_unsigned
1152         (regcache, E_V0_REGNUM,
1153          extract_unsigned_integer (valbuf, len, byte_order));
1154   else if (len <= 2 * v850_reg_size)
1155     {
1156       int i, regnum = E_V0_REGNUM;
1157       for (i = 0; i < len; i += 4)
1158         regcache->raw_write (regnum++, valbuf + i);
1159     }
1160 }
1161
1162 static enum return_value_convention
1163 v850_return_value (struct gdbarch *gdbarch, struct value *function,
1164                    struct type *type, struct regcache *regcache,
1165                    gdb_byte *readbuf, const gdb_byte *writebuf)
1166 {
1167   if (v850_use_struct_convention (gdbarch, type))
1168     return RETURN_VALUE_STRUCT_CONVENTION;
1169   if (writebuf)
1170     v850_store_return_value (type, regcache, writebuf);
1171   else if (readbuf)
1172     v850_extract_return_value (type, regcache, readbuf);
1173   return RETURN_VALUE_REGISTER_CONVENTION;
1174 }
1175
1176 /* Implement the breakpoint_kind_from_pc gdbarch method.  */
1177
1178 static int
1179 v850_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
1180 {
1181   return 2;
1182 }
1183
1184 /* Implement the sw_breakpoint_from_kind gdbarch method.  */
1185
1186 static const gdb_byte *
1187 v850_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
1188 {
1189   *size = kind;
1190
1191     switch (gdbarch_bfd_arch_info (gdbarch)->mach)
1192     {
1193     case bfd_mach_v850e2:
1194     case bfd_mach_v850e2v3:
1195     case bfd_mach_v850e3v5:
1196       {
1197         /* Implement software breakpoints by using the dbtrap instruction.
1198            Older architectures had no such instruction.  For those, an
1199            unconditional branch to self instruction is used.  */
1200
1201         static unsigned char dbtrap_breakpoint[] = { 0x40, 0xf8 };
1202
1203         return dbtrap_breakpoint;
1204       }
1205       break;
1206     default:
1207       {
1208         static unsigned char breakpoint[] = { 0x85, 0x05 };
1209
1210         return breakpoint;
1211       }
1212       break;
1213     }
1214 }
1215
1216 static struct v850_frame_cache *
1217 v850_alloc_frame_cache (struct frame_info *this_frame)
1218 {
1219   struct v850_frame_cache *cache;
1220
1221   cache = FRAME_OBSTACK_ZALLOC (struct v850_frame_cache);
1222   cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1223
1224   /* Base address.  */
1225   cache->base = 0;
1226   cache->sp_offset = 0;
1227   cache->pc = 0;
1228
1229   /* Frameless until proven otherwise.  */
1230   cache->uses_fp = 0;
1231
1232   return cache;
1233 }
1234
1235 static struct v850_frame_cache *
1236 v850_frame_cache (struct frame_info *this_frame, void **this_cache)
1237 {
1238   struct gdbarch *gdbarch = get_frame_arch (this_frame);
1239   struct v850_frame_cache *cache;
1240   CORE_ADDR current_pc;
1241   int i;
1242
1243   if (*this_cache)
1244     return (struct v850_frame_cache *) *this_cache;
1245
1246   cache = v850_alloc_frame_cache (this_frame);
1247   *this_cache = cache;
1248
1249   /* In principle, for normal frames, fp holds the frame pointer,
1250      which holds the base address for the current stack frame.
1251      However, for functions that don't need it, the frame pointer is
1252      optional.  For these "frameless" functions the frame pointer is
1253      actually the frame pointer of the calling frame.  */
1254   cache->base = get_frame_register_unsigned (this_frame, E_FP_REGNUM);
1255   if (cache->base == 0)
1256     return cache;
1257
1258   cache->pc = get_frame_func (this_frame);
1259   current_pc = get_frame_pc (this_frame);
1260   if (cache->pc != 0)
1261     {
1262       ULONGEST ctbp;
1263       ctbp = get_frame_register_unsigned (this_frame, E_CTBP_REGNUM);
1264       v850_analyze_prologue (gdbarch, cache->pc, current_pc, cache, ctbp);
1265     }
1266
1267   if (!cache->uses_fp)
1268     {
1269       /* We didn't find a valid frame, which means that CACHE->base
1270          currently holds the frame pointer for our calling frame.  If
1271          we're at the start of a function, or somewhere half-way its
1272          prologue, the function's frame probably hasn't been fully
1273          setup yet.  Try to reconstruct the base address for the stack
1274          frame by looking at the stack pointer.  For truly "frameless"
1275          functions this might work too.  */
1276       cache->base = get_frame_register_unsigned (this_frame, E_SP_REGNUM);
1277     }
1278
1279   /* Now that we have the base address for the stack frame we can
1280      calculate the value of sp in the calling frame.  */
1281   cache->saved_regs[E_SP_REGNUM].set_value (cache->base - cache->sp_offset);
1282
1283   /* Adjust all the saved registers such that they contain addresses
1284      instead of offsets.  */
1285   for (i = 0; i < gdbarch_num_regs (gdbarch); i++)
1286     if (cache->saved_regs[i].is_addr ())
1287       cache->saved_regs[i].set_addr (cache->saved_regs[i].addr ()
1288                                      + cache->base);
1289
1290   /* The call instruction moves the caller's PC in the callee's LP.
1291      Since this is an unwind, do the reverse.  Copy the location of LP
1292      into PC (the address / regnum) so that a request for PC will be
1293      converted into a request for the LP.  */
1294
1295   cache->saved_regs[E_PC_REGNUM] = cache->saved_regs[E_LP_REGNUM];
1296
1297   return cache;
1298 }
1299
1300
1301 static struct value *
1302 v850_frame_prev_register (struct frame_info *this_frame,
1303                           void **this_cache, int regnum)
1304 {
1305   struct v850_frame_cache *cache = v850_frame_cache (this_frame, this_cache);
1306
1307   gdb_assert (regnum >= 0);
1308
1309   return trad_frame_get_prev_register (this_frame, cache->saved_regs, regnum);
1310 }
1311
1312 static void
1313 v850_frame_this_id (struct frame_info *this_frame, void **this_cache,
1314                     struct frame_id *this_id)
1315 {
1316   struct v850_frame_cache *cache = v850_frame_cache (this_frame, this_cache);
1317
1318   /* This marks the outermost frame.  */
1319   if (cache->base == 0)
1320     return;
1321
1322   *this_id = frame_id_build (cache->saved_regs[E_SP_REGNUM].addr (), cache->pc);
1323 }
1324
1325 static const struct frame_unwind v850_frame_unwind = {
1326   "v850 prologue",
1327   NORMAL_FRAME,
1328   default_frame_unwind_stop_reason,
1329   v850_frame_this_id,
1330   v850_frame_prev_register,
1331   NULL,
1332   default_frame_sniffer
1333 };
1334
1335 static CORE_ADDR
1336 v850_frame_base_address (struct frame_info *this_frame, void **this_cache)
1337 {
1338   struct v850_frame_cache *cache = v850_frame_cache (this_frame, this_cache);
1339
1340   return cache->base;
1341 }
1342
1343 static const struct frame_base v850_frame_base = {
1344   &v850_frame_unwind,
1345   v850_frame_base_address,
1346   v850_frame_base_address,
1347   v850_frame_base_address
1348 };
1349
1350 static struct gdbarch *
1351 v850_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1352 {
1353   struct gdbarch *gdbarch;
1354   int e_flags, e_machine;
1355
1356   /* Extract the elf_flags if available.  */
1357   if (info.abfd != NULL
1358       && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
1359     {
1360       e_flags = elf_elfheader (info.abfd)->e_flags;
1361       e_machine = elf_elfheader (info.abfd)->e_machine;
1362     }
1363   else
1364     {
1365       e_flags = 0;
1366       e_machine = 0;
1367     }
1368
1369
1370   /* Try to find the architecture in the list of already defined
1371      architectures.  */
1372   for (arches = gdbarch_list_lookup_by_info (arches, &info);
1373        arches != NULL;
1374        arches = gdbarch_list_lookup_by_info (arches->next, &info))
1375     {
1376       v850_gdbarch_tdep *tdep
1377         = (v850_gdbarch_tdep *) gdbarch_tdep (arches->gdbarch);
1378
1379       if (tdep->e_flags != e_flags || tdep->e_machine != e_machine)
1380         continue;
1381
1382       return arches->gdbarch;
1383     }
1384
1385   v850_gdbarch_tdep *tdep = new v850_gdbarch_tdep;
1386   tdep->e_flags = e_flags;
1387   tdep->e_machine = e_machine;
1388
1389   switch (tdep->e_machine)
1390     {
1391     case EM_V800:
1392       tdep->abi = V850_ABI_RH850;
1393       break;
1394     default:
1395       tdep->abi = V850_ABI_GCC;
1396       break;
1397     }
1398
1399   tdep->eight_byte_align = (tdep->e_flags & EF_RH850_DATA_ALIGN8) ? 1 : 0;
1400   gdbarch = gdbarch_alloc (&info, tdep);
1401
1402   switch (info.bfd_arch_info->mach)
1403     {
1404     case bfd_mach_v850:
1405       set_gdbarch_register_name (gdbarch, v850_register_name);
1406       set_gdbarch_num_regs (gdbarch, E_NUM_OF_V850_REGS);
1407       break;
1408     case bfd_mach_v850e:
1409     case bfd_mach_v850e1:
1410       set_gdbarch_register_name (gdbarch, v850e_register_name);
1411       set_gdbarch_num_regs (gdbarch, E_NUM_OF_V850E_REGS);
1412       break;
1413     case bfd_mach_v850e2:
1414     case bfd_mach_v850e2v3:
1415       set_gdbarch_register_name (gdbarch, v850e2_register_name);
1416       set_gdbarch_num_regs (gdbarch, E_NUM_REGS);
1417       break;
1418     case bfd_mach_v850e3v5:
1419       set_gdbarch_register_name (gdbarch, v850e3v5_register_name);
1420       set_gdbarch_num_regs (gdbarch, E_NUM_OF_V850E3V5_REGS);
1421       break;
1422     }
1423
1424   set_gdbarch_num_pseudo_regs (gdbarch, 0);
1425   set_gdbarch_sp_regnum (gdbarch, E_SP_REGNUM);
1426   set_gdbarch_pc_regnum (gdbarch, E_PC_REGNUM);
1427   set_gdbarch_fp0_regnum (gdbarch, -1);
1428
1429   set_gdbarch_register_type (gdbarch, v850_register_type);
1430
1431   set_gdbarch_char_signed (gdbarch, 1);
1432   set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
1433   set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1434   set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1435   set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1436
1437   set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1438   set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1439   set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1440
1441   set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1442   set_gdbarch_addr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1443
1444   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1445
1446   set_gdbarch_breakpoint_kind_from_pc (gdbarch, v850_breakpoint_kind_from_pc);
1447   set_gdbarch_sw_breakpoint_from_kind (gdbarch, v850_sw_breakpoint_from_kind);
1448   set_gdbarch_return_value (gdbarch, v850_return_value);
1449   set_gdbarch_push_dummy_call (gdbarch, v850_push_dummy_call);
1450   set_gdbarch_skip_prologue (gdbarch, v850_skip_prologue);
1451
1452   set_gdbarch_frame_align (gdbarch, v850_frame_align);
1453   frame_base_set_default (gdbarch, &v850_frame_base);
1454
1455   /* Hook in ABI-specific overrides, if they have been registered.  */
1456   gdbarch_init_osabi (info, gdbarch);
1457
1458   dwarf2_append_unwinders (gdbarch);
1459   frame_unwind_append_unwinder (gdbarch, &v850_frame_unwind);
1460
1461   return gdbarch;
1462 }
1463
1464 void _initialize_v850_tdep ();
1465 void
1466 _initialize_v850_tdep ()
1467 {
1468   register_gdbarch_init (bfd_arch_v850, v850_gdbarch_init);
1469   register_gdbarch_init (bfd_arch_v850_rh850, v850_gdbarch_init);
1470 }