bfd/xtensa-modules.c

   1 /* Xtensa configuration-specific ISA information.
   2    Copyright (C) 2003-2022 Free Software Foundation, Inc.
   3
   4    This file is part of BFD, the Binary File Descriptor library.
   5
   6    This program is free software; you can redistribute it and/or
   7    modify it under the terms of the GNU General Public License as
   8    published by the Free Software Foundation; either version 2 of the
   9    License, or (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14    General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "ansidecl.h"
  22 #include <xtensa-isa.h>
  23 #include "xtensa-isa-internal.h"
  24
  25 \f
  26 /* Sysregs.  */
  27
  28 static xtensa_sysreg_internal sysregs[] = {
  29   { "LBEG", 0, 0 },
  30   { "LEND", 1, 0 },
  31   { "LCOUNT", 2, 0 },
  32   { "BR", 4, 0 },
  33   { "ACCLO", 16, 0 },
  34   { "ACCHI", 17, 0 },
  35   { "M0", 32, 0 },
  36   { "M1", 33, 0 },
  37   { "M2", 34, 0 },
  38   { "M3", 35, 0 },
  39   { "PTEVADDR", 83, 0 },
  40   { "MMID", 89, 0 },
  41   { "DDR", 104, 0 },
  42   { "176", 176, 0 },
  43   { "208", 208, 0 },
  44   { "INTERRUPT", 226, 0 },
  45   { "INTCLEAR", 227, 0 },
  46   { "CCOUNT", 234, 0 },
  47   { "PRID", 235, 0 },
  48   { "ICOUNT", 236, 0 },
  49   { "CCOMPARE0", 240, 0 },
  50   { "CCOMPARE1", 241, 0 },
  51   { "CCOMPARE2", 242, 0 },
  52   { "VECBASE", 231, 0 },
  53   { "EPC1", 177, 0 },
  54   { "EPC2", 178, 0 },
  55   { "EPC3", 179, 0 },
  56   { "EPC4", 180, 0 },
  57   { "EPC5", 181, 0 },
  58   { "EPC6", 182, 0 },
  59   { "EPC7", 183, 0 },
  60   { "EXCSAVE1", 209, 0 },
  61   { "EXCSAVE2", 210, 0 },
  62   { "EXCSAVE3", 211, 0 },
  63   { "EXCSAVE4", 212, 0 },
  64   { "EXCSAVE5", 213, 0 },
  65   { "EXCSAVE6", 214, 0 },
  66   { "EXCSAVE7", 215, 0 },
  67   { "EPS2", 194, 0 },
  68   { "EPS3", 195, 0 },
  69   { "EPS4", 196, 0 },
  70   { "EPS5", 197, 0 },
  71   { "EPS6", 198, 0 },
  72   { "EPS7", 199, 0 },
  73   { "EXCCAUSE", 232, 0 },
  74   { "DEPC", 192, 0 },
  75   { "EXCVADDR", 238, 0 },
  76   { "WINDOWBASE", 72, 0 },
  77   { "WINDOWSTART", 73, 0 },
  78   { "SAR", 3, 0 },
  79   { "LITBASE", 5, 0 },
  80   { "PS", 230, 0 },
  81   { "MISC0", 244, 0 },
  82   { "MISC1", 245, 0 },
  83   { "MISC2", 246, 0 },
  84   { "MISC3", 247, 0 },
  85   { "INTENABLE", 228, 0 },
  86   { "DBREAKA0", 144, 0 },
  87   { "DBREAKC0", 160, 0 },
  88   { "DBREAKA1", 145, 0 },
  89   { "DBREAKC1", 161, 0 },
  90   { "IBREAKA0", 128, 0 },
  91   { "IBREAKA1", 129, 0 },
  92   { "IBREAKENABLE", 96, 0 },
  93   { "ICOUNTLEVEL", 237, 0 },
  94   { "DEBUGCAUSE", 233, 0 },
  95   { "RASID", 90, 0 },
  96   { "ITLBCFG", 91, 0 },
  97   { "DTLBCFG", 92, 0 },
  98   { "CPENABLE", 224, 0 },
  99   { "SCOMPARE1", 12, 0 },
 100   { "THREADPTR", 231, 1 },
 101   { "FCR", 232, 1 },
 102   { "FSR", 233, 1 }
 103 };
 104
 105 #define NUM_SYSREGS 74
 106 #define MAX_SPECIAL_REG 247
 107 #define MAX_USER_REG 233
 108
 109 \f
 110 /* Processor states.  */
 111
 112 static xtensa_state_internal states[] = {
 113   { "LCOUNT", 32, 0 },
 114   { "PC", 32, 0 },
 115   { "ICOUNT", 32, 0 },
 116   { "DDR", 32, 0 },
 117   { "INTERRUPT", 32, 0 },
 118   { "CCOUNT", 32, 0 },
 119   { "XTSYNC", 1, 0 },
 120   { "VECBASE", 22, 0 },
 121   { "EPC1", 32, 0 },
 122   { "EPC2", 32, 0 },
 123   { "EPC3", 32, 0 },
 124   { "EPC4", 32, 0 },
 125   { "EPC5", 32, 0 },
 126   { "EPC6", 32, 0 },
 127   { "EPC7", 32, 0 },
 128   { "EXCSAVE1", 32, 0 },
 129   { "EXCSAVE2", 32, 0 },
 130   { "EXCSAVE3", 32, 0 },
 131   { "EXCSAVE4", 32, 0 },
 132   { "EXCSAVE5", 32, 0 },
 133   { "EXCSAVE6", 32, 0 },
 134   { "EXCSAVE7", 32, 0 },
 135   { "EPS2", 15, 0 },
 136   { "EPS3", 15, 0 },
 137   { "EPS4", 15, 0 },
 138   { "EPS5", 15, 0 },
 139   { "EPS6", 15, 0 },
 140   { "EPS7", 15, 0 },
 141   { "EXCCAUSE", 6, 0 },
 142   { "PSINTLEVEL", 4, 0 },
 143   { "PSUM", 1, 0 },
 144   { "PSWOE", 1, 0 },
 145   { "PSRING", 2, 0 },
 146   { "PSEXCM", 1, 0 },
 147   { "DEPC", 32, 0 },
 148   { "EXCVADDR", 32, 0 },
 149   { "WindowBase", 4, 0 },
 150   { "WindowStart", 16, 0 },
 151   { "PSCALLINC", 2, 0 },
 152   { "PSOWB", 4, 0 },
 153   { "LBEG", 32, 0 },
 154   { "LEND", 32, 0 },
 155   { "SAR", 6, 0 },
 156   { "THREADPTR", 32, 0 },
 157   { "LITBADDR", 20, 0 },
 158   { "LITBEN", 1, 0 },
 159   { "MISC0", 32, 0 },
 160   { "MISC1", 32, 0 },
 161   { "MISC2", 32, 0 },
 162   { "MISC3", 32, 0 },
 163   { "ACC", 40, 0 },
 164   { "InOCDMode", 1, 0 },
 165   { "INTENABLE", 32, 0 },
 166   { "DBREAKA0", 32, 0 },
 167   { "DBREAKC0", 8, 0 },
 168   { "DBREAKA1", 32, 0 },
 169   { "DBREAKC1", 8, 0 },
 170   { "IBREAKA0", 32, 0 },
 171   { "IBREAKA1", 32, 0 },
 172   { "IBREAKENABLE", 2, 0 },
 173   { "ICOUNTLEVEL", 4, 0 },
 174   { "DEBUGCAUSE", 6, 0 },
 175   { "DBNUM", 4, 0 },
 176   { "CCOMPARE0", 32, 0 },
 177   { "CCOMPARE1", 32, 0 },
 178   { "CCOMPARE2", 32, 0 },
 179   { "ASID3", 8, 0 },
 180   { "ASID2", 8, 0 },
 181   { "ASID1", 8, 0 },
 182   { "INSTPGSZID4", 2, 0 },
 183   { "DATAPGSZID4", 2, 0 },
 184   { "PTBASE", 10, 0 },
 185   { "CPENABLE", 1, 0 },
 186   { "SCOMPARE1", 32, 0 },
 187   { "RoundMode", 2, 0 },
 188   { "InvalidEnable", 1, 0 },
 189   { "DivZeroEnable", 1, 0 },
 190   { "OverflowEnable", 1, 0 },
 191   { "UnderflowEnable", 1, 0 },
 192   { "InexactEnable", 1, 0 },
 193   { "InvalidFlag", 1, 0 },
 194   { "DivZeroFlag", 1, 0 },
 195   { "OverflowFlag", 1, 0 },
 196   { "UnderflowFlag", 1, 0 },
 197   { "InexactFlag", 1, 0 },
 198   { "FPreserved20", 20, 0 },
 199   { "FPreserved20a", 20, 0 },
 200   { "FPreserved5", 5, 0 },
 201   { "FPreserved7", 7, 0 }
 202 };
 203
 204 #define NUM_STATES 89
 205
 206 /* Macros for xtensa_state numbers (for use in iclasses because the
 207    state numbers are not available when the iclass table is generated).  */
 208
 209 #define STATE_LCOUNT 0
 210 #define STATE_PC 1
 211 #define STATE_ICOUNT 2
 212 #define STATE_DDR 3
 213 #define STATE_INTERRUPT 4
 214 #define STATE_CCOUNT 5
 215 #define STATE_XTSYNC 6
 216 #define STATE_VECBASE 7
 217 #define STATE_EPC1 8
 218 #define STATE_EPC2 9
 219 #define STATE_EPC3 10
 220 #define STATE_EPC4 11
 221 #define STATE_EPC5 12
 222 #define STATE_EPC6 13
 223 #define STATE_EPC7 14
 224 #define STATE_EXCSAVE1 15
 225 #define STATE_EXCSAVE2 16
 226 #define STATE_EXCSAVE3 17
 227 #define STATE_EXCSAVE4 18
 228 #define STATE_EXCSAVE5 19
 229 #define STATE_EXCSAVE6 20
 230 #define STATE_EXCSAVE7 21
 231 #define STATE_EPS2 22
 232 #define STATE_EPS3 23
 233 #define STATE_EPS4 24
 234 #define STATE_EPS5 25
 235 #define STATE_EPS6 26
 236 #define STATE_EPS7 27
 237 #define STATE_EXCCAUSE 28
 238 #define STATE_PSINTLEVEL 29
 239 #define STATE_PSUM 30
 240 #define STATE_PSWOE 31
 241 #define STATE_PSRING 32
 242 #define STATE_PSEXCM 33
 243 #define STATE_DEPC 34
 244 #define STATE_EXCVADDR 35
 245 #define STATE_WindowBase 36
 246 #define STATE_WindowStart 37
 247 #define STATE_PSCALLINC 38
 248 #define STATE_PSOWB 39
 249 #define STATE_LBEG 40
 250 #define STATE_LEND 41
 251 #define STATE_SAR 42
 252 #define STATE_THREADPTR 43
 253 #define STATE_LITBADDR 44
 254 #define STATE_LITBEN 45
 255 #define STATE_MISC0 46
 256 #define STATE_MISC1 47
 257 #define STATE_MISC2 48
 258 #define STATE_MISC3 49
 259 #define STATE_ACC 50
 260 #define STATE_InOCDMode 51
 261 #define STATE_INTENABLE 52
 262 #define STATE_DBREAKA0 53
 263 #define STATE_DBREAKC0 54
 264 #define STATE_DBREAKA1 55
 265 #define STATE_DBREAKC1 56
 266 #define STATE_IBREAKA0 57
 267 #define STATE_IBREAKA1 58
 268 #define STATE_IBREAKENABLE 59
 269 #define STATE_ICOUNTLEVEL 60
 270 #define STATE_DEBUGCAUSE 61
 271 #define STATE_DBNUM 62
 272 #define STATE_CCOMPARE0 63
 273 #define STATE_CCOMPARE1 64
 274 #define STATE_CCOMPARE2 65
 275 #define STATE_ASID3 66
 276 #define STATE_ASID2 67
 277 #define STATE_ASID1 68
 278 #define STATE_INSTPGSZID4 69
 279 #define STATE_DATAPGSZID4 70
 280 #define STATE_PTBASE 71
 281 #define STATE_CPENABLE 72
 282 #define STATE_SCOMPARE1 73
 283 #define STATE_RoundMode 74
 284 #define STATE_InvalidEnable 75
 285 #define STATE_DivZeroEnable 76
 286 #define STATE_OverflowEnable 77
 287 #define STATE_UnderflowEnable 78
 288 #define STATE_InexactEnable 79
 289 #define STATE_InvalidFlag 80
 290 #define STATE_DivZeroFlag 81
 291 #define STATE_OverflowFlag 82
 292 #define STATE_UnderflowFlag 83
 293 #define STATE_InexactFlag 84
 294 #define STATE_FPreserved20 85
 295 #define STATE_FPreserved20a 86
 296 #define STATE_FPreserved5 87
 297 #define STATE_FPreserved7 88
 298
 299 \f
 300 /* Field definitions.  */
 301
 302 static unsigned
 303 Field_t_Slot_inst_get (const xtensa_insnbuf insn)
 304 {
 305   unsigned tie_t = (insn[0] >> 4) & 0xf;
 306   return tie_t;
 307 }
 308
 309 static void
 310 Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 311 {
 312   uint32 tie_t = val & 0xf;
 313   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 314 }
 315
 316 static unsigned
 317 Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
 318 {
 319   unsigned tie_t = ((insn[0] >> 4) & 0xf);
 320   return tie_t;
 321 }
 322
 323 static void
 324 Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 325 {
 326   uint32 tie_t = val & 0xf;
 327   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 328 }
 329
 330 static unsigned
 331 Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
 332 {
 333   unsigned tie_t = (insn[0] >> 4) & 0xf;
 334   return tie_t;
 335 }
 336
 337 static void
 338 Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 339 {
 340   uint32 tie_t = val & 0xf;
 341   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 342 }
 343
 344 static unsigned
 345 Field_t_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
 346 {
 347   unsigned tie_t = insn[0] & 0xf;
 348   return tie_t;
 349 }
 350
 351 static void
 352 Field_t_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
 353 {
 354   uint32 tie_t = val & 0xf;
 355   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 356 }
 357
 358 static unsigned
 359 Field_t_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
 360 {
 361   unsigned tie_t = insn[0] & 0xf;
 362   return tie_t;
 363 }
 364
 365 static void
 366 Field_t_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
 367 {
 368   uint32 tie_t = val & 0xf;
 369   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 370 }
 371
 372 static unsigned
 373 Field_t_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
 374 {
 375   unsigned tie_t = insn[0] & 0xf;
 376   return tie_t;
 377 }
 378
 379 static void
 380 Field_t_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
 381 {
 382   uint32 tie_t = val & 0xf;
 383   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 384 }
 385
 386 static unsigned
 387 Field_t_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
 388 {
 389   unsigned tie_t = insn[0] & 0xf;
 390   return tie_t;
 391 }
 392
 393 static void
 394 Field_t_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
 395 {
 396   uint32 tie_t = val & 0xf;
 397   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 398 }
 399
 400 static unsigned
 401 Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
 402 {
 403   unsigned tie_t = (insn[0] >> 12) & 1;
 404   return tie_t;
 405 }
 406
 407 static void
 408 Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 409 {
 410   uint32 tie_t = val & 1;
 411   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
 412 }
 413
 414 static unsigned
 415 Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
 416 {
 417   unsigned tie_t = (insn[0] >> 12) & 1;
 418   tie_t = (tie_t << 4) | ((insn[0] >> 4) & 0xf);
 419   return tie_t;
 420 }
 421
 422 static void
 423 Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 424 {
 425   uint32 tie_t = val & 0xf;
 426   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 427   tie_t = (val >> 4) & 1;
 428   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
 429 }
 430
 431 static unsigned
 432 Field_bbi_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
 433 {
 434   unsigned tie_t = (insn[0] >> 26) & 1;
 435   tie_t = (tie_t << 4) | (insn[0] & 0xf);
 436   return tie_t;
 437 }
 438
 439 static void
 440 Field_bbi_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
 441 {
 442   uint32 tie_t = val & 0xf;
 443   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 444   tie_t = (val >> 4) & 1;
 445   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
 446 }
 447
 448 static unsigned
 449 Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
 450 {
 451   unsigned tie_t = (insn[0] >> 12) & 0xfff;
 452   return tie_t;
 453 }
 454
 455 static void
 456 Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 457 {
 458   uint32 tie_t = val & 0xfff;
 459   insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
 460 }
 461
 462 static unsigned
 463 Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
 464 {
 465   unsigned tie_t = (insn[0] >> 16) & 0xff;
 466   return tie_t;
 467 }
 468
 469 static void
 470 Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 471 {
 472   uint32 tie_t = val & 0xff;
 473   insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
 474 }
 475
 476 static unsigned
 477 Field_imm8_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
 478 {
 479   unsigned tie_t = (insn[0] >> 12) & 0xff;
 480   return tie_t;
 481 }
 482
 483 static void
 484 Field_imm8_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
 485 {
 486   uint32 tie_t = val & 0xff;
 487   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
 488 }
 489
 490 static unsigned
 491 Field_imm8_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
 492 {
 493   unsigned tie_t = (insn[0] >> 12) & 0xf;
 494   tie_t = (tie_t << 4) | ((insn[0] >> 4) & 0xf);
 495   return tie_t;
 496 }
 497
 498 static void
 499 Field_imm8_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
 500 {
 501   uint32 tie_t = val & 0xf;
 502   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 503   tie_t = (val >> 4) & 0xf;
 504   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 505 }
 506
 507 static unsigned
 508 Field_s_Slot_inst_get (const xtensa_insnbuf insn)
 509 {
 510   unsigned tie_t = (insn[0] >> 8) & 0xf;
 511   return tie_t;
 512 }
 513
 514 static void
 515 Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 516 {
 517   uint32 tie_t = val & 0xf;
 518   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 519 }
 520
 521 static unsigned
 522 Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
 523 {
 524   unsigned tie_t = (insn[0] >> 8) & 0xf;
 525   return tie_t;
 526 }
 527
 528 static void
 529 Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 530 {
 531   uint32 tie_t = val & 0xf;
 532   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 533 }
 534
 535 static unsigned
 536 Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
 537 {
 538   unsigned tie_t = (insn[0] >> 8) & 0xf;
 539   return tie_t;
 540 }
 541
 542 static void
 543 Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 544 {
 545   uint32 tie_t = val & 0xf;
 546   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 547 }
 548
 549 static unsigned
 550 Field_s_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
 551 {
 552   unsigned tie_t = (insn[0] >> 4) & 0xf;
 553   return tie_t;
 554 }
 555
 556 static void
 557 Field_s_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
 558 {
 559   uint32 tie_t = val & 0xf;
 560   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 561 }
 562
 563 static unsigned
 564 Field_s_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
 565 {
 566   unsigned tie_t = (insn[0] >> 8) & 0xf;
 567   return tie_t;
 568 }
 569
 570 static void
 571 Field_s_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
 572 {
 573   uint32 tie_t = val & 0xf;
 574   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 575 }
 576
 577 static unsigned
 578 Field_s_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
 579 {
 580   unsigned tie_t = (insn[0] >> 8) & 0xf;
 581   return tie_t;
 582 }
 583
 584 static void
 585 Field_s_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
 586 {
 587   uint32 tie_t = val & 0xf;
 588   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 589 }
 590
 591 static unsigned
 592 Field_s_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
 593 {
 594   unsigned tie_t = (insn[0] >> 4) & 0xf;
 595   return tie_t;
 596 }
 597
 598 static void
 599 Field_s_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
 600 {
 601   uint32 tie_t = val & 0xf;
 602   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 603 }
 604
 605 static unsigned
 606 Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
 607 {
 608   unsigned tie_t = (insn[0] >> 8) & 0xf;
 609   tie_t = (tie_t << 8) | ((insn[0] >> 16) & 0xff);
 610   return tie_t;
 611 }
 612
 613 static void
 614 Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 615 {
 616   uint32 tie_t = val & 0xff;
 617   insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
 618   tie_t = (val >> 8) & 0xf;
 619   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 620 }
 621
 622 static unsigned
 623 Field_imm12b_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
 624 {
 625   unsigned tie_t = (insn[0] >> 4) & 0xf;
 626   tie_t = (tie_t << 8) | ((insn[0] >> 12) & 0xff);
 627   return tie_t;
 628 }
 629
 630 static void
 631 Field_imm12b_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
 632 {
 633   uint32 tie_t = val & 0xff;
 634   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
 635   tie_t = (val >> 8) & 0xf;
 636   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 637 }
 638
 639 static unsigned
 640 Field_imm12b_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
 641 {
 642   unsigned tie_t = (insn[0] >> 4) & 0xfff;
 643   return tie_t;
 644 }
 645
 646 static void
 647 Field_imm12b_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
 648 {
 649   uint32 tie_t = val & 0xfff;
 650   insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4);
 651 }
 652
 653 static unsigned
 654 Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
 655 {
 656   unsigned tie_t = (insn[0] >> 8) & 0xffff;
 657   return tie_t;
 658 }
 659
 660 static void
 661 Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 662 {
 663   uint32 tie_t = val & 0xffff;
 664   insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
 665 }
 666
 667 static unsigned
 668 Field_imm16_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
 669 {
 670   unsigned tie_t = (insn[0] >> 4) & 0xffff;
 671   return tie_t;
 672 }
 673
 674 static void
 675 Field_imm16_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
 676 {
 677   uint32 tie_t = val & 0xffff;
 678   insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4);
 679 }
 680
 681 static unsigned
 682 Field_m_Slot_inst_get (const xtensa_insnbuf insn)
 683 {
 684   unsigned tie_t = (insn[0] >> 6) & 3;
 685   return tie_t;
 686 }
 687
 688 static void
 689 Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 690 {
 691   uint32 tie_t = val & 3;
 692   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
 693 }
 694
 695 static unsigned
 696 Field_m_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
 697 {
 698   unsigned tie_t = (insn[0] >> 2) & 3;
 699   return tie_t;
 700 }
 701
 702 static void
 703 Field_m_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
 704 {
 705   uint32 tie_t = val & 3;
 706   insn[0] = (insn[0] & ~0xc) | (tie_t << 2);
 707 }
 708
 709 static unsigned
 710 Field_n_Slot_inst_get (const xtensa_insnbuf insn)
 711 {
 712   unsigned tie_t = (insn[0] >> 4) & 3;
 713   return tie_t;
 714 }
 715
 716 static void
 717 Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 718 {
 719   uint32 tie_t = val & 3;
 720   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
 721 }
 722
 723 static unsigned
 724 Field_n_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
 725 {
 726   unsigned tie_t = insn[0] & 3;
 727   return tie_t;
 728 }
 729
 730 static void
 731 Field_n_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
 732 {
 733   uint32 tie_t = val & 3;
 734   insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
 735 }
 736
 737 static unsigned
 738 Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
 739 {
 740   unsigned tie_t = (insn[0] >> 6) & 0x3ffff;
 741   return tie_t;
 742 }
 743
 744 static void
 745 Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 746 {
 747   uint32 tie_t = val & 0x3ffff;
 748   insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
 749 }
 750
 751 static unsigned
 752 Field_offset_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
 753 {
 754   unsigned tie_t = insn[0] & 0x3ffff;
 755   return tie_t;
 756 }
 757
 758 static void
 759 Field_offset_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
 760 {
 761   uint32 tie_t = val & 0x3ffff;
 762   insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0);
 763 }
 764
 765 static unsigned
 766 Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
 767 {
 768   unsigned tie_t = insn[0] & 0xf;
 769   return tie_t;
 770 }
 771
 772 static void
 773 Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 774 {
 775   uint32 tie_t = val & 0xf;
 776   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 777 }
 778
 779 static unsigned
 780 Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
 781 {
 782   unsigned tie_t = insn[0] & 0xf;
 783   return tie_t;
 784 }
 785
 786 static void
 787 Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 788 {
 789   uint32 tie_t = val & 0xf;
 790   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 791 }
 792
 793 static unsigned
 794 Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
 795 {
 796   unsigned tie_t = insn[0] & 0xf;
 797   return tie_t;
 798 }
 799
 800 static void
 801 Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 802 {
 803   uint32 tie_t = val & 0xf;
 804   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 805 }
 806
 807 static unsigned
 808 Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
 809 {
 810   unsigned tie_t = (insn[0] >> 16) & 0xf;
 811   return tie_t;
 812 }
 813
 814 static void
 815 Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 816 {
 817   uint32 tie_t = val & 0xf;
 818   insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
 819 }
 820
 821 static unsigned
 822 Field_op1_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
 823 {
 824   unsigned tie_t = (insn[0] >> 12) & 0xf;
 825   return tie_t;
 826 }
 827
 828 static void
 829 Field_op1_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
 830 {
 831   uint32 tie_t = val & 0xf;
 832   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 833 }
 834
 835 static unsigned
 836 Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
 837 {
 838   unsigned tie_t = (insn[0] >> 20) & 0xf;
 839   return tie_t;
 840 }
 841
 842 static void
 843 Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 844 {
 845   uint32 tie_t = val & 0xf;
 846   insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
 847 }
 848
 849 static unsigned
 850 Field_op2_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
 851 {
 852   unsigned tie_t = (insn[0] >> 16) & 0xf;
 853   return tie_t;
 854 }
 855
 856 static void
 857 Field_op2_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
 858 {
 859   uint32 tie_t = val & 0xf;
 860   insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
 861 }
 862
 863 static unsigned
 864 Field_op2_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
 865 {
 866   unsigned tie_t = (insn[0] >> 8) & 0xf;
 867   return tie_t;
 868 }
 869
 870 static void
 871 Field_op2_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
 872 {
 873   uint32 tie_t = val & 0xf;
 874   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 875 }
 876
 877 static unsigned
 878 Field_r_Slot_inst_get (const xtensa_insnbuf insn)
 879 {
 880   unsigned tie_t = (insn[0] >> 12) & 0xf;
 881   return tie_t;
 882 }
 883
 884 static void
 885 Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 886 {
 887   uint32 tie_t = val & 0xf;
 888   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 889 }
 890
 891 static unsigned
 892 Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
 893 {
 894   unsigned tie_t = (insn[0] >> 12) & 0xf;
 895   return tie_t;
 896 }
 897
 898 static void
 899 Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 900 {
 901   uint32 tie_t = val & 0xf;
 902   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 903 }
 904
 905 static unsigned
 906 Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
 907 {
 908   unsigned tie_t = (insn[0] >> 12) & 0xf;
 909   return tie_t;
 910 }
 911
 912 static void
 913 Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 914 {
 915   uint32 tie_t = val & 0xf;
 916   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 917 }
 918
 919 static unsigned
 920 Field_r_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
 921 {
 922   unsigned tie_t = (insn[0] >> 8) & 0xf;
 923   return tie_t;
 924 }
 925
 926 static void
 927 Field_r_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
 928 {
 929   uint32 tie_t = val & 0xf;
 930   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 931 }
 932
 933 static unsigned
 934 Field_r_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
 935 {
 936   unsigned tie_t = (insn[0] >> 4) & 0xf;
 937   return tie_t;
 938 }
 939
 940 static void
 941 Field_r_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
 942 {
 943   uint32 tie_t = val & 0xf;
 944   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 945 }
 946
 947 static unsigned
 948 Field_r_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
 949 {
 950   unsigned tie_t = (insn[0] >> 4) & 0xf;
 951   return tie_t;
 952 }
 953
 954 static void
 955 Field_r_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
 956 {
 957   uint32 tie_t = val & 0xf;
 958   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 959 }
 960
 961 static unsigned
 962 Field_r_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
 963 {
 964   unsigned tie_t = insn[0] & 0xf;
 965   return tie_t;
 966 }
 967
 968 static void
 969 Field_r_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
 970 {
 971   uint32 tie_t = val & 0xf;
 972   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 973 }
 974
 975 static unsigned
 976 Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
 977 {
 978   unsigned tie_t = (insn[0] >> 20) & 1;
 979   return tie_t;
 980 }
 981
 982 static void
 983 Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 984 {
 985   uint32 tie_t = val & 1;
 986   insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
 987 }
 988
 989 static unsigned
 990 Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
 991 {
 992   unsigned tie_t = (insn[0] >> 16) & 1;
 993   return tie_t;
 994 }
 995
 996 static void
 997 Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 998 {
 999   uint32 tie_t = val & 1;
1000   insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
1001 }
1002
1003 static unsigned
1004 Field_sae4_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1005 {
1006   unsigned tie_t = (insn[0] << 12) & 1;
1007   return tie_t;
1008 }
1009
1010 static void
1011 Field_sae4_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1012 {
1013   uint32 tie_t = val & 1;
1014   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
1015 }
1016
1017 static unsigned
1018 Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
1019 {
1020   unsigned tie_t = (insn[0] >> 16) & 1;
1021   tie_t = (tie_t << 4) | ((insn[0] >> 8) & 0xf);
1022   return tie_t;
1023 }
1024
1025 static void
1026 Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1027 {
1028   uint32 tie_t = val & 0xf;
1029   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1030   tie_t = (val >> 4) & 1;
1031   insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
1032 }
1033
1034 static unsigned
1035 Field_sae_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1036 {
1037   unsigned tie_t = (insn[0] >> 12) & 1;
1038   tie_t = (tie_t << 4) | ((insn[0] >> 4) & 0xf);
1039   return tie_t;
1040 }
1041
1042 static void
1043 Field_sae_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1044 {
1045   uint32 tie_t = val & 0xf;
1046   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1047   tie_t = (val >> 4) & 1;
1048   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
1049 }
1050
1051 static unsigned
1052 Field_sae_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
1053 {
1054   unsigned tie_t = (insn[0] >> 12) & 0x1f;
1055   return tie_t;
1056 }
1057
1058 static void
1059 Field_sae_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
1060 {
1061   uint32 tie_t = val & 0x1f;
1062   insn[0] = (insn[0] & ~0x1f000) | (tie_t << 12);
1063 }
1064
1065 static unsigned
1066 Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
1067 {
1068   unsigned tie_t = (insn[0] >> 20) & 1;
1069   tie_t = (tie_t << 4) | ((insn[0] >> 4) & 0xf);
1070   return tie_t;
1071 }
1072
1073 static void
1074 Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1075 {
1076   uint32 tie_t = val & 0xf;
1077   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1078   tie_t = (val >> 4) & 1;
1079   insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
1080 }
1081
1082 static unsigned
1083 Field_sal_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1084 {
1085   unsigned tie_t = (insn[0] >> 16) & 1;
1086   tie_t = (tie_t << 4) | (insn[0] & 0xf);
1087   return tie_t;
1088 }
1089
1090 static void
1091 Field_sal_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1092 {
1093   uint32 tie_t = val & 0xf;
1094   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1095   tie_t = (val >> 4) & 1;
1096   insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
1097 }
1098
1099 static unsigned
1100 Field_sal_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
1101 {
1102   unsigned tie_t = (insn[0] >> 12) & 1;
1103   tie_t = (tie_t << 4) | (insn[0] & 0xf);
1104   return tie_t;
1105 }
1106
1107 static void
1108 Field_sal_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
1109 {
1110   uint32 tie_t = val & 0xf;
1111   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1112   tie_t = (val >> 4) & 1;
1113   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
1114 }
1115
1116 static unsigned
1117 Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
1118 {
1119   unsigned tie_t = (insn[0] >> 20) & 1;
1120   tie_t = (tie_t << 4) | ((insn[0] >> 8) & 0xf);
1121   return tie_t;
1122 }
1123
1124 static void
1125 Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1126 {
1127   uint32 tie_t = val & 0xf;
1128   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1129   tie_t = (val >> 4) & 1;
1130   insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
1131 }
1132
1133 static unsigned
1134 Field_sargt_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1135 {
1136   unsigned tie_t = (insn[0] >> 16) & 1;
1137   tie_t = (tie_t << 4) | ((insn[0] >> 4) & 0xf);
1138   return tie_t;
1139 }
1140
1141 static void
1142 Field_sargt_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1143 {
1144   uint32 tie_t = val & 0xf;
1145   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1146   tie_t = (val >> 4) & 1;
1147   insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
1148 }
1149
1150 static unsigned
1151 Field_sargt_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
1152 {
1153   unsigned tie_t = (insn[0] >> 8) & 0x1f;
1154   return tie_t;
1155 }
1156
1157 static void
1158 Field_sargt_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
1159 {
1160   uint32 tie_t = val & 0x1f;
1161   insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8);
1162 }
1163
1164 static unsigned
1165 Field_sargt_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
1166 {
1167   unsigned tie_t = (insn[0] >> 8) & 0x1f;
1168   return tie_t;
1169 }
1170
1171 static void
1172 Field_sargt_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
1173 {
1174   uint32 tie_t = val & 0x1f;
1175   insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8);
1176 }
1177
1178 static unsigned
1179 Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
1180 {
1181   unsigned tie_t = (insn[0] >> 4) & 1;
1182   return tie_t;
1183 }
1184
1185 static void
1186 Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1187 {
1188   uint32 tie_t = val & 1;
1189   insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
1190 }
1191
1192 static unsigned
1193 Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
1194 {
1195   unsigned tie_t = (insn[0] >> 4) & 1;
1196   tie_t = (tie_t << 4) | ((insn[0] >> 8) & 0xf);
1197   return tie_t;
1198 }
1199
1200 static void
1201 Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1202 {
1203   uint32 tie_t = val & 0xf;
1204   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1205   tie_t = (val >> 4) & 1;
1206   insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
1207 }
1208
1209 static unsigned
1210 Field_sas_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1211 {
1212   unsigned tie_t = insn[0] & 1;
1213   tie_t = (tie_t << 4) | ((insn[0] >> 4) & 0xf);
1214   return tie_t;
1215 }
1216
1217 static void
1218 Field_sas_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1219 {
1220   uint32 tie_t = val & 0xf;
1221   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1222   tie_t = (val >> 4) & 1;
1223   insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
1224 }
1225
1226 static unsigned
1227 Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
1228 {
1229   unsigned tie_t = (insn[0] >> 12) & 0xf;
1230   tie_t = (tie_t << 4) | ((insn[0] >> 8) & 0xf);
1231   return tie_t;
1232 }
1233
1234 static void
1235 Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1236 {
1237   uint32 tie_t = val & 0xf;
1238   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1239   tie_t = (val >> 4) & 0xf;
1240   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1241 }
1242
1243 static unsigned
1244 Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
1245 {
1246   unsigned tie_t = (insn[0] >> 12) & 0xf;
1247   tie_t = (tie_t << 4) | ((insn[0] >> 8) & 0xf);
1248   return tie_t;
1249 }
1250
1251 static void
1252 Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1253 {
1254   uint32 tie_t = val & 0xf;
1255   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1256   tie_t = (val >> 4) & 0xf;
1257   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1258 }
1259
1260 static unsigned
1261 Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
1262 {
1263   unsigned tie_t = (insn[0] >> 12) & 0xf;
1264   tie_t = (tie_t << 4) | ((insn[0] >> 8) & 0xf);
1265   return tie_t;
1266 }
1267
1268 static void
1269 Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1270 {
1271   uint32 tie_t = val & 0xf;
1272   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1273   tie_t = (val >> 4) & 0xf;
1274   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1275 }
1276
1277 static unsigned
1278 Field_st_Slot_inst_get (const xtensa_insnbuf insn)
1279 {
1280   unsigned tie_t = (insn[0] >> 8) & 0xf;
1281   tie_t = (tie_t << 4) | ((insn[0] >> 4) & 0xf);
1282   return tie_t;
1283 }
1284
1285 static void
1286 Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1287 {
1288   uint32 tie_t = val & 0xf;
1289   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1290   tie_t = (val >> 4) & 0xf;
1291   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1292 }
1293
1294 static unsigned
1295 Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
1296 {
1297   unsigned tie_t = (insn[0] >> 8) & 0xf;
1298   tie_t = (tie_t << 4) | ((insn[0] >> 4) & 0xf);
1299   return tie_t;
1300 }
1301
1302 static void
1303 Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1304 {
1305   uint32 tie_t = val & 0xf;
1306   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1307   tie_t = (val >> 4) & 0xf;
1308   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1309 }
1310
1311 static unsigned
1312 Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
1313 {
1314   unsigned tie_t = (insn[0] >> 8) & 0xf;
1315   tie_t = (tie_t << 4) | ((insn[0] >> 4) & 0xf);
1316   return tie_t;
1317 }
1318
1319 static void
1320 Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1321 {
1322   uint32 tie_t = val & 0xf;
1323   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1324   tie_t = (val >> 4) & 0xf;
1325   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1326 }
1327
1328 static unsigned
1329 Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
1330 {
1331   unsigned tie_t = (insn[0] >> 5) & 7;
1332   return tie_t;
1333 }
1334
1335 static void
1336 Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1337 {
1338   uint32 tie_t = val & 7;
1339   insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
1340 }
1341
1342 static unsigned
1343 Field_thi3_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1344 {
1345   unsigned tie_t = (insn[0] >> 1) & 7;
1346   return tie_t;
1347 }
1348
1349 static void
1350 Field_thi3_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1351 {
1352   uint32 tie_t = val & 7;
1353   insn[0] = (insn[0] & ~0xe) | (tie_t << 1);
1354 }
1355
1356 static unsigned
1357 Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
1358 {
1359   unsigned tie_t = (insn[0] >> 12) & 0xf;
1360   return tie_t;
1361 }
1362
1363 static void
1364 Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1365 {
1366   uint32 tie_t = val & 0xf;
1367   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1368 }
1369
1370 static unsigned
1371 Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
1372 {
1373   unsigned tie_t = (insn[0] >> 12) & 0xf;
1374   return tie_t;
1375 }
1376
1377 static void
1378 Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1379 {
1380   uint32 tie_t = val & 0xf;
1381   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1382 }
1383
1384 static unsigned
1385 Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
1386 {
1387   unsigned tie_t = (insn[0] >> 12) & 0xf;
1388   return tie_t;
1389 }
1390
1391 static void
1392 Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1393 {
1394   uint32 tie_t = val & 0xf;
1395   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1396 }
1397
1398 static unsigned
1399 Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
1400 {
1401   unsigned tie_t = (insn[0] >> 6) & 3;
1402   tie_t = (tie_t << 2) | ((insn[0] >> 4) & 3);
1403   return tie_t;
1404 }
1405
1406 static void
1407 Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1408 {
1409   uint32 tie_t = val & 3;
1410   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1411   tie_t = (val >> 2) & 3;
1412   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
1413 }
1414
1415 static unsigned
1416 Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
1417 {
1418   unsigned tie_t = (insn[0] >> 7) & 1;
1419   return tie_t;
1420 }
1421
1422 static void
1423 Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1424 {
1425   uint32 tie_t = val & 1;
1426   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
1427 }
1428
1429 static unsigned
1430 Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
1431 {
1432   unsigned tie_t = (insn[0] >> 7) & 1;
1433   return tie_t;
1434 }
1435
1436 static void
1437 Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1438 {
1439   uint32 tie_t = val & 1;
1440   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
1441 }
1442
1443 static unsigned
1444 Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1445 {
1446   unsigned tie_t = (insn[0] >> 12) & 0xf;
1447   return tie_t;
1448 }
1449
1450 static void
1451 Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1452 {
1453   uint32 tie_t = val & 0xf;
1454   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1455 }
1456
1457 static unsigned
1458 Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1459 {
1460   unsigned tie_t = (insn[0] >> 12) & 0xf;
1461   return tie_t;
1462 }
1463
1464 static void
1465 Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1466 {
1467   uint32 tie_t = val & 0xf;
1468   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1469 }
1470
1471 static unsigned
1472 Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1473 {
1474   unsigned tie_t = (insn[0] >> 4) & 3;
1475   return tie_t;
1476 }
1477
1478 static void
1479 Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1480 {
1481   uint32 tie_t = val & 3;
1482   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1483 }
1484
1485 static unsigned
1486 Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1487 {
1488   unsigned tie_t = (insn[0] >> 4) & 3;
1489   return tie_t;
1490 }
1491
1492 static void
1493 Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1494 {
1495   uint32 tie_t = val & 3;
1496   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1497 }
1498
1499 static unsigned
1500 Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1501 {
1502   unsigned tie_t = (insn[0] >> 12) & 0xf;
1503   return tie_t;
1504 }
1505
1506 static void
1507 Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1508 {
1509   uint32 tie_t = val & 0xf;
1510   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1511 }
1512
1513 static unsigned
1514 Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1515 {
1516   unsigned tie_t = (insn[0] >> 12) & 0xf;
1517   return tie_t;
1518 }
1519
1520 static void
1521 Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1522 {
1523   uint32 tie_t = val & 0xf;
1524   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1525 }
1526
1527 static unsigned
1528 Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1529 {
1530   unsigned tie_t = (insn[0] >> 4) & 7;
1531   return tie_t;
1532 }
1533
1534 static void
1535 Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1536 {
1537   uint32 tie_t = val & 7;
1538   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1539 }
1540
1541 static unsigned
1542 Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1543 {
1544   unsigned tie_t = (insn[0] >> 4) & 7;
1545   return tie_t;
1546 }
1547
1548 static void
1549 Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1550 {
1551   uint32 tie_t = val & 7;
1552   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1553 }
1554
1555 static unsigned
1556 Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
1557 {
1558   unsigned tie_t = (insn[0] >> 6) & 1;
1559   return tie_t;
1560 }
1561
1562 static void
1563 Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1564 {
1565   uint32 tie_t = val & 1;
1566   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1567 }
1568
1569 static unsigned
1570 Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
1571 {
1572   unsigned tie_t = (insn[0] >> 6) & 1;
1573   return tie_t;
1574 }
1575
1576 static void
1577 Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1578 {
1579   uint32 tie_t = val & 1;
1580   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1581 }
1582
1583 static unsigned
1584 Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
1585 {
1586   unsigned tie_t = (insn[0] >> 4) & 3;
1587   tie_t = (tie_t << 4) | ((insn[0] >> 12) & 0xf);
1588   return tie_t;
1589 }
1590
1591 static void
1592 Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1593 {
1594   uint32 tie_t = val & 0xf;
1595   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1596   tie_t = (val >> 4) & 3;
1597   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1598 }
1599
1600 static unsigned
1601 Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
1602 {
1603   unsigned tie_t = (insn[0] >> 4) & 3;
1604   tie_t = (tie_t << 4) | ((insn[0] >> 12) & 0xf);
1605   return tie_t;
1606 }
1607
1608 static void
1609 Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1610 {
1611   uint32 tie_t = val & 0xf;
1612   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1613   tie_t = (val >> 4) & 3;
1614   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1615 }
1616
1617 static unsigned
1618 Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
1619 {
1620   unsigned tie_t = (insn[0] >> 4) & 7;
1621   tie_t = (tie_t << 4) | ((insn[0] >> 12) & 0xf);
1622   return tie_t;
1623 }
1624
1625 static void
1626 Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1627 {
1628   uint32 tie_t = val & 0xf;
1629   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1630   tie_t = (val >> 4) & 7;
1631   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1632 }
1633
1634 static unsigned
1635 Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
1636 {
1637   unsigned tie_t = (insn[0] >> 4) & 7;
1638   tie_t = (tie_t << 4) | ((insn[0] >> 12) & 0xf);
1639   return tie_t;
1640 }
1641
1642 static void
1643 Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1644 {
1645   uint32 tie_t = val & 0xf;
1646   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1647   tie_t = (val >> 4) & 7;
1648   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1649 }
1650
1651 static unsigned
1652 Field_imm7_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
1653 {
1654   unsigned tie_t = insn[0] & 0x7f;
1655   return tie_t;
1656 }
1657
1658 static void
1659 Field_imm7_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
1660 {
1661   uint32 tie_t;
1662   tie_t = val & 0x7f;
1663   insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
1664 }
1665
1666 static unsigned
1667 Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
1668 {
1669   unsigned tie_t = (insn[0] >> 15) & 1;
1670   return tie_t;
1671 }
1672
1673 static void
1674 Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1675 {
1676   uint32 tie_t = val & 1;
1677   insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
1678 }
1679
1680 static unsigned
1681 Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
1682 {
1683   unsigned tie_t = (insn[0] >> 14) & 1;
1684   return tie_t;
1685 }
1686
1687 static void
1688 Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1689 {
1690   uint32 tie_t = val & 1;
1691   insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
1692 }
1693
1694 static unsigned
1695 Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
1696 {
1697   unsigned tie_t = (insn[0] >> 14) & 3;
1698   return tie_t;
1699 }
1700
1701 static void
1702 Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1703 {
1704   uint32 tie_t = val & 3;
1705   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1706 }
1707
1708 static unsigned
1709 Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
1710 {
1711   unsigned tie_t = (insn[0] >> 7) & 1;
1712   return tie_t;
1713 }
1714
1715 static void
1716 Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1717 {
1718   uint32 tie_t = val & 1;
1719   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
1720 }
1721
1722 static unsigned
1723 Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
1724 {
1725   unsigned tie_t = (insn[0] >> 6) & 1;
1726   return tie_t;
1727 }
1728
1729 static void
1730 Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1731 {
1732   uint32 tie_t = val & 1;
1733   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1734 }
1735
1736 static unsigned
1737 Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
1738 {
1739   unsigned tie_t = (insn[0] >> 4) & 3;
1740   return tie_t;
1741 }
1742
1743 static void
1744 Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1745 {
1746   uint32 tie_t = val & 3;
1747   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1748 }
1749
1750 static unsigned
1751 Field_w_Slot_inst_get (const xtensa_insnbuf insn)
1752 {
1753   unsigned tie_t = (insn[0] >> 12) & 3;
1754   return tie_t;
1755 }
1756
1757 static void
1758 Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1759 {
1760   uint32 tie_t = val & 3;
1761   insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
1762 }
1763
1764 static unsigned
1765 Field_y_Slot_inst_get (const xtensa_insnbuf insn)
1766 {
1767   unsigned tie_t = (insn[0] >> 6) & 1;
1768   return tie_t;
1769 }
1770
1771 static void
1772 Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1773 {
1774   uint32 tie_t = val & 1;
1775   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1776 }
1777
1778 static unsigned
1779 Field_x_Slot_inst_get (const xtensa_insnbuf insn)
1780 {
1781   unsigned tie_t = (insn[0] >> 14) & 1;
1782   return tie_t;
1783 }
1784
1785 static void
1786 Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1787 {
1788   uint32 tie_t = val & 1;
1789   insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
1790 }
1791
1792 static unsigned
1793 Field_t2_Slot_inst_get (const xtensa_insnbuf insn)
1794 {
1795   unsigned tie_t = (insn[0] >> 5) & 7;
1796   return tie_t;
1797 }
1798
1799 static void
1800 Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1801 {
1802   uint32 tie_t = val & 7;
1803   insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
1804 }
1805
1806 static unsigned
1807 Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn)
1808 {
1809   unsigned tie_t = (insn[0] >> 5) & 7;
1810   return tie_t;
1811 }
1812
1813 static void
1814 Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1815 {
1816   uint32 tie_t = val & 7;
1817   insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
1818 }
1819
1820 static unsigned
1821 Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn)
1822 {
1823   unsigned tie_t = (insn[0] >> 5) & 7;
1824   return tie_t;
1825 }
1826
1827 static void
1828 Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1829 {
1830   uint32 tie_t = val & 7;
1831   insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
1832 }
1833
1834 static unsigned
1835 Field_s2_Slot_inst_get (const xtensa_insnbuf insn)
1836 {
1837   unsigned tie_t = (insn[0] >> 9) & 7;
1838   return tie_t;
1839 }
1840
1841 static void
1842 Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1843 {
1844   uint32 tie_t = val & 7;
1845   insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1846 }
1847
1848 static unsigned
1849 Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn)
1850 {
1851   unsigned tie_t = (insn[0] >> 9) & 7;
1852   return tie_t;
1853 }
1854
1855 static void
1856 Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1857 {
1858   uint32 tie_t = val & 7;
1859   insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1860 }
1861
1862 static unsigned
1863 Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn)
1864 {
1865   unsigned tie_t = (insn[0] >> 9) & 7;
1866   return tie_t;
1867 }
1868
1869 static void
1870 Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1871 {
1872   uint32 tie_t = val & 7;
1873   insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1874 }
1875
1876 static unsigned
1877 Field_r2_Slot_inst_get (const xtensa_insnbuf insn)
1878 {
1879   unsigned tie_t = (insn[0] >> 13) & 7;
1880   return tie_t;
1881 }
1882
1883 static void
1884 Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1885 {
1886   uint32 tie_t = val & 7;
1887   insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
1888 }
1889
1890 static unsigned
1891 Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn)
1892 {
1893   unsigned tie_t = (insn[0] >> 13) & 7;
1894   return tie_t;
1895 }
1896
1897 static void
1898 Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1899 {
1900   uint32 tie_t = val & 7;
1901   insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
1902 }
1903
1904 static unsigned
1905 Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn)
1906 {
1907   unsigned tie_t = (insn[0] >> 13) & 7;
1908   return tie_t;
1909 }
1910
1911 static void
1912 Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1913 {
1914   uint32 tie_t = val & 7;
1915   insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
1916 }
1917
1918 static unsigned
1919 Field_t4_Slot_inst_get (const xtensa_insnbuf insn)
1920 {
1921   unsigned tie_t = (insn[0] >> 6) & 3;
1922   return tie_t;
1923 }
1924
1925 static void
1926 Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1927 {
1928   uint32 tie_t = val & 3;
1929   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
1930 }
1931
1932 static unsigned
1933 Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn)
1934 {
1935   unsigned tie_t = (insn[0] >> 6) & 3;
1936   return tie_t;
1937 }
1938
1939 static void
1940 Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1941 {
1942   uint32 tie_t = val & 3;
1943   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
1944 }
1945
1946 static unsigned
1947 Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn)
1948 {
1949   unsigned tie_t = (insn[0] >> 6) & 3;
1950   return tie_t;
1951 }
1952
1953 static void
1954 Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1955 {
1956   uint32 tie_t = val & 3;
1957   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
1958 }
1959
1960 static unsigned
1961 Field_s4_Slot_inst_get (const xtensa_insnbuf insn)
1962 {
1963   unsigned tie_t = (insn[0] >> 10) & 3;
1964   return tie_t;
1965 }
1966
1967 static void
1968 Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1969 {
1970   uint32 tie_t = val & 3;
1971   insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
1972 }
1973
1974 static unsigned
1975 Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn)
1976 {
1977   unsigned tie_t = (insn[0] >> 10) & 3;
1978   return tie_t;
1979 }
1980
1981 static void
1982 Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1983 {
1984   uint32 tie_t = val & 3;
1985   insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
1986 }
1987
1988 static unsigned
1989 Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn)
1990 {
1991   unsigned tie_t = (insn[0] >> 10) & 3;
1992   return tie_t;
1993 }
1994
1995 static void
1996 Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1997 {
1998   uint32 tie_t = val & 3;
1999   insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
2000 }
2001
2002 static unsigned
2003 Field_r4_Slot_inst_get (const xtensa_insnbuf insn)
2004 {
2005   unsigned tie_t = (insn[0] >> 14) & 3;
2006   return tie_t;
2007 }
2008
2009 static void
2010 Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2011 {
2012   uint32 tie_t = val & 3;
2013   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2014 }
2015
2016 static unsigned
2017 Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn)
2018 {
2019   unsigned tie_t = (insn[0] >> 14) & 3;
2020   return tie_t;
2021 }
2022
2023 static void
2024 Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2025 {
2026   uint32 tie_t = val & 3;
2027   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2028 }
2029
2030 static unsigned
2031 Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn)
2032 {
2033   unsigned tie_t = (insn[0] >> 14) & 3;
2034   return tie_t;
2035 }
2036
2037 static void
2038 Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2039 {
2040   uint32 tie_t = val & 3;
2041   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2042 }
2043
2044 static unsigned
2045 Field_t8_Slot_inst_get (const xtensa_insnbuf insn)
2046 {
2047   unsigned tie_t = (insn[0] >> 7) & 1;
2048   return tie_t;
2049 }
2050
2051 static void
2052 Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2053 {
2054   uint32 tie_t = val & 1;
2055   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2056 }
2057
2058 static unsigned
2059 Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn)
2060 {
2061   unsigned tie_t = (insn[0] >> 7) & 1;
2062   return tie_t;
2063 }
2064
2065 static void
2066 Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2067 {
2068   uint32 tie_t = val & 1;
2069   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2070 }
2071
2072 static unsigned
2073 Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn)
2074 {
2075   unsigned tie_t = (insn[0] >> 7) & 1;
2076   return tie_t;
2077 }
2078
2079 static void
2080 Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2081 {
2082   uint32 tie_t = val & 1;
2083   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2084 }
2085
2086 static unsigned
2087 Field_s8_Slot_inst_get (const xtensa_insnbuf insn)
2088 {
2089   unsigned tie_t = (insn[0] >> 11) & 1;
2090   return tie_t;
2091 }
2092
2093 static void
2094 Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2095 {
2096   uint32 tie_t = val & 1;
2097   insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
2098 }
2099
2100 static unsigned
2101 Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn)
2102 {
2103   unsigned tie_t = (insn[0] >> 11) & 1;
2104   return tie_t;
2105 }
2106
2107 static void
2108 Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2109 {
2110   uint32 tie_t = val & 1;
2111   insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
2112 }
2113
2114 static unsigned
2115 Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn)
2116 {
2117   unsigned tie_t = (insn[0] >> 11) & 1;
2118   return tie_t;
2119 }
2120
2121 static void
2122 Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2123 {
2124   uint32 tie_t = val & 1;
2125   insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
2126 }
2127
2128 static unsigned
2129 Field_r8_Slot_inst_get (const xtensa_insnbuf insn)
2130 {
2131   unsigned tie_t = (insn[0] >> 15) & 1;
2132   return tie_t;
2133 }
2134
2135 static void
2136 Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2137 {
2138   uint32 tie_t = val & 1;
2139   insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
2140 }
2141
2142 static unsigned
2143 Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn)
2144 {
2145   unsigned tie_t = (insn[0] >> 15) & 1;
2146   return tie_t;
2147 }
2148
2149 static void
2150 Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2151 {
2152   uint32 tie_t = val & 1;
2153   insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
2154 }
2155
2156 static unsigned
2157 Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn)
2158 {
2159   unsigned tie_t = (insn[0] >> 15) & 1;
2160   return tie_t;
2161 }
2162
2163 static void
2164 Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2165 {
2166   uint32 tie_t = val & 1;
2167   insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
2168 }
2169
2170 static unsigned
2171 Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
2172 {
2173   unsigned tie_t = (insn[0] >> 9) & 0x7fff;
2174   return tie_t;
2175 }
2176
2177 static void
2178 Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2179 {
2180   uint32 tie_t = val & 0x7fff;
2181   insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
2182 }
2183
2184 static unsigned
2185 Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
2186 {
2187   unsigned tie_t = (insn[0] >> 6) & 0x3ffff;
2188   return tie_t;
2189 }
2190
2191 static void
2192 Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2193 {
2194   uint32 tie_t = val & 0x3ffff;
2195   insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
2196 }
2197
2198 static unsigned
2199 Field_xt_wbr18_imm_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
2200 {
2201   unsigned tie_t = (insn[0] >> 8) & 0x3ffff;
2202   return tie_t;
2203 }
2204
2205 static void
2206 Field_xt_wbr18_imm_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
2207 {
2208   uint32 tie_t = val & 0x3ffff;
2209   insn[0] = (insn[0] & ~0x3ffff00) | (tie_t << 8);
2210 }
2211
2212 static unsigned
2213 Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
2214 {
2215   unsigned tie_t = (insn[0] >> 20) & 0xf;
2216   return tie_t;
2217 }
2218
2219 static void
2220 Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
2221 {
2222   uint32 tie_t = val & 0xf;
2223   insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
2224 }
2225
2226 static unsigned
2227 Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
2228 {
2229   unsigned tie_t = (insn[0] >> 13) & 7;
2230   return tie_t;
2231 }
2232
2233 static void
2234 Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
2235 {
2236   uint32 tie_t = val & 7;
2237   insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
2238 }
2239
2240 static unsigned
2241 Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
2242 {
2243   unsigned tie_t = (insn[0] >> 13) & 7;
2244   return tie_t;
2245 }
2246
2247 static void
2248 Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
2249 {
2250   uint32 tie_t = val & 7;
2251   insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
2252 }
2253
2254 static unsigned
2255 Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
2256 {
2257   unsigned tie_t = (insn[0] >> 17) & 7;
2258   return tie_t;
2259 }
2260
2261 static void
2262 Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
2263 {
2264   uint32 tie_t = val & 7;
2265   insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
2266 }
2267
2268 static unsigned
2269 Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
2270 {
2271   unsigned tie_t = (insn[0] >> 17) & 7;
2272   return tie_t;
2273 }
2274
2275 static void
2276 Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
2277 {
2278   uint32 tie_t = val & 7;
2279   insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
2280 }
2281
2282 static unsigned
2283 Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
2284 {
2285   unsigned tie_t = (insn[0] >> 16) & 0xf;
2286   tie_t = (tie_t << 4) | ((insn[0] >> 8) & 0xf);
2287   return tie_t;
2288 }
2289
2290 static void
2291 Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
2292 {
2293   uint32 tie_t = val & 0xf;
2294   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
2295   tie_t = (val >> 4) & 0xf;
2296   insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
2297 }
2298
2299 static unsigned
2300 Field_op0_s4_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2301 {
2302   unsigned tie_t = (insn[0] >> 18) & 3;
2303   return tie_t;
2304 }
2305
2306 static void
2307 Field_op0_s4_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2308 {
2309   uint32 tie_t = val & 3;
2310   insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
2311 }
2312
2313 static unsigned
2314 Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2315 {
2316   unsigned tie_t = (insn[0] >> 12) & 0xf;
2317   return tie_t;
2318 }
2319
2320 static void
2321 Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2322 {
2323   uint32 tie_t = val & 0xf;
2324   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2325 }
2326
2327 static unsigned
2328 Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2329 {
2330   unsigned tie_t = (insn[0] >> 17) & 1;
2331   return tie_t;
2332 }
2333
2334 static void
2335 Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2336 {
2337   uint32 tie_t = val & 1;
2338   insn[0] = (insn[0] & ~0x20000) | (tie_t << 17);
2339 }
2340
2341 static unsigned
2342 Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2343 {
2344   unsigned tie_t = (insn[0] >> 16) & 3;
2345   return tie_t;
2346 }
2347
2348 static void
2349 Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2350 {
2351   uint32 tie_t = val & 3;
2352   insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
2353 }
2354
2355 static unsigned
2356 Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2357 {
2358   unsigned tie_t = (insn[0] >> 13) & 0x1f;
2359   return tie_t;
2360 }
2361
2362 static void
2363 Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2364 {
2365   uint32 tie_t = val & 0x1f;
2366   insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13);
2367 }
2368
2369 static unsigned
2370 Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2371 {
2372   unsigned tie_t = (insn[0] >> 12) & 0x3f;
2373   return tie_t;
2374 }
2375
2376 static void
2377 Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2378 {
2379   uint32 tie_t = val & 0x3f;
2380   insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2381 }
2382
2383 static unsigned
2384 Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2385 {
2386   unsigned tie_t = (insn[0] >> 12) & 0x3f;
2387   tie_t = (tie_t << 3) | ((insn[0] >> 4) & 7);
2388   return tie_t;
2389 }
2390
2391 static void
2392 Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2393 {
2394   uint32 tie_t = val & 7;
2395   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
2396   tie_t = (val >> 3) & 0x3f;
2397   insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2398 }
2399
2400 static unsigned
2401 Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2402 {
2403   unsigned tie_t = (insn[0] >> 12) & 0x3f;
2404   tie_t = (tie_t << 3) | ((insn[0] >> 4) & 7);
2405   return tie_t;
2406 }
2407
2408 static void
2409 Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2410 {
2411   uint32 tie_t = val & 7;
2412   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
2413   tie_t = (val >> 3) & 0x3f;
2414   insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2415 }
2416
2417 static unsigned
2418 Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2419 {
2420   unsigned tie_t = (insn[0] >> 12) & 0x3f;
2421   tie_t = (tie_t << 2) | ((insn[0] >> 5) & 3);
2422   return tie_t;
2423 }
2424
2425 static void
2426 Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2427 {
2428   uint32 tie_t = val & 3;
2429   insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
2430   tie_t = (val >> 2) & 0x3f;
2431   insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2432 }
2433
2434 static unsigned
2435 Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2436 {
2437   unsigned tie_t = (insn[0] >> 12) & 0x3f;
2438   tie_t = (tie_t << 1) | ((insn[0] >> 6) & 1);
2439   return tie_t;
2440 }
2441
2442 static void
2443 Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2444 {
2445   uint32 tie_t = val & 1;
2446   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
2447   tie_t = (val >> 1) & 0x3f;
2448   insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2449 }
2450
2451 static unsigned
2452 Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2453 {
2454   unsigned tie_t = (insn[0] >> 12) & 0x3f;
2455   tie_t = (tie_t << 2) | ((insn[0] >> 8) & 3);
2456   return tie_t;
2457 }
2458
2459 static void
2460 Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2461 {
2462   uint32 tie_t = val & 3;
2463   insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
2464   tie_t = (val >> 2) & 0x3f;
2465   insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2466 }
2467
2468 static unsigned
2469 Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2470 {
2471   unsigned tie_t = (insn[0] >> 12) & 0x3f;
2472   tie_t = (tie_t << 2) | ((insn[0] >> 8) & 3);
2473   return tie_t;
2474 }
2475
2476 static void
2477 Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2478 {
2479   uint32 tie_t = val & 3;
2480   insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
2481   tie_t = (val >> 2) & 0x3f;
2482   insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2483 }
2484
2485 static unsigned
2486 Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2487 {
2488   unsigned tie_t = (insn[0] >> 12) & 0x3f;
2489   tie_t = (tie_t << 1) | ((insn[0] >> 9) & 1);
2490   return tie_t;
2491 }
2492
2493 static void
2494 Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2495 {
2496   uint32 tie_t = val & 1;
2497   insn[0] = (insn[0] & ~0x200) | (tie_t << 9);
2498   tie_t = (val >> 1) & 0x3f;
2499   insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2500 }
2501
2502 static unsigned
2503 Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2504 {
2505   unsigned tie_t = (insn[0] >> 15) & 7;
2506   return tie_t;
2507 }
2508
2509 static void
2510 Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2511 {
2512   uint32 tie_t = val & 7;
2513   insn[0] = (insn[0] & ~0x38000) | (tie_t << 15);
2514 }
2515
2516 static unsigned
2517 Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2518 {
2519   unsigned tie_t = (insn[0] >> 7) & 1;
2520   return tie_t;
2521 }
2522
2523 static void
2524 Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2525 {
2526   uint32 tie_t = val & 1;
2527   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2528 }
2529
2530 static unsigned
2531 Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2532 {
2533   unsigned tie_t = (insn[0] >> 7) & 1;
2534   tie_t = (tie_t << 4) | (insn[0] & 0xf);
2535   return tie_t;
2536 }
2537
2538 static void
2539 Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2540 {
2541   uint32 tie_t = val & 0xf;
2542   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2543   tie_t = (val >> 4) & 1;
2544   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2545 }
2546
2547 static unsigned
2548 Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2549 {
2550   unsigned tie_t = (insn[0] >> 10) & 3;
2551   return tie_t;
2552 }
2553
2554 static void
2555 Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2556 {
2557   uint32 tie_t = val & 3;
2558   insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
2559 }
2560
2561 static unsigned
2562 Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2563 {
2564   unsigned tie_t = (insn[0] >> 7) & 0x1f;
2565   tie_t = (tie_t << 6) | (insn[0] & 0x3f);
2566   return tie_t;
2567 }
2568
2569 static void
2570 Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2571 {
2572   uint32 tie_t = val & 0x3f;
2573   insn[0] = (insn[0] & ~0x3f) | (tie_t << 0);
2574   tie_t = (val >> 6) & 0x1f;
2575   insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
2576 }
2577
2578 static unsigned
2579 Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2580 {
2581   unsigned tie_t = (insn[0] >> 12) & 1;
2582   tie_t = (tie_t << 4) | (insn[0] & 0xf);
2583   return tie_t;
2584 }
2585
2586 static void
2587 Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2588 {
2589   uint32 tie_t = val & 0xf;
2590   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2591   tie_t = (val >> 4) & 1;
2592   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
2593 }
2594
2595 static unsigned
2596 Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2597 {
2598   unsigned tie_t = (insn[0] >> 10) & 3;
2599   tie_t = (tie_t << 1) | ((insn[0] >> 8) & 1);
2600   return tie_t;
2601 }
2602
2603 static void
2604 Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2605 {
2606   uint32 tie_t = val & 1;
2607   insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
2608   tie_t = (val >> 1) & 3;
2609   insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
2610 }
2611
2612 static unsigned
2613 Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2614 {
2615   unsigned tie_t = (insn[0] >> 7) & 1;
2616   tie_t = (tie_t << 5) | (insn[0] & 0x1f);
2617   return tie_t;
2618 }
2619
2620 static void
2621 Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2622 {
2623   uint32 tie_t = val & 0x1f;
2624   insn[0] = (insn[0] & ~0x1f) | (tie_t << 0);
2625   tie_t = (val >> 5) & 1;
2626   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2627 }
2628
2629 static unsigned
2630 Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2631 {
2632   unsigned tie_t = (insn[0] >> 12) & 7;
2633   return tie_t;
2634 }
2635
2636 static void
2637 Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2638 {
2639   uint32 tie_t = val & 7;
2640   insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
2641 }
2642
2643 static unsigned
2644 Field_op0_s5_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
2645 {
2646   unsigned tie_t = (insn[0] >> 13) & 7;
2647   return tie_t;
2648 }
2649
2650 static void
2651 Field_op0_s5_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
2652 {
2653   uint32 tie_t = val & 7;
2654   insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
2655 }
2656
2657 static unsigned
2658 Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
2659 {
2660   unsigned tie_t = (insn[0] >> 12) & 1;
2661   return tie_t;
2662 }
2663
2664 static void
2665 Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
2666 {
2667   uint32 tie_t = val & 1;
2668   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
2669 }
2670
2671 static unsigned
2672 Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
2673 {
2674   unsigned tie_t = (insn[0] >> 12) & 1;
2675   tie_t = (tie_t << 1) | ((insn[0] >> 7) & 1);
2676   return tie_t;
2677 }
2678
2679 static void
2680 Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
2681 {
2682   uint32 tie_t = val & 1;
2683   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2684   tie_t = (val >> 1) & 1;
2685   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
2686 }
2687
2688 static unsigned
2689 Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
2690 {
2691   unsigned tie_t = (insn[0] >> 12) & 1;
2692   tie_t = (tie_t << 1) | ((insn[0] >> 7) & 1);
2693   tie_t = (tie_t << 1) | ((insn[0] >> 4) & 1);
2694   return tie_t;
2695 }
2696
2697 static void
2698 Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
2699 {
2700   uint32 tie_t = val & 1;
2701   insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
2702   tie_t = (val >> 1) & 1;
2703   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2704   tie_t = (val >> 2) & 1;
2705   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
2706 }
2707
2708 static unsigned
2709 Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
2710 {
2711   unsigned tie_t = (insn[0] >> 12) & 1;
2712   tie_t = (tie_t << 1) | ((insn[0] >> 7) & 1);
2713   tie_t = (tie_t << 1) | ((insn[0] >> 4) & 1);
2714   return tie_t;
2715 }
2716
2717 static void
2718 Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
2719 {
2720   uint32 tie_t = val & 1;
2721   insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
2722   tie_t = (val >> 1) & 1;
2723   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2724   tie_t = (val >> 2) & 1;
2725   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
2726 }
2727
2728 static unsigned
2729 Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
2730 {
2731   unsigned tie_t = (insn[0] >> 12) & 1;
2732   tie_t = (tie_t << 3) | ((insn[0] >> 8) & 7);
2733   return tie_t;
2734 }
2735
2736 static void
2737 Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
2738 {
2739   uint32 tie_t = val & 7;
2740   insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
2741   tie_t = (val >> 3) & 1;
2742   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
2743 }
2744
2745 static unsigned
2746 Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
2747 {
2748   unsigned tie_t = (insn[0] >> 12) & 1;
2749   tie_t = (tie_t << 3) | ((insn[0] >> 8) & 7);
2750   return tie_t;
2751 }
2752
2753 static void
2754 Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
2755 {
2756   uint32 tie_t = val & 7;
2757   insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
2758   tie_t = (val >> 3) & 1;
2759   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
2760 }
2761
2762 static unsigned
2763 Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
2764 {
2765   unsigned tie_t = (insn[0] >> 12) & 1;
2766   tie_t = (tie_t << 2) | ((insn[0] >> 9) & 3);
2767   return tie_t;
2768 }
2769
2770 static void
2771 Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
2772 {
2773   uint32 tie_t = val & 3;
2774   insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
2775   tie_t = (val >> 2) & 1;
2776   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
2777 }
2778
2779 static unsigned
2780 Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
2781 {
2782   unsigned tie_t = (insn[0] >> 12) & 1;
2783   tie_t = (tie_t << 1) | ((insn[0] >> 10) & 1);
2784   return tie_t;
2785 }
2786
2787 static void
2788 Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
2789 {
2790   uint32 tie_t = val & 1;
2791   insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
2792   tie_t = (val >> 1) & 1;
2793   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
2794 }
2795
2796 static unsigned
2797 Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
2798 {
2799   unsigned tie_t = (insn[0] >> 5) & 3;
2800   return tie_t;
2801 }
2802
2803 static void
2804 Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
2805 {
2806   uint32 tie_t = val & 3;
2807   insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
2808 }
2809
2810 static unsigned
2811 Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
2812 {
2813   unsigned tie_t = (insn[0] >> 11) & 1;
2814   return tie_t;
2815 }
2816
2817 static void
2818 Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
2819 {
2820   uint32 tie_t = val & 1;
2821   insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
2822 }
2823
2824 static unsigned
2825 Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
2826 {
2827   unsigned tie_t = (insn[0] >> 8) & 0xf;
2828   tie_t = (tie_t << 2) | ((insn[0] >> 5) & 3);
2829   tie_t = (tie_t << 4) | (insn[0] & 0xf);
2830   return tie_t;
2831 }
2832
2833 static void
2834 Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
2835 {
2836   uint32 tie_t = val & 0xf;
2837   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2838   tie_t = (val >> 4) & 3;
2839   insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
2840   tie_t = (val >> 6) & 0xf;
2841   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
2842 }
2843
2844 static unsigned
2845 Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
2846 {
2847   unsigned tie_t = (insn[0] >> 11) & 1;
2848   tie_t = (tie_t << 1) | ((insn[0] >> 8) & 1);
2849   return tie_t;
2850 }
2851
2852 static void
2853 Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
2854 {
2855   uint32 tie_t = val & 1;
2856   insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
2857   tie_t = (val >> 1) & 1;
2858   insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
2859 }
2860
2861 static unsigned
2862 Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
2863 {
2864   unsigned tie_t = (insn[0] >> 11) & 1;
2865   tie_t = (tie_t << 2) | ((insn[0] >> 8) & 3);
2866   return tie_t;
2867 }
2868
2869 static void
2870 Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
2871 {
2872   uint32 tie_t = val & 3;
2873   insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
2874   tie_t = (val >> 2) & 1;
2875   insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
2876 }
2877
2878 static unsigned
2879 Field_op0_s6_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
2880 {
2881   unsigned tie_t = (insn[0] >> 27) & 0x1f;
2882   return tie_t;
2883 }
2884
2885 static void
2886 Field_op0_s6_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
2887 {
2888   uint32 tie_t = val & 0x1f;
2889   insn[0] = (insn[0] & ~0xf8000000) | (tie_t << 27);
2890 }
2891
2892 static unsigned
2893 Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
2894 {
2895   unsigned tie_t = insn[1] & 7;
2896   tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
2897   tie_t = (tie_t << 4) | (insn[0] & 0xf);
2898   return tie_t;
2899 }
2900
2901 static void
2902 Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
2903 {
2904   uint32 tie_t = val & 0xf;
2905   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2906   tie_t = (val >> 4) & 1;
2907   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
2908   tie_t = (val >> 5) & 7;
2909   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
2910 }
2911
2912 static unsigned
2913 Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
2914 {
2915   unsigned tie_t = insn[1] & 7;
2916   return tie_t;
2917 }
2918
2919 static void
2920 Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
2921 {
2922   uint32 tie_t = val & 7;
2923   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
2924 }
2925
2926 static unsigned
2927 Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
2928 {
2929   unsigned tie_t = insn[1] & 7;
2930   tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
2931   tie_t = (tie_t << 4) | (insn[0] & 0xf);
2932   return tie_t;
2933 }
2934
2935 static void
2936 Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
2937 {
2938   uint32 tie_t = val & 0xf;
2939   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2940   tie_t = (val >> 4) & 1;
2941   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
2942   tie_t = (val >> 5) & 7;
2943   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
2944 }
2945
2946 static unsigned
2947 Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
2948 {
2949   unsigned tie_t = insn[1] & 7;
2950   tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
2951   tie_t = (tie_t << 4) | (insn[0] & 0xf);
2952   return tie_t;
2953 }
2954
2955 static void
2956 Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
2957 {
2958   uint32 tie_t = val & 0xf;
2959   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2960   tie_t = (val >> 4) & 1;
2961   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
2962   tie_t = (val >> 5) & 7;
2963   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
2964 }
2965
2966 static unsigned
2967 Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
2968 {
2969   unsigned tie_t = insn[1] & 7;
2970   tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
2971   tie_t = (tie_t << 4) | (insn[0] & 0xf);
2972   return tie_t;
2973 }
2974
2975 static void
2976 Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
2977 {
2978   uint32 tie_t = val & 0xf;
2979   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2980   tie_t = (val >> 4) & 1;
2981   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
2982   tie_t = (val >> 5) & 7;
2983   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
2984 }
2985
2986 static unsigned
2987 Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
2988 {
2989   unsigned tie_t = insn[1] & 7;
2990   tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
2991   return tie_t;
2992 }
2993
2994 static void
2995 Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
2996 {
2997   uint32 tie_t = val & 1;
2998   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
2999   tie_t = (val >> 1) & 7;
3000   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3001 }
3002
3003 static unsigned
3004 Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3005 {
3006   unsigned tie_t = insn[1] & 7;
3007   tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
3008   return tie_t;
3009 }
3010
3011 static void
3012 Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3013 {
3014   uint32 tie_t = val & 1;
3015   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3016   tie_t = (val >> 1) & 7;
3017   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3018 }
3019
3020 static unsigned
3021 Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3022 {
3023   unsigned tie_t = insn[1] & 7;
3024   tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
3025   return tie_t;
3026 }
3027
3028 static void
3029 Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3030 {
3031   uint32 tie_t = val & 1;
3032   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3033   tie_t = (val >> 1) & 7;
3034   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3035 }
3036
3037 static unsigned
3038 Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3039 {
3040   unsigned tie_t = insn[1] & 7;
3041   tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
3042   return tie_t;
3043 }
3044
3045 static void
3046 Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3047 {
3048   uint32 tie_t = val & 1;
3049   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3050   tie_t = (val >> 1) & 7;
3051   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3052 }
3053
3054 static unsigned
3055 Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3056 {
3057   unsigned tie_t = insn[1] & 7;
3058   tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
3059   return tie_t;
3060 }
3061
3062 static void
3063 Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3064 {
3065   uint32 tie_t = val & 1;
3066   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3067   tie_t = (val >> 1) & 7;
3068   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3069 }
3070
3071 static unsigned
3072 Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3073 {
3074   unsigned tie_t = insn[1] & 7;
3075   tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
3076   return tie_t;
3077 }
3078
3079 static void
3080 Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3081 {
3082   uint32 tie_t = val & 1;
3083   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3084   tie_t = (val >> 1) & 7;
3085   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3086 }
3087
3088 static unsigned
3089 Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3090 {
3091   unsigned tie_t = insn[1] & 7;
3092   tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
3093   return tie_t;
3094 }
3095
3096 static void
3097 Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3098 {
3099   uint32 tie_t = val & 1;
3100   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3101   tie_t = (val >> 1) & 7;
3102   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3103 }
3104
3105 static unsigned
3106 Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3107 {
3108   unsigned tie_t = insn[1] & 7;
3109   tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
3110   return tie_t;
3111 }
3112
3113 static void
3114 Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3115 {
3116   uint32 tie_t = val & 1;
3117   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3118   tie_t = (val >> 1) & 7;
3119   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3120 }
3121
3122 static unsigned
3123 Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3124 {
3125   unsigned tie_t = insn[1] & 7;
3126   tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
3127   return tie_t;
3128 }
3129
3130 static void
3131 Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3132 {
3133   uint32 tie_t = val & 1;
3134   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3135   tie_t = (val >> 1) & 7;
3136   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3137 }
3138
3139 static unsigned
3140 Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3141 {
3142   unsigned tie_t = insn[1] & 7;
3143   tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
3144   return tie_t;
3145 }
3146
3147 static void
3148 Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3149 {
3150   uint32 tie_t = val & 1;
3151   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3152   tie_t = (val >> 1) & 7;
3153   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3154 }
3155
3156 static unsigned
3157 Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3158 {
3159   unsigned tie_t = insn[1] & 7;
3160   tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
3161   return tie_t;
3162 }
3163
3164 static void
3165 Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3166 {
3167   uint32 tie_t = val & 1;
3168   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3169   tie_t = (val >> 1) & 7;
3170   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3171 }
3172
3173 static unsigned
3174 Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3175 {
3176   unsigned tie_t = insn[1] & 7;
3177   tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
3178   return tie_t;
3179 }
3180
3181 static void
3182 Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3183 {
3184   uint32 tie_t = val & 1;
3185   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3186   tie_t = (val >> 1) & 7;
3187   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3188 }
3189
3190 static unsigned
3191 Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3192 {
3193   unsigned tie_t = insn[1] & 7;
3194   tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
3195   return tie_t;
3196 }
3197
3198 static void
3199 Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3200 {
3201   uint32 tie_t = val & 1;
3202   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3203   tie_t = (val >> 1) & 7;
3204   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3205 }
3206
3207 static unsigned
3208 Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3209 {
3210   unsigned tie_t = insn[1] & 7;
3211   tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
3212   return tie_t;
3213 }
3214
3215 static void
3216 Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3217 {
3218   uint32 tie_t = val & 1;
3219   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3220   tie_t = (val >> 1) & 7;
3221   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3222 }
3223
3224 static unsigned
3225 Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3226 {
3227   unsigned tie_t = insn[1] & 7;
3228   tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
3229   return tie_t;
3230 }
3231
3232 static void
3233 Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3234 {
3235   uint32 tie_t = val & 1;
3236   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3237   tie_t = (val >> 1) & 7;
3238   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3239 }
3240
3241 static unsigned
3242 Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3243 {
3244   unsigned tie_t = insn[1] & 7;
3245   tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
3246   return tie_t;
3247 }
3248
3249 static void
3250 Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3251 {
3252   uint32 tie_t = val & 1;
3253   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3254   tie_t = (val >> 1) & 7;
3255   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3256 }
3257
3258 static unsigned
3259 Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3260 {
3261   unsigned tie_t = insn[1] & 7;
3262   tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
3263   return tie_t;
3264 }
3265
3266 static void
3267 Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3268 {
3269   uint32 tie_t = val & 1;
3270   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3271   tie_t = (val >> 1) & 7;
3272   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3273 }
3274
3275 static unsigned
3276 Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3277 {
3278   unsigned tie_t = insn[1] & 7;
3279   tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
3280   return tie_t;
3281 }
3282
3283 static void
3284 Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3285 {
3286   uint32 tie_t = val & 1;
3287   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3288   tie_t = (val >> 1) & 7;
3289   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3290 }
3291
3292 static unsigned
3293 Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3294 {
3295   unsigned tie_t = insn[1] & 7;
3296   tie_t = (tie_t << 27) | (insn[0] & 0x7ffffff);
3297   return tie_t;
3298 }
3299
3300 static void
3301 Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3302 {
3303   uint32 tie_t;
3304   tie_t = val & 0x7ffffff;
3305   insn[0] = (insn[0] & ~0x7ffffff) | (tie_t << 0);
3306   tie_t = (val >> 27) & 7;
3307   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3308 }
3309
3310 static unsigned
3311 Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
3312 {
3313   unsigned tie_t = (insn[0] >> 20) & 0xf;
3314   return tie_t;
3315 }
3316
3317 static void
3318 Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
3319 {
3320   uint32 tie_t = val & 0xf;
3321   insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
3322 }
3323
3324 static void
3325 Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
3326                     uint32 val ATTRIBUTE_UNUSED)
3327 {
3328   /* Do nothing.  */
3329 }
3330
3331 static unsigned
3332 Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3333 {
3334   return 0;
3335 }
3336
3337 static unsigned
3338 Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3339 {
3340   return 4;
3341 }
3342
3343 static unsigned
3344 Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3345 {
3346   return 8;
3347 }
3348
3349 static unsigned
3350 Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3351 {
3352   return 12;
3353 }
3354
3355 static unsigned
3356 Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3357 {
3358   return 0;
3359 }
3360
3361 static unsigned
3362 Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3363 {
3364   return 1;
3365 }
3366
3367 static unsigned
3368 Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3369 {
3370   return 2;
3371 }
3372
3373 static unsigned
3374 Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3375 {
3376   return 3;
3377 }
3378
3379 static unsigned
3380 Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3381 {
3382   return 0;
3383 }
3384
3385 static unsigned
3386 Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3387 {
3388   return 0;
3389 }
3390
3391 static unsigned
3392 Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3393 {
3394   return 0;
3395 }
3396
3397 static unsigned
3398 Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3399 {
3400   return 0;
3401 }
3402
3403 \f
3404 /* Functional units.  */
3405
3406 static xtensa_funcUnit_internal funcUnits[] = {
3407
3408 };
3409
3410 \f
3411 /* Register files.  */
3412
3413 static xtensa_regfile_internal regfiles[] = {
3414   { "AR", "a", 0, 32, 64 },
3415   { "MR", "m", 1, 32, 4 },
3416   { "BR", "b", 2, 1, 16 },
3417   { "FR", "f", 3, 32, 16 },
3418   { "BR2", "b", 2, 2, 8 },
3419   { "BR4", "b", 2, 4, 4 },
3420   { "BR8", "b", 2, 8, 2 },
3421   { "BR16", "b", 2, 16, 1 }
3422 };
3423
3424 \f
3425 /* Interfaces.  */
3426
3427 static xtensa_interface_internal interfaces[] = {
3428
3429 };
3430
3431 \f
3432 /* Constant tables.  */
3433
3434 /* constant table ai4c */
3435 static const unsigned CONST_TBL_ai4c_0[] = {
3436   0xffffffff,
3437   0x1,
3438   0x2,
3439   0x3,
3440   0x4,
3441   0x5,
3442   0x6,
3443   0x7,
3444   0x8,
3445   0x9,
3446   0xa,
3447   0xb,
3448   0xc,
3449   0xd,
3450   0xe,
3451   0xf,
3452   0
3453 };
3454
3455 /* constant table b4c */
3456 static const unsigned CONST_TBL_b4c_0[] = {
3457   0xffffffff,
3458   0x1,
3459   0x2,
3460   0x3,
3461   0x4,
3462   0x5,
3463   0x6,
3464   0x7,
3465   0x8,
3466   0xa,
3467   0xc,
3468   0x10,
3469   0x20,
3470   0x40,
3471   0x80,
3472   0x100,
3473   0
3474 };
3475
3476 /* constant table b4cu */
3477 static const unsigned CONST_TBL_b4cu_0[] = {
3478   0x8000,
3479   0x10000,
3480   0x2,
3481   0x3,
3482   0x4,
3483   0x5,
3484   0x6,
3485   0x7,
3486   0x8,
3487   0xa,
3488   0xc,
3489   0x10,
3490   0x20,
3491   0x40,
3492   0x80,
3493   0x100,
3494   0
3495 };
3496
3497 \f
3498 /* Instruction operands.  */
3499
3500 static int
3501 Operand_soffsetx4_decode (uint32 *valp)
3502 {
3503   unsigned soffsetx4_0, offset_0;
3504   offset_0 = *valp & 0x3ffff;
3505   soffsetx4_0 = 0x4 + (((offset_0 ^ 0x20000) - 0x20000) << 2);
3506   *valp = soffsetx4_0;
3507   return 0;
3508 }
3509
3510 static int
3511 Operand_soffsetx4_encode (uint32 *valp)
3512 {
3513   unsigned offset_0, soffsetx4_0;
3514   soffsetx4_0 = *valp;
3515   offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
3516   *valp = offset_0;
3517   return 0;
3518 }
3519
3520 static int
3521 Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
3522 {
3523   *valp -= (pc & ~0x3);
3524   return 0;
3525 }
3526
3527 static int
3528 Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
3529 {
3530   *valp += (pc & ~0x3);
3531   return 0;
3532 }
3533
3534 static int
3535 Operand_uimm12x8_decode (uint32 *valp)
3536 {
3537   unsigned uimm12x8_0, imm12_0;
3538   imm12_0 = *valp & 0xfff;
3539   uimm12x8_0 = imm12_0 << 3;
3540   *valp = uimm12x8_0;
3541   return 0;
3542 }
3543
3544 static int
3545 Operand_uimm12x8_encode (uint32 *valp)
3546 {
3547   unsigned imm12_0, uimm12x8_0;
3548   uimm12x8_0 = *valp;
3549   imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
3550   *valp = imm12_0;
3551   return 0;
3552 }
3553
3554 static int
3555 Operand_simm4_decode (uint32 *valp)
3556 {
3557   unsigned simm4_0, mn_0;
3558   mn_0 = *valp & 0xf;
3559   simm4_0 = (mn_0 ^ 0x8) - 0x8;
3560   *valp = simm4_0;
3561   return 0;
3562 }
3563
3564 static int
3565 Operand_simm4_encode (uint32 *valp)
3566 {
3567   unsigned mn_0, simm4_0;
3568   simm4_0 = *valp;
3569   mn_0 = (simm4_0 & 0xf);
3570   *valp = mn_0;
3571   return 0;
3572 }
3573
3574 static int
3575 Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
3576 {
3577   return 0;
3578 }
3579
3580 static int
3581 Operand_arr_encode (uint32 *valp)
3582 {
3583   int error;
3584   error = (*valp & ~0xf) != 0;
3585   return error;
3586 }
3587
3588 static int
3589 Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
3590 {
3591   return 0;
3592 }
3593
3594 static int
3595 Operand_ars_encode (uint32 *valp)
3596 {
3597   int error;
3598   error = (*valp & ~0xf) != 0;
3599   return error;
3600 }
3601
3602 static int
3603 Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
3604 {
3605   return 0;
3606 }
3607
3608 static int
3609 Operand_art_encode (uint32 *valp)
3610 {
3611   int error;
3612   error = (*valp & ~0xf) != 0;
3613   return error;
3614 }
3615
3616 static int
3617 Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
3618 {
3619   return 0;
3620 }
3621
3622 static int
3623 Operand_ar0_encode (uint32 *valp)
3624 {
3625   int error;
3626   error = (*valp & ~0x3f) != 0;
3627   return error;
3628 }
3629
3630 static int
3631 Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
3632 {
3633   return 0;
3634 }
3635
3636 static int
3637 Operand_ar4_encode (uint32 *valp)
3638 {
3639   int error;
3640   error = (*valp & ~0x3f) != 0;
3641   return error;
3642 }
3643
3644 static int
3645 Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
3646 {
3647   return 0;
3648 }
3649
3650 static int
3651 Operand_ar8_encode (uint32 *valp)
3652 {
3653   int error;
3654   error = (*valp & ~0x3f) != 0;
3655   return error;
3656 }
3657
3658 static int
3659 Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
3660 {
3661   return 0;
3662 }
3663
3664 static int
3665 Operand_ar12_encode (uint32 *valp)
3666 {
3667   int error;
3668   error = (*valp & ~0x3f) != 0;
3669   return error;
3670 }
3671
3672 static int
3673 Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
3674 {
3675   return 0;
3676 }
3677
3678 static int
3679 Operand_ars_entry_encode (uint32 *valp)
3680 {
3681   int error;
3682   error = (*valp & ~0x3f) != 0;
3683   return error;
3684 }
3685
3686 static int
3687 Operand_immrx4_decode (uint32 *valp)
3688 {
3689   unsigned immrx4_0, r_0;
3690   r_0 = *valp & 0xf;
3691   immrx4_0 = (0xfffffff0 | r_0) << 2;
3692   *valp = immrx4_0;
3693   return 0;
3694 }
3695
3696 static int
3697 Operand_immrx4_encode (uint32 *valp)
3698 {
3699   unsigned r_0, immrx4_0;
3700   immrx4_0 = *valp;
3701   r_0 = ((immrx4_0 >> 2) & 0xf);
3702   *valp = r_0;
3703   return 0;
3704 }
3705
3706 static int
3707 Operand_lsi4x4_decode (uint32 *valp)
3708 {
3709   unsigned lsi4x4_0, r_0;
3710   r_0 = *valp & 0xf;
3711   lsi4x4_0 = r_0 << 2;
3712   *valp = lsi4x4_0;
3713   return 0;
3714 }
3715
3716 static int
3717 Operand_lsi4x4_encode (uint32 *valp)
3718 {
3719   unsigned r_0, lsi4x4_0;
3720   lsi4x4_0 = *valp;
3721   r_0 = ((lsi4x4_0 >> 2) & 0xf);
3722   *valp = r_0;
3723   return 0;
3724 }
3725
3726 static int
3727 Operand_simm7_decode (uint32 *valp)
3728 {
3729   unsigned simm7_0, imm7_0;
3730   imm7_0 = *valp & 0x7f;
3731   simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
3732   *valp = simm7_0;
3733   return 0;
3734 }
3735
3736 static int
3737 Operand_simm7_encode (uint32 *valp)
3738 {
3739   unsigned imm7_0, simm7_0;
3740   simm7_0 = *valp;
3741   imm7_0 = (simm7_0 & 0x7f);
3742   *valp = imm7_0;
3743   return 0;
3744 }
3745
3746 static int
3747 Operand_uimm6_decode (uint32 *valp)
3748 {
3749   unsigned uimm6_0, imm6_0;
3750   imm6_0 = *valp & 0x3f;
3751   uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
3752   *valp = uimm6_0;
3753   return 0;
3754 }
3755
3756 static int
3757 Operand_uimm6_encode (uint32 *valp)
3758 {
3759   unsigned imm6_0, uimm6_0;
3760   uimm6_0 = *valp;
3761   imm6_0 = (uimm6_0 - 0x4) & 0x3f;
3762   *valp = imm6_0;
3763   return 0;
3764 }
3765
3766 static int
3767 Operand_uimm6_ator (uint32 *valp, uint32 pc)
3768 {
3769   *valp -= pc;
3770   return 0;
3771 }
3772
3773 static int
3774 Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
3775 {
3776   *valp += pc;
3777   return 0;
3778 }
3779
3780 static int
3781 Operand_ai4const_decode (uint32 *valp)
3782 {
3783   unsigned ai4const_0, t_0;
3784   t_0 = *valp & 0xf;
3785   ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
3786   *valp = ai4const_0;
3787   return 0;
3788 }
3789
3790 static int
3791 Operand_ai4const_encode (uint32 *valp)
3792 {
3793   unsigned t_0, ai4const_0;
3794   ai4const_0 = *valp;
3795   switch (ai4const_0)
3796     {
3797     case 0xffffffff: t_0 = 0; break;
3798     case 0x1: t_0 = 0x1; break;
3799     case 0x2: t_0 = 0x2; break;
3800     case 0x3: t_0 = 0x3; break;
3801     case 0x4: t_0 = 0x4; break;
3802     case 0x5: t_0 = 0x5; break;
3803     case 0x6: t_0 = 0x6; break;
3804     case 0x7: t_0 = 0x7; break;
3805     case 0x8: t_0 = 0x8; break;
3806     case 0x9: t_0 = 0x9; break;
3807     case 0xa: t_0 = 0xa; break;
3808     case 0xb: t_0 = 0xb; break;
3809     case 0xc: t_0 = 0xc; break;
3810     case 0xd: t_0 = 0xd; break;
3811     case 0xe: t_0 = 0xe; break;
3812     default: t_0 = 0xf; break;
3813     }
3814   *valp = t_0;
3815   return 0;
3816 }
3817
3818 static int
3819 Operand_b4const_decode (uint32 *valp)
3820 {
3821   unsigned b4const_0, r_0;
3822   r_0 = *valp & 0xf;
3823   b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
3824   *valp = b4const_0;
3825   return 0;
3826 }
3827
3828 static int
3829 Operand_b4const_encode (uint32 *valp)
3830 {
3831   unsigned r_0, b4const_0;
3832   b4const_0 = *valp;
3833   switch (b4const_0)
3834     {
3835     case 0xffffffff: r_0 = 0; break;
3836     case 0x1: r_0 = 0x1; break;
3837     case 0x2: r_0 = 0x2; break;
3838     case 0x3: r_0 = 0x3; break;
3839     case 0x4: r_0 = 0x4; break;
3840     case 0x5: r_0 = 0x5; break;
3841     case 0x6: r_0 = 0x6; break;
3842     case 0x7: r_0 = 0x7; break;
3843     case 0x8: r_0 = 0x8; break;
3844     case 0xa: r_0 = 0x9; break;
3845     case 0xc: r_0 = 0xa; break;
3846     case 0x10: r_0 = 0xb; break;
3847     case 0x20: r_0 = 0xc; break;
3848     case 0x40: r_0 = 0xd; break;
3849     case 0x80: r_0 = 0xe; break;
3850     default: r_0 = 0xf; break;
3851     }
3852   *valp = r_0;
3853   return 0;
3854 }
3855
3856 static int
3857 Operand_b4constu_decode (uint32 *valp)
3858 {
3859   unsigned b4constu_0, r_0;
3860   r_0 = *valp & 0xf;
3861   b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
3862   *valp = b4constu_0;
3863   return 0;
3864 }
3865
3866 static int
3867 Operand_b4constu_encode (uint32 *valp)
3868 {
3869   unsigned r_0, b4constu_0;
3870   b4constu_0 = *valp;
3871   switch (b4constu_0)
3872     {
3873     case 0x8000: r_0 = 0; break;
3874     case 0x10000: r_0 = 0x1; break;
3875     case 0x2: r_0 = 0x2; break;
3876     case 0x3: r_0 = 0x3; break;
3877     case 0x4: r_0 = 0x4; break;
3878     case 0x5: r_0 = 0x5; break;
3879     case 0x6: r_0 = 0x6; break;
3880     case 0x7: r_0 = 0x7; break;
3881     case 0x8: r_0 = 0x8; break;
3882     case 0xa: r_0 = 0x9; break;
3883     case 0xc: r_0 = 0xa; break;
3884     case 0x10: r_0 = 0xb; break;
3885     case 0x20: r_0 = 0xc; break;
3886     case 0x40: r_0 = 0xd; break;
3887     case 0x80: r_0 = 0xe; break;
3888     default: r_0 = 0xf; break;
3889     }
3890   *valp = r_0;
3891   return 0;
3892 }
3893
3894 static int
3895 Operand_uimm8_decode (uint32 *valp)
3896 {
3897   unsigned uimm8_0, imm8_0;
3898   imm8_0 = *valp & 0xff;
3899   uimm8_0 = imm8_0;
3900   *valp = uimm8_0;
3901   return 0;
3902 }
3903
3904 static int
3905 Operand_uimm8_encode (uint32 *valp)
3906 {
3907   unsigned imm8_0, uimm8_0;
3908   uimm8_0 = *valp;
3909   imm8_0 = (uimm8_0 & 0xff);
3910   *valp = imm8_0;
3911   return 0;
3912 }
3913
3914 static int
3915 Operand_uimm8x2_decode (uint32 *valp)
3916 {
3917   unsigned uimm8x2_0, imm8_0;
3918   imm8_0 = *valp & 0xff;
3919   uimm8x2_0 = imm8_0 << 1;
3920   *valp = uimm8x2_0;
3921   return 0;
3922 }
3923
3924 static int
3925 Operand_uimm8x2_encode (uint32 *valp)
3926 {
3927   unsigned imm8_0, uimm8x2_0;
3928   uimm8x2_0 = *valp;
3929   imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
3930   *valp = imm8_0;
3931   return 0;
3932 }
3933
3934 static int
3935 Operand_uimm8x4_decode (uint32 *valp)
3936 {
3937   unsigned uimm8x4_0, imm8_0;
3938   imm8_0 = *valp & 0xff;
3939   uimm8x4_0 = imm8_0 << 2;
3940   *valp = uimm8x4_0;
3941   return 0;
3942 }
3943
3944 static int
3945 Operand_uimm8x4_encode (uint32 *valp)
3946 {
3947   unsigned imm8_0, uimm8x4_0;
3948   uimm8x4_0 = *valp;
3949   imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
3950   *valp = imm8_0;
3951   return 0;
3952 }
3953
3954 static int
3955 Operand_uimm4x16_decode (uint32 *valp)
3956 {
3957   unsigned uimm4x16_0, op2_0;
3958   op2_0 = *valp & 0xf;
3959   uimm4x16_0 = op2_0 << 4;
3960   *valp = uimm4x16_0;
3961   return 0;
3962 }
3963
3964 static int
3965 Operand_uimm4x16_encode (uint32 *valp)
3966 {
3967   unsigned op2_0, uimm4x16_0;
3968   uimm4x16_0 = *valp;
3969   op2_0 = ((uimm4x16_0 >> 4) & 0xf);
3970   *valp = op2_0;
3971   return 0;
3972 }
3973
3974 static int
3975 Operand_simm8_decode (uint32 *valp)
3976 {
3977   unsigned simm8_0, imm8_0;
3978   imm8_0 = *valp & 0xff;
3979   simm8_0 = (imm8_0 ^ 0x80) - 0x80;
3980   *valp = simm8_0;
3981   return 0;
3982 }
3983
3984 static int
3985 Operand_simm8_encode (uint32 *valp)
3986 {
3987   unsigned imm8_0, simm8_0;
3988   simm8_0 = *valp;
3989   imm8_0 = (simm8_0 & 0xff);
3990   *valp = imm8_0;
3991   return 0;
3992 }
3993
3994 static int
3995 Operand_simm8x256_decode (uint32 *valp)
3996 {
3997   unsigned simm8x256_0, imm8_0;
3998   imm8_0 = *valp & 0xff;
3999   simm8x256_0 = ((imm8_0 ^ 0x80) - 0x80) << 8;
4000   *valp = simm8x256_0;
4001   return 0;
4002 }
4003
4004 static int
4005 Operand_simm8x256_encode (uint32 *valp)
4006 {
4007   unsigned imm8_0, simm8x256_0;
4008   simm8x256_0 = *valp;
4009   imm8_0 = ((simm8x256_0 >> 8) & 0xff);
4010   *valp = imm8_0;
4011   return 0;
4012 }
4013
4014 static int
4015 Operand_simm12b_decode (uint32 *valp)
4016 {
4017   unsigned simm12b_0, imm12b_0;
4018   imm12b_0 = *valp & 0xfff;
4019   simm12b_0 = (imm12b_0 ^ 0x800) - 0x800;
4020   *valp = simm12b_0;
4021   return 0;
4022 }
4023
4024 static int
4025 Operand_simm12b_encode (uint32 *valp)
4026 {
4027   unsigned imm12b_0, simm12b_0;
4028   simm12b_0 = *valp;
4029   imm12b_0 = (simm12b_0 & 0xfff);
4030   *valp = imm12b_0;
4031   return 0;
4032 }
4033
4034 static int
4035 Operand_msalp32_decode (uint32 *valp)
4036 {
4037   unsigned msalp32_0, sal_0;
4038   sal_0 = *valp & 0x1f;
4039   msalp32_0 = 0x20 - sal_0;
4040   *valp = msalp32_0;
4041   return 0;
4042 }
4043
4044 static int
4045 Operand_msalp32_encode (uint32 *valp)
4046 {
4047   unsigned sal_0, msalp32_0;
4048   msalp32_0 = *valp;
4049   sal_0 = (0x20 - msalp32_0) & 0x1f;
4050   *valp = sal_0;
4051   return 0;
4052 }
4053
4054 static int
4055 Operand_op2p1_decode (uint32 *valp)
4056 {
4057   unsigned op2p1_0, op2_0;
4058   op2_0 = *valp & 0xf;
4059   op2p1_0 = op2_0 + 0x1;
4060   *valp = op2p1_0;
4061   return 0;
4062 }
4063
4064 static int
4065 Operand_op2p1_encode (uint32 *valp)
4066 {
4067   unsigned op2_0, op2p1_0;
4068   op2p1_0 = *valp;
4069   op2_0 = (op2p1_0 - 0x1) & 0xf;
4070   *valp = op2_0;
4071   return 0;
4072 }
4073
4074 static int
4075 Operand_label8_decode (uint32 *valp)
4076 {
4077   unsigned label8_0, imm8_0;
4078   imm8_0 = *valp & 0xff;
4079   label8_0 = 0x4 + ((imm8_0 ^ 0x80) - 0x80);
4080   *valp = label8_0;
4081   return 0;
4082 }
4083
4084 static int
4085 Operand_label8_encode (uint32 *valp)
4086 {
4087   unsigned imm8_0, label8_0;
4088   label8_0 = *valp;
4089   imm8_0 = (label8_0 - 0x4) & 0xff;
4090   *valp = imm8_0;
4091   return 0;
4092 }
4093
4094 static int
4095 Operand_label8_ator (uint32 *valp, uint32 pc)
4096 {
4097   *valp -= pc;
4098   return 0;
4099 }
4100
4101 static int
4102 Operand_label8_rtoa (uint32 *valp, uint32 pc)
4103 {
4104   *valp += pc;
4105   return 0;
4106 }
4107
4108 static int
4109 Operand_ulabel8_decode (uint32 *valp)
4110 {
4111   unsigned ulabel8_0, imm8_0;
4112   imm8_0 = *valp & 0xff;
4113   ulabel8_0 = 0x4 + (((0) << 8) | imm8_0);
4114   *valp = ulabel8_0;
4115   return 0;
4116 }
4117
4118 static int
4119 Operand_ulabel8_encode (uint32 *valp)
4120 {
4121   unsigned imm8_0, ulabel8_0;
4122   ulabel8_0 = *valp;
4123   imm8_0 = (ulabel8_0 - 0x4) & 0xff;
4124   *valp = imm8_0;
4125   return 0;
4126 }
4127
4128 static int
4129 Operand_ulabel8_ator (uint32 *valp, uint32 pc)
4130 {
4131   *valp -= pc;
4132   return 0;
4133 }
4134
4135 static int
4136 Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
4137 {
4138   *valp += pc;
4139   return 0;
4140 }
4141
4142 static int
4143 Operand_label12_decode (uint32 *valp)
4144 {
4145   unsigned label12_0, imm12_0;
4146   imm12_0 = *valp & 0xfff;
4147   label12_0 = 0x4 + ((imm12_0 ^ 0x800) - 0x800);
4148   *valp = label12_0;
4149   return 0;
4150 }
4151
4152 static int
4153 Operand_label12_encode (uint32 *valp)
4154 {
4155   unsigned imm12_0, label12_0;
4156   label12_0 = *valp;
4157   imm12_0 = (label12_0 - 0x4) & 0xfff;
4158   *valp = imm12_0;
4159   return 0;
4160 }
4161
4162 static int
4163 Operand_label12_ator (uint32 *valp, uint32 pc)
4164 {
4165   *valp -= pc;
4166   return 0;
4167 }
4168
4169 static int
4170 Operand_label12_rtoa (uint32 *valp, uint32 pc)
4171 {
4172   *valp += pc;
4173   return 0;
4174 }
4175
4176 static int
4177 Operand_soffset_decode (uint32 *valp)
4178 {
4179   unsigned soffset_0, offset_0;
4180   offset_0 = *valp & 0x3ffff;
4181   soffset_0 = 0x4 + ((offset_0 ^ 0x20000) - 0x20000);
4182   *valp = soffset_0;
4183   return 0;
4184 }
4185
4186 static int
4187 Operand_soffset_encode (uint32 *valp)
4188 {
4189   unsigned offset_0, soffset_0;
4190   soffset_0 = *valp;
4191   offset_0 = (soffset_0 - 0x4) & 0x3ffff;
4192   *valp = offset_0;
4193   return 0;
4194 }
4195
4196 static int
4197 Operand_soffset_ator (uint32 *valp, uint32 pc)
4198 {
4199   *valp -= pc;
4200   return 0;
4201 }
4202
4203 static int
4204 Operand_soffset_rtoa (uint32 *valp, uint32 pc)
4205 {
4206   *valp += pc;
4207   return 0;
4208 }
4209
4210 static int
4211 Operand_uimm16x4_decode (uint32 *valp)
4212 {
4213   unsigned uimm16x4_0, imm16_0;
4214   imm16_0 = *valp & 0xffff;
4215   uimm16x4_0 = (0xffff0000 | imm16_0) << 2;
4216   *valp = uimm16x4_0;
4217   return 0;
4218 }
4219
4220 static int
4221 Operand_uimm16x4_encode (uint32 *valp)
4222 {
4223   unsigned imm16_0, uimm16x4_0;
4224   uimm16x4_0 = *valp;
4225   imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
4226   *valp = imm16_0;
4227   return 0;
4228 }
4229
4230 static int
4231 Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
4232 {
4233   *valp -= ((pc + 3) & ~0x3);
4234   return 0;
4235 }
4236
4237 static int
4238 Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
4239 {
4240   *valp += ((pc + 3) & ~0x3);
4241   return 0;
4242 }
4243
4244 static int
4245 Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED)
4246 {
4247   return 0;
4248 }
4249
4250 static int
4251 Operand_mx_encode (uint32 *valp)
4252 {
4253   int error;
4254   error = (*valp & ~0x3) != 0;
4255   return error;
4256 }
4257
4258 static int
4259 Operand_my_decode (uint32 *valp)
4260 {
4261   *valp += 2;
4262   return 0;
4263 }
4264
4265 static int
4266 Operand_my_encode (uint32 *valp)
4267 {
4268   int error;
4269   error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
4270   *valp = *valp & 1;
4271   return error;
4272 }
4273
4274 static int
4275 Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED)
4276 {
4277   return 0;
4278 }
4279
4280 static int
4281 Operand_mw_encode (uint32 *valp)
4282 {
4283   int error;
4284   error = (*valp & ~0x3) != 0;
4285   return error;
4286 }
4287
4288 static int
4289 Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED)
4290 {
4291   return 0;
4292 }
4293
4294 static int
4295 Operand_mr0_encode (uint32 *valp)
4296 {
4297   int error;
4298   error = (*valp & ~0x3) != 0;
4299   return error;
4300 }
4301
4302 static int
4303 Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED)
4304 {
4305   return 0;
4306 }
4307
4308 static int
4309 Operand_mr1_encode (uint32 *valp)
4310 {
4311   int error;
4312   error = (*valp & ~0x3) != 0;
4313   return error;
4314 }
4315
4316 static int
4317 Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED)
4318 {
4319   return 0;
4320 }
4321
4322 static int
4323 Operand_mr2_encode (uint32 *valp)
4324 {
4325   int error;
4326   error = (*valp & ~0x3) != 0;
4327   return error;
4328 }
4329
4330 static int
4331 Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED)
4332 {
4333   return 0;
4334 }
4335
4336 static int
4337 Operand_mr3_encode (uint32 *valp)
4338 {
4339   int error;
4340   error = (*valp & ~0x3) != 0;
4341   return error;
4342 }
4343
4344 static int
4345 Operand_immt_decode (uint32 *valp)
4346 {
4347   unsigned immt_0, t_0;
4348   t_0 = *valp & 0xf;
4349   immt_0 = t_0;
4350   *valp = immt_0;
4351   return 0;
4352 }
4353
4354 static int
4355 Operand_immt_encode (uint32 *valp)
4356 {
4357   unsigned t_0, immt_0;
4358   immt_0 = *valp;
4359   t_0 = immt_0 & 0xf;
4360   *valp = t_0;
4361   return 0;
4362 }
4363
4364 static int
4365 Operand_imms_decode (uint32 *valp)
4366 {
4367   unsigned imms_0, s_0;
4368   s_0 = *valp & 0xf;
4369   imms_0 = s_0;
4370   *valp = imms_0;
4371   return 0;
4372 }
4373
4374 static int
4375 Operand_imms_encode (uint32 *valp)
4376 {
4377   unsigned s_0, imms_0;
4378   imms_0 = *valp;
4379   s_0 = imms_0 & 0xf;
4380   *valp = s_0;
4381   return 0;
4382 }
4383
4384 static int
4385 Operand_bt_decode (uint32 *valp ATTRIBUTE_UNUSED)
4386 {
4387   return 0;
4388 }
4389
4390 static int
4391 Operand_bt_encode (uint32 *valp)
4392 {
4393   int error;
4394   error = (*valp & ~0xf) != 0;
4395   return error;
4396 }
4397
4398 static int
4399 Operand_bs_decode (uint32 *valp ATTRIBUTE_UNUSED)
4400 {
4401   return 0;
4402 }
4403
4404 static int
4405 Operand_bs_encode (uint32 *valp)
4406 {
4407   int error;
4408   error = (*valp & ~0xf) != 0;
4409   return error;
4410 }
4411
4412 static int
4413 Operand_br_decode (uint32 *valp ATTRIBUTE_UNUSED)
4414 {
4415   return 0;
4416 }
4417
4418 static int
4419 Operand_br_encode (uint32 *valp)
4420 {
4421   int error;
4422   error = (*valp & ~0xf) != 0;
4423   return error;
4424 }
4425
4426 static int
4427 Operand_bt2_decode (uint32 *valp)
4428 {
4429   *valp = *valp << 1;
4430   return 0;
4431 }
4432
4433 static int
4434 Operand_bt2_encode (uint32 *valp)
4435 {
4436   int error;
4437   error = (*valp & ~(0x7 << 1)) != 0;
4438   *valp = *valp >> 1;
4439   return error;
4440 }
4441
4442 static int
4443 Operand_bs2_decode (uint32 *valp)
4444 {
4445   *valp = *valp << 1;
4446   return 0;
4447 }
4448
4449 static int
4450 Operand_bs2_encode (uint32 *valp)
4451 {
4452   int error;
4453   error = (*valp & ~(0x7 << 1)) != 0;
4454   *valp = *valp >> 1;
4455   return error;
4456 }
4457
4458 static int
4459 Operand_br2_decode (uint32 *valp)
4460 {
4461   *valp = *valp << 1;
4462   return 0;
4463 }
4464
4465 static int
4466 Operand_br2_encode (uint32 *valp)
4467 {
4468   int error;
4469   error = (*valp & ~(0x7 << 1)) != 0;
4470   *valp = *valp >> 1;
4471   return error;
4472 }
4473
4474 static int
4475 Operand_bt4_decode (uint32 *valp)
4476 {
4477   *valp = *valp << 2;
4478   return 0;
4479 }
4480
4481 static int
4482 Operand_bt4_encode (uint32 *valp)
4483 {
4484   int error;
4485   error = (*valp & ~(0x3 << 2)) != 0;
4486   *valp = *valp >> 2;
4487   return error;
4488 }
4489
4490 static int
4491 Operand_bs4_decode (uint32 *valp)
4492 {
4493   *valp = *valp << 2;
4494   return 0;
4495 }
4496
4497 static int
4498 Operand_bs4_encode (uint32 *valp)
4499 {
4500   int error;
4501   error = (*valp & ~(0x3 << 2)) != 0;
4502   *valp = *valp >> 2;
4503   return error;
4504 }
4505
4506 static int
4507 Operand_br4_decode (uint32 *valp)
4508 {
4509   *valp = *valp << 2;
4510   return 0;
4511 }
4512
4513 static int
4514 Operand_br4_encode (uint32 *valp)
4515 {
4516   int error;
4517   error = (*valp & ~(0x3 << 2)) != 0;
4518   *valp = *valp >> 2;
4519   return error;
4520 }
4521
4522 static int
4523 Operand_bt8_decode (uint32 *valp)
4524 {
4525   *valp = *valp << 3;
4526   return 0;
4527 }
4528
4529 static int
4530 Operand_bt8_encode (uint32 *valp)
4531 {
4532   int error;
4533   error = (*valp & ~(0x1 << 3)) != 0;
4534   *valp = *valp >> 3;
4535   return error;
4536 }
4537
4538 static int
4539 Operand_bs8_decode (uint32 *valp)
4540 {
4541   *valp = *valp << 3;
4542   return 0;
4543 }
4544
4545 static int
4546 Operand_bs8_encode (uint32 *valp)
4547 {
4548   int error;
4549   error = (*valp & ~(0x1 << 3)) != 0;
4550   *valp = *valp >> 3;
4551   return error;
4552 }
4553
4554 static int
4555 Operand_br8_decode (uint32 *valp)
4556 {
4557   *valp = *valp << 3;
4558   return 0;
4559 }
4560
4561 static int
4562 Operand_br8_encode (uint32 *valp)
4563 {
4564   int error;
4565   error = (*valp & ~(0x1 << 3)) != 0;
4566   *valp = *valp >> 3;
4567   return error;
4568 }
4569
4570 static int
4571 Operand_bt16_decode (uint32 *valp)
4572 {
4573   *valp = *valp << 4;
4574   return 0;
4575 }
4576
4577 static int
4578 Operand_bt16_encode (uint32 *valp)
4579 {
4580   int error;
4581   error = (*valp & ~(0 << 4)) != 0;
4582   *valp = *valp >> 4;
4583   return error;
4584 }
4585
4586 static int
4587 Operand_bs16_decode (uint32 *valp)
4588 {
4589   *valp = *valp << 4;
4590   return 0;
4591 }
4592
4593 static int
4594 Operand_bs16_encode (uint32 *valp)
4595 {
4596   int error;
4597   error = (*valp & ~(0 << 4)) != 0;
4598   *valp = *valp >> 4;
4599   return error;
4600 }
4601
4602 static int
4603 Operand_br16_decode (uint32 *valp)
4604 {
4605   *valp = *valp << 4;
4606   return 0;
4607 }
4608
4609 static int
4610 Operand_br16_encode (uint32 *valp)
4611 {
4612   int error;
4613   error = (*valp & ~(0 << 4)) != 0;
4614   *valp = *valp >> 4;
4615   return error;
4616 }
4617
4618 static int
4619 Operand_brall_decode (uint32 *valp)
4620 {
4621   *valp = *valp << 4;
4622   return 0;
4623 }
4624
4625 static int
4626 Operand_brall_encode (uint32 *valp)
4627 {
4628   int error;
4629   error = (*valp & ~(0 << 4)) != 0;
4630   *valp = *valp >> 4;
4631   return error;
4632 }
4633
4634 static int
4635 Operand_tp7_decode (uint32 *valp)
4636 {
4637   unsigned tp7_0, t_0;
4638   t_0 = *valp & 0xf;
4639   tp7_0 = t_0 + 0x7;
4640   *valp = tp7_0;
4641   return 0;
4642 }
4643
4644 static int
4645 Operand_tp7_encode (uint32 *valp)
4646 {
4647   unsigned t_0, tp7_0;
4648   tp7_0 = *valp;
4649   t_0 = (tp7_0 - 0x7) & 0xf;
4650   *valp = t_0;
4651   return 0;
4652 }
4653
4654 static int
4655 Operand_xt_wbr15_label_decode (uint32 *valp)
4656 {
4657   unsigned xt_wbr15_label_0, xt_wbr15_imm_0;
4658   xt_wbr15_imm_0 = *valp & 0x7fff;
4659   xt_wbr15_label_0 = 0x4 + ((xt_wbr15_imm_0 ^ 0x4000) - 0x4000);
4660   *valp = xt_wbr15_label_0;
4661   return 0;
4662 }
4663
4664 static int
4665 Operand_xt_wbr15_label_encode (uint32 *valp)
4666 {
4667   unsigned xt_wbr15_imm_0, xt_wbr15_label_0;
4668   xt_wbr15_label_0 = *valp;
4669   xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff;
4670   *valp = xt_wbr15_imm_0;
4671   return 0;
4672 }
4673
4674 static int
4675 Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
4676 {
4677   *valp -= pc;
4678   return 0;
4679 }
4680
4681 static int
4682 Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
4683 {
4684   *valp += pc;
4685   return 0;
4686 }
4687
4688 static int
4689 Operand_xt_wbr18_label_decode (uint32 *valp)
4690 {
4691   unsigned xt_wbr18_label_0, xt_wbr18_imm_0;
4692   xt_wbr18_imm_0 = *valp & 0x3ffff;
4693   xt_wbr18_label_0 = 0x4 + ((xt_wbr18_imm_0 ^ 0x20000) - 0x20000);
4694   *valp = xt_wbr18_label_0;
4695   return 0;
4696 }
4697
4698 static int
4699 Operand_xt_wbr18_label_encode (uint32 *valp)
4700 {
4701   unsigned xt_wbr18_imm_0, xt_wbr18_label_0;
4702   xt_wbr18_label_0 = *valp;
4703   xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff;
4704   *valp = xt_wbr18_imm_0;
4705   return 0;
4706 }
4707
4708 static int
4709 Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
4710 {
4711   *valp -= pc;
4712   return 0;
4713 }
4714
4715 static int
4716 Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
4717 {
4718   *valp += pc;
4719   return 0;
4720 }
4721
4722 static int
4723 Operand_cimm8x4_decode (uint32 *valp)
4724 {
4725   unsigned cimm8x4_0, imm8_0;
4726   imm8_0 = *valp & 0xff;
4727   cimm8x4_0 = (imm8_0 << 2) | 0;
4728   *valp = cimm8x4_0;
4729   return 0;
4730 }
4731
4732 static int
4733 Operand_cimm8x4_encode (uint32 *valp)
4734 {
4735   unsigned imm8_0, cimm8x4_0;
4736   cimm8x4_0 = *valp;
4737   imm8_0 = (cimm8x4_0 >> 2) & 0xff;
4738   *valp = imm8_0;
4739   return 0;
4740 }
4741
4742 static int
4743 Operand_frr_decode (uint32 *valp ATTRIBUTE_UNUSED)
4744 {
4745   return 0;
4746 }
4747
4748 static int
4749 Operand_frr_encode (uint32 *valp)
4750 {
4751   int error;
4752   error = (*valp & ~0xf) != 0;
4753   return error;
4754 }
4755
4756 static int
4757 Operand_frs_decode (uint32 *valp ATTRIBUTE_UNUSED)
4758 {
4759   return 0;
4760 }
4761
4762 static int
4763 Operand_frs_encode (uint32 *valp)
4764 {
4765   int error;
4766   error = (*valp & ~0xf) != 0;
4767   return error;
4768 }
4769
4770 static int
4771 Operand_frt_decode (uint32 *valp ATTRIBUTE_UNUSED)
4772 {
4773   return 0;
4774 }
4775
4776 static int
4777 Operand_frt_encode (uint32 *valp)
4778 {
4779   int error;
4780   error = (*valp & ~0xf) != 0;
4781   return error;
4782 }
4783
4784 static xtensa_operand_internal operands[] = {
4785   { "soffsetx4", 10, -1, 0,
4786     XTENSA_OPERAND_IS_PCRELATIVE,
4787     Operand_soffsetx4_encode, Operand_soffsetx4_decode,
4788     Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
4789   { "uimm12x8", 3, -1, 0,
4790     0,
4791     Operand_uimm12x8_encode, Operand_uimm12x8_decode,
4792     0, 0 },
4793   { "simm4", 26, -1, 0,
4794     0,
4795     Operand_simm4_encode, Operand_simm4_decode,
4796     0, 0 },
4797   { "arr", 14, 0, 1,
4798     XTENSA_OPERAND_IS_REGISTER,
4799     Operand_arr_encode, Operand_arr_decode,
4800     0, 0 },
4801   { "ars", 5, 0, 1,
4802     XTENSA_OPERAND_IS_REGISTER,
4803     Operand_ars_encode, Operand_ars_decode,
4804     0, 0 },
4805   { "*ars_invisible", 5, 0, 1,
4806     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
4807     Operand_ars_encode, Operand_ars_decode,
4808     0, 0 },
4809   { "art", 0, 0, 1,
4810     XTENSA_OPERAND_IS_REGISTER,
4811     Operand_art_encode, Operand_art_decode,
4812     0, 0 },
4813   { "ar0", 123, 0, 1,
4814     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
4815     Operand_ar0_encode, Operand_ar0_decode,
4816     0, 0 },
4817   { "ar4", 124, 0, 1,
4818     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
4819     Operand_ar4_encode, Operand_ar4_decode,
4820     0, 0 },
4821   { "ar8", 125, 0, 1,
4822     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
4823     Operand_ar8_encode, Operand_ar8_decode,
4824     0, 0 },
4825   { "ar12", 126, 0, 1,
4826     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
4827     Operand_ar12_encode, Operand_ar12_decode,
4828     0, 0 },
4829   { "ars_entry", 5, 0, 1,
4830     XTENSA_OPERAND_IS_REGISTER,
4831     Operand_ars_entry_encode, Operand_ars_entry_decode,
4832     0, 0 },
4833   { "immrx4", 14, -1, 0,
4834     0,
4835     Operand_immrx4_encode, Operand_immrx4_decode,
4836     0, 0 },
4837   { "lsi4x4", 14, -1, 0,
4838     0,
4839     Operand_lsi4x4_encode, Operand_lsi4x4_decode,
4840     0, 0 },
4841   { "simm7", 34, -1, 0,
4842     0,
4843     Operand_simm7_encode, Operand_simm7_decode,
4844     0, 0 },
4845   { "uimm6", 33, -1, 0,
4846     XTENSA_OPERAND_IS_PCRELATIVE,
4847     Operand_uimm6_encode, Operand_uimm6_decode,
4848     Operand_uimm6_ator, Operand_uimm6_rtoa },
4849   { "ai4const", 0, -1, 0,
4850     0,
4851     Operand_ai4const_encode, Operand_ai4const_decode,
4852     0, 0 },
4853   { "b4const", 14, -1, 0,
4854     0,
4855     Operand_b4const_encode, Operand_b4const_decode,
4856     0, 0 },
4857   { "b4constu", 14, -1, 0,
4858     0,
4859     Operand_b4constu_encode, Operand_b4constu_decode,
4860     0, 0 },
4861   { "uimm8", 4, -1, 0,
4862     0,
4863     Operand_uimm8_encode, Operand_uimm8_decode,
4864     0, 0 },
4865   { "uimm8x2", 4, -1, 0,
4866     0,
4867     Operand_uimm8x2_encode, Operand_uimm8x2_decode,
4868     0, 0 },
4869   { "uimm8x4", 4, -1, 0,
4870     0,
4871     Operand_uimm8x4_encode, Operand_uimm8x4_decode,
4872     0, 0 },
4873   { "uimm4x16", 13, -1, 0,
4874     0,
4875     Operand_uimm4x16_encode, Operand_uimm4x16_decode,
4876     0, 0 },
4877   { "simm8", 4, -1, 0,
4878     0,
4879     Operand_simm8_encode, Operand_simm8_decode,
4880     0, 0 },
4881   { "simm8x256", 4, -1, 0,
4882     0,
4883     Operand_simm8x256_encode, Operand_simm8x256_decode,
4884     0, 0 },
4885   { "simm12b", 6, -1, 0,
4886     0,
4887     Operand_simm12b_encode, Operand_simm12b_decode,
4888     0, 0 },
4889   { "msalp32", 18, -1, 0,
4890     0,
4891     Operand_msalp32_encode, Operand_msalp32_decode,
4892     0, 0 },
4893   { "op2p1", 13, -1, 0,
4894     0,
4895     Operand_op2p1_encode, Operand_op2p1_decode,
4896     0, 0 },
4897   { "label8", 4, -1, 0,
4898     XTENSA_OPERAND_IS_PCRELATIVE,
4899     Operand_label8_encode, Operand_label8_decode,
4900     Operand_label8_ator, Operand_label8_rtoa },
4901   { "ulabel8", 4, -1, 0,
4902     XTENSA_OPERAND_IS_PCRELATIVE,
4903     Operand_ulabel8_encode, Operand_ulabel8_decode,
4904     Operand_ulabel8_ator, Operand_ulabel8_rtoa },
4905   { "label12", 3, -1, 0,
4906     XTENSA_OPERAND_IS_PCRELATIVE,
4907     Operand_label12_encode, Operand_label12_decode,
4908     Operand_label12_ator, Operand_label12_rtoa },
4909   { "soffset", 10, -1, 0,
4910     XTENSA_OPERAND_IS_PCRELATIVE,
4911     Operand_soffset_encode, Operand_soffset_decode,
4912     Operand_soffset_ator, Operand_soffset_rtoa },
4913   { "uimm16x4", 7, -1, 0,
4914     XTENSA_OPERAND_IS_PCRELATIVE,
4915     Operand_uimm16x4_encode, Operand_uimm16x4_decode,
4916     Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
4917   { "mx", 43, 1, 1,
4918     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
4919     Operand_mx_encode, Operand_mx_decode,
4920     0, 0 },
4921   { "my", 42, 1, 1,
4922     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
4923     Operand_my_encode, Operand_my_decode,
4924     0, 0 },
4925   { "mw", 41, 1, 1,
4926     XTENSA_OPERAND_IS_REGISTER,
4927     Operand_mw_encode, Operand_mw_decode,
4928     0, 0 },
4929   { "mr0", 127, 1, 1,
4930     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
4931     Operand_mr0_encode, Operand_mr0_decode,
4932     0, 0 },
4933   { "mr1", 128, 1, 1,
4934     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
4935     Operand_mr1_encode, Operand_mr1_decode,
4936     0, 0 },
4937   { "mr2", 129, 1, 1,
4938     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
4939     Operand_mr2_encode, Operand_mr2_decode,
4940     0, 0 },
4941   { "mr3", 130, 1, 1,
4942     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
4943     Operand_mr3_encode, Operand_mr3_decode,
4944     0, 0 },
4945   { "immt", 0, -1, 0,
4946     0,
4947     Operand_immt_encode, Operand_immt_decode,
4948     0, 0 },
4949   { "imms", 5, -1, 0,
4950     0,
4951     Operand_imms_encode, Operand_imms_decode,
4952     0, 0 },
4953   { "bt", 0, 2, 1,
4954     XTENSA_OPERAND_IS_REGISTER,
4955     Operand_bt_encode, Operand_bt_decode,
4956     0, 0 },
4957   { "bs", 5, 2, 1,
4958     XTENSA_OPERAND_IS_REGISTER,
4959     Operand_bs_encode, Operand_bs_decode,
4960     0, 0 },
4961   { "br", 14, 2, 1,
4962     XTENSA_OPERAND_IS_REGISTER,
4963     Operand_br_encode, Operand_br_decode,
4964     0, 0 },
4965   { "bt2", 44, 2, 2,
4966     XTENSA_OPERAND_IS_REGISTER,
4967     Operand_bt2_encode, Operand_bt2_decode,
4968     0, 0 },
4969   { "bs2", 45, 2, 2,
4970     XTENSA_OPERAND_IS_REGISTER,
4971     Operand_bs2_encode, Operand_bs2_decode,
4972     0, 0 },
4973   { "br2", 46, 2, 2,
4974     XTENSA_OPERAND_IS_REGISTER,
4975     Operand_br2_encode, Operand_br2_decode,
4976     0, 0 },
4977   { "bt4", 47, 2, 4,
4978     XTENSA_OPERAND_IS_REGISTER,
4979     Operand_bt4_encode, Operand_bt4_decode,
4980     0, 0 },
4981   { "bs4", 48, 2, 4,
4982     XTENSA_OPERAND_IS_REGISTER,
4983     Operand_bs4_encode, Operand_bs4_decode,
4984     0, 0 },
4985   { "br4", 49, 2, 4,
4986     XTENSA_OPERAND_IS_REGISTER,
4987     Operand_br4_encode, Operand_br4_decode,
4988     0, 0 },
4989   { "bt8", 50, 2, 8,
4990     XTENSA_OPERAND_IS_REGISTER,
4991     Operand_bt8_encode, Operand_bt8_decode,
4992     0, 0 },
4993   { "bs8", 51, 2, 8,
4994     XTENSA_OPERAND_IS_REGISTER,
4995     Operand_bs8_encode, Operand_bs8_decode,
4996     0, 0 },
4997   { "br8", 52, 2, 8,
4998     XTENSA_OPERAND_IS_REGISTER,
4999     Operand_br8_encode, Operand_br8_decode,
5000     0, 0 },
5001   { "bt16", 131, 2, 16,
5002     XTENSA_OPERAND_IS_REGISTER,
5003     Operand_bt16_encode, Operand_bt16_decode,
5004     0, 0 },
5005   { "bs16", 132, 2, 16,
5006     XTENSA_OPERAND_IS_REGISTER,
5007     Operand_bs16_encode, Operand_bs16_decode,
5008     0, 0 },
5009   { "br16", 133, 2, 16,
5010     XTENSA_OPERAND_IS_REGISTER,
5011     Operand_br16_encode, Operand_br16_decode,
5012     0, 0 },
5013   { "brall", 134, 2, 16,
5014     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5015     Operand_brall_encode, Operand_brall_decode,
5016     0, 0 },
5017   { "tp7", 0, -1, 0,
5018     0,
5019     Operand_tp7_encode, Operand_tp7_decode,
5020     0, 0 },
5021   { "xt_wbr15_label", 53, -1, 0,
5022     XTENSA_OPERAND_IS_PCRELATIVE,
5023     Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode,
5024     Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
5025   { "xt_wbr18_label", 54, -1, 0,
5026     XTENSA_OPERAND_IS_PCRELATIVE,
5027     Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode,
5028     Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
5029   { "cimm8x4", 4, -1, 0,
5030     0,
5031     Operand_cimm8x4_encode, Operand_cimm8x4_decode,
5032     0, 0 },
5033   { "frr", 14, 3, 1,
5034     XTENSA_OPERAND_IS_REGISTER,
5035     Operand_frr_encode, Operand_frr_decode,
5036     0, 0 },
5037   { "frs", 5, 3, 1,
5038     XTENSA_OPERAND_IS_REGISTER,
5039     Operand_frs_encode, Operand_frs_decode,
5040     0, 0 },
5041   { "frt", 0, 3, 1,
5042     XTENSA_OPERAND_IS_REGISTER,
5043     Operand_frt_encode, Operand_frt_decode,
5044     0, 0 },
5045   { "t", 0, -1, 0, 0, 0, 0, 0, 0 },
5046   { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 },
5047   { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 },
5048   { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 },
5049   { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 },
5050   { "s", 5, -1, 0, 0, 0, 0, 0, 0 },
5051   { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 },
5052   { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 },
5053   { "m", 8, -1, 0, 0, 0, 0, 0, 0 },
5054   { "n", 9, -1, 0, 0, 0, 0, 0, 0 },
5055   { "offset", 10, -1, 0, 0, 0, 0, 0, 0 },
5056   { "op0", 11, -1, 0, 0, 0, 0, 0, 0 },
5057   { "op1", 12, -1, 0, 0, 0, 0, 0, 0 },
5058   { "op2", 13, -1, 0, 0, 0, 0, 0, 0 },
5059   { "r", 14, -1, 0, 0, 0, 0, 0, 0 },
5060   { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 },
5061   { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 },
5062   { "sae", 17, -1, 0, 0, 0, 0, 0, 0 },
5063   { "sal", 18, -1, 0, 0, 0, 0, 0, 0 },
5064   { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 },
5065   { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 },
5066   { "sas", 21, -1, 0, 0, 0, 0, 0, 0 },
5067   { "sr", 22, -1, 0, 0, 0, 0, 0, 0 },
5068   { "st", 23, -1, 0, 0, 0, 0, 0, 0 },
5069   { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 },
5070   { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 },
5071   { "mn", 26, -1, 0, 0, 0, 0, 0, 0 },
5072   { "i", 27, -1, 0, 0, 0, 0, 0, 0 },
5073   { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 },
5074   { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 },
5075   { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 },
5076   { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 },
5077   { "z", 32, -1, 0, 0, 0, 0, 0, 0 },
5078   { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 },
5079   { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 },
5080   { "r3", 35, -1, 0, 0, 0, 0, 0, 0 },
5081   { "rbit2", 36, -1, 0, 0, 0, 0, 0, 0 },
5082   { "rhi", 37, -1, 0, 0, 0, 0, 0, 0 },
5083   { "t3", 38, -1, 0, 0, 0, 0, 0, 0 },
5084   { "tbit2", 39, -1, 0, 0, 0, 0, 0, 0 },
5085   { "tlo", 40, -1, 0, 0, 0, 0, 0, 0 },
5086   { "w", 41, -1, 0, 0, 0, 0, 0, 0 },
5087   { "y", 42, -1, 0, 0, 0, 0, 0, 0 },
5088   { "x", 43, -1, 0, 0, 0, 0, 0, 0 },
5089   { "t2", 44, -1, 0, 0, 0, 0, 0, 0 },
5090   { "s2", 45, -1, 0, 0, 0, 0, 0, 0 },
5091   { "r2", 46, -1, 0, 0, 0, 0, 0, 0 },
5092   { "t4", 47, -1, 0, 0, 0, 0, 0, 0 },
5093   { "s4", 48, -1, 0, 0, 0, 0, 0, 0 },
5094   { "r4", 49, -1, 0, 0, 0, 0, 0, 0 },
5095   { "t8", 50, -1, 0, 0, 0, 0, 0, 0 },
5096   { "s8", 51, -1, 0, 0, 0, 0, 0, 0 },
5097   { "r8", 52, -1, 0, 0, 0, 0, 0, 0 },
5098   { "xt_wbr15_imm", 53, -1, 0, 0, 0, 0, 0, 0 },
5099   { "xt_wbr18_imm", 54, -1, 0, 0, 0, 0, 0, 0 },
5100   { "op0_xt_flix64_slot0_s3", 55, -1, 0, 0, 0, 0, 0, 0 },
5101   { "combined3e2c5767_fld7", 56, -1, 0, 0, 0, 0, 0, 0 },
5102   { "combined3e2c5767_fld8", 57, -1, 0, 0, 0, 0, 0, 0 },
5103   { "combined3e2c5767_fld9", 58, -1, 0, 0, 0, 0, 0, 0 },
5104   { "combined3e2c5767_fld11", 59, -1, 0, 0, 0, 0, 0, 0 },
5105   { "combined3e2c5767_fld49xt_flix64_slot0", 60, -1, 0, 0, 0, 0, 0, 0 },
5106   { "op0_s4", 61, -1, 0, 0, 0, 0, 0, 0 },
5107   { "combined3e2c5767_fld16", 62, -1, 0, 0, 0, 0, 0, 0 },
5108   { "combined3e2c5767_fld19xt_flix64_slot1", 63, -1, 0, 0, 0, 0, 0, 0 },
5109   { "combined3e2c5767_fld20xt_flix64_slot1", 64, -1, 0, 0, 0, 0, 0, 0 },
5110   { "combined3e2c5767_fld21xt_flix64_slot1", 65, -1, 0, 0, 0, 0, 0, 0 },
5111   { "combined3e2c5767_fld22xt_flix64_slot1", 66, -1, 0, 0, 0, 0, 0, 0 },
5112   { "combined3e2c5767_fld23xt_flix64_slot1", 67, -1, 0, 0, 0, 0, 0, 0 },
5113   { "combined3e2c5767_fld25xt_flix64_slot1", 68, -1, 0, 0, 0, 0, 0, 0 },
5114   { "combined3e2c5767_fld26xt_flix64_slot1", 69, -1, 0, 0, 0, 0, 0, 0 },
5115   { "combined3e2c5767_fld28xt_flix64_slot1", 70, -1, 0, 0, 0, 0, 0, 0 },
5116   { "combined3e2c5767_fld30xt_flix64_slot1", 71, -1, 0, 0, 0, 0, 0, 0 },
5117   { "combined3e2c5767_fld32xt_flix64_slot1", 72, -1, 0, 0, 0, 0, 0, 0 },
5118   { "combined3e2c5767_fld33xt_flix64_slot1", 73, -1, 0, 0, 0, 0, 0, 0 },
5119   { "combined3e2c5767_fld35xt_flix64_slot1", 74, -1, 0, 0, 0, 0, 0, 0 },
5120   { "combined3e2c5767_fld51xt_flix64_slot1", 75, -1, 0, 0, 0, 0, 0, 0 },
5121   { "combined3e2c5767_fld52xt_flix64_slot1", 76, -1, 0, 0, 0, 0, 0, 0 },
5122   { "combined3e2c5767_fld53xt_flix64_slot1", 77, -1, 0, 0, 0, 0, 0, 0 },
5123   { "combined3e2c5767_fld54xt_flix64_slot1", 78, -1, 0, 0, 0, 0, 0, 0 },
5124   { "combined3e2c5767_fld57xt_flix64_slot1", 79, -1, 0, 0, 0, 0, 0, 0 },
5125   { "combined3e2c5767_fld58xt_flix64_slot1", 80, -1, 0, 0, 0, 0, 0, 0 },
5126   { "combined3e2c5767_fld60xt_flix64_slot1", 81, -1, 0, 0, 0, 0, 0, 0 },
5127   { "combined3e2c5767_fld62xt_flix64_slot1", 82, -1, 0, 0, 0, 0, 0, 0 },
5128   { "op0_s5", 83, -1, 0, 0, 0, 0, 0, 0 },
5129   { "combined3e2c5767_fld36xt_flix64_slot2", 84, -1, 0, 0, 0, 0, 0, 0 },
5130   { "combined3e2c5767_fld37xt_flix64_slot2", 85, -1, 0, 0, 0, 0, 0, 0 },
5131   { "combined3e2c5767_fld39xt_flix64_slot2", 86, -1, 0, 0, 0, 0, 0, 0 },
5132   { "combined3e2c5767_fld41xt_flix64_slot2", 87, -1, 0, 0, 0, 0, 0, 0 },
5133   { "combined3e2c5767_fld42xt_flix64_slot2", 88, -1, 0, 0, 0, 0, 0, 0 },
5134   { "combined3e2c5767_fld44xt_flix64_slot2", 89, -1, 0, 0, 0, 0, 0, 0 },
5135   { "combined3e2c5767_fld45xt_flix64_slot2", 90, -1, 0, 0, 0, 0, 0, 0 },
5136   { "combined3e2c5767_fld47xt_flix64_slot2", 91, -1, 0, 0, 0, 0, 0, 0 },
5137   { "combined3e2c5767_fld63xt_flix64_slot2", 92, -1, 0, 0, 0, 0, 0, 0 },
5138   { "combined3e2c5767_fld64xt_flix64_slot2", 93, -1, 0, 0, 0, 0, 0, 0 },
5139   { "combined3e2c5767_fld65xt_flix64_slot2", 94, -1, 0, 0, 0, 0, 0, 0 },
5140   { "combined3e2c5767_fld66xt_flix64_slot2", 95, -1, 0, 0, 0, 0, 0, 0 },
5141   { "combined3e2c5767_fld68xt_flix64_slot2", 96, -1, 0, 0, 0, 0, 0, 0 },
5142   { "op0_s6", 97, -1, 0, 0, 0, 0, 0, 0 },
5143   { "combined3e2c5767_fld70xt_flix64_slot3", 98, -1, 0, 0, 0, 0, 0, 0 },
5144   { "combined3e2c5767_fld71", 99, -1, 0, 0, 0, 0, 0, 0 },
5145   { "combined3e2c5767_fld72xt_flix64_slot3", 100, -1, 0, 0, 0, 0, 0, 0 },
5146   { "combined3e2c5767_fld73xt_flix64_slot3", 101, -1, 0, 0, 0, 0, 0, 0 },
5147   { "combined3e2c5767_fld74xt_flix64_slot3", 102, -1, 0, 0, 0, 0, 0, 0 },
5148   { "combined3e2c5767_fld75xt_flix64_slot3", 103, -1, 0, 0, 0, 0, 0, 0 },
5149   { "combined3e2c5767_fld76xt_flix64_slot3", 104, -1, 0, 0, 0, 0, 0, 0 },
5150   { "combined3e2c5767_fld77xt_flix64_slot3", 105, -1, 0, 0, 0, 0, 0, 0 },
5151   { "combined3e2c5767_fld78xt_flix64_slot3", 106, -1, 0, 0, 0, 0, 0, 0 },
5152   { "combined3e2c5767_fld79xt_flix64_slot3", 107, -1, 0, 0, 0, 0, 0, 0 },
5153   { "combined3e2c5767_fld80xt_flix64_slot3", 108, -1, 0, 0, 0, 0, 0, 0 },
5154   { "combined3e2c5767_fld81xt_flix64_slot3", 109, -1, 0, 0, 0, 0, 0, 0 },
5155   { "combined3e2c5767_fld82xt_flix64_slot3", 110, -1, 0, 0, 0, 0, 0, 0 },
5156   { "combined3e2c5767_fld83xt_flix64_slot3", 111, -1, 0, 0, 0, 0, 0, 0 },
5157   { "combined3e2c5767_fld84xt_flix64_slot3", 112, -1, 0, 0, 0, 0, 0, 0 },
5158   { "combined3e2c5767_fld85xt_flix64_slot3", 113, -1, 0, 0, 0, 0, 0, 0 },
5159   { "combined3e2c5767_fld86xt_flix64_slot3", 114, -1, 0, 0, 0, 0, 0, 0 },
5160   { "combined3e2c5767_fld87xt_flix64_slot3", 115, -1, 0, 0, 0, 0, 0, 0 },
5161   { "combined3e2c5767_fld88xt_flix64_slot3", 116, -1, 0, 0, 0, 0, 0, 0 },
5162   { "combined3e2c5767_fld89xt_flix64_slot3", 117, -1, 0, 0, 0, 0, 0, 0 },
5163   { "combined3e2c5767_fld90xt_flix64_slot3", 118, -1, 0, 0, 0, 0, 0, 0 },
5164   { "combined3e2c5767_fld91xt_flix64_slot3", 119, -1, 0, 0, 0, 0, 0, 0 },
5165   { "combined3e2c5767_fld92xt_flix64_slot3", 120, -1, 0, 0, 0, 0, 0, 0 },
5166   { "combined3e2c5767_fld93xt_flix64_slot3", 121, -1, 0, 0, 0, 0, 0, 0 },
5167   { "op0_xt_flix64_slot0", 122, -1, 0, 0, 0, 0, 0, 0 }
5168 };
5169
5170 \f
5171 /* Iclass table.  */
5172
5173 static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
5174   { { STATE_PSRING }, 'i' },
5175   { { STATE_PSEXCM }, 'm' },
5176   { { STATE_EPC1 }, 'i' }
5177 };
5178
5179 static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
5180   { { STATE_PSEXCM }, 'i' },
5181   { { STATE_PSRING }, 'i' },
5182   { { STATE_DEPC }, 'i' }
5183 };
5184
5185 static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
5186   { { 0 /* soffsetx4 */ }, 'i' },
5187   { { 10 /* ar12 */ }, 'o' }
5188 };
5189
5190 static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
5191   { { STATE_PSCALLINC }, 'o' }
5192 };
5193
5194 static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
5195   { { 0 /* soffsetx4 */ }, 'i' },
5196   { { 9 /* ar8 */ }, 'o' }
5197 };
5198
5199 static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
5200   { { STATE_PSCALLINC }, 'o' }
5201 };
5202
5203 static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
5204   { { 0 /* soffsetx4 */ }, 'i' },
5205   { { 8 /* ar4 */ }, 'o' }
5206 };
5207
5208 static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
5209   { { STATE_PSCALLINC }, 'o' }
5210 };
5211
5212 static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
5213   { { 4 /* ars */ }, 'i' },
5214   { { 10 /* ar12 */ }, 'o' }
5215 };
5216
5217 static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
5218   { { STATE_PSCALLINC }, 'o' }
5219 };
5220
5221 static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
5222   { { 4 /* ars */ }, 'i' },
5223   { { 9 /* ar8 */ }, 'o' }
5224 };
5225
5226 static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
5227   { { STATE_PSCALLINC }, 'o' }
5228 };
5229
5230 static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
5231   { { 4 /* ars */ }, 'i' },
5232   { { 8 /* ar4 */ }, 'o' }
5233 };
5234
5235 static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
5236   { { STATE_PSCALLINC }, 'o' }
5237 };
5238
5239 static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
5240   { { 11 /* ars_entry */ }, 's' },
5241   { { 4 /* ars */ }, 'i' },
5242   { { 1 /* uimm12x8 */ }, 'i' }
5243 };
5244
5245 static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
5246   { { STATE_PSCALLINC }, 'i' },
5247   { { STATE_PSEXCM }, 'i' },
5248   { { STATE_PSWOE }, 'i' },
5249   { { STATE_WindowBase }, 'm' },
5250   { { STATE_WindowStart }, 'm' }
5251 };
5252
5253 static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
5254   { { 6 /* art */ }, 'o' },
5255   { { 4 /* ars */ }, 'i' }
5256 };
5257
5258 static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
5259   { { STATE_WindowBase }, 'i' },
5260   { { STATE_WindowStart }, 'i' }
5261 };
5262
5263 static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
5264   { { 2 /* simm4 */ }, 'i' }
5265 };
5266
5267 static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
5268   { { STATE_PSEXCM }, 'i' },
5269   { { STATE_PSRING }, 'i' },
5270   { { STATE_WindowBase }, 'm' }
5271 };
5272
5273 static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
5274   { { 5 /* *ars_invisible */ }, 'i' }
5275 };
5276
5277 static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
5278   { { STATE_WindowBase }, 'm' },
5279   { { STATE_WindowStart }, 'm' },
5280   { { STATE_PSEXCM }, 'i' },
5281   { { STATE_PSWOE }, 'i' }
5282 };
5283
5284 static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
5285   { { STATE_EPC1 }, 'i' },
5286   { { STATE_PSEXCM }, 'm' },
5287   { { STATE_PSRING }, 'i' },
5288   { { STATE_WindowBase }, 'm' },
5289   { { STATE_WindowStart }, 'm' },
5290   { { STATE_PSOWB }, 'i' }
5291 };
5292
5293 static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
5294   { { 6 /* art */ }, 'o' },
5295   { { 4 /* ars */ }, 'i' },
5296   { { 12 /* immrx4 */ }, 'i' }
5297 };
5298
5299 static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
5300   { { STATE_PSEXCM }, 'i' },
5301   { { STATE_PSRING }, 'i' }
5302 };
5303
5304 static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
5305   { { 6 /* art */ }, 'i' },
5306   { { 4 /* ars */ }, 'i' },
5307   { { 12 /* immrx4 */ }, 'i' }
5308 };
5309
5310 static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
5311   { { STATE_PSEXCM }, 'i' },
5312   { { STATE_PSRING }, 'i' }
5313 };
5314
5315 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
5316   { { 6 /* art */ }, 'o' }
5317 };
5318
5319 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
5320   { { STATE_PSEXCM }, 'i' },
5321   { { STATE_PSRING }, 'i' },
5322   { { STATE_WindowBase }, 'i' }
5323 };
5324
5325 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
5326   { { 6 /* art */ }, 'i' }
5327 };
5328
5329 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
5330   { { STATE_PSEXCM }, 'i' },
5331   { { STATE_PSRING }, 'i' },
5332   { { STATE_WindowBase }, 'o' }
5333 };
5334
5335 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
5336   { { 6 /* art */ }, 'm' }
5337 };
5338
5339 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
5340   { { STATE_PSEXCM }, 'i' },
5341   { { STATE_PSRING }, 'i' },
5342   { { STATE_WindowBase }, 'm' }
5343 };
5344
5345 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
5346   { { 6 /* art */ }, 'o' }
5347 };
5348
5349 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
5350   { { STATE_PSEXCM }, 'i' },
5351   { { STATE_PSRING }, 'i' },
5352   { { STATE_WindowStart }, 'i' }
5353 };
5354
5355 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
5356   { { 6 /* art */ }, 'i' }
5357 };
5358
5359 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
5360   { { STATE_PSEXCM }, 'i' },
5361   { { STATE_PSRING }, 'i' },
5362   { { STATE_WindowStart }, 'o' }
5363 };
5364
5365 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
5366   { { 6 /* art */ }, 'm' }
5367 };
5368
5369 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
5370   { { STATE_PSEXCM }, 'i' },
5371   { { STATE_PSRING }, 'i' },
5372   { { STATE_WindowStart }, 'm' }
5373 };
5374
5375 static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
5376   { { 3 /* arr */ }, 'o' },
5377   { { 4 /* ars */ }, 'i' },
5378   { { 6 /* art */ }, 'i' }
5379 };
5380
5381 static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
5382   { { 3 /* arr */ }, 'o' },
5383   { { 4 /* ars */ }, 'i' },
5384   { { 16 /* ai4const */ }, 'i' }
5385 };
5386
5387 static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
5388   { { 4 /* ars */ }, 'i' },
5389   { { 15 /* uimm6 */ }, 'i' }
5390 };
5391
5392 static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
5393   { { 6 /* art */ }, 'o' },
5394   { { 4 /* ars */ }, 'i' },
5395   { { 13 /* lsi4x4 */ }, 'i' }
5396 };
5397
5398 static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
5399   { { 6 /* art */ }, 'o' },
5400   { { 4 /* ars */ }, 'i' }
5401 };
5402
5403 static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
5404   { { 4 /* ars */ }, 'o' },
5405   { { 14 /* simm7 */ }, 'i' }
5406 };
5407
5408 static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
5409   { { 5 /* *ars_invisible */ }, 'i' }
5410 };
5411
5412 static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
5413   { { 6 /* art */ }, 'i' },
5414   { { 4 /* ars */ }, 'i' },
5415   { { 13 /* lsi4x4 */ }, 'i' }
5416 };
5417
5418 static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
5419   { { 3 /* arr */ }, 'o' }
5420 };
5421
5422 static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
5423   { { STATE_THREADPTR }, 'i' }
5424 };
5425
5426 static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
5427   { { 6 /* art */ }, 'i' }
5428 };
5429
5430 static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
5431   { { STATE_THREADPTR }, 'o' }
5432 };
5433
5434 static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
5435   { { 6 /* art */ }, 'o' },
5436   { { 4 /* ars */ }, 'i' },
5437   { { 23 /* simm8 */ }, 'i' }
5438 };
5439
5440 static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
5441   { { 6 /* art */ }, 'o' },
5442   { { 4 /* ars */ }, 'i' },
5443   { { 24 /* simm8x256 */ }, 'i' }
5444 };
5445
5446 static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
5447   { { 3 /* arr */ }, 'o' },
5448   { { 4 /* ars */ }, 'i' },
5449   { { 6 /* art */ }, 'i' }
5450 };
5451
5452 static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
5453   { { 3 /* arr */ }, 'o' },
5454   { { 4 /* ars */ }, 'i' },
5455   { { 6 /* art */ }, 'i' }
5456 };
5457
5458 static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
5459   { { 4 /* ars */ }, 'i' },
5460   { { 17 /* b4const */ }, 'i' },
5461   { { 28 /* label8 */ }, 'i' }
5462 };
5463
5464 static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
5465   { { 4 /* ars */ }, 'i' },
5466   { { 67 /* bbi */ }, 'i' },
5467   { { 28 /* label8 */ }, 'i' }
5468 };
5469
5470 static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
5471   { { 4 /* ars */ }, 'i' },
5472   { { 18 /* b4constu */ }, 'i' },
5473   { { 28 /* label8 */ }, 'i' }
5474 };
5475
5476 static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
5477   { { 4 /* ars */ }, 'i' },
5478   { { 6 /* art */ }, 'i' },
5479   { { 28 /* label8 */ }, 'i' }
5480 };
5481
5482 static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
5483   { { 4 /* ars */ }, 'i' },
5484   { { 30 /* label12 */ }, 'i' }
5485 };
5486
5487 static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
5488   { { 0 /* soffsetx4 */ }, 'i' },
5489   { { 7 /* ar0 */ }, 'o' }
5490 };
5491
5492 static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
5493   { { 4 /* ars */ }, 'i' },
5494   { { 7 /* ar0 */ }, 'o' }
5495 };
5496
5497 static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
5498   { { 3 /* arr */ }, 'o' },
5499   { { 6 /* art */ }, 'i' },
5500   { { 82 /* sae */ }, 'i' },
5501   { { 27 /* op2p1 */ }, 'i' }
5502 };
5503
5504 static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
5505   { { 31 /* soffset */ }, 'i' }
5506 };
5507
5508 static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
5509   { { 4 /* ars */ }, 'i' }
5510 };
5511
5512 static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
5513   { { 6 /* art */ }, 'o' },
5514   { { 4 /* ars */ }, 'i' },
5515   { { 20 /* uimm8x2 */ }, 'i' }
5516 };
5517
5518 static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
5519   { { 6 /* art */ }, 'o' },
5520   { { 4 /* ars */ }, 'i' },
5521   { { 20 /* uimm8x2 */ }, 'i' }
5522 };
5523
5524 static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
5525   { { 6 /* art */ }, 'o' },
5526   { { 4 /* ars */ }, 'i' },
5527   { { 21 /* uimm8x4 */ }, 'i' }
5528 };
5529
5530 static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
5531   { { 6 /* art */ }, 'o' },
5532   { { 32 /* uimm16x4 */ }, 'i' }
5533 };
5534
5535 static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
5536   { { STATE_LITBADDR }, 'i' },
5537   { { STATE_LITBEN }, 'i' }
5538 };
5539
5540 static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
5541   { { 6 /* art */ }, 'o' },
5542   { { 4 /* ars */ }, 'i' },
5543   { { 19 /* uimm8 */ }, 'i' }
5544 };
5545
5546 static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
5547   { { 4 /* ars */ }, 'i' },
5548   { { 29 /* ulabel8 */ }, 'i' }
5549 };
5550
5551 static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
5552   { { STATE_LBEG }, 'o' },
5553   { { STATE_LEND }, 'o' },
5554   { { STATE_LCOUNT }, 'o' }
5555 };
5556
5557 static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
5558   { { 4 /* ars */ }, 'i' },
5559   { { 29 /* ulabel8 */ }, 'i' }
5560 };
5561
5562 static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
5563   { { STATE_LBEG }, 'o' },
5564   { { STATE_LEND }, 'o' },
5565   { { STATE_LCOUNT }, 'o' }
5566 };
5567
5568 static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
5569   { { 6 /* art */ }, 'o' },
5570   { { 25 /* simm12b */ }, 'i' }
5571 };
5572
5573 static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
5574   { { 3 /* arr */ }, 'm' },
5575   { { 4 /* ars */ }, 'i' },
5576   { { 6 /* art */ }, 'i' }
5577 };
5578
5579 static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
5580   { { 3 /* arr */ }, 'o' },
5581   { { 6 /* art */ }, 'i' }
5582 };
5583
5584 static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
5585   { { 5 /* *ars_invisible */ }, 'i' }
5586 };
5587
5588 static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
5589   { { 6 /* art */ }, 'i' },
5590   { { 4 /* ars */ }, 'i' },
5591   { { 20 /* uimm8x2 */ }, 'i' }
5592 };
5593
5594 static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
5595   { { 6 /* art */ }, 'i' },
5596   { { 4 /* ars */ }, 'i' },
5597   { { 21 /* uimm8x4 */ }, 'i' }
5598 };
5599
5600 static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
5601   { { 6 /* art */ }, 'i' },
5602   { { 4 /* ars */ }, 'i' },
5603   { { 19 /* uimm8 */ }, 'i' }
5604 };
5605
5606 static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
5607   { { 4 /* ars */ }, 'i' }
5608 };
5609
5610 static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
5611   { { STATE_SAR }, 'o' }
5612 };
5613
5614 static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
5615   { { 86 /* sas */ }, 'i' }
5616 };
5617
5618 static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
5619   { { STATE_SAR }, 'o' }
5620 };
5621
5622 static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
5623   { { 3 /* arr */ }, 'o' },
5624   { { 4 /* ars */ }, 'i' }
5625 };
5626
5627 static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
5628   { { STATE_SAR }, 'i' }
5629 };
5630
5631 static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
5632   { { 3 /* arr */ }, 'o' },
5633   { { 4 /* ars */ }, 'i' },
5634   { { 6 /* art */ }, 'i' }
5635 };
5636
5637 static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
5638   { { STATE_SAR }, 'i' }
5639 };
5640
5641 static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
5642   { { 3 /* arr */ }, 'o' },
5643   { { 6 /* art */ }, 'i' }
5644 };
5645
5646 static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
5647   { { STATE_SAR }, 'i' }
5648 };
5649
5650 static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
5651   { { 3 /* arr */ }, 'o' },
5652   { { 4 /* ars */ }, 'i' },
5653   { { 26 /* msalp32 */ }, 'i' }
5654 };
5655
5656 static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
5657   { { 3 /* arr */ }, 'o' },
5658   { { 6 /* art */ }, 'i' },
5659   { { 84 /* sargt */ }, 'i' }
5660 };
5661
5662 static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
5663   { { 3 /* arr */ }, 'o' },
5664   { { 6 /* art */ }, 'i' },
5665   { { 70 /* s */ }, 'i' }
5666 };
5667
5668 static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
5669   { { STATE_XTSYNC }, 'i' }
5670 };
5671
5672 static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
5673   { { 6 /* art */ }, 'o' },
5674   { { 70 /* s */ }, 'i' }
5675 };
5676
5677 static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
5678   { { STATE_PSWOE }, 'i' },
5679   { { STATE_PSCALLINC }, 'i' },
5680   { { STATE_PSOWB }, 'i' },
5681   { { STATE_PSRING }, 'i' },
5682   { { STATE_PSUM }, 'i' },
5683   { { STATE_PSEXCM }, 'i' },
5684   { { STATE_PSINTLEVEL }, 'm' }
5685 };
5686
5687 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
5688   { { 6 /* art */ }, 'o' }
5689 };
5690
5691 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
5692   { { STATE_LEND }, 'i' }
5693 };
5694
5695 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
5696   { { 6 /* art */ }, 'i' }
5697 };
5698
5699 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
5700   { { STATE_LEND }, 'o' }
5701 };
5702
5703 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
5704   { { 6 /* art */ }, 'm' }
5705 };
5706
5707 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
5708   { { STATE_LEND }, 'm' }
5709 };
5710
5711 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
5712   { { 6 /* art */ }, 'o' }
5713 };
5714
5715 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
5716   { { STATE_LCOUNT }, 'i' }
5717 };
5718
5719 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
5720   { { 6 /* art */ }, 'i' }
5721 };
5722
5723 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
5724   { { STATE_XTSYNC }, 'o' },
5725   { { STATE_LCOUNT }, 'o' }
5726 };
5727
5728 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
5729   { { 6 /* art */ }, 'm' }
5730 };
5731
5732 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
5733   { { STATE_XTSYNC }, 'o' },
5734   { { STATE_LCOUNT }, 'm' }
5735 };
5736
5737 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
5738   { { 6 /* art */ }, 'o' }
5739 };
5740
5741 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
5742   { { STATE_LBEG }, 'i' }
5743 };
5744
5745 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
5746   { { 6 /* art */ }, 'i' }
5747 };
5748
5749 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
5750   { { STATE_LBEG }, 'o' }
5751 };
5752
5753 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
5754   { { 6 /* art */ }, 'm' }
5755 };
5756
5757 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
5758   { { STATE_LBEG }, 'm' }
5759 };
5760
5761 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
5762   { { 6 /* art */ }, 'o' }
5763 };
5764
5765 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
5766   { { STATE_SAR }, 'i' }
5767 };
5768
5769 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
5770   { { 6 /* art */ }, 'i' }
5771 };
5772
5773 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
5774   { { STATE_SAR }, 'o' },
5775   { { STATE_XTSYNC }, 'o' }
5776 };
5777
5778 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
5779   { { 6 /* art */ }, 'm' }
5780 };
5781
5782 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
5783   { { STATE_SAR }, 'm' }
5784 };
5785
5786 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
5787   { { 6 /* art */ }, 'o' }
5788 };
5789
5790 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
5791   { { STATE_LITBADDR }, 'i' },
5792   { { STATE_LITBEN }, 'i' }
5793 };
5794
5795 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
5796   { { 6 /* art */ }, 'i' }
5797 };
5798
5799 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
5800   { { STATE_LITBADDR }, 'o' },
5801   { { STATE_LITBEN }, 'o' }
5802 };
5803
5804 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
5805   { { 6 /* art */ }, 'm' }
5806 };
5807
5808 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
5809   { { STATE_LITBADDR }, 'm' },
5810   { { STATE_LITBEN }, 'm' }
5811 };
5812
5813 static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
5814   { { 6 /* art */ }, 'o' }
5815 };
5816
5817 static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
5818   { { STATE_PSEXCM }, 'i' },
5819   { { STATE_PSRING }, 'i' }
5820 };
5821
5822 static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
5823   { { 6 /* art */ }, 'o' }
5824 };
5825
5826 static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
5827   { { STATE_PSEXCM }, 'i' },
5828   { { STATE_PSRING }, 'i' }
5829 };
5830
5831 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
5832   { { 6 /* art */ }, 'o' }
5833 };
5834
5835 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
5836   { { STATE_PSWOE }, 'i' },
5837   { { STATE_PSCALLINC }, 'i' },
5838   { { STATE_PSOWB }, 'i' },
5839   { { STATE_PSRING }, 'i' },
5840   { { STATE_PSUM }, 'i' },
5841   { { STATE_PSEXCM }, 'i' },
5842   { { STATE_PSINTLEVEL }, 'i' }
5843 };
5844
5845 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
5846   { { 6 /* art */ }, 'i' }
5847 };
5848
5849 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
5850   { { STATE_PSWOE }, 'o' },
5851   { { STATE_PSCALLINC }, 'o' },
5852   { { STATE_PSOWB }, 'o' },
5853   { { STATE_PSRING }, 'm' },
5854   { { STATE_PSUM }, 'o' },
5855   { { STATE_PSEXCM }, 'm' },
5856   { { STATE_PSINTLEVEL }, 'o' }
5857 };
5858
5859 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
5860   { { 6 /* art */ }, 'm' }
5861 };
5862
5863 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
5864   { { STATE_PSWOE }, 'm' },
5865   { { STATE_PSCALLINC }, 'm' },
5866   { { STATE_PSOWB }, 'm' },
5867   { { STATE_PSRING }, 'm' },
5868   { { STATE_PSUM }, 'm' },
5869   { { STATE_PSEXCM }, 'm' },
5870   { { STATE_PSINTLEVEL }, 'm' }
5871 };
5872
5873 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
5874   { { 6 /* art */ }, 'o' }
5875 };
5876
5877 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
5878   { { STATE_PSEXCM }, 'i' },
5879   { { STATE_PSRING }, 'i' },
5880   { { STATE_EPC1 }, 'i' }
5881 };
5882
5883 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
5884   { { 6 /* art */ }, 'i' }
5885 };
5886
5887 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
5888   { { STATE_PSEXCM }, 'i' },
5889   { { STATE_PSRING }, 'i' },
5890   { { STATE_EPC1 }, 'o' }
5891 };
5892
5893 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
5894   { { 6 /* art */ }, 'm' }
5895 };
5896
5897 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
5898   { { STATE_PSEXCM }, 'i' },
5899   { { STATE_PSRING }, 'i' },
5900   { { STATE_EPC1 }, 'm' }
5901 };
5902
5903 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
5904   { { 6 /* art */ }, 'o' }
5905 };
5906
5907 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
5908   { { STATE_PSEXCM }, 'i' },
5909   { { STATE_PSRING }, 'i' },
5910   { { STATE_EXCSAVE1 }, 'i' }
5911 };
5912
5913 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
5914   { { 6 /* art */ }, 'i' }
5915 };
5916
5917 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
5918   { { STATE_PSEXCM }, 'i' },
5919   { { STATE_PSRING }, 'i' },
5920   { { STATE_EXCSAVE1 }, 'o' }
5921 };
5922
5923 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
5924   { { 6 /* art */ }, 'm' }
5925 };
5926
5927 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
5928   { { STATE_PSEXCM }, 'i' },
5929   { { STATE_PSRING }, 'i' },
5930   { { STATE_EXCSAVE1 }, 'm' }
5931 };
5932
5933 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
5934   { { 6 /* art */ }, 'o' }
5935 };
5936
5937 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
5938   { { STATE_PSEXCM }, 'i' },
5939   { { STATE_PSRING }, 'i' },
5940   { { STATE_EPC2 }, 'i' }
5941 };
5942
5943 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
5944   { { 6 /* art */ }, 'i' }
5945 };
5946
5947 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
5948   { { STATE_PSEXCM }, 'i' },
5949   { { STATE_PSRING }, 'i' },
5950   { { STATE_EPC2 }, 'o' }
5951 };
5952
5953 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
5954   { { 6 /* art */ }, 'm' }
5955 };
5956
5957 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
5958   { { STATE_PSEXCM }, 'i' },
5959   { { STATE_PSRING }, 'i' },
5960   { { STATE_EPC2 }, 'm' }
5961 };
5962
5963 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
5964   { { 6 /* art */ }, 'o' }
5965 };
5966
5967 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
5968   { { STATE_PSEXCM }, 'i' },
5969   { { STATE_PSRING }, 'i' },
5970   { { STATE_EXCSAVE2 }, 'i' }
5971 };
5972
5973 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
5974   { { 6 /* art */ }, 'i' }
5975 };
5976
5977 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
5978   { { STATE_PSEXCM }, 'i' },
5979   { { STATE_PSRING }, 'i' },
5980   { { STATE_EXCSAVE2 }, 'o' }
5981 };
5982
5983 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
5984   { { 6 /* art */ }, 'm' }
5985 };
5986
5987 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
5988   { { STATE_PSEXCM }, 'i' },
5989   { { STATE_PSRING }, 'i' },
5990   { { STATE_EXCSAVE2 }, 'm' }
5991 };
5992
5993 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
5994   { { 6 /* art */ }, 'o' }
5995 };
5996
5997 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
5998   { { STATE_PSEXCM }, 'i' },
5999   { { STATE_PSRING }, 'i' },
6000   { { STATE_EPC3 }, 'i' }
6001 };
6002
6003 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
6004   { { 6 /* art */ }, 'i' }
6005 };
6006
6007 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
6008   { { STATE_PSEXCM }, 'i' },
6009   { { STATE_PSRING }, 'i' },
6010   { { STATE_EPC3 }, 'o' }
6011 };
6012
6013 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
6014   { { 6 /* art */ }, 'm' }
6015 };
6016
6017 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
6018   { { STATE_PSEXCM }, 'i' },
6019   { { STATE_PSRING }, 'i' },
6020   { { STATE_EPC3 }, 'm' }
6021 };
6022
6023 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
6024   { { 6 /* art */ }, 'o' }
6025 };
6026
6027 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
6028   { { STATE_PSEXCM }, 'i' },
6029   { { STATE_PSRING }, 'i' },
6030   { { STATE_EXCSAVE3 }, 'i' }
6031 };
6032
6033 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
6034   { { 6 /* art */ }, 'i' }
6035 };
6036
6037 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
6038   { { STATE_PSEXCM }, 'i' },
6039   { { STATE_PSRING }, 'i' },
6040   { { STATE_EXCSAVE3 }, 'o' }
6041 };
6042
6043 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
6044   { { 6 /* art */ }, 'm' }
6045 };
6046
6047 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
6048   { { STATE_PSEXCM }, 'i' },
6049   { { STATE_PSRING }, 'i' },
6050   { { STATE_EXCSAVE3 }, 'm' }
6051 };
6052
6053 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
6054   { { 6 /* art */ }, 'o' }
6055 };
6056
6057 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
6058   { { STATE_PSEXCM }, 'i' },
6059   { { STATE_PSRING }, 'i' },
6060   { { STATE_EPC4 }, 'i' }
6061 };
6062
6063 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
6064   { { 6 /* art */ }, 'i' }
6065 };
6066
6067 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
6068   { { STATE_PSEXCM }, 'i' },
6069   { { STATE_PSRING }, 'i' },
6070   { { STATE_EPC4 }, 'o' }
6071 };
6072
6073 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
6074   { { 6 /* art */ }, 'm' }
6075 };
6076
6077 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
6078   { { STATE_PSEXCM }, 'i' },
6079   { { STATE_PSRING }, 'i' },
6080   { { STATE_EPC4 }, 'm' }
6081 };
6082
6083 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
6084   { { 6 /* art */ }, 'o' }
6085 };
6086
6087 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
6088   { { STATE_PSEXCM }, 'i' },
6089   { { STATE_PSRING }, 'i' },
6090   { { STATE_EXCSAVE4 }, 'i' }
6091 };
6092
6093 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
6094   { { 6 /* art */ }, 'i' }
6095 };
6096
6097 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
6098   { { STATE_PSEXCM }, 'i' },
6099   { { STATE_PSRING }, 'i' },
6100   { { STATE_EXCSAVE4 }, 'o' }
6101 };
6102
6103 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
6104   { { 6 /* art */ }, 'm' }
6105 };
6106
6107 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
6108   { { STATE_PSEXCM }, 'i' },
6109   { { STATE_PSRING }, 'i' },
6110   { { STATE_EXCSAVE4 }, 'm' }
6111 };
6112
6113 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
6114   { { 6 /* art */ }, 'o' }
6115 };
6116
6117 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
6118   { { STATE_PSEXCM }, 'i' },
6119   { { STATE_PSRING }, 'i' },
6120   { { STATE_EPC5 }, 'i' }
6121 };
6122
6123 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
6124   { { 6 /* art */ }, 'i' }
6125 };
6126
6127 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
6128   { { STATE_PSEXCM }, 'i' },
6129   { { STATE_PSRING }, 'i' },
6130   { { STATE_EPC5 }, 'o' }
6131 };
6132
6133 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
6134   { { 6 /* art */ }, 'm' }
6135 };
6136
6137 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
6138   { { STATE_PSEXCM }, 'i' },
6139   { { STATE_PSRING }, 'i' },
6140   { { STATE_EPC5 }, 'm' }
6141 };
6142
6143 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
6144   { { 6 /* art */ }, 'o' }
6145 };
6146
6147 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
6148   { { STATE_PSEXCM }, 'i' },
6149   { { STATE_PSRING }, 'i' },
6150   { { STATE_EXCSAVE5 }, 'i' }
6151 };
6152
6153 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
6154   { { 6 /* art */ }, 'i' }
6155 };
6156
6157 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
6158   { { STATE_PSEXCM }, 'i' },
6159   { { STATE_PSRING }, 'i' },
6160   { { STATE_EXCSAVE5 }, 'o' }
6161 };
6162
6163 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
6164   { { 6 /* art */ }, 'm' }
6165 };
6166
6167 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
6168   { { STATE_PSEXCM }, 'i' },
6169   { { STATE_PSRING }, 'i' },
6170   { { STATE_EXCSAVE5 }, 'm' }
6171 };
6172
6173 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
6174   { { 6 /* art */ }, 'o' }
6175 };
6176
6177 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
6178   { { STATE_PSEXCM }, 'i' },
6179   { { STATE_PSRING }, 'i' },
6180   { { STATE_EPC6 }, 'i' }
6181 };
6182
6183 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
6184   { { 6 /* art */ }, 'i' }
6185 };
6186
6187 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
6188   { { STATE_PSEXCM }, 'i' },
6189   { { STATE_PSRING }, 'i' },
6190   { { STATE_EPC6 }, 'o' }
6191 };
6192
6193 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
6194   { { 6 /* art */ }, 'm' }
6195 };
6196
6197 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
6198   { { STATE_PSEXCM }, 'i' },
6199   { { STATE_PSRING }, 'i' },
6200   { { STATE_EPC6 }, 'm' }
6201 };
6202
6203 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
6204   { { 6 /* art */ }, 'o' }
6205 };
6206
6207 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
6208   { { STATE_PSEXCM }, 'i' },
6209   { { STATE_PSRING }, 'i' },
6210   { { STATE_EXCSAVE6 }, 'i' }
6211 };
6212
6213 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
6214   { { 6 /* art */ }, 'i' }
6215 };
6216
6217 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
6218   { { STATE_PSEXCM }, 'i' },
6219   { { STATE_PSRING }, 'i' },
6220   { { STATE_EXCSAVE6 }, 'o' }
6221 };
6222
6223 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
6224   { { 6 /* art */ }, 'm' }
6225 };
6226
6227 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
6228   { { STATE_PSEXCM }, 'i' },
6229   { { STATE_PSRING }, 'i' },
6230   { { STATE_EXCSAVE6 }, 'm' }
6231 };
6232
6233 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
6234   { { 6 /* art */ }, 'o' }
6235 };
6236
6237 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
6238   { { STATE_PSEXCM }, 'i' },
6239   { { STATE_PSRING }, 'i' },
6240   { { STATE_EPC7 }, 'i' }
6241 };
6242
6243 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
6244   { { 6 /* art */ }, 'i' }
6245 };
6246
6247 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
6248   { { STATE_PSEXCM }, 'i' },
6249   { { STATE_PSRING }, 'i' },
6250   { { STATE_EPC7 }, 'o' }
6251 };
6252
6253 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
6254   { { 6 /* art */ }, 'm' }
6255 };
6256
6257 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
6258   { { STATE_PSEXCM }, 'i' },
6259   { { STATE_PSRING }, 'i' },
6260   { { STATE_EPC7 }, 'm' }
6261 };
6262
6263 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
6264   { { 6 /* art */ }, 'o' }
6265 };
6266
6267 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
6268   { { STATE_PSEXCM }, 'i' },
6269   { { STATE_PSRING }, 'i' },
6270   { { STATE_EXCSAVE7 }, 'i' }
6271 };
6272
6273 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
6274   { { 6 /* art */ }, 'i' }
6275 };
6276
6277 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
6278   { { STATE_PSEXCM }, 'i' },
6279   { { STATE_PSRING }, 'i' },
6280   { { STATE_EXCSAVE7 }, 'o' }
6281 };
6282
6283 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
6284   { { 6 /* art */ }, 'm' }
6285 };
6286
6287 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
6288   { { STATE_PSEXCM }, 'i' },
6289   { { STATE_PSRING }, 'i' },
6290   { { STATE_EXCSAVE7 }, 'm' }
6291 };
6292
6293 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
6294   { { 6 /* art */ }, 'o' }
6295 };
6296
6297 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
6298   { { STATE_PSEXCM }, 'i' },
6299   { { STATE_PSRING }, 'i' },
6300   { { STATE_EPS2 }, 'i' }
6301 };
6302
6303 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
6304   { { 6 /* art */ }, 'i' }
6305 };
6306
6307 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
6308   { { STATE_PSEXCM }, 'i' },
6309   { { STATE_PSRING }, 'i' },
6310   { { STATE_EPS2 }, 'o' }
6311 };
6312
6313 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
6314   { { 6 /* art */ }, 'm' }
6315 };
6316
6317 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
6318   { { STATE_PSEXCM }, 'i' },
6319   { { STATE_PSRING }, 'i' },
6320   { { STATE_EPS2 }, 'm' }
6321 };
6322
6323 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
6324   { { 6 /* art */ }, 'o' }
6325 };
6326
6327 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
6328   { { STATE_PSEXCM }, 'i' },
6329   { { STATE_PSRING }, 'i' },
6330   { { STATE_EPS3 }, 'i' }
6331 };
6332
6333 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
6334   { { 6 /* art */ }, 'i' }
6335 };
6336
6337 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
6338   { { STATE_PSEXCM }, 'i' },
6339   { { STATE_PSRING }, 'i' },
6340   { { STATE_EPS3 }, 'o' }
6341 };
6342
6343 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
6344   { { 6 /* art */ }, 'm' }
6345 };
6346
6347 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
6348   { { STATE_PSEXCM }, 'i' },
6349   { { STATE_PSRING }, 'i' },
6350   { { STATE_EPS3 }, 'm' }
6351 };
6352
6353 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
6354   { { 6 /* art */ }, 'o' }
6355 };
6356
6357 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
6358   { { STATE_PSEXCM }, 'i' },
6359   { { STATE_PSRING }, 'i' },
6360   { { STATE_EPS4 }, 'i' }
6361 };
6362
6363 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
6364   { { 6 /* art */ }, 'i' }
6365 };
6366
6367 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
6368   { { STATE_PSEXCM }, 'i' },
6369   { { STATE_PSRING }, 'i' },
6370   { { STATE_EPS4 }, 'o' }
6371 };
6372
6373 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
6374   { { 6 /* art */ }, 'm' }
6375 };
6376
6377 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
6378   { { STATE_PSEXCM }, 'i' },
6379   { { STATE_PSRING }, 'i' },
6380   { { STATE_EPS4 }, 'm' }
6381 };
6382
6383 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
6384   { { 6 /* art */ }, 'o' }
6385 };
6386
6387 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
6388   { { STATE_PSEXCM }, 'i' },
6389   { { STATE_PSRING }, 'i' },
6390   { { STATE_EPS5 }, 'i' }
6391 };
6392
6393 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
6394   { { 6 /* art */ }, 'i' }
6395 };
6396
6397 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
6398   { { STATE_PSEXCM }, 'i' },
6399   { { STATE_PSRING }, 'i' },
6400   { { STATE_EPS5 }, 'o' }
6401 };
6402
6403 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
6404   { { 6 /* art */ }, 'm' }
6405 };
6406
6407 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
6408   { { STATE_PSEXCM }, 'i' },
6409   { { STATE_PSRING }, 'i' },
6410   { { STATE_EPS5 }, 'm' }
6411 };
6412
6413 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
6414   { { 6 /* art */ }, 'o' }
6415 };
6416
6417 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
6418   { { STATE_PSEXCM }, 'i' },
6419   { { STATE_PSRING }, 'i' },
6420   { { STATE_EPS6 }, 'i' }
6421 };
6422
6423 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
6424   { { 6 /* art */ }, 'i' }
6425 };
6426
6427 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
6428   { { STATE_PSEXCM }, 'i' },
6429   { { STATE_PSRING }, 'i' },
6430   { { STATE_EPS6 }, 'o' }
6431 };
6432
6433 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
6434   { { 6 /* art */ }, 'm' }
6435 };
6436
6437 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
6438   { { STATE_PSEXCM }, 'i' },
6439   { { STATE_PSRING }, 'i' },
6440   { { STATE_EPS6 }, 'm' }
6441 };
6442
6443 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
6444   { { 6 /* art */ }, 'o' }
6445 };
6446
6447 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
6448   { { STATE_PSEXCM }, 'i' },
6449   { { STATE_PSRING }, 'i' },
6450   { { STATE_EPS7 }, 'i' }
6451 };
6452
6453 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
6454   { { 6 /* art */ }, 'i' }
6455 };
6456
6457 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
6458   { { STATE_PSEXCM }, 'i' },
6459   { { STATE_PSRING }, 'i' },
6460   { { STATE_EPS7 }, 'o' }
6461 };
6462
6463 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
6464   { { 6 /* art */ }, 'm' }
6465 };
6466
6467 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
6468   { { STATE_PSEXCM }, 'i' },
6469   { { STATE_PSRING }, 'i' },
6470   { { STATE_EPS7 }, 'm' }
6471 };
6472
6473 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
6474   { { 6 /* art */ }, 'o' }
6475 };
6476
6477 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
6478   { { STATE_PSEXCM }, 'i' },
6479   { { STATE_PSRING }, 'i' },
6480   { { STATE_EXCVADDR }, 'i' }
6481 };
6482
6483 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
6484   { { 6 /* art */ }, 'i' }
6485 };
6486
6487 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
6488   { { STATE_PSEXCM }, 'i' },
6489   { { STATE_PSRING }, 'i' },
6490   { { STATE_EXCVADDR }, 'o' }
6491 };
6492
6493 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
6494   { { 6 /* art */ }, 'm' }
6495 };
6496
6497 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
6498   { { STATE_PSEXCM }, 'i' },
6499   { { STATE_PSRING }, 'i' },
6500   { { STATE_EXCVADDR }, 'm' }
6501 };
6502
6503 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
6504   { { 6 /* art */ }, 'o' }
6505 };
6506
6507 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
6508   { { STATE_PSEXCM }, 'i' },
6509   { { STATE_PSRING }, 'i' },
6510   { { STATE_DEPC }, 'i' }
6511 };
6512
6513 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
6514   { { 6 /* art */ }, 'i' }
6515 };
6516
6517 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
6518   { { STATE_PSEXCM }, 'i' },
6519   { { STATE_PSRING }, 'i' },
6520   { { STATE_DEPC }, 'o' }
6521 };
6522
6523 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
6524   { { 6 /* art */ }, 'm' }
6525 };
6526
6527 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
6528   { { STATE_PSEXCM }, 'i' },
6529   { { STATE_PSRING }, 'i' },
6530   { { STATE_DEPC }, 'm' }
6531 };
6532
6533 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
6534   { { 6 /* art */ }, 'o' }
6535 };
6536
6537 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
6538   { { STATE_PSEXCM }, 'i' },
6539   { { STATE_PSRING }, 'i' },
6540   { { STATE_EXCCAUSE }, 'i' },
6541   { { STATE_XTSYNC }, 'i' }
6542 };
6543
6544 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
6545   { { 6 /* art */ }, 'i' }
6546 };
6547
6548 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
6549   { { STATE_PSEXCM }, 'i' },
6550   { { STATE_PSRING }, 'i' },
6551   { { STATE_EXCCAUSE }, 'o' }
6552 };
6553
6554 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
6555   { { 6 /* art */ }, 'm' }
6556 };
6557
6558 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
6559   { { STATE_PSEXCM }, 'i' },
6560   { { STATE_PSRING }, 'i' },
6561   { { STATE_EXCCAUSE }, 'm' }
6562 };
6563
6564 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
6565   { { 6 /* art */ }, 'o' }
6566 };
6567
6568 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
6569   { { STATE_PSEXCM }, 'i' },
6570   { { STATE_PSRING }, 'i' },
6571   { { STATE_MISC0 }, 'i' }
6572 };
6573
6574 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
6575   { { 6 /* art */ }, 'i' }
6576 };
6577
6578 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
6579   { { STATE_PSEXCM }, 'i' },
6580   { { STATE_PSRING }, 'i' },
6581   { { STATE_MISC0 }, 'o' }
6582 };
6583
6584 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
6585   { { 6 /* art */ }, 'm' }
6586 };
6587
6588 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
6589   { { STATE_PSEXCM }, 'i' },
6590   { { STATE_PSRING }, 'i' },
6591   { { STATE_MISC0 }, 'm' }
6592 };
6593
6594 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
6595   { { 6 /* art */ }, 'o' }
6596 };
6597
6598 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
6599   { { STATE_PSEXCM }, 'i' },
6600   { { STATE_PSRING }, 'i' },
6601   { { STATE_MISC1 }, 'i' }
6602 };
6603
6604 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
6605   { { 6 /* art */ }, 'i' }
6606 };
6607
6608 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
6609   { { STATE_PSEXCM }, 'i' },
6610   { { STATE_PSRING }, 'i' },
6611   { { STATE_MISC1 }, 'o' }
6612 };
6613
6614 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
6615   { { 6 /* art */ }, 'm' }
6616 };
6617
6618 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
6619   { { STATE_PSEXCM }, 'i' },
6620   { { STATE_PSRING }, 'i' },
6621   { { STATE_MISC1 }, 'm' }
6622 };
6623
6624 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_args[] = {
6625   { { 6 /* art */ }, 'o' }
6626 };
6627
6628 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_stateArgs[] = {
6629   { { STATE_PSEXCM }, 'i' },
6630   { { STATE_PSRING }, 'i' },
6631   { { STATE_MISC2 }, 'i' }
6632 };
6633
6634 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_args[] = {
6635   { { 6 /* art */ }, 'i' }
6636 };
6637
6638 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_stateArgs[] = {
6639   { { STATE_PSEXCM }, 'i' },
6640   { { STATE_PSRING }, 'i' },
6641   { { STATE_MISC2 }, 'o' }
6642 };
6643
6644 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_args[] = {
6645   { { 6 /* art */ }, 'm' }
6646 };
6647
6648 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_stateArgs[] = {
6649   { { STATE_PSEXCM }, 'i' },
6650   { { STATE_PSRING }, 'i' },
6651   { { STATE_MISC2 }, 'm' }
6652 };
6653
6654 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_args[] = {
6655   { { 6 /* art */ }, 'o' }
6656 };
6657
6658 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_stateArgs[] = {
6659   { { STATE_PSEXCM }, 'i' },
6660   { { STATE_PSRING }, 'i' },
6661   { { STATE_MISC3 }, 'i' }
6662 };
6663
6664 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_args[] = {
6665   { { 6 /* art */ }, 'i' }
6666 };
6667
6668 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_stateArgs[] = {
6669   { { STATE_PSEXCM }, 'i' },
6670   { { STATE_PSRING }, 'i' },
6671   { { STATE_MISC3 }, 'o' }
6672 };
6673
6674 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_args[] = {
6675   { { 6 /* art */ }, 'm' }
6676 };
6677
6678 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_stateArgs[] = {
6679   { { STATE_PSEXCM }, 'i' },
6680   { { STATE_PSRING }, 'i' },
6681   { { STATE_MISC3 }, 'm' }
6682 };
6683
6684 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
6685   { { 6 /* art */ }, 'o' }
6686 };
6687
6688 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
6689   { { STATE_PSEXCM }, 'i' },
6690   { { STATE_PSRING }, 'i' }
6691 };
6692
6693 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
6694   { { 6 /* art */ }, 'o' }
6695 };
6696
6697 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
6698   { { STATE_PSEXCM }, 'i' },
6699   { { STATE_PSRING }, 'i' },
6700   { { STATE_VECBASE }, 'i' }
6701 };
6702
6703 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
6704   { { 6 /* art */ }, 'i' }
6705 };
6706
6707 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
6708   { { STATE_PSEXCM }, 'i' },
6709   { { STATE_PSRING }, 'i' },
6710   { { STATE_VECBASE }, 'o' }
6711 };
6712
6713 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
6714   { { 6 /* art */ }, 'm' }
6715 };
6716
6717 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
6718   { { STATE_PSEXCM }, 'i' },
6719   { { STATE_PSRING }, 'i' },
6720   { { STATE_VECBASE }, 'm' }
6721 };
6722
6723 static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
6724   { { 4 /* ars */ }, 'i' },
6725   { { 6 /* art */ }, 'i' }
6726 };
6727
6728 static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
6729   { { STATE_ACC }, 'o' }
6730 };
6731
6732 static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
6733   { { 4 /* ars */ }, 'i' },
6734   { { 34 /* my */ }, 'i' }
6735 };
6736
6737 static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
6738   { { STATE_ACC }, 'o' }
6739 };
6740
6741 static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
6742   { { 33 /* mx */ }, 'i' },
6743   { { 6 /* art */ }, 'i' }
6744 };
6745
6746 static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
6747   { { STATE_ACC }, 'o' }
6748 };
6749
6750 static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
6751   { { 33 /* mx */ }, 'i' },
6752   { { 34 /* my */ }, 'i' }
6753 };
6754
6755 static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
6756   { { STATE_ACC }, 'o' }
6757 };
6758
6759 static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
6760   { { 4 /* ars */ }, 'i' },
6761   { { 6 /* art */ }, 'i' }
6762 };
6763
6764 static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
6765   { { STATE_ACC }, 'm' }
6766 };
6767
6768 static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
6769   { { 4 /* ars */ }, 'i' },
6770   { { 34 /* my */ }, 'i' }
6771 };
6772
6773 static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
6774   { { STATE_ACC }, 'm' }
6775 };
6776
6777 static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
6778   { { 33 /* mx */ }, 'i' },
6779   { { 6 /* art */ }, 'i' }
6780 };
6781
6782 static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
6783   { { STATE_ACC }, 'm' }
6784 };
6785
6786 static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
6787   { { 33 /* mx */ }, 'i' },
6788   { { 34 /* my */ }, 'i' }
6789 };
6790
6791 static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
6792   { { STATE_ACC }, 'm' }
6793 };
6794
6795 static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
6796   { { 35 /* mw */ }, 'o' },
6797   { { 4 /* ars */ }, 'm' },
6798   { { 33 /* mx */ }, 'i' },
6799   { { 6 /* art */ }, 'i' }
6800 };
6801
6802 static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
6803   { { STATE_ACC }, 'm' }
6804 };
6805
6806 static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
6807   { { 35 /* mw */ }, 'o' },
6808   { { 4 /* ars */ }, 'm' },
6809   { { 33 /* mx */ }, 'i' },
6810   { { 34 /* my */ }, 'i' }
6811 };
6812
6813 static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
6814   { { STATE_ACC }, 'm' }
6815 };
6816
6817 static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
6818   { { 35 /* mw */ }, 'o' },
6819   { { 4 /* ars */ }, 'm' }
6820 };
6821
6822 static xtensa_arg_internal Iclass_xt_iclass_mul16_args[] = {
6823   { { 3 /* arr */ }, 'o' },
6824   { { 4 /* ars */ }, 'i' },
6825   { { 6 /* art */ }, 'i' }
6826 };
6827
6828 static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
6829   { { 6 /* art */ }, 'o' },
6830   { { 36 /* mr0 */ }, 'i' }
6831 };
6832
6833 static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
6834   { { 6 /* art */ }, 'i' },
6835   { { 36 /* mr0 */ }, 'o' }
6836 };
6837
6838 static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
6839   { { 6 /* art */ }, 'm' },
6840   { { 36 /* mr0 */ }, 'm' }
6841 };
6842
6843 static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
6844   { { 6 /* art */ }, 'o' },
6845   { { 37 /* mr1 */ }, 'i' }
6846 };
6847
6848 static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
6849   { { 6 /* art */ }, 'i' },
6850   { { 37 /* mr1 */ }, 'o' }
6851 };
6852
6853 static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
6854   { { 6 /* art */ }, 'm' },
6855   { { 37 /* mr1 */ }, 'm' }
6856 };
6857
6858 static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
6859   { { 6 /* art */ }, 'o' },
6860   { { 38 /* mr2 */ }, 'i' }
6861 };
6862
6863 static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
6864   { { 6 /* art */ }, 'i' },
6865   { { 38 /* mr2 */ }, 'o' }
6866 };
6867
6868 static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
6869   { { 6 /* art */ }, 'm' },
6870   { { 38 /* mr2 */ }, 'm' }
6871 };
6872
6873 static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
6874   { { 6 /* art */ }, 'o' },
6875   { { 39 /* mr3 */ }, 'i' }
6876 };
6877
6878 static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
6879   { { 6 /* art */ }, 'i' },
6880   { { 39 /* mr3 */ }, 'o' }
6881 };
6882
6883 static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
6884   { { 6 /* art */ }, 'm' },
6885   { { 39 /* mr3 */ }, 'm' }
6886 };
6887
6888 static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
6889   { { 6 /* art */ }, 'o' }
6890 };
6891
6892 static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
6893   { { STATE_ACC }, 'i' }
6894 };
6895
6896 static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
6897   { { 6 /* art */ }, 'i' }
6898 };
6899
6900 static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
6901   { { STATE_ACC }, 'm' }
6902 };
6903
6904 static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
6905   { { 6 /* art */ }, 'm' }
6906 };
6907
6908 static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
6909   { { STATE_ACC }, 'm' }
6910 };
6911
6912 static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
6913   { { 6 /* art */ }, 'o' }
6914 };
6915
6916 static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
6917   { { STATE_ACC }, 'i' }
6918 };
6919
6920 static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
6921   { { 6 /* art */ }, 'i' }
6922 };
6923
6924 static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
6925   { { STATE_ACC }, 'm' }
6926 };
6927
6928 static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
6929   { { 6 /* art */ }, 'm' }
6930 };
6931
6932 static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
6933   { { STATE_ACC }, 'm' }
6934 };
6935
6936 static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
6937   { { 70 /* s */ }, 'i' }
6938 };
6939
6940 static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
6941   { { STATE_PSWOE }, 'o' },
6942   { { STATE_PSCALLINC }, 'o' },
6943   { { STATE_PSOWB }, 'o' },
6944   { { STATE_PSRING }, 'm' },
6945   { { STATE_PSUM }, 'o' },
6946   { { STATE_PSEXCM }, 'm' },
6947   { { STATE_PSINTLEVEL }, 'o' },
6948   { { STATE_EPC1 }, 'i' },
6949   { { STATE_EPC2 }, 'i' },
6950   { { STATE_EPC3 }, 'i' },
6951   { { STATE_EPC4 }, 'i' },
6952   { { STATE_EPC5 }, 'i' },
6953   { { STATE_EPC6 }, 'i' },
6954   { { STATE_EPC7 }, 'i' },
6955   { { STATE_EPS2 }, 'i' },
6956   { { STATE_EPS3 }, 'i' },
6957   { { STATE_EPS4 }, 'i' },
6958   { { STATE_EPS5 }, 'i' },
6959   { { STATE_EPS6 }, 'i' },
6960   { { STATE_EPS7 }, 'i' },
6961   { { STATE_InOCDMode }, 'm' }
6962 };
6963
6964 static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
6965   { { 70 /* s */ }, 'i' }
6966 };
6967
6968 static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
6969   { { STATE_PSEXCM }, 'i' },
6970   { { STATE_PSRING }, 'i' },
6971   { { STATE_PSINTLEVEL }, 'o' }
6972 };
6973
6974 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
6975   { { 6 /* art */ }, 'o' }
6976 };
6977
6978 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
6979   { { STATE_PSEXCM }, 'i' },
6980   { { STATE_PSRING }, 'i' },
6981   { { STATE_INTERRUPT }, 'i' }
6982 };
6983
6984 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
6985   { { 6 /* art */ }, 'i' }
6986 };
6987
6988 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
6989   { { STATE_PSEXCM }, 'i' },
6990   { { STATE_PSRING }, 'i' },
6991   { { STATE_XTSYNC }, 'o' },
6992   { { STATE_INTERRUPT }, 'm' }
6993 };
6994
6995 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
6996   { { 6 /* art */ }, 'i' }
6997 };
6998
6999 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
7000   { { STATE_PSEXCM }, 'i' },
7001   { { STATE_PSRING }, 'i' },
7002   { { STATE_XTSYNC }, 'o' },
7003   { { STATE_INTERRUPT }, 'm' }
7004 };
7005
7006 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
7007   { { 6 /* art */ }, 'o' }
7008 };
7009
7010 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
7011   { { STATE_PSEXCM }, 'i' },
7012   { { STATE_PSRING }, 'i' },
7013   { { STATE_INTENABLE }, 'i' }
7014 };
7015
7016 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
7017   { { 6 /* art */ }, 'i' }
7018 };
7019
7020 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
7021   { { STATE_PSEXCM }, 'i' },
7022   { { STATE_PSRING }, 'i' },
7023   { { STATE_INTENABLE }, 'o' }
7024 };
7025
7026 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
7027   { { 6 /* art */ }, 'm' }
7028 };
7029
7030 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
7031   { { STATE_PSEXCM }, 'i' },
7032   { { STATE_PSRING }, 'i' },
7033   { { STATE_INTENABLE }, 'm' }
7034 };
7035
7036 static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
7037   { { 41 /* imms */ }, 'i' },
7038   { { 40 /* immt */ }, 'i' }
7039 };
7040
7041 static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
7042   { { STATE_PSEXCM }, 'i' },
7043   { { STATE_PSINTLEVEL }, 'i' }
7044 };
7045
7046 static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
7047   { { 41 /* imms */ }, 'i' }
7048 };
7049
7050 static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
7051   { { STATE_PSEXCM }, 'i' },
7052   { { STATE_PSINTLEVEL }, 'i' }
7053 };
7054
7055 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
7056   { { 6 /* art */ }, 'o' }
7057 };
7058
7059 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
7060   { { STATE_PSEXCM }, 'i' },
7061   { { STATE_PSRING }, 'i' },
7062   { { STATE_DBREAKA0 }, 'i' }
7063 };
7064
7065 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
7066   { { 6 /* art */ }, 'i' }
7067 };
7068
7069 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
7070   { { STATE_PSEXCM }, 'i' },
7071   { { STATE_PSRING }, 'i' },
7072   { { STATE_DBREAKA0 }, 'o' },
7073   { { STATE_XTSYNC }, 'o' }
7074 };
7075
7076 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
7077   { { 6 /* art */ }, 'm' }
7078 };
7079
7080 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
7081   { { STATE_PSEXCM }, 'i' },
7082   { { STATE_PSRING }, 'i' },
7083   { { STATE_DBREAKA0 }, 'm' },
7084   { { STATE_XTSYNC }, 'o' }
7085 };
7086
7087 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
7088   { { 6 /* art */ }, 'o' }
7089 };
7090
7091 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
7092   { { STATE_PSEXCM }, 'i' },
7093   { { STATE_PSRING }, 'i' },
7094   { { STATE_DBREAKC0 }, 'i' }
7095 };
7096
7097 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
7098   { { 6 /* art */ }, 'i' }
7099 };
7100
7101 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
7102   { { STATE_PSEXCM }, 'i' },
7103   { { STATE_PSRING }, 'i' },
7104   { { STATE_DBREAKC0 }, 'o' },
7105   { { STATE_XTSYNC }, 'o' }
7106 };
7107
7108 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
7109   { { 6 /* art */ }, 'm' }
7110 };
7111
7112 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
7113   { { STATE_PSEXCM }, 'i' },
7114   { { STATE_PSRING }, 'i' },
7115   { { STATE_DBREAKC0 }, 'm' },
7116   { { STATE_XTSYNC }, 'o' }
7117 };
7118
7119 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
7120   { { 6 /* art */ }, 'o' }
7121 };
7122
7123 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
7124   { { STATE_PSEXCM }, 'i' },
7125   { { STATE_PSRING }, 'i' },
7126   { { STATE_DBREAKA1 }, 'i' }
7127 };
7128
7129 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
7130   { { 6 /* art */ }, 'i' }
7131 };
7132
7133 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
7134   { { STATE_PSEXCM }, 'i' },
7135   { { STATE_PSRING }, 'i' },
7136   { { STATE_DBREAKA1 }, 'o' },
7137   { { STATE_XTSYNC }, 'o' }
7138 };
7139
7140 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
7141   { { 6 /* art */ }, 'm' }
7142 };
7143
7144 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
7145   { { STATE_PSEXCM }, 'i' },
7146   { { STATE_PSRING }, 'i' },
7147   { { STATE_DBREAKA1 }, 'm' },
7148   { { STATE_XTSYNC }, 'o' }
7149 };
7150
7151 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
7152   { { 6 /* art */ }, 'o' }
7153 };
7154
7155 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
7156   { { STATE_PSEXCM }, 'i' },
7157   { { STATE_PSRING }, 'i' },
7158   { { STATE_DBREAKC1 }, 'i' }
7159 };
7160
7161 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
7162   { { 6 /* art */ }, 'i' }
7163 };
7164
7165 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
7166   { { STATE_PSEXCM }, 'i' },
7167   { { STATE_PSRING }, 'i' },
7168   { { STATE_DBREAKC1 }, 'o' },
7169   { { STATE_XTSYNC }, 'o' }
7170 };
7171
7172 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
7173   { { 6 /* art */ }, 'm' }
7174 };
7175
7176 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
7177   { { STATE_PSEXCM }, 'i' },
7178   { { STATE_PSRING }, 'i' },
7179   { { STATE_DBREAKC1 }, 'm' },
7180   { { STATE_XTSYNC }, 'o' }
7181 };
7182
7183 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
7184   { { 6 /* art */ }, 'o' }
7185 };
7186
7187 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
7188   { { STATE_PSEXCM }, 'i' },
7189   { { STATE_PSRING }, 'i' },
7190   { { STATE_IBREAKA0 }, 'i' }
7191 };
7192
7193 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
7194   { { 6 /* art */ }, 'i' }
7195 };
7196
7197 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
7198   { { STATE_PSEXCM }, 'i' },
7199   { { STATE_PSRING }, 'i' },
7200   { { STATE_IBREAKA0 }, 'o' }
7201 };
7202
7203 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
7204   { { 6 /* art */ }, 'm' }
7205 };
7206
7207 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
7208   { { STATE_PSEXCM }, 'i' },
7209   { { STATE_PSRING }, 'i' },
7210   { { STATE_IBREAKA0 }, 'm' }
7211 };
7212
7213 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
7214   { { 6 /* art */ }, 'o' }
7215 };
7216
7217 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
7218   { { STATE_PSEXCM }, 'i' },
7219   { { STATE_PSRING }, 'i' },
7220   { { STATE_IBREAKA1 }, 'i' }
7221 };
7222
7223 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
7224   { { 6 /* art */ }, 'i' }
7225 };
7226
7227 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
7228   { { STATE_PSEXCM }, 'i' },
7229   { { STATE_PSRING }, 'i' },
7230   { { STATE_IBREAKA1 }, 'o' }
7231 };
7232
7233 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
7234   { { 6 /* art */ }, 'm' }
7235 };
7236
7237 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
7238   { { STATE_PSEXCM }, 'i' },
7239   { { STATE_PSRING }, 'i' },
7240   { { STATE_IBREAKA1 }, 'm' }
7241 };
7242
7243 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
7244   { { 6 /* art */ }, 'o' }
7245 };
7246
7247 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
7248   { { STATE_PSEXCM }, 'i' },
7249   { { STATE_PSRING }, 'i' },
7250   { { STATE_IBREAKENABLE }, 'i' }
7251 };
7252
7253 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
7254   { { 6 /* art */ }, 'i' }
7255 };
7256
7257 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
7258   { { STATE_PSEXCM }, 'i' },
7259   { { STATE_PSRING }, 'i' },
7260   { { STATE_IBREAKENABLE }, 'o' }
7261 };
7262
7263 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
7264   { { 6 /* art */ }, 'm' }
7265 };
7266
7267 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
7268   { { STATE_PSEXCM }, 'i' },
7269   { { STATE_PSRING }, 'i' },
7270   { { STATE_IBREAKENABLE }, 'm' }
7271 };
7272
7273 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
7274   { { 6 /* art */ }, 'o' }
7275 };
7276
7277 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
7278   { { STATE_PSEXCM }, 'i' },
7279   { { STATE_PSRING }, 'i' },
7280   { { STATE_DEBUGCAUSE }, 'i' },
7281   { { STATE_DBNUM }, 'i' }
7282 };
7283
7284 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
7285   { { 6 /* art */ }, 'i' }
7286 };
7287
7288 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
7289   { { STATE_PSEXCM }, 'i' },
7290   { { STATE_PSRING }, 'i' },
7291   { { STATE_DEBUGCAUSE }, 'o' },
7292   { { STATE_DBNUM }, 'o' }
7293 };
7294
7295 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
7296   { { 6 /* art */ }, 'm' }
7297 };
7298
7299 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
7300   { { STATE_PSEXCM }, 'i' },
7301   { { STATE_PSRING }, 'i' },
7302   { { STATE_DEBUGCAUSE }, 'm' },
7303   { { STATE_DBNUM }, 'm' }
7304 };
7305
7306 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
7307   { { 6 /* art */ }, 'o' }
7308 };
7309
7310 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
7311   { { STATE_PSEXCM }, 'i' },
7312   { { STATE_PSRING }, 'i' },
7313   { { STATE_ICOUNT }, 'i' }
7314 };
7315
7316 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
7317   { { 6 /* art */ }, 'i' }
7318 };
7319
7320 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
7321   { { STATE_PSEXCM }, 'i' },
7322   { { STATE_PSRING }, 'i' },
7323   { { STATE_XTSYNC }, 'o' },
7324   { { STATE_ICOUNT }, 'o' }
7325 };
7326
7327 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
7328   { { 6 /* art */ }, 'm' }
7329 };
7330
7331 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
7332   { { STATE_PSEXCM }, 'i' },
7333   { { STATE_PSRING }, 'i' },
7334   { { STATE_XTSYNC }, 'o' },
7335   { { STATE_ICOUNT }, 'm' }
7336 };
7337
7338 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
7339   { { 6 /* art */ }, 'o' }
7340 };
7341
7342 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
7343   { { STATE_PSEXCM }, 'i' },
7344   { { STATE_PSRING }, 'i' },
7345   { { STATE_ICOUNTLEVEL }, 'i' }
7346 };
7347
7348 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
7349   { { 6 /* art */ }, 'i' }
7350 };
7351
7352 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
7353   { { STATE_PSEXCM }, 'i' },
7354   { { STATE_PSRING }, 'i' },
7355   { { STATE_ICOUNTLEVEL }, 'o' }
7356 };
7357
7358 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
7359   { { 6 /* art */ }, 'm' }
7360 };
7361
7362 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
7363   { { STATE_PSEXCM }, 'i' },
7364   { { STATE_PSRING }, 'i' },
7365   { { STATE_ICOUNTLEVEL }, 'm' }
7366 };
7367
7368 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
7369   { { 6 /* art */ }, 'o' }
7370 };
7371
7372 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
7373   { { STATE_PSEXCM }, 'i' },
7374   { { STATE_PSRING }, 'i' },
7375   { { STATE_DDR }, 'i' }
7376 };
7377
7378 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
7379   { { 6 /* art */ }, 'i' }
7380 };
7381
7382 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
7383   { { STATE_PSEXCM }, 'i' },
7384   { { STATE_PSRING }, 'i' },
7385   { { STATE_XTSYNC }, 'o' },
7386   { { STATE_DDR }, 'o' }
7387 };
7388
7389 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
7390   { { 6 /* art */ }, 'm' }
7391 };
7392
7393 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
7394   { { STATE_PSEXCM }, 'i' },
7395   { { STATE_PSRING }, 'i' },
7396   { { STATE_XTSYNC }, 'o' },
7397   { { STATE_DDR }, 'm' }
7398 };
7399
7400 static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
7401   { { 41 /* imms */ }, 'i' }
7402 };
7403
7404 static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
7405   { { STATE_InOCDMode }, 'm' },
7406   { { STATE_EPC6 }, 'i' },
7407   { { STATE_PSWOE }, 'o' },
7408   { { STATE_PSCALLINC }, 'o' },
7409   { { STATE_PSOWB }, 'o' },
7410   { { STATE_PSRING }, 'o' },
7411   { { STATE_PSUM }, 'o' },
7412   { { STATE_PSEXCM }, 'o' },
7413   { { STATE_PSINTLEVEL }, 'o' },
7414   { { STATE_EPS6 }, 'i' }
7415 };
7416
7417 static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
7418   { { STATE_InOCDMode }, 'm' }
7419 };
7420
7421 static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
7422   { { 6 /* art */ }, 'i' }
7423 };
7424
7425 static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
7426   { { STATE_PSEXCM }, 'i' },
7427   { { STATE_PSRING }, 'i' },
7428   { { STATE_XTSYNC }, 'o' }
7429 };
7430
7431 static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = {
7432   { { 44 /* br */ }, 'o' },
7433   { { 43 /* bs */ }, 'i' },
7434   { { 42 /* bt */ }, 'i' }
7435 };
7436
7437 static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = {
7438   { { 42 /* bt */ }, 'o' },
7439   { { 49 /* bs4 */ }, 'i' }
7440 };
7441
7442 static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = {
7443   { { 42 /* bt */ }, 'o' },
7444   { { 52 /* bs8 */ }, 'i' }
7445 };
7446
7447 static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = {
7448   { { 43 /* bs */ }, 'i' },
7449   { { 28 /* label8 */ }, 'i' }
7450 };
7451
7452 static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = {
7453   { { 3 /* arr */ }, 'm' },
7454   { { 4 /* ars */ }, 'i' },
7455   { { 42 /* bt */ }, 'i' }
7456 };
7457
7458 static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = {
7459   { { 6 /* art */ }, 'o' },
7460   { { 57 /* brall */ }, 'i' }
7461 };
7462
7463 static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = {
7464   { { 6 /* art */ }, 'i' },
7465   { { 57 /* brall */ }, 'o' }
7466 };
7467
7468 static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = {
7469   { { 6 /* art */ }, 'm' },
7470   { { 57 /* brall */ }, 'm' }
7471 };
7472
7473 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
7474   { { 6 /* art */ }, 'o' }
7475 };
7476
7477 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
7478   { { STATE_PSEXCM }, 'i' },
7479   { { STATE_PSRING }, 'i' },
7480   { { STATE_CCOUNT }, 'i' }
7481 };
7482
7483 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
7484   { { 6 /* art */ }, 'i' }
7485 };
7486
7487 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
7488   { { STATE_PSEXCM }, 'i' },
7489   { { STATE_PSRING }, 'i' },
7490   { { STATE_XTSYNC }, 'o' },
7491   { { STATE_CCOUNT }, 'o' }
7492 };
7493
7494 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
7495   { { 6 /* art */ }, 'm' }
7496 };
7497
7498 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
7499   { { STATE_PSEXCM }, 'i' },
7500   { { STATE_PSRING }, 'i' },
7501   { { STATE_XTSYNC }, 'o' },
7502   { { STATE_CCOUNT }, 'm' }
7503 };
7504
7505 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
7506   { { 6 /* art */ }, 'o' }
7507 };
7508
7509 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
7510   { { STATE_PSEXCM }, 'i' },
7511   { { STATE_PSRING }, 'i' },
7512   { { STATE_CCOMPARE0 }, 'i' }
7513 };
7514
7515 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
7516   { { 6 /* art */ }, 'i' }
7517 };
7518
7519 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
7520   { { STATE_PSEXCM }, 'i' },
7521   { { STATE_PSRING }, 'i' },
7522   { { STATE_CCOMPARE0 }, 'o' },
7523   { { STATE_INTERRUPT }, 'm' }
7524 };
7525
7526 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
7527   { { 6 /* art */ }, 'm' }
7528 };
7529
7530 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
7531   { { STATE_PSEXCM }, 'i' },
7532   { { STATE_PSRING }, 'i' },
7533   { { STATE_CCOMPARE0 }, 'm' },
7534   { { STATE_INTERRUPT }, 'm' }
7535 };
7536
7537 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
7538   { { 6 /* art */ }, 'o' }
7539 };
7540
7541 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
7542   { { STATE_PSEXCM }, 'i' },
7543   { { STATE_PSRING }, 'i' },
7544   { { STATE_CCOMPARE1 }, 'i' }
7545 };
7546
7547 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
7548   { { 6 /* art */ }, 'i' }
7549 };
7550
7551 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
7552   { { STATE_PSEXCM }, 'i' },
7553   { { STATE_PSRING }, 'i' },
7554   { { STATE_CCOMPARE1 }, 'o' },
7555   { { STATE_INTERRUPT }, 'm' }
7556 };
7557
7558 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
7559   { { 6 /* art */ }, 'm' }
7560 };
7561
7562 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
7563   { { STATE_PSEXCM }, 'i' },
7564   { { STATE_PSRING }, 'i' },
7565   { { STATE_CCOMPARE1 }, 'm' },
7566   { { STATE_INTERRUPT }, 'm' }
7567 };
7568
7569 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
7570   { { 6 /* art */ }, 'o' }
7571 };
7572
7573 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
7574   { { STATE_PSEXCM }, 'i' },
7575   { { STATE_PSRING }, 'i' },
7576   { { STATE_CCOMPARE2 }, 'i' }
7577 };
7578
7579 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
7580   { { 6 /* art */ }, 'i' }
7581 };
7582
7583 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
7584   { { STATE_PSEXCM }, 'i' },
7585   { { STATE_PSRING }, 'i' },
7586   { { STATE_CCOMPARE2 }, 'o' },
7587   { { STATE_INTERRUPT }, 'm' }
7588 };
7589
7590 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
7591   { { 6 /* art */ }, 'm' }
7592 };
7593
7594 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
7595   { { STATE_PSEXCM }, 'i' },
7596   { { STATE_PSRING }, 'i' },
7597   { { STATE_CCOMPARE2 }, 'm' },
7598   { { STATE_INTERRUPT }, 'm' }
7599 };
7600
7601 static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
7602   { { 4 /* ars */ }, 'i' },
7603   { { 21 /* uimm8x4 */ }, 'i' }
7604 };
7605
7606 static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = {
7607   { { 4 /* ars */ }, 'i' },
7608   { { 22 /* uimm4x16 */ }, 'i' }
7609 };
7610
7611 static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = {
7612   { { STATE_PSEXCM }, 'i' },
7613   { { STATE_PSRING }, 'i' }
7614 };
7615
7616 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
7617   { { 4 /* ars */ }, 'i' },
7618   { { 21 /* uimm8x4 */ }, 'i' }
7619 };
7620
7621 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
7622   { { STATE_PSEXCM }, 'i' },
7623   { { STATE_PSRING }, 'i' }
7624 };
7625
7626 static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
7627   { { 6 /* art */ }, 'o' },
7628   { { 4 /* ars */ }, 'i' }
7629 };
7630
7631 static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
7632   { { STATE_PSEXCM }, 'i' },
7633   { { STATE_PSRING }, 'i' }
7634 };
7635
7636 static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
7637   { { 6 /* art */ }, 'i' },
7638   { { 4 /* ars */ }, 'i' }
7639 };
7640
7641 static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
7642   { { STATE_PSEXCM }, 'i' },
7643   { { STATE_PSRING }, 'i' }
7644 };
7645
7646 static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
7647   { { 4 /* ars */ }, 'i' },
7648   { { 21 /* uimm8x4 */ }, 'i' }
7649 };
7650
7651 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
7652   { { 4 /* ars */ }, 'i' },
7653   { { 22 /* uimm4x16 */ }, 'i' }
7654 };
7655
7656 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
7657   { { STATE_PSEXCM }, 'i' },
7658   { { STATE_PSRING }, 'i' }
7659 };
7660
7661 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
7662   { { 4 /* ars */ }, 'i' },
7663   { { 21 /* uimm8x4 */ }, 'i' }
7664 };
7665
7666 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
7667   { { STATE_PSEXCM }, 'i' },
7668   { { STATE_PSRING }, 'i' }
7669 };
7670
7671 static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
7672   { { 4 /* ars */ }, 'i' },
7673   { { 21 /* uimm8x4 */ }, 'i' }
7674 };
7675
7676 static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = {
7677   { { 4 /* ars */ }, 'i' },
7678   { { 22 /* uimm4x16 */ }, 'i' }
7679 };
7680
7681 static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = {
7682   { { STATE_PSEXCM }, 'i' },
7683   { { STATE_PSRING }, 'i' }
7684 };
7685
7686 static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
7687   { { 6 /* art */ }, 'i' },
7688   { { 4 /* ars */ }, 'i' }
7689 };
7690
7691 static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
7692   { { STATE_PSEXCM }, 'i' },
7693   { { STATE_PSRING }, 'i' }
7694 };
7695
7696 static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
7697   { { 6 /* art */ }, 'o' },
7698   { { 4 /* ars */ }, 'i' }
7699 };
7700
7701 static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
7702   { { STATE_PSEXCM }, 'i' },
7703   { { STATE_PSRING }, 'i' }
7704 };
7705
7706 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
7707   { { 6 /* art */ }, 'i' }
7708 };
7709
7710 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
7711   { { STATE_PSEXCM }, 'i' },
7712   { { STATE_PSRING }, 'i' },
7713   { { STATE_PTBASE }, 'o' },
7714   { { STATE_XTSYNC }, 'o' }
7715 };
7716
7717 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
7718   { { 6 /* art */ }, 'o' }
7719 };
7720
7721 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
7722   { { STATE_PSEXCM }, 'i' },
7723   { { STATE_PSRING }, 'i' },
7724   { { STATE_PTBASE }, 'i' },
7725   { { STATE_EXCVADDR }, 'i' }
7726 };
7727
7728 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
7729   { { 6 /* art */ }, 'm' }
7730 };
7731
7732 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
7733   { { STATE_PSEXCM }, 'i' },
7734   { { STATE_PSRING }, 'i' },
7735   { { STATE_PTBASE }, 'm' },
7736   { { STATE_EXCVADDR }, 'i' },
7737   { { STATE_XTSYNC }, 'o' }
7738 };
7739
7740 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
7741   { { 6 /* art */ }, 'o' }
7742 };
7743
7744 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
7745   { { STATE_PSEXCM }, 'i' },
7746   { { STATE_PSRING }, 'i' },
7747   { { STATE_ASID3 }, 'i' },
7748   { { STATE_ASID2 }, 'i' },
7749   { { STATE_ASID1 }, 'i' }
7750 };
7751
7752 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
7753   { { 6 /* art */ }, 'i' }
7754 };
7755
7756 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
7757   { { STATE_XTSYNC }, 'o' },
7758   { { STATE_PSEXCM }, 'i' },
7759   { { STATE_PSRING }, 'i' },
7760   { { STATE_ASID3 }, 'o' },
7761   { { STATE_ASID2 }, 'o' },
7762   { { STATE_ASID1 }, 'o' }
7763 };
7764
7765 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
7766   { { 6 /* art */ }, 'm' }
7767 };
7768
7769 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
7770   { { STATE_XTSYNC }, 'o' },
7771   { { STATE_PSEXCM }, 'i' },
7772   { { STATE_PSRING }, 'i' },
7773   { { STATE_ASID3 }, 'm' },
7774   { { STATE_ASID2 }, 'm' },
7775   { { STATE_ASID1 }, 'm' }
7776 };
7777
7778 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
7779   { { 6 /* art */ }, 'o' }
7780 };
7781
7782 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
7783   { { STATE_PSEXCM }, 'i' },
7784   { { STATE_PSRING }, 'i' },
7785   { { STATE_INSTPGSZID4 }, 'i' }
7786 };
7787
7788 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
7789   { { 6 /* art */ }, 'i' }
7790 };
7791
7792 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
7793   { { STATE_XTSYNC }, 'o' },
7794   { { STATE_PSEXCM }, 'i' },
7795   { { STATE_PSRING }, 'i' },
7796   { { STATE_INSTPGSZID4 }, 'o' }
7797 };
7798
7799 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
7800   { { 6 /* art */ }, 'm' }
7801 };
7802
7803 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
7804   { { STATE_XTSYNC }, 'o' },
7805   { { STATE_PSEXCM }, 'i' },
7806   { { STATE_PSRING }, 'i' },
7807   { { STATE_INSTPGSZID4 }, 'm' }
7808 };
7809
7810 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
7811   { { 6 /* art */ }, 'o' }
7812 };
7813
7814 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
7815   { { STATE_PSEXCM }, 'i' },
7816   { { STATE_PSRING }, 'i' },
7817   { { STATE_DATAPGSZID4 }, 'i' }
7818 };
7819
7820 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
7821   { { 6 /* art */ }, 'i' }
7822 };
7823
7824 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
7825   { { STATE_XTSYNC }, 'o' },
7826   { { STATE_PSEXCM }, 'i' },
7827   { { STATE_PSRING }, 'i' },
7828   { { STATE_DATAPGSZID4 }, 'o' }
7829 };
7830
7831 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
7832   { { 6 /* art */ }, 'm' }
7833 };
7834
7835 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
7836   { { STATE_XTSYNC }, 'o' },
7837   { { STATE_PSEXCM }, 'i' },
7838   { { STATE_PSRING }, 'i' },
7839   { { STATE_DATAPGSZID4 }, 'm' }
7840 };
7841
7842 static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
7843   { { 4 /* ars */ }, 'i' }
7844 };
7845
7846 static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
7847   { { STATE_PSEXCM }, 'i' },
7848   { { STATE_PSRING }, 'i' },
7849   { { STATE_XTSYNC }, 'o' }
7850 };
7851
7852 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
7853   { { 6 /* art */ }, 'o' },
7854   { { 4 /* ars */ }, 'i' }
7855 };
7856
7857 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
7858   { { STATE_PSEXCM }, 'i' },
7859   { { STATE_PSRING }, 'i' }
7860 };
7861
7862 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
7863   { { 6 /* art */ }, 'i' },
7864   { { 4 /* ars */ }, 'i' }
7865 };
7866
7867 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
7868   { { STATE_PSEXCM }, 'i' },
7869   { { STATE_PSRING }, 'i' },
7870   { { STATE_XTSYNC }, 'o' }
7871 };
7872
7873 static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
7874   { { 4 /* ars */ }, 'i' }
7875 };
7876
7877 static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
7878   { { STATE_PSEXCM }, 'i' },
7879   { { STATE_PSRING }, 'i' }
7880 };
7881
7882 static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
7883   { { 6 /* art */ }, 'o' },
7884   { { 4 /* ars */ }, 'i' }
7885 };
7886
7887 static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
7888   { { STATE_PSEXCM }, 'i' },
7889   { { STATE_PSRING }, 'i' }
7890 };
7891
7892 static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
7893   { { 6 /* art */ }, 'i' },
7894   { { 4 /* ars */ }, 'i' }
7895 };
7896
7897 static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
7898   { { STATE_PSEXCM }, 'i' },
7899   { { STATE_PSRING }, 'i' }
7900 };
7901
7902 static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
7903   { { STATE_PTBASE }, 'i' },
7904   { { STATE_EXCVADDR }, 'i' }
7905 };
7906
7907 static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
7908   { { STATE_EXCVADDR }, 'i' }
7909 };
7910
7911 static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
7912   { { STATE_EXCVADDR }, 'i' }
7913 };
7914
7915 static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
7916   { { 6 /* art */ }, 'o' }
7917 };
7918
7919 static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
7920   { { STATE_PSEXCM }, 'i' },
7921   { { STATE_PSRING }, 'i' },
7922   { { STATE_CPENABLE }, 'i' }
7923 };
7924
7925 static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
7926   { { 6 /* art */ }, 'i' }
7927 };
7928
7929 static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
7930   { { STATE_PSEXCM }, 'i' },
7931   { { STATE_PSRING }, 'i' },
7932   { { STATE_CPENABLE }, 'o' }
7933 };
7934
7935 static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
7936   { { 6 /* art */ }, 'm' }
7937 };
7938
7939 static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
7940   { { STATE_PSEXCM }, 'i' },
7941   { { STATE_PSRING }, 'i' },
7942   { { STATE_CPENABLE }, 'm' }
7943 };
7944
7945 static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
7946   { { 3 /* arr */ }, 'o' },
7947   { { 4 /* ars */ }, 'i' },
7948   { { 58 /* tp7 */ }, 'i' }
7949 };
7950
7951 static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
7952   { { 3 /* arr */ }, 'o' },
7953   { { 4 /* ars */ }, 'i' },
7954   { { 6 /* art */ }, 'i' }
7955 };
7956
7957 static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
7958   { { 6 /* art */ }, 'o' },
7959   { { 4 /* ars */ }, 'i' }
7960 };
7961
7962 static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
7963   { { 3 /* arr */ }, 'o' },
7964   { { 4 /* ars */ }, 'i' },
7965   { { 58 /* tp7 */ }, 'i' }
7966 };
7967
7968 static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
7969   { { 6 /* art */ }, 'o' },
7970   { { 4 /* ars */ }, 'i' },
7971   { { 21 /* uimm8x4 */ }, 'i' }
7972 };
7973
7974 static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
7975   { { 6 /* art */ }, 'i' },
7976   { { 4 /* ars */ }, 'i' },
7977   { { 21 /* uimm8x4 */ }, 'i' }
7978 };
7979
7980 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
7981   { { 6 /* art */ }, 'm' },
7982   { { 4 /* ars */ }, 'i' },
7983   { { 21 /* uimm8x4 */ }, 'i' }
7984 };
7985
7986 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
7987   { { STATE_SCOMPARE1 }, 'i' },
7988   { { STATE_SCOMPARE1 }, 'i' }
7989 };
7990
7991 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
7992   { { 6 /* art */ }, 'o' }
7993 };
7994
7995 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
7996   { { STATE_SCOMPARE1 }, 'i' }
7997 };
7998
7999 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
8000   { { 6 /* art */ }, 'i' }
8001 };
8002
8003 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
8004   { { STATE_SCOMPARE1 }, 'o' }
8005 };
8006
8007 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
8008   { { 6 /* art */ }, 'm' }
8009 };
8010
8011 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
8012   { { STATE_SCOMPARE1 }, 'm' }
8013 };
8014
8015 static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
8016   { { 3 /* arr */ }, 'o' },
8017   { { 4 /* ars */ }, 'i' },
8018   { { 6 /* art */ }, 'i' }
8019 };
8020
8021 static xtensa_arg_internal Iclass_xt_mul32_args[] = {
8022   { { 3 /* arr */ }, 'o' },
8023   { { 4 /* ars */ }, 'i' },
8024   { { 6 /* art */ }, 'i' }
8025 };
8026
8027 static xtensa_arg_internal Iclass_rur_fcr_args[] = {
8028   { { 3 /* arr */ }, 'o' }
8029 };
8030
8031 static xtensa_arg_internal Iclass_rur_fcr_stateArgs[] = {
8032   { { STATE_RoundMode }, 'i' },
8033   { { STATE_InvalidEnable }, 'i' },
8034   { { STATE_DivZeroEnable }, 'i' },
8035   { { STATE_OverflowEnable }, 'i' },
8036   { { STATE_UnderflowEnable }, 'i' },
8037   { { STATE_InexactEnable }, 'i' },
8038   { { STATE_FPreserved20 }, 'i' },
8039   { { STATE_FPreserved5 }, 'i' },
8040   { { STATE_CPENABLE }, 'i' }
8041 };
8042
8043 static xtensa_arg_internal Iclass_wur_fcr_args[] = {
8044   { { 6 /* art */ }, 'i' }
8045 };
8046
8047 static xtensa_arg_internal Iclass_wur_fcr_stateArgs[] = {
8048   { { STATE_RoundMode }, 'o' },
8049   { { STATE_InvalidEnable }, 'o' },
8050   { { STATE_DivZeroEnable }, 'o' },
8051   { { STATE_OverflowEnable }, 'o' },
8052   { { STATE_UnderflowEnable }, 'o' },
8053   { { STATE_InexactEnable }, 'o' },
8054   { { STATE_FPreserved20 }, 'o' },
8055   { { STATE_FPreserved5 }, 'o' },
8056   { { STATE_CPENABLE }, 'i' }
8057 };
8058
8059 static xtensa_arg_internal Iclass_rur_fsr_args[] = {
8060   { { 3 /* arr */ }, 'o' }
8061 };
8062
8063 static xtensa_arg_internal Iclass_rur_fsr_stateArgs[] = {
8064   { { STATE_InvalidFlag }, 'i' },
8065   { { STATE_DivZeroFlag }, 'i' },
8066   { { STATE_OverflowFlag }, 'i' },
8067   { { STATE_UnderflowFlag }, 'i' },
8068   { { STATE_InexactFlag }, 'i' },
8069   { { STATE_FPreserved20a }, 'i' },
8070   { { STATE_FPreserved7 }, 'i' },
8071   { { STATE_CPENABLE }, 'i' }
8072 };
8073
8074 static xtensa_arg_internal Iclass_wur_fsr_args[] = {
8075   { { 6 /* art */ }, 'i' }
8076 };
8077
8078 static xtensa_arg_internal Iclass_wur_fsr_stateArgs[] = {
8079   { { STATE_InvalidFlag }, 'o' },
8080   { { STATE_DivZeroFlag }, 'o' },
8081   { { STATE_OverflowFlag }, 'o' },
8082   { { STATE_UnderflowFlag }, 'o' },
8083   { { STATE_InexactFlag }, 'o' },
8084   { { STATE_FPreserved20a }, 'o' },
8085   { { STATE_FPreserved7 }, 'o' },
8086   { { STATE_CPENABLE }, 'i' }
8087 };
8088
8089 static xtensa_arg_internal Iclass_fp_args[] = {
8090   { { 62 /* frr */ }, 'o' },
8091   { { 63 /* frs */ }, 'i' },
8092   { { 64 /* frt */ }, 'i' }
8093 };
8094
8095 static xtensa_arg_internal Iclass_fp_stateArgs[] = {
8096   { { STATE_RoundMode }, 'i' },
8097   { { STATE_CPENABLE }, 'i' }
8098 };
8099
8100 static xtensa_arg_internal Iclass_fp_mac_args[] = {
8101   { { 62 /* frr */ }, 'm' },
8102   { { 63 /* frs */ }, 'i' },
8103   { { 64 /* frt */ }, 'i' }
8104 };
8105
8106 static xtensa_arg_internal Iclass_fp_mac_stateArgs[] = {
8107   { { STATE_RoundMode }, 'i' },
8108   { { STATE_CPENABLE }, 'i' }
8109 };
8110
8111 static xtensa_arg_internal Iclass_fp_cmov_args[] = {
8112   { { 62 /* frr */ }, 'm' },
8113   { { 63 /* frs */ }, 'i' },
8114   { { 42 /* bt */ }, 'i' }
8115 };
8116
8117 static xtensa_arg_internal Iclass_fp_cmov_stateArgs[] = {
8118   { { STATE_CPENABLE }, 'i' }
8119 };
8120
8121 static xtensa_arg_internal Iclass_fp_mov_args[] = {
8122   { { 62 /* frr */ }, 'm' },
8123   { { 63 /* frs */ }, 'i' },
8124   { { 6 /* art */ }, 'i' }
8125 };
8126
8127 static xtensa_arg_internal Iclass_fp_mov_stateArgs[] = {
8128   { { STATE_CPENABLE }, 'i' }
8129 };
8130
8131 static xtensa_arg_internal Iclass_fp_mov2_args[] = {
8132   { { 62 /* frr */ }, 'o' },
8133   { { 63 /* frs */ }, 'i' }
8134 };
8135
8136 static xtensa_arg_internal Iclass_fp_mov2_stateArgs[] = {
8137   { { STATE_CPENABLE }, 'i' }
8138 };
8139
8140 static xtensa_arg_internal Iclass_fp_cmp_args[] = {
8141   { { 44 /* br */ }, 'o' },
8142   { { 63 /* frs */ }, 'i' },
8143   { { 64 /* frt */ }, 'i' }
8144 };
8145
8146 static xtensa_arg_internal Iclass_fp_cmp_stateArgs[] = {
8147   { { STATE_CPENABLE }, 'i' }
8148 };
8149
8150 static xtensa_arg_internal Iclass_fp_float_args[] = {
8151   { { 62 /* frr */ }, 'o' },
8152   { { 4 /* ars */ }, 'i' },
8153   { { 65 /* t */ }, 'i' }
8154 };
8155
8156 static xtensa_arg_internal Iclass_fp_float_stateArgs[] = {
8157   { { STATE_RoundMode }, 'i' },
8158   { { STATE_CPENABLE }, 'i' }
8159 };
8160
8161 static xtensa_arg_internal Iclass_fp_int_args[] = {
8162   { { 3 /* arr */ }, 'o' },
8163   { { 63 /* frs */ }, 'i' },
8164   { { 65 /* t */ }, 'i' }
8165 };
8166
8167 static xtensa_arg_internal Iclass_fp_int_stateArgs[] = {
8168   { { STATE_CPENABLE }, 'i' }
8169 };
8170
8171 static xtensa_arg_internal Iclass_fp_rfr_args[] = {
8172   { { 3 /* arr */ }, 'o' },
8173   { { 63 /* frs */ }, 'i' }
8174 };
8175
8176 static xtensa_arg_internal Iclass_fp_rfr_stateArgs[] = {
8177   { { STATE_CPENABLE }, 'i' }
8178 };
8179
8180 static xtensa_arg_internal Iclass_fp_wfr_args[] = {
8181   { { 62 /* frr */ }, 'o' },
8182   { { 4 /* ars */ }, 'i' }
8183 };
8184
8185 static xtensa_arg_internal Iclass_fp_wfr_stateArgs[] = {
8186   { { STATE_CPENABLE }, 'i' }
8187 };
8188
8189 static xtensa_arg_internal Iclass_fp_lsi_args[] = {
8190   { { 64 /* frt */ }, 'o' },
8191   { { 4 /* ars */ }, 'i' },
8192   { { 61 /* cimm8x4 */ }, 'i' }
8193 };
8194
8195 static xtensa_arg_internal Iclass_fp_lsi_stateArgs[] = {
8196   { { STATE_CPENABLE }, 'i' }
8197 };
8198
8199 static xtensa_arg_internal Iclass_fp_lsiu_args[] = {
8200   { { 64 /* frt */ }, 'o' },
8201   { { 4 /* ars */ }, 'm' },
8202   { { 61 /* cimm8x4 */ }, 'i' }
8203 };
8204
8205 static xtensa_arg_internal Iclass_fp_lsiu_stateArgs[] = {
8206   { { STATE_CPENABLE }, 'i' }
8207 };
8208
8209 static xtensa_arg_internal Iclass_fp_lsx_args[] = {
8210   { { 62 /* frr */ }, 'o' },
8211   { { 4 /* ars */ }, 'i' },
8212   { { 6 /* art */ }, 'i' }
8213 };
8214
8215 static xtensa_arg_internal Iclass_fp_lsx_stateArgs[] = {
8216   { { STATE_CPENABLE }, 'i' }
8217 };
8218
8219 static xtensa_arg_internal Iclass_fp_lsxu_args[] = {
8220   { { 62 /* frr */ }, 'o' },
8221   { { 4 /* ars */ }, 'm' },
8222   { { 6 /* art */ }, 'i' }
8223 };
8224
8225 static xtensa_arg_internal Iclass_fp_lsxu_stateArgs[] = {
8226   { { STATE_CPENABLE }, 'i' }
8227 };
8228
8229 static xtensa_arg_internal Iclass_fp_ssi_args[] = {
8230   { { 64 /* frt */ }, 'i' },
8231   { { 4 /* ars */ }, 'i' },
8232   { { 61 /* cimm8x4 */ }, 'i' }
8233 };
8234
8235 static xtensa_arg_internal Iclass_fp_ssi_stateArgs[] = {
8236   { { STATE_CPENABLE }, 'i' }
8237 };
8238
8239 static xtensa_arg_internal Iclass_fp_ssiu_args[] = {
8240   { { 64 /* frt */ }, 'i' },
8241   { { 4 /* ars */ }, 'm' },
8242   { { 61 /* cimm8x4 */ }, 'i' }
8243 };
8244
8245 static xtensa_arg_internal Iclass_fp_ssiu_stateArgs[] = {
8246   { { STATE_CPENABLE }, 'i' }
8247 };
8248
8249 static xtensa_arg_internal Iclass_fp_ssx_args[] = {
8250   { { 62 /* frr */ }, 'i' },
8251   { { 4 /* ars */ }, 'i' },
8252   { { 6 /* art */ }, 'i' }
8253 };
8254
8255 static xtensa_arg_internal Iclass_fp_ssx_stateArgs[] = {
8256   { { STATE_CPENABLE }, 'i' }
8257 };
8258
8259 static xtensa_arg_internal Iclass_fp_ssxu_args[] = {
8260   { { 62 /* frr */ }, 'i' },
8261   { { 4 /* ars */ }, 'm' },
8262   { { 6 /* art */ }, 'i' }
8263 };
8264
8265 static xtensa_arg_internal Iclass_fp_ssxu_stateArgs[] = {
8266   { { STATE_CPENABLE }, 'i' }
8267 };
8268
8269 static xtensa_arg_internal Iclass_xt_iclass_wb18_0_args[] = {
8270   { { 4 /* ars */ }, 'i' },
8271   { { 60 /* xt_wbr18_label */ }, 'i' }
8272 };
8273
8274 static xtensa_arg_internal Iclass_xt_iclass_wb18_1_args[] = {
8275   { { 4 /* ars */ }, 'i' },
8276   { { 17 /* b4const */ }, 'i' },
8277   { { 60 /* xt_wbr18_label */ }, 'i' }
8278 };
8279
8280 static xtensa_arg_internal Iclass_xt_iclass_wb18_2_args[] = {
8281   { { 4 /* ars */ }, 'i' },
8282   { { 18 /* b4constu */ }, 'i' },
8283   { { 60 /* xt_wbr18_label */ }, 'i' }
8284 };
8285
8286 static xtensa_arg_internal Iclass_xt_iclass_wb18_3_args[] = {
8287   { { 4 /* ars */ }, 'i' },
8288   { { 67 /* bbi */ }, 'i' },
8289   { { 60 /* xt_wbr18_label */ }, 'i' }
8290 };
8291
8292 static xtensa_arg_internal Iclass_xt_iclass_wb18_4_args[] = {
8293   { { 4 /* ars */ }, 'i' },
8294   { { 6 /* art */ }, 'i' },
8295   { { 60 /* xt_wbr18_label */ }, 'i' }
8296 };
8297
8298 static xtensa_iclass_internal iclasses[] = {
8299   { 0, 0 /* xt_iclass_excw */,
8300     0, 0, 0, 0 },
8301   { 0, 0 /* xt_iclass_rfe */,
8302     3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
8303   { 0, 0 /* xt_iclass_rfde */,
8304     3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
8305   { 0, 0 /* xt_iclass_syscall */,
8306     0, 0, 0, 0 },
8307   { 0, 0 /* xt_iclass_simcall */,
8308     0, 0, 0, 0 },
8309   { 2, Iclass_xt_iclass_call12_args,
8310     1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
8311   { 2, Iclass_xt_iclass_call8_args,
8312     1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
8313   { 2, Iclass_xt_iclass_call4_args,
8314     1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
8315   { 2, Iclass_xt_iclass_callx12_args,
8316     1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
8317   { 2, Iclass_xt_iclass_callx8_args,
8318     1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
8319   { 2, Iclass_xt_iclass_callx4_args,
8320     1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
8321   { 3, Iclass_xt_iclass_entry_args,
8322     5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
8323   { 2, Iclass_xt_iclass_movsp_args,
8324     2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
8325   { 1, Iclass_xt_iclass_rotw_args,
8326     3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
8327   { 1, Iclass_xt_iclass_retw_args,
8328     4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
8329   { 0, 0 /* xt_iclass_rfwou */,
8330     6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
8331   { 3, Iclass_xt_iclass_l32e_args,
8332     2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
8333   { 3, Iclass_xt_iclass_s32e_args,
8334     2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
8335   { 1, Iclass_xt_iclass_rsr_windowbase_args,
8336     3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
8337   { 1, Iclass_xt_iclass_wsr_windowbase_args,
8338     3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
8339   { 1, Iclass_xt_iclass_xsr_windowbase_args,
8340     3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
8341   { 1, Iclass_xt_iclass_rsr_windowstart_args,
8342     3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
8343   { 1, Iclass_xt_iclass_wsr_windowstart_args,
8344     3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
8345   { 1, Iclass_xt_iclass_xsr_windowstart_args,
8346     3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
8347   { 3, Iclass_xt_iclass_add_n_args,
8348     0, 0, 0, 0 },
8349   { 3, Iclass_xt_iclass_addi_n_args,
8350     0, 0, 0, 0 },
8351   { 2, Iclass_xt_iclass_bz6_args,
8352     0, 0, 0, 0 },
8353   { 0, 0 /* xt_iclass_ill_n */,
8354     0, 0, 0, 0 },
8355   { 3, Iclass_xt_iclass_loadi4_args,
8356     0, 0, 0, 0 },
8357   { 2, Iclass_xt_iclass_mov_n_args,
8358     0, 0, 0, 0 },
8359   { 2, Iclass_xt_iclass_movi_n_args,
8360     0, 0, 0, 0 },
8361   { 0, 0 /* xt_iclass_nopn */,
8362     0, 0, 0, 0 },
8363   { 1, Iclass_xt_iclass_retn_args,
8364     0, 0, 0, 0 },
8365   { 3, Iclass_xt_iclass_storei4_args,
8366     0, 0, 0, 0 },
8367   { 1, Iclass_rur_threadptr_args,
8368     1, Iclass_rur_threadptr_stateArgs, 0, 0 },
8369   { 1, Iclass_wur_threadptr_args,
8370     1, Iclass_wur_threadptr_stateArgs, 0, 0 },
8371   { 3, Iclass_xt_iclass_addi_args,
8372     0, 0, 0, 0 },
8373   { 3, Iclass_xt_iclass_addmi_args,
8374     0, 0, 0, 0 },
8375   { 3, Iclass_xt_iclass_addsub_args,
8376     0, 0, 0, 0 },
8377   { 3, Iclass_xt_iclass_bit_args,
8378     0, 0, 0, 0 },
8379   { 3, Iclass_xt_iclass_bsi8_args,
8380     0, 0, 0, 0 },
8381   { 3, Iclass_xt_iclass_bsi8b_args,
8382     0, 0, 0, 0 },
8383   { 3, Iclass_xt_iclass_bsi8u_args,
8384     0, 0, 0, 0 },
8385   { 3, Iclass_xt_iclass_bst8_args,
8386     0, 0, 0, 0 },
8387   { 2, Iclass_xt_iclass_bsz12_args,
8388     0, 0, 0, 0 },
8389   { 2, Iclass_xt_iclass_call0_args,
8390     0, 0, 0, 0 },
8391   { 2, Iclass_xt_iclass_callx0_args,
8392     0, 0, 0, 0 },
8393   { 4, Iclass_xt_iclass_exti_args,
8394     0, 0, 0, 0 },
8395   { 0, 0 /* xt_iclass_ill */,
8396     0, 0, 0, 0 },
8397   { 1, Iclass_xt_iclass_jump_args,
8398     0, 0, 0, 0 },
8399   { 1, Iclass_xt_iclass_jumpx_args,
8400     0, 0, 0, 0 },
8401   { 3, Iclass_xt_iclass_l16ui_args,
8402     0, 0, 0, 0 },
8403   { 3, Iclass_xt_iclass_l16si_args,
8404     0, 0, 0, 0 },
8405   { 3, Iclass_xt_iclass_l32i_args,
8406     0, 0, 0, 0 },
8407   { 2, Iclass_xt_iclass_l32r_args,
8408     2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
8409   { 3, Iclass_xt_iclass_l8i_args,
8410     0, 0, 0, 0 },
8411   { 2, Iclass_xt_iclass_loop_args,
8412     3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
8413   { 2, Iclass_xt_iclass_loopz_args,
8414     3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
8415   { 2, Iclass_xt_iclass_movi_args,
8416     0, 0, 0, 0 },
8417   { 3, Iclass_xt_iclass_movz_args,
8418     0, 0, 0, 0 },
8419   { 2, Iclass_xt_iclass_neg_args,
8420     0, 0, 0, 0 },
8421   { 0, 0 /* xt_iclass_nop */,
8422     0, 0, 0, 0 },
8423   { 1, Iclass_xt_iclass_return_args,
8424     0, 0, 0, 0 },
8425   { 3, Iclass_xt_iclass_s16i_args,
8426     0, 0, 0, 0 },
8427   { 3, Iclass_xt_iclass_s32i_args,
8428     0, 0, 0, 0 },
8429   { 3, Iclass_xt_iclass_s8i_args,
8430     0, 0, 0, 0 },
8431   { 1, Iclass_xt_iclass_sar_args,
8432     1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
8433   { 1, Iclass_xt_iclass_sari_args,
8434     1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
8435   { 2, Iclass_xt_iclass_shifts_args,
8436     1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
8437   { 3, Iclass_xt_iclass_shiftst_args,
8438     1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
8439   { 2, Iclass_xt_iclass_shiftt_args,
8440     1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
8441   { 3, Iclass_xt_iclass_slli_args,
8442     0, 0, 0, 0 },
8443   { 3, Iclass_xt_iclass_srai_args,
8444     0, 0, 0, 0 },
8445   { 3, Iclass_xt_iclass_srli_args,
8446     0, 0, 0, 0 },
8447   { 0, 0 /* xt_iclass_memw */,
8448     0, 0, 0, 0 },
8449   { 0, 0 /* xt_iclass_extw */,
8450     0, 0, 0, 0 },
8451   { 0, 0 /* xt_iclass_isync */,
8452     0, 0, 0, 0 },
8453   { 0, 0 /* xt_iclass_sync */,
8454     1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
8455   { 2, Iclass_xt_iclass_rsil_args,
8456     7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
8457   { 1, Iclass_xt_iclass_rsr_lend_args,
8458     1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
8459   { 1, Iclass_xt_iclass_wsr_lend_args,
8460     1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
8461   { 1, Iclass_xt_iclass_xsr_lend_args,
8462     1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
8463   { 1, Iclass_xt_iclass_rsr_lcount_args,
8464     1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
8465   { 1, Iclass_xt_iclass_wsr_lcount_args,
8466     2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
8467   { 1, Iclass_xt_iclass_xsr_lcount_args,
8468     2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
8469   { 1, Iclass_xt_iclass_rsr_lbeg_args,
8470     1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
8471   { 1, Iclass_xt_iclass_wsr_lbeg_args,
8472     1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
8473   { 1, Iclass_xt_iclass_xsr_lbeg_args,
8474     1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
8475   { 1, Iclass_xt_iclass_rsr_sar_args,
8476     1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
8477   { 1, Iclass_xt_iclass_wsr_sar_args,
8478     2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
8479   { 1, Iclass_xt_iclass_xsr_sar_args,
8480     1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
8481   { 1, Iclass_xt_iclass_rsr_litbase_args,
8482     2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
8483   { 1, Iclass_xt_iclass_wsr_litbase_args,
8484     2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
8485   { 1, Iclass_xt_iclass_xsr_litbase_args,
8486     2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
8487   { 1, Iclass_xt_iclass_rsr_176_args,
8488     2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
8489   { 1, Iclass_xt_iclass_rsr_208_args,
8490     2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
8491   { 1, Iclass_xt_iclass_rsr_ps_args,
8492     7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
8493   { 1, Iclass_xt_iclass_wsr_ps_args,
8494     7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
8495   { 1, Iclass_xt_iclass_xsr_ps_args,
8496     7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
8497   { 1, Iclass_xt_iclass_rsr_epc1_args,
8498     3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
8499   { 1, Iclass_xt_iclass_wsr_epc1_args,
8500     3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
8501   { 1, Iclass_xt_iclass_xsr_epc1_args,
8502     3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
8503   { 1, Iclass_xt_iclass_rsr_excsave1_args,
8504     3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
8505   { 1, Iclass_xt_iclass_wsr_excsave1_args,
8506     3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
8507   { 1, Iclass_xt_iclass_xsr_excsave1_args,
8508     3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
8509   { 1, Iclass_xt_iclass_rsr_epc2_args,
8510     3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
8511   { 1, Iclass_xt_iclass_wsr_epc2_args,
8512     3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
8513   { 1, Iclass_xt_iclass_xsr_epc2_args,
8514     3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
8515   { 1, Iclass_xt_iclass_rsr_excsave2_args,
8516     3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
8517   { 1, Iclass_xt_iclass_wsr_excsave2_args,
8518     3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
8519   { 1, Iclass_xt_iclass_xsr_excsave2_args,
8520     3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
8521   { 1, Iclass_xt_iclass_rsr_epc3_args,
8522     3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
8523   { 1, Iclass_xt_iclass_wsr_epc3_args,
8524     3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
8525   { 1, Iclass_xt_iclass_xsr_epc3_args,
8526     3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
8527   { 1, Iclass_xt_iclass_rsr_excsave3_args,
8528     3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
8529   { 1, Iclass_xt_iclass_wsr_excsave3_args,
8530     3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
8531   { 1, Iclass_xt_iclass_xsr_excsave3_args,
8532     3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
8533   { 1, Iclass_xt_iclass_rsr_epc4_args,
8534     3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
8535   { 1, Iclass_xt_iclass_wsr_epc4_args,
8536     3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
8537   { 1, Iclass_xt_iclass_xsr_epc4_args,
8538     3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
8539   { 1, Iclass_xt_iclass_rsr_excsave4_args,
8540     3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
8541   { 1, Iclass_xt_iclass_wsr_excsave4_args,
8542     3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
8543   { 1, Iclass_xt_iclass_xsr_excsave4_args,
8544     3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
8545   { 1, Iclass_xt_iclass_rsr_epc5_args,
8546     3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
8547   { 1, Iclass_xt_iclass_wsr_epc5_args,
8548     3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
8549   { 1, Iclass_xt_iclass_xsr_epc5_args,
8550     3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
8551   { 1, Iclass_xt_iclass_rsr_excsave5_args,
8552     3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
8553   { 1, Iclass_xt_iclass_wsr_excsave5_args,
8554     3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
8555   { 1, Iclass_xt_iclass_xsr_excsave5_args,
8556     3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
8557   { 1, Iclass_xt_iclass_rsr_epc6_args,
8558     3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
8559   { 1, Iclass_xt_iclass_wsr_epc6_args,
8560     3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
8561   { 1, Iclass_xt_iclass_xsr_epc6_args,
8562     3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
8563   { 1, Iclass_xt_iclass_rsr_excsave6_args,
8564     3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
8565   { 1, Iclass_xt_iclass_wsr_excsave6_args,
8566     3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
8567   { 1, Iclass_xt_iclass_xsr_excsave6_args,
8568     3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
8569   { 1, Iclass_xt_iclass_rsr_epc7_args,
8570     3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
8571   { 1, Iclass_xt_iclass_wsr_epc7_args,
8572     3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
8573   { 1, Iclass_xt_iclass_xsr_epc7_args,
8574     3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
8575   { 1, Iclass_xt_iclass_rsr_excsave7_args,
8576     3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
8577   { 1, Iclass_xt_iclass_wsr_excsave7_args,
8578     3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
8579   { 1, Iclass_xt_iclass_xsr_excsave7_args,
8580     3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
8581   { 1, Iclass_xt_iclass_rsr_eps2_args,
8582     3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
8583   { 1, Iclass_xt_iclass_wsr_eps2_args,
8584     3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
8585   { 1, Iclass_xt_iclass_xsr_eps2_args,
8586     3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
8587   { 1, Iclass_xt_iclass_rsr_eps3_args,
8588     3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
8589   { 1, Iclass_xt_iclass_wsr_eps3_args,
8590     3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
8591   { 1, Iclass_xt_iclass_xsr_eps3_args,
8592     3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
8593   { 1, Iclass_xt_iclass_rsr_eps4_args,
8594     3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
8595   { 1, Iclass_xt_iclass_wsr_eps4_args,
8596     3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
8597   { 1, Iclass_xt_iclass_xsr_eps4_args,
8598     3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
8599   { 1, Iclass_xt_iclass_rsr_eps5_args,
8600     3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
8601   { 1, Iclass_xt_iclass_wsr_eps5_args,
8602     3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
8603   { 1, Iclass_xt_iclass_xsr_eps5_args,
8604     3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
8605   { 1, Iclass_xt_iclass_rsr_eps6_args,
8606     3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
8607   { 1, Iclass_xt_iclass_wsr_eps6_args,
8608     3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
8609   { 1, Iclass_xt_iclass_xsr_eps6_args,
8610     3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
8611   { 1, Iclass_xt_iclass_rsr_eps7_args,
8612     3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
8613   { 1, Iclass_xt_iclass_wsr_eps7_args,
8614     3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
8615   { 1, Iclass_xt_iclass_xsr_eps7_args,
8616     3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
8617   { 1, Iclass_xt_iclass_rsr_excvaddr_args,
8618     3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
8619   { 1, Iclass_xt_iclass_wsr_excvaddr_args,
8620     3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
8621   { 1, Iclass_xt_iclass_xsr_excvaddr_args,
8622     3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
8623   { 1, Iclass_xt_iclass_rsr_depc_args,
8624     3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
8625   { 1, Iclass_xt_iclass_wsr_depc_args,
8626     3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
8627   { 1, Iclass_xt_iclass_xsr_depc_args,
8628     3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
8629   { 1, Iclass_xt_iclass_rsr_exccause_args,
8630     4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
8631   { 1, Iclass_xt_iclass_wsr_exccause_args,
8632     3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
8633   { 1, Iclass_xt_iclass_xsr_exccause_args,
8634     3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
8635   { 1, Iclass_xt_iclass_rsr_misc0_args,
8636     3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
8637   { 1, Iclass_xt_iclass_wsr_misc0_args,
8638     3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
8639   { 1, Iclass_xt_iclass_xsr_misc0_args,
8640     3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
8641   { 1, Iclass_xt_iclass_rsr_misc1_args,
8642     3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
8643   { 1, Iclass_xt_iclass_wsr_misc1_args,
8644     3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
8645   { 1, Iclass_xt_iclass_xsr_misc1_args,
8646     3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
8647   { 1, Iclass_xt_iclass_rsr_misc2_args,
8648     3, Iclass_xt_iclass_rsr_misc2_stateArgs, 0, 0 },
8649   { 1, Iclass_xt_iclass_wsr_misc2_args,
8650     3, Iclass_xt_iclass_wsr_misc2_stateArgs, 0, 0 },
8651   { 1, Iclass_xt_iclass_xsr_misc2_args,
8652     3, Iclass_xt_iclass_xsr_misc2_stateArgs, 0, 0 },
8653   { 1, Iclass_xt_iclass_rsr_misc3_args,
8654     3, Iclass_xt_iclass_rsr_misc3_stateArgs, 0, 0 },
8655   { 1, Iclass_xt_iclass_wsr_misc3_args,
8656     3, Iclass_xt_iclass_wsr_misc3_stateArgs, 0, 0 },
8657   { 1, Iclass_xt_iclass_xsr_misc3_args,
8658     3, Iclass_xt_iclass_xsr_misc3_stateArgs, 0, 0 },
8659   { 1, Iclass_xt_iclass_rsr_prid_args,
8660     2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
8661   { 1, Iclass_xt_iclass_rsr_vecbase_args,
8662     3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
8663   { 1, Iclass_xt_iclass_wsr_vecbase_args,
8664     3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
8665   { 1, Iclass_xt_iclass_xsr_vecbase_args,
8666     3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
8667   { 2, Iclass_xt_iclass_mac16_aa_args,
8668     1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
8669   { 2, Iclass_xt_iclass_mac16_ad_args,
8670     1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
8671   { 2, Iclass_xt_iclass_mac16_da_args,
8672     1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
8673   { 2, Iclass_xt_iclass_mac16_dd_args,
8674     1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
8675   { 2, Iclass_xt_iclass_mac16a_aa_args,
8676     1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
8677   { 2, Iclass_xt_iclass_mac16a_ad_args,
8678     1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
8679   { 2, Iclass_xt_iclass_mac16a_da_args,
8680     1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
8681   { 2, Iclass_xt_iclass_mac16a_dd_args,
8682     1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
8683   { 4, Iclass_xt_iclass_mac16al_da_args,
8684     1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
8685   { 4, Iclass_xt_iclass_mac16al_dd_args,
8686     1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
8687   { 2, Iclass_xt_iclass_mac16_l_args,
8688     0, 0, 0, 0 },
8689   { 3, Iclass_xt_iclass_mul16_args,
8690     0, 0, 0, 0 },
8691   { 2, Iclass_xt_iclass_rsr_m0_args,
8692     0, 0, 0, 0 },
8693   { 2, Iclass_xt_iclass_wsr_m0_args,
8694     0, 0, 0, 0 },
8695   { 2, Iclass_xt_iclass_xsr_m0_args,
8696     0, 0, 0, 0 },
8697   { 2, Iclass_xt_iclass_rsr_m1_args,
8698     0, 0, 0, 0 },
8699   { 2, Iclass_xt_iclass_wsr_m1_args,
8700     0, 0, 0, 0 },
8701   { 2, Iclass_xt_iclass_xsr_m1_args,
8702     0, 0, 0, 0 },
8703   { 2, Iclass_xt_iclass_rsr_m2_args,
8704     0, 0, 0, 0 },
8705   { 2, Iclass_xt_iclass_wsr_m2_args,
8706     0, 0, 0, 0 },
8707   { 2, Iclass_xt_iclass_xsr_m2_args,
8708     0, 0, 0, 0 },
8709   { 2, Iclass_xt_iclass_rsr_m3_args,
8710     0, 0, 0, 0 },
8711   { 2, Iclass_xt_iclass_wsr_m3_args,
8712     0, 0, 0, 0 },
8713   { 2, Iclass_xt_iclass_xsr_m3_args,
8714     0, 0, 0, 0 },
8715   { 1, Iclass_xt_iclass_rsr_acclo_args,
8716     1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
8717   { 1, Iclass_xt_iclass_wsr_acclo_args,
8718     1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
8719   { 1, Iclass_xt_iclass_xsr_acclo_args,
8720     1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
8721   { 1, Iclass_xt_iclass_rsr_acchi_args,
8722     1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
8723   { 1, Iclass_xt_iclass_wsr_acchi_args,
8724     1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
8725   { 1, Iclass_xt_iclass_xsr_acchi_args,
8726     1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
8727   { 1, Iclass_xt_iclass_rfi_args,
8728     21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
8729   { 1, Iclass_xt_iclass_wait_args,
8730     3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
8731   { 1, Iclass_xt_iclass_rsr_interrupt_args,
8732     3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
8733   { 1, Iclass_xt_iclass_wsr_intset_args,
8734     4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
8735   { 1, Iclass_xt_iclass_wsr_intclear_args,
8736     4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
8737   { 1, Iclass_xt_iclass_rsr_intenable_args,
8738     3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
8739   { 1, Iclass_xt_iclass_wsr_intenable_args,
8740     3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
8741   { 1, Iclass_xt_iclass_xsr_intenable_args,
8742     3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
8743   { 2, Iclass_xt_iclass_break_args,
8744     2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
8745   { 1, Iclass_xt_iclass_break_n_args,
8746     2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
8747   { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
8748     3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
8749   { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
8750     4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
8751   { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
8752     4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
8753   { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
8754     3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
8755   { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
8756     4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
8757   { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
8758     4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
8759   { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
8760     3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
8761   { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
8762     4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
8763   { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
8764     4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
8765   { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
8766     3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
8767   { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
8768     4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
8769   { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
8770     4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
8771   { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
8772     3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
8773   { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
8774     3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
8775   { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
8776     3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
8777   { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
8778     3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
8779   { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
8780     3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
8781   { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
8782     3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
8783   { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
8784     3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
8785   { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
8786     3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
8787   { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
8788     3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
8789   { 1, Iclass_xt_iclass_rsr_debugcause_args,
8790     4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
8791   { 1, Iclass_xt_iclass_wsr_debugcause_args,
8792     4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
8793   { 1, Iclass_xt_iclass_xsr_debugcause_args,
8794     4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
8795   { 1, Iclass_xt_iclass_rsr_icount_args,
8796     3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
8797   { 1, Iclass_xt_iclass_wsr_icount_args,
8798     4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
8799   { 1, Iclass_xt_iclass_xsr_icount_args,
8800     4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
8801   { 1, Iclass_xt_iclass_rsr_icountlevel_args,
8802     3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
8803   { 1, Iclass_xt_iclass_wsr_icountlevel_args,
8804     3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
8805   { 1, Iclass_xt_iclass_xsr_icountlevel_args,
8806     3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
8807   { 1, Iclass_xt_iclass_rsr_ddr_args,
8808     3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
8809   { 1, Iclass_xt_iclass_wsr_ddr_args,
8810     4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
8811   { 1, Iclass_xt_iclass_xsr_ddr_args,
8812     4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
8813   { 1, Iclass_xt_iclass_rfdo_args,
8814     10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
8815   { 0, 0 /* xt_iclass_rfdd */,
8816     1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
8817   { 1, Iclass_xt_iclass_wsr_mmid_args,
8818     3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
8819   { 3, Iclass_xt_iclass_bbool1_args,
8820     0, 0, 0, 0 },
8821   { 2, Iclass_xt_iclass_bbool4_args,
8822     0, 0, 0, 0 },
8823   { 2, Iclass_xt_iclass_bbool8_args,
8824     0, 0, 0, 0 },
8825   { 2, Iclass_xt_iclass_bbranch_args,
8826     0, 0, 0, 0 },
8827   { 3, Iclass_xt_iclass_bmove_args,
8828     0, 0, 0, 0 },
8829   { 2, Iclass_xt_iclass_RSR_BR_args,
8830     0, 0, 0, 0 },
8831   { 2, Iclass_xt_iclass_WSR_BR_args,
8832     0, 0, 0, 0 },
8833   { 2, Iclass_xt_iclass_XSR_BR_args,
8834     0, 0, 0, 0 },
8835   { 1, Iclass_xt_iclass_rsr_ccount_args,
8836     3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
8837   { 1, Iclass_xt_iclass_wsr_ccount_args,
8838     4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
8839   { 1, Iclass_xt_iclass_xsr_ccount_args,
8840     4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
8841   { 1, Iclass_xt_iclass_rsr_ccompare0_args,
8842     3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
8843   { 1, Iclass_xt_iclass_wsr_ccompare0_args,
8844     4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
8845   { 1, Iclass_xt_iclass_xsr_ccompare0_args,
8846     4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
8847   { 1, Iclass_xt_iclass_rsr_ccompare1_args,
8848     3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
8849   { 1, Iclass_xt_iclass_wsr_ccompare1_args,
8850     4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
8851   { 1, Iclass_xt_iclass_xsr_ccompare1_args,
8852     4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
8853   { 1, Iclass_xt_iclass_rsr_ccompare2_args,
8854     3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
8855   { 1, Iclass_xt_iclass_wsr_ccompare2_args,
8856     4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
8857   { 1, Iclass_xt_iclass_xsr_ccompare2_args,
8858     4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
8859   { 2, Iclass_xt_iclass_icache_args,
8860     0, 0, 0, 0 },
8861   { 2, Iclass_xt_iclass_icache_lock_args,
8862     2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 },
8863   { 2, Iclass_xt_iclass_icache_inv_args,
8864     2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
8865   { 2, Iclass_xt_iclass_licx_args,
8866     2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
8867   { 2, Iclass_xt_iclass_sicx_args,
8868     2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
8869   { 2, Iclass_xt_iclass_dcache_args,
8870     0, 0, 0, 0 },
8871   { 2, Iclass_xt_iclass_dcache_ind_args,
8872     2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
8873   { 2, Iclass_xt_iclass_dcache_inv_args,
8874     2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
8875   { 2, Iclass_xt_iclass_dpf_args,
8876     0, 0, 0, 0 },
8877   { 2, Iclass_xt_iclass_dcache_lock_args,
8878     2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 },
8879   { 2, Iclass_xt_iclass_sdct_args,
8880     2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
8881   { 2, Iclass_xt_iclass_ldct_args,
8882     2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
8883   { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
8884     4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
8885   { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
8886     4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
8887   { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
8888     5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
8889   { 1, Iclass_xt_iclass_rsr_rasid_args,
8890     5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
8891   { 1, Iclass_xt_iclass_wsr_rasid_args,
8892     6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
8893   { 1, Iclass_xt_iclass_xsr_rasid_args,
8894     6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
8895   { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
8896     3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
8897   { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
8898     4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
8899   { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
8900     4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
8901   { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
8902     3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
8903   { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
8904     4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
8905   { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
8906     4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
8907   { 1, Iclass_xt_iclass_idtlb_args,
8908     3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
8909   { 2, Iclass_xt_iclass_rdtlb_args,
8910     2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
8911   { 2, Iclass_xt_iclass_wdtlb_args,
8912     3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
8913   { 1, Iclass_xt_iclass_iitlb_args,
8914     2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
8915   { 2, Iclass_xt_iclass_ritlb_args,
8916     2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
8917   { 2, Iclass_xt_iclass_witlb_args,
8918     2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
8919   { 0, 0 /* xt_iclass_ldpte */,
8920     2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
8921   { 0, 0 /* xt_iclass_hwwitlba */,
8922     1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
8923   { 0, 0 /* xt_iclass_hwwdtlba */,
8924     1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
8925   { 1, Iclass_xt_iclass_rsr_cpenable_args,
8926     3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
8927   { 1, Iclass_xt_iclass_wsr_cpenable_args,
8928     3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
8929   { 1, Iclass_xt_iclass_xsr_cpenable_args,
8930     3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
8931   { 3, Iclass_xt_iclass_clamp_args,
8932     0, 0, 0, 0 },
8933   { 3, Iclass_xt_iclass_minmax_args,
8934     0, 0, 0, 0 },
8935   { 2, Iclass_xt_iclass_nsa_args,
8936     0, 0, 0, 0 },
8937   { 3, Iclass_xt_iclass_sx_args,
8938     0, 0, 0, 0 },
8939   { 3, Iclass_xt_iclass_l32ai_args,
8940     0, 0, 0, 0 },
8941   { 3, Iclass_xt_iclass_s32ri_args,
8942     0, 0, 0, 0 },
8943   { 3, Iclass_xt_iclass_s32c1i_args,
8944     2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
8945   { 1, Iclass_xt_iclass_rsr_scompare1_args,
8946     1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
8947   { 1, Iclass_xt_iclass_wsr_scompare1_args,
8948     1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
8949   { 1, Iclass_xt_iclass_xsr_scompare1_args,
8950     1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
8951   { 3, Iclass_xt_iclass_div_args,
8952     0, 0, 0, 0 },
8953   { 3, Iclass_xt_mul32_args,
8954     0, 0, 0, 0 },
8955   { 1, Iclass_rur_fcr_args,
8956     9, Iclass_rur_fcr_stateArgs, 0, 0 },
8957   { 1, Iclass_wur_fcr_args,
8958     9, Iclass_wur_fcr_stateArgs, 0, 0 },
8959   { 1, Iclass_rur_fsr_args,
8960     8, Iclass_rur_fsr_stateArgs, 0, 0 },
8961   { 1, Iclass_wur_fsr_args,
8962     8, Iclass_wur_fsr_stateArgs, 0, 0 },
8963   { 3, Iclass_fp_args,
8964     2, Iclass_fp_stateArgs, 0, 0 },
8965   { 3, Iclass_fp_mac_args,
8966     2, Iclass_fp_mac_stateArgs, 0, 0 },
8967   { 3, Iclass_fp_cmov_args,
8968     1, Iclass_fp_cmov_stateArgs, 0, 0 },
8969   { 3, Iclass_fp_mov_args,
8970     1, Iclass_fp_mov_stateArgs, 0, 0 },
8971   { 2, Iclass_fp_mov2_args,
8972     1, Iclass_fp_mov2_stateArgs, 0, 0 },
8973   { 3, Iclass_fp_cmp_args,
8974     1, Iclass_fp_cmp_stateArgs, 0, 0 },
8975   { 3, Iclass_fp_float_args,
8976     2, Iclass_fp_float_stateArgs, 0, 0 },
8977   { 3, Iclass_fp_int_args,
8978     1, Iclass_fp_int_stateArgs, 0, 0 },
8979   { 2, Iclass_fp_rfr_args,
8980     1, Iclass_fp_rfr_stateArgs, 0, 0 },
8981   { 2, Iclass_fp_wfr_args,
8982     1, Iclass_fp_wfr_stateArgs, 0, 0 },
8983   { 3, Iclass_fp_lsi_args,
8984     1, Iclass_fp_lsi_stateArgs, 0, 0 },
8985   { 3, Iclass_fp_lsiu_args,
8986     1, Iclass_fp_lsiu_stateArgs, 0, 0 },
8987   { 3, Iclass_fp_lsx_args,
8988     1, Iclass_fp_lsx_stateArgs, 0, 0 },
8989   { 3, Iclass_fp_lsxu_args,
8990     1, Iclass_fp_lsxu_stateArgs, 0, 0 },
8991   { 3, Iclass_fp_ssi_args,
8992     1, Iclass_fp_ssi_stateArgs, 0, 0 },
8993   { 3, Iclass_fp_ssiu_args,
8994     1, Iclass_fp_ssiu_stateArgs, 0, 0 },
8995   { 3, Iclass_fp_ssx_args,
8996     1, Iclass_fp_ssx_stateArgs, 0, 0 },
8997   { 3, Iclass_fp_ssxu_args,
8998     1, Iclass_fp_ssxu_stateArgs, 0, 0 },
8999   { 2, Iclass_xt_iclass_wb18_0_args,
9000     0, 0, 0, 0 },
9001   { 3, Iclass_xt_iclass_wb18_1_args,
9002     0, 0, 0, 0 },
9003   { 3, Iclass_xt_iclass_wb18_2_args,
9004     0, 0, 0, 0 },
9005   { 3, Iclass_xt_iclass_wb18_3_args,
9006     0, 0, 0, 0 },
9007   { 3, Iclass_xt_iclass_wb18_4_args,
9008     0, 0, 0, 0 }
9009 };
9010
9011 \f
9012 /*  Opcode encodings.  */
9013
9014 static void
9015 Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
9016 {
9017   slotbuf[0] = 0x2080;
9018 }
9019
9020 static void
9021 Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
9022 {
9023   slotbuf[0] = 0x3000;
9024 }
9025
9026 static void
9027 Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
9028 {
9029   slotbuf[0] = 0x3200;
9030 }
9031
9032 static void
9033 Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
9034 {
9035   slotbuf[0] = 0x5000;
9036 }
9037
9038 static void
9039 Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
9040 {
9041   slotbuf[0] = 0x5100;
9042 }
9043
9044 static void
9045 Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
9046 {
9047   slotbuf[0] = 0x35;
9048 }
9049
9050 static void
9051 Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
9052 {
9053   slotbuf[0] = 0x25;
9054 }
9055
9056 static void
9057 Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
9058 {
9059   slotbuf[0] = 0x15;
9060 }
9061
9062 static void
9063 Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
9064 {
9065   slotbuf[0] = 0xf0;
9066 }
9067
9068 static void
9069 Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
9070 {
9071   slotbuf[0] = 0xe0;
9072 }
9073
9074 static void
9075 Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
9076 {
9077   slotbuf[0] = 0xd0;
9078 }
9079
9080 static void
9081 Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
9082 {
9083   slotbuf[0] = 0x36;
9084 }
9085
9086 static void
9087 Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
9088 {
9089   slotbuf[0] = 0x1000;
9090 }
9091
9092 static void
9093 Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
9094 {
9095   slotbuf[0] = 0x408000;
9096 }
9097
9098 static void
9099 Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
9100 {
9101   slotbuf[0] = 0x90;
9102 }
9103
9104 static void
9105 Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9106 {
9107   slotbuf[0] = 0xf01d;
9108 }
9109
9110 static void
9111 Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
9112 {
9113   slotbuf[0] = 0x3400;
9114 }
9115
9116 static void
9117 Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
9118 {
9119   slotbuf[0] = 0x3500;
9120 }
9121
9122 static void
9123 Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
9124 {
9125   slotbuf[0] = 0x90000;
9126 }
9127
9128 static void
9129 Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
9130 {
9131   slotbuf[0] = 0x490000;
9132 }
9133
9134 static void
9135 Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
9136 {
9137   slotbuf[0] = 0x34800;
9138 }
9139
9140 static void
9141 Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
9142 {
9143   slotbuf[0] = 0x134800;
9144 }
9145
9146 static void
9147 Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
9148 {
9149   slotbuf[0] = 0x614800;
9150 }
9151
9152 static void
9153 Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
9154 {
9155   slotbuf[0] = 0x34900;
9156 }
9157
9158 static void
9159 Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
9160 {
9161   slotbuf[0] = 0x134900;
9162 }
9163
9164 static void
9165 Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
9166 {
9167   slotbuf[0] = 0x614900;
9168 }
9169
9170 static void
9171 Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
9172 {
9173   slotbuf[0] = 0xa;
9174 }
9175
9176 static void
9177 Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
9178 {
9179   slotbuf[0] = 0xb;
9180 }
9181
9182 static void
9183 Opcode_addi_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9184 {
9185   slotbuf[0] = 0x3000;
9186 }
9187
9188 static void
9189 Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9190 {
9191   slotbuf[0] = 0x8c;
9192 }
9193
9194 static void
9195 Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9196 {
9197   slotbuf[0] = 0xcc;
9198 }
9199
9200 static void
9201 Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9202 {
9203   slotbuf[0] = 0xf06d;
9204 }
9205
9206 static void
9207 Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
9208 {
9209   slotbuf[0] = 0x8;
9210 }
9211
9212 static void
9213 Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9214 {
9215   slotbuf[0] = 0xd;
9216 }
9217
9218 static void
9219 Opcode_mov_n_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9220 {
9221   slotbuf[0] = 0x6000;
9222 }
9223
9224 static void
9225 Opcode_mov_n_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9226 {
9227   slotbuf[0] = 0xa3000;
9228 }
9229
9230 static void
9231 Opcode_mov_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9232 {
9233   slotbuf[0] = 0xc080;
9234 }
9235
9236 static void
9237 Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9238 {
9239   slotbuf[0] = 0xc;
9240 }
9241
9242 static void
9243 Opcode_movi_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9244 {
9245   slotbuf[0] = 0xc000;
9246 }
9247
9248 static void
9249 Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9250 {
9251   slotbuf[0] = 0xf03d;
9252 }
9253
9254 static void
9255 Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9256 {
9257   slotbuf[0] = 0xf00d;
9258 }
9259
9260 static void
9261 Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
9262 {
9263   slotbuf[0] = 0x9;
9264 }
9265
9266 static void
9267 Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
9268 {
9269   slotbuf[0] = 0xe30e70;
9270 }
9271
9272 static void
9273 Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
9274 {
9275   slotbuf[0] = 0xf3e700;
9276 }
9277
9278 static void
9279 Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
9280 {
9281   slotbuf[0] = 0xc002;
9282 }
9283
9284 static void
9285 Opcode_addi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9286 {
9287   slotbuf[0] = 0x60000;
9288 }
9289
9290 static void
9291 Opcode_addi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9292 {
9293   slotbuf[0] = 0x200c00;
9294 }
9295
9296 static void
9297 Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
9298 {
9299   slotbuf[0] = 0xd002;
9300 }
9301
9302 static void
9303 Opcode_addmi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9304 {
9305   slotbuf[0] = 0x70000;
9306 }
9307
9308 static void
9309 Opcode_addmi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9310 {
9311   slotbuf[0] = 0x200d00;
9312 }
9313
9314 static void
9315 Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
9316 {
9317   slotbuf[0] = 0x800000;
9318 }
9319
9320 static void
9321 Opcode_add_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9322 {
9323   slotbuf[0] = 0x92000;
9324 }
9325
9326 static void
9327 Opcode_add_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9328 {
9329   slotbuf[0] = 0x2000;
9330 }
9331
9332 static void
9333 Opcode_add_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9334 {
9335   slotbuf[0] = 0x80000;
9336 }
9337
9338 static void
9339 Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
9340 {
9341   slotbuf[0] = 0xc00000;
9342 }
9343
9344 static void
9345 Opcode_sub_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9346 {
9347   slotbuf[0] = 0xa8000;
9348 }
9349
9350 static void
9351 Opcode_sub_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9352 {
9353   slotbuf[0] = 0xa000;
9354 }
9355
9356 static void
9357 Opcode_sub_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9358 {
9359   slotbuf[0] = 0xc0000;
9360 }
9361
9362 static void
9363 Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
9364 {
9365   slotbuf[0] = 0x900000;
9366 }
9367
9368 static void
9369 Opcode_addx2_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9370 {
9371   slotbuf[0] = 0x94000;
9372 }
9373
9374 static void
9375 Opcode_addx2_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9376 {
9377   slotbuf[0] = 0x4000;
9378 }
9379
9380 static void
9381 Opcode_addx2_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9382 {
9383   slotbuf[0] = 0x90000;
9384 }
9385
9386 static void
9387 Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
9388 {
9389   slotbuf[0] = 0xa00000;
9390 }
9391
9392 static void
9393 Opcode_addx4_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9394 {
9395   slotbuf[0] = 0x98000;
9396 }
9397
9398 static void
9399 Opcode_addx4_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9400 {
9401   slotbuf[0] = 0x5000;
9402 }
9403
9404 static void
9405 Opcode_addx4_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9406 {
9407   slotbuf[0] = 0xa0000;
9408 }
9409
9410 static void
9411 Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
9412 {
9413   slotbuf[0] = 0xb00000;
9414 }
9415
9416 static void
9417 Opcode_addx8_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9418 {
9419   slotbuf[0] = 0x93000;
9420 }
9421
9422 static void
9423 Opcode_addx8_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9424 {
9425   slotbuf[0] = 0xb0000;
9426 }
9427
9428 static void
9429 Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
9430 {
9431   slotbuf[0] = 0xd00000;
9432 }
9433
9434 static void
9435 Opcode_subx2_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9436 {
9437   slotbuf[0] = 0xd0000;
9438 }
9439
9440 static void
9441 Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
9442 {
9443   slotbuf[0] = 0xe00000;
9444 }
9445
9446 static void
9447 Opcode_subx4_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9448 {
9449   slotbuf[0] = 0xe0000;
9450 }
9451
9452 static void
9453 Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
9454 {
9455   slotbuf[0] = 0xf00000;
9456 }
9457
9458 static void
9459 Opcode_subx8_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9460 {
9461   slotbuf[0] = 0xf0000;
9462 }
9463
9464 static void
9465 Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
9466 {
9467   slotbuf[0] = 0x100000;
9468 }
9469
9470 static void
9471 Opcode_and_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9472 {
9473   slotbuf[0] = 0x95000;
9474 }
9475
9476 static void
9477 Opcode_and_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9478 {
9479   slotbuf[0] = 0x6000;
9480 }
9481
9482 static void
9483 Opcode_and_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9484 {
9485   slotbuf[0] = 0x10000;
9486 }
9487
9488 static void
9489 Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
9490 {
9491   slotbuf[0] = 0x200000;
9492 }
9493
9494 static void
9495 Opcode_or_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9496 {
9497   slotbuf[0] = 0x9e000;
9498 }
9499
9500 static void
9501 Opcode_or_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9502 {
9503   slotbuf[0] = 0x7000;
9504 }
9505
9506 static void
9507 Opcode_or_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9508 {
9509   slotbuf[0] = 0x20000;
9510 }
9511
9512 static void
9513 Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
9514 {
9515   slotbuf[0] = 0x300000;
9516 }
9517
9518 static void
9519 Opcode_xor_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9520 {
9521   slotbuf[0] = 0xb0000;
9522 }
9523
9524 static void
9525 Opcode_xor_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9526 {
9527   slotbuf[0] = 0xb000;
9528 }
9529
9530 static void
9531 Opcode_xor_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9532 {
9533   slotbuf[0] = 0x30000;
9534 }
9535
9536 static void
9537 Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
9538 {
9539   slotbuf[0] = 0x26;
9540 }
9541
9542 static void
9543 Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
9544 {
9545   slotbuf[0] = 0x66;
9546 }
9547
9548 static void
9549 Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
9550 {
9551   slotbuf[0] = 0xe6;
9552 }
9553
9554 static void
9555 Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
9556 {
9557   slotbuf[0] = 0xa6;
9558 }
9559
9560 static void
9561 Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
9562 {
9563   slotbuf[0] = 0x6007;
9564 }
9565
9566 static void
9567 Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
9568 {
9569   slotbuf[0] = 0xe007;
9570 }
9571
9572 static void
9573 Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
9574 {
9575   slotbuf[0] = 0xf6;
9576 }
9577
9578 static void
9579 Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
9580 {
9581   slotbuf[0] = 0xb6;
9582 }
9583
9584 static void
9585 Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
9586 {
9587   slotbuf[0] = 0x1007;
9588 }
9589
9590 static void
9591 Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
9592 {
9593   slotbuf[0] = 0x9007;
9594 }
9595
9596 static void
9597 Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
9598 {
9599   slotbuf[0] = 0xa007;
9600 }
9601
9602 static void
9603 Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
9604 {
9605   slotbuf[0] = 0x2007;
9606 }
9607
9608 static void
9609 Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
9610 {
9611   slotbuf[0] = 0xb007;
9612 }
9613
9614 static void
9615 Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
9616 {
9617   slotbuf[0] = 0x3007;
9618 }
9619
9620 static void
9621 Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
9622 {
9623   slotbuf[0] = 0x8007;
9624 }
9625
9626 static void
9627 Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
9628 {
9629   slotbuf[0] = 0x7;
9630 }
9631
9632 static void
9633 Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
9634 {
9635   slotbuf[0] = 0x4007;
9636 }
9637
9638 static void
9639 Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
9640 {
9641   slotbuf[0] = 0xc007;
9642 }
9643
9644 static void
9645 Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
9646 {
9647   slotbuf[0] = 0x5007;
9648 }
9649
9650 static void
9651 Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
9652 {
9653   slotbuf[0] = 0xd007;
9654 }
9655
9656 static void
9657 Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
9658 {
9659   slotbuf[0] = 0x16;
9660 }
9661
9662 static void
9663 Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
9664 {
9665   slotbuf[0] = 0x56;
9666 }
9667
9668 static void
9669 Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
9670 {
9671   slotbuf[0] = 0xd6;
9672 }
9673
9674 static void
9675 Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
9676 {
9677   slotbuf[0] = 0x96;
9678 }
9679
9680 static void
9681 Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
9682 {
9683   slotbuf[0] = 0x5;
9684 }
9685
9686 static void
9687 Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
9688 {
9689   slotbuf[0] = 0xc0;
9690 }
9691
9692 static void
9693 Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
9694 {
9695   slotbuf[0] = 0x40000;
9696 }
9697
9698 static void
9699 Opcode_extui_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9700 {
9701   slotbuf[0] = 0x40000;
9702 }
9703
9704 static void
9705 Opcode_extui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9706 {
9707   slotbuf[0] = 0x4000;
9708 }
9709
9710 static void
9711 Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
9712 {
9713   slotbuf[0] = 0;
9714 }
9715
9716 static void
9717 Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
9718 {
9719   slotbuf[0] = 0x6;
9720 }
9721
9722 static void
9723 Opcode_j_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9724 {
9725   slotbuf[0] = 0xc0000;
9726 }
9727
9728 static void
9729 Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
9730 {
9731   slotbuf[0] = 0xa0;
9732 }
9733
9734 static void
9735 Opcode_jx_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9736 {
9737   slotbuf[0] = 0xa3010;
9738 }
9739
9740 static void
9741 Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
9742 {
9743   slotbuf[0] = 0x1002;
9744 }
9745
9746 static void
9747 Opcode_l16ui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9748 {
9749   slotbuf[0] = 0x200100;
9750 }
9751
9752 static void
9753 Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
9754 {
9755   slotbuf[0] = 0x9002;
9756 }
9757
9758 static void
9759 Opcode_l16si_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9760 {
9761   slotbuf[0] = 0x200900;
9762 }
9763
9764 static void
9765 Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
9766 {
9767   slotbuf[0] = 0x2002;
9768 }
9769
9770 static void
9771 Opcode_l32i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9772 {
9773   slotbuf[0] = 0x200200;
9774 }
9775
9776 static void
9777 Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
9778 {
9779   slotbuf[0] = 0x1;
9780 }
9781
9782 static void
9783 Opcode_l32r_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9784 {
9785   slotbuf[0] = 0x100000;
9786 }
9787
9788 static void
9789 Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
9790 {
9791   slotbuf[0] = 0x2;
9792 }
9793
9794 static void
9795 Opcode_l8ui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9796 {
9797   slotbuf[0] = 0x200000;
9798 }
9799
9800 static void
9801 Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
9802 {
9803   slotbuf[0] = 0x8076;
9804 }
9805
9806 static void
9807 Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
9808 {
9809   slotbuf[0] = 0x9076;
9810 }
9811
9812 static void
9813 Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
9814 {
9815   slotbuf[0] = 0xa076;
9816 }
9817
9818 static void
9819 Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
9820 {
9821   slotbuf[0] = 0xa002;
9822 }
9823
9824 static void
9825 Opcode_movi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9826 {
9827   slotbuf[0] = 0x80000;
9828 }
9829
9830 static void
9831 Opcode_movi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9832 {
9833   slotbuf[0] = 0x200a00;
9834 }
9835
9836 static void
9837 Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
9838 {
9839   slotbuf[0] = 0x830000;
9840 }
9841
9842 static void
9843 Opcode_moveqz_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9844 {
9845   slotbuf[0] = 0x96000;
9846 }
9847
9848 static void
9849 Opcode_moveqz_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9850 {
9851   slotbuf[0] = 0x83000;
9852 }
9853
9854 static void
9855 Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
9856 {
9857   slotbuf[0] = 0x930000;
9858 }
9859
9860 static void
9861 Opcode_movnez_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9862 {
9863   slotbuf[0] = 0x9a000;
9864 }
9865
9866 static void
9867 Opcode_movnez_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9868 {
9869   slotbuf[0] = 0x93000;
9870 }
9871
9872 static void
9873 Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
9874 {
9875   slotbuf[0] = 0xa30000;
9876 }
9877
9878 static void
9879 Opcode_movltz_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9880 {
9881   slotbuf[0] = 0x99000;
9882 }
9883
9884 static void
9885 Opcode_movltz_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9886 {
9887   slotbuf[0] = 0xa3000;
9888 }
9889
9890 static void
9891 Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
9892 {
9893   slotbuf[0] = 0xb30000;
9894 }
9895
9896 static void
9897 Opcode_movgez_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9898 {
9899   slotbuf[0] = 0x97000;
9900 }
9901
9902 static void
9903 Opcode_movgez_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9904 {
9905   slotbuf[0] = 0xb3000;
9906 }
9907
9908 static void
9909 Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
9910 {
9911   slotbuf[0] = 0x600000;
9912 }
9913
9914 static void
9915 Opcode_neg_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9916 {
9917   slotbuf[0] = 0xa5000;
9918 }
9919
9920 static void
9921 Opcode_neg_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9922 {
9923   slotbuf[0] = 0xd100;
9924 }
9925
9926 static void
9927 Opcode_neg_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9928 {
9929   slotbuf[0] = 0x60000;
9930 }
9931
9932 static void
9933 Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
9934 {
9935   slotbuf[0] = 0x600100;
9936 }
9937
9938 static void
9939 Opcode_abs_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9940 {
9941   slotbuf[0] = 0xd000;
9942 }
9943
9944 static void
9945 Opcode_abs_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9946 {
9947   slotbuf[0] = 0x60010;
9948 }
9949
9950 static void
9951 Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
9952 {
9953   slotbuf[0] = 0x20f0;
9954 }
9955
9956 static void
9957 Opcode_nop_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9958 {
9959   slotbuf[0] = 0xa3040;
9960 }
9961
9962 static void
9963 Opcode_nop_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9964 {
9965   slotbuf[0] = 0xc090;
9966 }
9967
9968 static void
9969 Opcode_nop_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
9970 {
9971   slotbuf[0] = 0xc8000000;
9972   slotbuf[1] = 0;
9973 }
9974
9975 static void
9976 Opcode_nop_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9977 {
9978   slotbuf[0] = 0x20f;
9979 }
9980
9981 static void
9982 Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
9983 {
9984   slotbuf[0] = 0x80;
9985 }
9986
9987 static void
9988 Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
9989 {
9990   slotbuf[0] = 0x5002;
9991 }
9992
9993 static void
9994 Opcode_s16i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9995 {
9996   slotbuf[0] = 0x200500;
9997 }
9998
9999 static void
10000 Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
10001 {
10002   slotbuf[0] = 0x6002;
10003 }
10004
10005 static void
10006 Opcode_s32i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10007 {
10008   slotbuf[0] = 0x200600;
10009 }
10010
10011 static void
10012 Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
10013 {
10014   slotbuf[0] = 0x4002;
10015 }
10016
10017 static void
10018 Opcode_s8i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10019 {
10020   slotbuf[0] = 0x200400;
10021 }
10022
10023 static void
10024 Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
10025 {
10026   slotbuf[0] = 0x400000;
10027 }
10028
10029 static void
10030 Opcode_ssr_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10031 {
10032   slotbuf[0] = 0x40000;
10033 }
10034
10035 static void
10036 Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
10037 {
10038   slotbuf[0] = 0x401000;
10039 }
10040
10041 static void
10042 Opcode_ssl_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10043 {
10044   slotbuf[0] = 0xa3020;
10045 }
10046
10047 static void
10048 Opcode_ssl_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10049 {
10050   slotbuf[0] = 0x40100;
10051 }
10052
10053 static void
10054 Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
10055 {
10056   slotbuf[0] = 0x402000;
10057 }
10058
10059 static void
10060 Opcode_ssa8l_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10061 {
10062   slotbuf[0] = 0x40200;
10063 }
10064
10065 static void
10066 Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
10067 {
10068   slotbuf[0] = 0x403000;
10069 }
10070
10071 static void
10072 Opcode_ssa8b_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10073 {
10074   slotbuf[0] = 0x40300;
10075 }
10076
10077 static void
10078 Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
10079 {
10080   slotbuf[0] = 0x404000;
10081 }
10082
10083 static void
10084 Opcode_ssai_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10085 {
10086   slotbuf[0] = 0x40400;
10087 }
10088
10089 static void
10090 Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
10091 {
10092   slotbuf[0] = 0xa10000;
10093 }
10094
10095 static void
10096 Opcode_sll_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10097 {
10098   slotbuf[0] = 0xa6000;
10099 }
10100
10101 static void
10102 Opcode_sll_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10103 {
10104   slotbuf[0] = 0xa1000;
10105 }
10106
10107 static void
10108 Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
10109 {
10110   slotbuf[0] = 0x810000;
10111 }
10112
10113 static void
10114 Opcode_src_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10115 {
10116   slotbuf[0] = 0xa2000;
10117 }
10118
10119 static void
10120 Opcode_src_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10121 {
10122   slotbuf[0] = 0x81000;
10123 }
10124
10125 static void
10126 Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
10127 {
10128   slotbuf[0] = 0x910000;
10129 }
10130
10131 static void
10132 Opcode_srl_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10133 {
10134   slotbuf[0] = 0xa5200;
10135 }
10136
10137 static void
10138 Opcode_srl_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
10139 {
10140   slotbuf[0] = 0xd400;
10141 }
10142
10143 static void
10144 Opcode_srl_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10145 {
10146   slotbuf[0] = 0x91000;
10147 }
10148
10149 static void
10150 Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
10151 {
10152   slotbuf[0] = 0xb10000;
10153 }
10154
10155 static void
10156 Opcode_sra_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10157 {
10158   slotbuf[0] = 0xa5100;
10159 }
10160
10161 static void
10162 Opcode_sra_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
10163 {
10164   slotbuf[0] = 0xd200;
10165 }
10166
10167 static void
10168 Opcode_sra_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10169 {
10170   slotbuf[0] = 0xb1000;
10171 }
10172
10173 static void
10174 Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
10175 {
10176   slotbuf[0] = 0x10000;
10177 }
10178
10179 static void
10180 Opcode_slli_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10181 {
10182   slotbuf[0] = 0x90000;
10183 }
10184
10185 static void
10186 Opcode_slli_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10187 {
10188   slotbuf[0] = 0x1000;
10189 }
10190
10191 static void
10192 Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
10193 {
10194   slotbuf[0] = 0x210000;
10195 }
10196
10197 static void
10198 Opcode_srai_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10199 {
10200   slotbuf[0] = 0xa0000;
10201 }
10202
10203 static void
10204 Opcode_srai_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
10205 {
10206   slotbuf[0] = 0xe000;
10207 }
10208
10209 static void
10210 Opcode_srai_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10211 {
10212   slotbuf[0] = 0x21000;
10213 }
10214
10215 static void
10216 Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
10217 {
10218   slotbuf[0] = 0x410000;
10219 }
10220
10221 static void
10222 Opcode_srli_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10223 {
10224   slotbuf[0] = 0xa4000;
10225 }
10226
10227 static void
10228 Opcode_srli_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
10229 {
10230   slotbuf[0] = 0x9000;
10231 }
10232
10233 static void
10234 Opcode_srli_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10235 {
10236   slotbuf[0] = 0x41000;
10237 }
10238
10239 static void
10240 Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
10241 {
10242   slotbuf[0] = 0x20c0;
10243 }
10244
10245 static void
10246 Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
10247 {
10248   slotbuf[0] = 0x20d0;
10249 }
10250
10251 static void
10252 Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
10253 {
10254   slotbuf[0] = 0x2000;
10255 }
10256
10257 static void
10258 Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
10259 {
10260   slotbuf[0] = 0x2010;
10261 }
10262
10263 static void
10264 Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
10265 {
10266   slotbuf[0] = 0x2020;
10267 }
10268
10269 static void
10270 Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
10271 {
10272   slotbuf[0] = 0x2030;
10273 }
10274
10275 static void
10276 Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
10277 {
10278   slotbuf[0] = 0x6000;
10279 }
10280
10281 static void
10282 Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
10283 {
10284   slotbuf[0] = 0x30100;
10285 }
10286
10287 static void
10288 Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
10289 {
10290   slotbuf[0] = 0x130100;
10291 }
10292
10293 static void
10294 Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
10295 {
10296   slotbuf[0] = 0x610100;
10297 }
10298
10299 static void
10300 Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
10301 {
10302   slotbuf[0] = 0x30200;
10303 }
10304
10305 static void
10306 Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
10307 {
10308   slotbuf[0] = 0x130200;
10309 }
10310
10311 static void
10312 Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
10313 {
10314   slotbuf[0] = 0x610200;
10315 }
10316
10317 static void
10318 Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
10319 {
10320   slotbuf[0] = 0x30000;
10321 }
10322
10323 static void
10324 Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
10325 {
10326   slotbuf[0] = 0x130000;
10327 }
10328
10329 static void
10330 Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
10331 {
10332   slotbuf[0] = 0x610000;
10333 }
10334
10335 static void
10336 Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
10337 {
10338   slotbuf[0] = 0x30300;
10339 }
10340
10341 static void
10342 Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
10343 {
10344   slotbuf[0] = 0x130300;
10345 }
10346
10347 static void
10348 Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
10349 {
10350   slotbuf[0] = 0x610300;
10351 }
10352
10353 static void
10354 Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
10355 {
10356   slotbuf[0] = 0x30500;
10357 }
10358
10359 static void
10360 Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
10361 {
10362   slotbuf[0] = 0x130500;
10363 }
10364
10365 static void
10366 Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
10367 {
10368   slotbuf[0] = 0x610500;
10369 }
10370
10371 static void
10372 Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
10373 {
10374   slotbuf[0] = 0x3b000;
10375 }
10376
10377 static void
10378 Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
10379 {
10380   slotbuf[0] = 0x3d000;
10381 }
10382
10383 static void
10384 Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
10385 {
10386   slotbuf[0] = 0x3e600;
10387 }
10388
10389 static void
10390 Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
10391 {
10392   slotbuf[0] = 0x13e600;
10393 }
10394
10395 static void
10396 Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
10397 {
10398   slotbuf[0] = 0x61e600;
10399 }
10400
10401 static void
10402 Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
10403 {
10404   slotbuf[0] = 0x3b100;
10405 }
10406
10407 static void
10408 Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
10409 {
10410   slotbuf[0] = 0x13b100;
10411 }
10412
10413 static void
10414 Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
10415 {
10416   slotbuf[0] = 0x61b100;
10417 }
10418
10419 static void
10420 Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
10421 {
10422   slotbuf[0] = 0x3d100;
10423 }
10424
10425 static void
10426 Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
10427 {
10428   slotbuf[0] = 0x13d100;
10429 }
10430
10431 static void
10432 Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
10433 {
10434   slotbuf[0] = 0x61d100;
10435 }
10436
10437 static void
10438 Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10439 {
10440   slotbuf[0] = 0x3b200;
10441 }
10442
10443 static void
10444 Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10445 {
10446   slotbuf[0] = 0x13b200;
10447 }
10448
10449 static void
10450 Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10451 {
10452   slotbuf[0] = 0x61b200;
10453 }
10454
10455 static void
10456 Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10457 {
10458   slotbuf[0] = 0x3d200;
10459 }
10460
10461 static void
10462 Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10463 {
10464   slotbuf[0] = 0x13d200;
10465 }
10466
10467 static void
10468 Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10469 {
10470   slotbuf[0] = 0x61d200;
10471 }
10472
10473 static void
10474 Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10475 {
10476   slotbuf[0] = 0x3b300;
10477 }
10478
10479 static void
10480 Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10481 {
10482   slotbuf[0] = 0x13b300;
10483 }
10484
10485 static void
10486 Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10487 {
10488   slotbuf[0] = 0x61b300;
10489 }
10490
10491 static void
10492 Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10493 {
10494   slotbuf[0] = 0x3d300;
10495 }
10496
10497 static void
10498 Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10499 {
10500   slotbuf[0] = 0x13d300;
10501 }
10502
10503 static void
10504 Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10505 {
10506   slotbuf[0] = 0x61d300;
10507 }
10508
10509 static void
10510 Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
10511 {
10512   slotbuf[0] = 0x3b400;
10513 }
10514
10515 static void
10516 Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
10517 {
10518   slotbuf[0] = 0x13b400;
10519 }
10520
10521 static void
10522 Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
10523 {
10524   slotbuf[0] = 0x61b400;
10525 }
10526
10527 static void
10528 Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
10529 {
10530   slotbuf[0] = 0x3d400;
10531 }
10532
10533 static void
10534 Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
10535 {
10536   slotbuf[0] = 0x13d400;
10537 }
10538
10539 static void
10540 Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
10541 {
10542   slotbuf[0] = 0x61d400;
10543 }
10544
10545 static void
10546 Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
10547 {
10548   slotbuf[0] = 0x3b500;
10549 }
10550
10551 static void
10552 Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
10553 {
10554   slotbuf[0] = 0x13b500;
10555 }
10556
10557 static void
10558 Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
10559 {
10560   slotbuf[0] = 0x61b500;
10561 }
10562
10563 static void
10564 Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
10565 {
10566   slotbuf[0] = 0x3d500;
10567 }
10568
10569 static void
10570 Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
10571 {
10572   slotbuf[0] = 0x13d500;
10573 }
10574
10575 static void
10576 Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
10577 {
10578   slotbuf[0] = 0x61d500;
10579 }
10580
10581 static void
10582 Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
10583 {
10584   slotbuf[0] = 0x3b600;
10585 }
10586
10587 static void
10588 Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
10589 {
10590   slotbuf[0] = 0x13b600;
10591 }
10592
10593 static void
10594 Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
10595 {
10596   slotbuf[0] = 0x61b600;
10597 }
10598
10599 static void
10600 Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
10601 {
10602   slotbuf[0] = 0x3d600;
10603 }
10604
10605 static void
10606 Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
10607 {
10608   slotbuf[0] = 0x13d600;
10609 }
10610
10611 static void
10612 Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
10613 {
10614   slotbuf[0] = 0x61d600;
10615 }
10616
10617 static void
10618 Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
10619 {
10620   slotbuf[0] = 0x3b700;
10621 }
10622
10623 static void
10624 Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
10625 {
10626   slotbuf[0] = 0x13b700;
10627 }
10628
10629 static void
10630 Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
10631 {
10632   slotbuf[0] = 0x61b700;
10633 }
10634
10635 static void
10636 Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
10637 {
10638   slotbuf[0] = 0x3d700;
10639 }
10640
10641 static void
10642 Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
10643 {
10644   slotbuf[0] = 0x13d700;
10645 }
10646
10647 static void
10648 Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
10649 {
10650   slotbuf[0] = 0x61d700;
10651 }
10652
10653 static void
10654 Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10655 {
10656   slotbuf[0] = 0x3c200;
10657 }
10658
10659 static void
10660 Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10661 {
10662   slotbuf[0] = 0x13c200;
10663 }
10664
10665 static void
10666 Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10667 {
10668   slotbuf[0] = 0x61c200;
10669 }
10670
10671 static void
10672 Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10673 {
10674   slotbuf[0] = 0x3c300;
10675 }
10676
10677 static void
10678 Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10679 {
10680   slotbuf[0] = 0x13c300;
10681 }
10682
10683 static void
10684 Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10685 {
10686   slotbuf[0] = 0x61c300;
10687 }
10688
10689 static void
10690 Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
10691 {
10692   slotbuf[0] = 0x3c400;
10693 }
10694
10695 static void
10696 Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
10697 {
10698   slotbuf[0] = 0x13c400;
10699 }
10700
10701 static void
10702 Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
10703 {
10704   slotbuf[0] = 0x61c400;
10705 }
10706
10707 static void
10708 Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
10709 {
10710   slotbuf[0] = 0x3c500;
10711 }
10712
10713 static void
10714 Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
10715 {
10716   slotbuf[0] = 0x13c500;
10717 }
10718
10719 static void
10720 Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
10721 {
10722   slotbuf[0] = 0x61c500;
10723 }
10724
10725 static void
10726 Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
10727 {
10728   slotbuf[0] = 0x3c600;
10729 }
10730
10731 static void
10732 Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
10733 {
10734   slotbuf[0] = 0x13c600;
10735 }
10736
10737 static void
10738 Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
10739 {
10740   slotbuf[0] = 0x61c600;
10741 }
10742
10743 static void
10744 Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
10745 {
10746   slotbuf[0] = 0x3c700;
10747 }
10748
10749 static void
10750 Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
10751 {
10752   slotbuf[0] = 0x13c700;
10753 }
10754
10755 static void
10756 Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
10757 {
10758   slotbuf[0] = 0x61c700;
10759 }
10760
10761 static void
10762 Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
10763 {
10764   slotbuf[0] = 0x3ee00;
10765 }
10766
10767 static void
10768 Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
10769 {
10770   slotbuf[0] = 0x13ee00;
10771 }
10772
10773 static void
10774 Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
10775 {
10776   slotbuf[0] = 0x61ee00;
10777 }
10778
10779 static void
10780 Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
10781 {
10782   slotbuf[0] = 0x3c000;
10783 }
10784
10785 static void
10786 Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
10787 {
10788   slotbuf[0] = 0x13c000;
10789 }
10790
10791 static void
10792 Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
10793 {
10794   slotbuf[0] = 0x61c000;
10795 }
10796
10797 static void
10798 Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
10799 {
10800   slotbuf[0] = 0x3e800;
10801 }
10802
10803 static void
10804 Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
10805 {
10806   slotbuf[0] = 0x13e800;
10807 }
10808
10809 static void
10810 Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
10811 {
10812   slotbuf[0] = 0x61e800;
10813 }
10814
10815 static void
10816 Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
10817 {
10818   slotbuf[0] = 0x3f400;
10819 }
10820
10821 static void
10822 Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
10823 {
10824   slotbuf[0] = 0x13f400;
10825 }
10826
10827 static void
10828 Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
10829 {
10830   slotbuf[0] = 0x61f400;
10831 }
10832
10833 static void
10834 Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
10835 {
10836   slotbuf[0] = 0x3f500;
10837 }
10838
10839 static void
10840 Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
10841 {
10842   slotbuf[0] = 0x13f500;
10843 }
10844
10845 static void
10846 Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
10847 {
10848   slotbuf[0] = 0x61f500;
10849 }
10850
10851 static void
10852 Opcode_rsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10853 {
10854   slotbuf[0] = 0x3f600;
10855 }
10856
10857 static void
10858 Opcode_wsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10859 {
10860   slotbuf[0] = 0x13f600;
10861 }
10862
10863 static void
10864 Opcode_xsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10865 {
10866   slotbuf[0] = 0x61f600;
10867 }
10868
10869 static void
10870 Opcode_rsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10871 {
10872   slotbuf[0] = 0x3f700;
10873 }
10874
10875 static void
10876 Opcode_wsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10877 {
10878   slotbuf[0] = 0x13f700;
10879 }
10880
10881 static void
10882 Opcode_xsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10883 {
10884   slotbuf[0] = 0x61f700;
10885 }
10886
10887 static void
10888 Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
10889 {
10890   slotbuf[0] = 0x3eb00;
10891 }
10892
10893 static void
10894 Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
10895 {
10896   slotbuf[0] = 0x3e700;
10897 }
10898
10899 static void
10900 Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
10901 {
10902   slotbuf[0] = 0x13e700;
10903 }
10904
10905 static void
10906 Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
10907 {
10908   slotbuf[0] = 0x61e700;
10909 }
10910
10911 static void
10912 Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
10913 {
10914   slotbuf[0] = 0x740004;
10915 }
10916
10917 static void
10918 Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
10919 {
10920   slotbuf[0] = 0x750004;
10921 }
10922
10923 static void
10924 Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
10925 {
10926   slotbuf[0] = 0x760004;
10927 }
10928
10929 static void
10930 Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
10931 {
10932   slotbuf[0] = 0x770004;
10933 }
10934
10935 static void
10936 Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
10937 {
10938   slotbuf[0] = 0x700004;
10939 }
10940
10941 static void
10942 Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
10943 {
10944   slotbuf[0] = 0x710004;
10945 }
10946
10947 static void
10948 Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
10949 {
10950   slotbuf[0] = 0x720004;
10951 }
10952
10953 static void
10954 Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
10955 {
10956   slotbuf[0] = 0x730004;
10957 }
10958
10959 static void
10960 Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
10961 {
10962   slotbuf[0] = 0x340004;
10963 }
10964
10965 static void
10966 Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
10967 {
10968   slotbuf[0] = 0x350004;
10969 }
10970
10971 static void
10972 Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
10973 {
10974   slotbuf[0] = 0x360004;
10975 }
10976
10977 static void
10978 Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
10979 {
10980   slotbuf[0] = 0x370004;
10981 }
10982
10983 static void
10984 Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
10985 {
10986   slotbuf[0] = 0x640004;
10987 }
10988
10989 static void
10990 Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
10991 {
10992   slotbuf[0] = 0x650004;
10993 }
10994
10995 static void
10996 Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
10997 {
10998   slotbuf[0] = 0x660004;
10999 }
11000
11001 static void
11002 Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11003 {
11004   slotbuf[0] = 0x670004;
11005 }
11006
11007 static void
11008 Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11009 {
11010   slotbuf[0] = 0x240004;
11011 }
11012
11013 static void
11014 Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11015 {
11016   slotbuf[0] = 0x250004;
11017 }
11018
11019 static void
11020 Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11021 {
11022   slotbuf[0] = 0x260004;
11023 }
11024
11025 static void
11026 Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11027 {
11028   slotbuf[0] = 0x270004;
11029 }
11030
11031 static void
11032 Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11033 {
11034   slotbuf[0] = 0x780004;
11035 }
11036
11037 static void
11038 Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11039 {
11040   slotbuf[0] = 0x790004;
11041 }
11042
11043 static void
11044 Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11045 {
11046   slotbuf[0] = 0x7a0004;
11047 }
11048
11049 static void
11050 Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11051 {
11052   slotbuf[0] = 0x7b0004;
11053 }
11054
11055 static void
11056 Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11057 {
11058   slotbuf[0] = 0x7c0004;
11059 }
11060
11061 static void
11062 Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11063 {
11064   slotbuf[0] = 0x7d0004;
11065 }
11066
11067 static void
11068 Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11069 {
11070   slotbuf[0] = 0x7e0004;
11071 }
11072
11073 static void
11074 Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11075 {
11076   slotbuf[0] = 0x7f0004;
11077 }
11078
11079 static void
11080 Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11081 {
11082   slotbuf[0] = 0x380004;
11083 }
11084
11085 static void
11086 Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11087 {
11088   slotbuf[0] = 0x390004;
11089 }
11090
11091 static void
11092 Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11093 {
11094   slotbuf[0] = 0x3a0004;
11095 }
11096
11097 static void
11098 Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11099 {
11100   slotbuf[0] = 0x3b0004;
11101 }
11102
11103 static void
11104 Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11105 {
11106   slotbuf[0] = 0x3c0004;
11107 }
11108
11109 static void
11110 Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11111 {
11112   slotbuf[0] = 0x3d0004;
11113 }
11114
11115 static void
11116 Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11117 {
11118   slotbuf[0] = 0x3e0004;
11119 }
11120
11121 static void
11122 Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11123 {
11124   slotbuf[0] = 0x3f0004;
11125 }
11126
11127 static void
11128 Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11129 {
11130   slotbuf[0] = 0x680004;
11131 }
11132
11133 static void
11134 Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11135 {
11136   slotbuf[0] = 0x690004;
11137 }
11138
11139 static void
11140 Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11141 {
11142   slotbuf[0] = 0x6a0004;
11143 }
11144
11145 static void
11146 Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11147 {
11148   slotbuf[0] = 0x6b0004;
11149 }
11150
11151 static void
11152 Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11153 {
11154   slotbuf[0] = 0x6c0004;
11155 }
11156
11157 static void
11158 Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11159 {
11160   slotbuf[0] = 0x6d0004;
11161 }
11162
11163 static void
11164 Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11165 {
11166   slotbuf[0] = 0x6e0004;
11167 }
11168
11169 static void
11170 Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11171 {
11172   slotbuf[0] = 0x6f0004;
11173 }
11174
11175 static void
11176 Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11177 {
11178   slotbuf[0] = 0x280004;
11179 }
11180
11181 static void
11182 Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11183 {
11184   slotbuf[0] = 0x290004;
11185 }
11186
11187 static void
11188 Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11189 {
11190   slotbuf[0] = 0x2a0004;
11191 }
11192
11193 static void
11194 Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11195 {
11196   slotbuf[0] = 0x2b0004;
11197 }
11198
11199 static void
11200 Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11201 {
11202   slotbuf[0] = 0x2c0004;
11203 }
11204
11205 static void
11206 Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11207 {
11208   slotbuf[0] = 0x2d0004;
11209 }
11210
11211 static void
11212 Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11213 {
11214   slotbuf[0] = 0x2e0004;
11215 }
11216
11217 static void
11218 Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11219 {
11220   slotbuf[0] = 0x2f0004;
11221 }
11222
11223 static void
11224 Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
11225 {
11226   slotbuf[0] = 0x580004;
11227 }
11228
11229 static void
11230 Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11231 {
11232   slotbuf[0] = 0x480004;
11233 }
11234
11235 static void
11236 Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
11237 {
11238   slotbuf[0] = 0x590004;
11239 }
11240
11241 static void
11242 Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11243 {
11244   slotbuf[0] = 0x490004;
11245 }
11246
11247 static void
11248 Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
11249 {
11250   slotbuf[0] = 0x5a0004;
11251 }
11252
11253 static void
11254 Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11255 {
11256   slotbuf[0] = 0x4a0004;
11257 }
11258
11259 static void
11260 Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
11261 {
11262   slotbuf[0] = 0x5b0004;
11263 }
11264
11265 static void
11266 Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11267 {
11268   slotbuf[0] = 0x4b0004;
11269 }
11270
11271 static void
11272 Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
11273 {
11274   slotbuf[0] = 0x180004;
11275 }
11276
11277 static void
11278 Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11279 {
11280   slotbuf[0] = 0x80004;
11281 }
11282
11283 static void
11284 Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
11285 {
11286   slotbuf[0] = 0x190004;
11287 }
11288
11289 static void
11290 Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11291 {
11292   slotbuf[0] = 0x90004;
11293 }
11294
11295 static void
11296 Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
11297 {
11298   slotbuf[0] = 0x1a0004;
11299 }
11300
11301 static void
11302 Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11303 {
11304   slotbuf[0] = 0xa0004;
11305 }
11306
11307 static void
11308 Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
11309 {
11310   slotbuf[0] = 0x1b0004;
11311 }
11312
11313 static void
11314 Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11315 {
11316   slotbuf[0] = 0xb0004;
11317 }
11318
11319 static void
11320 Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
11321 {
11322   slotbuf[0] = 0x900004;
11323 }
11324
11325 static void
11326 Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11327 {
11328   slotbuf[0] = 0x800004;
11329 }
11330
11331 static void
11332 Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
11333 {
11334   slotbuf[0] = 0xc10000;
11335 }
11336
11337 static void
11338 Opcode_mul16u_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
11339 {
11340   slotbuf[0] = 0x9b000;
11341 }
11342
11343 static void
11344 Opcode_mul16u_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
11345 {
11346   slotbuf[0] = 0xc1000;
11347 }
11348
11349 static void
11350 Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
11351 {
11352   slotbuf[0] = 0xd10000;
11353 }
11354
11355 static void
11356 Opcode_mul16s_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
11357 {
11358   slotbuf[0] = 0x9c000;
11359 }
11360
11361 static void
11362 Opcode_mul16s_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
11363 {
11364   slotbuf[0] = 0xd1000;
11365 }
11366
11367 static void
11368 Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11369 {
11370   slotbuf[0] = 0x32000;
11371 }
11372
11373 static void
11374 Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11375 {
11376   slotbuf[0] = 0x132000;
11377 }
11378
11379 static void
11380 Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11381 {
11382   slotbuf[0] = 0x612000;
11383 }
11384
11385 static void
11386 Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11387 {
11388   slotbuf[0] = 0x32100;
11389 }
11390
11391 static void
11392 Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11393 {
11394   slotbuf[0] = 0x132100;
11395 }
11396
11397 static void
11398 Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11399 {
11400   slotbuf[0] = 0x612100;
11401 }
11402
11403 static void
11404 Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11405 {
11406   slotbuf[0] = 0x32200;
11407 }
11408
11409 static void
11410 Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11411 {
11412   slotbuf[0] = 0x132200;
11413 }
11414
11415 static void
11416 Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11417 {
11418   slotbuf[0] = 0x612200;
11419 }
11420
11421 static void
11422 Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
11423 {
11424   slotbuf[0] = 0x32300;
11425 }
11426
11427 static void
11428 Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
11429 {
11430   slotbuf[0] = 0x132300;
11431 }
11432
11433 static void
11434 Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
11435 {
11436   slotbuf[0] = 0x612300;
11437 }
11438
11439 static void
11440 Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
11441 {
11442   slotbuf[0] = 0x31000;
11443 }
11444
11445 static void
11446 Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
11447 {
11448   slotbuf[0] = 0x131000;
11449 }
11450
11451 static void
11452 Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
11453 {
11454   slotbuf[0] = 0x611000;
11455 }
11456
11457 static void
11458 Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
11459 {
11460   slotbuf[0] = 0x31100;
11461 }
11462
11463 static void
11464 Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
11465 {
11466   slotbuf[0] = 0x131100;
11467 }
11468
11469 static void
11470 Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
11471 {
11472   slotbuf[0] = 0x611100;
11473 }
11474
11475 static void
11476 Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
11477 {
11478   slotbuf[0] = 0x3010;
11479 }
11480
11481 static void
11482 Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
11483 {
11484   slotbuf[0] = 0x7000;
11485 }
11486
11487 static void
11488 Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
11489 {
11490   slotbuf[0] = 0x3e200;
11491 }
11492
11493 static void
11494 Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
11495 {
11496   slotbuf[0] = 0x13e200;
11497 }
11498
11499 static void
11500 Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
11501 {
11502   slotbuf[0] = 0x13e300;
11503 }
11504
11505 static void
11506 Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
11507 {
11508   slotbuf[0] = 0x3e400;
11509 }
11510
11511 static void
11512 Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
11513 {
11514   slotbuf[0] = 0x13e400;
11515 }
11516
11517 static void
11518 Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
11519 {
11520   slotbuf[0] = 0x61e400;
11521 }
11522
11523 static void
11524 Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
11525 {
11526   slotbuf[0] = 0x4000;
11527 }
11528
11529 static void
11530 Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
11531 {
11532   slotbuf[0] = 0xf02d;
11533 }
11534
11535 static void
11536 Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11537 {
11538   slotbuf[0] = 0x39000;
11539 }
11540
11541 static void
11542 Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11543 {
11544   slotbuf[0] = 0x139000;
11545 }
11546
11547 static void
11548 Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11549 {
11550   slotbuf[0] = 0x619000;
11551 }
11552
11553 static void
11554 Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11555 {
11556   slotbuf[0] = 0x3a000;
11557 }
11558
11559 static void
11560 Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11561 {
11562   slotbuf[0] = 0x13a000;
11563 }
11564
11565 static void
11566 Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11567 {
11568   slotbuf[0] = 0x61a000;
11569 }
11570
11571 static void
11572 Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11573 {
11574   slotbuf[0] = 0x39100;
11575 }
11576
11577 static void
11578 Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11579 {
11580   slotbuf[0] = 0x139100;
11581 }
11582
11583 static void
11584 Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11585 {
11586   slotbuf[0] = 0x619100;
11587 }
11588
11589 static void
11590 Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11591 {
11592   slotbuf[0] = 0x3a100;
11593 }
11594
11595 static void
11596 Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11597 {
11598   slotbuf[0] = 0x13a100;
11599 }
11600
11601 static void
11602 Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11603 {
11604   slotbuf[0] = 0x61a100;
11605 }
11606
11607 static void
11608 Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11609 {
11610   slotbuf[0] = 0x38000;
11611 }
11612
11613 static void
11614 Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11615 {
11616   slotbuf[0] = 0x138000;
11617 }
11618
11619 static void
11620 Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11621 {
11622   slotbuf[0] = 0x618000;
11623 }
11624
11625 static void
11626 Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11627 {
11628   slotbuf[0] = 0x38100;
11629 }
11630
11631 static void
11632 Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11633 {
11634   slotbuf[0] = 0x138100;
11635 }
11636
11637 static void
11638 Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11639 {
11640   slotbuf[0] = 0x618100;
11641 }
11642
11643 static void
11644 Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
11645 {
11646   slotbuf[0] = 0x36000;
11647 }
11648
11649 static void
11650 Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
11651 {
11652   slotbuf[0] = 0x136000;
11653 }
11654
11655 static void
11656 Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
11657 {
11658   slotbuf[0] = 0x616000;
11659 }
11660
11661 static void
11662 Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
11663 {
11664   slotbuf[0] = 0x3e900;
11665 }
11666
11667 static void
11668 Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
11669 {
11670   slotbuf[0] = 0x13e900;
11671 }
11672
11673 static void
11674 Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
11675 {
11676   slotbuf[0] = 0x61e900;
11677 }
11678
11679 static void
11680 Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
11681 {
11682   slotbuf[0] = 0x3ec00;
11683 }
11684
11685 static void
11686 Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
11687 {
11688   slotbuf[0] = 0x13ec00;
11689 }
11690
11691 static void
11692 Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
11693 {
11694   slotbuf[0] = 0x61ec00;
11695 }
11696
11697 static void
11698 Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
11699 {
11700   slotbuf[0] = 0x3ed00;
11701 }
11702
11703 static void
11704 Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
11705 {
11706   slotbuf[0] = 0x13ed00;
11707 }
11708
11709 static void
11710 Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
11711 {
11712   slotbuf[0] = 0x61ed00;
11713 }
11714
11715 static void
11716 Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
11717 {
11718   slotbuf[0] = 0x36800;
11719 }
11720
11721 static void
11722 Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
11723 {
11724   slotbuf[0] = 0x136800;
11725 }
11726
11727 static void
11728 Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
11729 {
11730   slotbuf[0] = 0x616800;
11731 }
11732
11733 static void
11734 Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
11735 {
11736   slotbuf[0] = 0xf1e000;
11737 }
11738
11739 static void
11740 Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
11741 {
11742   slotbuf[0] = 0xf1e010;
11743 }
11744
11745 static void
11746 Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
11747 {
11748   slotbuf[0] = 0x135900;
11749 }
11750
11751 static void
11752 Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf)
11753 {
11754   slotbuf[0] = 0x20000;
11755 }
11756
11757 static void
11758 Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11759 {
11760   slotbuf[0] = 0x120000;
11761 }
11762
11763 static void
11764 Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf)
11765 {
11766   slotbuf[0] = 0x220000;
11767 }
11768
11769 static void
11770 Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11771 {
11772   slotbuf[0] = 0x320000;
11773 }
11774
11775 static void
11776 Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf)
11777 {
11778   slotbuf[0] = 0x420000;
11779 }
11780
11781 static void
11782 Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf)
11783 {
11784   slotbuf[0] = 0x8000;
11785 }
11786
11787 static void
11788 Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf)
11789 {
11790   slotbuf[0] = 0x9000;
11791 }
11792
11793 static void
11794 Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf)
11795 {
11796   slotbuf[0] = 0xa000;
11797 }
11798
11799 static void
11800 Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf)
11801 {
11802   slotbuf[0] = 0xb000;
11803 }
11804
11805 static void
11806 Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf)
11807 {
11808   slotbuf[0] = 0x76;
11809 }
11810
11811 static void
11812 Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf)
11813 {
11814   slotbuf[0] = 0x1076;
11815 }
11816
11817 static void
11818 Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf)
11819 {
11820   slotbuf[0] = 0xc30000;
11821 }
11822
11823 static void
11824 Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf)
11825 {
11826   slotbuf[0] = 0xd30000;
11827 }
11828
11829 static void
11830 Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
11831 {
11832   slotbuf[0] = 0x30400;
11833 }
11834
11835 static void
11836 Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
11837 {
11838   slotbuf[0] = 0x130400;
11839 }
11840
11841 static void
11842 Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
11843 {
11844   slotbuf[0] = 0x610400;
11845 }
11846
11847 static void
11848 Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
11849 {
11850   slotbuf[0] = 0x3ea00;
11851 }
11852
11853 static void
11854 Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
11855 {
11856   slotbuf[0] = 0x13ea00;
11857 }
11858
11859 static void
11860 Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
11861 {
11862   slotbuf[0] = 0x61ea00;
11863 }
11864
11865 static void
11866 Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11867 {
11868   slotbuf[0] = 0x3f000;
11869 }
11870
11871 static void
11872 Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11873 {
11874   slotbuf[0] = 0x13f000;
11875 }
11876
11877 static void
11878 Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11879 {
11880   slotbuf[0] = 0x61f000;
11881 }
11882
11883 static void
11884 Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11885 {
11886   slotbuf[0] = 0x3f100;
11887 }
11888
11889 static void
11890 Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11891 {
11892   slotbuf[0] = 0x13f100;
11893 }
11894
11895 static void
11896 Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11897 {
11898   slotbuf[0] = 0x61f100;
11899 }
11900
11901 static void
11902 Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11903 {
11904   slotbuf[0] = 0x3f200;
11905 }
11906
11907 static void
11908 Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11909 {
11910   slotbuf[0] = 0x13f200;
11911 }
11912
11913 static void
11914 Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11915 {
11916   slotbuf[0] = 0x61f200;
11917 }
11918
11919 static void
11920 Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
11921 {
11922   slotbuf[0] = 0x70c2;
11923 }
11924
11925 static void
11926 Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
11927 {
11928   slotbuf[0] = 0x70e2;
11929 }
11930
11931 static void
11932 Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11933 {
11934   slotbuf[0] = 0x70d2;
11935 }
11936
11937 static void
11938 Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf)
11939 {
11940   slotbuf[0] = 0x270d2;
11941 }
11942
11943 static void
11944 Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
11945 {
11946   slotbuf[0] = 0x370d2;
11947 }
11948
11949 static void
11950 Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
11951 {
11952   slotbuf[0] = 0x70f2;
11953 }
11954
11955 static void
11956 Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
11957 {
11958   slotbuf[0] = 0xf10000;
11959 }
11960
11961 static void
11962 Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
11963 {
11964   slotbuf[0] = 0xf12000;
11965 }
11966
11967 static void
11968 Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
11969 {
11970   slotbuf[0] = 0xf11000;
11971 }
11972
11973 static void
11974 Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
11975 {
11976   slotbuf[0] = 0xf13000;
11977 }
11978
11979 static void
11980 Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
11981 {
11982   slotbuf[0] = 0x7042;
11983 }
11984
11985 static void
11986 Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
11987 {
11988   slotbuf[0] = 0x7052;
11989 }
11990
11991 static void
11992 Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
11993 {
11994   slotbuf[0] = 0x47082;
11995 }
11996
11997 static void
11998 Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
11999 {
12000   slotbuf[0] = 0x57082;
12001 }
12002
12003 static void
12004 Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
12005 {
12006   slotbuf[0] = 0x7062;
12007 }
12008
12009 static void
12010 Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
12011 {
12012   slotbuf[0] = 0x7072;
12013 }
12014
12015 static void
12016 Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12017 {
12018   slotbuf[0] = 0x7002;
12019 }
12020
12021 static void
12022 Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
12023 {
12024   slotbuf[0] = 0x7012;
12025 }
12026
12027 static void
12028 Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
12029 {
12030   slotbuf[0] = 0x7022;
12031 }
12032
12033 static void
12034 Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
12035 {
12036   slotbuf[0] = 0x7032;
12037 }
12038
12039 static void
12040 Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
12041 {
12042   slotbuf[0] = 0x7082;
12043 }
12044
12045 static void
12046 Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12047 {
12048   slotbuf[0] = 0x27082;
12049 }
12050
12051 static void
12052 Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12053 {
12054   slotbuf[0] = 0x37082;
12055 }
12056
12057 static void
12058 Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
12059 {
12060   slotbuf[0] = 0xf19000;
12061 }
12062
12063 static void
12064 Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
12065 {
12066   slotbuf[0] = 0xf18000;
12067 }
12068
12069 static void
12070 Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12071 {
12072   slotbuf[0] = 0x135300;
12073 }
12074
12075 static void
12076 Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12077 {
12078   slotbuf[0] = 0x35300;
12079 }
12080
12081 static void
12082 Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12083 {
12084   slotbuf[0] = 0x615300;
12085 }
12086
12087 static void
12088 Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
12089 {
12090   slotbuf[0] = 0x35a00;
12091 }
12092
12093 static void
12094 Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
12095 {
12096   slotbuf[0] = 0x135a00;
12097 }
12098
12099 static void
12100 Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
12101 {
12102   slotbuf[0] = 0x615a00;
12103 }
12104
12105 static void
12106 Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
12107 {
12108   slotbuf[0] = 0x35b00;
12109 }
12110
12111 static void
12112 Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
12113 {
12114   slotbuf[0] = 0x135b00;
12115 }
12116
12117 static void
12118 Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
12119 {
12120   slotbuf[0] = 0x615b00;
12121 }
12122
12123 static void
12124 Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
12125 {
12126   slotbuf[0] = 0x35c00;
12127 }
12128
12129 static void
12130 Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
12131 {
12132   slotbuf[0] = 0x135c00;
12133 }
12134
12135 static void
12136 Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
12137 {
12138   slotbuf[0] = 0x615c00;
12139 }
12140
12141 static void
12142 Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12143 {
12144   slotbuf[0] = 0x50c000;
12145 }
12146
12147 static void
12148 Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12149 {
12150   slotbuf[0] = 0x50d000;
12151 }
12152
12153 static void
12154 Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
12155 {
12156   slotbuf[0] = 0x50b000;
12157 }
12158
12159 static void
12160 Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
12161 {
12162   slotbuf[0] = 0x50f000;
12163 }
12164
12165 static void
12166 Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12167 {
12168   slotbuf[0] = 0x50e000;
12169 }
12170
12171 static void
12172 Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12173 {
12174   slotbuf[0] = 0x504000;
12175 }
12176
12177 static void
12178 Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12179 {
12180   slotbuf[0] = 0x505000;
12181 }
12182
12183 static void
12184 Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
12185 {
12186   slotbuf[0] = 0x503000;
12187 }
12188
12189 static void
12190 Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
12191 {
12192   slotbuf[0] = 0x507000;
12193 }
12194
12195 static void
12196 Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12197 {
12198   slotbuf[0] = 0x506000;
12199 }
12200
12201 static void
12202 Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
12203 {
12204   slotbuf[0] = 0xf1f000;
12205 }
12206
12207 static void
12208 Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
12209 {
12210   slotbuf[0] = 0x501000;
12211 }
12212
12213 static void
12214 Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
12215 {
12216   slotbuf[0] = 0x509000;
12217 }
12218
12219 static void
12220 Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
12221 {
12222   slotbuf[0] = 0x3e000;
12223 }
12224
12225 static void
12226 Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
12227 {
12228   slotbuf[0] = 0x13e000;
12229 }
12230
12231 static void
12232 Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
12233 {
12234   slotbuf[0] = 0x61e000;
12235 }
12236
12237 static void
12238 Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
12239 {
12240   slotbuf[0] = 0x330000;
12241 }
12242
12243 static void
12244 Opcode_clamps_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12245 {
12246   slotbuf[0] = 0x33000;
12247 }
12248
12249 static void
12250 Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
12251 {
12252   slotbuf[0] = 0x430000;
12253 }
12254
12255 static void
12256 Opcode_min_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12257 {
12258   slotbuf[0] = 0x43000;
12259 }
12260
12261 static void
12262 Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
12263 {
12264   slotbuf[0] = 0x530000;
12265 }
12266
12267 static void
12268 Opcode_max_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12269 {
12270   slotbuf[0] = 0x53000;
12271 }
12272
12273 static void
12274 Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12275 {
12276   slotbuf[0] = 0x630000;
12277 }
12278
12279 static void
12280 Opcode_minu_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12281 {
12282   slotbuf[0] = 0x63000;
12283 }
12284
12285 static void
12286 Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12287 {
12288   slotbuf[0] = 0x730000;
12289 }
12290
12291 static void
12292 Opcode_maxu_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12293 {
12294   slotbuf[0] = 0x73000;
12295 }
12296
12297 static void
12298 Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
12299 {
12300   slotbuf[0] = 0x40e000;
12301 }
12302
12303 static void
12304 Opcode_nsa_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12305 {
12306   slotbuf[0] = 0x40e00;
12307 }
12308
12309 static void
12310 Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
12311 {
12312   slotbuf[0] = 0x40f000;
12313 }
12314
12315 static void
12316 Opcode_nsau_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12317 {
12318   slotbuf[0] = 0x40f00;
12319 }
12320
12321 static void
12322 Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
12323 {
12324   slotbuf[0] = 0x230000;
12325 }
12326
12327 static void
12328 Opcode_sext_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12329 {
12330   slotbuf[0] = 0x9f000;
12331 }
12332
12333 static void
12334 Opcode_sext_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12335 {
12336   slotbuf[0] = 0x8000;
12337 }
12338
12339 static void
12340 Opcode_sext_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12341 {
12342   slotbuf[0] = 0x23000;
12343 }
12344
12345 static void
12346 Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
12347 {
12348   slotbuf[0] = 0xb002;
12349 }
12350
12351 static void
12352 Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
12353 {
12354   slotbuf[0] = 0xf002;
12355 }
12356
12357 static void
12358 Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
12359 {
12360   slotbuf[0] = 0xe002;
12361 }
12362
12363 static void
12364 Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
12365 {
12366   slotbuf[0] = 0x30c00;
12367 }
12368
12369 static void
12370 Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
12371 {
12372   slotbuf[0] = 0x130c00;
12373 }
12374
12375 static void
12376 Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
12377 {
12378   slotbuf[0] = 0x610c00;
12379 }
12380
12381 static void
12382 Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
12383 {
12384   slotbuf[0] = 0xc20000;
12385 }
12386
12387 static void
12388 Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
12389 {
12390   slotbuf[0] = 0xd20000;
12391 }
12392
12393 static void
12394 Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12395 {
12396   slotbuf[0] = 0xe20000;
12397 }
12398
12399 static void
12400 Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
12401 {
12402   slotbuf[0] = 0xf20000;
12403 }
12404
12405 static void
12406 Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
12407 {
12408   slotbuf[0] = 0x820000;
12409 }
12410
12411 static void
12412 Opcode_mull_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12413 {
12414   slotbuf[0] = 0x9d000;
12415 }
12416
12417 static void
12418 Opcode_mull_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12419 {
12420   slotbuf[0] = 0x82000;
12421 }
12422
12423 static void
12424 Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf)
12425 {
12426   slotbuf[0] = 0xa20000;
12427 }
12428
12429 static void
12430 Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf)
12431 {
12432   slotbuf[0] = 0xb20000;
12433 }
12434
12435 static void
12436 Opcode_rur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12437 {
12438   slotbuf[0] = 0xe30e80;
12439 }
12440
12441 static void
12442 Opcode_wur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12443 {
12444   slotbuf[0] = 0xf3e800;
12445 }
12446
12447 static void
12448 Opcode_rur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12449 {
12450   slotbuf[0] = 0xe30e90;
12451 }
12452
12453 static void
12454 Opcode_wur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12455 {
12456   slotbuf[0] = 0xf3e900;
12457 }
12458
12459 static void
12460 Opcode_add_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12461 {
12462   slotbuf[0] = 0xa0000;
12463 }
12464
12465 static void
12466 Opcode_sub_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12467 {
12468   slotbuf[0] = 0x1a0000;
12469 }
12470
12471 static void
12472 Opcode_mul_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12473 {
12474   slotbuf[0] = 0x2a0000;
12475 }
12476
12477 static void
12478 Opcode_madd_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12479 {
12480   slotbuf[0] = 0x4a0000;
12481 }
12482
12483 static void
12484 Opcode_msub_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12485 {
12486   slotbuf[0] = 0x5a0000;
12487 }
12488
12489 static void
12490 Opcode_movf_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12491 {
12492   slotbuf[0] = 0xcb0000;
12493 }
12494
12495 static void
12496 Opcode_movt_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12497 {
12498   slotbuf[0] = 0xdb0000;
12499 }
12500
12501 static void
12502 Opcode_moveqz_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12503 {
12504   slotbuf[0] = 0x8b0000;
12505 }
12506
12507 static void
12508 Opcode_movnez_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12509 {
12510   slotbuf[0] = 0x9b0000;
12511 }
12512
12513 static void
12514 Opcode_movltz_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12515 {
12516   slotbuf[0] = 0xab0000;
12517 }
12518
12519 static void
12520 Opcode_movgez_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12521 {
12522   slotbuf[0] = 0xbb0000;
12523 }
12524
12525 static void
12526 Opcode_abs_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12527 {
12528   slotbuf[0] = 0xfa0010;
12529 }
12530
12531 static void
12532 Opcode_mov_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12533 {
12534   slotbuf[0] = 0xfa0000;
12535 }
12536
12537 static void
12538 Opcode_neg_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12539 {
12540   slotbuf[0] = 0xfa0060;
12541 }
12542
12543 static void
12544 Opcode_un_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12545 {
12546   slotbuf[0] = 0x1b0000;
12547 }
12548
12549 static void
12550 Opcode_oeq_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12551 {
12552   slotbuf[0] = 0x2b0000;
12553 }
12554
12555 static void
12556 Opcode_ueq_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12557 {
12558   slotbuf[0] = 0x3b0000;
12559 }
12560
12561 static void
12562 Opcode_olt_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12563 {
12564   slotbuf[0] = 0x4b0000;
12565 }
12566
12567 static void
12568 Opcode_ult_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12569 {
12570   slotbuf[0] = 0x5b0000;
12571 }
12572
12573 static void
12574 Opcode_ole_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12575 {
12576   slotbuf[0] = 0x6b0000;
12577 }
12578
12579 static void
12580 Opcode_ule_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12581 {
12582   slotbuf[0] = 0x7b0000;
12583 }
12584
12585 static void
12586 Opcode_float_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12587 {
12588   slotbuf[0] = 0xca0000;
12589 }
12590
12591 static void
12592 Opcode_ufloat_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12593 {
12594   slotbuf[0] = 0xda0000;
12595 }
12596
12597 static void
12598 Opcode_round_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12599 {
12600   slotbuf[0] = 0x8a0000;
12601 }
12602
12603 static void
12604 Opcode_ceil_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12605 {
12606   slotbuf[0] = 0xba0000;
12607 }
12608
12609 static void
12610 Opcode_floor_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12611 {
12612   slotbuf[0] = 0xaa0000;
12613 }
12614
12615 static void
12616 Opcode_trunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12617 {
12618   slotbuf[0] = 0x9a0000;
12619 }
12620
12621 static void
12622 Opcode_utrunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12623 {
12624   slotbuf[0] = 0xea0000;
12625 }
12626
12627 static void
12628 Opcode_rfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12629 {
12630   slotbuf[0] = 0xfa0040;
12631 }
12632
12633 static void
12634 Opcode_wfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12635 {
12636   slotbuf[0] = 0xfa0050;
12637 }
12638
12639 static void
12640 Opcode_lsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
12641 {
12642   slotbuf[0] = 0x3;
12643 }
12644
12645 static void
12646 Opcode_lsiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12647 {
12648   slotbuf[0] = 0x8003;
12649 }
12650
12651 static void
12652 Opcode_lsx_Slot_inst_encode (xtensa_insnbuf slotbuf)
12653 {
12654   slotbuf[0] = 0x80000;
12655 }
12656
12657 static void
12658 Opcode_lsxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12659 {
12660   slotbuf[0] = 0x180000;
12661 }
12662
12663 static void
12664 Opcode_ssi_Slot_inst_encode (xtensa_insnbuf slotbuf)
12665 {
12666   slotbuf[0] = 0x4003;
12667 }
12668
12669 static void
12670 Opcode_ssiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12671 {
12672   slotbuf[0] = 0xc003;
12673 }
12674
12675 static void
12676 Opcode_ssx_Slot_inst_encode (xtensa_insnbuf slotbuf)
12677 {
12678   slotbuf[0] = 0x480000;
12679 }
12680
12681 static void
12682 Opcode_ssxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12683 {
12684   slotbuf[0] = 0x580000;
12685 }
12686
12687 static void
12688 Opcode_beqz_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
12689 {
12690   slotbuf[0] = 0xa8000000;
12691   slotbuf[1] = 0;
12692 }
12693
12694 static void
12695 Opcode_bnez_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
12696 {
12697   slotbuf[0] = 0xc0000000;
12698   slotbuf[1] = 0;
12699 }
12700
12701 static void
12702 Opcode_bgez_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
12703 {
12704   slotbuf[0] = 0xb0000000;
12705   slotbuf[1] = 0;
12706 }
12707
12708 static void
12709 Opcode_bltz_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
12710 {
12711   slotbuf[0] = 0xb8000000;
12712   slotbuf[1] = 0;
12713 }
12714
12715 static void
12716 Opcode_beqi_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
12717 {
12718   slotbuf[0] = 0x40000000;
12719   slotbuf[1] = 0;
12720 }
12721
12722 static void
12723 Opcode_bnei_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
12724 {
12725   slotbuf[0] = 0x98000000;
12726   slotbuf[1] = 0;
12727 }
12728
12729 static void
12730 Opcode_bgei_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
12731 {
12732   slotbuf[0] = 0x50000000;
12733   slotbuf[1] = 0;
12734 }
12735
12736 static void
12737 Opcode_blti_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
12738 {
12739   slotbuf[0] = 0x70000000;
12740   slotbuf[1] = 0;
12741 }
12742
12743 static void
12744 Opcode_bgeui_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
12745 {
12746   slotbuf[0] = 0x60000000;
12747   slotbuf[1] = 0;
12748 }
12749
12750 static void
12751 Opcode_bltui_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
12752 {
12753   slotbuf[0] = 0x80000000;
12754   slotbuf[1] = 0;
12755 }
12756
12757 static void
12758 Opcode_bbci_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
12759 {
12760   slotbuf[0] = 0x8000000;
12761   slotbuf[1] = 0;
12762 }
12763
12764 static void
12765 Opcode_bbsi_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
12766 {
12767   slotbuf[0] = 0x10000000;
12768   slotbuf[1] = 0;
12769 }
12770
12771 static void
12772 Opcode_beq_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
12773 {
12774   slotbuf[0] = 0x38000000;
12775   slotbuf[1] = 0;
12776 }
12777
12778 static void
12779 Opcode_bne_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
12780 {
12781   slotbuf[0] = 0x90000000;
12782   slotbuf[1] = 0;
12783 }
12784
12785 static void
12786 Opcode_bge_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
12787 {
12788   slotbuf[0] = 0x48000000;
12789   slotbuf[1] = 0;
12790 }
12791
12792 static void
12793 Opcode_blt_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
12794 {
12795   slotbuf[0] = 0x68000000;
12796   slotbuf[1] = 0;
12797 }
12798
12799 static void
12800 Opcode_bgeu_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
12801 {
12802   slotbuf[0] = 0x58000000;
12803   slotbuf[1] = 0;
12804 }
12805
12806 static void
12807 Opcode_bltu_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
12808 {
12809   slotbuf[0] = 0x78000000;
12810   slotbuf[1] = 0;
12811 }
12812
12813 static void
12814 Opcode_bany_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
12815 {
12816   slotbuf[0] = 0x20000000;
12817   slotbuf[1] = 0;
12818 }
12819
12820 static void
12821 Opcode_bnone_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
12822 {
12823   slotbuf[0] = 0xa0000000;
12824   slotbuf[1] = 0;
12825 }
12826
12827 static void
12828 Opcode_ball_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
12829 {
12830   slotbuf[0] = 0x18000000;
12831   slotbuf[1] = 0;
12832 }
12833
12834 static void
12835 Opcode_bnall_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
12836 {
12837   slotbuf[0] = 0x88000000;
12838   slotbuf[1] = 0;
12839 }
12840
12841 static void
12842 Opcode_bbc_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
12843 {
12844   slotbuf[0] = 0x28000000;
12845   slotbuf[1] = 0;
12846 }
12847
12848 static void
12849 Opcode_bbs_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
12850 {
12851   slotbuf[0] = 0x30000000;
12852   slotbuf[1] = 0;
12853 }
12854
12855 const xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
12856   Opcode_excw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
12857 };
12858
12859 const xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
12860   Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
12861 };
12862
12863 const xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
12864   Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
12865 };
12866
12867 const xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
12868   Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
12869 };
12870
12871 const xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
12872   Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
12873 };
12874
12875 const xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
12876   Opcode_call12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
12877 };
12878
12879 const xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
12880   Opcode_call8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
12881 };
12882
12883 const xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
12884   Opcode_call4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
12885 };
12886
12887 const xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
12888   Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
12889 };
12890
12891 const xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
12892   Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
12893 };
12894
12895 const xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
12896   Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
12897 };
12898
12899 const xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
12900   Opcode_entry_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
12901 };
12902
12903 const xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
12904   Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
12905 };
12906
12907 const xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
12908   Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
12909 };
12910
12911 const xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
12912   Opcode_retw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
12913 };
12914
12915 const xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
12916   0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
12917 };
12918
12919 const xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
12920   Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
12921 };
12922
12923 const xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
12924   Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
12925 };
12926
12927 const xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
12928   Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
12929 };
12930
12931 const xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
12932   Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
12933 };
12934
12935 const xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
12936   Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
12937 };
12938
12939 const xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
12940   Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
12941 };
12942
12943 const xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
12944   Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
12945 };
12946
12947 const xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
12948   Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
12949 };
12950
12951 const xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
12952   Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
12953 };
12954
12955 const xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
12956   Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
12957 };
12958
12959 const xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
12960   0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0
12961 };
12962
12963 const xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
12964   0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0, 0, Opcode_addi_n_Slot_xt_flix64_slot2_encode, 0
12965 };
12966
12967 const xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
12968   0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
12969 };
12970
12971 const xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
12972   0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
12973 };
12974
12975 const xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
12976   0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
12977 };
12978
12979 const xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
12980   0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0
12981 };
12982
12983 const xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
12984   0, 0, Opcode_mov_n_Slot_inst16b_encode, Opcode_mov_n_Slot_xt_flix64_slot0_encode, Opcode_mov_n_Slot_xt_flix64_slot0_encode, Opcode_mov_n_Slot_xt_flix64_slot1_encode, Opcode_mov_n_Slot_xt_flix64_slot2_encode, 0
12985 };
12986
12987 const xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
12988   0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0, 0, Opcode_movi_n_Slot_xt_flix64_slot2_encode, 0
12989 };
12990
12991 const xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
12992   0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
12993 };
12994
12995 const xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
12996   0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
12997 };
12998
12999 const xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
13000   0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0
13001 };
13002
13003 const xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
13004   Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13005 };
13006
13007 const xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
13008   Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13009 };
13010
13011 const xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
13012   Opcode_addi_Slot_inst_encode, 0, 0, Opcode_addi_Slot_xt_flix64_slot0_encode, Opcode_addi_Slot_xt_flix64_slot0_encode, Opcode_addi_Slot_xt_flix64_slot1_encode, 0, 0
13013 };
13014
13015 const xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
13016   Opcode_addmi_Slot_inst_encode, 0, 0, Opcode_addmi_Slot_xt_flix64_slot0_encode, Opcode_addmi_Slot_xt_flix64_slot0_encode, Opcode_addmi_Slot_xt_flix64_slot1_encode, 0, 0
13017 };
13018
13019 const xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
13020   Opcode_add_Slot_inst_encode, 0, 0, Opcode_add_Slot_xt_flix64_slot0_encode, Opcode_add_Slot_xt_flix64_slot0_encode, Opcode_add_Slot_xt_flix64_slot1_encode, Opcode_add_Slot_xt_flix64_slot2_encode, 0
13021 };
13022
13023 const xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
13024   Opcode_sub_Slot_inst_encode, 0, 0, Opcode_sub_Slot_xt_flix64_slot0_encode, Opcode_sub_Slot_xt_flix64_slot0_encode, Opcode_sub_Slot_xt_flix64_slot1_encode, Opcode_sub_Slot_xt_flix64_slot2_encode, 0
13025 };
13026
13027 const xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
13028   Opcode_addx2_Slot_inst_encode, 0, 0, Opcode_addx2_Slot_xt_flix64_slot0_encode, Opcode_addx2_Slot_xt_flix64_slot0_encode, Opcode_addx2_Slot_xt_flix64_slot1_encode, Opcode_addx2_Slot_xt_flix64_slot2_encode, 0
13029 };
13030
13031 const xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
13032   Opcode_addx4_Slot_inst_encode, 0, 0, Opcode_addx4_Slot_xt_flix64_slot0_encode, Opcode_addx4_Slot_xt_flix64_slot0_encode, Opcode_addx4_Slot_xt_flix64_slot1_encode, Opcode_addx4_Slot_xt_flix64_slot2_encode, 0
13033 };
13034
13035 const xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
13036   Opcode_addx8_Slot_inst_encode, 0, 0, Opcode_addx8_Slot_xt_flix64_slot0_encode, Opcode_addx8_Slot_xt_flix64_slot0_encode, Opcode_addx8_Slot_xt_flix64_slot1_encode, 0, 0
13037 };
13038
13039 const xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
13040   Opcode_subx2_Slot_inst_encode, 0, 0, Opcode_subx2_Slot_xt_flix64_slot0_encode, Opcode_subx2_Slot_xt_flix64_slot0_encode, 0, 0, 0
13041 };
13042
13043 const xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
13044   Opcode_subx4_Slot_inst_encode, 0, 0, Opcode_subx4_Slot_xt_flix64_slot0_encode, Opcode_subx4_Slot_xt_flix64_slot0_encode, 0, 0, 0
13045 };
13046
13047 const xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
13048   Opcode_subx8_Slot_inst_encode, 0, 0, Opcode_subx8_Slot_xt_flix64_slot0_encode, Opcode_subx8_Slot_xt_flix64_slot0_encode, 0, 0, 0
13049 };
13050
13051 const xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
13052   Opcode_and_Slot_inst_encode, 0, 0, Opcode_and_Slot_xt_flix64_slot0_encode, Opcode_and_Slot_xt_flix64_slot0_encode, Opcode_and_Slot_xt_flix64_slot1_encode, Opcode_and_Slot_xt_flix64_slot2_encode, 0
13053 };
13054
13055 const xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
13056   Opcode_or_Slot_inst_encode, 0, 0, Opcode_or_Slot_xt_flix64_slot0_encode, Opcode_or_Slot_xt_flix64_slot0_encode, Opcode_or_Slot_xt_flix64_slot1_encode, Opcode_or_Slot_xt_flix64_slot2_encode, 0
13057 };
13058
13059 const xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
13060   Opcode_xor_Slot_inst_encode, 0, 0, Opcode_xor_Slot_xt_flix64_slot0_encode, Opcode_xor_Slot_xt_flix64_slot0_encode, Opcode_xor_Slot_xt_flix64_slot1_encode, Opcode_xor_Slot_xt_flix64_slot2_encode, 0
13061 };
13062
13063 const xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
13064   Opcode_beqi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13065 };
13066
13067 const xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
13068   Opcode_bnei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13069 };
13070
13071 const xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
13072   Opcode_bgei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13073 };
13074
13075 const xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
13076   Opcode_blti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13077 };
13078
13079 const xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
13080   Opcode_bbci_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13081 };
13082
13083 const xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
13084   Opcode_bbsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13085 };
13086
13087 const xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
13088   Opcode_bgeui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13089 };
13090
13091 const xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
13092   Opcode_bltui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13093 };
13094
13095 const xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
13096   Opcode_beq_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13097 };
13098
13099 const xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
13100   Opcode_bne_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13101 };
13102
13103 const xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
13104   Opcode_bge_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13105 };
13106
13107 const xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
13108   Opcode_blt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13109 };
13110
13111 const xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
13112   Opcode_bgeu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13113 };
13114
13115 const xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
13116   Opcode_bltu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13117 };
13118
13119 const xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
13120   Opcode_bany_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13121 };
13122
13123 const xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
13124   Opcode_bnone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13125 };
13126
13127 const xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
13128   Opcode_ball_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13129 };
13130
13131 const xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
13132   Opcode_bnall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13133 };
13134
13135 const xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
13136   Opcode_bbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13137 };
13138
13139 const xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
13140   Opcode_bbs_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13141 };
13142
13143 const xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
13144   Opcode_beqz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13145 };
13146
13147 const xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
13148   Opcode_bnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13149 };
13150
13151 const xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
13152   Opcode_bgez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13153 };
13154
13155 const xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
13156   Opcode_bltz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13157 };
13158
13159 const xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
13160   Opcode_call0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13161 };
13162
13163 const xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
13164   Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13165 };
13166
13167 const xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
13168   Opcode_extui_Slot_inst_encode, 0, 0, Opcode_extui_Slot_xt_flix64_slot0_encode, Opcode_extui_Slot_xt_flix64_slot0_encode, Opcode_extui_Slot_xt_flix64_slot1_encode, 0, 0
13169 };
13170
13171 const xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
13172   Opcode_ill_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13173 };
13174
13175 const xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
13176   Opcode_j_Slot_inst_encode, 0, 0, 0, 0, Opcode_j_Slot_xt_flix64_slot1_encode, 0, 0
13177 };
13178
13179 const xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
13180   Opcode_jx_Slot_inst_encode, 0, 0, 0, 0, Opcode_jx_Slot_xt_flix64_slot1_encode, 0, 0
13181 };
13182
13183 const xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
13184   Opcode_l16ui_Slot_inst_encode, 0, 0, Opcode_l16ui_Slot_xt_flix64_slot0_encode, Opcode_l16ui_Slot_xt_flix64_slot0_encode, 0, 0, 0
13185 };
13186
13187 const xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
13188   Opcode_l16si_Slot_inst_encode, 0, 0, Opcode_l16si_Slot_xt_flix64_slot0_encode, Opcode_l16si_Slot_xt_flix64_slot0_encode, 0, 0, 0
13189 };
13190
13191 const xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
13192   Opcode_l32i_Slot_inst_encode, 0, 0, Opcode_l32i_Slot_xt_flix64_slot0_encode, Opcode_l32i_Slot_xt_flix64_slot0_encode, 0, 0, 0
13193 };
13194
13195 const xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
13196   Opcode_l32r_Slot_inst_encode, 0, 0, Opcode_l32r_Slot_xt_flix64_slot0_encode, Opcode_l32r_Slot_xt_flix64_slot0_encode, 0, 0, 0
13197 };
13198
13199 const xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
13200   Opcode_l8ui_Slot_inst_encode, 0, 0, Opcode_l8ui_Slot_xt_flix64_slot0_encode, Opcode_l8ui_Slot_xt_flix64_slot0_encode, 0, 0, 0
13201 };
13202
13203 const xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
13204   Opcode_loop_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13205 };
13206
13207 const xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
13208   Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13209 };
13210
13211 const xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
13212   Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13213 };
13214
13215 const xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
13216   Opcode_movi_Slot_inst_encode, 0, 0, Opcode_movi_Slot_xt_flix64_slot0_encode, Opcode_movi_Slot_xt_flix64_slot0_encode, Opcode_movi_Slot_xt_flix64_slot1_encode, 0, 0
13217 };
13218
13219 const xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
13220   Opcode_moveqz_Slot_inst_encode, 0, 0, Opcode_moveqz_Slot_xt_flix64_slot0_encode, Opcode_moveqz_Slot_xt_flix64_slot0_encode, Opcode_moveqz_Slot_xt_flix64_slot1_encode, 0, 0
13221 };
13222
13223 const xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
13224   Opcode_movnez_Slot_inst_encode, 0, 0, Opcode_movnez_Slot_xt_flix64_slot0_encode, Opcode_movnez_Slot_xt_flix64_slot0_encode, Opcode_movnez_Slot_xt_flix64_slot1_encode, 0, 0
13225 };
13226
13227 const xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
13228   Opcode_movltz_Slot_inst_encode, 0, 0, Opcode_movltz_Slot_xt_flix64_slot0_encode, Opcode_movltz_Slot_xt_flix64_slot0_encode, Opcode_movltz_Slot_xt_flix64_slot1_encode, 0, 0
13229 };
13230
13231 const xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
13232   Opcode_movgez_Slot_inst_encode, 0, 0, Opcode_movgez_Slot_xt_flix64_slot0_encode, Opcode_movgez_Slot_xt_flix64_slot0_encode, Opcode_movgez_Slot_xt_flix64_slot1_encode, 0, 0
13233 };
13234
13235 const xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
13236   Opcode_neg_Slot_inst_encode, 0, 0, Opcode_neg_Slot_xt_flix64_slot0_encode, Opcode_neg_Slot_xt_flix64_slot0_encode, Opcode_neg_Slot_xt_flix64_slot1_encode, Opcode_neg_Slot_xt_flix64_slot2_encode, 0
13237 };
13238
13239 const xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
13240   Opcode_abs_Slot_inst_encode, 0, 0, Opcode_abs_Slot_xt_flix64_slot0_encode, Opcode_abs_Slot_xt_flix64_slot0_encode, 0, Opcode_abs_Slot_xt_flix64_slot2_encode, 0
13241 };
13242
13243 const xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
13244   Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_xt_flix64_slot0_encode, Opcode_nop_Slot_xt_flix64_slot0_encode, Opcode_nop_Slot_xt_flix64_slot1_encode, Opcode_nop_Slot_xt_flix64_slot2_encode, Opcode_nop_Slot_xt_flix64_slot3_encode
13245 };
13246
13247 const xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
13248   Opcode_ret_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13249 };
13250
13251 const xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
13252   Opcode_s16i_Slot_inst_encode, 0, 0, Opcode_s16i_Slot_xt_flix64_slot0_encode, Opcode_s16i_Slot_xt_flix64_slot0_encode, 0, 0, 0
13253 };
13254
13255 const xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
13256   Opcode_s32i_Slot_inst_encode, 0, 0, Opcode_s32i_Slot_xt_flix64_slot0_encode, Opcode_s32i_Slot_xt_flix64_slot0_encode, 0, 0, 0
13257 };
13258
13259 const xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
13260   Opcode_s8i_Slot_inst_encode, 0, 0, Opcode_s8i_Slot_xt_flix64_slot0_encode, Opcode_s8i_Slot_xt_flix64_slot0_encode, 0, 0, 0
13261 };
13262
13263 const xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
13264   Opcode_ssr_Slot_inst_encode, 0, 0, Opcode_ssr_Slot_xt_flix64_slot0_encode, Opcode_ssr_Slot_xt_flix64_slot0_encode, 0, 0, 0
13265 };
13266
13267 const xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
13268   Opcode_ssl_Slot_inst_encode, 0, 0, Opcode_ssl_Slot_xt_flix64_slot0_encode, Opcode_ssl_Slot_xt_flix64_slot0_encode, Opcode_ssl_Slot_xt_flix64_slot1_encode, 0, 0
13269 };
13270
13271 const xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
13272   Opcode_ssa8l_Slot_inst_encode, 0, 0, Opcode_ssa8l_Slot_xt_flix64_slot0_encode, Opcode_ssa8l_Slot_xt_flix64_slot0_encode, 0, 0, 0
13273 };
13274
13275 const xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
13276   Opcode_ssa8b_Slot_inst_encode, 0, 0, Opcode_ssa8b_Slot_xt_flix64_slot0_encode, Opcode_ssa8b_Slot_xt_flix64_slot0_encode, 0, 0, 0
13277 };
13278
13279 const xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
13280   Opcode_ssai_Slot_inst_encode, 0, 0, Opcode_ssai_Slot_xt_flix64_slot0_encode, Opcode_ssai_Slot_xt_flix64_slot0_encode, 0, 0, 0
13281 };
13282
13283 const xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
13284   Opcode_sll_Slot_inst_encode, 0, 0, Opcode_sll_Slot_xt_flix64_slot0_encode, Opcode_sll_Slot_xt_flix64_slot0_encode, Opcode_sll_Slot_xt_flix64_slot1_encode, 0, 0
13285 };
13286
13287 const xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
13288   Opcode_src_Slot_inst_encode, 0, 0, Opcode_src_Slot_xt_flix64_slot0_encode, Opcode_src_Slot_xt_flix64_slot0_encode, Opcode_src_Slot_xt_flix64_slot1_encode, 0, 0
13289 };
13290
13291 const xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
13292   Opcode_srl_Slot_inst_encode, 0, 0, Opcode_srl_Slot_xt_flix64_slot0_encode, Opcode_srl_Slot_xt_flix64_slot0_encode, Opcode_srl_Slot_xt_flix64_slot1_encode, Opcode_srl_Slot_xt_flix64_slot2_encode, 0
13293 };
13294
13295 const xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
13296   Opcode_sra_Slot_inst_encode, 0, 0, Opcode_sra_Slot_xt_flix64_slot0_encode, Opcode_sra_Slot_xt_flix64_slot0_encode, Opcode_sra_Slot_xt_flix64_slot1_encode, Opcode_sra_Slot_xt_flix64_slot2_encode, 0
13297 };
13298
13299 const xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
13300   Opcode_slli_Slot_inst_encode, 0, 0, Opcode_slli_Slot_xt_flix64_slot0_encode, Opcode_slli_Slot_xt_flix64_slot0_encode, Opcode_slli_Slot_xt_flix64_slot1_encode, 0, 0
13301 };
13302
13303 const xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
13304   Opcode_srai_Slot_inst_encode, 0, 0, Opcode_srai_Slot_xt_flix64_slot0_encode, Opcode_srai_Slot_xt_flix64_slot0_encode, Opcode_srai_Slot_xt_flix64_slot1_encode, Opcode_srai_Slot_xt_flix64_slot2_encode, 0
13305 };
13306
13307 const xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
13308   Opcode_srli_Slot_inst_encode, 0, 0, Opcode_srli_Slot_xt_flix64_slot0_encode, Opcode_srli_Slot_xt_flix64_slot0_encode, Opcode_srli_Slot_xt_flix64_slot1_encode, Opcode_srli_Slot_xt_flix64_slot2_encode, 0
13309 };
13310
13311 const xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
13312   Opcode_memw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13313 };
13314
13315 const xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
13316   Opcode_extw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13317 };
13318
13319 const xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
13320   Opcode_isync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13321 };
13322
13323 const xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
13324   Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13325 };
13326
13327 const xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
13328   Opcode_esync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13329 };
13330
13331 const xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
13332   Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13333 };
13334
13335 const xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
13336   Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13337 };
13338
13339 const xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
13340   Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13341 };
13342
13343 const xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
13344   Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13345 };
13346
13347 const xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
13348   Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13349 };
13350
13351 const xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
13352   Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13353 };
13354
13355 const xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
13356   Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13357 };
13358
13359 const xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
13360   Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13361 };
13362
13363 const xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
13364   Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13365 };
13366
13367 const xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
13368   Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13369 };
13370
13371 const xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
13372   Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13373 };
13374
13375 const xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
13376   Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13377 };
13378
13379 const xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
13380   Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13381 };
13382
13383 const xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
13384   Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13385 };
13386
13387 const xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
13388   Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13389 };
13390
13391 const xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
13392   Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13393 };
13394
13395 const xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
13396   Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13397 };
13398
13399 const xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
13400   Opcode_rsr_176_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13401 };
13402
13403 const xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
13404   Opcode_rsr_208_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13405 };
13406
13407 const xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
13408   Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13409 };
13410
13411 const xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
13412   Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13413 };
13414
13415 const xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
13416   Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13417 };
13418
13419 const xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
13420   Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13421 };
13422
13423 const xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
13424   Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13425 };
13426
13427 const xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
13428   Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13429 };
13430
13431 const xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
13432   Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13433 };
13434
13435 const xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
13436   Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13437 };
13438
13439 const xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
13440   Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13441 };
13442
13443 const xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
13444   Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13445 };
13446
13447 const xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
13448   Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13449 };
13450
13451 const xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
13452   Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13453 };
13454
13455 const xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
13456   Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13457 };
13458
13459 const xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
13460   Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13461 };
13462
13463 const xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
13464   Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13465 };
13466
13467 const xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
13468   Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13469 };
13470
13471 const xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
13472   Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13473 };
13474
13475 const xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
13476   Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13477 };
13478
13479 const xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
13480   Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13481 };
13482
13483 const xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
13484   Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13485 };
13486
13487 const xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
13488   Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13489 };
13490
13491 const xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
13492   Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13493 };
13494
13495 const xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
13496   Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13497 };
13498
13499 const xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
13500   Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13501 };
13502
13503 const xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
13504   Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13505 };
13506
13507 const xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
13508   Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13509 };
13510
13511 const xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
13512   Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13513 };
13514
13515 const xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
13516   Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13517 };
13518
13519 const xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
13520   Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13521 };
13522
13523 const xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
13524   Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13525 };
13526
13527 const xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
13528   Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13529 };
13530
13531 const xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
13532   Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13533 };
13534
13535 const xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
13536   Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13537 };
13538
13539 const xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
13540   Opcode_rsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13541 };
13542
13543 const xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
13544   Opcode_wsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13545 };
13546
13547 const xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
13548   Opcode_xsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13549 };
13550
13551 const xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
13552   Opcode_rsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13553 };
13554
13555 const xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
13556   Opcode_wsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13557 };
13558
13559 const xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
13560   Opcode_xsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13561 };
13562
13563 const xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
13564   Opcode_rsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13565 };
13566
13567 const xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
13568   Opcode_wsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13569 };
13570
13571 const xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
13572   Opcode_xsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13573 };
13574
13575 const xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
13576   Opcode_rsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13577 };
13578
13579 const xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
13580   Opcode_wsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13581 };
13582
13583 const xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
13584   Opcode_xsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13585 };
13586
13587 const xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
13588   Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13589 };
13590
13591 const xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
13592   Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13593 };
13594
13595 const xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
13596   Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13597 };
13598
13599 const xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
13600   Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13601 };
13602
13603 const xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
13604   Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13605 };
13606
13607 const xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
13608   Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13609 };
13610
13611 const xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
13612   Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13613 };
13614
13615 const xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
13616   Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13617 };
13618
13619 const xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
13620   Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13621 };
13622
13623 const xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
13624   Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13625 };
13626
13627 const xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
13628   Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13629 };
13630
13631 const xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
13632   Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13633 };
13634
13635 const xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
13636   Opcode_rsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13637 };
13638
13639 const xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
13640   Opcode_wsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13641 };
13642
13643 const xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
13644   Opcode_xsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13645 };
13646
13647 const xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
13648   Opcode_rsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13649 };
13650
13651 const xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
13652   Opcode_wsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13653 };
13654
13655 const xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
13656   Opcode_xsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13657 };
13658
13659 const xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
13660   Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13661 };
13662
13663 const xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
13664   Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13665 };
13666
13667 const xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
13668   Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13669 };
13670
13671 const xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
13672   Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13673 };
13674
13675 const xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
13676   Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13677 };
13678
13679 const xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
13680   Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13681 };
13682
13683 const xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
13684   Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13685 };
13686
13687 const xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
13688   Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13689 };
13690
13691 const xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
13692   Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13693 };
13694
13695 const xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
13696   Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13697 };
13698
13699 const xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
13700   Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13701 };
13702
13703 const xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
13704   Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13705 };
13706
13707 const xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
13708   Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13709 };
13710
13711 const xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
13712   Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13713 };
13714
13715 const xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
13716   Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13717 };
13718
13719 const xtensa_opcode_encode_fn Opcode_rsr_misc2_encode_fns[] = {
13720   Opcode_rsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13721 };
13722
13723 const xtensa_opcode_encode_fn Opcode_wsr_misc2_encode_fns[] = {
13724   Opcode_wsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13725 };
13726
13727 const xtensa_opcode_encode_fn Opcode_xsr_misc2_encode_fns[] = {
13728   Opcode_xsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13729 };
13730
13731 const xtensa_opcode_encode_fn Opcode_rsr_misc3_encode_fns[] = {
13732   Opcode_rsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13733 };
13734
13735 const xtensa_opcode_encode_fn Opcode_wsr_misc3_encode_fns[] = {
13736   Opcode_wsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13737 };
13738
13739 const xtensa_opcode_encode_fn Opcode_xsr_misc3_encode_fns[] = {
13740   Opcode_xsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13741 };
13742
13743 const xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
13744   Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13745 };
13746
13747 const xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
13748   Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13749 };
13750
13751 const xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
13752   Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13753 };
13754
13755 const xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
13756   Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13757 };
13758
13759 const xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = {
13760   Opcode_mul_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13761 };
13762
13763 const xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = {
13764   Opcode_mul_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13765 };
13766
13767 const xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = {
13768   Opcode_mul_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13769 };
13770
13771 const xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = {
13772   Opcode_mul_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13773 };
13774
13775 const xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = {
13776   Opcode_umul_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13777 };
13778
13779 const xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = {
13780   Opcode_umul_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13781 };
13782
13783 const xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = {
13784   Opcode_umul_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13785 };
13786
13787 const xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = {
13788   Opcode_umul_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13789 };
13790
13791 const xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = {
13792   Opcode_mul_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13793 };
13794
13795 const xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = {
13796   Opcode_mul_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13797 };
13798
13799 const xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = {
13800   Opcode_mul_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13801 };
13802
13803 const xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = {
13804   Opcode_mul_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13805 };
13806
13807 const xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = {
13808   Opcode_mul_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13809 };
13810
13811 const xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = {
13812   Opcode_mul_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13813 };
13814
13815 const xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = {
13816   Opcode_mul_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13817 };
13818
13819 const xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = {
13820   Opcode_mul_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13821 };
13822
13823 const xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = {
13824   Opcode_mul_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13825 };
13826
13827 const xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = {
13828   Opcode_mul_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13829 };
13830
13831 const xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = {
13832   Opcode_mul_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13833 };
13834
13835 const xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = {
13836   Opcode_mul_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13837 };
13838
13839 const xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = {
13840   Opcode_mula_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13841 };
13842
13843 const xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = {
13844   Opcode_mula_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13845 };
13846
13847 const xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = {
13848   Opcode_mula_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13849 };
13850
13851 const xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = {
13852   Opcode_mula_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13853 };
13854
13855 const xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = {
13856   Opcode_muls_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13857 };
13858
13859 const xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = {
13860   Opcode_muls_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13861 };
13862
13863 const xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = {
13864   Opcode_muls_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13865 };
13866
13867 const xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = {
13868   Opcode_muls_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13869 };
13870
13871 const xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = {
13872   Opcode_mula_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13873 };
13874
13875 const xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = {
13876   Opcode_mula_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13877 };
13878
13879 const xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = {
13880   Opcode_mula_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13881 };
13882
13883 const xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = {
13884   Opcode_mula_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13885 };
13886
13887 const xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = {
13888   Opcode_muls_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13889 };
13890
13891 const xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = {
13892   Opcode_muls_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13893 };
13894
13895 const xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = {
13896   Opcode_muls_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13897 };
13898
13899 const xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = {
13900   Opcode_muls_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13901 };
13902
13903 const xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = {
13904   Opcode_mula_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13905 };
13906
13907 const xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = {
13908   Opcode_mula_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13909 };
13910
13911 const xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = {
13912   Opcode_mula_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13913 };
13914
13915 const xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = {
13916   Opcode_mula_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13917 };
13918
13919 const xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = {
13920   Opcode_muls_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13921 };
13922
13923 const xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = {
13924   Opcode_muls_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13925 };
13926
13927 const xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = {
13928   Opcode_muls_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13929 };
13930
13931 const xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = {
13932   Opcode_muls_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13933 };
13934
13935 const xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = {
13936   Opcode_mula_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13937 };
13938
13939 const xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = {
13940   Opcode_mula_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13941 };
13942
13943 const xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = {
13944   Opcode_mula_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13945 };
13946
13947 const xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = {
13948   Opcode_mula_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13949 };
13950
13951 const xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = {
13952   Opcode_muls_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13953 };
13954
13955 const xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = {
13956   Opcode_muls_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13957 };
13958
13959 const xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = {
13960   Opcode_muls_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13961 };
13962
13963 const xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = {
13964   Opcode_muls_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13965 };
13966
13967 const xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = {
13968   Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13969 };
13970
13971 const xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = {
13972   Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13973 };
13974
13975 const xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = {
13976   Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13977 };
13978
13979 const xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = {
13980   Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13981 };
13982
13983 const xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = {
13984   Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13985 };
13986
13987 const xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = {
13988   Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13989 };
13990
13991 const xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = {
13992   Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13993 };
13994
13995 const xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = {
13996   Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13997 };
13998
13999 const xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = {
14000   Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14001 };
14002
14003 const xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = {
14004   Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14005 };
14006
14007 const xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = {
14008   Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14009 };
14010
14011 const xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = {
14012   Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14013 };
14014
14015 const xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = {
14016   Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14017 };
14018
14019 const xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = {
14020   Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14021 };
14022
14023 const xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = {
14024   Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14025 };
14026
14027 const xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = {
14028   Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14029 };
14030
14031 const xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = {
14032   Opcode_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14033 };
14034
14035 const xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = {
14036   Opcode_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14037 };
14038
14039 const xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
14040   Opcode_mul16u_Slot_inst_encode, 0, 0, Opcode_mul16u_Slot_xt_flix64_slot0_encode, Opcode_mul16u_Slot_xt_flix64_slot0_encode, Opcode_mul16u_Slot_xt_flix64_slot1_encode, 0, 0
14041 };
14042
14043 const xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
14044   Opcode_mul16s_Slot_inst_encode, 0, 0, Opcode_mul16s_Slot_xt_flix64_slot0_encode, Opcode_mul16s_Slot_xt_flix64_slot0_encode, Opcode_mul16s_Slot_xt_flix64_slot1_encode, 0, 0
14045 };
14046
14047 const xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = {
14048   Opcode_rsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14049 };
14050
14051 const xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = {
14052   Opcode_wsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14053 };
14054
14055 const xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = {
14056   Opcode_xsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14057 };
14058
14059 const xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = {
14060   Opcode_rsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14061 };
14062
14063 const xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = {
14064   Opcode_wsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14065 };
14066
14067 const xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = {
14068   Opcode_xsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14069 };
14070
14071 const xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = {
14072   Opcode_rsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14073 };
14074
14075 const xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = {
14076   Opcode_wsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14077 };
14078
14079 const xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = {
14080   Opcode_xsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14081 };
14082
14083 const xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = {
14084   Opcode_rsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14085 };
14086
14087 const xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = {
14088   Opcode_wsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14089 };
14090
14091 const xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = {
14092   Opcode_xsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14093 };
14094
14095 const xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = {
14096   Opcode_rsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14097 };
14098
14099 const xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = {
14100   Opcode_wsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14101 };
14102
14103 const xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = {
14104   Opcode_xsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14105 };
14106
14107 const xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = {
14108   Opcode_rsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14109 };
14110
14111 const xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = {
14112   Opcode_wsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14113 };
14114
14115 const xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = {
14116   Opcode_xsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14117 };
14118
14119 const xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
14120   Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14121 };
14122
14123 const xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
14124   Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14125 };
14126
14127 const xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
14128   Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14129 };
14130
14131 const xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
14132   Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14133 };
14134
14135 const xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
14136   Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14137 };
14138
14139 const xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
14140   Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14141 };
14142
14143 const xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
14144   Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14145 };
14146
14147 const xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
14148   Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14149 };
14150
14151 const xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
14152   Opcode_break_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14153 };
14154
14155 const xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
14156   0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
14157 };
14158
14159 const xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
14160   Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14161 };
14162
14163 const xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
14164   Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14165 };
14166
14167 const xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
14168   Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14169 };
14170
14171 const xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
14172   Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14173 };
14174
14175 const xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
14176   Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14177 };
14178
14179 const xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
14180   Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14181 };
14182
14183 const xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
14184   Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14185 };
14186
14187 const xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
14188   Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14189 };
14190
14191 const xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
14192   Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14193 };
14194
14195 const xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
14196   Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14197 };
14198
14199 const xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
14200   Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14201 };
14202
14203 const xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
14204   Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14205 };
14206
14207 const xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
14208   Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14209 };
14210
14211 const xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
14212   Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14213 };
14214
14215 const xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
14216   Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14217 };
14218
14219 const xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
14220   Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14221 };
14222
14223 const xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
14224   Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14225 };
14226
14227 const xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
14228   Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14229 };
14230
14231 const xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
14232   Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14233 };
14234
14235 const xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
14236   Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14237 };
14238
14239 const xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
14240   Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14241 };
14242
14243 const xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
14244   Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14245 };
14246
14247 const xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
14248   Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14249 };
14250
14251 const xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
14252   Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14253 };
14254
14255 const xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
14256   Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14257 };
14258
14259 const xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
14260   Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14261 };
14262
14263 const xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
14264   Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14265 };
14266
14267 const xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
14268   Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14269 };
14270
14271 const xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
14272   Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14273 };
14274
14275 const xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
14276   Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14277 };
14278
14279 const xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
14280   Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14281 };
14282
14283 const xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
14284   Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14285 };
14286
14287 const xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
14288   Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14289 };
14290
14291 const xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
14292   Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14293 };
14294
14295 const xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
14296   Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14297 };
14298
14299 const xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
14300   Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14301 };
14302
14303 const xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = {
14304   Opcode_andb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14305 };
14306
14307 const xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = {
14308   Opcode_andbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14309 };
14310
14311 const xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = {
14312   Opcode_orb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14313 };
14314
14315 const xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = {
14316   Opcode_orbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14317 };
14318
14319 const xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = {
14320   Opcode_xorb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14321 };
14322
14323 const xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = {
14324   Opcode_any4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14325 };
14326
14327 const xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = {
14328   Opcode_all4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14329 };
14330
14331 const xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = {
14332   Opcode_any8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14333 };
14334
14335 const xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = {
14336   Opcode_all8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14337 };
14338
14339 const xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = {
14340   Opcode_bf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14341 };
14342
14343 const xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = {
14344   Opcode_bt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14345 };
14346
14347 const xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = {
14348   Opcode_movf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14349 };
14350
14351 const xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = {
14352   Opcode_movt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14353 };
14354
14355 const xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = {
14356   Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14357 };
14358
14359 const xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = {
14360   Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14361 };
14362
14363 const xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = {
14364   Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14365 };
14366
14367 const xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
14368   Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14369 };
14370
14371 const xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
14372   Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14373 };
14374
14375 const xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
14376   Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14377 };
14378
14379 const xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
14380   Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14381 };
14382
14383 const xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
14384   Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14385 };
14386
14387 const xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
14388   Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14389 };
14390
14391 const xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
14392   Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14393 };
14394
14395 const xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
14396   Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14397 };
14398
14399 const xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
14400   Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14401 };
14402
14403 const xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
14404   Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14405 };
14406
14407 const xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
14408   Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14409 };
14410
14411 const xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
14412   Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14413 };
14414
14415 const xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
14416   Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14417 };
14418
14419 const xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
14420   Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14421 };
14422
14423 const xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = {
14424   Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14425 };
14426
14427 const xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = {
14428   Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14429 };
14430
14431 const xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = {
14432   Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14433 };
14434
14435 const xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
14436   Opcode_iii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14437 };
14438
14439 const xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
14440   Opcode_lict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14441 };
14442
14443 const xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
14444   Opcode_licw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14445 };
14446
14447 const xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
14448   Opcode_sict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14449 };
14450
14451 const xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
14452   Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14453 };
14454
14455 const xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
14456   Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14457 };
14458
14459 const xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
14460   Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14461 };
14462
14463 const xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
14464   Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14465 };
14466
14467 const xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
14468   Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14469 };
14470
14471 const xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
14472   Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14473 };
14474
14475 const xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
14476   Opcode_dii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14477 };
14478
14479 const xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
14480   Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14481 };
14482
14483 const xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
14484   Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14485 };
14486
14487 const xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
14488   Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14489 };
14490
14491 const xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
14492   Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14493 };
14494
14495 const xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = {
14496   Opcode_dpfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14497 };
14498
14499 const xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = {
14500   Opcode_dhu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14501 };
14502
14503 const xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = {
14504   Opcode_diu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14505 };
14506
14507 const xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
14508   Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14509 };
14510
14511 const xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
14512   Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14513 };
14514
14515 const xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
14516   Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14517 };
14518
14519 const xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
14520   Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14521 };
14522
14523 const xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
14524   Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14525 };
14526
14527 const xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
14528   Opcode_rsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14529 };
14530
14531 const xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
14532   Opcode_wsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14533 };
14534
14535 const xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
14536   Opcode_xsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14537 };
14538
14539 const xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
14540   Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14541 };
14542
14543 const xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
14544   Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14545 };
14546
14547 const xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
14548   Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14549 };
14550
14551 const xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
14552   Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14553 };
14554
14555 const xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
14556   Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14557 };
14558
14559 const xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
14560   Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14561 };
14562
14563 const xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
14564   Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14565 };
14566
14567 const xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
14568   Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14569 };
14570
14571 const xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
14572   Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14573 };
14574
14575 const xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
14576   Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14577 };
14578
14579 const xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
14580   Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14581 };
14582
14583 const xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
14584   Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14585 };
14586
14587 const xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
14588   Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14589 };
14590
14591 const xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
14592   Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14593 };
14594
14595 const xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
14596   Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14597 };
14598
14599 const xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
14600   Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14601 };
14602
14603 const xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
14604   Opcode_ldpte_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14605 };
14606
14607 const xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
14608   Opcode_hwwitlba_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14609 };
14610
14611 const xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
14612   Opcode_hwwdtlba_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14613 };
14614
14615 const xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
14616   Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14617 };
14618
14619 const xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
14620   Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14621 };
14622
14623 const xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
14624   Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14625 };
14626
14627 const xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
14628   Opcode_clamps_Slot_inst_encode, 0, 0, Opcode_clamps_Slot_xt_flix64_slot0_encode, Opcode_clamps_Slot_xt_flix64_slot0_encode, 0, 0, 0
14629 };
14630
14631 const xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
14632   Opcode_min_Slot_inst_encode, 0, 0, Opcode_min_Slot_xt_flix64_slot0_encode, Opcode_min_Slot_xt_flix64_slot0_encode, 0, 0, 0
14633 };
14634
14635 const xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
14636   Opcode_max_Slot_inst_encode, 0, 0, Opcode_max_Slot_xt_flix64_slot0_encode, Opcode_max_Slot_xt_flix64_slot0_encode, 0, 0, 0
14637 };
14638
14639 const xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
14640   Opcode_minu_Slot_inst_encode, 0, 0, Opcode_minu_Slot_xt_flix64_slot0_encode, Opcode_minu_Slot_xt_flix64_slot0_encode, 0, 0, 0
14641 };
14642
14643 const xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
14644   Opcode_maxu_Slot_inst_encode, 0, 0, Opcode_maxu_Slot_xt_flix64_slot0_encode, Opcode_maxu_Slot_xt_flix64_slot0_encode, 0, 0, 0
14645 };
14646
14647 const xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
14648   Opcode_nsa_Slot_inst_encode, 0, 0, Opcode_nsa_Slot_xt_flix64_slot0_encode, Opcode_nsa_Slot_xt_flix64_slot0_encode, 0, 0, 0
14649 };
14650
14651 const xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
14652   Opcode_nsau_Slot_inst_encode, 0, 0, Opcode_nsau_Slot_xt_flix64_slot0_encode, Opcode_nsau_Slot_xt_flix64_slot0_encode, 0, 0, 0
14653 };
14654
14655 const xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
14656   Opcode_sext_Slot_inst_encode, 0, 0, Opcode_sext_Slot_xt_flix64_slot0_encode, Opcode_sext_Slot_xt_flix64_slot0_encode, Opcode_sext_Slot_xt_flix64_slot1_encode, Opcode_sext_Slot_xt_flix64_slot2_encode, 0
14657 };
14658
14659 const xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
14660   Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14661 };
14662
14663 const xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
14664   Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14665 };
14666
14667 const xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
14668   Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14669 };
14670
14671 const xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
14672   Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14673 };
14674
14675 const xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
14676   Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14677 };
14678
14679 const xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
14680   Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14681 };
14682
14683 const xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
14684   Opcode_quou_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14685 };
14686
14687 const xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
14688   Opcode_quos_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14689 };
14690
14691 const xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
14692   Opcode_remu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14693 };
14694
14695 const xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
14696   Opcode_rems_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14697 };
14698
14699 const xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
14700   Opcode_mull_Slot_inst_encode, 0, 0, Opcode_mull_Slot_xt_flix64_slot0_encode, Opcode_mull_Slot_xt_flix64_slot0_encode, Opcode_mull_Slot_xt_flix64_slot1_encode, 0, 0
14701 };
14702
14703 const xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = {
14704   Opcode_muluh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14705 };
14706
14707 const xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = {
14708   Opcode_mulsh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14709 };
14710
14711 const xtensa_opcode_encode_fn Opcode_rur_fcr_encode_fns[] = {
14712   Opcode_rur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14713 };
14714
14715 const xtensa_opcode_encode_fn Opcode_wur_fcr_encode_fns[] = {
14716   Opcode_wur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14717 };
14718
14719 const xtensa_opcode_encode_fn Opcode_rur_fsr_encode_fns[] = {
14720   Opcode_rur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14721 };
14722
14723 const xtensa_opcode_encode_fn Opcode_wur_fsr_encode_fns[] = {
14724   Opcode_wur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14725 };
14726
14727 const xtensa_opcode_encode_fn Opcode_add_s_encode_fns[] = {
14728   Opcode_add_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14729 };
14730
14731 const xtensa_opcode_encode_fn Opcode_sub_s_encode_fns[] = {
14732   Opcode_sub_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14733 };
14734
14735 const xtensa_opcode_encode_fn Opcode_mul_s_encode_fns[] = {
14736   Opcode_mul_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14737 };
14738
14739 const xtensa_opcode_encode_fn Opcode_madd_s_encode_fns[] = {
14740   Opcode_madd_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14741 };
14742
14743 const xtensa_opcode_encode_fn Opcode_msub_s_encode_fns[] = {
14744   Opcode_msub_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14745 };
14746
14747 const xtensa_opcode_encode_fn Opcode_movf_s_encode_fns[] = {
14748   Opcode_movf_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14749 };
14750
14751 const xtensa_opcode_encode_fn Opcode_movt_s_encode_fns[] = {
14752   Opcode_movt_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14753 };
14754
14755 const xtensa_opcode_encode_fn Opcode_moveqz_s_encode_fns[] = {
14756   Opcode_moveqz_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14757 };
14758
14759 const xtensa_opcode_encode_fn Opcode_movnez_s_encode_fns[] = {
14760   Opcode_movnez_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14761 };
14762
14763 const xtensa_opcode_encode_fn Opcode_movltz_s_encode_fns[] = {
14764   Opcode_movltz_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14765 };
14766
14767 const xtensa_opcode_encode_fn Opcode_movgez_s_encode_fns[] = {
14768   Opcode_movgez_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14769 };
14770
14771 const xtensa_opcode_encode_fn Opcode_abs_s_encode_fns[] = {
14772   Opcode_abs_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14773 };
14774
14775 const xtensa_opcode_encode_fn Opcode_mov_s_encode_fns[] = {
14776   Opcode_mov_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14777 };
14778
14779 const xtensa_opcode_encode_fn Opcode_neg_s_encode_fns[] = {
14780   Opcode_neg_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14781 };
14782
14783 const xtensa_opcode_encode_fn Opcode_un_s_encode_fns[] = {
14784   Opcode_un_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14785 };
14786
14787 const xtensa_opcode_encode_fn Opcode_oeq_s_encode_fns[] = {
14788   Opcode_oeq_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14789 };
14790
14791 const xtensa_opcode_encode_fn Opcode_ueq_s_encode_fns[] = {
14792   Opcode_ueq_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14793 };
14794
14795 const xtensa_opcode_encode_fn Opcode_olt_s_encode_fns[] = {
14796   Opcode_olt_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14797 };
14798
14799 const xtensa_opcode_encode_fn Opcode_ult_s_encode_fns[] = {
14800   Opcode_ult_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14801 };
14802
14803 const xtensa_opcode_encode_fn Opcode_ole_s_encode_fns[] = {
14804   Opcode_ole_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14805 };
14806
14807 const xtensa_opcode_encode_fn Opcode_ule_s_encode_fns[] = {
14808   Opcode_ule_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14809 };
14810
14811 const xtensa_opcode_encode_fn Opcode_float_s_encode_fns[] = {
14812   Opcode_float_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14813 };
14814
14815 const xtensa_opcode_encode_fn Opcode_ufloat_s_encode_fns[] = {
14816   Opcode_ufloat_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14817 };
14818
14819 const xtensa_opcode_encode_fn Opcode_round_s_encode_fns[] = {
14820   Opcode_round_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14821 };
14822
14823 const xtensa_opcode_encode_fn Opcode_ceil_s_encode_fns[] = {
14824   Opcode_ceil_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14825 };
14826
14827 const xtensa_opcode_encode_fn Opcode_floor_s_encode_fns[] = {
14828   Opcode_floor_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14829 };
14830
14831 const xtensa_opcode_encode_fn Opcode_trunc_s_encode_fns[] = {
14832   Opcode_trunc_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14833 };
14834
14835 const xtensa_opcode_encode_fn Opcode_utrunc_s_encode_fns[] = {
14836   Opcode_utrunc_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14837 };
14838
14839 const xtensa_opcode_encode_fn Opcode_rfr_encode_fns[] = {
14840   Opcode_rfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14841 };
14842
14843 const xtensa_opcode_encode_fn Opcode_wfr_encode_fns[] = {
14844   Opcode_wfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14845 };
14846
14847 const xtensa_opcode_encode_fn Opcode_lsi_encode_fns[] = {
14848   Opcode_lsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14849 };
14850
14851 const xtensa_opcode_encode_fn Opcode_lsiu_encode_fns[] = {
14852   Opcode_lsiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14853 };
14854
14855 const xtensa_opcode_encode_fn Opcode_lsx_encode_fns[] = {
14856   Opcode_lsx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14857 };
14858
14859 const xtensa_opcode_encode_fn Opcode_lsxu_encode_fns[] = {
14860   Opcode_lsxu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14861 };
14862
14863 const xtensa_opcode_encode_fn Opcode_ssi_encode_fns[] = {
14864   Opcode_ssi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14865 };
14866
14867 const xtensa_opcode_encode_fn Opcode_ssiu_encode_fns[] = {
14868   Opcode_ssiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14869 };
14870
14871 const xtensa_opcode_encode_fn Opcode_ssx_encode_fns[] = {
14872   Opcode_ssx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14873 };
14874
14875 const xtensa_opcode_encode_fn Opcode_ssxu_encode_fns[] = {
14876   Opcode_ssxu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14877 };
14878
14879 const xtensa_opcode_encode_fn Opcode_beqz_w18_encode_fns[] = {
14880   0, 0, 0, 0, 0, 0, 0, Opcode_beqz_w18_Slot_xt_flix64_slot3_encode
14881 };
14882
14883 const xtensa_opcode_encode_fn Opcode_bnez_w18_encode_fns[] = {
14884   0, 0, 0, 0, 0, 0, 0, Opcode_bnez_w18_Slot_xt_flix64_slot3_encode
14885 };
14886
14887 const xtensa_opcode_encode_fn Opcode_bgez_w18_encode_fns[] = {
14888   0, 0, 0, 0, 0, 0, 0, Opcode_bgez_w18_Slot_xt_flix64_slot3_encode
14889 };
14890
14891 const xtensa_opcode_encode_fn Opcode_bltz_w18_encode_fns[] = {
14892   0, 0, 0, 0, 0, 0, 0, Opcode_bltz_w18_Slot_xt_flix64_slot3_encode
14893 };
14894
14895 const xtensa_opcode_encode_fn Opcode_beqi_w18_encode_fns[] = {
14896   0, 0, 0, 0, 0, 0, 0, Opcode_beqi_w18_Slot_xt_flix64_slot3_encode
14897 };
14898
14899 const xtensa_opcode_encode_fn Opcode_bnei_w18_encode_fns[] = {
14900   0, 0, 0, 0, 0, 0, 0, Opcode_bnei_w18_Slot_xt_flix64_slot3_encode
14901 };
14902
14903 const xtensa_opcode_encode_fn Opcode_bgei_w18_encode_fns[] = {
14904   0, 0, 0, 0, 0, 0, 0, Opcode_bgei_w18_Slot_xt_flix64_slot3_encode
14905 };
14906
14907 const xtensa_opcode_encode_fn Opcode_blti_w18_encode_fns[] = {
14908   0, 0, 0, 0, 0, 0, 0, Opcode_blti_w18_Slot_xt_flix64_slot3_encode
14909 };
14910
14911 const xtensa_opcode_encode_fn Opcode_bgeui_w18_encode_fns[] = {
14912   0, 0, 0, 0, 0, 0, 0, Opcode_bgeui_w18_Slot_xt_flix64_slot3_encode
14913 };
14914
14915 const xtensa_opcode_encode_fn Opcode_bltui_w18_encode_fns[] = {
14916   0, 0, 0, 0, 0, 0, 0, Opcode_bltui_w18_Slot_xt_flix64_slot3_encode
14917 };
14918
14919 const xtensa_opcode_encode_fn Opcode_bbci_w18_encode_fns[] = {
14920   0, 0, 0, 0, 0, 0, 0, Opcode_bbci_w18_Slot_xt_flix64_slot3_encode
14921 };
14922
14923 const xtensa_opcode_encode_fn Opcode_bbsi_w18_encode_fns[] = {
14924   0, 0, 0, 0, 0, 0, 0, Opcode_bbsi_w18_Slot_xt_flix64_slot3_encode
14925 };
14926
14927 const xtensa_opcode_encode_fn Opcode_beq_w18_encode_fns[] = {
14928   0, 0, 0, 0, 0, 0, 0, Opcode_beq_w18_Slot_xt_flix64_slot3_encode
14929 };
14930
14931 const xtensa_opcode_encode_fn Opcode_bne_w18_encode_fns[] = {
14932   0, 0, 0, 0, 0, 0, 0, Opcode_bne_w18_Slot_xt_flix64_slot3_encode
14933 };
14934
14935 const xtensa_opcode_encode_fn Opcode_bge_w18_encode_fns[] = {
14936   0, 0, 0, 0, 0, 0, 0, Opcode_bge_w18_Slot_xt_flix64_slot3_encode
14937 };
14938
14939 const xtensa_opcode_encode_fn Opcode_blt_w18_encode_fns[] = {
14940   0, 0, 0, 0, 0, 0, 0, Opcode_blt_w18_Slot_xt_flix64_slot3_encode
14941 };
14942
14943 const xtensa_opcode_encode_fn Opcode_bgeu_w18_encode_fns[] = {
14944   0, 0, 0, 0, 0, 0, 0, Opcode_bgeu_w18_Slot_xt_flix64_slot3_encode
14945 };
14946
14947 const xtensa_opcode_encode_fn Opcode_bltu_w18_encode_fns[] = {
14948   0, 0, 0, 0, 0, 0, 0, Opcode_bltu_w18_Slot_xt_flix64_slot3_encode
14949 };
14950
14951 const xtensa_opcode_encode_fn Opcode_bany_w18_encode_fns[] = {
14952   0, 0, 0, 0, 0, 0, 0, Opcode_bany_w18_Slot_xt_flix64_slot3_encode
14953 };
14954
14955 const xtensa_opcode_encode_fn Opcode_bnone_w18_encode_fns[] = {
14956   0, 0, 0, 0, 0, 0, 0, Opcode_bnone_w18_Slot_xt_flix64_slot3_encode
14957 };
14958
14959 const xtensa_opcode_encode_fn Opcode_ball_w18_encode_fns[] = {
14960   0, 0, 0, 0, 0, 0, 0, Opcode_ball_w18_Slot_xt_flix64_slot3_encode
14961 };
14962
14963 const xtensa_opcode_encode_fn Opcode_bnall_w18_encode_fns[] = {
14964   0, 0, 0, 0, 0, 0, 0, Opcode_bnall_w18_Slot_xt_flix64_slot3_encode
14965 };
14966
14967 const xtensa_opcode_encode_fn Opcode_bbc_w18_encode_fns[] = {
14968   0, 0, 0, 0, 0, 0, 0, Opcode_bbc_w18_Slot_xt_flix64_slot3_encode
14969 };
14970
14971 const xtensa_opcode_encode_fn Opcode_bbs_w18_encode_fns[] = {
14972   0, 0, 0, 0, 0, 0, 0, Opcode_bbs_w18_Slot_xt_flix64_slot3_encode
14973 };
14974
14975 \f
14976 /* Opcode table.  */
14977
14978 static xtensa_opcode_internal opcodes[] = {
14979   { "excw", 0 /* xt_iclass_excw */,
14980     0,
14981     Opcode_excw_encode_fns, 0, 0 },
14982   { "rfe", 1 /* xt_iclass_rfe */,
14983     XTENSA_OPCODE_IS_JUMP,
14984     Opcode_rfe_encode_fns, 0, 0 },
14985   { "rfde", 2 /* xt_iclass_rfde */,
14986     XTENSA_OPCODE_IS_JUMP,
14987     Opcode_rfde_encode_fns, 0, 0 },
14988   { "syscall", 3 /* xt_iclass_syscall */,
14989     0,
14990     Opcode_syscall_encode_fns, 0, 0 },
14991   { "simcall", 4 /* xt_iclass_simcall */,
14992     0,
14993     Opcode_simcall_encode_fns, 0, 0 },
14994   { "call12", 5 /* xt_iclass_call12 */,
14995     XTENSA_OPCODE_IS_CALL,
14996     Opcode_call12_encode_fns, 0, 0 },
14997   { "call8", 6 /* xt_iclass_call8 */,
14998     XTENSA_OPCODE_IS_CALL,
14999     Opcode_call8_encode_fns, 0, 0 },
15000   { "call4", 7 /* xt_iclass_call4 */,
15001     XTENSA_OPCODE_IS_CALL,
15002     Opcode_call4_encode_fns, 0, 0 },
15003   { "callx12", 8 /* xt_iclass_callx12 */,
15004     XTENSA_OPCODE_IS_CALL,
15005     Opcode_callx12_encode_fns, 0, 0 },
15006   { "callx8", 9 /* xt_iclass_callx8 */,
15007     XTENSA_OPCODE_IS_CALL,
15008     Opcode_callx8_encode_fns, 0, 0 },
15009   { "callx4", 10 /* xt_iclass_callx4 */,
15010     XTENSA_OPCODE_IS_CALL,
15011     Opcode_callx4_encode_fns, 0, 0 },
15012   { "entry", 11 /* xt_iclass_entry */,
15013     0,
15014     Opcode_entry_encode_fns, 0, 0 },
15015   { "movsp", 12 /* xt_iclass_movsp */,
15016     0,
15017     Opcode_movsp_encode_fns, 0, 0 },
15018   { "rotw", 13 /* xt_iclass_rotw */,
15019     0,
15020     Opcode_rotw_encode_fns, 0, 0 },
15021   { "retw", 14 /* xt_iclass_retw */,
15022     XTENSA_OPCODE_IS_JUMP,
15023     Opcode_retw_encode_fns, 0, 0 },
15024   { "retw.n", 14 /* xt_iclass_retw */,
15025     XTENSA_OPCODE_IS_JUMP,
15026     Opcode_retw_n_encode_fns, 0, 0 },
15027   { "rfwo", 15 /* xt_iclass_rfwou */,
15028     XTENSA_OPCODE_IS_JUMP,
15029     Opcode_rfwo_encode_fns, 0, 0 },
15030   { "rfwu", 15 /* xt_iclass_rfwou */,
15031     XTENSA_OPCODE_IS_JUMP,
15032     Opcode_rfwu_encode_fns, 0, 0 },
15033   { "l32e", 16 /* xt_iclass_l32e */,
15034     0,
15035     Opcode_l32e_encode_fns, 0, 0 },
15036   { "s32e", 17 /* xt_iclass_s32e */,
15037     0,
15038     Opcode_s32e_encode_fns, 0, 0 },
15039   { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */,
15040     0,
15041     Opcode_rsr_windowbase_encode_fns, 0, 0 },
15042   { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */,
15043     0,
15044     Opcode_wsr_windowbase_encode_fns, 0, 0 },
15045   { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */,
15046     0,
15047     Opcode_xsr_windowbase_encode_fns, 0, 0 },
15048   { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */,
15049     0,
15050     Opcode_rsr_windowstart_encode_fns, 0, 0 },
15051   { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */,
15052     0,
15053     Opcode_wsr_windowstart_encode_fns, 0, 0 },
15054   { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */,
15055     0,
15056     Opcode_xsr_windowstart_encode_fns, 0, 0 },
15057   { "add.n", 24 /* xt_iclass_add.n */,
15058     0,
15059     Opcode_add_n_encode_fns, 0, 0 },
15060   { "addi.n", 25 /* xt_iclass_addi.n */,
15061     0,
15062     Opcode_addi_n_encode_fns, 0, 0 },
15063   { "beqz.n", 26 /* xt_iclass_bz6 */,
15064     XTENSA_OPCODE_IS_BRANCH,
15065     Opcode_beqz_n_encode_fns, 0, 0 },
15066   { "bnez.n", 26 /* xt_iclass_bz6 */,
15067     XTENSA_OPCODE_IS_BRANCH,
15068     Opcode_bnez_n_encode_fns, 0, 0 },
15069   { "ill.n", 27 /* xt_iclass_ill.n */,
15070     0,
15071     Opcode_ill_n_encode_fns, 0, 0 },
15072   { "l32i.n", 28 /* xt_iclass_loadi4 */,
15073     0,
15074     Opcode_l32i_n_encode_fns, 0, 0 },
15075   { "mov.n", 29 /* xt_iclass_mov.n */,
15076     0,
15077     Opcode_mov_n_encode_fns, 0, 0 },
15078   { "movi.n", 30 /* xt_iclass_movi.n */,
15079     0,
15080     Opcode_movi_n_encode_fns, 0, 0 },
15081   { "nop.n", 31 /* xt_iclass_nopn */,
15082     0,
15083     Opcode_nop_n_encode_fns, 0, 0 },
15084   { "ret.n", 32 /* xt_iclass_retn */,
15085     XTENSA_OPCODE_IS_JUMP,
15086     Opcode_ret_n_encode_fns, 0, 0 },
15087   { "s32i.n", 33 /* xt_iclass_storei4 */,
15088     0,
15089     Opcode_s32i_n_encode_fns, 0, 0 },
15090   { "rur.threadptr", 34 /* rur_threadptr */,
15091     0,
15092     Opcode_rur_threadptr_encode_fns, 0, 0 },
15093   { "wur.threadptr", 35 /* wur_threadptr */,
15094     0,
15095     Opcode_wur_threadptr_encode_fns, 0, 0 },
15096   { "addi", 36 /* xt_iclass_addi */,
15097     0,
15098     Opcode_addi_encode_fns, 0, 0 },
15099   { "addmi", 37 /* xt_iclass_addmi */,
15100     0,
15101     Opcode_addmi_encode_fns, 0, 0 },
15102   { "add", 38 /* xt_iclass_addsub */,
15103     0,
15104     Opcode_add_encode_fns, 0, 0 },
15105   { "sub", 38 /* xt_iclass_addsub */,
15106     0,
15107     Opcode_sub_encode_fns, 0, 0 },
15108   { "addx2", 38 /* xt_iclass_addsub */,
15109     0,
15110     Opcode_addx2_encode_fns, 0, 0 },
15111   { "addx4", 38 /* xt_iclass_addsub */,
15112     0,
15113     Opcode_addx4_encode_fns, 0, 0 },
15114   { "addx8", 38 /* xt_iclass_addsub */,
15115     0,
15116     Opcode_addx8_encode_fns, 0, 0 },
15117   { "subx2", 38 /* xt_iclass_addsub */,
15118     0,
15119     Opcode_subx2_encode_fns, 0, 0 },
15120   { "subx4", 38 /* xt_iclass_addsub */,
15121     0,
15122     Opcode_subx4_encode_fns, 0, 0 },
15123   { "subx8", 38 /* xt_iclass_addsub */,
15124     0,
15125     Opcode_subx8_encode_fns, 0, 0 },
15126   { "and", 39 /* xt_iclass_bit */,
15127     0,
15128     Opcode_and_encode_fns, 0, 0 },
15129   { "or", 39 /* xt_iclass_bit */,
15130     0,
15131     Opcode_or_encode_fns, 0, 0 },
15132   { "xor", 39 /* xt_iclass_bit */,
15133     0,
15134     Opcode_xor_encode_fns, 0, 0 },
15135   { "beqi", 40 /* xt_iclass_bsi8 */,
15136     XTENSA_OPCODE_IS_BRANCH,
15137     Opcode_beqi_encode_fns, 0, 0 },
15138   { "bnei", 40 /* xt_iclass_bsi8 */,
15139     XTENSA_OPCODE_IS_BRANCH,
15140     Opcode_bnei_encode_fns, 0, 0 },
15141   { "bgei", 40 /* xt_iclass_bsi8 */,
15142     XTENSA_OPCODE_IS_BRANCH,
15143     Opcode_bgei_encode_fns, 0, 0 },
15144   { "blti", 40 /* xt_iclass_bsi8 */,
15145     XTENSA_OPCODE_IS_BRANCH,
15146     Opcode_blti_encode_fns, 0, 0 },
15147   { "bbci", 41 /* xt_iclass_bsi8b */,
15148     XTENSA_OPCODE_IS_BRANCH,
15149     Opcode_bbci_encode_fns, 0, 0 },
15150   { "bbsi", 41 /* xt_iclass_bsi8b */,
15151     XTENSA_OPCODE_IS_BRANCH,
15152     Opcode_bbsi_encode_fns, 0, 0 },
15153   { "bgeui", 42 /* xt_iclass_bsi8u */,
15154     XTENSA_OPCODE_IS_BRANCH,
15155     Opcode_bgeui_encode_fns, 0, 0 },
15156   { "bltui", 42 /* xt_iclass_bsi8u */,
15157     XTENSA_OPCODE_IS_BRANCH,
15158     Opcode_bltui_encode_fns, 0, 0 },
15159   { "beq", 43 /* xt_iclass_bst8 */,
15160     XTENSA_OPCODE_IS_BRANCH,
15161     Opcode_beq_encode_fns, 0, 0 },
15162   { "bne", 43 /* xt_iclass_bst8 */,
15163     XTENSA_OPCODE_IS_BRANCH,
15164     Opcode_bne_encode_fns, 0, 0 },
15165   { "bge", 43 /* xt_iclass_bst8 */,
15166     XTENSA_OPCODE_IS_BRANCH,
15167     Opcode_bge_encode_fns, 0, 0 },
15168   { "blt", 43 /* xt_iclass_bst8 */,
15169     XTENSA_OPCODE_IS_BRANCH,
15170     Opcode_blt_encode_fns, 0, 0 },
15171   { "bgeu", 43 /* xt_iclass_bst8 */,
15172     XTENSA_OPCODE_IS_BRANCH,
15173     Opcode_bgeu_encode_fns, 0, 0 },
15174   { "bltu", 43 /* xt_iclass_bst8 */,
15175     XTENSA_OPCODE_IS_BRANCH,
15176     Opcode_bltu_encode_fns, 0, 0 },
15177   { "bany", 43 /* xt_iclass_bst8 */,
15178     XTENSA_OPCODE_IS_BRANCH,
15179     Opcode_bany_encode_fns, 0, 0 },
15180   { "bnone", 43 /* xt_iclass_bst8 */,
15181     XTENSA_OPCODE_IS_BRANCH,
15182     Opcode_bnone_encode_fns, 0, 0 },
15183   { "ball", 43 /* xt_iclass_bst8 */,
15184     XTENSA_OPCODE_IS_BRANCH,
15185     Opcode_ball_encode_fns, 0, 0 },
15186   { "bnall", 43 /* xt_iclass_bst8 */,
15187     XTENSA_OPCODE_IS_BRANCH,
15188     Opcode_bnall_encode_fns, 0, 0 },
15189   { "bbc", 43 /* xt_iclass_bst8 */,
15190     XTENSA_OPCODE_IS_BRANCH,
15191     Opcode_bbc_encode_fns, 0, 0 },
15192   { "bbs", 43 /* xt_iclass_bst8 */,
15193     XTENSA_OPCODE_IS_BRANCH,
15194     Opcode_bbs_encode_fns, 0, 0 },
15195   { "beqz", 44 /* xt_iclass_bsz12 */,
15196     XTENSA_OPCODE_IS_BRANCH,
15197     Opcode_beqz_encode_fns, 0, 0 },
15198   { "bnez", 44 /* xt_iclass_bsz12 */,
15199     XTENSA_OPCODE_IS_BRANCH,
15200     Opcode_bnez_encode_fns, 0, 0 },
15201   { "bgez", 44 /* xt_iclass_bsz12 */,
15202     XTENSA_OPCODE_IS_BRANCH,
15203     Opcode_bgez_encode_fns, 0, 0 },
15204   { "bltz", 44 /* xt_iclass_bsz12 */,
15205     XTENSA_OPCODE_IS_BRANCH,
15206     Opcode_bltz_encode_fns, 0, 0 },
15207   { "call0", 45 /* xt_iclass_call0 */,
15208     XTENSA_OPCODE_IS_CALL,
15209     Opcode_call0_encode_fns, 0, 0 },
15210   { "callx0", 46 /* xt_iclass_callx0 */,
15211     XTENSA_OPCODE_IS_CALL,
15212     Opcode_callx0_encode_fns, 0, 0 },
15213   { "extui", 47 /* xt_iclass_exti */,
15214     0,
15215     Opcode_extui_encode_fns, 0, 0 },
15216   { "ill", 48 /* xt_iclass_ill */,
15217     0,
15218     Opcode_ill_encode_fns, 0, 0 },
15219   { "j", 49 /* xt_iclass_jump */,
15220     XTENSA_OPCODE_IS_JUMP,
15221     Opcode_j_encode_fns, 0, 0 },
15222   { "jx", 50 /* xt_iclass_jumpx */,
15223     XTENSA_OPCODE_IS_JUMP,
15224     Opcode_jx_encode_fns, 0, 0 },
15225   { "l16ui", 51 /* xt_iclass_l16ui */,
15226     0,
15227     Opcode_l16ui_encode_fns, 0, 0 },
15228   { "l16si", 52 /* xt_iclass_l16si */,
15229     0,
15230     Opcode_l16si_encode_fns, 0, 0 },
15231   { "l32i", 53 /* xt_iclass_l32i */,
15232     0,
15233     Opcode_l32i_encode_fns, 0, 0 },
15234   { "l32r", 54 /* xt_iclass_l32r */,
15235     0,
15236     Opcode_l32r_encode_fns, 0, 0 },
15237   { "l8ui", 55 /* xt_iclass_l8i */,
15238     0,
15239     Opcode_l8ui_encode_fns, 0, 0 },
15240   { "loop", 56 /* xt_iclass_loop */,
15241     XTENSA_OPCODE_IS_LOOP,
15242     Opcode_loop_encode_fns, 0, 0 },
15243   { "loopnez", 57 /* xt_iclass_loopz */,
15244     XTENSA_OPCODE_IS_LOOP,
15245     Opcode_loopnez_encode_fns, 0, 0 },
15246   { "loopgtz", 57 /* xt_iclass_loopz */,
15247     XTENSA_OPCODE_IS_LOOP,
15248     Opcode_loopgtz_encode_fns, 0, 0 },
15249   { "movi", 58 /* xt_iclass_movi */,
15250     0,
15251     Opcode_movi_encode_fns, 0, 0 },
15252   { "moveqz", 59 /* xt_iclass_movz */,
15253     0,
15254     Opcode_moveqz_encode_fns, 0, 0 },
15255   { "movnez", 59 /* xt_iclass_movz */,
15256     0,
15257     Opcode_movnez_encode_fns, 0, 0 },
15258   { "movltz", 59 /* xt_iclass_movz */,
15259     0,
15260     Opcode_movltz_encode_fns, 0, 0 },
15261   { "movgez", 59 /* xt_iclass_movz */,
15262     0,
15263     Opcode_movgez_encode_fns, 0, 0 },
15264   { "neg", 60 /* xt_iclass_neg */,
15265     0,
15266     Opcode_neg_encode_fns, 0, 0 },
15267   { "abs", 60 /* xt_iclass_neg */,
15268     0,
15269     Opcode_abs_encode_fns, 0, 0 },
15270   { "nop", 61 /* xt_iclass_nop */,
15271     0,
15272     Opcode_nop_encode_fns, 0, 0 },
15273   { "ret", 62 /* xt_iclass_return */,
15274     XTENSA_OPCODE_IS_JUMP,
15275     Opcode_ret_encode_fns, 0, 0 },
15276   { "s16i", 63 /* xt_iclass_s16i */,
15277     0,
15278     Opcode_s16i_encode_fns, 0, 0 },
15279   { "s32i", 64 /* xt_iclass_s32i */,
15280     0,
15281     Opcode_s32i_encode_fns, 0, 0 },
15282   { "s8i", 65 /* xt_iclass_s8i */,
15283     0,
15284     Opcode_s8i_encode_fns, 0, 0 },
15285   { "ssr", 66 /* xt_iclass_sar */,
15286     0,
15287     Opcode_ssr_encode_fns, 0, 0 },
15288   { "ssl", 66 /* xt_iclass_sar */,
15289     0,
15290     Opcode_ssl_encode_fns, 0, 0 },
15291   { "ssa8l", 66 /* xt_iclass_sar */,
15292     0,
15293     Opcode_ssa8l_encode_fns, 0, 0 },
15294   { "ssa8b", 66 /* xt_iclass_sar */,
15295     0,
15296     Opcode_ssa8b_encode_fns, 0, 0 },
15297   { "ssai", 67 /* xt_iclass_sari */,
15298     0,
15299     Opcode_ssai_encode_fns, 0, 0 },
15300   { "sll", 68 /* xt_iclass_shifts */,
15301     0,
15302     Opcode_sll_encode_fns, 0, 0 },
15303   { "src", 69 /* xt_iclass_shiftst */,
15304     0,
15305     Opcode_src_encode_fns, 0, 0 },
15306   { "srl", 70 /* xt_iclass_shiftt */,
15307     0,
15308     Opcode_srl_encode_fns, 0, 0 },
15309   { "sra", 70 /* xt_iclass_shiftt */,
15310     0,
15311     Opcode_sra_encode_fns, 0, 0 },
15312   { "slli", 71 /* xt_iclass_slli */,
15313     0,
15314     Opcode_slli_encode_fns, 0, 0 },
15315   { "srai", 72 /* xt_iclass_srai */,
15316     0,
15317     Opcode_srai_encode_fns, 0, 0 },
15318   { "srli", 73 /* xt_iclass_srli */,
15319     0,
15320     Opcode_srli_encode_fns, 0, 0 },
15321   { "memw", 74 /* xt_iclass_memw */,
15322     0,
15323     Opcode_memw_encode_fns, 0, 0 },
15324   { "extw", 75 /* xt_iclass_extw */,
15325     0,
15326     Opcode_extw_encode_fns, 0, 0 },
15327   { "isync", 76 /* xt_iclass_isync */,
15328     0,
15329     Opcode_isync_encode_fns, 0, 0 },
15330   { "rsync", 77 /* xt_iclass_sync */,
15331     0,
15332     Opcode_rsync_encode_fns, 0, 0 },
15333   { "esync", 77 /* xt_iclass_sync */,
15334     0,
15335     Opcode_esync_encode_fns, 0, 0 },
15336   { "dsync", 77 /* xt_iclass_sync */,
15337     0,
15338     Opcode_dsync_encode_fns, 0, 0 },
15339   { "rsil", 78 /* xt_iclass_rsil */,
15340     0,
15341     Opcode_rsil_encode_fns, 0, 0 },
15342   { "rsr.lend", 79 /* xt_iclass_rsr.lend */,
15343     0,
15344     Opcode_rsr_lend_encode_fns, 0, 0 },
15345   { "wsr.lend", 80 /* xt_iclass_wsr.lend */,
15346     0,
15347     Opcode_wsr_lend_encode_fns, 0, 0 },
15348   { "xsr.lend", 81 /* xt_iclass_xsr.lend */,
15349     0,
15350     Opcode_xsr_lend_encode_fns, 0, 0 },
15351   { "rsr.lcount", 82 /* xt_iclass_rsr.lcount */,
15352     0,
15353     Opcode_rsr_lcount_encode_fns, 0, 0 },
15354   { "wsr.lcount", 83 /* xt_iclass_wsr.lcount */,
15355     0,
15356     Opcode_wsr_lcount_encode_fns, 0, 0 },
15357   { "xsr.lcount", 84 /* xt_iclass_xsr.lcount */,
15358     0,
15359     Opcode_xsr_lcount_encode_fns, 0, 0 },
15360   { "rsr.lbeg", 85 /* xt_iclass_rsr.lbeg */,
15361     0,
15362     Opcode_rsr_lbeg_encode_fns, 0, 0 },
15363   { "wsr.lbeg", 86 /* xt_iclass_wsr.lbeg */,
15364     0,
15365     Opcode_wsr_lbeg_encode_fns, 0, 0 },
15366   { "xsr.lbeg", 87 /* xt_iclass_xsr.lbeg */,
15367     0,
15368     Opcode_xsr_lbeg_encode_fns, 0, 0 },
15369   { "rsr.sar", 88 /* xt_iclass_rsr.sar */,
15370     0,
15371     Opcode_rsr_sar_encode_fns, 0, 0 },
15372   { "wsr.sar", 89 /* xt_iclass_wsr.sar */,
15373     0,
15374     Opcode_wsr_sar_encode_fns, 0, 0 },
15375   { "xsr.sar", 90 /* xt_iclass_xsr.sar */,
15376     0,
15377     Opcode_xsr_sar_encode_fns, 0, 0 },
15378   { "rsr.litbase", 91 /* xt_iclass_rsr.litbase */,
15379     0,
15380     Opcode_rsr_litbase_encode_fns, 0, 0 },
15381   { "wsr.litbase", 92 /* xt_iclass_wsr.litbase */,
15382     0,
15383     Opcode_wsr_litbase_encode_fns, 0, 0 },
15384   { "xsr.litbase", 93 /* xt_iclass_xsr.litbase */,
15385     0,
15386     Opcode_xsr_litbase_encode_fns, 0, 0 },
15387   { "rsr.176", 94 /* xt_iclass_rsr.176 */,
15388     0,
15389     Opcode_rsr_176_encode_fns, 0, 0 },
15390   { "rsr.208", 95 /* xt_iclass_rsr.208 */,
15391     0,
15392     Opcode_rsr_208_encode_fns, 0, 0 },
15393   { "rsr.ps", 96 /* xt_iclass_rsr.ps */,
15394     0,
15395     Opcode_rsr_ps_encode_fns, 0, 0 },
15396   { "wsr.ps", 97 /* xt_iclass_wsr.ps */,
15397     0,
15398     Opcode_wsr_ps_encode_fns, 0, 0 },
15399   { "xsr.ps", 98 /* xt_iclass_xsr.ps */,
15400     0,
15401     Opcode_xsr_ps_encode_fns, 0, 0 },
15402   { "rsr.epc1", 99 /* xt_iclass_rsr.epc1 */,
15403     0,
15404     Opcode_rsr_epc1_encode_fns, 0, 0 },
15405   { "wsr.epc1", 100 /* xt_iclass_wsr.epc1 */,
15406     0,
15407     Opcode_wsr_epc1_encode_fns, 0, 0 },
15408   { "xsr.epc1", 101 /* xt_iclass_xsr.epc1 */,
15409     0,
15410     Opcode_xsr_epc1_encode_fns, 0, 0 },
15411   { "rsr.excsave1", 102 /* xt_iclass_rsr.excsave1 */,
15412     0,
15413     Opcode_rsr_excsave1_encode_fns, 0, 0 },
15414   { "wsr.excsave1", 103 /* xt_iclass_wsr.excsave1 */,
15415     0,
15416     Opcode_wsr_excsave1_encode_fns, 0, 0 },
15417   { "xsr.excsave1", 104 /* xt_iclass_xsr.excsave1 */,
15418     0,
15419     Opcode_xsr_excsave1_encode_fns, 0, 0 },
15420   { "rsr.epc2", 105 /* xt_iclass_rsr.epc2 */,
15421     0,
15422     Opcode_rsr_epc2_encode_fns, 0, 0 },
15423   { "wsr.epc2", 106 /* xt_iclass_wsr.epc2 */,
15424     0,
15425     Opcode_wsr_epc2_encode_fns, 0, 0 },
15426   { "xsr.epc2", 107 /* xt_iclass_xsr.epc2 */,
15427     0,
15428     Opcode_xsr_epc2_encode_fns, 0, 0 },
15429   { "rsr.excsave2", 108 /* xt_iclass_rsr.excsave2 */,
15430     0,
15431     Opcode_rsr_excsave2_encode_fns, 0, 0 },
15432   { "wsr.excsave2", 109 /* xt_iclass_wsr.excsave2 */,
15433     0,
15434     Opcode_wsr_excsave2_encode_fns, 0, 0 },
15435   { "xsr.excsave2", 110 /* xt_iclass_xsr.excsave2 */,
15436     0,
15437     Opcode_xsr_excsave2_encode_fns, 0, 0 },
15438   { "rsr.epc3", 111 /* xt_iclass_rsr.epc3 */,
15439     0,
15440     Opcode_rsr_epc3_encode_fns, 0, 0 },
15441   { "wsr.epc3", 112 /* xt_iclass_wsr.epc3 */,
15442     0,
15443     Opcode_wsr_epc3_encode_fns, 0, 0 },
15444   { "xsr.epc3", 113 /* xt_iclass_xsr.epc3 */,
15445     0,
15446     Opcode_xsr_epc3_encode_fns, 0, 0 },
15447   { "rsr.excsave3", 114 /* xt_iclass_rsr.excsave3 */,
15448     0,
15449     Opcode_rsr_excsave3_encode_fns, 0, 0 },
15450   { "wsr.excsave3", 115 /* xt_iclass_wsr.excsave3 */,
15451     0,
15452     Opcode_wsr_excsave3_encode_fns, 0, 0 },
15453   { "xsr.excsave3", 116 /* xt_iclass_xsr.excsave3 */,
15454     0,
15455     Opcode_xsr_excsave3_encode_fns, 0, 0 },
15456   { "rsr.epc4", 117 /* xt_iclass_rsr.epc4 */,
15457     0,
15458     Opcode_rsr_epc4_encode_fns, 0, 0 },
15459   { "wsr.epc4", 118 /* xt_iclass_wsr.epc4 */,
15460     0,
15461     Opcode_wsr_epc4_encode_fns, 0, 0 },
15462   { "xsr.epc4", 119 /* xt_iclass_xsr.epc4 */,
15463     0,
15464     Opcode_xsr_epc4_encode_fns, 0, 0 },
15465   { "rsr.excsave4", 120 /* xt_iclass_rsr.excsave4 */,
15466     0,
15467     Opcode_rsr_excsave4_encode_fns, 0, 0 },
15468   { "wsr.excsave4", 121 /* xt_iclass_wsr.excsave4 */,
15469     0,
15470     Opcode_wsr_excsave4_encode_fns, 0, 0 },
15471   { "xsr.excsave4", 122 /* xt_iclass_xsr.excsave4 */,
15472     0,
15473     Opcode_xsr_excsave4_encode_fns, 0, 0 },
15474   { "rsr.epc5", 123 /* xt_iclass_rsr.epc5 */,
15475     0,
15476     Opcode_rsr_epc5_encode_fns, 0, 0 },
15477   { "wsr.epc5", 124 /* xt_iclass_wsr.epc5 */,
15478     0,
15479     Opcode_wsr_epc5_encode_fns, 0, 0 },
15480   { "xsr.epc5", 125 /* xt_iclass_xsr.epc5 */,
15481     0,
15482     Opcode_xsr_epc5_encode_fns, 0, 0 },
15483   { "rsr.excsave5", 126 /* xt_iclass_rsr.excsave5 */,
15484     0,
15485     Opcode_rsr_excsave5_encode_fns, 0, 0 },
15486   { "wsr.excsave5", 127 /* xt_iclass_wsr.excsave5 */,
15487     0,
15488     Opcode_wsr_excsave5_encode_fns, 0, 0 },
15489   { "xsr.excsave5", 128 /* xt_iclass_xsr.excsave5 */,
15490     0,
15491     Opcode_xsr_excsave5_encode_fns, 0, 0 },
15492   { "rsr.epc6", 129 /* xt_iclass_rsr.epc6 */,
15493     0,
15494     Opcode_rsr_epc6_encode_fns, 0, 0 },
15495   { "wsr.epc6", 130 /* xt_iclass_wsr.epc6 */,
15496     0,
15497     Opcode_wsr_epc6_encode_fns, 0, 0 },
15498   { "xsr.epc6", 131 /* xt_iclass_xsr.epc6 */,
15499     0,
15500     Opcode_xsr_epc6_encode_fns, 0, 0 },
15501   { "rsr.excsave6", 132 /* xt_iclass_rsr.excsave6 */,
15502     0,
15503     Opcode_rsr_excsave6_encode_fns, 0, 0 },
15504   { "wsr.excsave6", 133 /* xt_iclass_wsr.excsave6 */,
15505     0,
15506     Opcode_wsr_excsave6_encode_fns, 0, 0 },
15507   { "xsr.excsave6", 134 /* xt_iclass_xsr.excsave6 */,
15508     0,
15509     Opcode_xsr_excsave6_encode_fns, 0, 0 },
15510   { "rsr.epc7", 135 /* xt_iclass_rsr.epc7 */,
15511     0,
15512     Opcode_rsr_epc7_encode_fns, 0, 0 },
15513   { "wsr.epc7", 136 /* xt_iclass_wsr.epc7 */,
15514     0,
15515     Opcode_wsr_epc7_encode_fns, 0, 0 },
15516   { "xsr.epc7", 137 /* xt_iclass_xsr.epc7 */,
15517     0,
15518     Opcode_xsr_epc7_encode_fns, 0, 0 },
15519   { "rsr.excsave7", 138 /* xt_iclass_rsr.excsave7 */,
15520     0,
15521     Opcode_rsr_excsave7_encode_fns, 0, 0 },
15522   { "wsr.excsave7", 139 /* xt_iclass_wsr.excsave7 */,
15523     0,
15524     Opcode_wsr_excsave7_encode_fns, 0, 0 },
15525   { "xsr.excsave7", 140 /* xt_iclass_xsr.excsave7 */,
15526     0,
15527     Opcode_xsr_excsave7_encode_fns, 0, 0 },
15528   { "rsr.eps2", 141 /* xt_iclass_rsr.eps2 */,
15529     0,
15530     Opcode_rsr_eps2_encode_fns, 0, 0 },
15531   { "wsr.eps2", 142 /* xt_iclass_wsr.eps2 */,
15532     0,
15533     Opcode_wsr_eps2_encode_fns, 0, 0 },
15534   { "xsr.eps2", 143 /* xt_iclass_xsr.eps2 */,
15535     0,
15536     Opcode_xsr_eps2_encode_fns, 0, 0 },
15537   { "rsr.eps3", 144 /* xt_iclass_rsr.eps3 */,
15538     0,
15539     Opcode_rsr_eps3_encode_fns, 0, 0 },
15540   { "wsr.eps3", 145 /* xt_iclass_wsr.eps3 */,
15541     0,
15542     Opcode_wsr_eps3_encode_fns, 0, 0 },
15543   { "xsr.eps3", 146 /* xt_iclass_xsr.eps3 */,
15544     0,
15545     Opcode_xsr_eps3_encode_fns, 0, 0 },
15546   { "rsr.eps4", 147 /* xt_iclass_rsr.eps4 */,
15547     0,
15548     Opcode_rsr_eps4_encode_fns, 0, 0 },
15549   { "wsr.eps4", 148 /* xt_iclass_wsr.eps4 */,
15550     0,
15551     Opcode_wsr_eps4_encode_fns, 0, 0 },
15552   { "xsr.eps4", 149 /* xt_iclass_xsr.eps4 */,
15553     0,
15554     Opcode_xsr_eps4_encode_fns, 0, 0 },
15555   { "rsr.eps5", 150 /* xt_iclass_rsr.eps5 */,
15556     0,
15557     Opcode_rsr_eps5_encode_fns, 0, 0 },
15558   { "wsr.eps5", 151 /* xt_iclass_wsr.eps5 */,
15559     0,
15560     Opcode_wsr_eps5_encode_fns, 0, 0 },
15561   { "xsr.eps5", 152 /* xt_iclass_xsr.eps5 */,
15562     0,
15563     Opcode_xsr_eps5_encode_fns, 0, 0 },
15564   { "rsr.eps6", 153 /* xt_iclass_rsr.eps6 */,
15565     0,
15566     Opcode_rsr_eps6_encode_fns, 0, 0 },
15567   { "wsr.eps6", 154 /* xt_iclass_wsr.eps6 */,
15568     0,
15569     Opcode_wsr_eps6_encode_fns, 0, 0 },
15570   { "xsr.eps6", 155 /* xt_iclass_xsr.eps6 */,
15571     0,
15572     Opcode_xsr_eps6_encode_fns, 0, 0 },
15573   { "rsr.eps7", 156 /* xt_iclass_rsr.eps7 */,
15574     0,
15575     Opcode_rsr_eps7_encode_fns, 0, 0 },
15576   { "wsr.eps7", 157 /* xt_iclass_wsr.eps7 */,
15577     0,
15578     Opcode_wsr_eps7_encode_fns, 0, 0 },
15579   { "xsr.eps7", 158 /* xt_iclass_xsr.eps7 */,
15580     0,
15581     Opcode_xsr_eps7_encode_fns, 0, 0 },
15582   { "rsr.excvaddr", 159 /* xt_iclass_rsr.excvaddr */,
15583     0,
15584     Opcode_rsr_excvaddr_encode_fns, 0, 0 },
15585   { "wsr.excvaddr", 160 /* xt_iclass_wsr.excvaddr */,
15586     0,
15587     Opcode_wsr_excvaddr_encode_fns, 0, 0 },
15588   { "xsr.excvaddr", 161 /* xt_iclass_xsr.excvaddr */,
15589     0,
15590     Opcode_xsr_excvaddr_encode_fns, 0, 0 },
15591   { "rsr.depc", 162 /* xt_iclass_rsr.depc */,
15592     0,
15593     Opcode_rsr_depc_encode_fns, 0, 0 },
15594   { "wsr.depc", 163 /* xt_iclass_wsr.depc */,
15595     0,
15596     Opcode_wsr_depc_encode_fns, 0, 0 },
15597   { "xsr.depc", 164 /* xt_iclass_xsr.depc */,
15598     0,
15599     Opcode_xsr_depc_encode_fns, 0, 0 },
15600   { "rsr.exccause", 165 /* xt_iclass_rsr.exccause */,
15601     0,
15602     Opcode_rsr_exccause_encode_fns, 0, 0 },
15603   { "wsr.exccause", 166 /* xt_iclass_wsr.exccause */,
15604     0,
15605     Opcode_wsr_exccause_encode_fns, 0, 0 },
15606   { "xsr.exccause", 167 /* xt_iclass_xsr.exccause */,
15607     0,
15608     Opcode_xsr_exccause_encode_fns, 0, 0 },
15609   { "rsr.misc0", 168 /* xt_iclass_rsr.misc0 */,
15610     0,
15611     Opcode_rsr_misc0_encode_fns, 0, 0 },
15612   { "wsr.misc0", 169 /* xt_iclass_wsr.misc0 */,
15613     0,
15614     Opcode_wsr_misc0_encode_fns, 0, 0 },
15615   { "xsr.misc0", 170 /* xt_iclass_xsr.misc0 */,
15616     0,
15617     Opcode_xsr_misc0_encode_fns, 0, 0 },
15618   { "rsr.misc1", 171 /* xt_iclass_rsr.misc1 */,
15619     0,
15620     Opcode_rsr_misc1_encode_fns, 0, 0 },
15621   { "wsr.misc1", 172 /* xt_iclass_wsr.misc1 */,
15622     0,
15623     Opcode_wsr_misc1_encode_fns, 0, 0 },
15624   { "xsr.misc1", 173 /* xt_iclass_xsr.misc1 */,
15625     0,
15626     Opcode_xsr_misc1_encode_fns, 0, 0 },
15627   { "rsr.misc2", 174 /* xt_iclass_rsr.misc2 */,
15628     0,
15629     Opcode_rsr_misc2_encode_fns, 0, 0 },
15630   { "wsr.misc2", 175 /* xt_iclass_wsr.misc2 */,
15631     0,
15632     Opcode_wsr_misc2_encode_fns, 0, 0 },
15633   { "xsr.misc2", 176 /* xt_iclass_xsr.misc2 */,
15634     0,
15635     Opcode_xsr_misc2_encode_fns, 0, 0 },
15636   { "rsr.misc3", 177 /* xt_iclass_rsr.misc3 */,
15637     0,
15638     Opcode_rsr_misc3_encode_fns, 0, 0 },
15639   { "wsr.misc3", 178 /* xt_iclass_wsr.misc3 */,
15640     0,
15641     Opcode_wsr_misc3_encode_fns, 0, 0 },
15642   { "xsr.misc3", 179 /* xt_iclass_xsr.misc3 */,
15643     0,
15644     Opcode_xsr_misc3_encode_fns, 0, 0 },
15645   { "rsr.prid", 180 /* xt_iclass_rsr.prid */,
15646     0,
15647     Opcode_rsr_prid_encode_fns, 0, 0 },
15648   { "rsr.vecbase", 181 /* xt_iclass_rsr.vecbase */,
15649     0,
15650     Opcode_rsr_vecbase_encode_fns, 0, 0 },
15651   { "wsr.vecbase", 182 /* xt_iclass_wsr.vecbase */,
15652     0,
15653     Opcode_wsr_vecbase_encode_fns, 0, 0 },
15654   { "xsr.vecbase", 183 /* xt_iclass_xsr.vecbase */,
15655     0,
15656     Opcode_xsr_vecbase_encode_fns, 0, 0 },
15657   { "mul.aa.ll", 184 /* xt_iclass_mac16_aa */,
15658     0,
15659     Opcode_mul_aa_ll_encode_fns, 0, 0 },
15660   { "mul.aa.hl", 184 /* xt_iclass_mac16_aa */,
15661     0,
15662     Opcode_mul_aa_hl_encode_fns, 0, 0 },
15663   { "mul.aa.lh", 184 /* xt_iclass_mac16_aa */,
15664     0,
15665     Opcode_mul_aa_lh_encode_fns, 0, 0 },
15666   { "mul.aa.hh", 184 /* xt_iclass_mac16_aa */,
15667     0,
15668     Opcode_mul_aa_hh_encode_fns, 0, 0 },
15669   { "umul.aa.ll", 184 /* xt_iclass_mac16_aa */,
15670     0,
15671     Opcode_umul_aa_ll_encode_fns, 0, 0 },
15672   { "umul.aa.hl", 184 /* xt_iclass_mac16_aa */,
15673     0,
15674     Opcode_umul_aa_hl_encode_fns, 0, 0 },
15675   { "umul.aa.lh", 184 /* xt_iclass_mac16_aa */,
15676     0,
15677     Opcode_umul_aa_lh_encode_fns, 0, 0 },
15678   { "umul.aa.hh", 184 /* xt_iclass_mac16_aa */,
15679     0,
15680     Opcode_umul_aa_hh_encode_fns, 0, 0 },
15681   { "mul.ad.ll", 185 /* xt_iclass_mac16_ad */,
15682     0,
15683     Opcode_mul_ad_ll_encode_fns, 0, 0 },
15684   { "mul.ad.hl", 185 /* xt_iclass_mac16_ad */,
15685     0,
15686     Opcode_mul_ad_hl_encode_fns, 0, 0 },
15687   { "mul.ad.lh", 185 /* xt_iclass_mac16_ad */,
15688     0,
15689     Opcode_mul_ad_lh_encode_fns, 0, 0 },
15690   { "mul.ad.hh", 185 /* xt_iclass_mac16_ad */,
15691     0,
15692     Opcode_mul_ad_hh_encode_fns, 0, 0 },
15693   { "mul.da.ll", 186 /* xt_iclass_mac16_da */,
15694     0,
15695     Opcode_mul_da_ll_encode_fns, 0, 0 },
15696   { "mul.da.hl", 186 /* xt_iclass_mac16_da */,
15697     0,
15698     Opcode_mul_da_hl_encode_fns, 0, 0 },
15699   { "mul.da.lh", 186 /* xt_iclass_mac16_da */,
15700     0,
15701     Opcode_mul_da_lh_encode_fns, 0, 0 },
15702   { "mul.da.hh", 186 /* xt_iclass_mac16_da */,
15703     0,
15704     Opcode_mul_da_hh_encode_fns, 0, 0 },
15705   { "mul.dd.ll", 187 /* xt_iclass_mac16_dd */,
15706     0,
15707     Opcode_mul_dd_ll_encode_fns, 0, 0 },
15708   { "mul.dd.hl", 187 /* xt_iclass_mac16_dd */,
15709     0,
15710     Opcode_mul_dd_hl_encode_fns, 0, 0 },
15711   { "mul.dd.lh", 187 /* xt_iclass_mac16_dd */,
15712     0,
15713     Opcode_mul_dd_lh_encode_fns, 0, 0 },
15714   { "mul.dd.hh", 187 /* xt_iclass_mac16_dd */,
15715     0,
15716     Opcode_mul_dd_hh_encode_fns, 0, 0 },
15717   { "mula.aa.ll", 188 /* xt_iclass_mac16a_aa */,
15718     0,
15719     Opcode_mula_aa_ll_encode_fns, 0, 0 },
15720   { "mula.aa.hl", 188 /* xt_iclass_mac16a_aa */,
15721     0,
15722     Opcode_mula_aa_hl_encode_fns, 0, 0 },
15723   { "mula.aa.lh", 188 /* xt_iclass_mac16a_aa */,
15724     0,
15725     Opcode_mula_aa_lh_encode_fns, 0, 0 },
15726   { "mula.aa.hh", 188 /* xt_iclass_mac16a_aa */,
15727     0,
15728     Opcode_mula_aa_hh_encode_fns, 0, 0 },
15729   { "muls.aa.ll", 188 /* xt_iclass_mac16a_aa */,
15730     0,
15731     Opcode_muls_aa_ll_encode_fns, 0, 0 },
15732   { "muls.aa.hl", 188 /* xt_iclass_mac16a_aa */,
15733     0,
15734     Opcode_muls_aa_hl_encode_fns, 0, 0 },
15735   { "muls.aa.lh", 188 /* xt_iclass_mac16a_aa */,
15736     0,
15737     Opcode_muls_aa_lh_encode_fns, 0, 0 },
15738   { "muls.aa.hh", 188 /* xt_iclass_mac16a_aa */,
15739     0,
15740     Opcode_muls_aa_hh_encode_fns, 0, 0 },
15741   { "mula.ad.ll", 189 /* xt_iclass_mac16a_ad */,
15742     0,
15743     Opcode_mula_ad_ll_encode_fns, 0, 0 },
15744   { "mula.ad.hl", 189 /* xt_iclass_mac16a_ad */,
15745     0,
15746     Opcode_mula_ad_hl_encode_fns, 0, 0 },
15747   { "mula.ad.lh", 189 /* xt_iclass_mac16a_ad */,
15748     0,
15749     Opcode_mula_ad_lh_encode_fns, 0, 0 },
15750   { "mula.ad.hh", 189 /* xt_iclass_mac16a_ad */,
15751     0,
15752     Opcode_mula_ad_hh_encode_fns, 0, 0 },
15753   { "muls.ad.ll", 189 /* xt_iclass_mac16a_ad */,
15754     0,
15755     Opcode_muls_ad_ll_encode_fns, 0, 0 },
15756   { "muls.ad.hl", 189 /* xt_iclass_mac16a_ad */,
15757     0,
15758     Opcode_muls_ad_hl_encode_fns, 0, 0 },
15759   { "muls.ad.lh", 189 /* xt_iclass_mac16a_ad */,
15760     0,
15761     Opcode_muls_ad_lh_encode_fns, 0, 0 },
15762   { "muls.ad.hh", 189 /* xt_iclass_mac16a_ad */,
15763     0,
15764     Opcode_muls_ad_hh_encode_fns, 0, 0 },
15765   { "mula.da.ll", 190 /* xt_iclass_mac16a_da */,
15766     0,
15767     Opcode_mula_da_ll_encode_fns, 0, 0 },
15768   { "mula.da.hl", 190 /* xt_iclass_mac16a_da */,
15769     0,
15770     Opcode_mula_da_hl_encode_fns, 0, 0 },
15771   { "mula.da.lh", 190 /* xt_iclass_mac16a_da */,
15772     0,
15773     Opcode_mula_da_lh_encode_fns, 0, 0 },
15774   { "mula.da.hh", 190 /* xt_iclass_mac16a_da */,
15775     0,
15776     Opcode_mula_da_hh_encode_fns, 0, 0 },
15777   { "muls.da.ll", 190 /* xt_iclass_mac16a_da */,
15778     0,
15779     Opcode_muls_da_ll_encode_fns, 0, 0 },
15780   { "muls.da.hl", 190 /* xt_iclass_mac16a_da */,
15781     0,
15782     Opcode_muls_da_hl_encode_fns, 0, 0 },
15783   { "muls.da.lh", 190 /* xt_iclass_mac16a_da */,
15784     0,
15785     Opcode_muls_da_lh_encode_fns, 0, 0 },
15786   { "muls.da.hh", 190 /* xt_iclass_mac16a_da */,
15787     0,
15788     Opcode_muls_da_hh_encode_fns, 0, 0 },
15789   { "mula.dd.ll", 191 /* xt_iclass_mac16a_dd */,
15790     0,
15791     Opcode_mula_dd_ll_encode_fns, 0, 0 },
15792   { "mula.dd.hl", 191 /* xt_iclass_mac16a_dd */,
15793     0,
15794     Opcode_mula_dd_hl_encode_fns, 0, 0 },
15795   { "mula.dd.lh", 191 /* xt_iclass_mac16a_dd */,
15796     0,
15797     Opcode_mula_dd_lh_encode_fns, 0, 0 },
15798   { "mula.dd.hh", 191 /* xt_iclass_mac16a_dd */,
15799     0,
15800     Opcode_mula_dd_hh_encode_fns, 0, 0 },
15801   { "muls.dd.ll", 191 /* xt_iclass_mac16a_dd */,
15802     0,
15803     Opcode_muls_dd_ll_encode_fns, 0, 0 },
15804   { "muls.dd.hl", 191 /* xt_iclass_mac16a_dd */,
15805     0,
15806     Opcode_muls_dd_hl_encode_fns, 0, 0 },
15807   { "muls.dd.lh", 191 /* xt_iclass_mac16a_dd */,
15808     0,
15809     Opcode_muls_dd_lh_encode_fns, 0, 0 },
15810   { "muls.dd.hh", 191 /* xt_iclass_mac16a_dd */,
15811     0,
15812     Opcode_muls_dd_hh_encode_fns, 0, 0 },
15813   { "mula.da.ll.lddec", 192 /* xt_iclass_mac16al_da */,
15814     0,
15815     Opcode_mula_da_ll_lddec_encode_fns, 0, 0 },
15816   { "mula.da.ll.ldinc", 192 /* xt_iclass_mac16al_da */,
15817     0,
15818     Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 },
15819   { "mula.da.hl.lddec", 192 /* xt_iclass_mac16al_da */,
15820     0,
15821     Opcode_mula_da_hl_lddec_encode_fns, 0, 0 },
15822   { "mula.da.hl.ldinc", 192 /* xt_iclass_mac16al_da */,
15823     0,
15824     Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 },
15825   { "mula.da.lh.lddec", 192 /* xt_iclass_mac16al_da */,
15826     0,
15827     Opcode_mula_da_lh_lddec_encode_fns, 0, 0 },
15828   { "mula.da.lh.ldinc", 192 /* xt_iclass_mac16al_da */,
15829     0,
15830     Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 },
15831   { "mula.da.hh.lddec", 192 /* xt_iclass_mac16al_da */,
15832     0,
15833     Opcode_mula_da_hh_lddec_encode_fns, 0, 0 },
15834   { "mula.da.hh.ldinc", 192 /* xt_iclass_mac16al_da */,
15835     0,
15836     Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 },
15837   { "mula.dd.ll.lddec", 193 /* xt_iclass_mac16al_dd */,
15838     0,
15839     Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 },
15840   { "mula.dd.ll.ldinc", 193 /* xt_iclass_mac16al_dd */,
15841     0,
15842     Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 },
15843   { "mula.dd.hl.lddec", 193 /* xt_iclass_mac16al_dd */,
15844     0,
15845     Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 },
15846   { "mula.dd.hl.ldinc", 193 /* xt_iclass_mac16al_dd */,
15847     0,
15848     Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 },
15849   { "mula.dd.lh.lddec", 193 /* xt_iclass_mac16al_dd */,
15850     0,
15851     Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 },
15852   { "mula.dd.lh.ldinc", 193 /* xt_iclass_mac16al_dd */,
15853     0,
15854     Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 },
15855   { "mula.dd.hh.lddec", 193 /* xt_iclass_mac16al_dd */,
15856     0,
15857     Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 },
15858   { "mula.dd.hh.ldinc", 193 /* xt_iclass_mac16al_dd */,
15859     0,
15860     Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 },
15861   { "lddec", 194 /* xt_iclass_mac16_l */,
15862     0,
15863     Opcode_lddec_encode_fns, 0, 0 },
15864   { "ldinc", 194 /* xt_iclass_mac16_l */,
15865     0,
15866     Opcode_ldinc_encode_fns, 0, 0 },
15867   { "mul16u", 195 /* xt_iclass_mul16 */,
15868     0,
15869     Opcode_mul16u_encode_fns, 0, 0 },
15870   { "mul16s", 195 /* xt_iclass_mul16 */,
15871     0,
15872     Opcode_mul16s_encode_fns, 0, 0 },
15873   { "rsr.m0", 196 /* xt_iclass_rsr.m0 */,
15874     0,
15875     Opcode_rsr_m0_encode_fns, 0, 0 },
15876   { "wsr.m0", 197 /* xt_iclass_wsr.m0 */,
15877     0,
15878     Opcode_wsr_m0_encode_fns, 0, 0 },
15879   { "xsr.m0", 198 /* xt_iclass_xsr.m0 */,
15880     0,
15881     Opcode_xsr_m0_encode_fns, 0, 0 },
15882   { "rsr.m1", 199 /* xt_iclass_rsr.m1 */,
15883     0,
15884     Opcode_rsr_m1_encode_fns, 0, 0 },
15885   { "wsr.m1", 200 /* xt_iclass_wsr.m1 */,
15886     0,
15887     Opcode_wsr_m1_encode_fns, 0, 0 },
15888   { "xsr.m1", 201 /* xt_iclass_xsr.m1 */,
15889     0,
15890     Opcode_xsr_m1_encode_fns, 0, 0 },
15891   { "rsr.m2", 202 /* xt_iclass_rsr.m2 */,
15892     0,
15893     Opcode_rsr_m2_encode_fns, 0, 0 },
15894   { "wsr.m2", 203 /* xt_iclass_wsr.m2 */,
15895     0,
15896     Opcode_wsr_m2_encode_fns, 0, 0 },
15897   { "xsr.m2", 204 /* xt_iclass_xsr.m2 */,
15898     0,
15899     Opcode_xsr_m2_encode_fns, 0, 0 },
15900   { "rsr.m3", 205 /* xt_iclass_rsr.m3 */,
15901     0,
15902     Opcode_rsr_m3_encode_fns, 0, 0 },
15903   { "wsr.m3", 206 /* xt_iclass_wsr.m3 */,
15904     0,
15905     Opcode_wsr_m3_encode_fns, 0, 0 },
15906   { "xsr.m3", 207 /* xt_iclass_xsr.m3 */,
15907     0,
15908     Opcode_xsr_m3_encode_fns, 0, 0 },
15909   { "rsr.acclo", 208 /* xt_iclass_rsr.acclo */,
15910     0,
15911     Opcode_rsr_acclo_encode_fns, 0, 0 },
15912   { "wsr.acclo", 209 /* xt_iclass_wsr.acclo */,
15913     0,
15914     Opcode_wsr_acclo_encode_fns, 0, 0 },
15915   { "xsr.acclo", 210 /* xt_iclass_xsr.acclo */,
15916     0,
15917     Opcode_xsr_acclo_encode_fns, 0, 0 },
15918   { "rsr.acchi", 211 /* xt_iclass_rsr.acchi */,
15919     0,
15920     Opcode_rsr_acchi_encode_fns, 0, 0 },
15921   { "wsr.acchi", 212 /* xt_iclass_wsr.acchi */,
15922     0,
15923     Opcode_wsr_acchi_encode_fns, 0, 0 },
15924   { "xsr.acchi", 213 /* xt_iclass_xsr.acchi */,
15925     0,
15926     Opcode_xsr_acchi_encode_fns, 0, 0 },
15927   { "rfi", 214 /* xt_iclass_rfi */,
15928     XTENSA_OPCODE_IS_JUMP,
15929     Opcode_rfi_encode_fns, 0, 0 },
15930   { "waiti", 215 /* xt_iclass_wait */,
15931     0,
15932     Opcode_waiti_encode_fns, 0, 0 },
15933   { "rsr.interrupt", 216 /* xt_iclass_rsr.interrupt */,
15934     0,
15935     Opcode_rsr_interrupt_encode_fns, 0, 0 },
15936   { "wsr.intset", 217 /* xt_iclass_wsr.intset */,
15937     0,
15938     Opcode_wsr_intset_encode_fns, 0, 0 },
15939   { "wsr.intclear", 218 /* xt_iclass_wsr.intclear */,
15940     0,
15941     Opcode_wsr_intclear_encode_fns, 0, 0 },
15942   { "rsr.intenable", 219 /* xt_iclass_rsr.intenable */,
15943     0,
15944     Opcode_rsr_intenable_encode_fns, 0, 0 },
15945   { "wsr.intenable", 220 /* xt_iclass_wsr.intenable */,
15946     0,
15947     Opcode_wsr_intenable_encode_fns, 0, 0 },
15948   { "xsr.intenable", 221 /* xt_iclass_xsr.intenable */,
15949     0,
15950     Opcode_xsr_intenable_encode_fns, 0, 0 },
15951   { "break", 222 /* xt_iclass_break */,
15952     0,
15953     Opcode_break_encode_fns, 0, 0 },
15954   { "break.n", 223 /* xt_iclass_break.n */,
15955     0,
15956     Opcode_break_n_encode_fns, 0, 0 },
15957   { "rsr.dbreaka0", 224 /* xt_iclass_rsr.dbreaka0 */,
15958     0,
15959     Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
15960   { "wsr.dbreaka0", 225 /* xt_iclass_wsr.dbreaka0 */,
15961     0,
15962     Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
15963   { "xsr.dbreaka0", 226 /* xt_iclass_xsr.dbreaka0 */,
15964     0,
15965     Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
15966   { "rsr.dbreakc0", 227 /* xt_iclass_rsr.dbreakc0 */,
15967     0,
15968     Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
15969   { "wsr.dbreakc0", 228 /* xt_iclass_wsr.dbreakc0 */,
15970     0,
15971     Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
15972   { "xsr.dbreakc0", 229 /* xt_iclass_xsr.dbreakc0 */,
15973     0,
15974     Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
15975   { "rsr.dbreaka1", 230 /* xt_iclass_rsr.dbreaka1 */,
15976     0,
15977     Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
15978   { "wsr.dbreaka1", 231 /* xt_iclass_wsr.dbreaka1 */,
15979     0,
15980     Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
15981   { "xsr.dbreaka1", 232 /* xt_iclass_xsr.dbreaka1 */,
15982     0,
15983     Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
15984   { "rsr.dbreakc1", 233 /* xt_iclass_rsr.dbreakc1 */,
15985     0,
15986     Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
15987   { "wsr.dbreakc1", 234 /* xt_iclass_wsr.dbreakc1 */,
15988     0,
15989     Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
15990   { "xsr.dbreakc1", 235 /* xt_iclass_xsr.dbreakc1 */,
15991     0,
15992     Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
15993   { "rsr.ibreaka0", 236 /* xt_iclass_rsr.ibreaka0 */,
15994     0,
15995     Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
15996   { "wsr.ibreaka0", 237 /* xt_iclass_wsr.ibreaka0 */,
15997     0,
15998     Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
15999   { "xsr.ibreaka0", 238 /* xt_iclass_xsr.ibreaka0 */,
16000     0,
16001     Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
16002   { "rsr.ibreaka1", 239 /* xt_iclass_rsr.ibreaka1 */,
16003     0,
16004     Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
16005   { "wsr.ibreaka1", 240 /* xt_iclass_wsr.ibreaka1 */,
16006     0,
16007     Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
16008   { "xsr.ibreaka1", 241 /* xt_iclass_xsr.ibreaka1 */,
16009     0,
16010     Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
16011   { "rsr.ibreakenable", 242 /* xt_iclass_rsr.ibreakenable */,
16012     0,
16013     Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
16014   { "wsr.ibreakenable", 243 /* xt_iclass_wsr.ibreakenable */,
16015     0,
16016     Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
16017   { "xsr.ibreakenable", 244 /* xt_iclass_xsr.ibreakenable */,
16018     0,
16019     Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
16020   { "rsr.debugcause", 245 /* xt_iclass_rsr.debugcause */,
16021     0,
16022     Opcode_rsr_debugcause_encode_fns, 0, 0 },
16023   { "wsr.debugcause", 246 /* xt_iclass_wsr.debugcause */,
16024     0,
16025     Opcode_wsr_debugcause_encode_fns, 0, 0 },
16026   { "xsr.debugcause", 247 /* xt_iclass_xsr.debugcause */,
16027     0,
16028     Opcode_xsr_debugcause_encode_fns, 0, 0 },
16029   { "rsr.icount", 248 /* xt_iclass_rsr.icount */,
16030     0,
16031     Opcode_rsr_icount_encode_fns, 0, 0 },
16032   { "wsr.icount", 249 /* xt_iclass_wsr.icount */,
16033     0,
16034     Opcode_wsr_icount_encode_fns, 0, 0 },
16035   { "xsr.icount", 250 /* xt_iclass_xsr.icount */,
16036     0,
16037     Opcode_xsr_icount_encode_fns, 0, 0 },
16038   { "rsr.icountlevel", 251 /* xt_iclass_rsr.icountlevel */,
16039     0,
16040     Opcode_rsr_icountlevel_encode_fns, 0, 0 },
16041   { "wsr.icountlevel", 252 /* xt_iclass_wsr.icountlevel */,
16042     0,
16043     Opcode_wsr_icountlevel_encode_fns, 0, 0 },
16044   { "xsr.icountlevel", 253 /* xt_iclass_xsr.icountlevel */,
16045     0,
16046     Opcode_xsr_icountlevel_encode_fns, 0, 0 },
16047   { "rsr.ddr", 254 /* xt_iclass_rsr.ddr */,
16048     0,
16049     Opcode_rsr_ddr_encode_fns, 0, 0 },
16050   { "wsr.ddr", 255 /* xt_iclass_wsr.ddr */,
16051     0,
16052     Opcode_wsr_ddr_encode_fns, 0, 0 },
16053   { "xsr.ddr", 256 /* xt_iclass_xsr.ddr */,
16054     0,
16055     Opcode_xsr_ddr_encode_fns, 0, 0 },
16056   { "rfdo", 257 /* xt_iclass_rfdo */,
16057     XTENSA_OPCODE_IS_JUMP,
16058     Opcode_rfdo_encode_fns, 0, 0 },
16059   { "rfdd", 258 /* xt_iclass_rfdd */,
16060     XTENSA_OPCODE_IS_JUMP,
16061     Opcode_rfdd_encode_fns, 0, 0 },
16062   { "wsr.mmid", 259 /* xt_iclass_wsr.mmid */,
16063     0,
16064     Opcode_wsr_mmid_encode_fns, 0, 0 },
16065   { "andb", 260 /* xt_iclass_bbool1 */,
16066     0,
16067     Opcode_andb_encode_fns, 0, 0 },
16068   { "andbc", 260 /* xt_iclass_bbool1 */,
16069     0,
16070     Opcode_andbc_encode_fns, 0, 0 },
16071   { "orb", 260 /* xt_iclass_bbool1 */,
16072     0,
16073     Opcode_orb_encode_fns, 0, 0 },
16074   { "orbc", 260 /* xt_iclass_bbool1 */,
16075     0,
16076     Opcode_orbc_encode_fns, 0, 0 },
16077   { "xorb", 260 /* xt_iclass_bbool1 */,
16078     0,
16079     Opcode_xorb_encode_fns, 0, 0 },
16080   { "any4", 261 /* xt_iclass_bbool4 */,
16081     0,
16082     Opcode_any4_encode_fns, 0, 0 },
16083   { "all4", 261 /* xt_iclass_bbool4 */,
16084     0,
16085     Opcode_all4_encode_fns, 0, 0 },
16086   { "any8", 262 /* xt_iclass_bbool8 */,
16087     0,
16088     Opcode_any8_encode_fns, 0, 0 },
16089   { "all8", 262 /* xt_iclass_bbool8 */,
16090     0,
16091     Opcode_all8_encode_fns, 0, 0 },
16092   { "bf", 263 /* xt_iclass_bbranch */,
16093     XTENSA_OPCODE_IS_BRANCH,
16094     Opcode_bf_encode_fns, 0, 0 },
16095   { "bt", 263 /* xt_iclass_bbranch */,
16096     XTENSA_OPCODE_IS_BRANCH,
16097     Opcode_bt_encode_fns, 0, 0 },
16098   { "movf", 264 /* xt_iclass_bmove */,
16099     0,
16100     Opcode_movf_encode_fns, 0, 0 },
16101   { "movt", 264 /* xt_iclass_bmove */,
16102     0,
16103     Opcode_movt_encode_fns, 0, 0 },
16104   { "rsr.br", 265 /* xt_iclass_RSR.BR */,
16105     0,
16106     Opcode_rsr_br_encode_fns, 0, 0 },
16107   { "wsr.br", 266 /* xt_iclass_WSR.BR */,
16108     0,
16109     Opcode_wsr_br_encode_fns, 0, 0 },
16110   { "xsr.br", 267 /* xt_iclass_XSR.BR */,
16111     0,
16112     Opcode_xsr_br_encode_fns, 0, 0 },
16113   { "rsr.ccount", 268 /* xt_iclass_rsr.ccount */,
16114     0,
16115     Opcode_rsr_ccount_encode_fns, 0, 0 },
16116   { "wsr.ccount", 269 /* xt_iclass_wsr.ccount */,
16117     0,
16118     Opcode_wsr_ccount_encode_fns, 0, 0 },
16119   { "xsr.ccount", 270 /* xt_iclass_xsr.ccount */,
16120     0,
16121     Opcode_xsr_ccount_encode_fns, 0, 0 },
16122   { "rsr.ccompare0", 271 /* xt_iclass_rsr.ccompare0 */,
16123     0,
16124     Opcode_rsr_ccompare0_encode_fns, 0, 0 },
16125   { "wsr.ccompare0", 272 /* xt_iclass_wsr.ccompare0 */,
16126     0,
16127     Opcode_wsr_ccompare0_encode_fns, 0, 0 },
16128   { "xsr.ccompare0", 273 /* xt_iclass_xsr.ccompare0 */,
16129     0,
16130     Opcode_xsr_ccompare0_encode_fns, 0, 0 },
16131   { "rsr.ccompare1", 274 /* xt_iclass_rsr.ccompare1 */,
16132     0,
16133     Opcode_rsr_ccompare1_encode_fns, 0, 0 },
16134   { "wsr.ccompare1", 275 /* xt_iclass_wsr.ccompare1 */,
16135     0,
16136     Opcode_wsr_ccompare1_encode_fns, 0, 0 },
16137   { "xsr.ccompare1", 276 /* xt_iclass_xsr.ccompare1 */,
16138     0,
16139     Opcode_xsr_ccompare1_encode_fns, 0, 0 },
16140   { "rsr.ccompare2", 277 /* xt_iclass_rsr.ccompare2 */,
16141     0,
16142     Opcode_rsr_ccompare2_encode_fns, 0, 0 },
16143   { "wsr.ccompare2", 278 /* xt_iclass_wsr.ccompare2 */,
16144     0,
16145     Opcode_wsr_ccompare2_encode_fns, 0, 0 },
16146   { "xsr.ccompare2", 279 /* xt_iclass_xsr.ccompare2 */,
16147     0,
16148     Opcode_xsr_ccompare2_encode_fns, 0, 0 },
16149   { "ipf", 280 /* xt_iclass_icache */,
16150     0,
16151     Opcode_ipf_encode_fns, 0, 0 },
16152   { "ihi", 280 /* xt_iclass_icache */,
16153     0,
16154     Opcode_ihi_encode_fns, 0, 0 },
16155   { "ipfl", 281 /* xt_iclass_icache_lock */,
16156     0,
16157     Opcode_ipfl_encode_fns, 0, 0 },
16158   { "ihu", 281 /* xt_iclass_icache_lock */,
16159     0,
16160     Opcode_ihu_encode_fns, 0, 0 },
16161   { "iiu", 281 /* xt_iclass_icache_lock */,
16162     0,
16163     Opcode_iiu_encode_fns, 0, 0 },
16164   { "iii", 282 /* xt_iclass_icache_inv */,
16165     0,
16166     Opcode_iii_encode_fns, 0, 0 },
16167   { "lict", 283 /* xt_iclass_licx */,
16168     0,
16169     Opcode_lict_encode_fns, 0, 0 },
16170   { "licw", 283 /* xt_iclass_licx */,
16171     0,
16172     Opcode_licw_encode_fns, 0, 0 },
16173   { "sict", 284 /* xt_iclass_sicx */,
16174     0,
16175     Opcode_sict_encode_fns, 0, 0 },
16176   { "sicw", 284 /* xt_iclass_sicx */,
16177     0,
16178     Opcode_sicw_encode_fns, 0, 0 },
16179   { "dhwb", 285 /* xt_iclass_dcache */,
16180     0,
16181     Opcode_dhwb_encode_fns, 0, 0 },
16182   { "dhwbi", 285 /* xt_iclass_dcache */,
16183     0,
16184     Opcode_dhwbi_encode_fns, 0, 0 },
16185   { "diwb", 286 /* xt_iclass_dcache_ind */,
16186     0,
16187     Opcode_diwb_encode_fns, 0, 0 },
16188   { "diwbi", 286 /* xt_iclass_dcache_ind */,
16189     0,
16190     Opcode_diwbi_encode_fns, 0, 0 },
16191   { "dhi", 287 /* xt_iclass_dcache_inv */,
16192     0,
16193     Opcode_dhi_encode_fns, 0, 0 },
16194   { "dii", 287 /* xt_iclass_dcache_inv */,
16195     0,
16196     Opcode_dii_encode_fns, 0, 0 },
16197   { "dpfr", 288 /* xt_iclass_dpf */,
16198     0,
16199     Opcode_dpfr_encode_fns, 0, 0 },
16200   { "dpfw", 288 /* xt_iclass_dpf */,
16201     0,
16202     Opcode_dpfw_encode_fns, 0, 0 },
16203   { "dpfro", 288 /* xt_iclass_dpf */,
16204     0,
16205     Opcode_dpfro_encode_fns, 0, 0 },
16206   { "dpfwo", 288 /* xt_iclass_dpf */,
16207     0,
16208     Opcode_dpfwo_encode_fns, 0, 0 },
16209   { "dpfl", 289 /* xt_iclass_dcache_lock */,
16210     0,
16211     Opcode_dpfl_encode_fns, 0, 0 },
16212   { "dhu", 289 /* xt_iclass_dcache_lock */,
16213     0,
16214     Opcode_dhu_encode_fns, 0, 0 },
16215   { "diu", 289 /* xt_iclass_dcache_lock */,
16216     0,
16217     Opcode_diu_encode_fns, 0, 0 },
16218   { "sdct", 290 /* xt_iclass_sdct */,
16219     0,
16220     Opcode_sdct_encode_fns, 0, 0 },
16221   { "ldct", 291 /* xt_iclass_ldct */,
16222     0,
16223     Opcode_ldct_encode_fns, 0, 0 },
16224   { "wsr.ptevaddr", 292 /* xt_iclass_wsr.ptevaddr */,
16225     0,
16226     Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
16227   { "rsr.ptevaddr", 293 /* xt_iclass_rsr.ptevaddr */,
16228     0,
16229     Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
16230   { "xsr.ptevaddr", 294 /* xt_iclass_xsr.ptevaddr */,
16231     0,
16232     Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
16233   { "rsr.rasid", 295 /* xt_iclass_rsr.rasid */,
16234     0,
16235     Opcode_rsr_rasid_encode_fns, 0, 0 },
16236   { "wsr.rasid", 296 /* xt_iclass_wsr.rasid */,
16237     0,
16238     Opcode_wsr_rasid_encode_fns, 0, 0 },
16239   { "xsr.rasid", 297 /* xt_iclass_xsr.rasid */,
16240     0,
16241     Opcode_xsr_rasid_encode_fns, 0, 0 },
16242   { "rsr.itlbcfg", 298 /* xt_iclass_rsr.itlbcfg */,
16243     0,
16244     Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
16245   { "wsr.itlbcfg", 299 /* xt_iclass_wsr.itlbcfg */,
16246     0,
16247     Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
16248   { "xsr.itlbcfg", 300 /* xt_iclass_xsr.itlbcfg */,
16249     0,
16250     Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
16251   { "rsr.dtlbcfg", 301 /* xt_iclass_rsr.dtlbcfg */,
16252     0,
16253     Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
16254   { "wsr.dtlbcfg", 302 /* xt_iclass_wsr.dtlbcfg */,
16255     0,
16256     Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
16257   { "xsr.dtlbcfg", 303 /* xt_iclass_xsr.dtlbcfg */,
16258     0,
16259     Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
16260   { "idtlb", 304 /* xt_iclass_idtlb */,
16261     0,
16262     Opcode_idtlb_encode_fns, 0, 0 },
16263   { "pdtlb", 305 /* xt_iclass_rdtlb */,
16264     0,
16265     Opcode_pdtlb_encode_fns, 0, 0 },
16266   { "rdtlb0", 305 /* xt_iclass_rdtlb */,
16267     0,
16268     Opcode_rdtlb0_encode_fns, 0, 0 },
16269   { "rdtlb1", 305 /* xt_iclass_rdtlb */,
16270     0,
16271     Opcode_rdtlb1_encode_fns, 0, 0 },
16272   { "wdtlb", 306 /* xt_iclass_wdtlb */,
16273     0,
16274     Opcode_wdtlb_encode_fns, 0, 0 },
16275   { "iitlb", 307 /* xt_iclass_iitlb */,
16276     0,
16277     Opcode_iitlb_encode_fns, 0, 0 },
16278   { "pitlb", 308 /* xt_iclass_ritlb */,
16279     0,
16280     Opcode_pitlb_encode_fns, 0, 0 },
16281   { "ritlb0", 308 /* xt_iclass_ritlb */,
16282     0,
16283     Opcode_ritlb0_encode_fns, 0, 0 },
16284   { "ritlb1", 308 /* xt_iclass_ritlb */,
16285     0,
16286     Opcode_ritlb1_encode_fns, 0, 0 },
16287   { "witlb", 309 /* xt_iclass_witlb */,
16288     0,
16289     Opcode_witlb_encode_fns, 0, 0 },
16290   { "ldpte", 310 /* xt_iclass_ldpte */,
16291     0,
16292     Opcode_ldpte_encode_fns, 0, 0 },
16293   { "hwwitlba", 311 /* xt_iclass_hwwitlba */,
16294     XTENSA_OPCODE_IS_BRANCH,
16295     Opcode_hwwitlba_encode_fns, 0, 0 },
16296   { "hwwdtlba", 312 /* xt_iclass_hwwdtlba */,
16297     0,
16298     Opcode_hwwdtlba_encode_fns, 0, 0 },
16299   { "rsr.cpenable", 313 /* xt_iclass_rsr.cpenable */,
16300     0,
16301     Opcode_rsr_cpenable_encode_fns, 0, 0 },
16302   { "wsr.cpenable", 314 /* xt_iclass_wsr.cpenable */,
16303     0,
16304     Opcode_wsr_cpenable_encode_fns, 0, 0 },
16305   { "xsr.cpenable", 315 /* xt_iclass_xsr.cpenable */,
16306     0,
16307     Opcode_xsr_cpenable_encode_fns, 0, 0 },
16308   { "clamps", 316 /* xt_iclass_clamp */,
16309     0,
16310     Opcode_clamps_encode_fns, 0, 0 },
16311   { "min", 317 /* xt_iclass_minmax */,
16312     0,
16313     Opcode_min_encode_fns, 0, 0 },
16314   { "max", 317 /* xt_iclass_minmax */,
16315     0,
16316     Opcode_max_encode_fns, 0, 0 },
16317   { "minu", 317 /* xt_iclass_minmax */,
16318     0,
16319     Opcode_minu_encode_fns, 0, 0 },
16320   { "maxu", 317 /* xt_iclass_minmax */,
16321     0,
16322     Opcode_maxu_encode_fns, 0, 0 },
16323   { "nsa", 318 /* xt_iclass_nsa */,
16324     0,
16325     Opcode_nsa_encode_fns, 0, 0 },
16326   { "nsau", 318 /* xt_iclass_nsa */,
16327     0,
16328     Opcode_nsau_encode_fns, 0, 0 },
16329   { "sext", 319 /* xt_iclass_sx */,
16330     0,
16331     Opcode_sext_encode_fns, 0, 0 },
16332   { "l32ai", 320 /* xt_iclass_l32ai */,
16333     0,
16334     Opcode_l32ai_encode_fns, 0, 0 },
16335   { "s32ri", 321 /* xt_iclass_s32ri */,
16336     0,
16337     Opcode_s32ri_encode_fns, 0, 0 },
16338   { "s32c1i", 322 /* xt_iclass_s32c1i */,
16339     0,
16340     Opcode_s32c1i_encode_fns, 0, 0 },
16341   { "rsr.scompare1", 323 /* xt_iclass_rsr.scompare1 */,
16342     0,
16343     Opcode_rsr_scompare1_encode_fns, 0, 0 },
16344   { "wsr.scompare1", 324 /* xt_iclass_wsr.scompare1 */,
16345     0,
16346     Opcode_wsr_scompare1_encode_fns, 0, 0 },
16347   { "xsr.scompare1", 325 /* xt_iclass_xsr.scompare1 */,
16348     0,
16349     Opcode_xsr_scompare1_encode_fns, 0, 0 },
16350   { "quou", 326 /* xt_iclass_div */,
16351     0,
16352     Opcode_quou_encode_fns, 0, 0 },
16353   { "quos", 326 /* xt_iclass_div */,
16354     0,
16355     Opcode_quos_encode_fns, 0, 0 },
16356   { "remu", 326 /* xt_iclass_div */,
16357     0,
16358     Opcode_remu_encode_fns, 0, 0 },
16359   { "rems", 326 /* xt_iclass_div */,
16360     0,
16361     Opcode_rems_encode_fns, 0, 0 },
16362   { "mull", 327 /* xt_mul32 */,
16363     0,
16364     Opcode_mull_encode_fns, 0, 0 },
16365   { "muluh", 327 /* xt_mul32 */,
16366     0,
16367     Opcode_muluh_encode_fns, 0, 0 },
16368   { "mulsh", 327 /* xt_mul32 */,
16369     0,
16370     Opcode_mulsh_encode_fns, 0, 0 },
16371   { "rur.fcr", 328 /* rur_fcr */,
16372     0,
16373     Opcode_rur_fcr_encode_fns, 0, 0 },
16374   { "wur.fcr", 329 /* wur_fcr */,
16375     0,
16376     Opcode_wur_fcr_encode_fns, 0, 0 },
16377   { "rur.fsr", 330 /* rur_fsr */,
16378     0,
16379     Opcode_rur_fsr_encode_fns, 0, 0 },
16380   { "wur.fsr", 331 /* wur_fsr */,
16381     0,
16382     Opcode_wur_fsr_encode_fns, 0, 0 },
16383   { "add.s", 332 /* fp */,
16384     0,
16385     Opcode_add_s_encode_fns, 0, 0 },
16386   { "sub.s", 332 /* fp */,
16387     0,
16388     Opcode_sub_s_encode_fns, 0, 0 },
16389   { "mul.s", 332 /* fp */,
16390     0,
16391     Opcode_mul_s_encode_fns, 0, 0 },
16392   { "madd.s", 333 /* fp_mac */,
16393     0,
16394     Opcode_madd_s_encode_fns, 0, 0 },
16395   { "msub.s", 333 /* fp_mac */,
16396     0,
16397     Opcode_msub_s_encode_fns, 0, 0 },
16398   { "movf.s", 334 /* fp_cmov */,
16399     0,
16400     Opcode_movf_s_encode_fns, 0, 0 },
16401   { "movt.s", 334 /* fp_cmov */,
16402     0,
16403     Opcode_movt_s_encode_fns, 0, 0 },
16404   { "moveqz.s", 335 /* fp_mov */,
16405     0,
16406     Opcode_moveqz_s_encode_fns, 0, 0 },
16407   { "movnez.s", 335 /* fp_mov */,
16408     0,
16409     Opcode_movnez_s_encode_fns, 0, 0 },
16410   { "movltz.s", 335 /* fp_mov */,
16411     0,
16412     Opcode_movltz_s_encode_fns, 0, 0 },
16413   { "movgez.s", 335 /* fp_mov */,
16414     0,
16415     Opcode_movgez_s_encode_fns, 0, 0 },
16416   { "abs.s", 336 /* fp_mov2 */,
16417     0,
16418     Opcode_abs_s_encode_fns, 0, 0 },
16419   { "mov.s", 336 /* fp_mov2 */,
16420     0,
16421     Opcode_mov_s_encode_fns, 0, 0 },
16422   { "neg.s", 336 /* fp_mov2 */,
16423     0,
16424     Opcode_neg_s_encode_fns, 0, 0 },
16425   { "un.s", 337 /* fp_cmp */,
16426     0,
16427     Opcode_un_s_encode_fns, 0, 0 },
16428   { "oeq.s", 337 /* fp_cmp */,
16429     0,
16430     Opcode_oeq_s_encode_fns, 0, 0 },
16431   { "ueq.s", 337 /* fp_cmp */,
16432     0,
16433     Opcode_ueq_s_encode_fns, 0, 0 },
16434   { "olt.s", 337 /* fp_cmp */,
16435     0,
16436     Opcode_olt_s_encode_fns, 0, 0 },
16437   { "ult.s", 337 /* fp_cmp */,
16438     0,
16439     Opcode_ult_s_encode_fns, 0, 0 },
16440   { "ole.s", 337 /* fp_cmp */,
16441     0,
16442     Opcode_ole_s_encode_fns, 0, 0 },
16443   { "ule.s", 337 /* fp_cmp */,
16444     0,
16445     Opcode_ule_s_encode_fns, 0, 0 },
16446   { "float.s", 338 /* fp_float */,
16447     0,
16448     Opcode_float_s_encode_fns, 0, 0 },
16449   { "ufloat.s", 338 /* fp_float */,
16450     0,
16451     Opcode_ufloat_s_encode_fns, 0, 0 },
16452   { "round.s", 339 /* fp_int */,
16453     0,
16454     Opcode_round_s_encode_fns, 0, 0 },
16455   { "ceil.s", 339 /* fp_int */,
16456     0,
16457     Opcode_ceil_s_encode_fns, 0, 0 },
16458   { "floor.s", 339 /* fp_int */,
16459     0,
16460     Opcode_floor_s_encode_fns, 0, 0 },
16461   { "trunc.s", 339 /* fp_int */,
16462     0,
16463     Opcode_trunc_s_encode_fns, 0, 0 },
16464   { "utrunc.s", 339 /* fp_int */,
16465     0,
16466     Opcode_utrunc_s_encode_fns, 0, 0 },
16467   { "rfr", 340 /* fp_rfr */,
16468     0,
16469     Opcode_rfr_encode_fns, 0, 0 },
16470   { "wfr", 341 /* fp_wfr */,
16471     0,
16472     Opcode_wfr_encode_fns, 0, 0 },
16473   { "lsi", 342 /* fp_lsi */,
16474     0,
16475     Opcode_lsi_encode_fns, 0, 0 },
16476   { "lsiu", 343 /* fp_lsiu */,
16477     0,
16478     Opcode_lsiu_encode_fns, 0, 0 },
16479   { "lsx", 344 /* fp_lsx */,
16480     0,
16481     Opcode_lsx_encode_fns, 0, 0 },
16482   { "lsxu", 345 /* fp_lsxu */,
16483     0,
16484     Opcode_lsxu_encode_fns, 0, 0 },
16485   { "ssi", 346 /* fp_ssi */,
16486     0,
16487     Opcode_ssi_encode_fns, 0, 0 },
16488   { "ssiu", 347 /* fp_ssiu */,
16489     0,
16490     Opcode_ssiu_encode_fns, 0, 0 },
16491   { "ssx", 348 /* fp_ssx */,
16492     0,
16493     Opcode_ssx_encode_fns, 0, 0 },
16494   { "ssxu", 349 /* fp_ssxu */,
16495     0,
16496     Opcode_ssxu_encode_fns, 0, 0 },
16497   { "beqz.w18", 350 /* xt_iclass_wb18_0 */,
16498     XTENSA_OPCODE_IS_BRANCH,
16499     Opcode_beqz_w18_encode_fns, 0, 0 },
16500   { "bnez.w18", 350 /* xt_iclass_wb18_0 */,
16501     XTENSA_OPCODE_IS_BRANCH,
16502     Opcode_bnez_w18_encode_fns, 0, 0 },
16503   { "bgez.w18", 350 /* xt_iclass_wb18_0 */,
16504     XTENSA_OPCODE_IS_BRANCH,
16505     Opcode_bgez_w18_encode_fns, 0, 0 },
16506   { "bltz.w18", 350 /* xt_iclass_wb18_0 */,
16507     XTENSA_OPCODE_IS_BRANCH,
16508     Opcode_bltz_w18_encode_fns, 0, 0 },
16509   { "beqi.w18", 351 /* xt_iclass_wb18_1 */,
16510     XTENSA_OPCODE_IS_BRANCH,
16511     Opcode_beqi_w18_encode_fns, 0, 0 },
16512   { "bnei.w18", 351 /* xt_iclass_wb18_1 */,
16513     XTENSA_OPCODE_IS_BRANCH,
16514     Opcode_bnei_w18_encode_fns, 0, 0 },
16515   { "bgei.w18", 351 /* xt_iclass_wb18_1 */,
16516     XTENSA_OPCODE_IS_BRANCH,
16517     Opcode_bgei_w18_encode_fns, 0, 0 },
16518   { "blti.w18", 351 /* xt_iclass_wb18_1 */,
16519     XTENSA_OPCODE_IS_BRANCH,
16520     Opcode_blti_w18_encode_fns, 0, 0 },
16521   { "bgeui.w18", 352 /* xt_iclass_wb18_2 */,
16522     XTENSA_OPCODE_IS_BRANCH,
16523     Opcode_bgeui_w18_encode_fns, 0, 0 },
16524   { "bltui.w18", 352 /* xt_iclass_wb18_2 */,
16525     XTENSA_OPCODE_IS_BRANCH,
16526     Opcode_bltui_w18_encode_fns, 0, 0 },
16527   { "bbci.w18", 353 /* xt_iclass_wb18_3 */,
16528     XTENSA_OPCODE_IS_BRANCH,
16529     Opcode_bbci_w18_encode_fns, 0, 0 },
16530   { "bbsi.w18", 353 /* xt_iclass_wb18_3 */,
16531     XTENSA_OPCODE_IS_BRANCH,
16532     Opcode_bbsi_w18_encode_fns, 0, 0 },
16533   { "beq.w18", 354 /* xt_iclass_wb18_4 */,
16534     XTENSA_OPCODE_IS_BRANCH,
16535     Opcode_beq_w18_encode_fns, 0, 0 },
16536   { "bne.w18", 354 /* xt_iclass_wb18_4 */,
16537     XTENSA_OPCODE_IS_BRANCH,
16538     Opcode_bne_w18_encode_fns, 0, 0 },
16539   { "bge.w18", 354 /* xt_iclass_wb18_4 */,
16540     XTENSA_OPCODE_IS_BRANCH,
16541     Opcode_bge_w18_encode_fns, 0, 0 },
16542   { "blt.w18", 354 /* xt_iclass_wb18_4 */,
16543     XTENSA_OPCODE_IS_BRANCH,
16544     Opcode_blt_w18_encode_fns, 0, 0 },
16545   { "bgeu.w18", 354 /* xt_iclass_wb18_4 */,
16546     XTENSA_OPCODE_IS_BRANCH,
16547     Opcode_bgeu_w18_encode_fns, 0, 0 },
16548   { "bltu.w18", 354 /* xt_iclass_wb18_4 */,
16549     XTENSA_OPCODE_IS_BRANCH,
16550     Opcode_bltu_w18_encode_fns, 0, 0 },
16551   { "bany.w18", 354 /* xt_iclass_wb18_4 */,
16552     XTENSA_OPCODE_IS_BRANCH,
16553     Opcode_bany_w18_encode_fns, 0, 0 },
16554   { "bnone.w18", 354 /* xt_iclass_wb18_4 */,
16555     XTENSA_OPCODE_IS_BRANCH,
16556     Opcode_bnone_w18_encode_fns, 0, 0 },
16557   { "ball.w18", 354 /* xt_iclass_wb18_4 */,
16558     XTENSA_OPCODE_IS_BRANCH,
16559     Opcode_ball_w18_encode_fns, 0, 0 },
16560   { "bnall.w18", 354 /* xt_iclass_wb18_4 */,
16561     XTENSA_OPCODE_IS_BRANCH,
16562     Opcode_bnall_w18_encode_fns, 0, 0 },
16563   { "bbc.w18", 354 /* xt_iclass_wb18_4 */,
16564     XTENSA_OPCODE_IS_BRANCH,
16565     Opcode_bbc_w18_encode_fns, 0, 0 },
16566   { "bbs.w18", 354 /* xt_iclass_wb18_4 */,
16567     XTENSA_OPCODE_IS_BRANCH,
16568     Opcode_bbs_w18_encode_fns, 0, 0 }
16569 };
16570
16571 \f
16572 /* Slot-specific opcode decode functions.  */
16573
16574 static int
16575 Slot_inst_decode (const xtensa_insnbuf insn)
16576 {
16577   switch (Field_op0_Slot_inst_get (insn))
16578     {
16579     case 0:
16580       switch (Field_op1_Slot_inst_get (insn))
16581         {
16582         case 0:
16583           switch (Field_op2_Slot_inst_get (insn))
16584             {
16585             case 0:
16586               switch (Field_r_Slot_inst_get (insn))
16587                 {
16588                 case 0:
16589                   switch (Field_m_Slot_inst_get (insn))
16590                     {
16591                     case 0:
16592                       if (Field_s_Slot_inst_get (insn) == 0 &&
16593                           Field_n_Slot_inst_get (insn) == 0)
16594                         return 79; /* ill */
16595                       break;
16596                     case 2:
16597                       switch (Field_n_Slot_inst_get (insn))
16598                         {
16599                         case 0:
16600                           return 98; /* ret */
16601                         case 1:
16602                           return 14; /* retw */
16603                         case 2:
16604                           return 81; /* jx */
16605                         }
16606                       break;
16607                     case 3:
16608                       switch (Field_n_Slot_inst_get (insn))
16609                         {
16610                         case 0:
16611                           return 77; /* callx0 */
16612                         case 1:
16613                           return 10; /* callx4 */
16614                         case 2:
16615                           return 9; /* callx8 */
16616                         case 3:
16617                           return 8; /* callx12 */
16618                         }
16619                       break;
16620                     }
16621                   break;
16622                 case 1:
16623                   return 12; /* movsp */
16624                 case 2:
16625                   if (Field_s_Slot_inst_get (insn) == 0)
16626                     {
16627                       switch (Field_t_Slot_inst_get (insn))
16628                         {
16629                         case 0:
16630                           return 116; /* isync */
16631                         case 1:
16632                           return 117; /* rsync */
16633                         case 2:
16634                           return 118; /* esync */
16635                         case 3:
16636                           return 119; /* dsync */
16637                         case 8:
16638                           return 0; /* excw */
16639                         case 12:
16640                           return 114; /* memw */
16641                         case 13:
16642                           return 115; /* extw */
16643                         case 15:
16644                           return 97; /* nop */
16645                         }
16646                     }
16647                   break;
16648                 case 3:
16649                   switch (Field_t_Slot_inst_get (insn))
16650                     {
16651                     case 0:
16652                       switch (Field_s_Slot_inst_get (insn))
16653                         {
16654                         case 0:
16655                           return 1; /* rfe */
16656                         case 2:
16657                           return 2; /* rfde */
16658                         case 4:
16659                           return 16; /* rfwo */
16660                         case 5:
16661                           return 17; /* rfwu */
16662                         }
16663                       break;
16664                     case 1:
16665                       return 316; /* rfi */
16666                     }
16667                   break;
16668                 case 4:
16669                   return 324; /* break */
16670                 case 5:
16671                   switch (Field_s_Slot_inst_get (insn))
16672                     {
16673                     case 0:
16674                       if (Field_t_Slot_inst_get (insn) == 0)
16675                         return 3; /* syscall */
16676                       break;
16677                     case 1:
16678                       if (Field_t_Slot_inst_get (insn) == 0)
16679                         return 4; /* simcall */
16680                       break;
16681                     }
16682                   break;
16683                 case 6:
16684                   return 120; /* rsil */
16685                 case 7:
16686                   if (Field_t_Slot_inst_get (insn) == 0)
16687                     return 317; /* waiti */
16688                   break;
16689                 case 8:
16690                   return 367; /* any4 */
16691                 case 9:
16692                   return 368; /* all4 */
16693                 case 10:
16694                   return 369; /* any8 */
16695                 case 11:
16696                   return 370; /* all8 */
16697                 }
16698               break;
16699             case 1:
16700               return 49; /* and */
16701             case 2:
16702               return 50; /* or */
16703             case 3:
16704               return 51; /* xor */
16705             case 4:
16706               switch (Field_r_Slot_inst_get (insn))
16707                 {
16708                 case 0:
16709                   if (Field_t_Slot_inst_get (insn) == 0)
16710                     return 102; /* ssr */
16711                   break;
16712                 case 1:
16713                   if (Field_t_Slot_inst_get (insn) == 0)
16714                     return 103; /* ssl */
16715                   break;
16716                 case 2:
16717                   if (Field_t_Slot_inst_get (insn) == 0)
16718                     return 104; /* ssa8l */
16719                   break;
16720                 case 3:
16721                   if (Field_t_Slot_inst_get (insn) == 0)
16722                     return 105; /* ssa8b */
16723                   break;
16724                 case 4:
16725                   if (Field_thi3_Slot_inst_get (insn) == 0)
16726                     return 106; /* ssai */
16727                   break;
16728                 case 8:
16729                   if (Field_s_Slot_inst_get (insn) == 0)
16730                     return 13; /* rotw */
16731                   break;
16732                 case 14:
16733                   return 448; /* nsa */
16734                 case 15:
16735                   return 449; /* nsau */
16736                 }
16737               break;
16738             case 5:
16739               switch (Field_r_Slot_inst_get (insn))
16740                 {
16741                 case 1:
16742                   return 438; /* hwwitlba */
16743                 case 3:
16744                   return 434; /* ritlb0 */
16745                 case 4:
16746                   if (Field_t_Slot_inst_get (insn) == 0)
16747                     return 432; /* iitlb */
16748                   break;
16749                 case 5:
16750                   return 433; /* pitlb */
16751                 case 6:
16752                   return 436; /* witlb */
16753                 case 7:
16754                   return 435; /* ritlb1 */
16755                 case 9:
16756                   return 439; /* hwwdtlba */
16757                 case 11:
16758                   return 429; /* rdtlb0 */
16759                 case 12:
16760                   if (Field_t_Slot_inst_get (insn) == 0)
16761                     return 427; /* idtlb */
16762                   break;
16763                 case 13:
16764                   return 428; /* pdtlb */
16765                 case 14:
16766                   return 431; /* wdtlb */
16767                 case 15:
16768                   return 430; /* rdtlb1 */
16769                 }
16770               break;
16771             case 6:
16772               switch (Field_s_Slot_inst_get (insn))
16773                 {
16774                 case 0:
16775                   return 95; /* neg */
16776                 case 1:
16777                   return 96; /* abs */
16778                 }
16779               break;
16780             case 8:
16781               return 41; /* add */
16782             case 9:
16783               return 43; /* addx2 */
16784             case 10:
16785               return 44; /* addx4 */
16786             case 11:
16787               return 45; /* addx8 */
16788             case 12:
16789               return 42; /* sub */
16790             case 13:
16791               return 46; /* subx2 */
16792             case 14:
16793               return 47; /* subx4 */
16794             case 15:
16795               return 48; /* subx8 */
16796             }
16797           break;
16798         case 1:
16799           switch (Field_op2_Slot_inst_get (insn))
16800             {
16801             case 0:
16802             case 1:
16803               return 111; /* slli */
16804             case 2:
16805             case 3:
16806               return 112; /* srai */
16807             case 4:
16808               return 113; /* srli */
16809             case 6:
16810               switch (Field_sr_Slot_inst_get (insn))
16811                 {
16812                 case 0:
16813                   return 129; /* xsr.lbeg */
16814                 case 1:
16815                   return 123; /* xsr.lend */
16816                 case 2:
16817                   return 126; /* xsr.lcount */
16818                 case 3:
16819                   return 132; /* xsr.sar */
16820                 case 4:
16821                   return 377; /* xsr.br */
16822                 case 5:
16823                   return 135; /* xsr.litbase */
16824                 case 12:
16825                   return 456; /* xsr.scompare1 */
16826                 case 16:
16827                   return 312; /* xsr.acclo */
16828                 case 17:
16829                   return 315; /* xsr.acchi */
16830                 case 32:
16831                   return 300; /* xsr.m0 */
16832                 case 33:
16833                   return 303; /* xsr.m1 */
16834                 case 34:
16835                   return 306; /* xsr.m2 */
16836                 case 35:
16837                   return 309; /* xsr.m3 */
16838                 case 72:
16839                   return 22; /* xsr.windowbase */
16840                 case 73:
16841                   return 25; /* xsr.windowstart */
16842                 case 83:
16843                   return 417; /* xsr.ptevaddr */
16844                 case 90:
16845                   return 420; /* xsr.rasid */
16846                 case 91:
16847                   return 423; /* xsr.itlbcfg */
16848                 case 92:
16849                   return 426; /* xsr.dtlbcfg */
16850                 case 96:
16851                   return 346; /* xsr.ibreakenable */
16852                 case 104:
16853                   return 358; /* xsr.ddr */
16854                 case 128:
16855                   return 340; /* xsr.ibreaka0 */
16856                 case 129:
16857                   return 343; /* xsr.ibreaka1 */
16858                 case 144:
16859                   return 328; /* xsr.dbreaka0 */
16860                 case 145:
16861                   return 334; /* xsr.dbreaka1 */
16862                 case 160:
16863                   return 331; /* xsr.dbreakc0 */
16864                 case 161:
16865                   return 337; /* xsr.dbreakc1 */
16866                 case 177:
16867                   return 143; /* xsr.epc1 */
16868                 case 178:
16869                   return 149; /* xsr.epc2 */
16870                 case 179:
16871                   return 155; /* xsr.epc3 */
16872                 case 180:
16873                   return 161; /* xsr.epc4 */
16874                 case 181:
16875                   return 167; /* xsr.epc5 */
16876                 case 182:
16877                   return 173; /* xsr.epc6 */
16878                 case 183:
16879                   return 179; /* xsr.epc7 */
16880                 case 192:
16881                   return 206; /* xsr.depc */
16882                 case 194:
16883                   return 185; /* xsr.eps2 */
16884                 case 195:
16885                   return 188; /* xsr.eps3 */
16886                 case 196:
16887                   return 191; /* xsr.eps4 */
16888                 case 197:
16889                   return 194; /* xsr.eps5 */
16890                 case 198:
16891                   return 197; /* xsr.eps6 */
16892                 case 199:
16893                   return 200; /* xsr.eps7 */
16894                 case 209:
16895                   return 146; /* xsr.excsave1 */
16896                 case 210:
16897                   return 152; /* xsr.excsave2 */
16898                 case 211:
16899                   return 158; /* xsr.excsave3 */
16900                 case 212:
16901                   return 164; /* xsr.excsave4 */
16902                 case 213:
16903                   return 170; /* xsr.excsave5 */
16904                 case 214:
16905                   return 176; /* xsr.excsave6 */
16906                 case 215:
16907                   return 182; /* xsr.excsave7 */
16908                 case 224:
16909                   return 442; /* xsr.cpenable */
16910                 case 228:
16911                   return 323; /* xsr.intenable */
16912                 case 230:
16913                   return 140; /* xsr.ps */
16914                 case 231:
16915                   return 225; /* xsr.vecbase */
16916                 case 232:
16917                   return 209; /* xsr.exccause */
16918                 case 233:
16919                   return 349; /* xsr.debugcause */
16920                 case 234:
16921                   return 380; /* xsr.ccount */
16922                 case 236:
16923                   return 352; /* xsr.icount */
16924                 case 237:
16925                   return 355; /* xsr.icountlevel */
16926                 case 238:
16927                   return 203; /* xsr.excvaddr */
16928                 case 240:
16929                   return 383; /* xsr.ccompare0 */
16930                 case 241:
16931                   return 386; /* xsr.ccompare1 */
16932                 case 242:
16933                   return 389; /* xsr.ccompare2 */
16934                 case 244:
16935                   return 212; /* xsr.misc0 */
16936                 case 245:
16937                   return 215; /* xsr.misc1 */
16938                 case 246:
16939                   return 218; /* xsr.misc2 */
16940                 case 247:
16941                   return 221; /* xsr.misc3 */
16942                 }
16943               break;
16944             case 8:
16945               return 108; /* src */
16946             case 9:
16947               if (Field_s_Slot_inst_get (insn) == 0)
16948                 return 109; /* srl */
16949               break;
16950             case 10:
16951               if (Field_t_Slot_inst_get (insn) == 0)
16952                 return 107; /* sll */
16953               break;
16954             case 11:
16955               if (Field_s_Slot_inst_get (insn) == 0)
16956                 return 110; /* sra */
16957               break;
16958             case 12:
16959               return 296; /* mul16u */
16960             case 13:
16961               return 297; /* mul16s */
16962             case 15:
16963               switch (Field_r_Slot_inst_get (insn))
16964                 {
16965                 case 0:
16966                   return 396; /* lict */
16967                 case 1:
16968                   return 398; /* sict */
16969                 case 2:
16970                   return 397; /* licw */
16971                 case 3:
16972                   return 399; /* sicw */
16973                 case 8:
16974                   return 414; /* ldct */
16975                 case 9:
16976                   return 413; /* sdct */
16977                 case 14:
16978                   if (Field_t_Slot_inst_get (insn) == 0)
16979                     return 359; /* rfdo */
16980                   if (Field_t_Slot_inst_get (insn) == 1)
16981                     return 360; /* rfdd */
16982                   break;
16983                 case 15:
16984                   return 437; /* ldpte */
16985                 }
16986               break;
16987             }
16988           break;
16989         case 2:
16990           switch (Field_op2_Slot_inst_get (insn))
16991             {
16992             case 0:
16993               return 362; /* andb */
16994             case 1:
16995               return 363; /* andbc */
16996             case 2:
16997               return 364; /* orb */
16998             case 3:
16999               return 365; /* orbc */
17000             case 4:
17001               return 366; /* xorb */
17002             case 8:
17003               return 461; /* mull */
17004             case 10:
17005               return 462; /* muluh */
17006             case 11:
17007               return 463; /* mulsh */
17008             case 12:
17009               return 457; /* quou */
17010             case 13:
17011               return 458; /* quos */
17012             case 14:
17013               return 459; /* remu */
17014             case 15:
17015               return 460; /* rems */
17016             }
17017           break;
17018         case 3:
17019           switch (Field_op2_Slot_inst_get (insn))
17020             {
17021             case 0:
17022               switch (Field_sr_Slot_inst_get (insn))
17023                 {
17024                 case 0:
17025                   return 127; /* rsr.lbeg */
17026                 case 1:
17027                   return 121; /* rsr.lend */
17028                 case 2:
17029                   return 124; /* rsr.lcount */
17030                 case 3:
17031                   return 130; /* rsr.sar */
17032                 case 4:
17033                   return 375; /* rsr.br */
17034                 case 5:
17035                   return 133; /* rsr.litbase */
17036                 case 12:
17037                   return 454; /* rsr.scompare1 */
17038                 case 16:
17039                   return 310; /* rsr.acclo */
17040                 case 17:
17041                   return 313; /* rsr.acchi */
17042                 case 32:
17043                   return 298; /* rsr.m0 */
17044                 case 33:
17045                   return 301; /* rsr.m1 */
17046                 case 34:
17047                   return 304; /* rsr.m2 */
17048                 case 35:
17049                   return 307; /* rsr.m3 */
17050                 case 72:
17051                   return 20; /* rsr.windowbase */
17052                 case 73:
17053                   return 23; /* rsr.windowstart */
17054                 case 83:
17055                   return 416; /* rsr.ptevaddr */
17056                 case 90:
17057                   return 418; /* rsr.rasid */
17058                 case 91:
17059                   return 421; /* rsr.itlbcfg */
17060                 case 92:
17061                   return 424; /* rsr.dtlbcfg */
17062                 case 96:
17063                   return 344; /* rsr.ibreakenable */
17064                 case 104:
17065                   return 356; /* rsr.ddr */
17066                 case 128:
17067                   return 338; /* rsr.ibreaka0 */
17068                 case 129:
17069                   return 341; /* rsr.ibreaka1 */
17070                 case 144:
17071                   return 326; /* rsr.dbreaka0 */
17072                 case 145:
17073                   return 332; /* rsr.dbreaka1 */
17074                 case 160:
17075                   return 329; /* rsr.dbreakc0 */
17076                 case 161:
17077                   return 335; /* rsr.dbreakc1 */
17078                 case 176:
17079                   return 136; /* rsr.176 */
17080                 case 177:
17081                   return 141; /* rsr.epc1 */
17082                 case 178:
17083                   return 147; /* rsr.epc2 */
17084                 case 179:
17085                   return 153; /* rsr.epc3 */
17086                 case 180:
17087                   return 159; /* rsr.epc4 */
17088                 case 181:
17089                   return 165; /* rsr.epc5 */
17090                 case 182:
17091                   return 171; /* rsr.epc6 */
17092                 case 183:
17093                   return 177; /* rsr.epc7 */
17094                 case 192:
17095                   return 204; /* rsr.depc */
17096                 case 194:
17097                   return 183; /* rsr.eps2 */
17098                 case 195:
17099                   return 186; /* rsr.eps3 */
17100                 case 196:
17101                   return 189; /* rsr.eps4 */
17102                 case 197:
17103                   return 192; /* rsr.eps5 */
17104                 case 198:
17105                   return 195; /* rsr.eps6 */
17106                 case 199:
17107                   return 198; /* rsr.eps7 */
17108                 case 208:
17109                   return 137; /* rsr.208 */
17110                 case 209:
17111                   return 144; /* rsr.excsave1 */
17112                 case 210:
17113                   return 150; /* rsr.excsave2 */
17114                 case 211:
17115                   return 156; /* rsr.excsave3 */
17116                 case 212:
17117                   return 162; /* rsr.excsave4 */
17118                 case 213:
17119                   return 168; /* rsr.excsave5 */
17120                 case 214:
17121                   return 174; /* rsr.excsave6 */
17122                 case 215:
17123                   return 180; /* rsr.excsave7 */
17124                 case 224:
17125                   return 440; /* rsr.cpenable */
17126                 case 226:
17127                   return 318; /* rsr.interrupt */
17128                 case 228:
17129                   return 321; /* rsr.intenable */
17130                 case 230:
17131                   return 138; /* rsr.ps */
17132                 case 231:
17133                   return 223; /* rsr.vecbase */
17134                 case 232:
17135                   return 207; /* rsr.exccause */
17136                 case 233:
17137                   return 347; /* rsr.debugcause */
17138                 case 234:
17139                   return 378; /* rsr.ccount */
17140                 case 235:
17141                   return 222; /* rsr.prid */
17142                 case 236:
17143                   return 350; /* rsr.icount */
17144                 case 237:
17145                   return 353; /* rsr.icountlevel */
17146                 case 238:
17147                   return 201; /* rsr.excvaddr */
17148                 case 240:
17149                   return 381; /* rsr.ccompare0 */
17150                 case 241:
17151                   return 384; /* rsr.ccompare1 */
17152                 case 242:
17153                   return 387; /* rsr.ccompare2 */
17154                 case 244:
17155                   return 210; /* rsr.misc0 */
17156                 case 245:
17157                   return 213; /* rsr.misc1 */
17158                 case 246:
17159                   return 216; /* rsr.misc2 */
17160                 case 247:
17161                   return 219; /* rsr.misc3 */
17162                 }
17163               break;
17164             case 1:
17165               switch (Field_sr_Slot_inst_get (insn))
17166                 {
17167                 case 0:
17168                   return 128; /* wsr.lbeg */
17169                 case 1:
17170                   return 122; /* wsr.lend */
17171                 case 2:
17172                   return 125; /* wsr.lcount */
17173                 case 3:
17174                   return 131; /* wsr.sar */
17175                 case 4:
17176                   return 376; /* wsr.br */
17177                 case 5:
17178                   return 134; /* wsr.litbase */
17179                 case 12:
17180                   return 455; /* wsr.scompare1 */
17181                 case 16:
17182                   return 311; /* wsr.acclo */
17183                 case 17:
17184                   return 314; /* wsr.acchi */
17185                 case 32:
17186                   return 299; /* wsr.m0 */
17187                 case 33:
17188                   return 302; /* wsr.m1 */
17189                 case 34:
17190                   return 305; /* wsr.m2 */
17191                 case 35:
17192                   return 308; /* wsr.m3 */
17193                 case 72:
17194                   return 21; /* wsr.windowbase */
17195                 case 73:
17196                   return 24; /* wsr.windowstart */
17197                 case 83:
17198                   return 415; /* wsr.ptevaddr */
17199                 case 89:
17200                   return 361; /* wsr.mmid */
17201                 case 90:
17202                   return 419; /* wsr.rasid */
17203                 case 91:
17204                   return 422; /* wsr.itlbcfg */
17205                 case 92:
17206                   return 425; /* wsr.dtlbcfg */
17207                 case 96:
17208                   return 345; /* wsr.ibreakenable */
17209                 case 104:
17210                   return 357; /* wsr.ddr */
17211                 case 128:
17212                   return 339; /* wsr.ibreaka0 */
17213                 case 129:
17214                   return 342; /* wsr.ibreaka1 */
17215                 case 144:
17216                   return 327; /* wsr.dbreaka0 */
17217                 case 145:
17218                   return 333; /* wsr.dbreaka1 */
17219                 case 160:
17220                   return 330; /* wsr.dbreakc0 */
17221                 case 161:
17222                   return 336; /* wsr.dbreakc1 */
17223                 case 177:
17224                   return 142; /* wsr.epc1 */
17225                 case 178:
17226                   return 148; /* wsr.epc2 */
17227                 case 179:
17228                   return 154; /* wsr.epc3 */
17229                 case 180:
17230                   return 160; /* wsr.epc4 */
17231                 case 181:
17232                   return 166; /* wsr.epc5 */
17233                 case 182:
17234                   return 172; /* wsr.epc6 */
17235                 case 183:
17236                   return 178; /* wsr.epc7 */
17237                 case 192:
17238                   return 205; /* wsr.depc */
17239                 case 194:
17240                   return 184; /* wsr.eps2 */
17241                 case 195:
17242                   return 187; /* wsr.eps3 */
17243                 case 196:
17244                   return 190; /* wsr.eps4 */
17245                 case 197:
17246                   return 193; /* wsr.eps5 */
17247                 case 198:
17248                   return 196; /* wsr.eps6 */
17249                 case 199:
17250                   return 199; /* wsr.eps7 */
17251                 case 209:
17252                   return 145; /* wsr.excsave1 */
17253                 case 210:
17254                   return 151; /* wsr.excsave2 */
17255                 case 211:
17256                   return 157; /* wsr.excsave3 */
17257                 case 212:
17258                   return 163; /* wsr.excsave4 */
17259                 case 213:
17260                   return 169; /* wsr.excsave5 */
17261                 case 214:
17262                   return 175; /* wsr.excsave6 */
17263                 case 215:
17264                   return 181; /* wsr.excsave7 */
17265                 case 224:
17266                   return 441; /* wsr.cpenable */
17267                 case 226:
17268                   return 319; /* wsr.intset */
17269                 case 227:
17270                   return 320; /* wsr.intclear */
17271                 case 228:
17272                   return 322; /* wsr.intenable */
17273                 case 230:
17274                   return 139; /* wsr.ps */
17275                 case 231:
17276                   return 224; /* wsr.vecbase */
17277                 case 232:
17278                   return 208; /* wsr.exccause */
17279                 case 233:
17280                   return 348; /* wsr.debugcause */
17281                 case 234:
17282                   return 379; /* wsr.ccount */
17283                 case 236:
17284                   return 351; /* wsr.icount */
17285                 case 237:
17286                   return 354; /* wsr.icountlevel */
17287                 case 238:
17288                   return 202; /* wsr.excvaddr */
17289                 case 240:
17290                   return 382; /* wsr.ccompare0 */
17291                 case 241:
17292                   return 385; /* wsr.ccompare1 */
17293                 case 242:
17294                   return 388; /* wsr.ccompare2 */
17295                 case 244:
17296                   return 211; /* wsr.misc0 */
17297                 case 245:
17298                   return 214; /* wsr.misc1 */
17299                 case 246:
17300                   return 217; /* wsr.misc2 */
17301                 case 247:
17302                   return 220; /* wsr.misc3 */
17303                 }
17304               break;
17305             case 2:
17306               return 450; /* sext */
17307             case 3:
17308               return 443; /* clamps */
17309             case 4:
17310               return 444; /* min */
17311             case 5:
17312               return 445; /* max */
17313             case 6:
17314               return 446; /* minu */
17315             case 7:
17316               return 447; /* maxu */
17317             case 8:
17318               return 91; /* moveqz */
17319             case 9:
17320               return 92; /* movnez */
17321             case 10:
17322               return 93; /* movltz */
17323             case 11:
17324               return 94; /* movgez */
17325             case 12:
17326               return 373; /* movf */
17327             case 13:
17328               return 374; /* movt */
17329             case 14:
17330               switch (Field_st_Slot_inst_get (insn))
17331                 {
17332                 case 231:
17333                   return 37; /* rur.threadptr */
17334                 case 232:
17335                   return 464; /* rur.fcr */
17336                 case 233:
17337                   return 466; /* rur.fsr */
17338                 }
17339               break;
17340             case 15:
17341               switch (Field_sr_Slot_inst_get (insn))
17342                 {
17343                 case 231:
17344                   return 38; /* wur.threadptr */
17345                 case 232:
17346                   return 465; /* wur.fcr */
17347                 case 233:
17348                   return 467; /* wur.fsr */
17349                 }
17350               break;
17351             }
17352           break;
17353         case 4:
17354         case 5:
17355           return 78; /* extui */
17356         case 8:
17357           switch (Field_op2_Slot_inst_get (insn))
17358             {
17359             case 0:
17360               return 500; /* lsx */
17361             case 1:
17362               return 501; /* lsxu */
17363             case 4:
17364               return 504; /* ssx */
17365             case 5:
17366               return 505; /* ssxu */
17367             }
17368           break;
17369         case 9:
17370           switch (Field_op2_Slot_inst_get (insn))
17371             {
17372             case 0:
17373               return 18; /* l32e */
17374             case 4:
17375               return 19; /* s32e */
17376             }
17377           break;
17378         case 10:
17379           switch (Field_op2_Slot_inst_get (insn))
17380             {
17381             case 0:
17382               return 468; /* add.s */
17383             case 1:
17384               return 469; /* sub.s */
17385             case 2:
17386               return 470; /* mul.s */
17387             case 4:
17388               return 471; /* madd.s */
17389             case 5:
17390               return 472; /* msub.s */
17391             case 8:
17392               return 491; /* round.s */
17393             case 9:
17394               return 494; /* trunc.s */
17395             case 10:
17396               return 493; /* floor.s */
17397             case 11:
17398               return 492; /* ceil.s */
17399             case 12:
17400               return 489; /* float.s */
17401             case 13:
17402               return 490; /* ufloat.s */
17403             case 14:
17404               return 495; /* utrunc.s */
17405             case 15:
17406               switch (Field_t_Slot_inst_get (insn))
17407                 {
17408                 case 0:
17409                   return 480; /* mov.s */
17410                 case 1:
17411                   return 479; /* abs.s */
17412                 case 4:
17413                   return 496; /* rfr */
17414                 case 5:
17415                   return 497; /* wfr */
17416                 case 6:
17417                   return 481; /* neg.s */
17418                 }
17419               break;
17420             }
17421           break;
17422         case 11:
17423           switch (Field_op2_Slot_inst_get (insn))
17424             {
17425             case 1:
17426               return 482; /* un.s */
17427             case 2:
17428               return 483; /* oeq.s */
17429             case 3:
17430               return 484; /* ueq.s */
17431             case 4:
17432               return 485; /* olt.s */
17433             case 5:
17434               return 486; /* ult.s */
17435             case 6:
17436               return 487; /* ole.s */
17437             case 7:
17438               return 488; /* ule.s */
17439             case 8:
17440               return 475; /* moveqz.s */
17441             case 9:
17442               return 476; /* movnez.s */
17443             case 10:
17444               return 477; /* movltz.s */
17445             case 11:
17446               return 478; /* movgez.s */
17447             case 12:
17448               return 473; /* movf.s */
17449             case 13:
17450               return 474; /* movt.s */
17451             }
17452           break;
17453         }
17454       break;
17455     case 1:
17456       return 85; /* l32r */
17457     case 2:
17458       switch (Field_r_Slot_inst_get (insn))
17459         {
17460         case 0:
17461           return 86; /* l8ui */
17462         case 1:
17463           return 82; /* l16ui */
17464         case 2:
17465           return 84; /* l32i */
17466         case 4:
17467           return 101; /* s8i */
17468         case 5:
17469           return 99; /* s16i */
17470         case 6:
17471           return 100; /* s32i */
17472         case 7:
17473           switch (Field_t_Slot_inst_get (insn))
17474             {
17475             case 0:
17476               return 406; /* dpfr */
17477             case 1:
17478               return 407; /* dpfw */
17479             case 2:
17480               return 408; /* dpfro */
17481             case 3:
17482               return 409; /* dpfwo */
17483             case 4:
17484               return 400; /* dhwb */
17485             case 5:
17486               return 401; /* dhwbi */
17487             case 6:
17488               return 404; /* dhi */
17489             case 7:
17490               return 405; /* dii */
17491             case 8:
17492               switch (Field_op1_Slot_inst_get (insn))
17493                 {
17494                 case 0:
17495                   return 410; /* dpfl */
17496                 case 2:
17497                   return 411; /* dhu */
17498                 case 3:
17499                   return 412; /* diu */
17500                 case 4:
17501                   return 402; /* diwb */
17502                 case 5:
17503                   return 403; /* diwbi */
17504                 }
17505               break;
17506             case 12:
17507               return 390; /* ipf */
17508             case 13:
17509               switch (Field_op1_Slot_inst_get (insn))
17510                 {
17511                 case 0:
17512                   return 392; /* ipfl */
17513                 case 2:
17514                   return 393; /* ihu */
17515                 case 3:
17516                   return 394; /* iiu */
17517                 }
17518               break;
17519             case 14:
17520               return 391; /* ihi */
17521             case 15:
17522               return 395; /* iii */
17523             }
17524           break;
17525         case 9:
17526           return 83; /* l16si */
17527         case 10:
17528           return 90; /* movi */
17529         case 11:
17530           return 451; /* l32ai */
17531         case 12:
17532           return 39; /* addi */
17533         case 13:
17534           return 40; /* addmi */
17535         case 14:
17536           return 453; /* s32c1i */
17537         case 15:
17538           return 452; /* s32ri */
17539         }
17540       break;
17541     case 3:
17542       switch (Field_r_Slot_inst_get (insn))
17543         {
17544         case 0:
17545           return 498; /* lsi */
17546         case 4:
17547           return 502; /* ssi */
17548         case 8:
17549           return 499; /* lsiu */
17550         case 12:
17551           return 503; /* ssiu */
17552         }
17553       break;
17554     case 4:
17555       switch (Field_op2_Slot_inst_get (insn))
17556         {
17557         case 0:
17558           switch (Field_op1_Slot_inst_get (insn))
17559             {
17560             case 8:
17561               if (Field_t3_Slot_inst_get (insn) == 0 &&
17562                   Field_tlo_Slot_inst_get (insn) == 0 &&
17563                   Field_r3_Slot_inst_get (insn) == 0)
17564                 return 287; /* mula.dd.ll.ldinc */
17565               break;
17566             case 9:
17567               if (Field_t3_Slot_inst_get (insn) == 0 &&
17568                   Field_tlo_Slot_inst_get (insn) == 0 &&
17569                   Field_r3_Slot_inst_get (insn) == 0)
17570                 return 289; /* mula.dd.hl.ldinc */
17571               break;
17572             case 10:
17573               if (Field_t3_Slot_inst_get (insn) == 0 &&
17574                   Field_tlo_Slot_inst_get (insn) == 0 &&
17575                   Field_r3_Slot_inst_get (insn) == 0)
17576                 return 291; /* mula.dd.lh.ldinc */
17577               break;
17578             case 11:
17579               if (Field_t3_Slot_inst_get (insn) == 0 &&
17580                   Field_tlo_Slot_inst_get (insn) == 0 &&
17581                   Field_r3_Slot_inst_get (insn) == 0)
17582                 return 293; /* mula.dd.hh.ldinc */
17583               break;
17584             }
17585           break;
17586         case 1:
17587           switch (Field_op1_Slot_inst_get (insn))
17588             {
17589             case 8:
17590               if (Field_t3_Slot_inst_get (insn) == 0 &&
17591                   Field_tlo_Slot_inst_get (insn) == 0 &&
17592                   Field_r3_Slot_inst_get (insn) == 0)
17593                 return 286; /* mula.dd.ll.lddec */
17594               break;
17595             case 9:
17596               if (Field_t3_Slot_inst_get (insn) == 0 &&
17597                   Field_tlo_Slot_inst_get (insn) == 0 &&
17598                   Field_r3_Slot_inst_get (insn) == 0)
17599                 return 288; /* mula.dd.hl.lddec */
17600               break;
17601             case 10:
17602               if (Field_t3_Slot_inst_get (insn) == 0 &&
17603                   Field_tlo_Slot_inst_get (insn) == 0 &&
17604                   Field_r3_Slot_inst_get (insn) == 0)
17605                 return 290; /* mula.dd.lh.lddec */
17606               break;
17607             case 11:
17608               if (Field_t3_Slot_inst_get (insn) == 0 &&
17609                   Field_tlo_Slot_inst_get (insn) == 0 &&
17610                   Field_r3_Slot_inst_get (insn) == 0)
17611                 return 292; /* mula.dd.hh.lddec */
17612               break;
17613             }
17614           break;
17615         case 2:
17616           switch (Field_op1_Slot_inst_get (insn))
17617             {
17618             case 4:
17619               if (Field_s_Slot_inst_get (insn) == 0 &&
17620                   Field_w_Slot_inst_get (insn) == 0 &&
17621                   Field_r3_Slot_inst_get (insn) == 0 &&
17622                   Field_t3_Slot_inst_get (insn) == 0 &&
17623                   Field_tlo_Slot_inst_get (insn) == 0)
17624                 return 242; /* mul.dd.ll */
17625               break;
17626             case 5:
17627               if (Field_s_Slot_inst_get (insn) == 0 &&
17628                   Field_w_Slot_inst_get (insn) == 0 &&
17629                   Field_r3_Slot_inst_get (insn) == 0 &&
17630                   Field_t3_Slot_inst_get (insn) == 0 &&
17631                   Field_tlo_Slot_inst_get (insn) == 0)
17632                 return 243; /* mul.dd.hl */
17633               break;
17634             case 6:
17635               if (Field_s_Slot_inst_get (insn) == 0 &&
17636                   Field_w_Slot_inst_get (insn) == 0 &&
17637                   Field_r3_Slot_inst_get (insn) == 0 &&
17638                   Field_t3_Slot_inst_get (insn) == 0 &&
17639                   Field_tlo_Slot_inst_get (insn) == 0)
17640                 return 244; /* mul.dd.lh */
17641               break;
17642             case 7:
17643               if (Field_s_Slot_inst_get (insn) == 0 &&
17644                   Field_w_Slot_inst_get (insn) == 0 &&
17645                   Field_r3_Slot_inst_get (insn) == 0 &&
17646                   Field_t3_Slot_inst_get (insn) == 0 &&
17647                   Field_tlo_Slot_inst_get (insn) == 0)
17648                 return 245; /* mul.dd.hh */
17649               break;
17650             case 8:
17651               if (Field_s_Slot_inst_get (insn) == 0 &&
17652                   Field_w_Slot_inst_get (insn) == 0 &&
17653                   Field_r3_Slot_inst_get (insn) == 0 &&
17654                   Field_t3_Slot_inst_get (insn) == 0 &&
17655                   Field_tlo_Slot_inst_get (insn) == 0)
17656                 return 270; /* mula.dd.ll */
17657               break;
17658             case 9:
17659               if (Field_s_Slot_inst_get (insn) == 0 &&
17660                   Field_w_Slot_inst_get (insn) == 0 &&
17661                   Field_r3_Slot_inst_get (insn) == 0 &&
17662                   Field_t3_Slot_inst_get (insn) == 0 &&
17663                   Field_tlo_Slot_inst_get (insn) == 0)
17664                 return 271; /* mula.dd.hl */
17665               break;
17666             case 10:
17667               if (Field_s_Slot_inst_get (insn) == 0 &&
17668                   Field_w_Slot_inst_get (insn) == 0 &&
17669                   Field_r3_Slot_inst_get (insn) == 0 &&
17670                   Field_t3_Slot_inst_get (insn) == 0 &&
17671                   Field_tlo_Slot_inst_get (insn) == 0)
17672                 return 272; /* mula.dd.lh */
17673               break;
17674             case 11:
17675               if (Field_s_Slot_inst_get (insn) == 0 &&
17676                   Field_w_Slot_inst_get (insn) == 0 &&
17677                   Field_r3_Slot_inst_get (insn) == 0 &&
17678                   Field_t3_Slot_inst_get (insn) == 0 &&
17679                   Field_tlo_Slot_inst_get (insn) == 0)
17680                 return 273; /* mula.dd.hh */
17681               break;
17682             case 12:
17683               if (Field_s_Slot_inst_get (insn) == 0 &&
17684                   Field_w_Slot_inst_get (insn) == 0 &&
17685                   Field_r3_Slot_inst_get (insn) == 0 &&
17686                   Field_t3_Slot_inst_get (insn) == 0 &&
17687                   Field_tlo_Slot_inst_get (insn) == 0)
17688                 return 274; /* muls.dd.ll */
17689               break;
17690             case 13:
17691               if (Field_s_Slot_inst_get (insn) == 0 &&
17692                   Field_w_Slot_inst_get (insn) == 0 &&
17693                   Field_r3_Slot_inst_get (insn) == 0 &&
17694                   Field_t3_Slot_inst_get (insn) == 0 &&
17695                   Field_tlo_Slot_inst_get (insn) == 0)
17696                 return 275; /* muls.dd.hl */
17697               break;
17698             case 14:
17699               if (Field_s_Slot_inst_get (insn) == 0 &&
17700                   Field_w_Slot_inst_get (insn) == 0 &&
17701                   Field_r3_Slot_inst_get (insn) == 0 &&
17702                   Field_t3_Slot_inst_get (insn) == 0 &&
17703                   Field_tlo_Slot_inst_get (insn) == 0)
17704                 return 276; /* muls.dd.lh */
17705               break;
17706             case 15:
17707               if (Field_s_Slot_inst_get (insn) == 0 &&
17708                   Field_w_Slot_inst_get (insn) == 0 &&
17709                   Field_r3_Slot_inst_get (insn) == 0 &&
17710                   Field_t3_Slot_inst_get (insn) == 0 &&
17711                   Field_tlo_Slot_inst_get (insn) == 0)
17712                 return 277; /* muls.dd.hh */
17713               break;
17714             }
17715           break;
17716         case 3:
17717           switch (Field_op1_Slot_inst_get (insn))
17718             {
17719             case 4:
17720               if (Field_r_Slot_inst_get (insn) == 0 &&
17721                   Field_t3_Slot_inst_get (insn) == 0 &&
17722                   Field_tlo_Slot_inst_get (insn) == 0)
17723                 return 234; /* mul.ad.ll */
17724               break;
17725             case 5:
17726               if (Field_r_Slot_inst_get (insn) == 0 &&
17727                   Field_t3_Slot_inst_get (insn) == 0 &&
17728                   Field_tlo_Slot_inst_get (insn) == 0)
17729                 return 235; /* mul.ad.hl */
17730               break;
17731             case 6:
17732               if (Field_r_Slot_inst_get (insn) == 0 &&
17733                   Field_t3_Slot_inst_get (insn) == 0 &&
17734                   Field_tlo_Slot_inst_get (insn) == 0)
17735                 return 236; /* mul.ad.lh */
17736               break;
17737             case 7:
17738               if (Field_r_Slot_inst_get (insn) == 0 &&
17739                   Field_t3_Slot_inst_get (insn) == 0 &&
17740                   Field_tlo_Slot_inst_get (insn) == 0)
17741                 return 237; /* mul.ad.hh */
17742               break;
17743             case 8:
17744               if (Field_r_Slot_inst_get (insn) == 0 &&
17745                   Field_t3_Slot_inst_get (insn) == 0 &&
17746                   Field_tlo_Slot_inst_get (insn) == 0)
17747                 return 254; /* mula.ad.ll */
17748               break;
17749             case 9:
17750               if (Field_r_Slot_inst_get (insn) == 0 &&
17751                   Field_t3_Slot_inst_get (insn) == 0 &&
17752                   Field_tlo_Slot_inst_get (insn) == 0)
17753                 return 255; /* mula.ad.hl */
17754               break;
17755             case 10:
17756               if (Field_r_Slot_inst_get (insn) == 0 &&
17757                   Field_t3_Slot_inst_get (insn) == 0 &&
17758                   Field_tlo_Slot_inst_get (insn) == 0)
17759                 return 256; /* mula.ad.lh */
17760               break;
17761             case 11:
17762               if (Field_r_Slot_inst_get (insn) == 0 &&
17763                   Field_t3_Slot_inst_get (insn) == 0 &&
17764                   Field_tlo_Slot_inst_get (insn) == 0)
17765                 return 257; /* mula.ad.hh */
17766               break;
17767             case 12:
17768               if (Field_r_Slot_inst_get (insn) == 0 &&
17769                   Field_t3_Slot_inst_get (insn) == 0 &&
17770                   Field_tlo_Slot_inst_get (insn) == 0)
17771                 return 258; /* muls.ad.ll */
17772               break;
17773             case 13:
17774               if (Field_r_Slot_inst_get (insn) == 0 &&
17775                   Field_t3_Slot_inst_get (insn) == 0 &&
17776                   Field_tlo_Slot_inst_get (insn) == 0)
17777                 return 259; /* muls.ad.hl */
17778               break;
17779             case 14:
17780               if (Field_r_Slot_inst_get (insn) == 0 &&
17781                   Field_t3_Slot_inst_get (insn) == 0 &&
17782                   Field_tlo_Slot_inst_get (insn) == 0)
17783                 return 260; /* muls.ad.lh */
17784               break;
17785             case 15:
17786               if (Field_r_Slot_inst_get (insn) == 0 &&
17787                   Field_t3_Slot_inst_get (insn) == 0 &&
17788                   Field_tlo_Slot_inst_get (insn) == 0)
17789                 return 261; /* muls.ad.hh */
17790               break;
17791             }
17792           break;
17793         case 4:
17794           switch (Field_op1_Slot_inst_get (insn))
17795             {
17796             case 8:
17797               if (Field_r3_Slot_inst_get (insn) == 0)
17798                 return 279; /* mula.da.ll.ldinc */
17799               break;
17800             case 9:
17801               if (Field_r3_Slot_inst_get (insn) == 0)
17802                 return 281; /* mula.da.hl.ldinc */
17803               break;
17804             case 10:
17805               if (Field_r3_Slot_inst_get (insn) == 0)
17806                 return 283; /* mula.da.lh.ldinc */
17807               break;
17808             case 11:
17809               if (Field_r3_Slot_inst_get (insn) == 0)
17810                 return 285; /* mula.da.hh.ldinc */
17811               break;
17812             }
17813           break;
17814         case 5:
17815           switch (Field_op1_Slot_inst_get (insn))
17816             {
17817             case 8:
17818               if (Field_r3_Slot_inst_get (insn) == 0)
17819                 return 278; /* mula.da.ll.lddec */
17820               break;
17821             case 9:
17822               if (Field_r3_Slot_inst_get (insn) == 0)
17823                 return 280; /* mula.da.hl.lddec */
17824               break;
17825             case 10:
17826               if (Field_r3_Slot_inst_get (insn) == 0)
17827                 return 282; /* mula.da.lh.lddec */
17828               break;
17829             case 11:
17830               if (Field_r3_Slot_inst_get (insn) == 0)
17831                 return 284; /* mula.da.hh.lddec */
17832               break;
17833             }
17834           break;
17835         case 6:
17836           switch (Field_op1_Slot_inst_get (insn))
17837             {
17838             case 4:
17839               if (Field_s_Slot_inst_get (insn) == 0 &&
17840                   Field_w_Slot_inst_get (insn) == 0 &&
17841                   Field_r3_Slot_inst_get (insn) == 0)
17842                 return 238; /* mul.da.ll */
17843               break;
17844             case 5:
17845               if (Field_s_Slot_inst_get (insn) == 0 &&
17846                   Field_w_Slot_inst_get (insn) == 0 &&
17847                   Field_r3_Slot_inst_get (insn) == 0)
17848                 return 239; /* mul.da.hl */
17849               break;
17850             case 6:
17851               if (Field_s_Slot_inst_get (insn) == 0 &&
17852                   Field_w_Slot_inst_get (insn) == 0 &&
17853                   Field_r3_Slot_inst_get (insn) == 0)
17854                 return 240; /* mul.da.lh */
17855               break;
17856             case 7:
17857               if (Field_s_Slot_inst_get (insn) == 0 &&
17858                   Field_w_Slot_inst_get (insn) == 0 &&
17859                   Field_r3_Slot_inst_get (insn) == 0)
17860                 return 241; /* mul.da.hh */
17861               break;
17862             case 8:
17863               if (Field_s_Slot_inst_get (insn) == 0 &&
17864                   Field_w_Slot_inst_get (insn) == 0 &&
17865                   Field_r3_Slot_inst_get (insn) == 0)
17866                 return 262; /* mula.da.ll */
17867               break;
17868             case 9:
17869               if (Field_s_Slot_inst_get (insn) == 0 &&
17870                   Field_w_Slot_inst_get (insn) == 0 &&
17871                   Field_r3_Slot_inst_get (insn) == 0)
17872                 return 263; /* mula.da.hl */
17873               break;
17874             case 10:
17875               if (Field_s_Slot_inst_get (insn) == 0 &&
17876                   Field_w_Slot_inst_get (insn) == 0 &&
17877                   Field_r3_Slot_inst_get (insn) == 0)
17878                 return 264; /* mula.da.lh */
17879               break;
17880             case 11:
17881               if (Field_s_Slot_inst_get (insn) == 0 &&
17882                   Field_w_Slot_inst_get (insn) == 0 &&
17883                   Field_r3_Slot_inst_get (insn) == 0)
17884                 return 265; /* mula.da.hh */
17885               break;
17886             case 12:
17887               if (Field_s_Slot_inst_get (insn) == 0 &&
17888                   Field_w_Slot_inst_get (insn) == 0 &&
17889                   Field_r3_Slot_inst_get (insn) == 0)
17890                 return 266; /* muls.da.ll */
17891               break;
17892             case 13:
17893               if (Field_s_Slot_inst_get (insn) == 0 &&
17894                   Field_w_Slot_inst_get (insn) == 0 &&
17895                   Field_r3_Slot_inst_get (insn) == 0)
17896                 return 267; /* muls.da.hl */
17897               break;
17898             case 14:
17899               if (Field_s_Slot_inst_get (insn) == 0 &&
17900                   Field_w_Slot_inst_get (insn) == 0 &&
17901                   Field_r3_Slot_inst_get (insn) == 0)
17902                 return 268; /* muls.da.lh */
17903               break;
17904             case 15:
17905               if (Field_s_Slot_inst_get (insn) == 0 &&
17906                   Field_w_Slot_inst_get (insn) == 0 &&
17907                   Field_r3_Slot_inst_get (insn) == 0)
17908                 return 269; /* muls.da.hh */
17909               break;
17910             }
17911           break;
17912         case 7:
17913           switch (Field_op1_Slot_inst_get (insn))
17914             {
17915             case 0:
17916               if (Field_r_Slot_inst_get (insn) == 0)
17917                 return 230; /* umul.aa.ll */
17918               break;
17919             case 1:
17920               if (Field_r_Slot_inst_get (insn) == 0)
17921                 return 231; /* umul.aa.hl */
17922               break;
17923             case 2:
17924               if (Field_r_Slot_inst_get (insn) == 0)
17925                 return 232; /* umul.aa.lh */
17926               break;
17927             case 3:
17928               if (Field_r_Slot_inst_get (insn) == 0)
17929                 return 233; /* umul.aa.hh */
17930               break;
17931             case 4:
17932               if (Field_r_Slot_inst_get (insn) == 0)
17933                 return 226; /* mul.aa.ll */
17934               break;
17935             case 5:
17936               if (Field_r_Slot_inst_get (insn) == 0)
17937                 return 227; /* mul.aa.hl */
17938               break;
17939             case 6:
17940               if (Field_r_Slot_inst_get (insn) == 0)
17941                 return 228; /* mul.aa.lh */
17942               break;
17943             case 7:
17944               if (Field_r_Slot_inst_get (insn) == 0)
17945                 return 229; /* mul.aa.hh */
17946               break;
17947             case 8:
17948               if (Field_r_Slot_inst_get (insn) == 0)
17949                 return 246; /* mula.aa.ll */
17950               break;
17951             case 9:
17952               if (Field_r_Slot_inst_get (insn) == 0)
17953                 return 247; /* mula.aa.hl */
17954               break;
17955             case 10:
17956               if (Field_r_Slot_inst_get (insn) == 0)
17957                 return 248; /* mula.aa.lh */
17958               break;
17959             case 11:
17960               if (Field_r_Slot_inst_get (insn) == 0)
17961                 return 249; /* mula.aa.hh */
17962               break;
17963             case 12:
17964               if (Field_r_Slot_inst_get (insn) == 0)
17965                 return 250; /* muls.aa.ll */
17966               break;
17967             case 13:
17968               if (Field_r_Slot_inst_get (insn) == 0)
17969                 return 251; /* muls.aa.hl */
17970               break;
17971             case 14:
17972               if (Field_r_Slot_inst_get (insn) == 0)
17973                 return 252; /* muls.aa.lh */
17974               break;
17975             case 15:
17976               if (Field_r_Slot_inst_get (insn) == 0)
17977                 return 253; /* muls.aa.hh */
17978               break;
17979             }
17980           break;
17981         case 8:
17982           if (Field_op1_Slot_inst_get (insn) == 0 &&
17983               Field_t_Slot_inst_get (insn) == 0 &&
17984               Field_rhi_Slot_inst_get (insn) == 0)
17985             return 295; /* ldinc */
17986           break;
17987         case 9:
17988           if (Field_op1_Slot_inst_get (insn) == 0 &&
17989               Field_t_Slot_inst_get (insn) == 0 &&
17990               Field_rhi_Slot_inst_get (insn) == 0)
17991             return 294; /* lddec */
17992           break;
17993         }
17994       break;
17995     case 5:
17996       switch (Field_n_Slot_inst_get (insn))
17997         {
17998         case 0:
17999           return 76; /* call0 */
18000         case 1:
18001           return 7; /* call4 */
18002         case 2:
18003           return 6; /* call8 */
18004         case 3:
18005           return 5; /* call12 */
18006         }
18007       break;
18008     case 6:
18009       switch (Field_n_Slot_inst_get (insn))
18010         {
18011         case 0:
18012           return 80; /* j */
18013         case 1:
18014           switch (Field_m_Slot_inst_get (insn))
18015             {
18016             case 0:
18017               return 72; /* beqz */
18018             case 1:
18019               return 73; /* bnez */
18020             case 2:
18021               return 75; /* bltz */
18022             case 3:
18023               return 74; /* bgez */
18024             }
18025           break;
18026         case 2:
18027           switch (Field_m_Slot_inst_get (insn))
18028             {
18029             case 0:
18030               return 52; /* beqi */
18031             case 1:
18032               return 53; /* bnei */
18033             case 2:
18034               return 55; /* blti */
18035             case 3:
18036               return 54; /* bgei */
18037             }
18038           break;
18039         case 3:
18040           switch (Field_m_Slot_inst_get (insn))
18041             {
18042             case 0:
18043               return 11; /* entry */
18044             case 1:
18045               switch (Field_r_Slot_inst_get (insn))
18046                 {
18047                 case 0:
18048                   return 371; /* bf */
18049                 case 1:
18050                   return 372; /* bt */
18051                 case 8:
18052                   return 87; /* loop */
18053                 case 9:
18054                   return 88; /* loopnez */
18055                 case 10:
18056                   return 89; /* loopgtz */
18057                 }
18058               break;
18059             case 2:
18060               return 59; /* bltui */
18061             case 3:
18062               return 58; /* bgeui */
18063             }
18064           break;
18065         }
18066       break;
18067     case 7:
18068       switch (Field_r_Slot_inst_get (insn))
18069         {
18070         case 0:
18071           return 67; /* bnone */
18072         case 1:
18073           return 60; /* beq */
18074         case 2:
18075           return 63; /* blt */
18076         case 3:
18077           return 65; /* bltu */
18078         case 4:
18079           return 68; /* ball */
18080         case 5:
18081           return 70; /* bbc */
18082         case 6:
18083         case 7:
18084           return 56; /* bbci */
18085         case 8:
18086           return 66; /* bany */
18087         case 9:
18088           return 61; /* bne */
18089         case 10:
18090           return 62; /* bge */
18091         case 11:
18092           return 64; /* bgeu */
18093         case 12:
18094           return 69; /* bnall */
18095         case 13:
18096           return 71; /* bbs */
18097         case 14:
18098         case 15:
18099           return 57; /* bbsi */
18100         }
18101       break;
18102     }
18103   return 0;
18104 }
18105
18106 static int
18107 Slot_inst16b_decode (const xtensa_insnbuf insn)
18108 {
18109   switch (Field_op0_Slot_inst16b_get (insn))
18110     {
18111     case 12:
18112       switch (Field_i_Slot_inst16b_get (insn))
18113         {
18114         case 0:
18115           return 33; /* movi.n */
18116         case 1:
18117           switch (Field_z_Slot_inst16b_get (insn))
18118             {
18119             case 0:
18120               return 28; /* beqz.n */
18121             case 1:
18122               return 29; /* bnez.n */
18123             }
18124           break;
18125         }
18126       break;
18127     case 13:
18128       switch (Field_r_Slot_inst16b_get (insn))
18129         {
18130         case 0:
18131           return 32; /* mov.n */
18132         case 15:
18133           switch (Field_t_Slot_inst16b_get (insn))
18134             {
18135             case 0:
18136               return 35; /* ret.n */
18137             case 1:
18138               return 15; /* retw.n */
18139             case 2:
18140               return 325; /* break.n */
18141             case 3:
18142               if (Field_s_Slot_inst16b_get (insn) == 0)
18143                 return 34; /* nop.n */
18144               break;
18145             case 6:
18146               if (Field_s_Slot_inst16b_get (insn) == 0)
18147                 return 30; /* ill.n */
18148               break;
18149             }
18150           break;
18151         }
18152       break;
18153     }
18154   return 0;
18155 }
18156
18157 static int
18158 Slot_inst16a_decode (const xtensa_insnbuf insn)
18159 {
18160   switch (Field_op0_Slot_inst16a_get (insn))
18161     {
18162     case 8:
18163       return 31; /* l32i.n */
18164     case 9:
18165       return 36; /* s32i.n */
18166     case 10:
18167       return 26; /* add.n */
18168     case 11:
18169       return 27; /* addi.n */
18170     }
18171   return 0;
18172 }
18173
18174 static int
18175 Slot_xt_flix64_slot2_decode (const xtensa_insnbuf insn)
18176 {
18177   switch (Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn))
18178     {
18179     case 0:
18180       if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 1)
18181         return 41; /* add */
18182       if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 5)
18183         return 42; /* sub */
18184       if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 2)
18185         return 43; /* addx2 */
18186       if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 3)
18187         return 49; /* and */
18188       if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 4)
18189         return 450; /* sext */
18190       break;
18191     case 1:
18192       if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 1)
18193         return 27; /* addi.n */
18194       if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 2)
18195         return 44; /* addx4 */
18196       if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 3)
18197         return 50; /* or */
18198       if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 5)
18199         return 51; /* xor */
18200       if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 4)
18201         return 113; /* srli */
18202       break;
18203     }
18204   if (Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0 &&
18205       Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6)
18206     return 33; /* movi.n */
18207   if (Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 2 &&
18208       Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
18209       Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
18210     return 32; /* mov.n */
18211   if (Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 3 &&
18212       Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
18213       Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
18214     return 97; /* nop */
18215   if (Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 8 &&
18216       Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
18217       Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
18218     return 96; /* abs */
18219   if (Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 9 &&
18220       Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
18221       Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
18222     return 95; /* neg */
18223   if (Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 5 &&
18224       Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
18225       Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
18226     return 110; /* sra */
18227   if (Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 3 &&
18228       Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
18229       Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
18230     return 109; /* srl */
18231   if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 7)
18232     return 112; /* srai */
18233   return 0;
18234 }
18235
18236 static int
18237 Slot_xt_flix64_slot0_decode (const xtensa_insnbuf insn)
18238 {
18239   switch (Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get (insn))
18240     {
18241     case 0:
18242       if (Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get (insn) == 2)
18243         return 78; /* extui */
18244       switch (Field_op1_Slot_xt_flix64_slot0_get (insn))
18245         {
18246         case 0:
18247           switch (Field_op2_Slot_xt_flix64_slot0_get (insn))
18248             {
18249             case 0:
18250               if (Field_r_Slot_xt_flix64_slot0_get (insn) == 2)
18251                 {
18252                   if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0)
18253                     {
18254                       if (Field_t_Slot_xt_flix64_slot0_get (insn) == 15)
18255                         return 97; /* nop */
18256                     }
18257                 }
18258               break;
18259             case 1:
18260               return 49; /* and */
18261             case 2:
18262               return 50; /* or */
18263             case 3:
18264               return 51; /* xor */
18265             case 4:
18266               switch (Field_r_Slot_xt_flix64_slot0_get (insn))
18267                 {
18268                 case 0:
18269                   if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
18270                     return 102; /* ssr */
18271                   break;
18272                 case 1:
18273                   if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
18274                     return 103; /* ssl */
18275                   break;
18276                 case 2:
18277                   if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
18278                     return 104; /* ssa8l */
18279                   break;
18280                 case 3:
18281                   if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
18282                     return 105; /* ssa8b */
18283                   break;
18284                 case 4:
18285                   if (Field_thi3_Slot_xt_flix64_slot0_get (insn) == 0)
18286                     return 106; /* ssai */
18287                   break;
18288                 case 14:
18289                   return 448; /* nsa */
18290                 case 15:
18291                   return 449; /* nsau */
18292                 }
18293               break;
18294             case 6:
18295               switch (Field_s_Slot_xt_flix64_slot0_get (insn))
18296                 {
18297                 case 0:
18298                   return 95; /* neg */
18299                 case 1:
18300                   return 96; /* abs */
18301                 }
18302               break;
18303             case 8:
18304               return 41; /* add */
18305             case 9:
18306               return 43; /* addx2 */
18307             case 10:
18308               return 44; /* addx4 */
18309             case 11:
18310               return 45; /* addx8 */
18311             case 12:
18312               return 42; /* sub */
18313             case 13:
18314               return 46; /* subx2 */
18315             case 14:
18316               return 47; /* subx4 */
18317             case 15:
18318               return 48; /* subx8 */
18319             }
18320           break;
18321         case 1:
18322           if (Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get (insn) == 1)
18323             return 112; /* srai */
18324           if (Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get (insn) == 0)
18325             return 111; /* slli */
18326           switch (Field_op2_Slot_xt_flix64_slot0_get (insn))
18327             {
18328             case 4:
18329               return 113; /* srli */
18330             case 8:
18331               return 108; /* src */
18332             case 9:
18333               if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0)
18334                 return 109; /* srl */
18335               break;
18336             case 10:
18337               if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
18338                 return 107; /* sll */
18339               break;
18340             case 11:
18341               if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0)
18342                 return 110; /* sra */
18343               break;
18344             case 12:
18345               return 296; /* mul16u */
18346             case 13:
18347               return 297; /* mul16s */
18348             }
18349           break;
18350         case 2:
18351           if (Field_op2_Slot_xt_flix64_slot0_get (insn) == 8)
18352             return 461; /* mull */
18353           break;
18354         case 3:
18355           switch (Field_op2_Slot_xt_flix64_slot0_get (insn))
18356             {
18357             case 2:
18358               return 450; /* sext */
18359             case 3:
18360               return 443; /* clamps */
18361             case 4:
18362               return 444; /* min */
18363             case 5:
18364               return 445; /* max */
18365             case 6:
18366               return 446; /* minu */
18367             case 7:
18368               return 447; /* maxu */
18369             case 8:
18370               return 91; /* moveqz */
18371             case 9:
18372               return 92; /* movnez */
18373             case 10:
18374               return 93; /* movltz */
18375             case 11:
18376               return 94; /* movgez */
18377             }
18378           break;
18379         }
18380       break;
18381     case 2:
18382       switch (Field_r_Slot_xt_flix64_slot0_get (insn))
18383         {
18384         case 0:
18385           return 86; /* l8ui */
18386         case 1:
18387           return 82; /* l16ui */
18388         case 2:
18389           return 84; /* l32i */
18390         case 4:
18391           return 101; /* s8i */
18392         case 5:
18393           return 99; /* s16i */
18394         case 6:
18395           return 100; /* s32i */
18396         case 9:
18397           return 83; /* l16si */
18398         case 10:
18399           return 90; /* movi */
18400         case 12:
18401           return 39; /* addi */
18402         case 13:
18403           return 40; /* addmi */
18404         }
18405       break;
18406     }
18407   if (Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (insn) == 1)
18408     return 85; /* l32r */
18409   if (Field_sae4_Slot_xt_flix64_slot0_get (insn) == 0 &&
18410       Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get (insn) == 3 &&
18411       Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (insn) == 0 &&
18412       Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get (insn) == 0)
18413     return 32; /* mov.n */
18414   return 0;
18415 }
18416
18417 static int
18418 Slot_xt_flix64_slot1_decode (const xtensa_insnbuf insn)
18419 {
18420   if (Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0 &&
18421       Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1)
18422     return 78; /* extui */
18423   switch (Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn))
18424     {
18425     case 0:
18426       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18427         return 90; /* movi */
18428       break;
18429     case 2:
18430       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1)
18431         return 39; /* addi */
18432       break;
18433     case 3:
18434       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1)
18435         return 40; /* addmi */
18436       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18437           Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get (insn) == 0)
18438         return 51; /* xor */
18439       break;
18440     }
18441   switch (Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn))
18442     {
18443     case 8:
18444       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18445         return 111; /* slli */
18446       break;
18447     case 16:
18448       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18449         return 112; /* srai */
18450       break;
18451     case 19:
18452       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18453           Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18454         return 107; /* sll */
18455       break;
18456     }
18457   switch (Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn))
18458     {
18459     case 18:
18460       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18461         return 41; /* add */
18462       break;
18463     case 19:
18464       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18465         return 45; /* addx8 */
18466       break;
18467     case 20:
18468       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18469         return 43; /* addx2 */
18470       break;
18471     case 21:
18472       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18473         return 49; /* and */
18474       break;
18475     case 22:
18476       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18477         return 91; /* moveqz */
18478       break;
18479     case 23:
18480       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18481         return 94; /* movgez */
18482       break;
18483     case 24:
18484       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18485         return 44; /* addx4 */
18486       break;
18487     case 25:
18488       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18489         return 93; /* movltz */
18490       break;
18491     case 26:
18492       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18493         return 92; /* movnez */
18494       break;
18495     case 27:
18496       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18497         return 296; /* mul16u */
18498       break;
18499     case 28:
18500       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18501         return 297; /* mul16s */
18502       break;
18503     case 29:
18504       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18505         return 461; /* mull */
18506       break;
18507     case 30:
18508       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18509         return 50; /* or */
18510       break;
18511     case 31:
18512       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18513         return 450; /* sext */
18514       break;
18515     case 34:
18516       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18517         return 108; /* src */
18518       break;
18519     case 36:
18520       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18521         return 113; /* srli */
18522       break;
18523     }
18524   if (Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 280 &&
18525       Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18526       Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18527     return 32; /* mov.n */
18528   if (Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 281 &&
18529       Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18530       Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18531     return 81; /* jx */
18532   if (Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 141 &&
18533       Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18534       Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18535     return 103; /* ssl */
18536   if (Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 71 &&
18537       Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18538       Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18539     return 97; /* nop */
18540   if (Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 148 &&
18541       Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18542       Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18543     return 95; /* neg */
18544   if (Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 149 &&
18545       Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18546       Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18547     return 110; /* sra */
18548   if (Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 75 &&
18549       Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18550       Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18551     return 109; /* srl */
18552   if (Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 5 &&
18553       Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18554       Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18555     return 42; /* sub */
18556   if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 3)
18557     return 80; /* j */
18558   return 0;
18559 }
18560
18561 static int
18562 Slot_xt_flix64_slot3_decode (const xtensa_insnbuf insn)
18563 {
18564   switch (Field_op0_s6_Slot_xt_flix64_slot3_get (insn))
18565     {
18566     case 1:
18567       if (Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (insn) == 0)
18568         return 516; /* bbci.w18 */
18569       break;
18570     case 2:
18571       if (Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (insn) == 0)
18572         return 517; /* bbsi.w18 */
18573       break;
18574     case 3:
18575       if (Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18576         return 526; /* ball.w18 */
18577       break;
18578     case 4:
18579       if (Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18580         return 524; /* bany.w18 */
18581       break;
18582     case 5:
18583       if (Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18584         return 528; /* bbc.w18 */
18585       break;
18586     case 6:
18587       if (Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18588         return 529; /* bbs.w18 */
18589       break;
18590     case 7:
18591       if (Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18592         return 518; /* beq.w18 */
18593       break;
18594     case 8:
18595       if (Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18596         return 510; /* beqi.w18 */
18597       break;
18598     case 9:
18599       if (Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18600         return 520; /* bge.w18 */
18601       break;
18602     case 10:
18603       if (Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18604         return 512; /* bgei.w18 */
18605       break;
18606     case 11:
18607       if (Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18608         return 522; /* bgeu.w18 */
18609       break;
18610     case 12:
18611       if (Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18612         return 514; /* bgeui.w18 */
18613       break;
18614     case 13:
18615       if (Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18616         return 521; /* blt.w18 */
18617       break;
18618     case 14:
18619       if (Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18620         return 513; /* blti.w18 */
18621       break;
18622     case 15:
18623       if (Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18624         return 523; /* bltu.w18 */
18625       break;
18626     case 16:
18627       if (Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18628         return 515; /* bltui.w18 */
18629       break;
18630     case 17:
18631       if (Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18632         return 527; /* bnall.w18 */
18633       break;
18634     case 18:
18635       if (Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18636         return 519; /* bne.w18 */
18637       break;
18638     case 19:
18639       if (Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18640         return 511; /* bnei.w18 */
18641       break;
18642     case 20:
18643       if (Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18644         return 525; /* bnone.w18 */
18645       break;
18646     case 21:
18647       if (Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18648         return 506; /* beqz.w18 */
18649       break;
18650     case 22:
18651       if (Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18652         return 508; /* bgez.w18 */
18653       break;
18654     case 23:
18655       if (Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18656         return 509; /* bltz.w18 */
18657       break;
18658     case 24:
18659       if (Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18660         return 507; /* bnez.w18 */
18661       break;
18662     case 25:
18663       if (Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18664         return 97; /* nop */
18665       break;
18666     }
18667   return 0;
18668 }
18669
18670 \f
18671 /* Instruction slots.  */
18672
18673 static void
18674 Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
18675                             xtensa_insnbuf slotbuf)
18676 {
18677   slotbuf[1] = 0;
18678   slotbuf[0] = (insn[0] & 0xffffff);
18679 }
18680
18681 static void
18682 Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
18683                             const xtensa_insnbuf slotbuf)
18684 {
18685   insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
18686 }
18687
18688 static void
18689 Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
18690                                 xtensa_insnbuf slotbuf)
18691 {
18692   slotbuf[1] = 0;
18693   slotbuf[0] = (insn[0] & 0xffff);
18694 }
18695
18696 static void
18697 Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
18698                                 const xtensa_insnbuf slotbuf)
18699 {
18700   insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
18701 }
18702
18703 static void
18704 Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
18705                                 xtensa_insnbuf slotbuf)
18706 {
18707   slotbuf[1] = 0;
18708   slotbuf[0] = (insn[0] & 0xffff);
18709 }
18710
18711 static void
18712 Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
18713                                 const xtensa_insnbuf slotbuf)
18714 {
18715   insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
18716 }
18717
18718 static void
18719 Slot_xt_format1_Format_xt_flix64_slot0_4_get (const xtensa_insnbuf insn,
18720                                               xtensa_insnbuf slotbuf)
18721 {
18722   slotbuf[1] = 0;
18723   slotbuf[0] = ((insn[0] & 0xffffff0) >> 4);
18724 }
18725
18726 static void
18727 Slot_xt_format1_Format_xt_flix64_slot0_4_set (xtensa_insnbuf insn,
18728                                               const xtensa_insnbuf slotbuf)
18729 {
18730   insn[0] = (insn[0] & ~0xffffff0) | ((slotbuf[0] & 0xffffff) << 4);
18731 }
18732
18733 static void
18734 Slot_xt_format2_Format_xt_flix64_slot0_4_get (const xtensa_insnbuf insn,
18735                                               xtensa_insnbuf slotbuf)
18736 {
18737   slotbuf[1] = 0;
18738   slotbuf[0] = ((insn[0] & 0xffffff0) >> 4);
18739 }
18740
18741 static void
18742 Slot_xt_format2_Format_xt_flix64_slot0_4_set (xtensa_insnbuf insn,
18743                                               const xtensa_insnbuf slotbuf)
18744 {
18745   insn[0] = (insn[0] & ~0xffffff0) | ((slotbuf[0] & 0xffffff) << 4);
18746 }
18747
18748 static void
18749 Slot_xt_format1_Format_xt_flix64_slot1_28_get (const xtensa_insnbuf insn,
18750                                               xtensa_insnbuf slotbuf)
18751 {
18752   slotbuf[1] = 0;
18753   slotbuf[0] = ((insn[0] & 0xf0000000) >> 28);
18754   slotbuf[0] = (slotbuf[0] & ~0xffff0) | ((insn[1] & 0xffff) << 4);
18755 }
18756
18757 static void
18758 Slot_xt_format1_Format_xt_flix64_slot1_28_set (xtensa_insnbuf insn,
18759                                               const xtensa_insnbuf slotbuf)
18760 {
18761   insn[0] = (insn[0] & ~0xf0000000) | ((slotbuf[0] & 0xf) << 28);
18762   insn[1] = (insn[1] & ~0xffff) | ((slotbuf[0] & 0xffff0) >> 4);
18763 }
18764
18765 static void
18766 Slot_xt_format1_Format_xt_flix64_slot2_48_get (const xtensa_insnbuf insn,
18767                                               xtensa_insnbuf slotbuf)
18768 {
18769   slotbuf[1] = 0;
18770   slotbuf[0] = ((insn[1] & 0xffff0000) >> 16);
18771 }
18772
18773 static void
18774 Slot_xt_format1_Format_xt_flix64_slot2_48_set (xtensa_insnbuf insn,
18775                                               const xtensa_insnbuf slotbuf)
18776 {
18777   insn[1] = (insn[1] & ~0xffff0000) | ((slotbuf[0] & 0xffff) << 16);
18778 }
18779
18780 static void
18781 Slot_xt_format2_Format_xt_flix64_slot3_28_get (const xtensa_insnbuf insn,
18782                                               xtensa_insnbuf slotbuf)
18783 {
18784   slotbuf[0] = ((insn[0] & 0xf0000000) >> 28);
18785   slotbuf[0] = (slotbuf[0] & ~0xfffffff0) | ((insn[1] & 0xfffffff) << 4);
18786   slotbuf[1] = ((insn[1] & 0x70000000) >> 28);
18787 }
18788
18789 static void
18790 Slot_xt_format2_Format_xt_flix64_slot3_28_set (xtensa_insnbuf insn,
18791                                               const xtensa_insnbuf slotbuf)
18792 {
18793   insn[0] = (insn[0] & ~0xf0000000) | ((slotbuf[0] & 0xf) << 28);
18794   insn[1] = (insn[1] & ~0xfffffff) | ((slotbuf[0] & 0xfffffff0) >> 4);
18795   insn[1] = (insn[1] & ~0x70000000) | ((slotbuf[1] & 0x7) << 28);
18796 }
18797
18798 static const xtensa_get_field_fn
18799 Slot_inst_get_field_fns[] = {
18800   Field_t_Slot_inst_get,
18801   Field_bbi4_Slot_inst_get,
18802   Field_bbi_Slot_inst_get,
18803   Field_imm12_Slot_inst_get,
18804   Field_imm8_Slot_inst_get,
18805   Field_s_Slot_inst_get,
18806   Field_imm12b_Slot_inst_get,
18807   Field_imm16_Slot_inst_get,
18808   Field_m_Slot_inst_get,
18809   Field_n_Slot_inst_get,
18810   Field_offset_Slot_inst_get,
18811   Field_op0_Slot_inst_get,
18812   Field_op1_Slot_inst_get,
18813   Field_op2_Slot_inst_get,
18814   Field_r_Slot_inst_get,
18815   Field_sa4_Slot_inst_get,
18816   Field_sae4_Slot_inst_get,
18817   Field_sae_Slot_inst_get,
18818   Field_sal_Slot_inst_get,
18819   Field_sargt_Slot_inst_get,
18820   Field_sas4_Slot_inst_get,
18821   Field_sas_Slot_inst_get,
18822   Field_sr_Slot_inst_get,
18823   Field_st_Slot_inst_get,
18824   Field_thi3_Slot_inst_get,
18825   Field_imm4_Slot_inst_get,
18826   Field_mn_Slot_inst_get,
18827   0,
18828   0,
18829   0,
18830   0,
18831   0,
18832   0,
18833   0,
18834   0,
18835   Field_r3_Slot_inst_get,
18836   Field_rbit2_Slot_inst_get,
18837   Field_rhi_Slot_inst_get,
18838   Field_t3_Slot_inst_get,
18839   Field_tbit2_Slot_inst_get,
18840   Field_tlo_Slot_inst_get,
18841   Field_w_Slot_inst_get,
18842   Field_y_Slot_inst_get,
18843   Field_x_Slot_inst_get,
18844   Field_t2_Slot_inst_get,
18845   Field_s2_Slot_inst_get,
18846   Field_r2_Slot_inst_get,
18847   Field_t4_Slot_inst_get,
18848   Field_s4_Slot_inst_get,
18849   Field_r4_Slot_inst_get,
18850   Field_t8_Slot_inst_get,
18851   Field_s8_Slot_inst_get,
18852   Field_r8_Slot_inst_get,
18853   Field_xt_wbr15_imm_Slot_inst_get,
18854   Field_xt_wbr18_imm_Slot_inst_get,
18855   0,
18856   0,
18857   0,
18858   0,
18859   0,
18860   0,
18861   0,
18862   0,
18863   0,
18864   0,
18865   0,
18866   0,
18867   0,
18868   0,
18869   0,
18870   0,
18871   0,
18872   0,
18873   0,
18874   0,
18875   0,
18876   0,
18877   0,
18878   0,
18879   0,
18880   0,
18881   0,
18882   0,
18883   0,
18884   0,
18885   0,
18886   0,
18887   0,
18888   0,
18889   0,
18890   0,
18891   0,
18892   0,
18893   0,
18894   0,
18895   0,
18896   0,
18897   0,
18898   0,
18899   0,
18900   0,
18901   0,
18902   0,
18903   0,
18904   0,
18905   0,
18906   0,
18907   0,
18908   0,
18909   0,
18910   0,
18911   0,
18912   0,
18913   0,
18914   0,
18915   0,
18916   0,
18917   0,
18918   0,
18919   0,
18920   0,
18921   0,
18922   0,
18923   Implicit_Field_ar0_get,
18924   Implicit_Field_ar4_get,
18925   Implicit_Field_ar8_get,
18926   Implicit_Field_ar12_get,
18927   Implicit_Field_mr0_get,
18928   Implicit_Field_mr1_get,
18929   Implicit_Field_mr2_get,
18930   Implicit_Field_mr3_get,
18931   Implicit_Field_bt16_get,
18932   Implicit_Field_bs16_get,
18933   Implicit_Field_br16_get,
18934   Implicit_Field_brall_get
18935 };
18936
18937 static const xtensa_set_field_fn
18938 Slot_inst_set_field_fns[] = {
18939   Field_t_Slot_inst_set,
18940   Field_bbi4_Slot_inst_set,
18941   Field_bbi_Slot_inst_set,
18942   Field_imm12_Slot_inst_set,
18943   Field_imm8_Slot_inst_set,
18944   Field_s_Slot_inst_set,
18945   Field_imm12b_Slot_inst_set,
18946   Field_imm16_Slot_inst_set,
18947   Field_m_Slot_inst_set,
18948   Field_n_Slot_inst_set,
18949   Field_offset_Slot_inst_set,
18950   Field_op0_Slot_inst_set,
18951   Field_op1_Slot_inst_set,
18952   Field_op2_Slot_inst_set,
18953   Field_r_Slot_inst_set,
18954   Field_sa4_Slot_inst_set,
18955   Field_sae4_Slot_inst_set,
18956   Field_sae_Slot_inst_set,
18957   Field_sal_Slot_inst_set,
18958   Field_sargt_Slot_inst_set,
18959   Field_sas4_Slot_inst_set,
18960   Field_sas_Slot_inst_set,
18961   Field_sr_Slot_inst_set,
18962   Field_st_Slot_inst_set,
18963   Field_thi3_Slot_inst_set,
18964   Field_imm4_Slot_inst_set,
18965   Field_mn_Slot_inst_set,
18966   0,
18967   0,
18968   0,
18969   0,
18970   0,
18971   0,
18972   0,
18973   0,
18974   Field_r3_Slot_inst_set,
18975   Field_rbit2_Slot_inst_set,
18976   Field_rhi_Slot_inst_set,
18977   Field_t3_Slot_inst_set,
18978   Field_tbit2_Slot_inst_set,
18979   Field_tlo_Slot_inst_set,
18980   Field_w_Slot_inst_set,
18981   Field_y_Slot_inst_set,
18982   Field_x_Slot_inst_set,
18983   Field_t2_Slot_inst_set,
18984   Field_s2_Slot_inst_set,
18985   Field_r2_Slot_inst_set,
18986   Field_t4_Slot_inst_set,
18987   Field_s4_Slot_inst_set,
18988   Field_r4_Slot_inst_set,
18989   Field_t8_Slot_inst_set,
18990   Field_s8_Slot_inst_set,
18991   Field_r8_Slot_inst_set,
18992   Field_xt_wbr15_imm_Slot_inst_set,
18993   Field_xt_wbr18_imm_Slot_inst_set,
18994   0,
18995   0,
18996   0,
18997   0,
18998   0,
18999   0,
19000   0,
19001   0,
19002   0,
19003   0,
19004   0,
19005   0,
19006   0,
19007   0,
19008   0,
19009   0,
19010   0,
19011   0,
19012   0,
19013   0,
19014   0,
19015   0,
19016   0,
19017   0,
19018   0,
19019   0,
19020   0,
19021   0,
19022   0,
19023   0,
19024   0,
19025   0,
19026   0,
19027   0,
19028   0,
19029   0,
19030   0,
19031   0,
19032   0,
19033   0,
19034   0,
19035   0,
19036   0,
19037   0,
19038   0,
19039   0,
19040   0,
19041   0,
19042   0,
19043   0,
19044   0,
19045   0,
19046   0,
19047   0,
19048   0,
19049   0,
19050   0,
19051   0,
19052   0,
19053   0,
19054   0,
19055   0,
19056   0,
19057   0,
19058   0,
19059   0,
19060   0,
19061   0,
19062   Implicit_Field_set,
19063   Implicit_Field_set,
19064   Implicit_Field_set,
19065   Implicit_Field_set,
19066   Implicit_Field_set,
19067   Implicit_Field_set,
19068   Implicit_Field_set,
19069   Implicit_Field_set,
19070   Implicit_Field_set,
19071   Implicit_Field_set,
19072   Implicit_Field_set,
19073   Implicit_Field_set
19074 };
19075
19076 static const xtensa_get_field_fn
19077 Slot_inst16a_get_field_fns[] = {
19078   Field_t_Slot_inst16a_get,
19079   0,
19080   0,
19081   0,
19082   0,
19083   Field_s_Slot_inst16a_get,
19084   0,
19085   0,
19086   0,
19087   0,
19088   0,
19089   Field_op0_Slot_inst16a_get,
19090   0,
19091   0,
19092   Field_r_Slot_inst16a_get,
19093   0,
19094   0,
19095   0,
19096   0,
19097   0,
19098   0,
19099   0,
19100   Field_sr_Slot_inst16a_get,
19101   Field_st_Slot_inst16a_get,
19102   0,
19103   Field_imm4_Slot_inst16a_get,
19104   0,
19105   Field_i_Slot_inst16a_get,
19106   Field_imm6lo_Slot_inst16a_get,
19107   Field_imm6hi_Slot_inst16a_get,
19108   Field_imm7lo_Slot_inst16a_get,
19109   Field_imm7hi_Slot_inst16a_get,
19110   Field_z_Slot_inst16a_get,
19111   Field_imm6_Slot_inst16a_get,
19112   Field_imm7_Slot_inst16a_get,
19113   0,
19114   0,
19115   0,
19116   0,
19117   0,
19118   0,
19119   0,
19120   0,
19121   0,
19122   Field_t2_Slot_inst16a_get,
19123   Field_s2_Slot_inst16a_get,
19124   Field_r2_Slot_inst16a_get,
19125   Field_t4_Slot_inst16a_get,
19126   Field_s4_Slot_inst16a_get,
19127   Field_r4_Slot_inst16a_get,
19128   Field_t8_Slot_inst16a_get,
19129   Field_s8_Slot_inst16a_get,
19130   Field_r8_Slot_inst16a_get,
19131   0,
19132   0,
19133   0,
19134   0,
19135   0,
19136   0,
19137   0,
19138   0,
19139   0,
19140   0,
19141   0,
19142   0,
19143   0,
19144   0,
19145   0,
19146   0,
19147   0,
19148   0,
19149   0,
19150   0,
19151   0,
19152   0,
19153   0,
19154   0,
19155   0,
19156   0,
19157   0,
19158   0,
19159   0,
19160   0,
19161   0,
19162   0,
19163   0,
19164   0,
19165   0,
19166   0,
19167   0,
19168   0,
19169   0,
19170   0,
19171   0,
19172   0,
19173   0,
19174   0,
19175   0,
19176   0,
19177   0,
19178   0,
19179   0,
19180   0,
19181   0,
19182   0,
19183   0,
19184   0,
19185   0,
19186   0,
19187   0,
19188   0,
19189   0,
19190   0,
19191   0,
19192   0,
19193   0,
19194   0,
19195   0,
19196   0,
19197   0,
19198   0,
19199   0,
19200   0,
19201   Implicit_Field_ar0_get,
19202   Implicit_Field_ar4_get,
19203   Implicit_Field_ar8_get,
19204   Implicit_Field_ar12_get,
19205   Implicit_Field_mr0_get,
19206   Implicit_Field_mr1_get,
19207   Implicit_Field_mr2_get,
19208   Implicit_Field_mr3_get,
19209   Implicit_Field_bt16_get,
19210   Implicit_Field_bs16_get,
19211   Implicit_Field_br16_get,
19212   Implicit_Field_brall_get
19213 };
19214
19215 static const xtensa_set_field_fn
19216 Slot_inst16a_set_field_fns[] = {
19217   Field_t_Slot_inst16a_set,
19218   0,
19219   0,
19220   0,
19221   0,
19222   Field_s_Slot_inst16a_set,
19223   0,
19224   0,
19225   0,
19226   0,
19227   0,
19228   Field_op0_Slot_inst16a_set,
19229   0,
19230   0,
19231   Field_r_Slot_inst16a_set,
19232   0,
19233   0,
19234   0,
19235   0,
19236   0,
19237   0,
19238   0,
19239   Field_sr_Slot_inst16a_set,
19240   Field_st_Slot_inst16a_set,
19241   0,
19242   Field_imm4_Slot_inst16a_set,
19243   0,
19244   Field_i_Slot_inst16a_set,
19245   Field_imm6lo_Slot_inst16a_set,
19246   Field_imm6hi_Slot_inst16a_set,
19247   Field_imm7lo_Slot_inst16a_set,
19248   Field_imm7hi_Slot_inst16a_set,
19249   Field_z_Slot_inst16a_set,
19250   Field_imm6_Slot_inst16a_set,
19251   Field_imm7_Slot_inst16a_set,
19252   0,
19253   0,
19254   0,
19255   0,
19256   0,
19257   0,
19258   0,
19259   0,
19260   0,
19261   Field_t2_Slot_inst16a_set,
19262   Field_s2_Slot_inst16a_set,
19263   Field_r2_Slot_inst16a_set,
19264   Field_t4_Slot_inst16a_set,
19265   Field_s4_Slot_inst16a_set,
19266   Field_r4_Slot_inst16a_set,
19267   Field_t8_Slot_inst16a_set,
19268   Field_s8_Slot_inst16a_set,
19269   Field_r8_Slot_inst16a_set,
19270   0,
19271   0,
19272   0,
19273   0,
19274   0,
19275   0,
19276   0,
19277   0,
19278   0,
19279   0,
19280   0,
19281   0,
19282   0,
19283   0,
19284   0,
19285   0,
19286   0,
19287   0,
19288   0,
19289   0,
19290   0,
19291   0,
19292   0,
19293   0,
19294   0,
19295   0,
19296   0,
19297   0,
19298   0,
19299   0,
19300   0,
19301   0,
19302   0,
19303   0,
19304   0,
19305   0,
19306   0,
19307   0,
19308   0,
19309   0,
19310   0,
19311   0,
19312   0,
19313   0,
19314   0,
19315   0,
19316   0,
19317   0,
19318   0,
19319   0,
19320   0,
19321   0,
19322   0,
19323   0,
19324   0,
19325   0,
19326   0,
19327   0,
19328   0,
19329   0,
19330   0,
19331   0,
19332   0,
19333   0,
19334   0,
19335   0,
19336   0,
19337   0,
19338   0,
19339   0,
19340   Implicit_Field_set,
19341   Implicit_Field_set,
19342   Implicit_Field_set,
19343   Implicit_Field_set,
19344   Implicit_Field_set,
19345   Implicit_Field_set,
19346   Implicit_Field_set,
19347   Implicit_Field_set,
19348   Implicit_Field_set,
19349   Implicit_Field_set,
19350   Implicit_Field_set,
19351   Implicit_Field_set
19352 };
19353
19354 static const xtensa_get_field_fn
19355 Slot_inst16b_get_field_fns[] = {
19356   Field_t_Slot_inst16b_get,
19357   0,
19358   0,
19359   0,
19360   0,
19361   Field_s_Slot_inst16b_get,
19362   0,
19363   0,
19364   0,
19365   0,
19366   0,
19367   Field_op0_Slot_inst16b_get,
19368   0,
19369   0,
19370   Field_r_Slot_inst16b_get,
19371   0,
19372   0,
19373   0,
19374   0,
19375   0,
19376   0,
19377   0,
19378   Field_sr_Slot_inst16b_get,
19379   Field_st_Slot_inst16b_get,
19380   0,
19381   Field_imm4_Slot_inst16b_get,
19382   0,
19383   Field_i_Slot_inst16b_get,
19384   Field_imm6lo_Slot_inst16b_get,
19385   Field_imm6hi_Slot_inst16b_get,
19386   Field_imm7lo_Slot_inst16b_get,
19387   Field_imm7hi_Slot_inst16b_get,
19388   Field_z_Slot_inst16b_get,
19389   Field_imm6_Slot_inst16b_get,
19390   Field_imm7_Slot_inst16b_get,
19391   0,
19392   0,
19393   0,
19394   0,
19395   0,
19396   0,
19397   0,
19398   0,
19399   0,
19400   Field_t2_Slot_inst16b_get,
19401   Field_s2_Slot_inst16b_get,
19402   Field_r2_Slot_inst16b_get,
19403   Field_t4_Slot_inst16b_get,
19404   Field_s4_Slot_inst16b_get,
19405   Field_r4_Slot_inst16b_get,
19406   Field_t8_Slot_inst16b_get,
19407   Field_s8_Slot_inst16b_get,
19408   Field_r8_Slot_inst16b_get,
19409   0,
19410   0,
19411   0,
19412   0,
19413   0,
19414   0,
19415   0,
19416   0,
19417   0,
19418   0,
19419   0,
19420   0,
19421   0,
19422   0,
19423   0,
19424   0,
19425   0,
19426   0,
19427   0,
19428   0,
19429   0,
19430   0,
19431   0,
19432   0,
19433   0,
19434   0,
19435   0,
19436   0,
19437   0,
19438   0,
19439   0,
19440   0,
19441   0,
19442   0,
19443   0,
19444   0,
19445   0,
19446   0,
19447   0,
19448   0,
19449   0,
19450   0,
19451   0,
19452   0,
19453   0,
19454   0,
19455   0,
19456   0,
19457   0,
19458   0,
19459   0,
19460   0,
19461   0,
19462   0,
19463   0,
19464   0,
19465   0,
19466   0,
19467   0,
19468   0,
19469   0,
19470   0,
19471   0,
19472   0,
19473   0,
19474   0,
19475   0,
19476   0,
19477   0,
19478   0,
19479   Implicit_Field_ar0_get,
19480   Implicit_Field_ar4_get,
19481   Implicit_Field_ar8_get,
19482   Implicit_Field_ar12_get,
19483   Implicit_Field_mr0_get,
19484   Implicit_Field_mr1_get,
19485   Implicit_Field_mr2_get,
19486   Implicit_Field_mr3_get,
19487   Implicit_Field_bt16_get,
19488   Implicit_Field_bs16_get,
19489   Implicit_Field_br16_get,
19490   Implicit_Field_brall_get
19491 };
19492
19493 static const xtensa_set_field_fn
19494 Slot_inst16b_set_field_fns[] = {
19495   Field_t_Slot_inst16b_set,
19496   0,
19497   0,
19498   0,
19499   0,
19500   Field_s_Slot_inst16b_set,
19501   0,
19502   0,
19503   0,
19504   0,
19505   0,
19506   Field_op0_Slot_inst16b_set,
19507   0,
19508   0,
19509   Field_r_Slot_inst16b_set,
19510   0,
19511   0,
19512   0,
19513   0,
19514   0,
19515   0,
19516   0,
19517   Field_sr_Slot_inst16b_set,
19518   Field_st_Slot_inst16b_set,
19519   0,
19520   Field_imm4_Slot_inst16b_set,
19521   0,
19522   Field_i_Slot_inst16b_set,
19523   Field_imm6lo_Slot_inst16b_set,
19524   Field_imm6hi_Slot_inst16b_set,
19525   Field_imm7lo_Slot_inst16b_set,
19526   Field_imm7hi_Slot_inst16b_set,
19527   Field_z_Slot_inst16b_set,
19528   Field_imm6_Slot_inst16b_set,
19529   Field_imm7_Slot_inst16b_set,
19530   0,
19531   0,
19532   0,
19533   0,
19534   0,
19535   0,
19536   0,
19537   0,
19538   0,
19539   Field_t2_Slot_inst16b_set,
19540   Field_s2_Slot_inst16b_set,
19541   Field_r2_Slot_inst16b_set,
19542   Field_t4_Slot_inst16b_set,
19543   Field_s4_Slot_inst16b_set,
19544   Field_r4_Slot_inst16b_set,
19545   Field_t8_Slot_inst16b_set,
19546   Field_s8_Slot_inst16b_set,
19547   Field_r8_Slot_inst16b_set,
19548   0,
19549   0,
19550   0,
19551   0,
19552   0,
19553   0,
19554   0,
19555   0,
19556   0,
19557   0,
19558   0,
19559   0,
19560   0,
19561   0,
19562   0,
19563   0,
19564   0,
19565   0,
19566   0,
19567   0,
19568   0,
19569   0,
19570   0,
19571   0,
19572   0,
19573   0,
19574   0,
19575   0,
19576   0,
19577   0,
19578   0,
19579   0,
19580   0,
19581   0,
19582   0,
19583   0,
19584   0,
19585   0,
19586   0,
19587   0,
19588   0,
19589   0,
19590   0,
19591   0,
19592   0,
19593   0,
19594   0,
19595   0,
19596   0,
19597   0,
19598   0,
19599   0,
19600   0,
19601   0,
19602   0,
19603   0,
19604   0,
19605   0,
19606   0,
19607   0,
19608   0,
19609   0,
19610   0,
19611   0,
19612   0,
19613   0,
19614   0,
19615   0,
19616   0,
19617   0,
19618   Implicit_Field_set,
19619   Implicit_Field_set,
19620   Implicit_Field_set,
19621   Implicit_Field_set,
19622   Implicit_Field_set,
19623   Implicit_Field_set,
19624   Implicit_Field_set,
19625   Implicit_Field_set,
19626   Implicit_Field_set,
19627   Implicit_Field_set,
19628   Implicit_Field_set,
19629   Implicit_Field_set
19630 };
19631
19632 static const xtensa_get_field_fn
19633 Slot_xt_flix64_slot0_get_field_fns[] = {
19634   Field_t_Slot_xt_flix64_slot0_get,
19635   0,
19636   0,
19637   0,
19638   Field_imm8_Slot_xt_flix64_slot0_get,
19639   Field_s_Slot_xt_flix64_slot0_get,
19640   Field_imm12b_Slot_xt_flix64_slot0_get,
19641   Field_imm16_Slot_xt_flix64_slot0_get,
19642   Field_m_Slot_xt_flix64_slot0_get,
19643   Field_n_Slot_xt_flix64_slot0_get,
19644   0,
19645   0,
19646   Field_op1_Slot_xt_flix64_slot0_get,
19647   Field_op2_Slot_xt_flix64_slot0_get,
19648   Field_r_Slot_xt_flix64_slot0_get,
19649   0,
19650   Field_sae4_Slot_xt_flix64_slot0_get,
19651   Field_sae_Slot_xt_flix64_slot0_get,
19652   Field_sal_Slot_xt_flix64_slot0_get,
19653   Field_sargt_Slot_xt_flix64_slot0_get,
19654   0,
19655   Field_sas_Slot_xt_flix64_slot0_get,
19656   0,
19657   0,
19658   Field_thi3_Slot_xt_flix64_slot0_get,
19659   0,
19660   0,
19661   0,
19662   0,
19663   0,
19664   0,
19665   0,
19666   0,
19667   0,
19668   0,
19669   0,
19670   0,
19671   0,
19672   0,
19673   0,
19674   0,
19675   0,
19676   0,
19677   0,
19678   0,
19679   0,
19680   0,
19681   0,
19682   0,
19683   0,
19684   0,
19685   0,
19686   0,
19687   0,
19688   0,
19689   Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get,
19690   Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get,
19691   Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get,
19692   Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get,
19693   Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get,
19694   Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get,
19695   0,
19696   0,
19697   0,
19698   0,
19699   0,
19700   0,
19701   0,
19702   0,
19703   0,
19704   0,
19705   0,
19706   0,
19707   0,
19708   0,
19709   0,
19710   0,
19711   0,
19712   0,
19713   0,
19714   0,
19715   0,
19716   0,
19717   0,
19718   0,
19719   0,
19720   0,
19721   0,
19722   0,
19723   0,
19724   0,
19725   0,
19726   0,
19727   0,
19728   0,
19729   0,
19730   0,
19731   0,
19732   0,
19733   0,
19734   0,
19735   0,
19736   0,
19737   0,
19738   0,
19739   0,
19740   0,
19741   0,
19742   0,
19743   0,
19744   0,
19745   0,
19746   0,
19747   0,
19748   0,
19749   0,
19750   0,
19751   0,
19752   0,
19753   0,
19754   0,
19755   0,
19756   Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get,
19757   Implicit_Field_ar0_get,
19758   Implicit_Field_ar4_get,
19759   Implicit_Field_ar8_get,
19760   Implicit_Field_ar12_get,
19761   Implicit_Field_mr0_get,
19762   Implicit_Field_mr1_get,
19763   Implicit_Field_mr2_get,
19764   Implicit_Field_mr3_get,
19765   Implicit_Field_bt16_get,
19766   Implicit_Field_bs16_get,
19767   Implicit_Field_br16_get,
19768   Implicit_Field_brall_get
19769 };
19770
19771 static const xtensa_set_field_fn
19772 Slot_xt_flix64_slot0_set_field_fns[] = {
19773   Field_t_Slot_xt_flix64_slot0_set,
19774   0,
19775   0,
19776   0,
19777   Field_imm8_Slot_xt_flix64_slot0_set,
19778   Field_s_Slot_xt_flix64_slot0_set,
19779   Field_imm12b_Slot_xt_flix64_slot0_set,
19780   Field_imm16_Slot_xt_flix64_slot0_set,
19781   Field_m_Slot_xt_flix64_slot0_set,
19782   Field_n_Slot_xt_flix64_slot0_set,
19783   0,
19784   0,
19785   Field_op1_Slot_xt_flix64_slot0_set,
19786   Field_op2_Slot_xt_flix64_slot0_set,
19787   Field_r_Slot_xt_flix64_slot0_set,
19788   0,
19789   Field_sae4_Slot_xt_flix64_slot0_set,
19790   Field_sae_Slot_xt_flix64_slot0_set,
19791   Field_sal_Slot_xt_flix64_slot0_set,
19792   Field_sargt_Slot_xt_flix64_slot0_set,
19793   0,
19794   Field_sas_Slot_xt_flix64_slot0_set,
19795   0,
19796   0,
19797   Field_thi3_Slot_xt_flix64_slot0_set,
19798   0,
19799   0,
19800   0,
19801   0,
19802   0,
19803   0,
19804   0,
19805   0,
19806   0,
19807   0,
19808   0,
19809   0,
19810   0,
19811   0,
19812   0,
19813   0,
19814   0,
19815   0,
19816   0,
19817   0,
19818   0,
19819   0,
19820   0,
19821   0,
19822   0,
19823   0,
19824   0,
19825   0,
19826   0,
19827   0,
19828   Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_set,
19829   Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_set,
19830   Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_set,
19831   Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_set,
19832   Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_set,
19833   Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_set,
19834   0,
19835   0,
19836   0,
19837   0,
19838   0,
19839   0,
19840   0,
19841   0,
19842   0,
19843   0,
19844   0,
19845   0,
19846   0,
19847   0,
19848   0,
19849   0,
19850   0,
19851   0,
19852   0,
19853   0,
19854   0,
19855   0,
19856   0,
19857   0,
19858   0,
19859   0,
19860   0,
19861   0,
19862   0,
19863   0,
19864   0,
19865   0,
19866   0,
19867   0,
19868   0,
19869   0,
19870   0,
19871   0,
19872   0,
19873   0,
19874   0,
19875   0,
19876   0,
19877   0,
19878   0,
19879   0,
19880   0,
19881   0,
19882   0,
19883   0,
19884   0,
19885   0,
19886   0,
19887   0,
19888   0,
19889   0,
19890   0,
19891   0,
19892   0,
19893   0,
19894   0,
19895   Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_set,
19896   Implicit_Field_set,
19897   Implicit_Field_set,
19898   Implicit_Field_set,
19899   Implicit_Field_set,
19900   Implicit_Field_set,
19901   Implicit_Field_set,
19902   Implicit_Field_set,
19903   Implicit_Field_set,
19904   Implicit_Field_set,
19905   Implicit_Field_set,
19906   Implicit_Field_set,
19907   Implicit_Field_set
19908 };
19909
19910 static const xtensa_get_field_fn
19911 Slot_xt_flix64_slot1_get_field_fns[] = {
19912   Field_t_Slot_xt_flix64_slot1_get,
19913   0,
19914   0,
19915   0,
19916   Field_imm8_Slot_xt_flix64_slot1_get,
19917   Field_s_Slot_xt_flix64_slot1_get,
19918   Field_imm12b_Slot_xt_flix64_slot1_get,
19919   0,
19920   0,
19921   0,
19922   Field_offset_Slot_xt_flix64_slot1_get,
19923   0,
19924   0,
19925   Field_op2_Slot_xt_flix64_slot1_get,
19926   Field_r_Slot_xt_flix64_slot1_get,
19927   0,
19928   0,
19929   Field_sae_Slot_xt_flix64_slot1_get,
19930   Field_sal_Slot_xt_flix64_slot1_get,
19931   Field_sargt_Slot_xt_flix64_slot1_get,
19932   0,
19933   0,
19934   0,
19935   0,
19936   0,
19937   0,
19938   0,
19939   0,
19940   0,
19941   0,
19942   0,
19943   0,
19944   0,
19945   0,
19946   0,
19947   0,
19948   0,
19949   0,
19950   0,
19951   0,
19952   0,
19953   0,
19954   0,
19955   0,
19956   0,
19957   0,
19958   0,
19959   0,
19960   0,
19961   0,
19962   0,
19963   0,
19964   0,
19965   0,
19966   0,
19967   0,
19968   0,
19969   0,
19970   0,
19971   0,
19972   0,
19973   Field_op0_s4_Slot_xt_flix64_slot1_get,
19974   Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get,
19975   Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get,
19976   Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get,
19977   Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get,
19978   Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get,
19979   Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get,
19980   Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get,
19981   Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get,
19982   Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get,
19983   Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get,
19984   Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get,
19985   Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get,
19986   Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get,
19987   Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get,
19988   Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get,
19989   Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get,
19990   Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get,
19991   Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get,
19992   Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get,
19993   Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get,
19994   Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get,
19995   0,
19996   0,
19997   0,
19998   0,
19999   0,
20000   0,
20001   0,
20002   0,
20003   0,
20004   0,
20005   0,
20006   0,
20007   0,
20008   0,
20009   0,
20010   0,
20011   0,
20012   0,
20013   0,
20014   0,
20015   0,
20016   0,
20017   0,
20018   0,
20019   0,
20020   0,
20021   0,
20022   0,
20023   0,
20024   0,
20025   0,
20026   0,
20027   0,
20028   0,
20029   0,
20030   0,
20031   0,
20032   0,
20033   0,
20034   0,
20035   Implicit_Field_ar0_get,
20036   Implicit_Field_ar4_get,
20037   Implicit_Field_ar8_get,
20038   Implicit_Field_ar12_get,
20039   Implicit_Field_mr0_get,
20040   Implicit_Field_mr1_get,
20041   Implicit_Field_mr2_get,
20042   Implicit_Field_mr3_get,
20043   Implicit_Field_bt16_get,
20044   Implicit_Field_bs16_get,
20045   Implicit_Field_br16_get,
20046   Implicit_Field_brall_get
20047 };
20048
20049 static const xtensa_set_field_fn
20050 Slot_xt_flix64_slot1_set_field_fns[] = {
20051   Field_t_Slot_xt_flix64_slot1_set,
20052   0,
20053   0,
20054   0,
20055   Field_imm8_Slot_xt_flix64_slot1_set,
20056   Field_s_Slot_xt_flix64_slot1_set,
20057   Field_imm12b_Slot_xt_flix64_slot1_set,
20058   0,
20059   0,
20060   0,
20061   Field_offset_Slot_xt_flix64_slot1_set,
20062   0,
20063   0,
20064   Field_op2_Slot_xt_flix64_slot1_set,
20065   Field_r_Slot_xt_flix64_slot1_set,
20066   0,
20067   0,
20068   Field_sae_Slot_xt_flix64_slot1_set,
20069   Field_sal_Slot_xt_flix64_slot1_set,
20070   Field_sargt_Slot_xt_flix64_slot1_set,
20071   0,
20072   0,
20073   0,
20074   0,
20075   0,
20076   0,
20077   0,
20078   0,
20079   0,
20080   0,
20081   0,
20082   0,
20083   0,
20084   0,
20085   0,
20086   0,
20087   0,
20088   0,
20089   0,
20090   0,
20091   0,
20092   0,
20093   0,
20094   0,
20095   0,
20096   0,
20097   0,
20098   0,
20099   0,
20100   0,
20101   0,
20102   0,
20103   0,
20104   0,
20105   0,
20106   0,
20107   0,
20108   0,
20109   0,
20110   0,
20111   0,
20112   Field_op0_s4_Slot_xt_flix64_slot1_set,
20113   Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_set,
20114   Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20115   Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20116   Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20117   Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20118   Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20119   Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20120   Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20121   Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20122   Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20123   Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20124   Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20125   Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20126   Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20127   Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20128   Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20129   Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20130   Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20131   Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20132   Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20133   Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20134   0,
20135   0,
20136   0,
20137   0,
20138   0,
20139   0,
20140   0,
20141   0,
20142   0,
20143   0,
20144   0,
20145   0,
20146   0,
20147   0,
20148   0,
20149   0,
20150   0,
20151   0,
20152   0,
20153   0,
20154   0,
20155   0,
20156   0,
20157   0,
20158   0,
20159   0,
20160   0,
20161   0,
20162   0,
20163   0,
20164   0,
20165   0,
20166   0,
20167   0,
20168   0,
20169   0,
20170   0,
20171   0,
20172   0,
20173   0,
20174   Implicit_Field_set,
20175   Implicit_Field_set,
20176   Implicit_Field_set,
20177   Implicit_Field_set,
20178   Implicit_Field_set,
20179   Implicit_Field_set,
20180   Implicit_Field_set,
20181   Implicit_Field_set,
20182   Implicit_Field_set,
20183   Implicit_Field_set,
20184   Implicit_Field_set,
20185   Implicit_Field_set
20186 };
20187
20188 static const xtensa_get_field_fn
20189 Slot_xt_flix64_slot2_get_field_fns[] = {
20190   Field_t_Slot_xt_flix64_slot2_get,
20191   0,
20192   0,
20193   0,
20194   0,
20195   Field_s_Slot_xt_flix64_slot2_get,
20196   0,
20197   0,
20198   0,
20199   0,
20200   0,
20201   0,
20202   0,
20203   0,
20204   Field_r_Slot_xt_flix64_slot2_get,
20205   0,
20206   0,
20207   0,
20208   0,
20209   Field_sargt_Slot_xt_flix64_slot2_get,
20210   0,
20211   0,
20212   0,
20213   0,
20214   0,
20215   0,
20216   0,
20217   0,
20218   0,
20219   0,
20220   0,
20221   0,
20222   0,
20223   0,
20224   Field_imm7_Slot_xt_flix64_slot2_get,
20225   0,
20226   0,
20227   0,
20228   0,
20229   0,
20230   0,
20231   0,
20232   0,
20233   0,
20234   0,
20235   0,
20236   0,
20237   0,
20238   0,
20239   0,
20240   0,
20241   0,
20242   0,
20243   0,
20244   0,
20245   0,
20246   0,
20247   0,
20248   0,
20249   0,
20250   0,
20251   0,
20252   0,
20253   0,
20254   0,
20255   0,
20256   0,
20257   0,
20258   0,
20259   0,
20260   0,
20261   0,
20262   0,
20263   0,
20264   0,
20265   0,
20266   0,
20267   0,
20268   0,
20269   0,
20270   0,
20271   0,
20272   0,
20273   Field_op0_s5_Slot_xt_flix64_slot2_get,
20274   Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20275   Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20276   Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20277   Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20278   Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20279   Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20280   Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20281   Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20282   Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20283   Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20284   Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20285   Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20286   Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20287   0,
20288   0,
20289   0,
20290   0,
20291   0,
20292   0,
20293   0,
20294   0,
20295   0,
20296   0,
20297   0,
20298   0,
20299   0,
20300   0,
20301   0,
20302   0,
20303   0,
20304   0,
20305   0,
20306   0,
20307   0,
20308   0,
20309   0,
20310   0,
20311   0,
20312   0,
20313   Implicit_Field_ar0_get,
20314   Implicit_Field_ar4_get,
20315   Implicit_Field_ar8_get,
20316   Implicit_Field_ar12_get,
20317   Implicit_Field_mr0_get,
20318   Implicit_Field_mr1_get,
20319   Implicit_Field_mr2_get,
20320   Implicit_Field_mr3_get,
20321   Implicit_Field_bt16_get,
20322   Implicit_Field_bs16_get,
20323   Implicit_Field_br16_get,
20324   Implicit_Field_brall_get
20325 };
20326
20327 static const xtensa_set_field_fn
20328 Slot_xt_flix64_slot2_set_field_fns[] = {
20329   Field_t_Slot_xt_flix64_slot2_set,
20330   0,
20331   0,
20332   0,
20333   0,
20334   Field_s_Slot_xt_flix64_slot2_set,
20335   0,
20336   0,
20337   0,
20338   0,
20339   0,
20340   0,
20341   0,
20342   0,
20343   Field_r_Slot_xt_flix64_slot2_set,
20344   0,
20345   0,
20346   0,
20347   0,
20348   Field_sargt_Slot_xt_flix64_slot2_set,
20349   0,
20350   0,
20351   0,
20352   0,
20353   0,
20354   0,
20355   0,
20356   0,
20357   0,
20358   0,
20359   0,
20360   0,
20361   0,
20362   0,
20363   Field_imm7_Slot_xt_flix64_slot2_set,
20364   0,
20365   0,
20366   0,
20367   0,
20368   0,
20369   0,
20370   0,
20371   0,
20372   0,
20373   0,
20374   0,
20375   0,
20376   0,
20377   0,
20378   0,
20379   0,
20380   0,
20381   0,
20382   0,
20383   0,
20384   0,
20385   0,
20386   0,
20387   0,
20388   0,
20389   0,
20390   0,
20391   0,
20392   0,
20393   0,
20394   0,
20395   0,
20396   0,
20397   0,
20398   0,
20399   0,
20400   0,
20401   0,
20402   0,
20403   0,
20404   0,
20405   0,
20406   0,
20407   0,
20408   0,
20409   0,
20410   0,
20411   0,
20412   Field_op0_s5_Slot_xt_flix64_slot2_set,
20413   Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20414   Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20415   Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20416   Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20417   Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20418   Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20419   Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20420   Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20421   Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20422   Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20423   Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20424   Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20425   Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20426   0,
20427   0,
20428   0,
20429   0,
20430   0,
20431   0,
20432   0,
20433   0,
20434   0,
20435   0,
20436   0,
20437   0,
20438   0,
20439   0,
20440   0,
20441   0,
20442   0,
20443   0,
20444   0,
20445   0,
20446   0,
20447   0,
20448   0,
20449   0,
20450   0,
20451   0,
20452   Implicit_Field_set,
20453   Implicit_Field_set,
20454   Implicit_Field_set,
20455   Implicit_Field_set,
20456   Implicit_Field_set,
20457   Implicit_Field_set,
20458   Implicit_Field_set,
20459   Implicit_Field_set,
20460   Implicit_Field_set,
20461   Implicit_Field_set,
20462   Implicit_Field_set,
20463   Implicit_Field_set
20464 };
20465
20466 static const xtensa_get_field_fn
20467 Slot_xt_flix64_slot3_get_field_fns[] = {
20468   Field_t_Slot_xt_flix64_slot3_get,
20469   0,
20470   Field_bbi_Slot_xt_flix64_slot3_get,
20471   0,
20472   0,
20473   Field_s_Slot_xt_flix64_slot3_get,
20474   0,
20475   0,
20476   0,
20477   0,
20478   0,
20479   0,
20480   0,
20481   0,
20482   Field_r_Slot_xt_flix64_slot3_get,
20483   0,
20484   0,
20485   0,
20486   0,
20487   0,
20488   0,
20489   0,
20490   0,
20491   0,
20492   0,
20493   0,
20494   0,
20495   0,
20496   0,
20497   0,
20498   0,
20499   0,
20500   0,
20501   0,
20502   0,
20503   0,
20504   0,
20505   0,
20506   0,
20507   0,
20508   0,
20509   0,
20510   0,
20511   0,
20512   0,
20513   0,
20514   0,
20515   0,
20516   0,
20517   0,
20518   0,
20519   0,
20520   0,
20521   0,
20522   Field_xt_wbr18_imm_Slot_xt_flix64_slot3_get,
20523   0,
20524   0,
20525   0,
20526   0,
20527   0,
20528   0,
20529   0,
20530   0,
20531   0,
20532   0,
20533   0,
20534   0,
20535   0,
20536   0,
20537   0,
20538   0,
20539   0,
20540   0,
20541   0,
20542   0,
20543   0,
20544   0,
20545   0,
20546   0,
20547   0,
20548   0,
20549   0,
20550   0,
20551   0,
20552   0,
20553   0,
20554   0,
20555   0,
20556   0,
20557   0,
20558   0,
20559   0,
20560   0,
20561   0,
20562   0,
20563   0,
20564   0,
20565   Field_op0_s6_Slot_xt_flix64_slot3_get,
20566   Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20567   Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get,
20568   Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20569   Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20570   Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20571   Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20572   Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20573   Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20574   Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20575   Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20576   Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20577   Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20578   Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20579   Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20580   Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20581   Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20582   Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20583   Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20584   Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20585   Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20586   Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20587   Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20588   Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20589   Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20590   0,
20591   Implicit_Field_ar0_get,
20592   Implicit_Field_ar4_get,
20593   Implicit_Field_ar8_get,
20594   Implicit_Field_ar12_get,
20595   Implicit_Field_mr0_get,
20596   Implicit_Field_mr1_get,
20597   Implicit_Field_mr2_get,
20598   Implicit_Field_mr3_get,
20599   Implicit_Field_bt16_get,
20600   Implicit_Field_bs16_get,
20601   Implicit_Field_br16_get,
20602   Implicit_Field_brall_get
20603 };
20604
20605 static const xtensa_set_field_fn
20606 Slot_xt_flix64_slot3_set_field_fns[] = {
20607   Field_t_Slot_xt_flix64_slot3_set,
20608   0,
20609   Field_bbi_Slot_xt_flix64_slot3_set,
20610   0,
20611   0,
20612   Field_s_Slot_xt_flix64_slot3_set,
20613   0,
20614   0,
20615   0,
20616   0,
20617   0,
20618   0,
20619   0,
20620   0,
20621   Field_r_Slot_xt_flix64_slot3_set,
20622   0,
20623   0,
20624   0,
20625   0,
20626   0,
20627   0,
20628   0,
20629   0,
20630   0,
20631   0,
20632   0,
20633   0,
20634   0,
20635   0,
20636   0,
20637   0,
20638   0,
20639   0,
20640   0,
20641   0,
20642   0,
20643   0,
20644   0,
20645   0,
20646   0,
20647   0,
20648   0,
20649   0,
20650   0,
20651   0,
20652   0,
20653   0,
20654   0,
20655   0,
20656   0,
20657   0,
20658   0,
20659   0,
20660   0,
20661   Field_xt_wbr18_imm_Slot_xt_flix64_slot3_set,
20662   0,
20663   0,
20664   0,
20665   0,
20666   0,
20667   0,
20668   0,
20669   0,
20670   0,
20671   0,
20672   0,
20673   0,
20674   0,
20675   0,
20676   0,
20677   0,
20678   0,
20679   0,
20680   0,
20681   0,
20682   0,
20683   0,
20684   0,
20685   0,
20686   0,
20687   0,
20688   0,
20689   0,
20690   0,
20691   0,
20692   0,
20693   0,
20694   0,
20695   0,
20696   0,
20697   0,
20698   0,
20699   0,
20700   0,
20701   0,
20702   0,
20703   0,
20704   Field_op0_s6_Slot_xt_flix64_slot3_set,
20705   Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_set,
20706   Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_set,
20707   Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_set,
20708   Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_set,
20709   Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_set,
20710   Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_set,
20711   Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_set,
20712   Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_set,
20713   Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_set,
20714   Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_set,
20715   Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_set,
20716   Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_set,
20717   Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_set,
20718   Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_set,
20719   Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_set,
20720   Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_set,
20721   Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_set,
20722   Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_set,
20723   Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_set,
20724   Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_set,
20725   Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_set,
20726   Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_set,
20727   Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_set,
20728   Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_set,
20729   0,
20730   Implicit_Field_set,
20731   Implicit_Field_set,
20732   Implicit_Field_set,
20733   Implicit_Field_set,
20734   Implicit_Field_set,
20735   Implicit_Field_set,
20736   Implicit_Field_set,
20737   Implicit_Field_set,
20738   Implicit_Field_set,
20739   Implicit_Field_set,
20740   Implicit_Field_set,
20741   Implicit_Field_set
20742 };
20743
20744 static xtensa_slot_internal slots[] = {
20745   { "Inst", "x24", 0,
20746     Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
20747     Slot_inst_get_field_fns, Slot_inst_set_field_fns,
20748     Slot_inst_decode, "nop" },
20749   { "Inst16a", "x16a", 0,
20750     Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
20751     Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
20752     Slot_inst16a_decode, "" },
20753   { "Inst16b", "x16b", 0,
20754     Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
20755     Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
20756     Slot_inst16b_decode, "nop.n" },
20757   { "xt_flix64_slot0", "xt_format1", 0,
20758     Slot_xt_format1_Format_xt_flix64_slot0_4_get, Slot_xt_format1_Format_xt_flix64_slot0_4_set,
20759     Slot_xt_flix64_slot0_get_field_fns, Slot_xt_flix64_slot0_set_field_fns,
20760     Slot_xt_flix64_slot0_decode, "nop" },
20761   { "xt_flix64_slot0", "xt_format2", 0,
20762     Slot_xt_format2_Format_xt_flix64_slot0_4_get, Slot_xt_format2_Format_xt_flix64_slot0_4_set,
20763     Slot_xt_flix64_slot0_get_field_fns, Slot_xt_flix64_slot0_set_field_fns,
20764     Slot_xt_flix64_slot0_decode, "nop" },
20765   { "xt_flix64_slot1", "xt_format1", 1,
20766     Slot_xt_format1_Format_xt_flix64_slot1_28_get, Slot_xt_format1_Format_xt_flix64_slot1_28_set,
20767     Slot_xt_flix64_slot1_get_field_fns, Slot_xt_flix64_slot1_set_field_fns,
20768     Slot_xt_flix64_slot1_decode, "nop" },
20769   { "xt_flix64_slot2", "xt_format1", 2,
20770     Slot_xt_format1_Format_xt_flix64_slot2_48_get, Slot_xt_format1_Format_xt_flix64_slot2_48_set,
20771     Slot_xt_flix64_slot2_get_field_fns, Slot_xt_flix64_slot2_set_field_fns,
20772     Slot_xt_flix64_slot2_decode, "nop" },
20773   { "xt_flix64_slot3", "xt_format2", 1,
20774     Slot_xt_format2_Format_xt_flix64_slot3_28_get, Slot_xt_format2_Format_xt_flix64_slot3_28_set,
20775     Slot_xt_flix64_slot3_get_field_fns, Slot_xt_flix64_slot3_set_field_fns,
20776     Slot_xt_flix64_slot3_decode, "nop" }
20777 };
20778
20779 \f
20780 /* Instruction formats.  */
20781
20782 static void
20783 Format_x24_encode (xtensa_insnbuf insn)
20784 {
20785   insn[0] = 0;
20786   insn[1] = 0;
20787 }
20788
20789 static void
20790 Format_x16a_encode (xtensa_insnbuf insn)
20791 {
20792   insn[0] = 0x8;
20793   insn[1] = 0;
20794 }
20795
20796 static void
20797 Format_x16b_encode (xtensa_insnbuf insn)
20798 {
20799   insn[0] = 0xc;
20800   insn[1] = 0;
20801 }
20802
20803 static void
20804 Format_xt_format1_encode (xtensa_insnbuf insn)
20805 {
20806   insn[0] = 0xe;
20807   insn[1] = 0;
20808 }
20809
20810 static void
20811 Format_xt_format2_encode (xtensa_insnbuf insn)
20812 {
20813   insn[0] = 0xf;
20814   insn[1] = 0;
20815 }
20816
20817 static const int Format_x24_slots[] = { 0 };
20818
20819 static const int Format_x16a_slots[] = { 1 };
20820
20821 static const int Format_x16b_slots[] = { 2 };
20822
20823 static const int Format_xt_format1_slots[] = { 3, 5, 6 };
20824
20825 static const int Format_xt_format2_slots[] = { 4, 7 };
20826
20827 static xtensa_format_internal formats[] = {
20828   { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
20829   { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
20830   { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots },
20831   { "xt_format1", 8, Format_xt_format1_encode, 3, Format_xt_format1_slots },
20832   { "xt_format2", 8, Format_xt_format2_encode, 2, Format_xt_format2_slots }
20833 };
20834
20835
20836 static int
20837 format_decoder (const xtensa_insnbuf insn)
20838 {
20839   if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0)
20840     return 0; /* x24 */
20841   if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0)
20842     return 1; /* x16a */
20843   if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0)
20844     return 2; /* x16b */
20845   if ((insn[0] & 0xf) == 0xe && (insn[1] & 0) == 0)
20846     return 3; /* xt_format1 */
20847   if ((insn[0] & 0xf) == 0xf && (insn[1] & 0x80000000) == 0)
20848     return 4; /* xt_format2 */
20849   return -1;
20850 }
20851
20852 static const int length_table[16] = {
20853   3,
20854   3,
20855   3,
20856   3,
20857   3,
20858   3,
20859   3,
20860   3,
20861   2,
20862   2,
20863   2,
20864   2,
20865   2,
20866   2,
20867   8,
20868   8
20869 };
20870
20871 static int
20872 length_decoder (const unsigned char *insn)
20873 {
20874   int op0 = insn[0] & 0xf;
20875   return length_table[op0];
20876 }
20877
20878 \f
20879 /* Top-level ISA structure.  */
20880
20881 xtensa_isa_internal xtensa_modules = {
20882   0 /* little-endian */,
20883   8 /* insn_size */, 0,
20884   5, formats, format_decoder, length_decoder,
20885   8, slots,
20886   135 /* num_fields */,
20887   188, operands,
20888   355, iclasses,
20889   530, opcodes, 0,
20890   8, regfiles,
20891   NUM_STATES, states, 0,
20892   NUM_SYSREGS, sysregs, 0,
20893   { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
20894   0, interfaces, 0,
20895   0, funcUnits, 0
20896 };