1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2022 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
35 #include "arch-utils.h"
38 #include "mips-tdep.h"
40 #include "reggroups.h"
41 #include "opcode/mips.h"
45 #include "sim-regno.h"
48 #include "frame-unwind.h"
49 #include "frame-base.h"
50 #include "trad-frame.h"
53 #include "target-descriptions.h"
54 #include "dwarf2/frame.h"
55 #include "user-regs.h"
58 #include "target-float.h"
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 static int mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
65 static int micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
);
66 static int mips16_instruction_has_delay_slot (unsigned short inst
,
69 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
71 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
72 CORE_ADDR addr
, int mustbe32
);
73 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
74 CORE_ADDR addr
, int mustbe32
);
76 static void mips_print_float_info (struct gdbarch
*, struct ui_file
*,
77 struct frame_info
*, const char *);
79 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
80 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
81 #define ST0_FR (1 << 26)
83 /* The sizes of floating point registers. */
87 MIPS_FPU_SINGLE_REGSIZE
= 4,
88 MIPS_FPU_DOUBLE_REGSIZE
= 8
97 static const char *mips_abi_string
;
99 static const char *const mips_abi_strings
[] = {
110 /* Enum describing the different kinds of breakpoints. */
112 enum mips_breakpoint_kind
114 /* 16-bit MIPS16 mode breakpoint. */
115 MIPS_BP_KIND_MIPS16
= 2,
117 /* 16-bit microMIPS mode breakpoint. */
118 MIPS_BP_KIND_MICROMIPS16
= 3,
120 /* 32-bit standard MIPS mode breakpoint. */
121 MIPS_BP_KIND_MIPS32
= 4,
123 /* 32-bit microMIPS mode breakpoint. */
124 MIPS_BP_KIND_MICROMIPS32
= 5,
127 /* For backwards compatibility we default to MIPS16. This flag is
128 overridden as soon as unambiguous ELF file flags tell us the
129 compressed ISA encoding used. */
130 static const char mips_compression_mips16
[] = "mips16";
131 static const char mips_compression_micromips
[] = "micromips";
132 static const char *const mips_compression_strings
[] =
134 mips_compression_mips16
,
135 mips_compression_micromips
,
139 static const char *mips_compression_string
= mips_compression_mips16
;
141 /* The standard register names, and all the valid aliases for them. */
142 struct register_alias
148 /* Aliases for o32 and most other ABIs. */
149 const struct register_alias mips_o32_aliases
[] = {
156 /* Aliases for n32 and n64. */
157 const struct register_alias mips_n32_n64_aliases
[] = {
164 /* Aliases for ABI-independent registers. */
165 const struct register_alias mips_register_aliases
[] = {
166 /* The architecture manuals specify these ABI-independent names for
168 #define R(n) { "r" #n, n }
169 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
170 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
171 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
172 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
175 /* k0 and k1 are sometimes called these instead (for "kernel
180 /* This is the traditional GDB name for the CP0 status register. */
181 { "sr", MIPS_PS_REGNUM
},
183 /* This is the traditional GDB name for the CP0 BadVAddr register. */
184 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
186 /* This is the traditional GDB name for the FCSR. */
187 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
190 const struct register_alias mips_numeric_register_aliases
[] = {
191 #define R(n) { #n, n }
192 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
193 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
194 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
195 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
199 #ifndef MIPS_DEFAULT_FPU_TYPE
200 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
202 static int mips_fpu_type_auto
= 1;
203 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
205 static unsigned int mips_debug
= 0;
207 /* Properties (for struct target_desc) describing the g/G packet
209 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
210 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
212 struct target_desc
*mips_tdesc_gp32
;
213 struct target_desc
*mips_tdesc_gp64
;
215 /* The current set of options to be passed to the disassembler. */
216 static char *mips_disassembler_options
;
218 /* Implicit disassembler options for individual ABIs. These tell
219 libopcodes to use general-purpose register names corresponding
220 to the ABI we have selected, perhaps via a `set mips abi ...'
221 override, rather than ones inferred from the ABI set in the ELF
222 headers of the binary file selected for debugging. */
223 static const char mips_disassembler_options_o32
[] = "gpr-names=32";
224 static const char mips_disassembler_options_n32
[] = "gpr-names=n32";
225 static const char mips_disassembler_options_n64
[] = "gpr-names=64";
227 const struct mips_regnum
*
228 mips_regnum (struct gdbarch
*gdbarch
)
230 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
235 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
237 return mips_regnum (gdbarch
)->fp0
+ 12;
240 /* Return 1 if REGNUM refers to a floating-point general register, raw
241 or cooked. Otherwise return 0. */
244 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
246 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
248 return (rawnum
>= mips_regnum (gdbarch
)->fp0
249 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
253 mips_eabi (gdbarch
*arch
)
255 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (arch
);
256 return (tdep
->mips_abi
== MIPS_ABI_EABI32 \
257 || tdep
->mips_abi
== MIPS_ABI_EABI64
);
261 mips_last_fp_arg_regnum (gdbarch
*arch
)
263 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (arch
);
264 return tdep
->mips_last_fp_arg_regnum
;
268 mips_last_arg_regnum (gdbarch
*arch
)
270 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (arch
);
271 return tdep
->mips_last_arg_regnum
;
274 static enum mips_fpu_type
275 mips_get_fpu_type (gdbarch
*arch
)
277 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (arch
);
278 return tdep
->mips_fpu_type
;
281 /* Return the MIPS ABI associated with GDBARCH. */
283 mips_abi (struct gdbarch
*gdbarch
)
285 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
286 return tdep
->mips_abi
;
290 mips_isa_regsize (struct gdbarch
*gdbarch
)
292 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
294 /* If we know how big the registers are, use that size. */
295 if (tdep
->register_size_valid_p
)
296 return tdep
->register_size
;
298 /* Fall back to the previous behavior. */
299 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
300 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
303 /* Max saved register size. */
304 #define MAX_MIPS_ABI_REGSIZE 8
306 /* Return the currently configured (or set) saved register size. */
309 mips_abi_regsize (struct gdbarch
*gdbarch
)
311 switch (mips_abi (gdbarch
))
313 case MIPS_ABI_EABI32
:
319 case MIPS_ABI_EABI64
:
321 case MIPS_ABI_UNKNOWN
:
324 internal_error (__FILE__
, __LINE__
, _("bad switch"));
328 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
329 are some functions to handle addresses associated with compressed
330 code including but not limited to testing, setting, or clearing
331 bit 0 of such addresses. */
333 /* Return one iff compressed code is the MIPS16 instruction set. */
336 is_mips16_isa (struct gdbarch
*gdbarch
)
338 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
339 return tdep
->mips_isa
== ISA_MIPS16
;
342 /* Return one iff compressed code is the microMIPS instruction set. */
345 is_micromips_isa (struct gdbarch
*gdbarch
)
347 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
348 return tdep
->mips_isa
== ISA_MICROMIPS
;
351 /* Return one iff ADDR denotes compressed code. */
354 is_compact_addr (CORE_ADDR addr
)
359 /* Return one iff ADDR denotes standard ISA code. */
362 is_mips_addr (CORE_ADDR addr
)
364 return !is_compact_addr (addr
);
367 /* Return one iff ADDR denotes MIPS16 code. */
370 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
372 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
375 /* Return one iff ADDR denotes microMIPS code. */
378 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
380 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
383 /* Strip the ISA (compression) bit off from ADDR. */
386 unmake_compact_addr (CORE_ADDR addr
)
388 return ((addr
) & ~(CORE_ADDR
) 1);
391 /* Add the ISA (compression) bit to ADDR. */
394 make_compact_addr (CORE_ADDR addr
)
396 return ((addr
) | (CORE_ADDR
) 1);
399 /* Extern version of unmake_compact_addr; we use a separate function
400 so that unmake_compact_addr can be inlined throughout this file. */
403 mips_unmake_compact_addr (CORE_ADDR addr
)
405 return unmake_compact_addr (addr
);
408 /* Functions for setting and testing a bit in a minimal symbol that
409 marks it as MIPS16 or microMIPS function. The MSB of the minimal
410 symbol's "info" field is used for this purpose.
412 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
413 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
414 one of the "special" bits in a minimal symbol to mark it accordingly.
415 The test checks an ELF-private flag that is valid for true function
416 symbols only; for synthetic symbols such as for PLT stubs that have
417 no ELF-private part at all the MIPS BFD backend arranges for this
418 information to be carried in the asymbol's udata field instead.
420 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
421 in a minimal symbol. */
424 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
426 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
427 unsigned char st_other
;
429 if ((sym
->flags
& BSF_SYNTHETIC
) == 0)
430 st_other
= elfsym
->internal_elf_sym
.st_other
;
431 else if ((sym
->flags
& BSF_FUNCTION
) != 0)
432 st_other
= sym
->udata
.i
;
436 if (ELF_ST_IS_MICROMIPS (st_other
))
438 SET_MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
439 msym
->set_value_address (msym
->value_raw_address () | 1);
441 else if (ELF_ST_IS_MIPS16 (st_other
))
443 SET_MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
444 msym
->set_value_address (msym
->value_raw_address () | 1);
448 /* Return one iff MSYM refers to standard ISA code. */
451 msymbol_is_mips (struct minimal_symbol
*msym
)
453 return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym
)
454 || MSYMBOL_TARGET_FLAG_MICROMIPS (msym
));
457 /* Return one iff MSYM refers to MIPS16 code. */
460 msymbol_is_mips16 (struct minimal_symbol
*msym
)
462 return MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
465 /* Return one iff MSYM refers to microMIPS code. */
468 msymbol_is_micromips (struct minimal_symbol
*msym
)
470 return MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
473 /* Set the ISA bit in the main symbol too, complementing the corresponding
474 minimal symbol setting and reflecting the run-time value of the symbol.
475 The need for comes from the ISA bit having been cleared as code in
476 `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's
477 `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values
478 of symbols referring to compressed code different in GDB to the values
479 used by actual code. That in turn makes them evaluate incorrectly in
480 expressions, producing results different to what the same expressions
481 yield when compiled into the program being debugged. */
484 mips_make_symbol_special (struct symbol
*sym
, struct objfile
*objfile
)
486 if (sym
->aclass () == LOC_BLOCK
)
488 /* We are in symbol reading so it is OK to cast away constness. */
489 struct block
*block
= (struct block
*) sym
->value_block ();
490 CORE_ADDR compact_block_start
;
491 struct bound_minimal_symbol msym
;
493 compact_block_start
= block
->start () | 1;
494 msym
= lookup_minimal_symbol_by_pc (compact_block_start
);
495 if (msym
.minsym
&& !msymbol_is_mips (msym
.minsym
))
497 block
->set_start (compact_block_start
);
502 /* XFER a value from the big/little/left end of the register.
503 Depending on the size of the value it might occupy the entire
504 register or just part of it. Make an allowance for this, aligning
505 things accordingly. */
508 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
509 int reg_num
, int length
,
510 enum bfd_endian endian
, gdb_byte
*in
,
511 const gdb_byte
*out
, int buf_offset
)
515 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
516 /* Need to transfer the left or right part of the register, based on
517 the targets byte order. */
521 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
523 case BFD_ENDIAN_LITTLE
:
526 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
530 internal_error (__FILE__
, __LINE__
, _("bad switch"));
533 gdb_printf (gdb_stderr
,
534 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
535 reg_num
, reg_offset
, buf_offset
, length
);
536 if (mips_debug
&& out
!= NULL
)
539 gdb_printf (gdb_stdlog
, "out ");
540 for (i
= 0; i
< length
; i
++)
541 gdb_printf (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
544 regcache
->cooked_read_part (reg_num
, reg_offset
, length
, in
+ buf_offset
);
546 regcache
->cooked_write_part (reg_num
, reg_offset
, length
, out
+ buf_offset
);
547 if (mips_debug
&& in
!= NULL
)
550 gdb_printf (gdb_stdlog
, "in ");
551 for (i
= 0; i
< length
; i
++)
552 gdb_printf (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
555 gdb_printf (gdb_stdlog
, "\n");
558 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
559 compatiblity mode. A return value of 1 means that we have
560 physical 64-bit registers, but should treat them as 32-bit registers. */
563 mips2_fp_compat (struct frame_info
*frame
)
565 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
566 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
568 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
572 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
573 in all the places we deal with FP registers. PR gdb/413. */
574 /* Otherwise check the FR bit in the status register - it controls
575 the FP compatiblity mode. If it is clear we are in compatibility
577 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
584 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
586 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
588 /* The list of available "set mips " and "show mips " commands. */
590 static struct cmd_list_element
*setmipscmdlist
= NULL
;
591 static struct cmd_list_element
*showmipscmdlist
= NULL
;
593 /* Integer registers 0 thru 31 are handled explicitly by
594 mips_register_name(). Processor specific registers 32 and above
595 are listed in the following tables. */
598 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
602 static const char * const mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
603 "sr", "lo", "hi", "bad", "cause", "pc",
604 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
605 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
606 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
607 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
611 /* Names of tx39 registers. */
613 static const char * const mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
614 "sr", "lo", "hi", "bad", "cause", "pc",
615 "", "", "", "", "", "", "", "",
616 "", "", "", "", "", "", "", "",
617 "", "", "", "", "", "", "", "",
618 "", "", "", "", "", "", "", "",
620 "", "", "", "", "", "", "", "",
621 "", "", "config", "cache", "debug", "depc", "epc",
624 /* Names of registers with Linux kernels. */
625 static const char * const mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
626 "sr", "lo", "hi", "bad", "cause", "pc",
627 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
628 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
629 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
630 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
635 /* Return the name of the register corresponding to REGNO. */
637 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
639 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
640 /* GPR names for all ABIs other than n32/n64. */
641 static const char *mips_gpr_names
[] = {
642 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
643 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
644 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
645 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
648 /* GPR names for n32 and n64 ABIs. */
649 static const char *mips_n32_n64_gpr_names
[] = {
650 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
651 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
652 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
653 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
656 enum mips_abi abi
= mips_abi (gdbarch
);
658 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
659 but then don't make the raw register names visible. This (upper)
660 range of user visible register numbers are the pseudo-registers.
662 This approach was adopted accommodate the following scenario:
663 It is possible to debug a 64-bit device using a 32-bit
664 programming model. In such instances, the raw registers are
665 configured to be 64-bits wide, while the pseudo registers are
666 configured to be 32-bits wide. The registers that the user
667 sees - the pseudo registers - match the users expectations
668 given the programming model being used. */
669 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
670 if (regno
< gdbarch_num_regs (gdbarch
))
673 /* The MIPS integer registers are always mapped from 0 to 31. The
674 names of the registers (which reflects the conventions regarding
675 register use) vary depending on the ABI. */
676 if (0 <= rawnum
&& rawnum
< 32)
678 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
679 return mips_n32_n64_gpr_names
[rawnum
];
681 return mips_gpr_names
[rawnum
];
683 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
684 return tdesc_register_name (gdbarch
, rawnum
);
685 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
687 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
688 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
689 return tdep
->mips_processor_reg_names
[rawnum
- 32];
693 internal_error (__FILE__
, __LINE__
,
694 _("mips_register_name: bad register number %d"), rawnum
);
697 /* Return the groups that a MIPS register can be categorised into. */
700 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
701 const struct reggroup
*reggroup
)
706 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
707 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
708 if (reggroup
== all_reggroup
)
710 vector_p
= register_type (gdbarch
, regnum
)->is_vector ();
711 float_p
= register_type (gdbarch
, regnum
)->code () == TYPE_CODE_FLT
;
712 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
713 (gdbarch), as not all architectures are multi-arch. */
714 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
715 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
716 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
718 if (reggroup
== float_reggroup
)
719 return float_p
&& pseudo
;
720 if (reggroup
== vector_reggroup
)
721 return vector_p
&& pseudo
;
722 if (reggroup
== general_reggroup
)
723 return (!vector_p
&& !float_p
) && pseudo
;
724 /* Save the pseudo registers. Need to make certain that any code
725 extracting register values from a saved register cache also uses
727 if (reggroup
== save_reggroup
)
728 return raw_p
&& pseudo
;
729 /* Restore the same pseudo register. */
730 if (reggroup
== restore_reggroup
)
731 return raw_p
&& pseudo
;
735 /* Return the groups that a MIPS register can be categorised into.
736 This version is only used if we have a target description which
737 describes real registers (and their groups). */
740 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
741 const struct reggroup
*reggroup
)
743 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
744 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
747 /* Only save, restore, and display the pseudo registers. Need to
748 make certain that any code extracting register values from a
749 saved register cache also uses pseudo registers.
751 Note: saving and restoring the pseudo registers is slightly
752 strange; if we have 64 bits, we should save and restore all
753 64 bits. But this is hard and has little benefit. */
757 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
761 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
764 /* Map the symbol table registers which live in the range [1 *
765 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
766 registers. Take care of alignment and size problems. */
768 static enum register_status
769 mips_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
770 int cookednum
, gdb_byte
*buf
)
772 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
773 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
774 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
775 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
776 return regcache
->raw_read (rawnum
, buf
);
777 else if (register_size (gdbarch
, rawnum
) >
778 register_size (gdbarch
, cookednum
))
780 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
782 if (tdep
->mips64_transfers_32bit_regs_p
)
783 return regcache
->raw_read_part (rawnum
, 0, 4, buf
);
786 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
788 enum register_status status
;
790 status
= regcache
->raw_read (rawnum
, ®val
);
791 if (status
== REG_VALID
)
792 store_signed_integer (buf
, 4, byte_order
, regval
);
797 internal_error (__FILE__
, __LINE__
, _("bad register size"));
801 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
802 struct regcache
*regcache
, int cookednum
,
805 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
806 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
807 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
808 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
809 regcache
->raw_write (rawnum
, buf
);
810 else if (register_size (gdbarch
, rawnum
) >
811 register_size (gdbarch
, cookednum
))
813 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
815 if (tdep
->mips64_transfers_32bit_regs_p
)
816 regcache
->raw_write_part (rawnum
, 0, 4, buf
);
819 /* Sign extend the shortened version of the register prior
820 to placing it in the raw register. This is required for
821 some mips64 parts in order to avoid unpredictable behavior. */
822 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
823 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
824 regcache_raw_write_signed (regcache
, rawnum
, regval
);
828 internal_error (__FILE__
, __LINE__
, _("bad register size"));
832 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
833 struct agent_expr
*ax
, int reg
)
835 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
836 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
837 && reg
< 2 * gdbarch_num_regs (gdbarch
));
839 ax_reg_mask (ax
, rawnum
);
845 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
846 struct agent_expr
*ax
, int reg
)
848 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
849 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
850 && reg
< 2 * gdbarch_num_regs (gdbarch
));
851 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
855 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
857 mips_gdbarch_tdep
*tdep
858 = (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
860 if (!tdep
->mips64_transfers_32bit_regs_p
861 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
864 ax_simple (ax
, aop_lsh
);
867 ax_simple (ax
, aop_rsh_signed
);
871 internal_error (__FILE__
, __LINE__
, _("bad register size"));
876 /* Table to translate 3-bit register field to actual register number. */
877 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
879 /* Heuristic_proc_start may hunt through the text section for a long
880 time across a 2400 baud serial line. Allows the user to limit this
883 static int heuristic_fence_post
= 0;
885 /* Number of bytes of storage in the actual machine representation for
886 register N. NOTE: This defines the pseudo register type so need to
887 rebuild the architecture vector. */
889 static bool mips64_transfers_32bit_regs_p
= false;
892 set_mips64_transfers_32bit_regs (const char *args
, int from_tty
,
893 struct cmd_list_element
*c
)
895 struct gdbarch_info info
;
896 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
897 instead of relying on globals. Doing that would let generic code
898 handle the search for this specific architecture. */
899 if (!gdbarch_update_p (info
))
901 mips64_transfers_32bit_regs_p
= 0;
902 error (_("32-bit compatibility mode not supported"));
906 /* Convert to/from a register and the corresponding memory value. */
908 /* This predicate tests for the case of an 8 byte floating point
909 value that is being transferred to or from a pair of floating point
910 registers each of which are (or are considered to be) only 4 bytes
913 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
916 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
917 && register_size (gdbarch
, regnum
) == 4
918 && mips_float_register_p (gdbarch
, regnum
)
919 && type
->code () == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
922 /* This predicate tests for the case of a value of less than 8
923 bytes in width that is being transfered to or from an 8 byte
924 general purpose register. */
926 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
929 int num_regs
= gdbarch_num_regs (gdbarch
);
931 return (register_size (gdbarch
, regnum
) == 8
932 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
933 && TYPE_LENGTH (type
) < 8);
937 mips_convert_register_p (struct gdbarch
*gdbarch
,
938 int regnum
, struct type
*type
)
940 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
941 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
945 mips_register_to_value (struct frame_info
*frame
, int regnum
,
946 struct type
*type
, gdb_byte
*to
,
947 int *optimizedp
, int *unavailablep
)
949 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
951 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
953 get_frame_register (frame
, regnum
+ 0, to
+ 4);
954 get_frame_register (frame
, regnum
+ 1, to
+ 0);
956 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, {to
+ 4, 4},
957 optimizedp
, unavailablep
))
960 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, {to
+ 0, 4},
961 optimizedp
, unavailablep
))
963 *optimizedp
= *unavailablep
= 0;
966 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
968 size_t len
= TYPE_LENGTH (type
);
971 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
972 if (!get_frame_register_bytes (frame
, regnum
, offset
, {to
, len
},
973 optimizedp
, unavailablep
))
976 *optimizedp
= *unavailablep
= 0;
981 internal_error (__FILE__
, __LINE__
,
982 _("mips_register_to_value: unrecognized case"));
987 mips_value_to_register (struct frame_info
*frame
, int regnum
,
988 struct type
*type
, const gdb_byte
*from
)
990 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
992 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
994 put_frame_register (frame
, regnum
+ 0, from
+ 4);
995 put_frame_register (frame
, regnum
+ 1, from
+ 0);
997 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
1000 size_t len
= TYPE_LENGTH (type
);
1002 /* Sign extend values, irrespective of type, that are stored to
1003 a 64-bit general purpose register. (32-bit unsigned values
1004 are stored as signed quantities within a 64-bit register.
1005 When performing an operation, in compiled code, that combines
1006 a 32-bit unsigned value with a signed 64-bit value, a type
1007 conversion is first performed that zeroes out the high 32 bits.) */
1008 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1011 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
1013 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
1014 put_frame_register_bytes (frame
, regnum
, 0, {fill
, 8 - len
});
1015 put_frame_register_bytes (frame
, regnum
, 8 - len
, {from
, len
});
1019 if (from
[len
-1] & 0x80)
1020 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
1022 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
1023 put_frame_register_bytes (frame
, regnum
, 0, {from
, len
});
1024 put_frame_register_bytes (frame
, regnum
, len
, {fill
, 8 - len
});
1029 internal_error (__FILE__
, __LINE__
,
1030 _("mips_value_to_register: unrecognized case"));
1034 /* Return the GDB type object for the "standard" data type of data in
1037 static struct type
*
1038 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
1040 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
1041 if (mips_float_register_p (gdbarch
, regnum
))
1043 /* The floating-point registers raw, or cooked, always match
1044 mips_isa_regsize(), and also map 1:1, byte for byte. */
1045 if (mips_isa_regsize (gdbarch
) == 4)
1046 return builtin_type (gdbarch
)->builtin_float
;
1048 return builtin_type (gdbarch
)->builtin_double
;
1050 else if (regnum
< gdbarch_num_regs (gdbarch
))
1052 /* The raw or ISA registers. These are all sized according to
1054 if (mips_isa_regsize (gdbarch
) == 4)
1055 return builtin_type (gdbarch
)->builtin_int32
;
1057 return builtin_type (gdbarch
)->builtin_int64
;
1061 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
1062 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1064 /* The cooked or ABI registers. These are sized according to
1065 the ABI (with a few complications). */
1066 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1067 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1068 return builtin_type (gdbarch
)->builtin_int32
;
1069 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1070 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1071 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1072 /* The pseudo/cooked view of the embedded registers is always
1073 32-bit. The raw view is handled below. */
1074 return builtin_type (gdbarch
)->builtin_int32
;
1075 else if (tdep
->mips64_transfers_32bit_regs_p
)
1076 /* The target, while possibly using a 64-bit register buffer,
1077 is only transfering 32-bits of each integer register.
1078 Reflect this in the cooked/pseudo (ABI) register value. */
1079 return builtin_type (gdbarch
)->builtin_int32
;
1080 else if (mips_abi_regsize (gdbarch
) == 4)
1081 /* The ABI is restricted to 32-bit registers (the ISA could be
1083 return builtin_type (gdbarch
)->builtin_int32
;
1086 return builtin_type (gdbarch
)->builtin_int64
;
1090 /* Return the GDB type for the pseudo register REGNUM, which is the
1091 ABI-level view. This function is only called if there is a target
1092 description which includes registers, so we know precisely the
1093 types of hardware registers. */
1095 static struct type
*
1096 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1098 const int num_regs
= gdbarch_num_regs (gdbarch
);
1099 int rawnum
= regnum
% num_regs
;
1100 struct type
*rawtype
;
1102 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1104 /* Absent registers are still absent. */
1105 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1106 if (TYPE_LENGTH (rawtype
) == 0)
1109 /* Present the floating point registers however the hardware did;
1110 do not try to convert between FPU layouts. */
1111 if (mips_float_register_p (gdbarch
, rawnum
))
1114 /* Floating-point control registers are always 32-bit even though for
1115 backwards compatibility reasons 64-bit targets will transfer them
1116 as 64-bit quantities even if using XML descriptions. */
1117 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1118 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1119 return builtin_type (gdbarch
)->builtin_int32
;
1121 /* Use pointer types for registers if we can. For n32 we can not,
1122 since we do not have a 64-bit pointer type. */
1123 if (mips_abi_regsize (gdbarch
)
1124 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
1126 if (rawnum
== MIPS_SP_REGNUM
1127 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1128 return builtin_type (gdbarch
)->builtin_data_ptr
;
1129 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1130 return builtin_type (gdbarch
)->builtin_func_ptr
;
1133 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
1134 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1135 || rawnum
== mips_regnum (gdbarch
)->lo
1136 || rawnum
== mips_regnum (gdbarch
)->hi
1137 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1138 || rawnum
== mips_regnum (gdbarch
)->cause
1139 || rawnum
== mips_regnum (gdbarch
)->pc
1140 || (mips_regnum (gdbarch
)->dspacc
!= -1
1141 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1142 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1143 return builtin_type (gdbarch
)->builtin_int32
;
1145 /* The pseudo/cooked view of embedded registers is always
1146 32-bit, even if the target transfers 64-bit values for them.
1147 New targets relying on XML descriptions should only transfer
1148 the necessary 32 bits, but older versions of GDB expected 64,
1149 so allow the target to provide 64 bits without interfering
1150 with the displayed type. */
1151 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1152 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1153 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1154 return builtin_type (gdbarch
)->builtin_int32
;
1156 /* For all other registers, pass through the hardware type. */
1160 /* Should the upper word of 64-bit addresses be zeroed? */
1161 static enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1164 mips_mask_address_p (mips_gdbarch_tdep
*tdep
)
1166 switch (mask_address_var
)
1168 case AUTO_BOOLEAN_TRUE
:
1170 case AUTO_BOOLEAN_FALSE
:
1173 case AUTO_BOOLEAN_AUTO
:
1174 return tdep
->default_mask_address_p
;
1176 internal_error (__FILE__
, __LINE__
,
1177 _("mips_mask_address_p: bad switch"));
1183 show_mask_address (struct ui_file
*file
, int from_tty
,
1184 struct cmd_list_element
*c
, const char *value
)
1186 mips_gdbarch_tdep
*tdep
1187 = (mips_gdbarch_tdep
*) gdbarch_tdep (target_gdbarch ());
1189 deprecated_show_value_hack (file
, from_tty
, c
, value
);
1190 switch (mask_address_var
)
1192 case AUTO_BOOLEAN_TRUE
:
1193 gdb_printf (file
, "The 32 bit mips address mask is enabled\n");
1195 case AUTO_BOOLEAN_FALSE
:
1196 gdb_printf (file
, "The 32 bit mips address mask is disabled\n");
1198 case AUTO_BOOLEAN_AUTO
:
1201 "The 32 bit address mask is set automatically. Currently %s\n",
1202 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1205 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1210 /* Tell if the program counter value in MEMADDR is in a standard ISA
1214 mips_pc_is_mips (CORE_ADDR memaddr
)
1216 struct bound_minimal_symbol sym
;
1218 /* Flags indicating that this is a MIPS16 or microMIPS function is
1219 stored by elfread.c in the high bit of the info field. Use this
1220 to decide if the function is standard MIPS. Otherwise if bit 0
1221 of the address is clear, then this is a standard MIPS function. */
1222 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1224 return msymbol_is_mips (sym
.minsym
);
1226 return is_mips_addr (memaddr
);
1229 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1232 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1234 struct bound_minimal_symbol sym
;
1236 /* A flag indicating that this is a MIPS16 function is stored by
1237 elfread.c in the high bit of the info field. Use this to decide
1238 if the function is MIPS16. Otherwise if bit 0 of the address is
1239 set, then ELF file flags will tell if this is a MIPS16 function. */
1240 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1242 return msymbol_is_mips16 (sym
.minsym
);
1244 return is_mips16_addr (gdbarch
, memaddr
);
1247 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1250 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1252 struct bound_minimal_symbol sym
;
1254 /* A flag indicating that this is a microMIPS function is stored by
1255 elfread.c in the high bit of the info field. Use this to decide
1256 if the function is microMIPS. Otherwise if bit 0 of the address
1257 is set, then ELF file flags will tell if this is a microMIPS
1259 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1261 return msymbol_is_micromips (sym
.minsym
);
1263 return is_micromips_addr (gdbarch
, memaddr
);
1266 /* Tell the ISA type of the function the program counter value in MEMADDR
1269 static enum mips_isa
1270 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1272 struct bound_minimal_symbol sym
;
1274 /* A flag indicating that this is a MIPS16 or a microMIPS function
1275 is stored by elfread.c in the high bit of the info field. Use
1276 this to decide if the function is MIPS16 or microMIPS or normal
1277 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1278 flags will tell if this is a MIPS16 or a microMIPS function. */
1279 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1282 if (msymbol_is_micromips (sym
.minsym
))
1283 return ISA_MICROMIPS
;
1284 else if (msymbol_is_mips16 (sym
.minsym
))
1291 if (is_mips_addr (memaddr
))
1293 else if (is_micromips_addr (gdbarch
, memaddr
))
1294 return ISA_MICROMIPS
;
1300 /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery.
1301 The need for comes from the ISA bit having been cleared, making
1302 addresses in FDE, range records, etc. referring to compressed code
1303 different to those in line information, the symbol table and finally
1304 the PC register. That in turn confuses many operations. */
1307 mips_adjust_dwarf2_addr (CORE_ADDR pc
)
1309 pc
= unmake_compact_addr (pc
);
1310 return mips_pc_is_mips (pc
) ? pc
: make_compact_addr (pc
);
1313 /* Recalculate the line record requested so that the resulting PC has
1314 the ISA bit set correctly, used by DWARF-2 machinery. The need for
1315 this adjustment comes from some records associated with compressed
1316 code having the ISA bit cleared, most notably at function prologue
1317 ends. The ISA bit is in this context retrieved from the minimal
1318 symbol covering the address requested, which in turn has been
1319 constructed from the binary's symbol table rather than DWARF-2
1320 information. The correct setting of the ISA bit is required for
1321 breakpoint addresses to correctly match against the stop PC.
1323 As line entries can specify relative address adjustments we need to
1324 keep track of the absolute value of the last line address recorded
1325 in line information, so that we can calculate the actual address to
1326 apply the ISA bit adjustment to. We use PC for this tracking and
1327 keep the original address there.
1329 As such relative address adjustments can be odd within compressed
1330 code we need to keep track of the last line address with the ISA
1331 bit adjustment applied too, as the original address may or may not
1332 have had the ISA bit set. We use ADJ_PC for this tracking and keep
1333 the adjusted address there.
1335 For relative address adjustments we then use these variables to
1336 calculate the address intended by line information, which will be
1337 PC-relative, and return an updated adjustment carrying ISA bit
1338 information, which will be ADJ_PC-relative. For absolute address
1339 adjustments we just return the same address that we store in ADJ_PC
1342 As the first line entry can be relative to an implied address value
1343 of 0 we need to have the initial address set up that we store in PC
1344 and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1'
1345 that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */
1348 mips_adjust_dwarf2_line (CORE_ADDR addr
, int rel
)
1350 static CORE_ADDR adj_pc
;
1351 static CORE_ADDR pc
;
1354 pc
= rel
? pc
+ addr
: addr
;
1355 isa_pc
= mips_adjust_dwarf2_addr (pc
);
1356 addr
= rel
? isa_pc
- adj_pc
: isa_pc
;
1361 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1363 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1364 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1365 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1366 static const char mips_str_call_stub
[] = "__call_stub_";
1367 static const char mips_str_fn_stub
[] = "__fn_stub_";
1369 /* This is used as a PIC thunk prefix. */
1371 static const char mips_str_pic
[] = ".pic.";
1373 /* Return non-zero if the PC is inside a call thunk (aka stub or
1374 trampoline) that should be treated as a temporary frame. */
1377 mips_in_frame_stub (CORE_ADDR pc
)
1379 CORE_ADDR start_addr
;
1382 /* Find the starting address of the function containing the PC. */
1383 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1386 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1387 if (startswith (name
, mips_str_mips16_call_stub
))
1389 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1390 if (startswith (name
, mips_str_call_stub
))
1392 /* If the PC is in __fn_stub_*, this is a call stub. */
1393 if (startswith (name
, mips_str_fn_stub
))
1396 return 0; /* Not a stub. */
1399 /* MIPS believes that the PC has a sign extended value. Perhaps the
1400 all registers should be sign extended for simplicity? */
1403 mips_read_pc (readable_regcache
*regcache
)
1405 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1408 regcache
->cooked_read (regnum
, &pc
);
1413 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1417 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1418 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1419 intermediate frames. In this case we can get the caller's address
1420 from $ra, or if $ra contains an address within a thunk as well, then
1421 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1422 and thus the caller's address is in $s2. */
1423 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1425 pc
= frame_unwind_register_signed
1426 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1427 if (mips_in_frame_stub (pc
))
1428 pc
= frame_unwind_register_signed
1429 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1435 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1437 return frame_unwind_register_signed
1438 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1441 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1442 dummy frame. The frame ID's base needs to match the TOS value
1443 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1446 static struct frame_id
1447 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1449 return frame_id_build
1450 (get_frame_register_signed (this_frame
,
1451 gdbarch_num_regs (gdbarch
)
1453 get_frame_pc (this_frame
));
1456 /* Implement the "write_pc" gdbarch method. */
1459 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1461 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1463 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1466 /* Fetch and return instruction from the specified location. Handle
1467 MIPS16/microMIPS as appropriate. */
1470 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1471 enum mips_isa isa
, CORE_ADDR addr
, int *errp
)
1473 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1474 gdb_byte buf
[MIPS_INSN32_SIZE
];
1482 instlen
= MIPS_INSN16_SIZE
;
1483 addr
= unmake_compact_addr (addr
);
1486 instlen
= MIPS_INSN32_SIZE
;
1489 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1492 err
= target_read_memory (addr
, buf
, instlen
);
1498 memory_error (TARGET_XFER_E_IO
, addr
);
1501 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1504 /* These are the fields of 32 bit mips instructions. */
1505 #define mips32_op(x) (x >> 26)
1506 #define itype_op(x) (x >> 26)
1507 #define itype_rs(x) ((x >> 21) & 0x1f)
1508 #define itype_rt(x) ((x >> 16) & 0x1f)
1509 #define itype_immediate(x) (x & 0xffff)
1511 #define jtype_op(x) (x >> 26)
1512 #define jtype_target(x) (x & 0x03ffffff)
1514 #define rtype_op(x) (x >> 26)
1515 #define rtype_rs(x) ((x >> 21) & 0x1f)
1516 #define rtype_rt(x) ((x >> 16) & 0x1f)
1517 #define rtype_rd(x) ((x >> 11) & 0x1f)
1518 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1519 #define rtype_funct(x) (x & 0x3f)
1521 /* MicroMIPS instruction fields. */
1522 #define micromips_op(x) ((x) >> 10)
1524 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1525 bit and the size respectively of the field extracted. */
1526 #define b0s4_imm(x) ((x) & 0xf)
1527 #define b0s5_imm(x) ((x) & 0x1f)
1528 #define b0s5_reg(x) ((x) & 0x1f)
1529 #define b0s7_imm(x) ((x) & 0x7f)
1530 #define b0s10_imm(x) ((x) & 0x3ff)
1531 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1532 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1533 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1534 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1535 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1536 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1537 #define b6s4_op(x) (((x) >> 6) & 0xf)
1538 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1540 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1541 respectively of the field extracted. */
1542 #define b0s6_op(x) ((x) & 0x3f)
1543 #define b0s11_op(x) ((x) & 0x7ff)
1544 #define b0s12_imm(x) ((x) & 0xfff)
1545 #define b0s16_imm(x) ((x) & 0xffff)
1546 #define b0s26_imm(x) ((x) & 0x3ffffff)
1547 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1548 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1549 #define b12s4_op(x) (((x) >> 12) & 0xf)
1551 /* Return the size in bytes of the instruction INSN encoded in the ISA
1555 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1560 if ((micromips_op (insn
) & 0x4) == 0x4
1561 || (micromips_op (insn
) & 0x7) == 0x0)
1562 return 2 * MIPS_INSN16_SIZE
;
1564 return MIPS_INSN16_SIZE
;
1566 if ((insn
& 0xf800) == 0xf000)
1567 return 2 * MIPS_INSN16_SIZE
;
1569 return MIPS_INSN16_SIZE
;
1571 return MIPS_INSN32_SIZE
;
1573 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1577 mips32_relative_offset (ULONGEST inst
)
1579 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1582 /* Determine the address of the next instruction executed after the INST
1583 floating condition branch instruction at PC. COUNT specifies the
1584 number of the floating condition bits tested by the branch. */
1587 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1588 ULONGEST inst
, CORE_ADDR pc
, int count
)
1590 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1591 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1592 int tf
= itype_rt (inst
) & 1;
1593 int mask
= (1 << count
) - 1;
1598 /* No way to handle; it'll most likely trap anyway. */
1601 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1602 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1604 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1605 pc
+= mips32_relative_offset (inst
);
1612 /* Return nonzero if the gdbarch is an Octeon series. */
1615 is_octeon (struct gdbarch
*gdbarch
)
1617 const struct bfd_arch_info
*info
= gdbarch_bfd_arch_info (gdbarch
);
1619 return (info
->mach
== bfd_mach_mips_octeon
1620 || info
->mach
== bfd_mach_mips_octeonp
1621 || info
->mach
== bfd_mach_mips_octeon2
);
1624 /* Return true if the OP represents the Octeon's BBIT instruction. */
1627 is_octeon_bbit_op (int op
, struct gdbarch
*gdbarch
)
1629 if (!is_octeon (gdbarch
))
1631 /* BBIT0 is encoded as LWC2: 110 010. */
1632 /* BBIT032 is encoded as LDC2: 110 110. */
1633 /* BBIT1 is encoded as SWC2: 111 010. */
1634 /* BBIT132 is encoded as SDC2: 111 110. */
1635 if (op
== 50 || op
== 54 || op
== 58 || op
== 62)
1641 /* Determine where to set a single step breakpoint while considering
1642 branch prediction. */
1645 mips32_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1647 struct gdbarch
*gdbarch
= regcache
->arch ();
1650 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1651 op
= itype_op (inst
);
1652 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1656 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1667 goto greater_branch
;
1672 else if (op
== 17 && itype_rs (inst
) == 8)
1673 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1674 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 1);
1675 else if (op
== 17 && itype_rs (inst
) == 9
1676 && (itype_rt (inst
) & 2) == 0)
1677 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1678 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 2);
1679 else if (op
== 17 && itype_rs (inst
) == 10
1680 && (itype_rt (inst
) & 2) == 0)
1681 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1682 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 4);
1685 /* The new PC will be alternate mode. */
1689 reg
= jtype_target (inst
) << 2;
1690 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1691 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1693 else if (is_octeon_bbit_op (op
, gdbarch
))
1697 branch_if
= op
== 58 || op
== 62;
1698 bit
= itype_rt (inst
);
1700 /* Take into account the *32 instructions. */
1701 if (op
== 54 || op
== 62)
1704 if (((regcache_raw_get_signed (regcache
,
1705 itype_rs (inst
)) >> bit
) & 1)
1707 pc
+= mips32_relative_offset (inst
) + 4;
1709 pc
+= 8; /* After the delay slot. */
1713 pc
+= 4; /* Not a branch, next instruction is easy. */
1716 { /* This gets way messy. */
1718 /* Further subdivide into SPECIAL, REGIMM and other. */
1719 switch (op
& 0x07) /* Extract bits 28,27,26. */
1721 case 0: /* SPECIAL */
1722 op
= rtype_funct (inst
);
1727 /* Set PC to that address. */
1728 pc
= regcache_raw_get_signed (regcache
, rtype_rs (inst
));
1730 case 12: /* SYSCALL */
1732 mips_gdbarch_tdep
*tdep
1733 = (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1735 if (tdep
->syscall_next_pc
!= NULL
)
1736 pc
= tdep
->syscall_next_pc (get_current_frame ());
1745 break; /* end SPECIAL */
1746 case 1: /* REGIMM */
1748 op
= itype_rt (inst
); /* branch condition */
1753 case 16: /* BLTZAL */
1754 case 18: /* BLTZALL */
1756 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) < 0)
1757 pc
+= mips32_relative_offset (inst
) + 4;
1759 pc
+= 8; /* after the delay slot */
1763 case 17: /* BGEZAL */
1764 case 19: /* BGEZALL */
1765 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) >= 0)
1766 pc
+= mips32_relative_offset (inst
) + 4;
1768 pc
+= 8; /* after the delay slot */
1770 case 0x1c: /* BPOSGE32 */
1771 case 0x1e: /* BPOSGE64 */
1773 if (itype_rs (inst
) == 0)
1775 unsigned int pos
= (op
& 2) ? 64 : 32;
1776 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1779 /* No way to handle; it'll most likely trap anyway. */
1782 if ((regcache_raw_get_unsigned (regcache
,
1783 dspctl
) & 0x7f) >= pos
)
1784 pc
+= mips32_relative_offset (inst
);
1789 /* All of the other instructions in the REGIMM category */
1794 break; /* end REGIMM */
1799 reg
= jtype_target (inst
) << 2;
1800 /* Upper four bits get never changed... */
1801 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1804 case 4: /* BEQ, BEQL */
1806 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) ==
1807 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1808 pc
+= mips32_relative_offset (inst
) + 4;
1812 case 5: /* BNE, BNEL */
1814 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) !=
1815 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1816 pc
+= mips32_relative_offset (inst
) + 4;
1820 case 6: /* BLEZ, BLEZL */
1821 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) <= 0)
1822 pc
+= mips32_relative_offset (inst
) + 4;
1828 greater_branch
: /* BGTZ, BGTZL */
1829 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) > 0)
1830 pc
+= mips32_relative_offset (inst
) + 4;
1837 } /* mips32_next_pc */
1839 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1843 micromips_relative_offset7 (ULONGEST insn
)
1845 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1848 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1852 micromips_relative_offset10 (ULONGEST insn
)
1854 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1857 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1861 micromips_relative_offset16 (ULONGEST insn
)
1863 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1866 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1869 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1873 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1874 return mips_insn_size (ISA_MICROMIPS
, insn
);
1877 /* Calculate the address of the next microMIPS instruction to execute
1878 after the INSN coprocessor 1 conditional branch instruction at the
1879 address PC. COUNT denotes the number of coprocessor condition bits
1880 examined by the branch. */
1883 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1884 ULONGEST insn
, CORE_ADDR pc
, int count
)
1886 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1887 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1888 int tf
= b5s5_op (insn
>> 16) & 1;
1889 int mask
= (1 << count
) - 1;
1894 /* No way to handle; it'll most likely trap anyway. */
1897 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1898 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1900 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1901 pc
+= micromips_relative_offset16 (insn
);
1903 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1908 /* Calculate the address of the next microMIPS instruction to execute
1909 after the instruction at the address PC. */
1912 micromips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1914 struct gdbarch
*gdbarch
= regcache
->arch ();
1917 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1918 pc
+= MIPS_INSN16_SIZE
;
1919 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1921 /* 32-bit instructions. */
1922 case 2 * MIPS_INSN16_SIZE
:
1924 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1925 pc
+= MIPS_INSN16_SIZE
;
1926 switch (micromips_op (insn
>> 16))
1928 case 0x00: /* POOL32A: bits 000000 */
1929 switch (b0s6_op (insn
))
1931 case 0x3c: /* POOL32Axf: bits 000000 ... 111100 */
1932 switch (b6s10_ext (insn
))
1934 case 0x3c: /* JALR: 000000 0000111100 111100 */
1935 case 0x7c: /* JALR.HB: 000000 0001111100 111100 */
1936 case 0x13c: /* JALRS: 000000 0100111100 111100 */
1937 case 0x17c: /* JALRS.HB: 000000 0101111100 111100 */
1938 pc
= regcache_raw_get_signed (regcache
,
1939 b0s5_reg (insn
>> 16));
1941 case 0x22d: /* SYSCALL: 000000 1000101101 111100 */
1943 mips_gdbarch_tdep
*tdep
1944 = (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1946 if (tdep
->syscall_next_pc
!= NULL
)
1947 pc
= tdep
->syscall_next_pc (get_current_frame ());
1955 case 0x10: /* POOL32I: bits 010000 */
1956 switch (b5s5_op (insn
>> 16))
1958 case 0x00: /* BLTZ: bits 010000 00000 */
1959 case 0x01: /* BLTZAL: bits 010000 00001 */
1960 case 0x11: /* BLTZALS: bits 010000 10001 */
1961 if (regcache_raw_get_signed (regcache
,
1962 b0s5_reg (insn
>> 16)) < 0)
1963 pc
+= micromips_relative_offset16 (insn
);
1965 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1968 case 0x02: /* BGEZ: bits 010000 00010 */
1969 case 0x03: /* BGEZAL: bits 010000 00011 */
1970 case 0x13: /* BGEZALS: bits 010000 10011 */
1971 if (regcache_raw_get_signed (regcache
,
1972 b0s5_reg (insn
>> 16)) >= 0)
1973 pc
+= micromips_relative_offset16 (insn
);
1975 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1978 case 0x04: /* BLEZ: bits 010000 00100 */
1979 if (regcache_raw_get_signed (regcache
,
1980 b0s5_reg (insn
>> 16)) <= 0)
1981 pc
+= micromips_relative_offset16 (insn
);
1983 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1986 case 0x05: /* BNEZC: bits 010000 00101 */
1987 if (regcache_raw_get_signed (regcache
,
1988 b0s5_reg (insn
>> 16)) != 0)
1989 pc
+= micromips_relative_offset16 (insn
);
1992 case 0x06: /* BGTZ: bits 010000 00110 */
1993 if (regcache_raw_get_signed (regcache
,
1994 b0s5_reg (insn
>> 16)) > 0)
1995 pc
+= micromips_relative_offset16 (insn
);
1997 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2000 case 0x07: /* BEQZC: bits 010000 00111 */
2001 if (regcache_raw_get_signed (regcache
,
2002 b0s5_reg (insn
>> 16)) == 0)
2003 pc
+= micromips_relative_offset16 (insn
);
2006 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
2007 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
2008 if (((insn
>> 16) & 0x3) == 0x0)
2009 /* BC2F, BC2T: don't know how to handle these. */
2013 case 0x1a: /* BPOSGE64: bits 010000 11010 */
2014 case 0x1b: /* BPOSGE32: bits 010000 11011 */
2016 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
2017 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
2020 /* No way to handle; it'll most likely trap anyway. */
2023 if ((regcache_raw_get_unsigned (regcache
,
2024 dspctl
) & 0x7f) >= pos
)
2025 pc
+= micromips_relative_offset16 (insn
);
2027 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2031 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
2032 /* BC1ANY2F: bits 010000 11100 xxx01 */
2033 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
2034 /* BC1ANY2T: bits 010000 11101 xxx01 */
2035 if (((insn
>> 16) & 0x2) == 0x0)
2036 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
,
2037 ((insn
>> 16) & 0x1) + 1);
2040 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
2041 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
2042 if (((insn
>> 16) & 0x3) == 0x1)
2043 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
, 4);
2048 case 0x1d: /* JALS: bits 011101 */
2049 case 0x35: /* J: bits 110101 */
2050 case 0x3d: /* JAL: bits 111101 */
2051 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
2054 case 0x25: /* BEQ: bits 100101 */
2055 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2056 == regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2057 pc
+= micromips_relative_offset16 (insn
);
2059 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2062 case 0x2d: /* BNE: bits 101101 */
2063 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2064 != regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2065 pc
+= micromips_relative_offset16 (insn
);
2067 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2070 case 0x3c: /* JALX: bits 111100 */
2071 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
2076 /* 16-bit instructions. */
2077 case MIPS_INSN16_SIZE
:
2078 switch (micromips_op (insn
))
2080 case 0x11: /* POOL16C: bits 010001 */
2081 if ((b5s5_op (insn
) & 0x1c) == 0xc)
2082 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
2083 pc
= regcache_raw_get_signed (regcache
, b0s5_reg (insn
));
2084 else if (b5s5_op (insn
) == 0x18)
2085 /* JRADDIUSP: bits 010001 11000 */
2086 pc
= regcache_raw_get_signed (regcache
, MIPS_RA_REGNUM
);
2089 case 0x23: /* BEQZ16: bits 100011 */
2091 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2093 if (regcache_raw_get_signed (regcache
, rs
) == 0)
2094 pc
+= micromips_relative_offset7 (insn
);
2096 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2100 case 0x2b: /* BNEZ16: bits 101011 */
2102 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2104 if (regcache_raw_get_signed (regcache
, rs
) != 0)
2105 pc
+= micromips_relative_offset7 (insn
);
2107 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2111 case 0x33: /* B16: bits 110011 */
2112 pc
+= micromips_relative_offset10 (insn
);
2121 /* Decoding the next place to set a breakpoint is irregular for the
2122 mips 16 variant, but fortunately, there fewer instructions. We have
2123 to cope ith extensions for 16 bit instructions and a pair of actual
2124 32 bit instructions. We dont want to set a single step instruction
2125 on the extend instruction either. */
2127 /* Lots of mips16 instruction formats */
2128 /* Predicting jumps requires itype,ritype,i8type
2129 and their extensions extItype,extritype,extI8type. */
2130 enum mips16_inst_fmts
2132 itype
, /* 0 immediate 5,10 */
2133 ritype
, /* 1 5,3,8 */
2134 rrtype
, /* 2 5,3,3,5 */
2135 rritype
, /* 3 5,3,3,5 */
2136 rrrtype
, /* 4 5,3,3,3,2 */
2137 rriatype
, /* 5 5,3,3,1,4 */
2138 shifttype
, /* 6 5,3,3,3,2 */
2139 i8type
, /* 7 5,3,8 */
2140 i8movtype
, /* 8 5,3,3,5 */
2141 i8mov32rtype
, /* 9 5,3,5,3 */
2142 i64type
, /* 10 5,3,8 */
2143 ri64type
, /* 11 5,3,3,5 */
2144 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
2145 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
2146 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
2147 extRRItype
, /* 15 5,5,5,5,3,3,5 */
2148 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
2149 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
2150 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
2151 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
2152 extRi64type
, /* 20 5,6,5,5,3,3,5 */
2153 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2155 /* I am heaping all the fields of the formats into one structure and
2156 then, only the fields which are involved in instruction extension. */
2160 unsigned int regx
; /* Function in i8 type. */
2165 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2166 for the bits which make up the immediate extension. */
2169 extended_offset (unsigned int extension
)
2173 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
2175 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
2177 value
|= extension
& 0x1f; /* Extract 4:0. */
2182 /* Only call this function if you know that this is an extendable
2183 instruction. It won't malfunction, but why make excess remote memory
2184 references? If the immediate operands get sign extended or something,
2185 do it after the extension is performed. */
2186 /* FIXME: Every one of these cases needs to worry about sign extension
2187 when the offset is to be used in relative addressing. */
2190 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2192 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2195 pc
= unmake_compact_addr (pc
); /* Clear the low order bit. */
2196 target_read_memory (pc
, buf
, 2);
2197 return extract_unsigned_integer (buf
, 2, byte_order
);
2201 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
2202 unsigned int extension
,
2204 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2209 switch (insn_format
)
2216 value
= extended_offset ((extension
<< 16) | inst
);
2217 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2221 value
= inst
& 0x7ff;
2222 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2231 { /* A register identifier and an offset. */
2232 /* Most of the fields are the same as I type but the
2233 immediate value is of a different length. */
2237 value
= extended_offset ((extension
<< 16) | inst
);
2238 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2242 value
= inst
& 0xff; /* 8 bits */
2243 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2246 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2252 unsigned long value
;
2253 unsigned int nexthalf
;
2254 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2255 value
= value
<< 16;
2256 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2257 /* Low bit still set. */
2265 internal_error (__FILE__
, __LINE__
, _("bad switch"));
2267 upk
->offset
= offset
;
2273 /* Calculate the destination of a branch whose 16-bit opcode word is at PC,
2274 and having a signed 16-bit OFFSET. */
2277 add_offset_16 (CORE_ADDR pc
, int offset
)
2279 return pc
+ (offset
<< 1) + 2;
2283 extended_mips16_next_pc (regcache
*regcache
, CORE_ADDR pc
,
2284 unsigned int extension
, unsigned int insn
)
2286 struct gdbarch
*gdbarch
= regcache
->arch ();
2287 int op
= (insn
>> 11);
2290 case 2: /* Branch */
2292 struct upk_mips16 upk
;
2293 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2294 pc
= add_offset_16 (pc
, upk
.offset
);
2297 case 3: /* JAL , JALX - Watch out, these are 32 bit
2300 struct upk_mips16 upk
;
2301 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2302 pc
= ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)) | (upk
.offset
<< 2);
2303 if ((insn
>> 10) & 0x01) /* Exchange mode */
2304 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2311 struct upk_mips16 upk
;
2313 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2314 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2316 pc
= add_offset_16 (pc
, upk
.offset
);
2323 struct upk_mips16 upk
;
2325 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2326 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2328 pc
= add_offset_16 (pc
, upk
.offset
);
2333 case 12: /* I8 Formats btez btnez */
2335 struct upk_mips16 upk
;
2337 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2338 /* upk.regx contains the opcode */
2339 /* Test register is 24 */
2340 reg
= regcache_raw_get_signed (regcache
, 24);
2341 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2342 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2343 pc
= add_offset_16 (pc
, upk
.offset
);
2348 case 29: /* RR Formats JR, JALR, JALR-RA */
2350 struct upk_mips16 upk
;
2351 /* upk.fmt = rrtype; */
2356 upk
.regx
= (insn
>> 8) & 0x07;
2357 upk
.regy
= (insn
>> 5) & 0x07;
2358 if ((upk
.regy
& 1) == 0)
2359 reg
= mips_reg3_to_reg
[upk
.regx
];
2361 reg
= 31; /* Function return instruction. */
2362 pc
= regcache_raw_get_signed (regcache
, reg
);
2369 /* This is an instruction extension. Fetch the real instruction
2370 (which follows the extension) and decode things based on
2374 pc
= extended_mips16_next_pc (regcache
, pc
, insn
,
2375 fetch_mips_16 (gdbarch
, pc
));
2388 mips16_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2390 struct gdbarch
*gdbarch
= regcache
->arch ();
2391 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2392 return extended_mips16_next_pc (regcache
, pc
, 0, insn
);
2395 /* The mips_next_pc function supports single_step when the remote
2396 target monitor or stub is not developed enough to do a single_step.
2397 It works by decoding the current instruction and predicting where a
2398 branch will go. This isn't hard because all the data is available.
2399 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2401 mips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2403 struct gdbarch
*gdbarch
= regcache
->arch ();
2405 if (mips_pc_is_mips16 (gdbarch
, pc
))
2406 return mips16_next_pc (regcache
, pc
);
2407 else if (mips_pc_is_micromips (gdbarch
, pc
))
2408 return micromips_next_pc (regcache
, pc
);
2410 return mips32_next_pc (regcache
, pc
);
2413 /* Return non-zero if the MIPS16 instruction INSN is a compact branch
2417 mips16_instruction_is_compact_branch (unsigned short insn
)
2419 switch (insn
& 0xf800)
2422 return (insn
& 0x009f) == 0x80; /* JALRC/JRC */
2424 return (insn
& 0x0600) == 0; /* BTNEZ/BTEQZ */
2425 case 0x2800: /* BNEZ */
2426 case 0x2000: /* BEQZ */
2427 case 0x1000: /* B */
2434 /* Return non-zero if the microMIPS instruction INSN is a compact branch
2438 micromips_instruction_is_compact_branch (unsigned short insn
)
2440 switch (micromips_op (insn
))
2442 case 0x11: /* POOL16C: bits 010001 */
2443 return (b5s5_op (insn
) == 0x18
2444 /* JRADDIUSP: bits 010001 11000 */
2445 || b5s5_op (insn
) == 0xd);
2446 /* JRC: bits 010011 01101 */
2447 case 0x10: /* POOL32I: bits 010000 */
2448 return (b5s5_op (insn
) & 0x1d) == 0x5;
2449 /* BEQZC/BNEZC: bits 010000 001x1 */
2455 struct mips_frame_cache
2458 trad_frame_saved_reg
*saved_regs
;
2461 /* Set a register's saved stack address in temp_saved_regs. If an
2462 address has already been set for this register, do nothing; this
2463 way we will only recognize the first save of a given register in a
2466 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2467 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2468 Strictly speaking, only the second range is used as it is only second
2469 range (the ABI instead of ISA registers) that comes into play when finding
2470 saved registers in a frame. */
2473 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2474 int regnum
, CORE_ADDR offset
)
2476 if (this_cache
!= NULL
2477 && this_cache
->saved_regs
[regnum
].is_realreg ()
2478 && this_cache
->saved_regs
[regnum
].realreg () == regnum
)
2480 this_cache
->saved_regs
[regnum
+ 0
2481 * gdbarch_num_regs (gdbarch
)].set_addr (offset
);
2482 this_cache
->saved_regs
[regnum
+ 1
2483 * gdbarch_num_regs (gdbarch
)].set_addr (offset
);
2488 /* Fetch the immediate value from a MIPS16 instruction.
2489 If the previous instruction was an EXTEND, use it to extend
2490 the upper bits of the immediate value. This is a helper function
2491 for mips16_scan_prologue. */
2494 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2495 unsigned short inst
, /* current instruction */
2496 int nbits
, /* number of bits in imm field */
2497 int scale
, /* scale factor to be applied to imm */
2498 int is_signed
) /* is the imm field signed? */
2502 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2504 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2505 if (offset
& 0x8000) /* check for negative extend */
2506 offset
= 0 - (0x10000 - (offset
& 0xffff));
2507 return offset
| (inst
& 0x1f);
2511 int max_imm
= 1 << nbits
;
2512 int mask
= max_imm
- 1;
2513 int sign_bit
= max_imm
>> 1;
2515 offset
= inst
& mask
;
2516 if (is_signed
&& (offset
& sign_bit
))
2517 offset
= 0 - (max_imm
- offset
);
2518 return offset
* scale
;
2523 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2524 the associated FRAME_CACHE if not null.
2525 Return the address of the first instruction past the prologue. */
2528 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2529 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2530 struct frame_info
*this_frame
,
2531 struct mips_frame_cache
*this_cache
)
2533 int prev_non_prologue_insn
= 0;
2534 int this_non_prologue_insn
;
2535 int non_prologue_insns
= 0;
2538 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2540 long frame_offset
= 0; /* Size of stack frame. */
2541 long frame_adjust
= 0; /* Offset of FP from SP. */
2542 int frame_reg
= MIPS_SP_REGNUM
;
2543 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2544 unsigned inst
= 0; /* current instruction */
2545 unsigned entry_inst
= 0; /* the entry instruction */
2546 unsigned save_inst
= 0; /* the save instruction */
2547 int prev_delay_slot
= 0;
2551 int extend_bytes
= 0;
2552 int prev_extend_bytes
= 0;
2553 CORE_ADDR end_prologue_addr
;
2555 /* Can be called when there's no process, and hence when there's no
2557 if (this_frame
!= NULL
)
2558 sp
= get_frame_register_signed (this_frame
,
2559 gdbarch_num_regs (gdbarch
)
2564 if (limit_pc
> start_pc
+ 200)
2565 limit_pc
= start_pc
+ 200;
2568 /* Permit at most one non-prologue non-control-transfer instruction
2569 in the middle which may have been reordered by the compiler for
2571 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2573 this_non_prologue_insn
= 0;
2576 /* Save the previous instruction. If it's an EXTEND, we'll extract
2577 the immediate offset extension from it in mips16_get_imm. */
2580 /* Fetch and decode the instruction. */
2581 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2584 /* Normally we ignore extend instructions. However, if it is
2585 not followed by a valid prologue instruction, then this
2586 instruction is not part of the prologue either. We must
2587 remember in this case to adjust the end_prologue_addr back
2589 if ((inst
& 0xf800) == 0xf000) /* extend */
2591 extend_bytes
= MIPS_INSN16_SIZE
;
2595 prev_extend_bytes
= extend_bytes
;
2598 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2599 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2601 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2602 if (offset
< 0) /* Negative stack adjustment? */
2603 frame_offset
-= offset
;
2605 /* Exit loop if a positive stack adjustment is found, which
2606 usually means that the stack cleanup code in the function
2607 epilogue is reached. */
2610 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2612 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2613 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2614 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2616 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2618 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2619 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2620 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2622 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2624 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2625 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2627 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2629 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2630 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2632 else if (inst
== 0x673d) /* move $s1, $sp */
2637 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2639 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2640 frame_addr
= sp
+ offset
;
2642 frame_adjust
= offset
;
2644 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2646 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2647 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2648 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2650 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2652 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2653 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2654 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2656 else if ((inst
& 0xf81f) == 0xe809
2657 && (inst
& 0x700) != 0x700) /* entry */
2658 entry_inst
= inst
; /* Save for later processing. */
2659 else if ((inst
& 0xff80) == 0x6480) /* save */
2661 save_inst
= inst
; /* Save for later processing. */
2662 if (prev_extend_bytes
) /* extend */
2663 save_inst
|= prev_inst
<< 16;
2665 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2667 /* This instruction is part of the prologue, but we don't
2668 need to do anything special to handle it. */
2670 else if (mips16_instruction_has_delay_slot (inst
, 0))
2671 /* JAL/JALR/JALX/JR */
2673 /* The instruction in the delay slot can be a part
2674 of the prologue, so move forward once more. */
2676 if (mips16_instruction_has_delay_slot (inst
, 1))
2679 prev_extend_bytes
= MIPS_INSN16_SIZE
;
2680 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2685 this_non_prologue_insn
= 1;
2688 non_prologue_insns
+= this_non_prologue_insn
;
2690 /* A jump or branch, or enough non-prologue insns seen? If so,
2691 then we must have reached the end of the prologue by now. */
2692 if (prev_delay_slot
|| non_prologue_insns
> 1
2693 || mips16_instruction_is_compact_branch (inst
))
2696 prev_non_prologue_insn
= this_non_prologue_insn
;
2697 prev_delay_slot
= in_delay_slot
;
2698 prev_pc
= cur_pc
- prev_extend_bytes
;
2701 /* The entry instruction is typically the first instruction in a function,
2702 and it stores registers at offsets relative to the value of the old SP
2703 (before the prologue). But the value of the sp parameter to this
2704 function is the new SP (after the prologue has been executed). So we
2705 can't calculate those offsets until we've seen the entire prologue,
2706 and can calculate what the old SP must have been. */
2707 if (entry_inst
!= 0)
2709 int areg_count
= (entry_inst
>> 8) & 7;
2710 int sreg_count
= (entry_inst
>> 6) & 3;
2712 /* The entry instruction always subtracts 32 from the SP. */
2715 /* Now we can calculate what the SP must have been at the
2716 start of the function prologue. */
2719 /* Check if a0-a3 were saved in the caller's argument save area. */
2720 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2722 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2723 offset
+= mips_abi_regsize (gdbarch
);
2726 /* Check if the ra register was pushed on the stack. */
2728 if (entry_inst
& 0x20)
2730 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2731 offset
-= mips_abi_regsize (gdbarch
);
2734 /* Check if the s0 and s1 registers were pushed on the stack. */
2735 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2737 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2738 offset
-= mips_abi_regsize (gdbarch
);
2742 /* The SAVE instruction is similar to ENTRY, except that defined by the
2743 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2744 size of the frame is specified as an immediate field of instruction
2745 and an extended variation exists which lets additional registers and
2746 frame space to be specified. The instruction always treats registers
2747 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2748 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2750 static int args_table
[16] = {
2751 0, 0, 0, 0, 1, 1, 1, 1,
2752 2, 2, 2, 0, 3, 3, 4, -1,
2754 static int astatic_table
[16] = {
2755 0, 1, 2, 3, 0, 1, 2, 3,
2756 0, 1, 2, 4, 0, 1, 0, -1,
2758 int aregs
= (save_inst
>> 16) & 0xf;
2759 int xsregs
= (save_inst
>> 24) & 0x7;
2760 int args
= args_table
[aregs
];
2761 int astatic
= astatic_table
[aregs
];
2766 warning (_("Invalid number of argument registers encoded in SAVE."));
2771 warning (_("Invalid number of static registers encoded in SAVE."));
2775 /* For standard SAVE the frame size of 0 means 128. */
2776 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2777 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2780 frame_offset
+= frame_size
;
2782 /* Now we can calculate what the SP must have been at the
2783 start of the function prologue. */
2786 /* Check if A0-A3 were saved in the caller's argument save area. */
2787 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2789 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2790 offset
+= mips_abi_regsize (gdbarch
);
2795 /* Check if the RA register was pushed on the stack. */
2796 if (save_inst
& 0x40)
2798 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2799 offset
-= mips_abi_regsize (gdbarch
);
2802 /* Check if the S8 register was pushed on the stack. */
2805 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2806 offset
-= mips_abi_regsize (gdbarch
);
2809 /* Check if S2-S7 were pushed on the stack. */
2810 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2812 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2813 offset
-= mips_abi_regsize (gdbarch
);
2816 /* Check if the S1 register was pushed on the stack. */
2817 if (save_inst
& 0x10)
2819 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2820 offset
-= mips_abi_regsize (gdbarch
);
2822 /* Check if the S0 register was pushed on the stack. */
2823 if (save_inst
& 0x20)
2825 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2826 offset
-= mips_abi_regsize (gdbarch
);
2829 /* Check if A0-A3 were pushed on the stack. */
2830 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2832 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2833 offset
-= mips_abi_regsize (gdbarch
);
2837 if (this_cache
!= NULL
)
2840 (get_frame_register_signed (this_frame
,
2841 gdbarch_num_regs (gdbarch
) + frame_reg
)
2842 + frame_offset
- frame_adjust
);
2843 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2844 be able to get rid of the assignment below, evetually. But it's
2845 still needed for now. */
2846 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2847 + mips_regnum (gdbarch
)->pc
]
2848 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2851 /* Set end_prologue_addr to the address of the instruction immediately
2852 after the last one we scanned. Unless the last one looked like a
2853 non-prologue instruction (and we looked ahead), in which case use
2854 its address instead. */
2855 end_prologue_addr
= (prev_non_prologue_insn
|| prev_delay_slot
2856 ? prev_pc
: cur_pc
- prev_extend_bytes
);
2858 return end_prologue_addr
;
2861 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2862 Procedures that use the 32-bit instruction set are handled by the
2863 mips_insn32 unwinder. */
2865 static struct mips_frame_cache
*
2866 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2868 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2869 struct mips_frame_cache
*cache
;
2871 if ((*this_cache
) != NULL
)
2872 return (struct mips_frame_cache
*) (*this_cache
);
2873 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2874 (*this_cache
) = cache
;
2875 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2877 /* Analyze the function prologue. */
2879 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2880 CORE_ADDR start_addr
;
2882 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2883 if (start_addr
== 0)
2884 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2885 /* We can't analyze the prologue if we couldn't find the begining
2887 if (start_addr
== 0)
2890 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
2891 (struct mips_frame_cache
*) *this_cache
);
2894 /* gdbarch_sp_regnum contains the value and not the address. */
2895 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2896 + MIPS_SP_REGNUM
].set_value (cache
->base
);
2898 return (struct mips_frame_cache
*) (*this_cache
);
2902 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2903 struct frame_id
*this_id
)
2905 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2907 /* This marks the outermost frame. */
2908 if (info
->base
== 0)
2910 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2913 static struct value
*
2914 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2915 void **this_cache
, int regnum
)
2917 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2919 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2923 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2924 struct frame_info
*this_frame
, void **this_cache
)
2926 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2927 CORE_ADDR pc
= get_frame_pc (this_frame
);
2928 if (mips_pc_is_mips16 (gdbarch
, pc
))
2933 static const struct frame_unwind mips_insn16_frame_unwind
=
2935 "mips insn16 prologue",
2937 default_frame_unwind_stop_reason
,
2938 mips_insn16_frame_this_id
,
2939 mips_insn16_frame_prev_register
,
2941 mips_insn16_frame_sniffer
2945 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2948 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2953 static const struct frame_base mips_insn16_frame_base
=
2955 &mips_insn16_frame_unwind
,
2956 mips_insn16_frame_base_address
,
2957 mips_insn16_frame_base_address
,
2958 mips_insn16_frame_base_address
2961 static const struct frame_base
*
2962 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2964 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2965 CORE_ADDR pc
= get_frame_pc (this_frame
);
2966 if (mips_pc_is_mips16 (gdbarch
, pc
))
2967 return &mips_insn16_frame_base
;
2972 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2973 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2974 interpreted directly, and then multiplied by 4. */
2977 micromips_decode_imm9 (int imm
)
2979 imm
= (imm
^ 0x100) - 0x100;
2980 if (imm
> -3 && imm
< 2)
2985 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2986 the address of the first instruction past the prologue. */
2989 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2990 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2991 struct frame_info
*this_frame
,
2992 struct mips_frame_cache
*this_cache
)
2994 CORE_ADDR end_prologue_addr
;
2995 int prev_non_prologue_insn
= 0;
2996 int frame_reg
= MIPS_SP_REGNUM
;
2997 int this_non_prologue_insn
;
2998 int non_prologue_insns
= 0;
2999 long frame_offset
= 0; /* Size of stack frame. */
3000 long frame_adjust
= 0; /* Offset of FP from SP. */
3001 int prev_delay_slot
= 0;
3005 ULONGEST insn
; /* current instruction */
3009 long v1_off
= 0; /* The assumption is LUI will replace it. */
3020 /* Can be called when there's no process, and hence when there's no
3022 if (this_frame
!= NULL
)
3023 sp
= get_frame_register_signed (this_frame
,
3024 gdbarch_num_regs (gdbarch
)
3029 if (limit_pc
> start_pc
+ 200)
3030 limit_pc
= start_pc
+ 200;
3033 /* Permit at most one non-prologue non-control-transfer instruction
3034 in the middle which may have been reordered by the compiler for
3036 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
3038 this_non_prologue_insn
= 0;
3042 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
3043 loc
+= MIPS_INSN16_SIZE
;
3044 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
3046 /* 32-bit instructions. */
3047 case 2 * MIPS_INSN16_SIZE
:
3049 insn
|= mips_fetch_instruction (gdbarch
,
3050 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
3051 loc
+= MIPS_INSN16_SIZE
;
3052 switch (micromips_op (insn
>> 16))
3054 /* Record $sp/$fp adjustment. */
3055 /* Discard (D)ADDU $gp,$jp used for PIC code. */
3056 case 0x0: /* POOL32A: bits 000000 */
3057 case 0x16: /* POOL32S: bits 010110 */
3058 op
= b0s11_op (insn
);
3059 sreg
= b0s5_reg (insn
>> 16);
3060 treg
= b5s5_reg (insn
>> 16);
3061 dreg
= b11s5_reg (insn
);
3063 /* SUBU: bits 000000 00111010000 */
3064 /* DSUBU: bits 010110 00111010000 */
3065 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
3067 /* (D)SUBU $sp, $v1 */
3069 else if (op
!= 0x150
3070 /* ADDU: bits 000000 00101010000 */
3071 /* DADDU: bits 010110 00101010000 */
3072 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
3073 this_non_prologue_insn
= 1;
3076 case 0x8: /* POOL32B: bits 001000 */
3077 op
= b12s4_op (insn
);
3078 breg
= b0s5_reg (insn
>> 16);
3079 reglist
= sreg
= b5s5_reg (insn
>> 16);
3080 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
3081 if ((op
== 0x9 || op
== 0xc)
3082 /* SWP: bits 001000 1001 */
3083 /* SDP: bits 001000 1100 */
3084 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
3085 /* S[DW]P reg,offset($sp) */
3087 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
3088 set_reg_offset (gdbarch
, this_cache
,
3090 set_reg_offset (gdbarch
, this_cache
,
3091 sreg
+ 1, sp
+ offset
+ s
);
3093 else if ((op
== 0xd || op
== 0xf)
3094 /* SWM: bits 001000 1101 */
3095 /* SDM: bits 001000 1111 */
3096 && breg
== MIPS_SP_REGNUM
3097 /* SWM reglist,offset($sp) */
3098 && ((reglist
>= 1 && reglist
<= 9)
3099 || (reglist
>= 16 && reglist
<= 25)))
3101 int sreglist
= std::min(reglist
& 0xf, 8);
3103 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
3104 for (i
= 0; i
< sreglist
; i
++)
3105 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
3106 if ((reglist
& 0xf) > 8)
3107 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
3108 if ((reglist
& 0x10) == 0x10)
3109 set_reg_offset (gdbarch
, this_cache
,
3110 MIPS_RA_REGNUM
, sp
+ s
* i
++);
3113 this_non_prologue_insn
= 1;
3116 /* Record $sp/$fp adjustment. */
3117 /* Discard (D)ADDIU $gp used for PIC code. */
3118 case 0xc: /* ADDIU: bits 001100 */
3119 case 0x17: /* DADDIU: bits 010111 */
3120 sreg
= b0s5_reg (insn
>> 16);
3121 dreg
= b5s5_reg (insn
>> 16);
3122 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3123 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
3124 /* (D)ADDIU $sp, imm */
3126 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3127 /* (D)ADDIU $fp, $sp, imm */
3129 frame_adjust
= offset
;
3132 else if (sreg
!= 28 || dreg
!= 28)
3133 /* (D)ADDIU $gp, imm */
3134 this_non_prologue_insn
= 1;
3137 /* LUI $v1 is used for larger $sp adjustments. */
3138 /* Discard LUI $gp used for PIC code. */
3139 case 0x10: /* POOL32I: bits 010000 */
3140 if (b5s5_op (insn
>> 16) == 0xd
3141 /* LUI: bits 010000 001101 */
3142 && b0s5_reg (insn
>> 16) == 3)
3144 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
3145 else if (b5s5_op (insn
>> 16) != 0xd
3146 /* LUI: bits 010000 001101 */
3147 || b0s5_reg (insn
>> 16) != 28)
3149 this_non_prologue_insn
= 1;
3152 /* ORI $v1 is used for larger $sp adjustments. */
3153 case 0x14: /* ORI: bits 010100 */
3154 sreg
= b0s5_reg (insn
>> 16);
3155 dreg
= b5s5_reg (insn
>> 16);
3156 if (sreg
== 3 && dreg
== 3)
3158 v1_off
|= b0s16_imm (insn
);
3160 this_non_prologue_insn
= 1;
3163 case 0x26: /* SWC1: bits 100110 */
3164 case 0x2e: /* SDC1: bits 101110 */
3165 breg
= b0s5_reg (insn
>> 16);
3166 if (breg
!= MIPS_SP_REGNUM
)
3167 /* S[DW]C1 reg,offset($sp) */
3168 this_non_prologue_insn
= 1;
3171 case 0x36: /* SD: bits 110110 */
3172 case 0x3e: /* SW: bits 111110 */
3173 breg
= b0s5_reg (insn
>> 16);
3174 sreg
= b5s5_reg (insn
>> 16);
3175 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3176 if (breg
== MIPS_SP_REGNUM
)
3177 /* S[DW] reg,offset($sp) */
3178 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3180 this_non_prologue_insn
= 1;
3184 /* The instruction in the delay slot can be a part
3185 of the prologue, so move forward once more. */
3186 if (micromips_instruction_has_delay_slot (insn
, 0))
3189 this_non_prologue_insn
= 1;
3195 /* 16-bit instructions. */
3196 case MIPS_INSN16_SIZE
:
3197 switch (micromips_op (insn
))
3199 case 0x3: /* MOVE: bits 000011 */
3200 sreg
= b0s5_reg (insn
);
3201 dreg
= b5s5_reg (insn
);
3202 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3205 else if ((sreg
& 0x1c) != 0x4)
3206 /* MOVE reg, $a0-$a3 */
3207 this_non_prologue_insn
= 1;
3210 case 0x11: /* POOL16C: bits 010001 */
3211 if (b6s4_op (insn
) == 0x5)
3212 /* SWM: bits 010001 0101 */
3214 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
3215 reglist
= b4s2_regl (insn
);
3216 for (i
= 0; i
<= reglist
; i
++)
3217 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
3218 set_reg_offset (gdbarch
, this_cache
,
3219 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
3222 this_non_prologue_insn
= 1;
3225 case 0x13: /* POOL16D: bits 010011 */
3226 if ((insn
& 0x1) == 0x1)
3227 /* ADDIUSP: bits 010011 1 */
3228 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
3229 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
3230 /* ADDIUS5: bits 010011 0 */
3231 /* ADDIUS5 $sp, imm */
3232 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
3234 this_non_prologue_insn
= 1;
3237 case 0x32: /* SWSP: bits 110010 */
3238 offset
= b0s5_imm (insn
) << 2;
3239 sreg
= b5s5_reg (insn
);
3240 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3244 /* The instruction in the delay slot can be a part
3245 of the prologue, so move forward once more. */
3246 if (micromips_instruction_has_delay_slot (insn
<< 16, 0))
3249 this_non_prologue_insn
= 1;
3255 frame_offset
-= sp_adj
;
3257 non_prologue_insns
+= this_non_prologue_insn
;
3259 /* A jump or branch, enough non-prologue insns seen or positive
3260 stack adjustment? If so, then we must have reached the end
3261 of the prologue by now. */
3262 if (prev_delay_slot
|| non_prologue_insns
> 1 || sp_adj
> 0
3263 || micromips_instruction_is_compact_branch (insn
))
3266 prev_non_prologue_insn
= this_non_prologue_insn
;
3267 prev_delay_slot
= in_delay_slot
;
3271 if (this_cache
!= NULL
)
3274 (get_frame_register_signed (this_frame
,
3275 gdbarch_num_regs (gdbarch
) + frame_reg
)
3276 + frame_offset
- frame_adjust
);
3277 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3278 be able to get rid of the assignment below, evetually. But it's
3279 still needed for now. */
3280 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3281 + mips_regnum (gdbarch
)->pc
]
3282 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
3285 /* Set end_prologue_addr to the address of the instruction immediately
3286 after the last one we scanned. Unless the last one looked like a
3287 non-prologue instruction (and we looked ahead), in which case use
3288 its address instead. */
3290 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3292 return end_prologue_addr
;
3295 /* Heuristic unwinder for procedures using microMIPS instructions.
3296 Procedures that use the 32-bit instruction set are handled by the
3297 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3299 static struct mips_frame_cache
*
3300 mips_micro_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3302 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3303 struct mips_frame_cache
*cache
;
3305 if ((*this_cache
) != NULL
)
3306 return (struct mips_frame_cache
*) (*this_cache
);
3308 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3309 (*this_cache
) = cache
;
3310 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3312 /* Analyze the function prologue. */
3314 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3315 CORE_ADDR start_addr
;
3317 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3318 if (start_addr
== 0)
3319 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3320 /* We can't analyze the prologue if we couldn't find the begining
3322 if (start_addr
== 0)
3325 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3326 (struct mips_frame_cache
*) *this_cache
);
3329 /* gdbarch_sp_regnum contains the value and not the address. */
3330 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3331 + MIPS_SP_REGNUM
].set_value (cache
->base
);
3333 return (struct mips_frame_cache
*) (*this_cache
);
3337 mips_micro_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3338 struct frame_id
*this_id
)
3340 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3342 /* This marks the outermost frame. */
3343 if (info
->base
== 0)
3345 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3348 static struct value
*
3349 mips_micro_frame_prev_register (struct frame_info
*this_frame
,
3350 void **this_cache
, int regnum
)
3352 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3354 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3358 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3359 struct frame_info
*this_frame
, void **this_cache
)
3361 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3362 CORE_ADDR pc
= get_frame_pc (this_frame
);
3364 if (mips_pc_is_micromips (gdbarch
, pc
))
3369 static const struct frame_unwind mips_micro_frame_unwind
=
3371 "mips micro prologue",
3373 default_frame_unwind_stop_reason
,
3374 mips_micro_frame_this_id
,
3375 mips_micro_frame_prev_register
,
3377 mips_micro_frame_sniffer
3381 mips_micro_frame_base_address (struct frame_info
*this_frame
,
3384 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3389 static const struct frame_base mips_micro_frame_base
=
3391 &mips_micro_frame_unwind
,
3392 mips_micro_frame_base_address
,
3393 mips_micro_frame_base_address
,
3394 mips_micro_frame_base_address
3397 static const struct frame_base
*
3398 mips_micro_frame_base_sniffer (struct frame_info
*this_frame
)
3400 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3401 CORE_ADDR pc
= get_frame_pc (this_frame
);
3403 if (mips_pc_is_micromips (gdbarch
, pc
))
3404 return &mips_micro_frame_base
;
3409 /* Mark all the registers as unset in the saved_regs array
3410 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3413 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3415 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3419 const int num_regs
= gdbarch_num_regs (gdbarch
);
3422 /* Reset the register values to their default state. Register i's value
3423 is in register i. */
3424 for (i
= 0; i
< num_regs
; i
++)
3425 this_cache
->saved_regs
[i
].set_realreg (i
);
3429 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3430 the associated FRAME_CACHE if not null.
3431 Return the address of the first instruction past the prologue. */
3434 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3435 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3436 struct frame_info
*this_frame
,
3437 struct mips_frame_cache
*this_cache
)
3439 int prev_non_prologue_insn
;
3440 int this_non_prologue_insn
;
3441 int non_prologue_insns
;
3442 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3444 int prev_delay_slot
;
3449 int frame_reg
= MIPS_SP_REGNUM
;
3451 CORE_ADDR end_prologue_addr
;
3452 int seen_sp_adjust
= 0;
3453 int load_immediate_bytes
= 0;
3455 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3457 /* Can be called when there's no process, and hence when there's no
3459 if (this_frame
!= NULL
)
3460 sp
= get_frame_register_signed (this_frame
,
3461 gdbarch_num_regs (gdbarch
)
3466 if (limit_pc
> start_pc
+ 200)
3467 limit_pc
= start_pc
+ 200;
3470 prev_non_prologue_insn
= 0;
3471 non_prologue_insns
= 0;
3472 prev_delay_slot
= 0;
3475 /* Permit at most one non-prologue non-control-transfer instruction
3476 in the middle which may have been reordered by the compiler for
3479 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3481 unsigned long inst
, high_word
;
3485 this_non_prologue_insn
= 0;
3488 /* Fetch the instruction. */
3489 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3492 /* Save some code by pre-extracting some useful fields. */
3493 high_word
= (inst
>> 16) & 0xffff;
3494 offset
= ((inst
& 0xffff) ^ 0x8000) - 0x8000;
3495 reg
= high_word
& 0x1f;
3497 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3498 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3499 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3501 if (offset
< 0) /* Negative stack adjustment? */
3502 frame_offset
-= offset
;
3504 /* Exit loop if a positive stack adjustment is found, which
3505 usually means that the stack cleanup code in the function
3506 epilogue is reached. */
3510 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3511 && !regsize_is_64_bits
)
3513 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3515 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3516 && regsize_is_64_bits
)
3518 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3519 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3521 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3523 /* Old gcc frame, r30 is virtual frame pointer. */
3524 if (offset
!= frame_offset
)
3525 frame_addr
= sp
+ offset
;
3526 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3528 unsigned alloca_adjust
;
3531 frame_addr
= get_frame_register_signed
3532 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3535 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ offset
));
3536 if (alloca_adjust
> 0)
3538 /* FP > SP + frame_size. This may be because of
3539 an alloca or somethings similar. Fix sp to
3540 "pre-alloca" value, and try again. */
3541 sp
+= alloca_adjust
;
3542 /* Need to reset the status of all registers. Otherwise,
3543 we will hit a guard that prevents the new address
3544 for each register to be recomputed during the second
3546 reset_saved_regs (gdbarch
, this_cache
);
3551 /* move $30,$sp. With different versions of gas this will be either
3552 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3553 Accept any one of these. */
3554 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3556 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3557 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3559 unsigned alloca_adjust
;
3562 frame_addr
= get_frame_register_signed
3563 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3565 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3566 if (alloca_adjust
> 0)
3568 /* FP > SP + frame_size. This may be because of
3569 an alloca or somethings similar. Fix sp to
3570 "pre-alloca" value, and try again. */
3572 /* Need to reset the status of all registers. Otherwise,
3573 we will hit a guard that prevents the new address
3574 for each register to be recomputed during the second
3576 reset_saved_regs (gdbarch
, this_cache
);
3581 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3582 && !regsize_is_64_bits
)
3584 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
3586 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3587 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3588 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3589 || high_word
== 0x3c1c /* lui $gp,n */
3590 || high_word
== 0x279c /* addiu $gp,$gp,n */
3591 || high_word
== 0x679c /* daddiu $gp,$gp,n */
3592 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3593 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3594 || inst
== 0x0399e02d /* daddu $gp,$gp,$t9 */
3595 || inst
== 0x033ce02d /* daddu $gp,$t9,$gp */
3598 /* These instructions are part of the prologue, but we don't
3599 need to do anything special to handle them. */
3601 /* The instructions below load $at or $t0 with an immediate
3602 value in preparation for a stack adjustment via
3603 subu $sp,$sp,[$at,$t0]. These instructions could also
3604 initialize a local variable, so we accept them only before
3605 a stack adjustment instruction was seen. */
3606 else if (!seen_sp_adjust
3608 && (high_word
== 0x3c01 /* lui $at,n */
3609 || high_word
== 0x3c08 /* lui $t0,n */
3610 || high_word
== 0x3421 /* ori $at,$at,n */
3611 || high_word
== 0x3508 /* ori $t0,$t0,n */
3612 || high_word
== 0x3401 /* ori $at,$zero,n */
3613 || high_word
== 0x3408 /* ori $t0,$zero,n */
3616 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3618 /* Check for branches and jumps. The instruction in the delay
3619 slot can be a part of the prologue, so move forward once more. */
3620 else if (mips32_instruction_has_delay_slot (gdbarch
, inst
))
3624 /* This instruction is not an instruction typically found
3625 in a prologue, so we must have reached the end of the
3629 this_non_prologue_insn
= 1;
3632 non_prologue_insns
+= this_non_prologue_insn
;
3634 /* A jump or branch, or enough non-prologue insns seen? If so,
3635 then we must have reached the end of the prologue by now. */
3636 if (prev_delay_slot
|| non_prologue_insns
> 1)
3639 prev_non_prologue_insn
= this_non_prologue_insn
;
3640 prev_delay_slot
= in_delay_slot
;
3644 if (this_cache
!= NULL
)
3647 (get_frame_register_signed (this_frame
,
3648 gdbarch_num_regs (gdbarch
) + frame_reg
)
3650 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3651 this assignment below, eventually. But it's still needed
3653 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3654 + mips_regnum (gdbarch
)->pc
]
3655 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3659 /* Set end_prologue_addr to the address of the instruction immediately
3660 after the last one we scanned. Unless the last one looked like a
3661 non-prologue instruction (and we looked ahead), in which case use
3662 its address instead. */
3664 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3666 /* In a frameless function, we might have incorrectly
3667 skipped some load immediate instructions. Undo the skipping
3668 if the load immediate was not followed by a stack adjustment. */
3669 if (load_immediate_bytes
&& !seen_sp_adjust
)
3670 end_prologue_addr
-= load_immediate_bytes
;
3672 return end_prologue_addr
;
3675 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3676 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3677 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3678 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3680 static struct mips_frame_cache
*
3681 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3683 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3684 struct mips_frame_cache
*cache
;
3686 if ((*this_cache
) != NULL
)
3687 return (struct mips_frame_cache
*) (*this_cache
);
3689 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3690 (*this_cache
) = cache
;
3691 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3693 /* Analyze the function prologue. */
3695 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3696 CORE_ADDR start_addr
;
3698 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3699 if (start_addr
== 0)
3700 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3701 /* We can't analyze the prologue if we couldn't find the begining
3703 if (start_addr
== 0)
3706 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3707 (struct mips_frame_cache
*) *this_cache
);
3710 /* gdbarch_sp_regnum contains the value and not the address. */
3711 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3712 + MIPS_SP_REGNUM
].set_value (cache
->base
);
3714 return (struct mips_frame_cache
*) (*this_cache
);
3718 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3719 struct frame_id
*this_id
)
3721 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3723 /* This marks the outermost frame. */
3724 if (info
->base
== 0)
3726 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3729 static struct value
*
3730 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
3731 void **this_cache
, int regnum
)
3733 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3735 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3739 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3740 struct frame_info
*this_frame
, void **this_cache
)
3742 CORE_ADDR pc
= get_frame_pc (this_frame
);
3743 if (mips_pc_is_mips (pc
))
3748 static const struct frame_unwind mips_insn32_frame_unwind
=
3750 "mips insn32 prologue",
3752 default_frame_unwind_stop_reason
,
3753 mips_insn32_frame_this_id
,
3754 mips_insn32_frame_prev_register
,
3756 mips_insn32_frame_sniffer
3760 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
3763 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3768 static const struct frame_base mips_insn32_frame_base
=
3770 &mips_insn32_frame_unwind
,
3771 mips_insn32_frame_base_address
,
3772 mips_insn32_frame_base_address
,
3773 mips_insn32_frame_base_address
3776 static const struct frame_base
*
3777 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
3779 CORE_ADDR pc
= get_frame_pc (this_frame
);
3780 if (mips_pc_is_mips (pc
))
3781 return &mips_insn32_frame_base
;
3786 static struct trad_frame_cache
*
3787 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3790 CORE_ADDR start_addr
;
3791 CORE_ADDR stack_addr
;
3792 struct trad_frame_cache
*this_trad_cache
;
3793 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3794 int num_regs
= gdbarch_num_regs (gdbarch
);
3796 if ((*this_cache
) != NULL
)
3797 return (struct trad_frame_cache
*) (*this_cache
);
3798 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3799 (*this_cache
) = this_trad_cache
;
3801 /* The return address is in the link register. */
3802 trad_frame_set_reg_realreg (this_trad_cache
,
3803 gdbarch_pc_regnum (gdbarch
),
3804 num_regs
+ MIPS_RA_REGNUM
);
3806 /* Frame ID, since it's a frameless / stackless function, no stack
3807 space is allocated and SP on entry is the current SP. */
3808 pc
= get_frame_pc (this_frame
);
3809 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3810 stack_addr
= get_frame_register_signed (this_frame
,
3811 num_regs
+ MIPS_SP_REGNUM
);
3812 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3814 /* Assume that the frame's base is the same as the
3816 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3818 return this_trad_cache
;
3822 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3823 struct frame_id
*this_id
)
3825 struct trad_frame_cache
*this_trad_cache
3826 = mips_stub_frame_cache (this_frame
, this_cache
);
3827 trad_frame_get_id (this_trad_cache
, this_id
);
3830 static struct value
*
3831 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
3832 void **this_cache
, int regnum
)
3834 struct trad_frame_cache
*this_trad_cache
3835 = mips_stub_frame_cache (this_frame
, this_cache
);
3836 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3840 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3841 struct frame_info
*this_frame
, void **this_cache
)
3844 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3845 struct bound_minimal_symbol msym
;
3847 /* Use the stub unwinder for unreadable code. */
3848 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3851 if (in_plt_section (pc
) || in_mips_stubs_section (pc
))
3854 /* Calling a PIC function from a non-PIC function passes through a
3855 stub. The stub for foo is named ".pic.foo". */
3856 msym
= lookup_minimal_symbol_by_pc (pc
);
3857 if (msym
.minsym
!= NULL
3858 && msym
.minsym
->linkage_name () != NULL
3859 && startswith (msym
.minsym
->linkage_name (), ".pic."))
3865 static const struct frame_unwind mips_stub_frame_unwind
=
3869 default_frame_unwind_stop_reason
,
3870 mips_stub_frame_this_id
,
3871 mips_stub_frame_prev_register
,
3873 mips_stub_frame_sniffer
3877 mips_stub_frame_base_address (struct frame_info
*this_frame
,
3880 struct trad_frame_cache
*this_trad_cache
3881 = mips_stub_frame_cache (this_frame
, this_cache
);
3882 return trad_frame_get_this_base (this_trad_cache
);
3885 static const struct frame_base mips_stub_frame_base
=
3887 &mips_stub_frame_unwind
,
3888 mips_stub_frame_base_address
,
3889 mips_stub_frame_base_address
,
3890 mips_stub_frame_base_address
3893 static const struct frame_base
*
3894 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
3896 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3897 return &mips_stub_frame_base
;
3902 /* mips_addr_bits_remove - remove useless address bits */
3905 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3907 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3909 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3910 /* This hack is a work-around for existing boards using PMON, the
3911 simulator, and any other 64-bit targets that doesn't have true
3912 64-bit addressing. On these targets, the upper 32 bits of
3913 addresses are ignored by the hardware. Thus, the PC or SP are
3914 likely to have been sign extended to all 1s by instruction
3915 sequences that load 32-bit addresses. For example, a typical
3916 piece of code that loads an address is this:
3918 lui $r2, <upper 16 bits>
3919 ori $r2, <lower 16 bits>
3921 But the lui sign-extends the value such that the upper 32 bits
3922 may be all 1s. The workaround is simply to mask off these
3923 bits. In the future, gcc may be changed to support true 64-bit
3924 addressing, and this masking will have to be disabled. */
3925 return addr
&= 0xffffffffUL
;
3931 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3932 instruction and ending with a SC/SCD instruction. If such a sequence
3933 is found, attempt to step through it. A breakpoint is placed at the end of
3936 /* Instructions used during single-stepping of atomic sequences, standard
3938 #define LL_OPCODE 0x30
3939 #define LLD_OPCODE 0x34
3940 #define SC_OPCODE 0x38
3941 #define SCD_OPCODE 0x3c
3943 static std::vector
<CORE_ADDR
>
3944 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3946 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
3948 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3952 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3953 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3955 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3956 /* Assume all atomic sequences start with a ll/lld instruction. */
3957 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3960 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3962 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3965 loc
+= MIPS_INSN32_SIZE
;
3966 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3968 /* Assume that there is at most one branch in the atomic
3969 sequence. If a branch is found, put a breakpoint in its
3970 destination address. */
3971 switch (itype_op (insn
))
3973 case 0: /* SPECIAL */
3974 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3975 return {}; /* fallback to the standard single-step code. */
3977 case 1: /* REGIMM */
3978 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3979 || ((itype_rt (insn
) & 0x1e) == 0
3980 && itype_rs (insn
) == 0)); /* BPOSGE* */
3984 return {}; /* fallback to the standard single-step code. */
3991 case 22: /* BLEZL */
3992 case 23: /* BGTTL */
3996 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3997 && (itype_rt (insn
) & 0x2) == 0);
3998 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
4003 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
4008 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
4009 if (last_breakpoint
>= 1)
4010 return {}; /* More than one branch found, fallback to the
4011 standard single-step code. */
4012 breaks
[1] = branch_bp
;
4016 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
4020 /* Assume that the atomic sequence ends with a sc/scd instruction. */
4021 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
4024 loc
+= MIPS_INSN32_SIZE
;
4026 /* Insert a breakpoint right after the end of the atomic sequence. */
4029 /* Check for duplicated breakpoints. Check also for a breakpoint
4030 placed (branch instruction's destination) in the atomic sequence. */
4031 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4032 last_breakpoint
= 0;
4034 std::vector
<CORE_ADDR
> next_pcs
;
4036 /* Effectively inserts the breakpoints. */
4037 for (index
= 0; index
<= last_breakpoint
; index
++)
4038 next_pcs
.push_back (breaks
[index
]);
4043 static std::vector
<CORE_ADDR
>
4044 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
4047 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
4048 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
4049 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
4050 CORE_ADDR branch_bp
= 0; /* Breakpoint at branch instruction's
4058 /* Assume all atomic sequences start with a ll/lld instruction. */
4059 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4060 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
4062 loc
+= MIPS_INSN16_SIZE
;
4064 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4065 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
4067 loc
+= MIPS_INSN16_SIZE
;
4069 /* Assume all atomic sequences end with an sc/scd instruction. Assume
4070 that no atomic sequence is longer than "atomic_sequence_length"
4072 for (insn_count
= 0;
4073 !sc_found
&& insn_count
< atomic_sequence_length
;
4078 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4079 loc
+= MIPS_INSN16_SIZE
;
4081 /* Assume that there is at most one conditional branch in the
4082 atomic sequence. If a branch is found, put a breakpoint in
4083 its destination address. */
4084 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
4086 /* 32-bit instructions. */
4087 case 2 * MIPS_INSN16_SIZE
:
4088 switch (micromips_op (insn
))
4090 case 0x10: /* POOL32I: bits 010000 */
4091 if ((b5s5_op (insn
) & 0x18) != 0x0
4092 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
4093 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
4094 && (b5s5_op (insn
) & 0x1d) != 0x11
4095 /* BLTZALS, BGEZALS: bits 010000 100x1 */
4096 && ((b5s5_op (insn
) & 0x1e) != 0x14
4097 || (insn
& 0x3) != 0x0)
4098 /* BC2F, BC2T: bits 010000 1010x xxx00 */
4099 && (b5s5_op (insn
) & 0x1e) != 0x1a
4100 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
4101 && ((b5s5_op (insn
) & 0x1e) != 0x1c
4102 || (insn
& 0x3) != 0x0)
4103 /* BC1F, BC1T: bits 010000 1110x xxx00 */
4104 && ((b5s5_op (insn
) & 0x1c) != 0x1c
4105 || (insn
& 0x3) != 0x1))
4106 /* BC1ANY*: bits 010000 111xx xxx01 */
4110 case 0x25: /* BEQ: bits 100101 */
4111 case 0x2d: /* BNE: bits 101101 */
4113 insn
|= mips_fetch_instruction (gdbarch
,
4114 ISA_MICROMIPS
, loc
, NULL
);
4115 branch_bp
= (loc
+ MIPS_INSN16_SIZE
4116 + micromips_relative_offset16 (insn
));
4120 case 0x00: /* POOL32A: bits 000000 */
4122 insn
|= mips_fetch_instruction (gdbarch
,
4123 ISA_MICROMIPS
, loc
, NULL
);
4124 if (b0s6_op (insn
) != 0x3c
4125 /* POOL32Axf: bits 000000 ... 111100 */
4126 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
4127 /* JALR, JALR.HB: 000000 000x111100 111100 */
4128 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
4132 case 0x1d: /* JALS: bits 011101 */
4133 case 0x35: /* J: bits 110101 */
4134 case 0x3d: /* JAL: bits 111101 */
4135 case 0x3c: /* JALX: bits 111100 */
4136 return {}; /* Fall back to the standard single-step code. */
4138 case 0x18: /* POOL32C: bits 011000 */
4139 if ((b12s4_op (insn
) & 0xb) == 0xb)
4140 /* SC, SCD: bits 011000 1x11 */
4144 loc
+= MIPS_INSN16_SIZE
;
4147 /* 16-bit instructions. */
4148 case MIPS_INSN16_SIZE
:
4149 switch (micromips_op (insn
))
4151 case 0x23: /* BEQZ16: bits 100011 */
4152 case 0x2b: /* BNEZ16: bits 101011 */
4153 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
4157 case 0x11: /* POOL16C: bits 010001 */
4158 if ((b5s5_op (insn
) & 0x1c) != 0xc
4159 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
4160 && b5s5_op (insn
) != 0x18)
4161 /* JRADDIUSP: bits 010001 11000 */
4163 return {}; /* Fall back to the standard single-step code. */
4165 case 0x33: /* B16: bits 110011 */
4166 return {}; /* Fall back to the standard single-step code. */
4172 if (last_breakpoint
>= 1)
4173 return {}; /* More than one branch found, fallback to the
4174 standard single-step code. */
4175 breaks
[1] = branch_bp
;
4182 /* Insert a breakpoint right after the end of the atomic sequence. */
4185 /* Check for duplicated breakpoints. Check also for a breakpoint
4186 placed (branch instruction's destination) in the atomic sequence */
4187 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4188 last_breakpoint
= 0;
4190 std::vector
<CORE_ADDR
> next_pcs
;
4192 /* Effectively inserts the breakpoints. */
4193 for (index
= 0; index
<= last_breakpoint
; index
++)
4194 next_pcs
.push_back (breaks
[index
]);
4199 static std::vector
<CORE_ADDR
>
4200 deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4202 if (mips_pc_is_mips (pc
))
4203 return mips_deal_with_atomic_sequence (gdbarch
, pc
);
4204 else if (mips_pc_is_micromips (gdbarch
, pc
))
4205 return micromips_deal_with_atomic_sequence (gdbarch
, pc
);
4210 /* mips_software_single_step() is called just before we want to resume
4211 the inferior, if we want to single-step it but there is no hardware
4212 or kernel single-step support (MIPS on GNU/Linux for example). We find
4213 the target of the coming instruction and breakpoint it. */
4215 std::vector
<CORE_ADDR
>
4216 mips_software_single_step (struct regcache
*regcache
)
4218 struct gdbarch
*gdbarch
= regcache
->arch ();
4219 CORE_ADDR pc
, next_pc
;
4221 pc
= regcache_read_pc (regcache
);
4222 std::vector
<CORE_ADDR
> next_pcs
= deal_with_atomic_sequence (gdbarch
, pc
);
4224 if (!next_pcs
.empty ())
4227 next_pc
= mips_next_pc (regcache
, pc
);
4232 /* Test whether the PC points to the return instruction at the
4233 end of a function. */
4236 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4241 /* This used to check for MIPS16, but this piece of code is never
4242 called for MIPS16 functions. And likewise microMIPS ones. */
4243 gdb_assert (mips_pc_is_mips (pc
));
4245 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
4247 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
4251 /* This fencepost looks highly suspicious to me. Removing it also
4252 seems suspicious as it could affect remote debugging across serial
4256 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4262 struct inferior
*inf
;
4264 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4266 fence
= start_pc
- heuristic_fence_post
;
4270 if (heuristic_fence_post
== -1 || fence
< VM_MIN_ADDRESS
)
4271 fence
= VM_MIN_ADDRESS
;
4273 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
4275 inf
= current_inferior ();
4277 /* Search back for previous return. */
4278 for (start_pc
-= instlen
;; start_pc
-= instlen
)
4279 if (start_pc
< fence
)
4281 /* It's not clear to me why we reach this point when
4282 stop_soon, but with this test, at least we
4283 don't print out warnings for every child forked (eg, on
4284 decstation). 22apr93 rich@cygnus.com. */
4285 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
4287 static int blurb_printed
= 0;
4289 warning (_("GDB can't find the start of the function at %s."),
4290 paddress (gdbarch
, pc
));
4294 /* This actually happens frequently in embedded
4295 development, when you first connect to a board
4296 and your stack pointer and pc are nowhere in
4297 particular. This message needs to give people
4298 in that situation enough information to
4299 determine that it's no big deal. */
4301 GDB is unable to find the start of the function at %s\n\
4302 and thus can't determine the size of that function's stack frame.\n\
4303 This means that GDB may be unable to access that stack frame, or\n\
4304 the frames below it.\n\
4305 This problem is most likely caused by an invalid program counter or\n\
4307 However, if you think GDB should simply search farther back\n\
4308 from %s for code which looks like the beginning of a\n\
4309 function, you can increase the range of the search using the `set\n\
4310 heuristic-fence-post' command.\n",
4311 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4318 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4320 unsigned short inst
;
4322 /* On MIPS16, any one of the following is likely to be the
4323 start of a function:
4329 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4330 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4331 if ((inst
& 0xff80) == 0x6480) /* save */
4333 if (start_pc
- instlen
>= fence
)
4335 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4336 start_pc
- instlen
, NULL
);
4337 if ((inst
& 0xf800) == 0xf000) /* extend */
4338 start_pc
-= instlen
;
4342 else if (((inst
& 0xf81f) == 0xe809
4343 && (inst
& 0x700) != 0x700) /* entry */
4344 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4345 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4346 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4348 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4349 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4354 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4362 /* On microMIPS, any one of the following is likely to be the
4363 start of a function:
4367 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4368 switch (micromips_op (insn
))
4370 case 0xc: /* ADDIU: bits 001100 */
4371 case 0x17: /* DADDIU: bits 010111 */
4372 sreg
= b0s5_reg (insn
);
4373 dreg
= b5s5_reg (insn
);
4375 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4376 pc
+ MIPS_INSN16_SIZE
, NULL
);
4377 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4378 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4379 /* (D)ADDIU $sp, imm */
4384 case 0x10: /* POOL32I: bits 010000 */
4385 if (b5s5_op (insn
) == 0xd
4386 /* LUI: bits 010000 001101 */
4387 && b0s5_reg (insn
>> 16) == 28)
4392 case 0x13: /* POOL16D: bits 010011 */
4393 if ((insn
& 0x1) == 0x1)
4394 /* ADDIUSP: bits 010011 1 */
4396 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4402 /* ADDIUS5: bits 010011 0 */
4404 dreg
= b5s5_reg (insn
);
4405 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4406 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4407 /* ADDIUS5 $sp, -imm */
4415 else if (mips_about_to_return (gdbarch
, start_pc
))
4417 /* Skip return and its delay slot. */
4418 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4425 struct mips_objfile_private
4431 /* According to the current ABI, should the type be passed in a
4432 floating-point register (assuming that there is space)? When there
4433 is no FPU, FP are not even considered as possible candidates for
4434 FP registers and, consequently this returns false - forces FP
4435 arguments into integer registers. */
4438 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4439 struct type
*arg_type
)
4441 return ((typecode
== TYPE_CODE_FLT
4442 || (mips_eabi (gdbarch
)
4443 && (typecode
== TYPE_CODE_STRUCT
4444 || typecode
== TYPE_CODE_UNION
)
4445 && arg_type
->num_fields () == 1
4446 && check_typedef (arg_type
->field (0).type ())->code ()
4448 && mips_get_fpu_type (gdbarch
) != MIPS_FPU_NONE
);
4451 /* On o32, argument passing in GPRs depends on the alignment of the type being
4452 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4455 mips_type_needs_double_align (struct type
*type
)
4457 enum type_code typecode
= type
->code ();
4459 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
4461 else if (typecode
== TYPE_CODE_STRUCT
)
4463 if (type
->num_fields () < 1)
4465 return mips_type_needs_double_align (type
->field (0).type ());
4467 else if (typecode
== TYPE_CODE_UNION
)
4471 n
= type
->num_fields ();
4472 for (i
= 0; i
< n
; i
++)
4473 if (mips_type_needs_double_align (type
->field (i
).type ()))
4480 /* Adjust the address downward (direction of stack growth) so that it
4481 is correctly aligned for a new stack frame. */
4483 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4485 return align_down (addr
, 16);
4488 /* Implement the "push_dummy_code" gdbarch method. */
4491 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4492 CORE_ADDR funaddr
, struct value
**args
,
4493 int nargs
, struct type
*value_type
,
4494 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4495 struct regcache
*regcache
)
4497 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4501 /* Reserve enough room on the stack for our breakpoint instruction. */
4502 bp_slot
= sp
- sizeof (nop_insn
);
4504 /* Return to microMIPS mode if calling microMIPS code to avoid
4505 triggering an address error exception on processors that only
4506 support microMIPS execution. */
4507 *bp_addr
= (mips_pc_is_micromips (gdbarch
, funaddr
)
4508 ? make_compact_addr (bp_slot
) : bp_slot
);
4510 /* The breakpoint layer automatically adjusts the address of
4511 breakpoints inserted in a branch delay slot. With enough
4512 bad luck, the 4 bytes located just before our breakpoint
4513 instruction could look like a branch instruction, and thus
4514 trigger the adjustement, and break the function call entirely.
4515 So, we reserve those 4 bytes and write a nop instruction
4516 to prevent that from happening. */
4517 nop_addr
= bp_slot
- sizeof (nop_insn
);
4518 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4519 sp
= mips_frame_align (gdbarch
, nop_addr
);
4521 /* Inferior resumes at the function entry point. */
4528 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4529 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4530 int nargs
, struct value
**args
, CORE_ADDR sp
,
4531 function_call_return_method return_method
,
4532 CORE_ADDR struct_addr
)
4538 int stack_offset
= 0;
4539 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4540 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4541 int abi_regsize
= mips_abi_regsize (gdbarch
);
4543 /* For shared libraries, "t9" needs to point at the function
4545 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4547 /* Set the return address register to point to the entry point of
4548 the program, where a breakpoint lies in wait. */
4549 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4551 /* First ensure that the stack and structure return address (if any)
4552 are properly aligned. The stack has to be at least 64-bit
4553 aligned even on 32-bit machines, because doubles must be 64-bit
4554 aligned. For n32 and n64, stack frames need to be 128-bit
4555 aligned, so we round to this widest known alignment. */
4557 sp
= align_down (sp
, 16);
4558 struct_addr
= align_down (struct_addr
, 16);
4560 /* Now make space on the stack for the args. We allocate more
4561 than necessary for EABI, because the first few arguments are
4562 passed in registers, but that's OK. */
4563 for (argnum
= 0; argnum
< nargs
; argnum
++)
4564 arg_space
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), abi_regsize
);
4565 sp
-= align_up (arg_space
, 16);
4568 gdb_printf (gdb_stdlog
,
4569 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4570 paddress (gdbarch
, sp
),
4571 (long) align_up (arg_space
, 16));
4573 /* Initialize the integer and float register pointers. */
4574 argreg
= MIPS_A0_REGNUM
;
4575 float_argreg
= mips_fpa0_regnum (gdbarch
);
4577 /* The struct_return pointer occupies the first parameter-passing reg. */
4578 if (return_method
== return_method_struct
)
4581 gdb_printf (gdb_stdlog
,
4582 "mips_eabi_push_dummy_call: "
4583 "struct_return reg=%d %s\n",
4584 argreg
, paddress (gdbarch
, struct_addr
));
4585 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4588 /* Now load as many as possible of the first arguments into
4589 registers, and push the rest onto the stack. Loop thru args
4590 from first to last. */
4591 for (argnum
= 0; argnum
< nargs
; argnum
++)
4593 const gdb_byte
*val
;
4594 /* This holds the address of structures that are passed by
4596 gdb_byte ref_valbuf
[MAX_MIPS_ABI_REGSIZE
];
4597 struct value
*arg
= args
[argnum
];
4598 struct type
*arg_type
= check_typedef (value_type (arg
));
4599 int len
= TYPE_LENGTH (arg_type
);
4600 enum type_code typecode
= arg_type
->code ();
4603 gdb_printf (gdb_stdlog
,
4604 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4605 argnum
+ 1, len
, (int) typecode
);
4607 /* The EABI passes structures that do not fit in a register by
4609 if (len
> abi_regsize
4610 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4612 gdb_assert (abi_regsize
<= ARRAY_SIZE (ref_valbuf
));
4613 store_unsigned_integer (ref_valbuf
, abi_regsize
, byte_order
,
4614 value_address (arg
));
4615 typecode
= TYPE_CODE_PTR
;
4619 gdb_printf (gdb_stdlog
, " push");
4622 val
= value_contents (arg
).data ();
4624 /* 32-bit ABIs always start floating point arguments in an
4625 even-numbered floating point register. Round the FP register
4626 up before the check to see if there are any FP registers
4627 left. Non MIPS_EABI targets also pass the FP in the integer
4628 registers so also round up normal registers. */
4629 if (abi_regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4631 if ((float_argreg
& 1))
4635 /* Floating point arguments passed in registers have to be
4636 treated specially. On 32-bit architectures, doubles
4637 are passed in register pairs; the even register gets
4638 the low word, and the odd register gets the high word.
4639 On non-EABI processors, the first two floating point arguments are
4640 also copied to general registers, because MIPS16 functions
4641 don't use float registers for arguments. This duplication of
4642 arguments in general registers can't hurt non-MIPS16 functions
4643 because those registers are normally skipped. */
4644 /* MIPS_EABI squeezes a struct that contains a single floating
4645 point value into an FP register instead of pushing it onto the
4647 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4648 && float_argreg
<= mips_last_fp_arg_regnum (gdbarch
))
4650 /* EABI32 will pass doubles in consecutive registers, even on
4651 64-bit cores. At one time, we used to check the size of
4652 `float_argreg' to determine whether or not to pass doubles
4653 in consecutive registers, but this is not sufficient for
4654 making the ABI determination. */
4655 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4657 int low_offset
= gdbarch_byte_order (gdbarch
)
4658 == BFD_ENDIAN_BIG
? 4 : 0;
4661 /* Write the low word of the double to the even register(s). */
4662 regval
= extract_signed_integer (val
+ low_offset
,
4665 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
4666 float_argreg
, phex (regval
, 4));
4667 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4669 /* Write the high word of the double to the odd register(s). */
4670 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4673 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
4674 float_argreg
, phex (regval
, 4));
4675 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4679 /* This is a floating point value that fits entirely
4680 in a single register. */
4681 /* On 32 bit ABI's the float_argreg is further adjusted
4682 above to ensure that it is even register aligned. */
4683 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4685 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
4686 float_argreg
, phex (regval
, len
));
4687 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4692 /* Copy the argument to general registers or the stack in
4693 register-sized pieces. Large arguments are split between
4694 registers and stack. */
4695 /* Note: structs whose size is not a multiple of abi_regsize
4696 are treated specially: Irix cc passes
4697 them in registers where gcc sometimes puts them on the
4698 stack. For maximum compatibility, we will put them in
4700 int odd_sized_struct
= (len
> abi_regsize
&& len
% abi_regsize
!= 0);
4702 /* Note: Floating-point values that didn't fit into an FP
4703 register are only written to memory. */
4706 /* Remember if the argument was written to the stack. */
4707 int stack_used_p
= 0;
4708 int partial_len
= (len
< abi_regsize
? len
: abi_regsize
);
4711 gdb_printf (gdb_stdlog
, " -- partial=%d",
4714 /* Write this portion of the argument to the stack. */
4715 if (argreg
> mips_last_arg_regnum (gdbarch
)
4717 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4719 /* Should shorter than int integer values be
4720 promoted to int before being stored? */
4721 int longword_offset
= 0;
4724 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4726 if (abi_regsize
== 8
4727 && (typecode
== TYPE_CODE_INT
4728 || typecode
== TYPE_CODE_PTR
4729 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4730 longword_offset
= abi_regsize
- len
;
4731 else if ((typecode
== TYPE_CODE_STRUCT
4732 || typecode
== TYPE_CODE_UNION
)
4733 && TYPE_LENGTH (arg_type
) < abi_regsize
)
4734 longword_offset
= abi_regsize
- len
;
4739 gdb_printf (gdb_stdlog
, " - stack_offset=%s",
4740 paddress (gdbarch
, stack_offset
));
4741 gdb_printf (gdb_stdlog
, " longword_offset=%s",
4742 paddress (gdbarch
, longword_offset
));
4745 addr
= sp
+ stack_offset
+ longword_offset
;
4750 gdb_printf (gdb_stdlog
, " @%s ",
4751 paddress (gdbarch
, addr
));
4752 for (i
= 0; i
< partial_len
; i
++)
4754 gdb_printf (gdb_stdlog
, "%02x",
4758 write_memory (addr
, val
, partial_len
);
4761 /* Note!!! This is NOT an else clause. Odd sized
4762 structs may go thru BOTH paths. Floating point
4763 arguments will not. */
4764 /* Write this portion of the argument to a general
4765 purpose register. */
4766 if (argreg
<= mips_last_arg_regnum (gdbarch
)
4767 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4770 extract_signed_integer (val
, partial_len
, byte_order
);
4773 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
4775 phex (regval
, abi_regsize
));
4776 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4783 /* Compute the offset into the stack at which we will
4784 copy the next parameter.
4786 In the new EABI (and the NABI32), the stack_offset
4787 only needs to be adjusted when it has been used. */
4790 stack_offset
+= align_up (partial_len
, abi_regsize
);
4794 gdb_printf (gdb_stdlog
, "\n");
4797 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4799 /* Return adjusted stack pointer. */
4803 /* Determine the return value convention being used. */
4805 static enum return_value_convention
4806 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4807 struct type
*type
, struct regcache
*regcache
,
4808 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4810 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
4811 int fp_return_type
= 0;
4812 int offset
, regnum
, xfer
;
4814 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
4815 return RETURN_VALUE_STRUCT_CONVENTION
;
4817 /* Floating point type? */
4818 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4820 if (type
->code () == TYPE_CODE_FLT
)
4822 /* Structs with a single field of float type
4823 are returned in a floating point register. */
4824 if ((type
->code () == TYPE_CODE_STRUCT
4825 || type
->code () == TYPE_CODE_UNION
)
4826 && type
->num_fields () == 1)
4828 struct type
*fieldtype
= type
->field (0).type ();
4830 if (check_typedef (fieldtype
)->code () == TYPE_CODE_FLT
)
4837 /* A floating-point value belongs in the least significant part
4840 gdb_printf (gdb_stderr
, "Return float in $fp0\n");
4841 regnum
= mips_regnum (gdbarch
)->fp0
;
4845 /* An integer value goes in V0/V1. */
4847 gdb_printf (gdb_stderr
, "Return scalar in $v0\n");
4848 regnum
= MIPS_V0_REGNUM
;
4851 offset
< TYPE_LENGTH (type
);
4852 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4854 xfer
= mips_abi_regsize (gdbarch
);
4855 if (offset
+ xfer
> TYPE_LENGTH (type
))
4856 xfer
= TYPE_LENGTH (type
) - offset
;
4857 mips_xfer_register (gdbarch
, regcache
,
4858 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4859 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4863 return RETURN_VALUE_REGISTER_CONVENTION
;
4867 /* N32/N64 ABI stuff. */
4869 /* Search for a naturally aligned double at OFFSET inside a struct
4870 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4874 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4879 if (arg_type
->code () != TYPE_CODE_STRUCT
)
4882 if (mips_get_fpu_type (gdbarch
) != MIPS_FPU_DOUBLE
)
4885 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
4888 for (i
= 0; i
< arg_type
->num_fields (); i
++)
4891 struct type
*field_type
;
4893 /* We're only looking at normal fields. */
4894 if (field_is_static (&arg_type
->field (i
))
4895 || (arg_type
->field (i
).loc_bitpos () % 8) != 0)
4898 /* If we have gone past the offset, there is no double to pass. */
4899 pos
= arg_type
->field (i
).loc_bitpos () / 8;
4903 field_type
= check_typedef (arg_type
->field (i
).type ());
4905 /* If this field is entirely before the requested offset, go
4906 on to the next one. */
4907 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
4910 /* If this is our special aligned double, we can stop. */
4911 if (field_type
->code () == TYPE_CODE_FLT
4912 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
4915 /* This field starts at or before the requested offset, and
4916 overlaps it. If it is a structure, recurse inwards. */
4917 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4924 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4925 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4926 int nargs
, struct value
**args
, CORE_ADDR sp
,
4927 function_call_return_method return_method
,
4928 CORE_ADDR struct_addr
)
4934 int stack_offset
= 0;
4935 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4936 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4938 /* For shared libraries, "t9" needs to point at the function
4940 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4942 /* Set the return address register to point to the entry point of
4943 the program, where a breakpoint lies in wait. */
4944 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4946 /* First ensure that the stack and structure return address (if any)
4947 are properly aligned. The stack has to be at least 64-bit
4948 aligned even on 32-bit machines, because doubles must be 64-bit
4949 aligned. For n32 and n64, stack frames need to be 128-bit
4950 aligned, so we round to this widest known alignment. */
4952 sp
= align_down (sp
, 16);
4953 struct_addr
= align_down (struct_addr
, 16);
4955 /* Now make space on the stack for the args. */
4956 for (argnum
= 0; argnum
< nargs
; argnum
++)
4957 arg_space
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
4958 sp
-= align_up (arg_space
, 16);
4961 gdb_printf (gdb_stdlog
,
4962 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4963 paddress (gdbarch
, sp
),
4964 (long) align_up (arg_space
, 16));
4966 /* Initialize the integer and float register pointers. */
4967 argreg
= MIPS_A0_REGNUM
;
4968 float_argreg
= mips_fpa0_regnum (gdbarch
);
4970 /* The struct_return pointer occupies the first parameter-passing reg. */
4971 if (return_method
== return_method_struct
)
4974 gdb_printf (gdb_stdlog
,
4975 "mips_n32n64_push_dummy_call: "
4976 "struct_return reg=%d %s\n",
4977 argreg
, paddress (gdbarch
, struct_addr
));
4978 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4981 /* Now load as many as possible of the first arguments into
4982 registers, and push the rest onto the stack. Loop thru args
4983 from first to last. */
4984 for (argnum
= 0; argnum
< nargs
; argnum
++)
4986 const gdb_byte
*val
;
4987 struct value
*arg
= args
[argnum
];
4988 struct type
*arg_type
= check_typedef (value_type (arg
));
4989 int len
= TYPE_LENGTH (arg_type
);
4990 enum type_code typecode
= arg_type
->code ();
4993 gdb_printf (gdb_stdlog
,
4994 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4995 argnum
+ 1, len
, (int) typecode
);
4997 val
= value_contents (arg
).data ();
4999 /* A 128-bit long double value requires an even-odd pair of
5000 floating-point registers. */
5002 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5003 && (float_argreg
& 1))
5009 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5010 && argreg
<= mips_last_arg_regnum (gdbarch
))
5012 /* This is a floating point value that fits entirely
5013 in a single register or a pair of registers. */
5014 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5015 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
5017 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5018 float_argreg
, phex (regval
, reglen
));
5019 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
5022 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5023 argreg
, phex (regval
, reglen
));
5024 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5029 regval
= extract_unsigned_integer (val
+ reglen
,
5030 reglen
, byte_order
);
5032 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5033 float_argreg
, phex (regval
, reglen
));
5034 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
5037 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5038 argreg
, phex (regval
, reglen
));
5039 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5046 /* Copy the argument to general registers or the stack in
5047 register-sized pieces. Large arguments are split between
5048 registers and stack. */
5049 /* For N32/N64, structs, unions, or other composite types are
5050 treated as a sequence of doublewords, and are passed in integer
5051 or floating point registers as though they were simple scalar
5052 parameters to the extent that they fit, with any excess on the
5053 stack packed according to the normal memory layout of the
5055 The caller does not reserve space for the register arguments;
5056 the callee is responsible for reserving it if required. */
5057 /* Note: Floating-point values that didn't fit into an FP
5058 register are only written to memory. */
5061 /* Remember if the argument was written to the stack. */
5062 int stack_used_p
= 0;
5063 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5066 gdb_printf (gdb_stdlog
, " -- partial=%d",
5069 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5070 gdb_assert (argreg
> mips_last_arg_regnum (gdbarch
));
5072 /* Write this portion of the argument to the stack. */
5073 if (argreg
> mips_last_arg_regnum (gdbarch
))
5075 /* Should shorter than int integer values be
5076 promoted to int before being stored? */
5077 int longword_offset
= 0;
5080 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5082 if ((typecode
== TYPE_CODE_INT
5083 || typecode
== TYPE_CODE_PTR
)
5085 longword_offset
= MIPS64_REGSIZE
- len
;
5090 gdb_printf (gdb_stdlog
, " - stack_offset=%s",
5091 paddress (gdbarch
, stack_offset
));
5092 gdb_printf (gdb_stdlog
, " longword_offset=%s",
5093 paddress (gdbarch
, longword_offset
));
5096 addr
= sp
+ stack_offset
+ longword_offset
;
5101 gdb_printf (gdb_stdlog
, " @%s ",
5102 paddress (gdbarch
, addr
));
5103 for (i
= 0; i
< partial_len
; i
++)
5105 gdb_printf (gdb_stdlog
, "%02x",
5109 write_memory (addr
, val
, partial_len
);
5112 /* Note!!! This is NOT an else clause. Odd sized
5113 structs may go thru BOTH paths. */
5114 /* Write this portion of the argument to a general
5115 purpose register. */
5116 if (argreg
<= mips_last_arg_regnum (gdbarch
))
5120 /* Sign extend pointers, 32-bit integers and signed
5121 16-bit and 8-bit integers; everything else is taken
5124 if ((partial_len
== 4
5125 && (typecode
== TYPE_CODE_PTR
5126 || typecode
== TYPE_CODE_INT
))
5128 && typecode
== TYPE_CODE_INT
5129 && !arg_type
->is_unsigned ()))
5130 regval
= extract_signed_integer (val
, partial_len
,
5133 regval
= extract_unsigned_integer (val
, partial_len
,
5136 /* A non-floating-point argument being passed in a
5137 general register. If a struct or union, and if
5138 the remaining length is smaller than the register
5139 size, we have to adjust the register value on
5142 It does not seem to be necessary to do the
5143 same for integral types. */
5145 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5146 && partial_len
< MIPS64_REGSIZE
5147 && (typecode
== TYPE_CODE_STRUCT
5148 || typecode
== TYPE_CODE_UNION
))
5149 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5153 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5155 phex (regval
, MIPS64_REGSIZE
));
5156 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5158 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
5159 TYPE_LENGTH (arg_type
) - len
))
5162 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5164 phex (regval
, MIPS64_REGSIZE
));
5165 regcache_cooked_write_unsigned (regcache
, float_argreg
,
5176 /* Compute the offset into the stack at which we will
5177 copy the next parameter.
5179 In N32 (N64?), the stack_offset only needs to be
5180 adjusted when it has been used. */
5183 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5187 gdb_printf (gdb_stdlog
, "\n");
5190 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5192 /* Return adjusted stack pointer. */
5196 static enum return_value_convention
5197 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5198 struct type
*type
, struct regcache
*regcache
,
5199 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5201 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
5203 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
5205 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
5206 if needed), as appropriate for the type. Composite results (struct,
5207 union, or array) are returned in $2/$f0 and $3/$f2 according to the
5210 * A struct with only one or two floating point fields is returned in $f0
5211 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
5214 * Any other composite results of at most 128 bits are returned in
5215 $2 (first 64 bits) and $3 (remainder, if necessary).
5217 * Larger composite results are handled by converting the function to a
5218 procedure with an implicit first parameter, which is a pointer to an area
5219 reserved by the caller to receive the result. [The o32-bit ABI requires
5220 that all composite results be handled by conversion to implicit first
5221 parameters. The MIPS/SGI Fortran implementation has always made a
5222 specific exception to return COMPLEX results in the floating point
5225 From MIPSpro Assembly Language Programmer's Guide, Document Number:
5230 Name fgregdef.h) Use and Linkage
5231 -----------------------------------------------------------------
5232 $f0, $f2 fv0, fv1 Hold results of floating-point type function
5233 ($f0) and complex type function ($f0 has the
5234 real part, $f2 has the imaginary part.) */
5236 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
5237 return RETURN_VALUE_STRUCT_CONVENTION
;
5238 else if ((type
->code () == TYPE_CODE_COMPLEX
5239 || (type
->code () == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 16))
5240 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5242 /* A complex value of up to 128 bits in width as well as a 128-bit
5243 floating-point value goes in both $f0 and $f2. A single complex
5244 value is held in the lower halves only of the respective registers.
5245 The two registers are used in the same as memory order, so the
5246 bytes with the lower memory address are in $f0. */
5248 gdb_printf (gdb_stderr
, "Return float in $f0 and $f2\n");
5249 mips_xfer_register (gdbarch
, regcache
,
5250 (gdbarch_num_regs (gdbarch
)
5251 + mips_regnum (gdbarch
)->fp0
),
5252 TYPE_LENGTH (type
) / 2, gdbarch_byte_order (gdbarch
),
5253 readbuf
, writebuf
, 0);
5254 mips_xfer_register (gdbarch
, regcache
,
5255 (gdbarch_num_regs (gdbarch
)
5256 + mips_regnum (gdbarch
)->fp0
+ 2),
5257 TYPE_LENGTH (type
) / 2, gdbarch_byte_order (gdbarch
),
5258 readbuf
? readbuf
+ TYPE_LENGTH (type
) / 2 : readbuf
,
5260 ? writebuf
+ TYPE_LENGTH (type
) / 2 : writebuf
), 0);
5261 return RETURN_VALUE_REGISTER_CONVENTION
;
5263 else if (type
->code () == TYPE_CODE_FLT
5264 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5266 /* A single or double floating-point value that fits in FP0. */
5268 gdb_printf (gdb_stderr
, "Return float in $fp0\n");
5269 mips_xfer_register (gdbarch
, regcache
,
5270 (gdbarch_num_regs (gdbarch
)
5271 + mips_regnum (gdbarch
)->fp0
),
5273 gdbarch_byte_order (gdbarch
),
5274 readbuf
, writebuf
, 0);
5275 return RETURN_VALUE_REGISTER_CONVENTION
;
5277 else if (type
->code () == TYPE_CODE_STRUCT
5278 && type
->num_fields () <= 2
5279 && type
->num_fields () >= 1
5280 && ((type
->num_fields () == 1
5281 && (check_typedef (type
->field (0).type ())->code ()
5283 || (type
->num_fields () == 2
5284 && (check_typedef (type
->field (0).type ())->code ()
5286 && (check_typedef (type
->field (1).type ())->code ()
5287 == TYPE_CODE_FLT
))))
5289 /* A struct that contains one or two floats. Each value is part
5290 in the least significant part of their floating point
5291 register (or GPR, for soft float). */
5294 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
5295 ? mips_regnum (gdbarch
)->fp0
5297 field
< type
->num_fields (); field
++, regnum
+= 2)
5299 int offset
= type
->field (field
).loc_bitpos () / TARGET_CHAR_BIT
;
5301 gdb_printf (gdb_stderr
, "Return float struct+%d\n",
5303 if (TYPE_LENGTH (type
->field (field
).type ()) == 16)
5305 /* A 16-byte long double field goes in two consecutive
5307 mips_xfer_register (gdbarch
, regcache
,
5308 gdbarch_num_regs (gdbarch
) + regnum
,
5310 gdbarch_byte_order (gdbarch
),
5311 readbuf
, writebuf
, offset
);
5312 mips_xfer_register (gdbarch
, regcache
,
5313 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5315 gdbarch_byte_order (gdbarch
),
5316 readbuf
, writebuf
, offset
+ 8);
5319 mips_xfer_register (gdbarch
, regcache
,
5320 gdbarch_num_regs (gdbarch
) + regnum
,
5321 TYPE_LENGTH (type
->field (field
).type ()),
5322 gdbarch_byte_order (gdbarch
),
5323 readbuf
, writebuf
, offset
);
5325 return RETURN_VALUE_REGISTER_CONVENTION
;
5327 else if (type
->code () == TYPE_CODE_STRUCT
5328 || type
->code () == TYPE_CODE_UNION
5329 || type
->code () == TYPE_CODE_ARRAY
)
5331 /* A composite type. Extract the left justified value,
5332 regardless of the byte order. I.e. DO NOT USE
5336 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5337 offset
< TYPE_LENGTH (type
);
5338 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5340 int xfer
= register_size (gdbarch
, regnum
);
5341 if (offset
+ xfer
> TYPE_LENGTH (type
))
5342 xfer
= TYPE_LENGTH (type
) - offset
;
5344 gdb_printf (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5345 offset
, xfer
, regnum
);
5346 mips_xfer_register (gdbarch
, regcache
,
5347 gdbarch_num_regs (gdbarch
) + regnum
,
5348 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5351 return RETURN_VALUE_REGISTER_CONVENTION
;
5355 /* A scalar extract each part but least-significant-byte
5359 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5360 offset
< TYPE_LENGTH (type
);
5361 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5363 int xfer
= register_size (gdbarch
, regnum
);
5364 if (offset
+ xfer
> TYPE_LENGTH (type
))
5365 xfer
= TYPE_LENGTH (type
) - offset
;
5367 gdb_printf (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5368 offset
, xfer
, regnum
);
5369 mips_xfer_register (gdbarch
, regcache
,
5370 gdbarch_num_regs (gdbarch
) + regnum
,
5371 xfer
, gdbarch_byte_order (gdbarch
),
5372 readbuf
, writebuf
, offset
);
5374 return RETURN_VALUE_REGISTER_CONVENTION
;
5378 /* Which registers to use for passing floating-point values between
5379 function calls, one of floating-point, general and both kinds of
5380 registers. O32 and O64 use different register kinds for standard
5381 MIPS and MIPS16 code; to make the handling of cases where we may
5382 not know what kind of code is being used (e.g. no debug information)
5383 easier we sometimes use both kinds. */
5392 /* O32 ABI stuff. */
5395 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5396 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5397 int nargs
, struct value
**args
, CORE_ADDR sp
,
5398 function_call_return_method return_method
,
5399 CORE_ADDR struct_addr
)
5405 int stack_offset
= 0;
5406 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5407 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5409 /* For shared libraries, "t9" needs to point at the function
5411 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5413 /* Set the return address register to point to the entry point of
5414 the program, where a breakpoint lies in wait. */
5415 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5417 /* First ensure that the stack and structure return address (if any)
5418 are properly aligned. The stack has to be at least 64-bit
5419 aligned even on 32-bit machines, because doubles must be 64-bit
5420 aligned. For n32 and n64, stack frames need to be 128-bit
5421 aligned, so we round to this widest known alignment. */
5423 sp
= align_down (sp
, 16);
5424 struct_addr
= align_down (struct_addr
, 16);
5426 /* Now make space on the stack for the args. */
5427 for (argnum
= 0; argnum
< nargs
; argnum
++)
5429 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5431 /* Align to double-word if necessary. */
5432 if (mips_type_needs_double_align (arg_type
))
5433 arg_space
= align_up (arg_space
, MIPS32_REGSIZE
* 2);
5434 /* Allocate space on the stack. */
5435 arg_space
+= align_up (TYPE_LENGTH (arg_type
), MIPS32_REGSIZE
);
5437 sp
-= align_up (arg_space
, 16);
5440 gdb_printf (gdb_stdlog
,
5441 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5442 paddress (gdbarch
, sp
),
5443 (long) align_up (arg_space
, 16));
5445 /* Initialize the integer and float register pointers. */
5446 argreg
= MIPS_A0_REGNUM
;
5447 float_argreg
= mips_fpa0_regnum (gdbarch
);
5449 /* The struct_return pointer occupies the first parameter-passing reg. */
5450 if (return_method
== return_method_struct
)
5453 gdb_printf (gdb_stdlog
,
5454 "mips_o32_push_dummy_call: "
5455 "struct_return reg=%d %s\n",
5456 argreg
, paddress (gdbarch
, struct_addr
));
5457 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5458 stack_offset
+= MIPS32_REGSIZE
;
5461 /* Now load as many as possible of the first arguments into
5462 registers, and push the rest onto the stack. Loop thru args
5463 from first to last. */
5464 for (argnum
= 0; argnum
< nargs
; argnum
++)
5466 const gdb_byte
*val
;
5467 struct value
*arg
= args
[argnum
];
5468 struct type
*arg_type
= check_typedef (value_type (arg
));
5469 int len
= TYPE_LENGTH (arg_type
);
5470 enum type_code typecode
= arg_type
->code ();
5473 gdb_printf (gdb_stdlog
,
5474 "mips_o32_push_dummy_call: %d len=%d type=%d",
5475 argnum
+ 1, len
, (int) typecode
);
5477 val
= value_contents (arg
).data ();
5479 /* 32-bit ABIs always start floating point arguments in an
5480 even-numbered floating point register. Round the FP register
5481 up before the check to see if there are any FP registers
5482 left. O32 targets also pass the FP in the integer registers
5483 so also round up normal registers. */
5484 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5486 if ((float_argreg
& 1))
5490 /* Floating point arguments passed in registers have to be
5491 treated specially. On 32-bit architectures, doubles are
5492 passed in register pairs; the even FP register gets the
5493 low word, and the odd FP register gets the high word.
5494 On O32, the first two floating point arguments are also
5495 copied to general registers, following their memory order,
5496 because MIPS16 functions don't use float registers for
5497 arguments. This duplication of arguments in general
5498 registers can't hurt non-MIPS16 functions, because those
5499 registers are normally skipped. */
5501 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5502 && float_argreg
<= mips_last_fp_arg_regnum (gdbarch
))
5504 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5506 int freg_offset
= gdbarch_byte_order (gdbarch
)
5507 == BFD_ENDIAN_BIG
? 1 : 0;
5508 unsigned long regval
;
5511 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5513 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5514 float_argreg
+ freg_offset
,
5516 regcache_cooked_write_unsigned (regcache
,
5517 float_argreg
++ + freg_offset
,
5520 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5521 argreg
, phex (regval
, 4));
5522 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5525 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5527 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5528 float_argreg
- freg_offset
,
5530 regcache_cooked_write_unsigned (regcache
,
5531 float_argreg
++ - freg_offset
,
5534 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5535 argreg
, phex (regval
, 4));
5536 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5540 /* This is a floating point value that fits entirely
5541 in a single register. */
5542 /* On 32 bit ABI's the float_argreg is further adjusted
5543 above to ensure that it is even register aligned. */
5544 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5546 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5547 float_argreg
, phex (regval
, len
));
5548 regcache_cooked_write_unsigned (regcache
,
5549 float_argreg
++, regval
);
5550 /* Although two FP registers are reserved for each
5551 argument, only one corresponding integer register is
5554 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5555 argreg
, phex (regval
, len
));
5556 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5558 /* Reserve space for the FP register. */
5559 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5563 /* Copy the argument to general registers or the stack in
5564 register-sized pieces. Large arguments are split between
5565 registers and stack. */
5566 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5567 are treated specially: Irix cc passes
5568 them in registers where gcc sometimes puts them on the
5569 stack. For maximum compatibility, we will put them in
5571 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5572 && len
% MIPS32_REGSIZE
!= 0);
5573 /* Structures should be aligned to eight bytes (even arg registers)
5574 on MIPS_ABI_O32, if their first member has double precision. */
5575 if (mips_type_needs_double_align (arg_type
))
5580 stack_offset
+= MIPS32_REGSIZE
;
5585 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5588 gdb_printf (gdb_stdlog
, " -- partial=%d",
5591 /* Write this portion of the argument to the stack. */
5592 if (argreg
> mips_last_arg_regnum (gdbarch
)
5593 || odd_sized_struct
)
5595 /* Should shorter than int integer values be
5596 promoted to int before being stored? */
5597 int longword_offset
= 0;
5602 gdb_printf (gdb_stdlog
, " - stack_offset=%s",
5603 paddress (gdbarch
, stack_offset
));
5604 gdb_printf (gdb_stdlog
, " longword_offset=%s",
5605 paddress (gdbarch
, longword_offset
));
5608 addr
= sp
+ stack_offset
+ longword_offset
;
5613 gdb_printf (gdb_stdlog
, " @%s ",
5614 paddress (gdbarch
, addr
));
5615 for (i
= 0; i
< partial_len
; i
++)
5617 gdb_printf (gdb_stdlog
, "%02x",
5621 write_memory (addr
, val
, partial_len
);
5624 /* Note!!! This is NOT an else clause. Odd sized
5625 structs may go thru BOTH paths. */
5626 /* Write this portion of the argument to a general
5627 purpose register. */
5628 if (argreg
<= mips_last_arg_regnum (gdbarch
))
5630 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5632 /* Value may need to be sign extended, because
5633 mips_isa_regsize() != mips_abi_regsize(). */
5635 /* A non-floating-point argument being passed in a
5636 general register. If a struct or union, and if
5637 the remaining length is smaller than the register
5638 size, we have to adjust the register value on
5641 It does not seem to be necessary to do the
5642 same for integral types.
5644 Also don't do this adjustment on O64 binaries.
5646 cagney/2001-07-23: gdb/179: Also, GCC, when
5647 outputting LE O32 with sizeof (struct) <
5648 mips_abi_regsize(), generates a left shift
5649 as part of storing the argument in a register
5650 (the left shift isn't generated when
5651 sizeof (struct) >= mips_abi_regsize()). Since
5652 it is quite possible that this is GCC
5653 contradicting the LE/O32 ABI, GDB has not been
5654 adjusted to accommodate this. Either someone
5655 needs to demonstrate that the LE/O32 ABI
5656 specifies such a left shift OR this new ABI gets
5657 identified as such and GDB gets tweaked
5660 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5661 && partial_len
< MIPS32_REGSIZE
5662 && (typecode
== TYPE_CODE_STRUCT
5663 || typecode
== TYPE_CODE_UNION
))
5664 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5668 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5670 phex (regval
, MIPS32_REGSIZE
));
5671 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5674 /* Prevent subsequent floating point arguments from
5675 being passed in floating point registers. */
5676 float_argreg
= mips_last_fp_arg_regnum (gdbarch
) + 1;
5682 /* Compute the offset into the stack at which we will
5683 copy the next parameter.
5685 In older ABIs, the caller reserved space for
5686 registers that contained arguments. This was loosely
5687 refered to as their "home". Consequently, space is
5688 always allocated. */
5690 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5694 gdb_printf (gdb_stdlog
, "\n");
5697 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5699 /* Return adjusted stack pointer. */
5703 static enum return_value_convention
5704 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5705 struct type
*type
, struct regcache
*regcache
,
5706 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5708 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5709 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5710 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
5711 enum mips_fval_reg fval_reg
;
5713 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5714 if (type
->code () == TYPE_CODE_STRUCT
5715 || type
->code () == TYPE_CODE_UNION
5716 || type
->code () == TYPE_CODE_ARRAY
)
5717 return RETURN_VALUE_STRUCT_CONVENTION
;
5718 else if (type
->code () == TYPE_CODE_FLT
5719 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5721 /* A single-precision floating-point value. If reading in or copying,
5722 then we get it from/put it to FP0 for standard MIPS code or GPR2
5723 for MIPS16 code. If writing out only, then we put it to both FP0
5724 and GPR2. We do not support reading in with no function known, if
5725 this safety check ever triggers, then we'll have to try harder. */
5726 gdb_assert (function
|| !readbuf
);
5731 gdb_printf (gdb_stderr
, "Return float in $fp0\n");
5734 gdb_printf (gdb_stderr
, "Return float in $2\n");
5736 case mips_fval_both
:
5737 gdb_printf (gdb_stderr
, "Return float in $fp0 and $2\n");
5740 if (fval_reg
!= mips_fval_gpr
)
5741 mips_xfer_register (gdbarch
, regcache
,
5742 (gdbarch_num_regs (gdbarch
)
5743 + mips_regnum (gdbarch
)->fp0
),
5745 gdbarch_byte_order (gdbarch
),
5746 readbuf
, writebuf
, 0);
5747 if (fval_reg
!= mips_fval_fpr
)
5748 mips_xfer_register (gdbarch
, regcache
,
5749 gdbarch_num_regs (gdbarch
) + 2,
5751 gdbarch_byte_order (gdbarch
),
5752 readbuf
, writebuf
, 0);
5753 return RETURN_VALUE_REGISTER_CONVENTION
;
5755 else if (type
->code () == TYPE_CODE_FLT
5756 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5758 /* A double-precision floating-point value. If reading in or copying,
5759 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5760 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5761 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5762 no function known, if this safety check ever triggers, then we'll
5763 have to try harder. */
5764 gdb_assert (function
|| !readbuf
);
5769 gdb_printf (gdb_stderr
, "Return float in $fp1/$fp0\n");
5772 gdb_printf (gdb_stderr
, "Return float in $2/$3\n");
5774 case mips_fval_both
:
5775 gdb_printf (gdb_stderr
,
5776 "Return float in $fp1/$fp0 and $2/$3\n");
5779 if (fval_reg
!= mips_fval_gpr
)
5781 /* The most significant part goes in FP1, and the least significant
5783 switch (gdbarch_byte_order (gdbarch
))
5785 case BFD_ENDIAN_LITTLE
:
5786 mips_xfer_register (gdbarch
, regcache
,
5787 (gdbarch_num_regs (gdbarch
)
5788 + mips_regnum (gdbarch
)->fp0
+ 0),
5789 4, gdbarch_byte_order (gdbarch
),
5790 readbuf
, writebuf
, 0);
5791 mips_xfer_register (gdbarch
, regcache
,
5792 (gdbarch_num_regs (gdbarch
)
5793 + mips_regnum (gdbarch
)->fp0
+ 1),
5794 4, gdbarch_byte_order (gdbarch
),
5795 readbuf
, writebuf
, 4);
5797 case BFD_ENDIAN_BIG
:
5798 mips_xfer_register (gdbarch
, regcache
,
5799 (gdbarch_num_regs (gdbarch
)
5800 + mips_regnum (gdbarch
)->fp0
+ 1),
5801 4, gdbarch_byte_order (gdbarch
),
5802 readbuf
, writebuf
, 0);
5803 mips_xfer_register (gdbarch
, regcache
,
5804 (gdbarch_num_regs (gdbarch
)
5805 + mips_regnum (gdbarch
)->fp0
+ 0),
5806 4, gdbarch_byte_order (gdbarch
),
5807 readbuf
, writebuf
, 4);
5810 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5813 if (fval_reg
!= mips_fval_fpr
)
5815 /* The two 32-bit parts are always placed in GPR2 and GPR3
5816 following these registers' memory order. */
5817 mips_xfer_register (gdbarch
, regcache
,
5818 gdbarch_num_regs (gdbarch
) + 2,
5819 4, gdbarch_byte_order (gdbarch
),
5820 readbuf
, writebuf
, 0);
5821 mips_xfer_register (gdbarch
, regcache
,
5822 gdbarch_num_regs (gdbarch
) + 3,
5823 4, gdbarch_byte_order (gdbarch
),
5824 readbuf
, writebuf
, 4);
5826 return RETURN_VALUE_REGISTER_CONVENTION
;
5829 else if (type
->code () == TYPE_CODE_STRUCT
5830 && type
->num_fields () <= 2
5831 && type
->num_fields () >= 1
5832 && ((type
->num_fields () == 1
5833 && (TYPE_CODE (type
->field (0).type ())
5835 || (type
->num_fields () == 2
5836 && (TYPE_CODE (type
->field (0).type ())
5838 && (TYPE_CODE (type
->field (1).type ())
5840 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5842 /* A struct that contains one or two floats. Each value is part
5843 in the least significant part of their floating point
5847 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5848 field
< type
->num_fields (); field
++, regnum
+= 2)
5850 int offset
= (type
->fields ()[field
].loc_bitpos () / TARGET_CHAR_BIT
);
5852 gdb_printf (gdb_stderr
, "Return float struct+%d\n",
5854 mips_xfer_register (gdbarch
, regcache
,
5855 gdbarch_num_regs (gdbarch
) + regnum
,
5856 TYPE_LENGTH (type
->field (field
).type ()),
5857 gdbarch_byte_order (gdbarch
),
5858 readbuf
, writebuf
, offset
);
5860 return RETURN_VALUE_REGISTER_CONVENTION
;
5864 else if (type
->code () == TYPE_CODE_STRUCT
5865 || type
->code () == TYPE_CODE_UNION
)
5867 /* A structure or union. Extract the left justified value,
5868 regardless of the byte order. I.e. DO NOT USE
5872 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5873 offset
< TYPE_LENGTH (type
);
5874 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5876 int xfer
= register_size (gdbarch
, regnum
);
5877 if (offset
+ xfer
> TYPE_LENGTH (type
))
5878 xfer
= TYPE_LENGTH (type
) - offset
;
5880 gdb_printf (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5881 offset
, xfer
, regnum
);
5882 mips_xfer_register (gdbarch
, regcache
,
5883 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5884 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5886 return RETURN_VALUE_REGISTER_CONVENTION
;
5891 /* A scalar extract each part but least-significant-byte
5892 justified. o32 thinks registers are 4 byte, regardless of
5896 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5897 offset
< TYPE_LENGTH (type
);
5898 offset
+= MIPS32_REGSIZE
, regnum
++)
5900 int xfer
= MIPS32_REGSIZE
;
5901 if (offset
+ xfer
> TYPE_LENGTH (type
))
5902 xfer
= TYPE_LENGTH (type
) - offset
;
5904 gdb_printf (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5905 offset
, xfer
, regnum
);
5906 mips_xfer_register (gdbarch
, regcache
,
5907 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5908 gdbarch_byte_order (gdbarch
),
5909 readbuf
, writebuf
, offset
);
5911 return RETURN_VALUE_REGISTER_CONVENTION
;
5915 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5919 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5920 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5922 struct value
**args
, CORE_ADDR sp
,
5923 function_call_return_method return_method
, CORE_ADDR struct_addr
)
5929 int stack_offset
= 0;
5930 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5931 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5933 /* For shared libraries, "t9" needs to point at the function
5935 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5937 /* Set the return address register to point to the entry point of
5938 the program, where a breakpoint lies in wait. */
5939 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5941 /* First ensure that the stack and structure return address (if any)
5942 are properly aligned. The stack has to be at least 64-bit
5943 aligned even on 32-bit machines, because doubles must be 64-bit
5944 aligned. For n32 and n64, stack frames need to be 128-bit
5945 aligned, so we round to this widest known alignment. */
5947 sp
= align_down (sp
, 16);
5948 struct_addr
= align_down (struct_addr
, 16);
5950 /* Now make space on the stack for the args. */
5951 for (argnum
= 0; argnum
< nargs
; argnum
++)
5953 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5955 /* Allocate space on the stack. */
5956 arg_space
+= align_up (TYPE_LENGTH (arg_type
), MIPS64_REGSIZE
);
5958 sp
-= align_up (arg_space
, 16);
5961 gdb_printf (gdb_stdlog
,
5962 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5963 paddress (gdbarch
, sp
),
5964 (long) align_up (arg_space
, 16));
5966 /* Initialize the integer and float register pointers. */
5967 argreg
= MIPS_A0_REGNUM
;
5968 float_argreg
= mips_fpa0_regnum (gdbarch
);
5970 /* The struct_return pointer occupies the first parameter-passing reg. */
5971 if (return_method
== return_method_struct
)
5974 gdb_printf (gdb_stdlog
,
5975 "mips_o64_push_dummy_call: "
5976 "struct_return reg=%d %s\n",
5977 argreg
, paddress (gdbarch
, struct_addr
));
5978 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5979 stack_offset
+= MIPS64_REGSIZE
;
5982 /* Now load as many as possible of the first arguments into
5983 registers, and push the rest onto the stack. Loop thru args
5984 from first to last. */
5985 for (argnum
= 0; argnum
< nargs
; argnum
++)
5987 const gdb_byte
*val
;
5988 struct value
*arg
= args
[argnum
];
5989 struct type
*arg_type
= check_typedef (value_type (arg
));
5990 int len
= TYPE_LENGTH (arg_type
);
5991 enum type_code typecode
= arg_type
->code ();
5994 gdb_printf (gdb_stdlog
,
5995 "mips_o64_push_dummy_call: %d len=%d type=%d",
5996 argnum
+ 1, len
, (int) typecode
);
5998 val
= value_contents (arg
).data ();
6000 /* Floating point arguments passed in registers have to be
6001 treated specially. On 32-bit architectures, doubles are
6002 passed in register pairs; the even FP register gets the
6003 low word, and the odd FP register gets the high word.
6004 On O64, the first two floating point arguments are also
6005 copied to general registers, because MIPS16 functions
6006 don't use float registers for arguments. This duplication
6007 of arguments in general registers can't hurt non-MIPS16
6008 functions because those registers are normally skipped. */
6010 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
6011 && float_argreg
<= mips_last_fp_arg_regnum (gdbarch
))
6013 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
6015 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
6016 float_argreg
, phex (regval
, len
));
6017 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
6019 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
6020 argreg
, phex (regval
, len
));
6021 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6023 /* Reserve space for the FP register. */
6024 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
6028 /* Copy the argument to general registers or the stack in
6029 register-sized pieces. Large arguments are split between
6030 registers and stack. */
6031 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
6032 are treated specially: Irix cc passes them in registers
6033 where gcc sometimes puts them on the stack. For maximum
6034 compatibility, we will put them in both places. */
6035 int odd_sized_struct
= (len
> MIPS64_REGSIZE
6036 && len
% MIPS64_REGSIZE
!= 0);
6039 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
6042 gdb_printf (gdb_stdlog
, " -- partial=%d",
6045 /* Write this portion of the argument to the stack. */
6046 if (argreg
> mips_last_arg_regnum (gdbarch
)
6047 || odd_sized_struct
)
6049 /* Should shorter than int integer values be
6050 promoted to int before being stored? */
6051 int longword_offset
= 0;
6053 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6055 if ((typecode
== TYPE_CODE_INT
6056 || typecode
== TYPE_CODE_PTR
6057 || typecode
== TYPE_CODE_FLT
)
6059 longword_offset
= MIPS64_REGSIZE
- len
;
6064 gdb_printf (gdb_stdlog
, " - stack_offset=%s",
6065 paddress (gdbarch
, stack_offset
));
6066 gdb_printf (gdb_stdlog
, " longword_offset=%s",
6067 paddress (gdbarch
, longword_offset
));
6070 addr
= sp
+ stack_offset
+ longword_offset
;
6075 gdb_printf (gdb_stdlog
, " @%s ",
6076 paddress (gdbarch
, addr
));
6077 for (i
= 0; i
< partial_len
; i
++)
6079 gdb_printf (gdb_stdlog
, "%02x",
6083 write_memory (addr
, val
, partial_len
);
6086 /* Note!!! This is NOT an else clause. Odd sized
6087 structs may go thru BOTH paths. */
6088 /* Write this portion of the argument to a general
6089 purpose register. */
6090 if (argreg
<= mips_last_arg_regnum (gdbarch
))
6092 LONGEST regval
= extract_signed_integer (val
, partial_len
,
6094 /* Value may need to be sign extended, because
6095 mips_isa_regsize() != mips_abi_regsize(). */
6097 /* A non-floating-point argument being passed in a
6098 general register. If a struct or union, and if
6099 the remaining length is smaller than the register
6100 size, we have to adjust the register value on
6103 It does not seem to be necessary to do the
6104 same for integral types. */
6106 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
6107 && partial_len
< MIPS64_REGSIZE
6108 && (typecode
== TYPE_CODE_STRUCT
6109 || typecode
== TYPE_CODE_UNION
))
6110 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
6114 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
6116 phex (regval
, MIPS64_REGSIZE
));
6117 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6120 /* Prevent subsequent floating point arguments from
6121 being passed in floating point registers. */
6122 float_argreg
= mips_last_fp_arg_regnum (gdbarch
) + 1;
6128 /* Compute the offset into the stack at which we will
6129 copy the next parameter.
6131 In older ABIs, the caller reserved space for
6132 registers that contained arguments. This was loosely
6133 refered to as their "home". Consequently, space is
6134 always allocated. */
6136 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
6140 gdb_printf (gdb_stdlog
, "\n");
6143 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
6145 /* Return adjusted stack pointer. */
6149 static enum return_value_convention
6150 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
6151 struct type
*type
, struct regcache
*regcache
,
6152 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
6154 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
6155 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
6156 enum mips_fval_reg fval_reg
;
6158 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
6159 if (type
->code () == TYPE_CODE_STRUCT
6160 || type
->code () == TYPE_CODE_UNION
6161 || type
->code () == TYPE_CODE_ARRAY
)
6162 return RETURN_VALUE_STRUCT_CONVENTION
;
6163 else if (fp_register_arg_p (gdbarch
, type
->code (), type
))
6165 /* A floating-point value. If reading in or copying, then we get it
6166 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
6167 If writing out only, then we put it to both FP0 and GPR2. We do
6168 not support reading in with no function known, if this safety
6169 check ever triggers, then we'll have to try harder. */
6170 gdb_assert (function
|| !readbuf
);
6175 gdb_printf (gdb_stderr
, "Return float in $fp0\n");
6178 gdb_printf (gdb_stderr
, "Return float in $2\n");
6180 case mips_fval_both
:
6181 gdb_printf (gdb_stderr
, "Return float in $fp0 and $2\n");
6184 if (fval_reg
!= mips_fval_gpr
)
6185 mips_xfer_register (gdbarch
, regcache
,
6186 (gdbarch_num_regs (gdbarch
)
6187 + mips_regnum (gdbarch
)->fp0
),
6189 gdbarch_byte_order (gdbarch
),
6190 readbuf
, writebuf
, 0);
6191 if (fval_reg
!= mips_fval_fpr
)
6192 mips_xfer_register (gdbarch
, regcache
,
6193 gdbarch_num_regs (gdbarch
) + 2,
6195 gdbarch_byte_order (gdbarch
),
6196 readbuf
, writebuf
, 0);
6197 return RETURN_VALUE_REGISTER_CONVENTION
;
6201 /* A scalar extract each part but least-significant-byte
6205 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
6206 offset
< TYPE_LENGTH (type
);
6207 offset
+= MIPS64_REGSIZE
, regnum
++)
6209 int xfer
= MIPS64_REGSIZE
;
6210 if (offset
+ xfer
> TYPE_LENGTH (type
))
6211 xfer
= TYPE_LENGTH (type
) - offset
;
6213 gdb_printf (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
6214 offset
, xfer
, regnum
);
6215 mips_xfer_register (gdbarch
, regcache
,
6216 gdbarch_num_regs (gdbarch
) + regnum
,
6217 xfer
, gdbarch_byte_order (gdbarch
),
6218 readbuf
, writebuf
, offset
);
6220 return RETURN_VALUE_REGISTER_CONVENTION
;
6224 /* Floating point register management.
6226 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
6227 64bit operations, these early MIPS cpus treat fp register pairs
6228 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6229 registers and offer a compatibility mode that emulates the MIPS2 fp
6230 model. When operating in MIPS2 fp compat mode, later cpu's split
6231 double precision floats into two 32-bit chunks and store them in
6232 consecutive fp regs. To display 64-bit floats stored in this
6233 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6234 Throw in user-configurable endianness and you have a real mess.
6236 The way this works is:
6237 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6238 double-precision value will be split across two logical registers.
6239 The lower-numbered logical register will hold the low-order bits,
6240 regardless of the processor's endianness.
6241 - If we are on a 64-bit processor, and we are looking for a
6242 single-precision value, it will be in the low ordered bits
6243 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6244 save slot in memory.
6245 - If we are in 64-bit mode, everything is straightforward.
6247 Note that this code only deals with "live" registers at the top of the
6248 stack. We will attempt to deal with saved registers later, when
6249 the raw/cooked register interface is in place. (We need a general
6250 interface that can deal with dynamic saved register sizes -- fp
6251 regs could be 32 bits wide in one frame and 64 on the frame above
6254 /* Copy a 32-bit single-precision value from the current frame
6255 into rare_buffer. */
6258 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
6259 gdb_byte
*rare_buffer
)
6261 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6262 int raw_size
= register_size (gdbarch
, regno
);
6263 gdb_byte
*raw_buffer
= (gdb_byte
*) alloca (raw_size
);
6265 if (!deprecated_frame_register_read (frame
, regno
, raw_buffer
))
6266 error (_("can't read register %d (%s)"),
6267 regno
, gdbarch_register_name (gdbarch
, regno
));
6270 /* We have a 64-bit value for this register. Find the low-order
6274 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6279 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
6283 memcpy (rare_buffer
, raw_buffer
, 4);
6287 /* Copy a 64-bit double-precision value from the current frame into
6288 rare_buffer. This may include getting half of it from the next
6292 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
6293 gdb_byte
*rare_buffer
)
6295 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6296 int raw_size
= register_size (gdbarch
, regno
);
6298 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6300 /* We have a 64-bit value for this register, and we should use
6302 if (!deprecated_frame_register_read (frame
, regno
, rare_buffer
))
6303 error (_("can't read register %d (%s)"),
6304 regno
, gdbarch_register_name (gdbarch
, regno
));
6308 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6310 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6311 internal_error (__FILE__
, __LINE__
,
6312 _("mips_read_fp_register_double: bad access to "
6313 "odd-numbered FP register"));
6315 /* mips_read_fp_register_single will find the correct 32 bits from
6317 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6319 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6320 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6324 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6325 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6331 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
6333 { /* Do values for FP (float) regs. */
6334 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6335 gdb_byte
*raw_buffer
;
6336 std::string flt_str
, dbl_str
;
6338 const struct type
*flt_type
= builtin_type (gdbarch
)->builtin_float
;
6339 const struct type
*dbl_type
= builtin_type (gdbarch
)->builtin_double
;
6343 alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
)));
6345 gdb_printf (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6346 gdb_printf (file
, "%*s",
6347 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6350 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6352 struct value_print_options opts
;
6354 /* 4-byte registers: Print hex and floating. Also print even
6355 numbered registers as doubles. */
6356 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6357 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6359 get_formatted_print_options (&opts
, 'x');
6360 print_scalar_formatted (raw_buffer
,
6361 builtin_type (gdbarch
)->builtin_uint32
,
6364 gdb_printf (file
, " flt: %s", flt_str
.c_str ());
6366 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6368 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6369 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6371 gdb_printf (file
, " dbl: %s", dbl_str
.c_str ());
6376 struct value_print_options opts
;
6378 /* Eight byte registers: print each one as hex, float and double. */
6379 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6380 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6382 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6383 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6385 get_formatted_print_options (&opts
, 'x');
6386 print_scalar_formatted (raw_buffer
,
6387 builtin_type (gdbarch
)->builtin_uint64
,
6390 gdb_printf (file
, " flt: %s", flt_str
.c_str ());
6391 gdb_printf (file
, " dbl: %s", dbl_str
.c_str ());
6396 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
6399 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6400 struct value_print_options opts
;
6403 if (mips_float_register_p (gdbarch
, regnum
))
6405 mips_print_fp_register (file
, frame
, regnum
);
6409 val
= get_frame_register_value (frame
, regnum
);
6411 gdb_puts (gdbarch_register_name (gdbarch
, regnum
), file
);
6413 /* The problem with printing numeric register names (r26, etc.) is that
6414 the user can't use them on input. Probably the best solution is to
6415 fix it so that either the numeric or the funky (a2, etc.) names
6416 are accepted on input. */
6417 if (regnum
< MIPS_NUMREGS
)
6418 gdb_printf (file
, "(r%d): ", regnum
);
6420 gdb_printf (file
, ": ");
6422 get_formatted_print_options (&opts
, 'x');
6423 value_print_scalar_formatted (val
, &opts
, 0, file
);
6426 /* Print IEEE exception condition bits in FLAGS. */
6429 print_fpu_flags (struct ui_file
*file
, int flags
)
6431 if (flags
& (1 << 0))
6432 gdb_puts (" inexact", file
);
6433 if (flags
& (1 << 1))
6434 gdb_puts (" uflow", file
);
6435 if (flags
& (1 << 2))
6436 gdb_puts (" oflow", file
);
6437 if (flags
& (1 << 3))
6438 gdb_puts (" div0", file
);
6439 if (flags
& (1 << 4))
6440 gdb_puts (" inval", file
);
6441 if (flags
& (1 << 5))
6442 gdb_puts (" unimp", file
);
6443 gdb_putc ('\n', file
);
6446 /* Print interesting information about the floating point processor
6447 (if present) or emulator. */
6450 mips_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6451 struct frame_info
*frame
, const char *args
)
6453 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
6454 enum mips_fpu_type type
= mips_get_fpu_type (gdbarch
);
6458 if (fcsr
== -1 || !read_frame_register_unsigned (frame
, fcsr
, &fcs
))
6459 type
= MIPS_FPU_NONE
;
6461 gdb_printf (file
, "fpu type: %s\n",
6462 type
== MIPS_FPU_DOUBLE
? "double-precision"
6463 : type
== MIPS_FPU_SINGLE
? "single-precision"
6466 if (type
== MIPS_FPU_NONE
)
6469 gdb_printf (file
, "reg size: %d bits\n",
6470 register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) * 8);
6472 gdb_puts ("cond :", file
);
6473 if (fcs
& (1 << 23))
6474 gdb_puts (" 0", file
);
6475 for (i
= 1; i
<= 7; i
++)
6476 if (fcs
& (1 << (24 + i
)))
6477 gdb_printf (file
, " %d", i
);
6478 gdb_putc ('\n', file
);
6480 gdb_puts ("cause :", file
);
6481 print_fpu_flags (file
, (fcs
>> 12) & 0x3f);
6482 fputs ("mask :", stdout
);
6483 print_fpu_flags (file
, (fcs
>> 7) & 0x1f);
6484 fputs ("flags :", stdout
);
6485 print_fpu_flags (file
, (fcs
>> 2) & 0x1f);
6487 gdb_puts ("rounding: ", file
);
6490 case 0: gdb_puts ("nearest\n", file
); break;
6491 case 1: gdb_puts ("zero\n", file
); break;
6492 case 2: gdb_puts ("+inf\n", file
); break;
6493 case 3: gdb_puts ("-inf\n", file
); break;
6496 gdb_puts ("flush :", file
);
6497 if (fcs
& (1 << 21))
6498 gdb_puts (" nearest", file
);
6499 if (fcs
& (1 << 22))
6500 gdb_puts (" override", file
);
6501 if (fcs
& (1 << 24))
6502 gdb_puts (" zero", file
);
6503 if ((fcs
& (0xb << 21)) == 0)
6504 gdb_puts (" no", file
);
6505 gdb_putc ('\n', file
);
6507 gdb_printf (file
, "nan2008 : %s\n", fcs
& (1 << 18) ? "yes" : "no");
6508 gdb_printf (file
, "abs2008 : %s\n", fcs
& (1 << 19) ? "yes" : "no");
6509 gdb_putc ('\n', file
);
6511 default_print_float_info (gdbarch
, file
, frame
, args
);
6514 /* Replacement for generic do_registers_info.
6515 Print regs in pretty columns. */
6518 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6521 gdb_printf (file
, " ");
6522 mips_print_fp_register (file
, frame
, regnum
);
6523 gdb_printf (file
, "\n");
6528 /* Print a row's worth of GP (int) registers, with name labels above. */
6531 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6534 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6535 /* Do values for GP (int) regs. */
6536 const gdb_byte
*raw_buffer
;
6537 struct value
*value
;
6538 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6543 /* For GP registers, we print a separate row of names above the vals. */
6544 for (col
= 0, regnum
= start_regnum
;
6545 col
< ncols
&& regnum
< gdbarch_num_cooked_regs (gdbarch
);
6548 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6549 continue; /* unused register */
6550 if (mips_float_register_p (gdbarch
, regnum
))
6551 break; /* End the row: reached FP register. */
6552 /* Large registers are handled separately. */
6553 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6556 break; /* End the row before this register. */
6558 /* Print this register on a row by itself. */
6559 mips_print_register (file
, frame
, regnum
);
6560 gdb_printf (file
, "\n");
6564 gdb_printf (file
, " ");
6566 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6567 gdbarch_register_name (gdbarch
, regnum
));
6574 /* Print the R0 to R31 names. */
6575 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6576 gdb_printf (file
, "\n R%-4d",
6577 start_regnum
% gdbarch_num_regs (gdbarch
));
6579 gdb_printf (file
, "\n ");
6581 /* Now print the values in hex, 4 or 8 to the row. */
6582 for (col
= 0, regnum
= start_regnum
;
6583 col
< ncols
&& regnum
< gdbarch_num_cooked_regs (gdbarch
);
6586 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6587 continue; /* unused register */
6588 if (mips_float_register_p (gdbarch
, regnum
))
6589 break; /* End row: reached FP register. */
6590 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6591 break; /* End row: large register. */
6593 /* OK: get the data in raw format. */
6594 value
= get_frame_register_value (frame
, regnum
);
6595 if (value_optimized_out (value
)
6596 || !value_entirely_available (value
))
6598 gdb_printf (file
, "%*s ",
6599 (int) mips_abi_regsize (gdbarch
) * 2,
6600 (mips_abi_regsize (gdbarch
) == 4 ? "<unavl>"
6601 : "<unavailable>"));
6605 raw_buffer
= value_contents_all (value
).data ();
6606 /* pad small registers */
6608 byte
< (mips_abi_regsize (gdbarch
)
6609 - register_size (gdbarch
, regnum
)); byte
++)
6610 gdb_printf (file
, " ");
6611 /* Now print the register value in hex, endian order. */
6612 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6614 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6615 byte
< register_size (gdbarch
, regnum
); byte
++)
6616 gdb_printf (file
, "%02x", raw_buffer
[byte
]);
6618 for (byte
= register_size (gdbarch
, regnum
) - 1;
6620 gdb_printf (file
, "%02x", raw_buffer
[byte
]);
6621 gdb_printf (file
, " ");
6624 if (col
> 0) /* ie. if we actually printed anything... */
6625 gdb_printf (file
, "\n");
6630 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6633 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6634 struct frame_info
*frame
, int regnum
, int all
)
6636 if (regnum
!= -1) /* Do one specified register. */
6638 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6639 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6640 error (_("Not a valid register for the current processor type"));
6642 mips_print_register (file
, frame
, regnum
);
6643 gdb_printf (file
, "\n");
6646 /* Do all (or most) registers. */
6648 regnum
= gdbarch_num_regs (gdbarch
);
6649 while (regnum
< gdbarch_num_cooked_regs (gdbarch
))
6651 if (mips_float_register_p (gdbarch
, regnum
))
6653 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6654 regnum
= print_fp_register_row (file
, frame
, regnum
);
6656 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6659 regnum
= print_gp_register_row (file
, frame
, regnum
);
6665 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6666 struct frame_info
*frame
)
6668 CORE_ADDR pc
= get_frame_pc (frame
);
6673 if ((mips_pc_is_mips (pc
)
6674 && !mips32_insn_at_pc_has_delay_slot (gdbarch
, pc
))
6675 || (mips_pc_is_micromips (gdbarch
, pc
)
6676 && !micromips_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0))
6677 || (mips_pc_is_mips16 (gdbarch
, pc
)
6678 && !mips16_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0)))
6681 isa
= mips_pc_isa (gdbarch
, pc
);
6682 /* _has_delay_slot above will have validated the read. */
6683 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6684 size
= mips_insn_size (isa
, insn
);
6686 const address_space
*aspace
= get_frame_address_space (frame
);
6688 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6691 /* To skip prologues, I use this predicate. Returns either PC itself
6692 if the code at PC does not look like a function prologue; otherwise
6693 returns an address that (if we're lucky) follows the prologue. If
6694 LENIENT, then we must skip everything which is involved in setting
6695 up the frame (it's OK to skip more, just so long as we don't skip
6696 anything which might clobber the registers which are being saved.
6697 We must skip more in the case where part of the prologue is in the
6698 delay slot of a non-prologue instruction). */
6701 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6704 CORE_ADDR func_addr
;
6706 /* See if we can determine the end of the prologue via the symbol table.
6707 If so, then return either PC, or the PC after the prologue, whichever
6709 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6711 CORE_ADDR post_prologue_pc
6712 = skip_prologue_using_sal (gdbarch
, func_addr
);
6713 if (post_prologue_pc
!= 0)
6714 return std::max (pc
, post_prologue_pc
);
6717 /* Can't determine prologue from the symbol table, need to examine
6720 /* Find an upper limit on the function prologue using the debug
6721 information. If the debug information could not be used to provide
6722 that bound, then use an arbitrary large number as the upper bound. */
6723 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6725 limit_pc
= pc
+ 100; /* Magic. */
6727 if (mips_pc_is_mips16 (gdbarch
, pc
))
6728 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6729 else if (mips_pc_is_micromips (gdbarch
, pc
))
6730 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6732 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6735 /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version).
6736 This is a helper function for mips_stack_frame_destroyed_p. */
6739 mips32_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6741 CORE_ADDR func_addr
= 0, func_end
= 0;
6743 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6745 /* The MIPS epilogue is max. 12 bytes long. */
6746 CORE_ADDR addr
= func_end
- 12;
6748 if (addr
< func_addr
+ 4)
6749 addr
= func_addr
+ 4;
6753 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6755 unsigned long high_word
;
6758 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6759 high_word
= (inst
>> 16) & 0xffff;
6761 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6762 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6763 && inst
!= 0x03e00008 /* jr $ra */
6764 && inst
!= 0x00000000) /* nop */
6774 /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version).
6775 This is a helper function for mips_stack_frame_destroyed_p. */
6778 micromips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6780 CORE_ADDR func_addr
= 0;
6781 CORE_ADDR func_end
= 0;
6789 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6792 /* The microMIPS epilogue is max. 12 bytes long. */
6793 addr
= func_end
- 12;
6795 if (addr
< func_addr
+ 2)
6796 addr
= func_addr
+ 2;
6800 for (; pc
< func_end
; pc
+= loc
)
6803 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6804 loc
+= MIPS_INSN16_SIZE
;
6805 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6807 /* 32-bit instructions. */
6808 case 2 * MIPS_INSN16_SIZE
:
6810 insn
|= mips_fetch_instruction (gdbarch
,
6811 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6812 loc
+= MIPS_INSN16_SIZE
;
6813 switch (micromips_op (insn
>> 16))
6815 case 0xc: /* ADDIU: bits 001100 */
6816 case 0x17: /* DADDIU: bits 010111 */
6817 sreg
= b0s5_reg (insn
>> 16);
6818 dreg
= b5s5_reg (insn
>> 16);
6819 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6820 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6821 /* (D)ADDIU $sp, imm */
6831 /* 16-bit instructions. */
6832 case MIPS_INSN16_SIZE
:
6833 switch (micromips_op (insn
))
6835 case 0x3: /* MOVE: bits 000011 */
6836 sreg
= b0s5_reg (insn
);
6837 dreg
= b5s5_reg (insn
);
6838 if (sreg
== 0 && dreg
== 0)
6839 /* MOVE $zero, $zero aka NOP */
6843 case 0x11: /* POOL16C: bits 010001 */
6844 if (b5s5_op (insn
) == 0x18
6845 /* JRADDIUSP: bits 010011 11000 */
6846 || (b5s5_op (insn
) == 0xd
6847 /* JRC: bits 010011 01101 */
6848 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6853 case 0x13: /* POOL16D: bits 010011 */
6854 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6855 if ((insn
& 0x1) == 0x1
6856 /* ADDIUSP: bits 010011 1 */
6870 /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version).
6871 This is a helper function for mips_stack_frame_destroyed_p. */
6874 mips16_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6876 CORE_ADDR func_addr
= 0, func_end
= 0;
6878 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6880 /* The MIPS epilogue is max. 12 bytes long. */
6881 CORE_ADDR addr
= func_end
- 12;
6883 if (addr
< func_addr
+ 4)
6884 addr
= func_addr
+ 4;
6888 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6890 unsigned short inst
;
6892 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6894 if ((inst
& 0xf800) == 0xf000) /* extend */
6897 if (inst
!= 0x6300 /* addiu $sp,offset */
6898 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6899 && inst
!= 0xe820 /* jr $ra */
6900 && inst
!= 0xe8a0 /* jrc $ra */
6901 && inst
!= 0x6500) /* nop */
6911 /* Implement the stack_frame_destroyed_p gdbarch method.
6913 The epilogue is defined here as the area at the end of a function,
6914 after an instruction which destroys the function's stack frame. */
6917 mips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6919 if (mips_pc_is_mips16 (gdbarch
, pc
))
6920 return mips16_stack_frame_destroyed_p (gdbarch
, pc
);
6921 else if (mips_pc_is_micromips (gdbarch
, pc
))
6922 return micromips_stack_frame_destroyed_p (gdbarch
, pc
);
6924 return mips32_stack_frame_destroyed_p (gdbarch
, pc
);
6927 /* Commands to show/set the MIPS FPU type. */
6930 show_mipsfpu_command (const char *args
, int from_tty
)
6934 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
6937 ("The MIPS floating-point coprocessor is unknown "
6938 "because the current architecture is not MIPS.\n");
6942 switch (mips_get_fpu_type (target_gdbarch ()))
6944 case MIPS_FPU_SINGLE
:
6945 fpu
= "single-precision";
6947 case MIPS_FPU_DOUBLE
:
6948 fpu
= "double-precision";
6951 fpu
= "absent (none)";
6954 internal_error (__FILE__
, __LINE__
, _("bad switch"));
6956 if (mips_fpu_type_auto
)
6957 gdb_printf ("The MIPS floating-point coprocessor "
6958 "is set automatically (currently %s)\n",
6962 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6967 set_mipsfpu_single_command (const char *args
, int from_tty
)
6969 struct gdbarch_info info
;
6970 mips_fpu_type
= MIPS_FPU_SINGLE
;
6971 mips_fpu_type_auto
= 0;
6972 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6973 instead of relying on globals. Doing that would let generic code
6974 handle the search for this specific architecture. */
6975 if (!gdbarch_update_p (info
))
6976 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6980 set_mipsfpu_double_command (const char *args
, int from_tty
)
6982 struct gdbarch_info info
;
6983 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6984 mips_fpu_type_auto
= 0;
6985 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6986 instead of relying on globals. Doing that would let generic code
6987 handle the search for this specific architecture. */
6988 if (!gdbarch_update_p (info
))
6989 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6993 set_mipsfpu_none_command (const char *args
, int from_tty
)
6995 struct gdbarch_info info
;
6996 mips_fpu_type
= MIPS_FPU_NONE
;
6997 mips_fpu_type_auto
= 0;
6998 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6999 instead of relying on globals. Doing that would let generic code
7000 handle the search for this specific architecture. */
7001 if (!gdbarch_update_p (info
))
7002 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
7006 set_mipsfpu_auto_command (const char *args
, int from_tty
)
7008 mips_fpu_type_auto
= 1;
7011 /* Just like reinit_frame_cache, but with the right arguments to be
7012 callable as an sfunc. */
7015 reinit_frame_cache_sfunc (const char *args
, int from_tty
,
7016 struct cmd_list_element
*c
)
7018 reinit_frame_cache ();
7022 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
7024 gdb_disassembler
*di
7025 = static_cast<gdb_disassembler
*>(info
->application_data
);
7026 struct gdbarch
*gdbarch
= di
->arch ();
7028 /* FIXME: cagney/2003-06-26: Is this even necessary? The
7029 disassembler needs to be able to locally determine the ISA, and
7030 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
7032 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
7033 info
->mach
= bfd_mach_mips16
;
7034 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
7035 info
->mach
= bfd_mach_mips_micromips
;
7037 /* Round down the instruction address to the appropriate boundary. */
7038 memaddr
&= (info
->mach
== bfd_mach_mips16
7039 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
7041 return default_print_insn (memaddr
, info
);
7044 /* Implement the breakpoint_kind_from_pc gdbarch method. */
7047 mips_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
7049 CORE_ADDR pc
= *pcptr
;
7051 if (mips_pc_is_mips16 (gdbarch
, pc
))
7053 *pcptr
= unmake_compact_addr (pc
);
7054 return MIPS_BP_KIND_MIPS16
;
7056 else if (mips_pc_is_micromips (gdbarch
, pc
))
7061 *pcptr
= unmake_compact_addr (pc
);
7062 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
7063 if (status
|| (mips_insn_size (ISA_MICROMIPS
, insn
) == 2))
7064 return MIPS_BP_KIND_MICROMIPS16
;
7066 return MIPS_BP_KIND_MICROMIPS32
;
7069 return MIPS_BP_KIND_MIPS32
;
7072 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7074 static const gdb_byte
*
7075 mips_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
7077 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7081 case MIPS_BP_KIND_MIPS16
:
7083 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
7084 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
7087 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7088 return mips16_big_breakpoint
;
7090 return mips16_little_breakpoint
;
7092 case MIPS_BP_KIND_MICROMIPS16
:
7094 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
7095 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
7099 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7100 return micromips16_big_breakpoint
;
7102 return micromips16_little_breakpoint
;
7104 case MIPS_BP_KIND_MICROMIPS32
:
7106 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
7107 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
7110 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7111 return micromips32_big_breakpoint
;
7113 return micromips32_little_breakpoint
;
7115 case MIPS_BP_KIND_MIPS32
:
7117 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
7118 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
7121 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7122 return big_breakpoint
;
7124 return little_breakpoint
;
7127 gdb_assert_not_reached ("unexpected mips breakpoint kind");
7131 /* Return non-zero if the standard MIPS instruction INST has a branch
7132 delay slot (i.e. it is a jump or branch instruction). This function
7133 is based on mips32_next_pc. */
7136 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, ULONGEST inst
)
7142 op
= itype_op (inst
);
7143 if ((inst
& 0xe0000000) != 0)
7145 rs
= itype_rs (inst
);
7146 rt
= itype_rt (inst
);
7147 return (is_octeon_bbit_op (op
, gdbarch
)
7148 || op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
7149 || op
== 29 /* JALX: bits 011101 */
7152 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7153 || (rs
== 9 && (rt
& 0x2) == 0)
7154 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7155 || (rs
== 10 && (rt
& 0x2) == 0))));
7156 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7159 switch (op
& 0x07) /* extract bits 28,27,26 */
7161 case 0: /* SPECIAL */
7162 op
= rtype_funct (inst
);
7163 return (op
== 8 /* JR */
7164 || op
== 9); /* JALR */
7165 break; /* end SPECIAL */
7166 case 1: /* REGIMM */
7167 rs
= itype_rs (inst
);
7168 rt
= itype_rt (inst
); /* branch condition */
7169 return ((rt
& 0xc) == 0
7170 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7171 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7172 || ((rt
& 0x1e) == 0x1c && rs
== 0));
7173 /* BPOSGE32, BPOSGE64: bits 1110x */
7174 break; /* end REGIMM */
7175 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7181 /* Return non-zero if a standard MIPS instruction at ADDR has a branch
7182 delay slot (i.e. it is a jump or branch instruction). */
7185 mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
7190 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
7194 return mips32_instruction_has_delay_slot (gdbarch
, insn
);
7197 /* Return non-zero if the microMIPS instruction INSN, comprising the
7198 16-bit major opcode word in the high 16 bits and any second word
7199 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact
7200 jump or branch instruction). The instruction must be 32-bit if
7201 MUSTBE32 is set or can be any instruction otherwise. */
7204 micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
)
7206 ULONGEST major
= insn
>> 16;
7208 switch (micromips_op (major
))
7210 /* 16-bit instructions. */
7211 case 0x33: /* B16: bits 110011 */
7212 case 0x2b: /* BNEZ16: bits 101011 */
7213 case 0x23: /* BEQZ16: bits 100011 */
7215 case 0x11: /* POOL16C: bits 010001 */
7217 && ((b5s5_op (major
) == 0xc
7218 /* JR16: bits 010001 01100 */
7219 || (b5s5_op (major
) & 0x1e) == 0xe)));
7220 /* JALR16, JALRS16: bits 010001 0111x */
7221 /* 32-bit instructions. */
7222 case 0x3d: /* JAL: bits 111101 */
7223 case 0x3c: /* JALX: bits 111100 */
7224 case 0x35: /* J: bits 110101 */
7225 case 0x2d: /* BNE: bits 101101 */
7226 case 0x25: /* BEQ: bits 100101 */
7227 case 0x1d: /* JALS: bits 011101 */
7229 case 0x10: /* POOL32I: bits 010000 */
7230 return ((b5s5_op (major
) & 0x1c) == 0x0
7231 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7232 || (b5s5_op (major
) & 0x1d) == 0x4
7233 /* BLEZ, BGTZ: bits 010000 001x0 */
7234 || (b5s5_op (major
) & 0x1d) == 0x11
7235 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7236 || ((b5s5_op (major
) & 0x1e) == 0x14
7237 && (major
& 0x3) == 0x0)
7238 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7239 || (b5s5_op (major
) & 0x1e) == 0x1a
7240 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7241 || ((b5s5_op (major
) & 0x1e) == 0x1c
7242 && (major
& 0x3) == 0x0)
7243 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7244 || ((b5s5_op (major
) & 0x1c) == 0x1c
7245 && (major
& 0x3) == 0x1));
7246 /* BC1ANY*: bits 010000 111xx xxx01 */
7247 case 0x0: /* POOL32A: bits 000000 */
7248 return (b0s6_op (insn
) == 0x3c
7249 /* POOL32Axf: bits 000000 ... 111100 */
7250 && (b6s10_ext (insn
) & 0x2bf) == 0x3c);
7251 /* JALR, JALR.HB: 000000 000x111100 111100 */
7252 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7258 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay
7259 slot (i.e. it is a non-compact jump instruction). The instruction
7260 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7263 micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7264 CORE_ADDR addr
, int mustbe32
)
7270 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7273 size
= mips_insn_size (ISA_MICROMIPS
, insn
);
7275 if (size
== 2 * MIPS_INSN16_SIZE
)
7277 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7282 return micromips_instruction_has_delay_slot (insn
, mustbe32
);
7285 /* Return non-zero if the MIPS16 instruction INST, which must be
7286 a 32-bit instruction if MUSTBE32 is set or can be any instruction
7287 otherwise, has a branch delay slot (i.e. it is a non-compact jump
7288 instruction). This function is based on mips16_next_pc. */
7291 mips16_instruction_has_delay_slot (unsigned short inst
, int mustbe32
)
7293 if ((inst
& 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */
7295 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7298 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay
7299 slot (i.e. it is a non-compact jump instruction). The instruction
7300 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7303 mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7304 CORE_ADDR addr
, int mustbe32
)
7306 unsigned short insn
;
7309 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7313 return mips16_instruction_has_delay_slot (insn
, mustbe32
);
7316 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7317 This assumes KSSEG exists. */
7320 mips_segment_boundary (CORE_ADDR bpaddr
)
7322 CORE_ADDR mask
= CORE_ADDR_MAX
;
7325 if (sizeof (CORE_ADDR
) == 8)
7326 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7327 a compiler warning produced where CORE_ADDR is a 32-bit type even
7328 though in that case this is dead code). */
7329 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7332 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7333 segsize
= 29; /* 32-bit compatibility segment */
7335 segsize
= 62; /* xkseg */
7337 case 2: /* xkphys */
7340 default: /* xksseg (1), xkuseg/kuseg (0) */
7344 else if (bpaddr
& 0x80000000) /* kernel segment */
7347 segsize
= 31; /* user segment */
7349 return bpaddr
& mask
;
7352 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7353 it backwards if necessary. Return the address of the new location. */
7356 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7358 CORE_ADDR prev_addr
;
7360 CORE_ADDR func_addr
;
7362 /* If a breakpoint is set on the instruction in a branch delay slot,
7363 GDB gets confused. When the breakpoint is hit, the PC isn't on
7364 the instruction in the branch delay slot, the PC will point to
7365 the branch instruction. Since the PC doesn't match any known
7366 breakpoints, GDB reports a trap exception.
7368 There are two possible fixes for this problem.
7370 1) When the breakpoint gets hit, see if the BD bit is set in the
7371 Cause register (which indicates the last exception occurred in a
7372 branch delay slot). If the BD bit is set, fix the PC to point to
7373 the instruction in the branch delay slot.
7375 2) When the user sets the breakpoint, don't allow him to set the
7376 breakpoint on the instruction in the branch delay slot. Instead
7377 move the breakpoint to the branch instruction (which will have
7380 The problem with the first solution is that if the user then
7381 single-steps the processor, the branch instruction will get
7382 skipped (since GDB thinks the PC is on the instruction in the
7385 So, we'll use the second solution. To do this we need to know if
7386 the instruction we're trying to set the breakpoint on is in the
7387 branch delay slot. */
7389 boundary
= mips_segment_boundary (bpaddr
);
7391 /* Make sure we don't scan back before the beginning of the current
7392 function, since we may fetch constant data or insns that look like
7393 a jump. Of course we might do that anyway if the compiler has
7394 moved constants inline. :-( */
7395 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7396 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7397 boundary
= func_addr
;
7399 if (mips_pc_is_mips (bpaddr
))
7401 if (bpaddr
== boundary
)
7404 /* If the previous instruction has a branch delay slot, we have
7405 to move the breakpoint to the branch instruction. */
7406 prev_addr
= bpaddr
- 4;
7407 if (mips32_insn_at_pc_has_delay_slot (gdbarch
, prev_addr
))
7412 int (*insn_at_pc_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7413 CORE_ADDR addr
, jmpaddr
;
7416 boundary
= unmake_compact_addr (boundary
);
7418 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7419 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7420 so try for that first, then try the 2 byte JALR/JR.
7421 The microMIPS ASE has a whole range of jumps and branches
7422 with delay slots, some of which take 4 bytes and some take
7423 2 bytes, so the idea is the same.
7424 FIXME: We have to assume that bpaddr is not the second half
7425 of an extended instruction. */
7426 insn_at_pc_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7427 ? micromips_insn_at_pc_has_delay_slot
7428 : mips16_insn_at_pc_has_delay_slot
);
7432 for (i
= 1; i
< 4; i
++)
7434 if (unmake_compact_addr (addr
) == boundary
)
7436 addr
-= MIPS_INSN16_SIZE
;
7437 if (i
== 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 0))
7438 /* Looks like a JR/JALR at [target-1], but it could be
7439 the second word of a previous JAL/JALX, so record it
7440 and check back one more. */
7442 else if (i
> 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 1))
7445 /* Looks like a JAL/JALX at [target-2], but it could also
7446 be the second word of a previous JAL/JALX, record it,
7447 and check back one more. */
7450 /* Looks like a JAL/JALX at [target-3], so any previously
7451 recorded JAL/JALX or JR/JALR must be wrong, because:
7454 -2: JAL-ext (can't be JAL/JALX)
7455 -1: bdslot (can't be JR/JALR)
7458 Of course it could be another JAL-ext which looks
7459 like a JAL, but in that case we'd have broken out
7460 of this loop at [target-2]:
7464 -2: bdslot (can't be jmp)
7471 /* Not a jump instruction: if we're at [target-1] this
7472 could be the second word of a JAL/JALX, so continue;
7473 otherwise we're done. */
7486 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7487 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7490 mips_is_stub_suffix (const char *suffix
, int zero
)
7495 return zero
&& suffix
[1] == '\0';
7497 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7502 return suffix
[1] == '\0';
7508 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7509 call stubs, one of sf, df, sc, or dc. */
7512 mips_is_stub_mode (const char *mode
)
7514 return ((mode
[0] == 's' || mode
[0] == 'd')
7515 && (mode
[1] == 'f' || mode
[1] == 'c'));
7518 /* Code at PC is a compiler-generated stub. Such a stub for a function
7519 bar might have a name like __fn_stub_bar, and might look like this:
7526 followed by (or interspersed with):
7533 addiu $25, $25, %lo(bar)
7536 ($1 may be used in old code; for robustness we accept any register)
7539 lui $28, %hi(_gp_disp)
7540 addiu $28, $28, %lo(_gp_disp)
7543 addiu $25, $25, %lo(bar)
7546 In the case of a __call_stub_bar stub, the sequence to set up
7547 arguments might look like this:
7554 followed by (or interspersed with) one of the jump sequences above.
7556 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7557 of J or JR, respectively, followed by:
7563 We are at the beginning of the stub here, and scan down and extract
7564 the target address from the jump immediate instruction or, if a jump
7565 register instruction is used, from the register referred. Return
7566 the value of PC calculated or 0 if inconclusive.
7568 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7571 mips_get_mips16_fn_stub_pc (struct frame_info
*frame
, CORE_ADDR pc
)
7573 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7574 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7575 int addrreg
= MIPS_ZERO_REGNUM
;
7576 CORE_ADDR start_pc
= pc
;
7577 CORE_ADDR target_pc
= 0;
7584 status
== 0 && target_pc
== 0 && i
< 20;
7585 i
++, pc
+= MIPS_INSN32_SIZE
)
7587 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7593 switch (itype_op (inst
))
7595 case 0: /* SPECIAL */
7596 switch (rtype_funct (inst
))
7600 rs
= rtype_rs (inst
);
7601 if (rs
== MIPS_GP_REGNUM
)
7602 target_pc
= gp
; /* Hmm... */
7603 else if (rs
== addrreg
)
7607 case 0x21: /* ADDU */
7608 rt
= rtype_rt (inst
);
7609 rs
= rtype_rs (inst
);
7610 rd
= rtype_rd (inst
);
7611 if (rd
== MIPS_GP_REGNUM
7612 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7613 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7621 target_pc
= jtype_target (inst
) << 2;
7622 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7626 rt
= itype_rt (inst
);
7627 rs
= itype_rs (inst
);
7630 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7631 if (rt
== MIPS_GP_REGNUM
)
7633 else if (rt
== addrreg
)
7639 rt
= itype_rt (inst
);
7640 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7641 if (rt
== MIPS_GP_REGNUM
)
7643 else if (rt
!= MIPS_ZERO_REGNUM
)
7651 rt
= itype_rt (inst
);
7652 rs
= itype_rs (inst
);
7653 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7654 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7658 memset (buf
, 0, sizeof (buf
));
7659 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7661 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7670 /* If PC is in a MIPS16 call or return stub, return the address of the
7671 target PC, which is either the callee or the caller. There are several
7672 cases which must be handled:
7674 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7675 and the target PC is in $31 ($ra).
7676 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7677 and the target PC is in $2.
7678 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7679 i.e. before the JALR instruction, this is effectively a call stub
7680 and the target PC is in $2. Otherwise this is effectively
7681 a return stub and the target PC is in $18.
7682 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7683 JAL or JALR instruction, this is effectively a call stub and the
7684 target PC is buried in the instruction stream. Otherwise this
7685 is effectively a return stub and the target PC is in $18.
7686 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7687 stub and the target PC is buried in the instruction stream.
7689 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7690 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7694 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7696 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7697 CORE_ADDR start_addr
;
7701 /* Find the starting address and name of the function containing the PC. */
7702 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7705 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7706 and the target PC is in $31 ($ra). */
7707 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7708 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7709 && mips_is_stub_mode (name
+ prefixlen
)
7710 && name
[prefixlen
+ 2] == '\0')
7711 return get_frame_register_signed
7712 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7714 /* If the PC is in __mips16_call_stub_*, this is one of the call
7715 call/return stubs. */
7716 prefixlen
= strlen (mips_str_mips16_call_stub
);
7717 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7719 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7720 and the target PC is in $2. */
7721 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7722 return get_frame_register_signed
7723 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7725 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7726 i.e. before the JALR instruction, this is effectively a call stub
7727 and the target PC is in $2. Otherwise this is effectively
7728 a return stub and the target PC is in $18. */
7729 else if (mips_is_stub_mode (name
+ prefixlen
)
7730 && name
[prefixlen
+ 2] == '_'
7731 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7733 if (pc
== start_addr
)
7734 /* This is the 'call' part of a call stub. The return
7735 address is in $2. */
7736 return get_frame_register_signed
7737 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7739 /* This is the 'return' part of a call stub. The return
7740 address is in $18. */
7741 return get_frame_register_signed
7742 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7745 return 0; /* Not a stub. */
7748 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7749 compiler-generated call or call/return stubs. */
7750 if (startswith (name
, mips_str_fn_stub
)
7751 || startswith (name
, mips_str_call_stub
))
7753 if (pc
== start_addr
)
7754 /* This is the 'call' part of a call stub. Call this helper
7755 to scan through this code for interesting instructions
7756 and determine the final PC. */
7757 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7759 /* This is the 'return' part of a call stub. The return address
7761 return get_frame_register_signed
7762 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7765 return 0; /* Not a stub. */
7768 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7769 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7772 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7774 CORE_ADDR start_addr
;
7777 /* Find the starting address of the function containing the PC. */
7778 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7781 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7782 the start, i.e. after the JALR instruction, this is effectively
7784 prefixlen
= strlen (mips_str_mips16_call_stub
);
7785 if (pc
!= start_addr
7786 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7787 && mips_is_stub_mode (name
+ prefixlen
)
7788 && name
[prefixlen
+ 2] == '_'
7789 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7792 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7793 the JAL or JALR instruction, this is effectively a return stub. */
7794 prefixlen
= strlen (mips_str_call_fp_stub
);
7795 if (pc
!= start_addr
7796 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7799 /* Consume the .pic. prefix of any PIC stub, this function must return
7800 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7801 or the call stub path will trigger in handle_inferior_event causing
7803 prefixlen
= strlen (mips_str_pic
);
7804 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7807 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7808 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7809 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7810 && mips_is_stub_mode (name
+ prefixlen
)
7811 && name
[prefixlen
+ 2] == '\0')
7814 return 0; /* Not a stub. */
7817 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7818 PC of the stub target. The stub just loads $t9 and jumps to it,
7819 so that $t9 has the correct value at function entry. */
7822 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7824 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7825 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7826 struct bound_minimal_symbol msym
;
7828 gdb_byte stub_code
[16];
7829 int32_t stub_words
[4];
7831 /* The stub for foo is named ".pic.foo", and is either two
7832 instructions inserted before foo or a three instruction sequence
7833 which jumps to foo. */
7834 msym
= lookup_minimal_symbol_by_pc (pc
);
7835 if (msym
.minsym
== NULL
7836 || msym
.value_address () != pc
7837 || msym
.minsym
->linkage_name () == NULL
7838 || !startswith (msym
.minsym
->linkage_name (), ".pic."))
7841 /* A two-instruction header. */
7842 if (msym
.minsym
->size () == 8)
7845 /* A three-instruction (plus delay slot) trampoline. */
7846 if (msym
.minsym
->size () == 16)
7848 if (target_read_memory (pc
, stub_code
, 16) != 0)
7850 for (i
= 0; i
< 4; i
++)
7851 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7854 /* A stub contains these instructions:
7857 addiu t9, t9, %lo(target)
7860 This works even for N64, since stubs are only generated with
7862 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7863 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7864 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7865 && stub_words
[3] == 0x00000000)
7866 return ((((stub_words
[0] & 0x0000ffff) << 16)
7867 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7870 /* Not a recognized stub. */
7875 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7877 CORE_ADDR requested_pc
= pc
;
7878 CORE_ADDR target_pc
;
7885 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7889 new_pc
= find_solib_trampoline_target (frame
, pc
);
7893 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
7897 while (pc
!= target_pc
);
7899 return pc
!= requested_pc
? pc
: 0;
7902 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7903 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7906 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7909 if (num
>= 0 && num
< 32)
7911 else if (num
>= 38 && num
< 70)
7912 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
7914 regnum
= mips_regnum (gdbarch
)->hi
;
7916 regnum
= mips_regnum (gdbarch
)->lo
;
7917 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
7918 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
7921 return gdbarch_num_regs (gdbarch
) + regnum
;
7925 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7926 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7929 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7932 if (num
>= 0 && num
< 32)
7934 else if (num
>= 32 && num
< 64)
7935 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
7937 regnum
= mips_regnum (gdbarch
)->hi
;
7939 regnum
= mips_regnum (gdbarch
)->lo
;
7940 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
7941 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
7944 return gdbarch_num_regs (gdbarch
) + regnum
;
7948 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
7950 /* Only makes sense to supply raw registers. */
7951 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
7952 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7953 decide if it is valid. Should instead define a standard sim/gdb
7954 register numbering scheme. */
7955 if (gdbarch_register_name (gdbarch
,
7956 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
7957 && gdbarch_register_name (gdbarch
,
7958 gdbarch_num_regs (gdbarch
)
7959 + regnum
)[0] != '\0')
7962 return LEGACY_SIM_REGNO_IGNORE
;
7966 /* Convert an integer into an address. Extracting the value signed
7967 guarantees a correctly sign extended address. */
7970 mips_integer_to_address (struct gdbarch
*gdbarch
,
7971 struct type
*type
, const gdb_byte
*buf
)
7973 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7974 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
7977 /* Dummy virtual frame pointer method. This is no more or less accurate
7978 than most other architectures; we just need to be explicit about it,
7979 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7980 an assertion failure. */
7983 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
7984 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
7986 *reg
= MIPS_SP_REGNUM
;
7991 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
7993 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
7994 const char *name
= bfd_section_name (sect
);
7996 if (*abip
!= MIPS_ABI_UNKNOWN
)
7999 if (!startswith (name
, ".mdebug."))
8002 if (strcmp (name
, ".mdebug.abi32") == 0)
8003 *abip
= MIPS_ABI_O32
;
8004 else if (strcmp (name
, ".mdebug.abiN32") == 0)
8005 *abip
= MIPS_ABI_N32
;
8006 else if (strcmp (name
, ".mdebug.abi64") == 0)
8007 *abip
= MIPS_ABI_N64
;
8008 else if (strcmp (name
, ".mdebug.abiO64") == 0)
8009 *abip
= MIPS_ABI_O64
;
8010 else if (strcmp (name
, ".mdebug.eabi32") == 0)
8011 *abip
= MIPS_ABI_EABI32
;
8012 else if (strcmp (name
, ".mdebug.eabi64") == 0)
8013 *abip
= MIPS_ABI_EABI64
;
8015 warning (_("unsupported ABI %s."), name
+ 8);
8019 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
8021 int *lbp
= (int *) obj
;
8022 const char *name
= bfd_section_name (sect
);
8024 if (startswith (name
, ".gcc_compiled_long32"))
8026 else if (startswith (name
, ".gcc_compiled_long64"))
8028 else if (startswith (name
, ".gcc_compiled_long"))
8029 warning (_("unrecognized .gcc_compiled_longXX"));
8032 static enum mips_abi
8033 global_mips_abi (void)
8037 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
8038 if (mips_abi_strings
[i
] == mips_abi_string
)
8039 return (enum mips_abi
) i
;
8041 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
8044 /* Return the default compressed instruction set, either of MIPS16
8045 or microMIPS, selected when none could have been determined from
8046 the ELF header of the binary being executed (or no binary has been
8049 static enum mips_isa
8050 global_mips_compression (void)
8054 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
8055 if (mips_compression_strings
[i
] == mips_compression_string
)
8056 return (enum mips_isa
) i
;
8058 internal_error (__FILE__
, __LINE__
, _("unknown compressed ISA string"));
8062 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8064 /* If the size matches the set of 32-bit or 64-bit integer registers,
8065 assume that's what we've got. */
8066 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
8067 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
8069 /* If the size matches the full set of registers GDB traditionally
8070 knows about, including floating point, for either 32-bit or
8071 64-bit, assume that's what we've got. */
8072 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
8073 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
8075 /* Otherwise we don't have a useful guess. */
8078 static struct value
*
8079 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
8081 const int *reg_p
= (const int *) baton
;
8082 return value_of_register (*reg_p
, frame
);
8085 static struct gdbarch
*
8086 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8088 struct gdbarch
*gdbarch
;
8090 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
8092 enum mips_fpu_type fpu_type
;
8093 tdesc_arch_data_up tdesc_data
;
8094 int elf_fpu_type
= Val_GNU_MIPS_ABI_FP_ANY
;
8095 const char * const *reg_names
;
8096 struct mips_regnum mips_regnum
, *regnum
;
8097 enum mips_isa mips_isa
;
8101 /* First of all, extract the elf_flags, if available. */
8102 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8103 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8104 else if (arches
!= NULL
)
8106 mips_gdbarch_tdep
*tdep
8107 = (mips_gdbarch_tdep
*) gdbarch_tdep (arches
->gdbarch
);
8108 elf_flags
= tdep
->elf_flags
;
8113 gdb_printf (gdb_stdlog
,
8114 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8116 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8117 switch ((elf_flags
& EF_MIPS_ABI
))
8119 case E_MIPS_ABI_O32
:
8120 found_abi
= MIPS_ABI_O32
;
8122 case E_MIPS_ABI_O64
:
8123 found_abi
= MIPS_ABI_O64
;
8125 case E_MIPS_ABI_EABI32
:
8126 found_abi
= MIPS_ABI_EABI32
;
8128 case E_MIPS_ABI_EABI64
:
8129 found_abi
= MIPS_ABI_EABI64
;
8132 if ((elf_flags
& EF_MIPS_ABI2
))
8133 found_abi
= MIPS_ABI_N32
;
8135 found_abi
= MIPS_ABI_UNKNOWN
;
8139 /* GCC creates a pseudo-section whose name describes the ABI. */
8140 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8141 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8143 /* If we have no useful BFD information, use the ABI from the last
8144 MIPS architecture (if there is one). */
8145 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8147 mips_gdbarch_tdep
*tdep
8148 = (mips_gdbarch_tdep
*) gdbarch_tdep (arches
->gdbarch
);
8149 found_abi
= tdep
->found_abi
;
8152 /* Try the architecture for any hint of the correct ABI. */
8153 if (found_abi
== MIPS_ABI_UNKNOWN
8154 && info
.bfd_arch_info
!= NULL
8155 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8157 switch (info
.bfd_arch_info
->mach
)
8159 case bfd_mach_mips3900
:
8160 found_abi
= MIPS_ABI_EABI32
;
8162 case bfd_mach_mips4100
:
8163 case bfd_mach_mips5000
:
8164 found_abi
= MIPS_ABI_EABI64
;
8166 case bfd_mach_mips8000
:
8167 case bfd_mach_mips10000
:
8168 /* On Irix, ELF64 executables use the N64 ABI. The
8169 pseudo-sections which describe the ABI aren't present
8170 on IRIX. (Even for executables created by gcc.) */
8171 if (info
.abfd
!= NULL
8172 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8173 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8174 found_abi
= MIPS_ABI_N64
;
8176 found_abi
= MIPS_ABI_N32
;
8181 /* Default 64-bit objects to N64 instead of O32. */
8182 if (found_abi
== MIPS_ABI_UNKNOWN
8183 && info
.abfd
!= NULL
8184 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8185 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8186 found_abi
= MIPS_ABI_N64
;
8189 gdb_printf (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8192 /* What has the user specified from the command line? */
8193 wanted_abi
= global_mips_abi ();
8195 gdb_printf (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8198 /* Now that we have found what the ABI for this binary would be,
8199 check whether the user is overriding it. */
8200 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8201 mips_abi
= wanted_abi
;
8202 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8203 mips_abi
= found_abi
;
8205 mips_abi
= MIPS_ABI_O32
;
8207 gdb_printf (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8210 /* Make sure we don't use a 32-bit architecture with a 64-bit ABI. */
8211 if (mips_abi
!= MIPS_ABI_EABI32
8212 && mips_abi
!= MIPS_ABI_O32
8213 && info
.bfd_arch_info
!= NULL
8214 && info
.bfd_arch_info
->arch
== bfd_arch_mips
8215 && info
.bfd_arch_info
->bits_per_word
< 64)
8216 info
.bfd_arch_info
= bfd_lookup_arch (bfd_arch_mips
, bfd_mach_mips4000
);
8218 /* Determine the default compressed ISA. */
8219 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8220 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8221 mips_isa
= ISA_MICROMIPS
;
8222 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8223 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8224 mips_isa
= ISA_MIPS16
;
8226 mips_isa
= global_mips_compression ();
8227 mips_compression_string
= mips_compression_strings
[mips_isa
];
8229 /* Also used when doing an architecture lookup. */
8231 gdb_printf (gdb_stdlog
,
8232 "mips_gdbarch_init: "
8233 "mips64_transfers_32bit_regs_p = %d\n",
8234 mips64_transfers_32bit_regs_p
);
8236 /* Determine the MIPS FPU type. */
8239 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8240 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8241 Tag_GNU_MIPS_ABI_FP
);
8242 #endif /* HAVE_ELF */
8244 if (!mips_fpu_type_auto
)
8245 fpu_type
= mips_fpu_type
;
8246 else if (elf_fpu_type
!= Val_GNU_MIPS_ABI_FP_ANY
)
8248 switch (elf_fpu_type
)
8250 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
8251 fpu_type
= MIPS_FPU_DOUBLE
;
8253 case Val_GNU_MIPS_ABI_FP_SINGLE
:
8254 fpu_type
= MIPS_FPU_SINGLE
;
8256 case Val_GNU_MIPS_ABI_FP_SOFT
:
8258 /* Soft float or unknown. */
8259 fpu_type
= MIPS_FPU_NONE
;
8263 else if (info
.bfd_arch_info
!= NULL
8264 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8265 switch (info
.bfd_arch_info
->mach
)
8267 case bfd_mach_mips3900
:
8268 case bfd_mach_mips4100
:
8269 case bfd_mach_mips4111
:
8270 case bfd_mach_mips4120
:
8271 fpu_type
= MIPS_FPU_NONE
;
8273 case bfd_mach_mips4650
:
8274 fpu_type
= MIPS_FPU_SINGLE
;
8277 fpu_type
= MIPS_FPU_DOUBLE
;
8280 else if (arches
!= NULL
)
8281 fpu_type
= mips_get_fpu_type (arches
->gdbarch
);
8283 fpu_type
= MIPS_FPU_DOUBLE
;
8285 gdb_printf (gdb_stdlog
,
8286 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8288 /* Check for blatant incompatibilities. */
8290 /* If we have only 32-bit registers, then we can't debug a 64-bit
8292 if (info
.target_desc
8293 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8294 && mips_abi
!= MIPS_ABI_EABI32
8295 && mips_abi
!= MIPS_ABI_O32
)
8298 /* Fill in the OS dependent register numbers and names. */
8299 if (info
.osabi
== GDB_OSABI_LINUX
)
8301 mips_regnum
.fp0
= 38;
8302 mips_regnum
.pc
= 37;
8303 mips_regnum
.cause
= 36;
8304 mips_regnum
.badvaddr
= 35;
8305 mips_regnum
.hi
= 34;
8306 mips_regnum
.lo
= 33;
8307 mips_regnum
.fp_control_status
= 70;
8308 mips_regnum
.fp_implementation_revision
= 71;
8309 mips_regnum
.dspacc
= -1;
8310 mips_regnum
.dspctl
= -1;
8314 reg_names
= mips_linux_reg_names
;
8318 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
8319 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
8320 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
8321 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
8322 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
8323 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
8324 mips_regnum
.fp_control_status
= 70;
8325 mips_regnum
.fp_implementation_revision
= 71;
8326 mips_regnum
.dspacc
= dspacc
= -1;
8327 mips_regnum
.dspctl
= dspctl
= -1;
8328 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
8329 if (info
.bfd_arch_info
!= NULL
8330 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
8331 reg_names
= mips_tx39_reg_names
;
8333 reg_names
= mips_generic_reg_names
;
8336 /* Check any target description for validity. */
8337 if (tdesc_has_registers (info
.target_desc
))
8339 static const char *const mips_gprs
[] = {
8340 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8341 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8342 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8343 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
8345 static const char *const mips_fprs
[] = {
8346 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
8347 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
8348 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
8349 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
8352 const struct tdesc_feature
*feature
;
8355 feature
= tdesc_find_feature (info
.target_desc
,
8356 "org.gnu.gdb.mips.cpu");
8357 if (feature
== NULL
)
8360 tdesc_data
= tdesc_data_alloc ();
8363 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
8364 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (), i
,
8368 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8369 mips_regnum
.lo
, "lo");
8370 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8371 mips_regnum
.hi
, "hi");
8372 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8373 mips_regnum
.pc
, "pc");
8378 feature
= tdesc_find_feature (info
.target_desc
,
8379 "org.gnu.gdb.mips.cp0");
8380 if (feature
== NULL
)
8384 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8385 mips_regnum
.badvaddr
, "badvaddr");
8386 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8387 MIPS_PS_REGNUM
, "status");
8388 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8389 mips_regnum
.cause
, "cause");
8394 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8395 backend is not prepared for that, though. */
8396 feature
= tdesc_find_feature (info
.target_desc
,
8397 "org.gnu.gdb.mips.fpu");
8398 if (feature
== NULL
)
8402 for (i
= 0; i
< 32; i
++)
8403 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8404 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
8406 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8407 mips_regnum
.fp_control_status
,
8410 &= tdesc_numbered_register (feature
, tdesc_data
.get (),
8411 mips_regnum
.fp_implementation_revision
,
8417 num_regs
= mips_regnum
.fp_implementation_revision
+ 1;
8421 feature
= tdesc_find_feature (info
.target_desc
,
8422 "org.gnu.gdb.mips.dsp");
8423 /* The DSP registers are optional; it's OK if they are absent. */
8424 if (feature
!= NULL
)
8428 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8429 dspacc
+ i
++, "hi1");
8430 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8431 dspacc
+ i
++, "lo1");
8432 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8433 dspacc
+ i
++, "hi2");
8434 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8435 dspacc
+ i
++, "lo2");
8436 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8437 dspacc
+ i
++, "hi3");
8438 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8439 dspacc
+ i
++, "lo3");
8441 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8447 mips_regnum
.dspacc
= dspacc
;
8448 mips_regnum
.dspctl
= dspctl
;
8450 num_regs
= mips_regnum
.dspctl
+ 1;
8454 /* It would be nice to detect an attempt to use a 64-bit ABI
8455 when only 32-bit registers are provided. */
8459 /* Try to find a pre-existing architecture. */
8460 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8462 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8464 mips_gdbarch_tdep
*tdep
8465 = (mips_gdbarch_tdep
*) gdbarch_tdep (arches
->gdbarch
);
8467 /* MIPS needs to be pedantic about which ABI and the compressed
8468 ISA variation the object is using. */
8469 if (tdep
->elf_flags
!= elf_flags
)
8471 if (tdep
->mips_abi
!= mips_abi
)
8473 if (tdep
->mips_isa
!= mips_isa
)
8475 /* Need to be pedantic about which register virtual size is
8477 if (tdep
->mips64_transfers_32bit_regs_p
8478 != mips64_transfers_32bit_regs_p
)
8480 /* Be pedantic about which FPU is selected. */
8481 if (mips_get_fpu_type (arches
->gdbarch
) != fpu_type
)
8484 return arches
->gdbarch
;
8487 /* Need a new architecture. Fill in a target specific vector. */
8488 mips_gdbarch_tdep
*tdep
= new mips_gdbarch_tdep
;
8489 gdbarch
= gdbarch_alloc (&info
, tdep
);
8490 tdep
->elf_flags
= elf_flags
;
8491 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8492 tdep
->found_abi
= found_abi
;
8493 tdep
->mips_abi
= mips_abi
;
8494 tdep
->mips_isa
= mips_isa
;
8495 tdep
->mips_fpu_type
= fpu_type
;
8496 tdep
->register_size_valid_p
= 0;
8497 tdep
->register_size
= 0;
8499 if (info
.target_desc
)
8501 /* Some useful properties can be inferred from the target. */
8502 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8504 tdep
->register_size_valid_p
= 1;
8505 tdep
->register_size
= 4;
8507 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8509 tdep
->register_size_valid_p
= 1;
8510 tdep
->register_size
= 8;
8514 /* Initially set everything according to the default ABI/ISA. */
8515 set_gdbarch_short_bit (gdbarch
, 16);
8516 set_gdbarch_int_bit (gdbarch
, 32);
8517 set_gdbarch_float_bit (gdbarch
, 32);
8518 set_gdbarch_double_bit (gdbarch
, 64);
8519 set_gdbarch_long_double_bit (gdbarch
, 64);
8520 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8521 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8522 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
8524 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8525 mips_ax_pseudo_register_collect
);
8526 set_gdbarch_ax_pseudo_register_push_stack
8527 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8529 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8530 mips_elf_make_msymbol_special
);
8531 set_gdbarch_make_symbol_special (gdbarch
, mips_make_symbol_special
);
8532 set_gdbarch_adjust_dwarf2_addr (gdbarch
, mips_adjust_dwarf2_addr
);
8533 set_gdbarch_adjust_dwarf2_line (gdbarch
, mips_adjust_dwarf2_line
);
8535 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8536 *regnum
= mips_regnum
;
8537 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8538 set_gdbarch_num_regs (gdbarch
, num_regs
);
8539 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8540 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8541 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8542 tdep
->mips_processor_reg_names
= reg_names
;
8543 tdep
->regnum
= regnum
;
8548 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8549 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8550 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8551 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8552 tdep
->default_mask_address_p
= 0;
8553 set_gdbarch_long_bit (gdbarch
, 32);
8554 set_gdbarch_ptr_bit (gdbarch
, 32);
8555 set_gdbarch_long_long_bit (gdbarch
, 64);
8558 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8559 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8560 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8561 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8562 tdep
->default_mask_address_p
= 0;
8563 set_gdbarch_long_bit (gdbarch
, 32);
8564 set_gdbarch_ptr_bit (gdbarch
, 32);
8565 set_gdbarch_long_long_bit (gdbarch
, 64);
8567 case MIPS_ABI_EABI32
:
8568 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8569 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8570 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8571 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8572 tdep
->default_mask_address_p
= 0;
8573 set_gdbarch_long_bit (gdbarch
, 32);
8574 set_gdbarch_ptr_bit (gdbarch
, 32);
8575 set_gdbarch_long_long_bit (gdbarch
, 64);
8577 case MIPS_ABI_EABI64
:
8578 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8579 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8580 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8581 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8582 tdep
->default_mask_address_p
= 0;
8583 set_gdbarch_long_bit (gdbarch
, 64);
8584 set_gdbarch_ptr_bit (gdbarch
, 64);
8585 set_gdbarch_long_long_bit (gdbarch
, 64);
8588 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8589 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8590 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8591 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8592 tdep
->default_mask_address_p
= 0;
8593 set_gdbarch_long_bit (gdbarch
, 32);
8594 set_gdbarch_ptr_bit (gdbarch
, 32);
8595 set_gdbarch_long_long_bit (gdbarch
, 64);
8596 set_gdbarch_long_double_bit (gdbarch
, 128);
8597 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8600 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8601 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8602 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8603 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8604 tdep
->default_mask_address_p
= 0;
8605 set_gdbarch_long_bit (gdbarch
, 64);
8606 set_gdbarch_ptr_bit (gdbarch
, 64);
8607 set_gdbarch_long_long_bit (gdbarch
, 64);
8608 set_gdbarch_long_double_bit (gdbarch
, 128);
8609 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8612 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8615 /* GCC creates a pseudo-section whose name specifies the size of
8616 longs, since -mlong32 or -mlong64 may be used independent of
8617 other options. How those options affect pointer sizes is ABI and
8618 architecture dependent, so use them to override the default sizes
8619 set by the ABI. This table shows the relationship between ABI,
8620 -mlongXX, and size of pointers:
8622 ABI -mlongXX ptr bits
8623 --- -------- --------
8637 Note that for o32 and eabi32, pointers are always 32 bits
8638 regardless of any -mlongXX option. For all others, pointers and
8639 longs are the same, as set by -mlongXX or set by defaults. */
8641 if (info
.abfd
!= NULL
)
8645 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8648 set_gdbarch_long_bit (gdbarch
, long_bit
);
8652 case MIPS_ABI_EABI32
:
8657 case MIPS_ABI_EABI64
:
8658 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8661 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8666 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8667 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8670 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8671 flag in object files because to do so would make it impossible to
8672 link with libraries compiled without "-gp32". This is
8673 unnecessarily restrictive.
8675 We could solve this problem by adding "-gp32" multilibs to gcc,
8676 but to set this flag before gcc is built with such multilibs will
8677 break too many systems.''
8679 But even more unhelpfully, the default linker output target for
8680 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8681 for 64-bit programs - you need to change the ABI to change this,
8682 and not all gcc targets support that currently. Therefore using
8683 this flag to detect 32-bit mode would do the wrong thing given
8684 the current gcc - it would make GDB treat these 64-bit programs
8685 as 32-bit programs by default. */
8687 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8688 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8690 /* Add/remove bits from an address. The MIPS needs be careful to
8691 ensure that all 32 bit addresses are sign extended to 64 bits. */
8692 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8694 /* Unwind the frame. */
8695 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8696 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8697 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8699 /* Map debug register numbers onto internal register numbers. */
8700 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8701 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8702 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8703 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8704 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8705 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8707 /* MIPS version of CALL_DUMMY. */
8709 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8710 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8711 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8713 set_gdbarch_print_float_info (gdbarch
, mips_print_float_info
);
8715 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8716 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8717 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8719 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8720 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, mips_breakpoint_kind_from_pc
);
8721 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, mips_sw_breakpoint_from_kind
);
8722 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8723 mips_adjust_breakpoint_address
);
8725 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8727 set_gdbarch_stack_frame_destroyed_p (gdbarch
, mips_stack_frame_destroyed_p
);
8729 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8730 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8731 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8733 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8735 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8737 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8738 if (mips_abi
== MIPS_ABI_N64
)
8739 set_gdbarch_disassembler_options_implicit
8740 (gdbarch
, (const char *) mips_disassembler_options_n64
);
8741 else if (mips_abi
== MIPS_ABI_N32
)
8742 set_gdbarch_disassembler_options_implicit
8743 (gdbarch
, (const char *) mips_disassembler_options_n32
);
8745 set_gdbarch_disassembler_options_implicit
8746 (gdbarch
, (const char *) mips_disassembler_options_o32
);
8747 set_gdbarch_disassembler_options (gdbarch
, &mips_disassembler_options
);
8748 set_gdbarch_valid_disassembler_options (gdbarch
,
8749 disassembler_options_mips ());
8751 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8752 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8753 need to all be folded into the target vector. Since they are
8754 being used as guards for target_stopped_by_watchpoint, why not have
8755 target_stopped_by_watchpoint return the type of watchpoint that the code
8757 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8759 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8761 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8762 to support MIPS16. This is a bad thing. Make sure not to do it
8763 if we have an OS ABI that actually supports shared libraries, since
8764 shared library support is more important. If we have an OS someday
8765 that supports both shared libraries and MIPS16, we'll have to find
8766 a better place for these.
8767 macro/2012-04-25: But that applies to return trampolines only and
8768 currently no MIPS OS ABI uses shared libraries that have them. */
8769 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8771 set_gdbarch_single_step_through_delay (gdbarch
,
8772 mips_single_step_through_delay
);
8774 /* Virtual tables. */
8775 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8777 mips_register_g_packet_guesses (gdbarch
);
8779 /* Hook in OS ABI-specific overrides, if they have been registered. */
8780 info
.tdesc_data
= tdesc_data
.get ();
8781 gdbarch_init_osabi (info
, gdbarch
);
8783 /* The hook may have adjusted num_regs, fetch the final value and
8784 set pc_regnum and sp_regnum now that it has been fixed. */
8785 num_regs
= gdbarch_num_regs (gdbarch
);
8786 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8787 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8789 /* Unwind the frame. */
8790 dwarf2_append_unwinders (gdbarch
);
8791 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8792 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8793 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8794 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8795 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8796 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8797 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8798 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8799 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8801 if (tdesc_data
!= nullptr)
8803 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8804 tdesc_use_registers (gdbarch
, info
.target_desc
, std::move (tdesc_data
));
8806 /* Override the normal target description methods to handle our
8807 dual real and pseudo registers. */
8808 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8809 set_gdbarch_register_reggroup_p (gdbarch
,
8810 mips_tdesc_register_reggroup_p
);
8812 num_regs
= gdbarch_num_regs (gdbarch
);
8813 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8814 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8815 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8818 /* Add ABI-specific aliases for the registers. */
8819 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8820 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8821 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8822 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8824 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8825 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8826 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8828 /* Add some other standard aliases. */
8829 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8830 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8831 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8833 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8834 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8835 value_of_mips_user_reg
,
8836 &mips_numeric_register_aliases
[i
].regnum
);
8842 mips_abi_update (const char *ignore_args
,
8843 int from_tty
, struct cmd_list_element
*c
)
8845 struct gdbarch_info info
;
8847 /* Force the architecture to update, and (if it's a MIPS architecture)
8848 mips_gdbarch_init will take care of the rest. */
8849 gdbarch_update_p (info
);
8852 /* Print out which MIPS ABI is in use. */
8855 show_mips_abi (struct ui_file
*file
,
8857 struct cmd_list_element
*ignored_cmd
,
8858 const char *ignored_value
)
8860 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
8863 "The MIPS ABI is unknown because the current architecture "
8867 enum mips_abi global_abi
= global_mips_abi ();
8868 enum mips_abi actual_abi
= mips_abi (target_gdbarch ());
8869 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8871 if (global_abi
== MIPS_ABI_UNKNOWN
)
8874 "The MIPS ABI is set automatically (currently \"%s\").\n",
8876 else if (global_abi
== actual_abi
)
8879 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8883 /* Probably shouldn't happen... */
8885 "The (auto detected) MIPS ABI \"%s\" is in use "
8886 "even though the user setting was \"%s\".\n",
8887 actual_abi_str
, mips_abi_strings
[global_abi
]);
8892 /* Print out which MIPS compressed ISA encoding is used. */
8895 show_mips_compression (struct ui_file
*file
, int from_tty
,
8896 struct cmd_list_element
*c
, const char *value
)
8898 gdb_printf (file
, _("The compressed ISA encoding used is %s.\n"),
8902 /* Return a textual name for MIPS FPU type FPU_TYPE. */
8905 mips_fpu_type_str (enum mips_fpu_type fpu_type
)
8911 case MIPS_FPU_SINGLE
:
8913 case MIPS_FPU_DOUBLE
:
8921 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8923 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
8927 int ef_mips_32bitmode
;
8928 /* Determine the ISA. */
8929 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
8947 /* Determine the size of a pointer. */
8948 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
8950 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8953 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8956 "mips_dump_tdep: ef_mips_arch = %d\n",
8959 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8960 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
8963 "mips_mask_address_p() %d (default %d)\n",
8964 mips_mask_address_p (tdep
),
8965 tdep
->default_mask_address_p
);
8968 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8969 MIPS_DEFAULT_FPU_TYPE
,
8970 mips_fpu_type_str (MIPS_DEFAULT_FPU_TYPE
));
8971 gdb_printf (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
8972 mips_eabi (gdbarch
));
8974 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8975 mips_get_fpu_type (gdbarch
),
8976 mips_fpu_type_str (mips_get_fpu_type (gdbarch
)));
8979 void _initialize_mips_tdep ();
8981 _initialize_mips_tdep ()
8983 static struct cmd_list_element
*mipsfpulist
= NULL
;
8985 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
8986 if (MIPS_ABI_LAST
+ 1
8987 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
8988 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
8990 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
8992 /* Create feature sets with the appropriate properties. The values
8993 are not important. */
8994 mips_tdesc_gp32
= allocate_target_description ().release ();
8995 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
8997 mips_tdesc_gp64
= allocate_target_description ().release ();
8998 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
9000 /* Add root prefix command for all "set mips"/"show mips" commands. */
9001 add_setshow_prefix_cmd ("mips", no_class
,
9002 _("Various MIPS specific commands."),
9003 _("Various MIPS specific commands."),
9004 &setmipscmdlist
, &showmipscmdlist
,
9005 &setlist
, &showlist
);
9007 /* Allow the user to override the ABI. */
9008 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
9009 &mips_abi_string
, _("\
9010 Set the MIPS ABI used by this program."), _("\
9011 Show the MIPS ABI used by this program."), _("\
9012 This option can be set to one of:\n\
9013 auto - the default ABI associated with the current binary\n\
9022 &setmipscmdlist
, &showmipscmdlist
);
9024 /* Allow the user to set the ISA to assume for compressed code if ELF
9025 file flags don't tell or there is no program file selected. This
9026 setting is updated whenever unambiguous ELF file flags are interpreted,
9027 and carried over to subsequent sessions. */
9028 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
9029 &mips_compression_string
, _("\
9030 Set the compressed ISA encoding used by MIPS code."), _("\
9031 Show the compressed ISA encoding used by MIPS code."), _("\
9032 Select the compressed ISA encoding used in functions that have no symbol\n\
9033 information available. The encoding can be set to either of:\n\
9036 and is updated automatically from ELF file flags if available."),
9038 show_mips_compression
,
9039 &setmipscmdlist
, &showmipscmdlist
);
9041 /* Let the user turn off floating point and set the fence post for
9042 heuristic_proc_start. */
9044 add_basic_prefix_cmd ("mipsfpu", class_support
,
9045 _("Set use of MIPS floating-point coprocessor."),
9046 &mipsfpulist
, 0, &setlist
);
9047 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
9048 _("Select single-precision MIPS floating-point coprocessor."),
9050 cmd_list_element
*set_mipsfpu_double_cmd
9051 = add_cmd ("double", class_support
, set_mipsfpu_double_command
,
9052 _("Select double-precision MIPS floating-point coprocessor."),
9054 add_alias_cmd ("on", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
9055 add_alias_cmd ("yes", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
9056 add_alias_cmd ("1", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
9058 cmd_list_element
*set_mipsfpu_none_cmd
9059 = add_cmd ("none", class_support
, set_mipsfpu_none_command
,
9060 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
9061 add_alias_cmd ("off", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9062 add_alias_cmd ("no", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9063 add_alias_cmd ("0", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9064 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
9065 _("Select MIPS floating-point coprocessor automatically."),
9067 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
9068 _("Show current use of MIPS floating-point coprocessor target."),
9071 /* We really would like to have both "0" and "unlimited" work, but
9072 command.c doesn't deal with that. So make it a var_zinteger
9073 because the user can always use "999999" or some such for unlimited. */
9074 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
9075 &heuristic_fence_post
, _("\
9076 Set the distance searched for the start of a function."), _("\
9077 Show the distance searched for the start of a function."), _("\
9078 If you are debugging a stripped executable, GDB needs to search through the\n\
9079 program for the start of a function. This command sets the distance of the\n\
9080 search. The only need to set it is when debugging a stripped executable."),
9081 reinit_frame_cache_sfunc
,
9082 NULL
, /* FIXME: i18n: The distance searched for
9083 the start of a function is %s. */
9084 &setlist
, &showlist
);
9086 /* Allow the user to control whether the upper bits of 64-bit
9087 addresses should be zeroed. */
9088 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
9089 &mask_address_var
, _("\
9090 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
9091 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
9092 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
9093 allow GDB to determine the correct value."),
9094 NULL
, show_mask_address
,
9095 &setmipscmdlist
, &showmipscmdlist
);
9097 /* Allow the user to control the size of 32 bit registers within the
9098 raw remote packet. */
9099 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
9100 &mips64_transfers_32bit_regs_p
, _("\
9101 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9103 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9105 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
9106 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
9107 64 bits for others. Use \"off\" to disable compatibility mode"),
9108 set_mips64_transfers_32bit_regs
,
9109 NULL
, /* FIXME: i18n: Compatibility with 64-bit
9110 MIPS target that transfers 32-bit
9111 quantities is %s. */
9112 &setlist
, &showlist
);
9114 /* Debug this files internals. */
9115 add_setshow_zuinteger_cmd ("mips", class_maintenance
,
9117 Set mips debugging."), _("\
9118 Show mips debugging."), _("\
9119 When non-zero, mips specific debugging is enabled."),
9121 NULL
, /* FIXME: i18n: Mips debugging is
9123 &setdebuglist
, &showdebuglist
);