ld/testsuite/ld-spu/ovl.d

   1 #source: ovl.s
   2 #ld: -N -T ovl.lnk --emit-relocs
   3 #objdump: -D -r
   4
   5 .*elf32-spu
   6
   7 Disassembly of section \.text:
   8
   9 00000100 <_start>:
  10  100:   1c f8 00 81     ai      \$1,\$1,-32
  11  104:   48 20 00 00     xor     \$0,\$0,\$0
  12  108:   24 00 00 80     stqd    \$0,0\(\$1\)
  13  10c:   24 00 40 80     stqd    \$0,16\(\$1\)
  14  110:   33 00 04 00     brsl    \$0,130 <00000000\.ovl_call\.f1_a1>     # 130
  15                         110: SPU_REL16  f1_a1
  16  114:   33 00 04 80     brsl    \$0,138 <00000000\.ovl_call\.f2_a1>     # 138
  17                         114: SPU_REL16  f2_a1
  18  118:   33 00 07 00     brsl    \$0,150 <00000000\.ovl_call\.f1_a2>     # 150
  19                         118: SPU_REL16  f1_a2
  20  11c:   42 00 ac 09     ila     \$9,344 # 158
  21                         11c: SPU_ADDR18 f2_a2
  22  120:   35 20 04 80     bisl    \$0,\$9
  23  124:   1c 08 00 81     ai      \$1,\$1,32      # 20
  24  128:   32 7f fb 00     br      100 <_start>    # 100
  25                         128: SPU_REL16  _start
  26
  27 0000012c <f0>:
  28  12c:   35 00 00 00     bi      \$0
  29
  30 00000130 <00000000\.ovl_call\.f1_a1>:
  31  130:   42 02 00 4f     ila     \$79,1024       # 400
  32  134:   32 00 02 80     br      148 .*
  33                         134: SPU_REL16  \*ABS\*\+0x148
  34
  35 00000138 <00000000\.ovl_call\.f2_a1>:
  36  138:   42 02 02 4f     ila     \$79,1028       # 404
  37  13c:   32 00 01 80     br      148 .*
  38                         13c: SPU_REL16  \*ABS\*\+0x148
  39
  40 00000140 <00000000\.ovl_call\.f4_a1>:
  41  140:   42 02 08 4f     ila     \$79,1040       # 410
  42  144:   40 20 00 00     nop     \$0
  43  148:   42 00 00 ce     ila     \$78,1
  44  14c:   32 00 0a 80     br      1a0 <__ovly_load>       # 1a0
  45                         14c: SPU_REL16  __ovly_load
  46
  47 00000150 <00000000\.ovl_call\.f1_a2>:
  48  150:   42 02 00 4f     ila     \$79,1024       # 400
  49  154:   32 00 02 80     br      168 .*
  50                         154: SPU_REL16  \*ABS\*\+0x168
  51
  52 00000158 <00000000\.ovl_call\.f2_a2>:
  53  158:   42 02 12 4f     ila     \$79,1060       # 424
  54  15c:   32 00 01 80     br      168 .*
  55                         15c: SPU_REL16  \*ABS\*\+0x168
  56
  57 00000160 <00000000\.ovl_call\.14:8>:
  58  160:   42 02 1a 4f     ila     \$79,1076       # 434
  59  164:   40 20 00 00     nop     \$0
  60  168:   42 00 01 4e     ila     \$78,2
  61  16c:   32 00 06 80     br      1a0 <__ovly_load>       # 1a0
  62                         16c: SPU_REL16  __ovly_load
  63 #...
  64 [0-9a-f]+ <__ovly_return>:
  65 [0-9a-f ]+:     3f e1 00 4e     shlqbyi \$78,\$0,4
  66 [0-9a-f ]+:     3f e2 00 4f     shlqbyi \$79,\$0,8
  67 [0-9a-f ]+:     25 00 27 ce     biz     \$78,\$79
  68
  69 [0-9a-f]+ <__ovly_load>:
  70 #...
  71 [0-9a-f]+ <_ovly_debug_event>:
  72 #...
  73 Disassembly of section \.ov_a1:
  74
  75 00000400 <f1_a1>:
  76  400:   32 00 01 80     br      40c <f3_a1>     # 40c
  77                         400: SPU_REL16  f3_a1
  78
  79 00000404 <f2_a1>:
  80  404:   42 00 a0 03     ila     \$3,320 # 140
  81                         404: SPU_ADDR18 f4_a1
  82  408:   35 00 00 00     bi      \$0
  83
  84 0000040c <f3_a1>:
  85  40c:   35 00 00 00     bi      \$0
  86
  87 00000410 <f4_a1>:
  88  410:   35 00 00 00     bi      \$0
  89         \.\.\.
  90 Disassembly of section \.ov_a2:
  91
  92 00000400 <f1_a2>:
  93  400:   24 00 40 80     stqd    \$0,16\(\$1\)
  94  404:   24 ff 80 81     stqd    \$1,-32\(\$1\)
  95  408:   1c f8 00 81     ai      \$1,\$1,-32
  96  40c:   33 7f a4 00     brsl    \$0,12c <f0>    # 12c
  97                         40c: SPU_REL16  f0
  98  410:   33 7f a4 00     brsl    \$0,130 <00000000\.ovl_call\.f1_a1>     # 130
  99                         410: SPU_REL16  f1_a1
 100  414:   33 00 03 80     brsl    \$0,430 <f3_a2> # 430
 101                         414: SPU_REL16  f3_a2
 102  418:   34 00 c0 80     lqd     \$0,48\(\$1\)   # 30
 103  41c:   1c 08 00 81     ai      \$1,\$1,32      # 20
 104  420:   35 00 00 00     bi      \$0
 105
 106 00000424 <f2_a2>:
 107  424:   41 00 00 03     ilhu    \$3,0
 108                         424: SPU_ADDR16_HI      f4_a2
 109  428:   60 80 b0 03     iohl    \$3,352 # 160
 110                         428: SPU_ADDR16_LO      f4_a2
 111  42c:   35 00 00 00     bi      \$0
 112
 113 00000430 <f3_a2>:
 114  430:   35 00 00 00     bi      \$0
 115
 116 00000434 <f4_a2>:
 117  434:   32 7f ff 80     br      430 <f3_a2>     # 430
 118                         434: SPU_REL16  f3_a2
 119         \.\.\.
 120 Disassembly of section .data:
 121
 122 00000440 <_ovly_table>:
 123  440:   00 00 04 00 .*
 124  444:   00 00 00 20 .*
 125  448:   00 00 02 f0 .*
 126  44c:   00 00 00 01 .*
 127  450:   00 00 04 00 .*
 128  454:   00 00 00 40 .*
 129  458:   00 00 03 10 .*
 130  45c:   00 00 00 01 .*
 131
 132 00000460 <_ovly_buf_table>:
 133  460:   00 00 00 00 .*
 134 Disassembly of section \.toe:
 135
 136 00000470 <_EAR_>:
 137         \.\.\.
 138 Disassembly of section \.note\.spu_name:
 139
 140 .* <\.note\.spu_name>:
 141 .*:     00 00 00 08 .*
 142 .*:     00 00 00 0c .*
 143 .*:     00 00 00 01 .*
 144 .*:     53 50 55 4e .*
 145 .*:     41 4d 45 00 .*
 146 .*:     74 6d 70 64 .*
 147 .*:     69 72 2f 64 .*
 148 .*:     75 6d 70 00 .*