include/opcode/mips.h

   1 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
   2    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
   3    2003, 2004, 2005
   4    Free Software Foundation, Inc.
   5    Contributed by Ralph Campbell and OSF
   6    Commented and modified by Ian Lance Taylor, Cygnus Support
   7
   8 This file is part of GDB, GAS, and the GNU binutils.
   9
  10 GDB, GAS, and the GNU binutils are free software; you can redistribute
  11 them and/or modify them under the terms of the GNU General Public
  12 License as published by the Free Software Foundation; either version
  13 1, or (at your option) any later version.
  14
  15 GDB, GAS, and the GNU binutils are distributed in the hope that they
  16 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  17 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  18 the GNU General Public License for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with this file; see the file COPYING.  If not, write to the Free
  22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
  23
  24 #ifndef _MIPS_H_
  25 #define _MIPS_H_
  26
  27 /* These are bit masks and shift counts to use to access the various
  28    fields of an instruction.  To retrieve the X field of an
  29    instruction, use the expression
  30         (i >> OP_SH_X) & OP_MASK_X
  31    To set the same field (to j), use
  32         i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
  33
  34    Make sure you use fields that are appropriate for the instruction,
  35    of course.
  36
  37    The 'i' format uses OP, RS, RT and IMMEDIATE.
  38
  39    The 'j' format uses OP and TARGET.
  40
  41    The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
  42
  43    The 'b' format uses OP, RS, RT and DELTA.
  44
  45    The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
  46
  47    The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
  48
  49    A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
  50    breakpoint instruction are not defined; Kane says the breakpoint
  51    code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
  52    only use ten bits).  An optional two-operand form of break/sdbbp
  53    allows the lower ten bits to be set too, and MIPS32 and later
  54    architectures allow 20 bits to be set with a signal operand
  55    (using CODE20).
  56
  57    The syscall instruction uses CODE20.
  58
  59    The general coprocessor instructions use COPZ.  */
  60
  61 #define OP_MASK_OP              0x3f
  62 #define OP_SH_OP                26
  63 #define OP_MASK_RS              0x1f
  64 #define OP_SH_RS                21
  65 #define OP_MASK_FR              0x1f
  66 #define OP_SH_FR                21
  67 #define OP_MASK_FMT             0x1f
  68 #define OP_SH_FMT               21
  69 #define OP_MASK_BCC             0x7
  70 #define OP_SH_BCC               18
  71 #define OP_MASK_CODE            0x3ff
  72 #define OP_SH_CODE              16
  73 #define OP_MASK_CODE2           0x3ff
  74 #define OP_SH_CODE2             6
  75 #define OP_MASK_RT              0x1f
  76 #define OP_SH_RT                16
  77 #define OP_MASK_FT              0x1f
  78 #define OP_SH_FT                16
  79 #define OP_MASK_CACHE           0x1f
  80 #define OP_SH_CACHE             16
  81 #define OP_MASK_RD              0x1f
  82 #define OP_SH_RD                11
  83 #define OP_MASK_FS              0x1f
  84 #define OP_SH_FS                11
  85 #define OP_MASK_PREFX           0x1f
  86 #define OP_SH_PREFX             11
  87 #define OP_MASK_CCC             0x7
  88 #define OP_SH_CCC               8
  89 #define OP_MASK_CODE20          0xfffff /* 20 bit syscall/breakpoint code.  */
  90 #define OP_SH_CODE20            6
  91 #define OP_MASK_SHAMT           0x1f
  92 #define OP_SH_SHAMT             6
  93 #define OP_MASK_FD              0x1f
  94 #define OP_SH_FD                6
  95 #define OP_MASK_TARGET          0x3ffffff
  96 #define OP_SH_TARGET            0
  97 #define OP_MASK_COPZ            0x1ffffff
  98 #define OP_SH_COPZ              0
  99 #define OP_MASK_IMMEDIATE       0xffff
 100 #define OP_SH_IMMEDIATE         0
 101 #define OP_MASK_DELTA           0xffff
 102 #define OP_SH_DELTA             0
 103 #define OP_MASK_FUNCT           0x3f
 104 #define OP_SH_FUNCT             0
 105 #define OP_MASK_SPEC            0x3f
 106 #define OP_SH_SPEC              0
 107 #define OP_SH_LOCC              8       /* FP condition code.  */
 108 #define OP_SH_HICC              18      /* FP condition code.  */
 109 #define OP_MASK_CC              0x7
 110 #define OP_SH_COP1NORM          25      /* Normal COP1 encoding.  */
 111 #define OP_MASK_COP1NORM        0x1     /* a single bit.  */
 112 #define OP_SH_COP1SPEC          21      /* COP1 encodings.  */
 113 #define OP_MASK_COP1SPEC        0xf
 114 #define OP_MASK_COP1SCLR        0x4
 115 #define OP_MASK_COP1CMP         0x3
 116 #define OP_SH_COP1CMP           4
 117 #define OP_SH_FORMAT            21      /* FP short format field.  */
 118 #define OP_MASK_FORMAT          0x7
 119 #define OP_SH_TRUE              16
 120 #define OP_MASK_TRUE            0x1
 121 #define OP_SH_GE                17
 122 #define OP_MASK_GE              0x01
 123 #define OP_SH_UNSIGNED          16
 124 #define OP_MASK_UNSIGNED        0x1
 125 #define OP_SH_HINT              16
 126 #define OP_MASK_HINT            0x1f
 127 #define OP_SH_MMI               0       /* Multimedia (parallel) op.  */
 128 #define OP_MASK_MMI             0x3f
 129 #define OP_SH_MMISUB            6
 130 #define OP_MASK_MMISUB          0x1f
 131 #define OP_MASK_PERFREG         0x1f    /* Performance monitoring.  */
 132 #define OP_SH_PERFREG           1
 133 #define OP_SH_SEL               0       /* Coprocessor select field.  */
 134 #define OP_MASK_SEL             0x7     /* The sel field of mfcZ and mtcZ.  */
 135 #define OP_SH_CODE19            6       /* 19 bit wait code.  */
 136 #define OP_MASK_CODE19          0x7ffff
 137 #define OP_SH_ALN               21
 138 #define OP_MASK_ALN             0x7
 139 #define OP_SH_VSEL              21
 140 #define OP_MASK_VSEL            0x1f
 141 #define OP_MASK_VECBYTE         0x7     /* Selector field is really 4 bits,
 142                                            but 0x8-0xf don't select bytes.  */
 143 #define OP_SH_VECBYTE           22
 144 #define OP_MASK_VECALIGN        0x7     /* Vector byte-align (alni.ob) op.  */
 145 #define OP_SH_VECALIGN          21
 146 #define OP_MASK_INSMSB          0x1f    /* "ins" MSB.  */
 147 #define OP_SH_INSMSB            11
 148 #define OP_MASK_EXTMSBD         0x1f    /* "ext" MSBD.  */
 149 #define OP_SH_EXTMSBD           11
 150
 151 #define OP_OP_COP0              0x10
 152 #define OP_OP_COP1              0x11
 153 #define OP_OP_COP2              0x12
 154 #define OP_OP_COP3              0x13
 155 #define OP_OP_LWC1              0x31
 156 #define OP_OP_LWC2              0x32
 157 #define OP_OP_LWC3              0x33    /* a.k.a. pref */
 158 #define OP_OP_LDC1              0x35
 159 #define OP_OP_LDC2              0x36
 160 #define OP_OP_LDC3              0x37    /* a.k.a. ld */
 161 #define OP_OP_SWC1              0x39
 162 #define OP_OP_SWC2              0x3a
 163 #define OP_OP_SWC3              0x3b
 164 #define OP_OP_SDC1              0x3d
 165 #define OP_OP_SDC2              0x3e
 166 #define OP_OP_SDC3              0x3f    /* a.k.a. sd */
 167
 168 /* Values in the 'VSEL' field.  */
 169 #define MDMX_FMTSEL_IMM_QH      0x1d
 170 #define MDMX_FMTSEL_IMM_OB      0x1e
 171 #define MDMX_FMTSEL_VEC_QH      0x15
 172 #define MDMX_FMTSEL_VEC_OB      0x16
 173
 174 /* This structure holds information for a particular instruction.  */
 175
 176 struct mips_opcode
 177 {
 178   /* The name of the instruction.  */
 179   const char *name;
 180   /* A string describing the arguments for this instruction.  */
 181   const char *args;
 182   /* The basic opcode for the instruction.  When assembling, this
 183      opcode is modified by the arguments to produce the actual opcode
 184      that is used.  If pinfo is INSN_MACRO, then this is 0.  */
 185   unsigned long match;
 186   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
 187      relevant portions of the opcode when disassembling.  If the
 188      actual opcode anded with the match field equals the opcode field,
 189      then we have found the correct instruction.  If pinfo is
 190      INSN_MACRO, then this field is the macro identifier.  */
 191   unsigned long mask;
 192   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 193      of bits describing the instruction, notably any relevant hazard
 194      information.  */
 195   unsigned long pinfo;
 196   /* A collection of additional bits describing the instruction. */
 197   unsigned long pinfo2;
 198   /* A collection of bits describing the instruction sets of which this
 199      instruction or macro is a member. */
 200   unsigned long membership;
 201 };
 202
 203 /* These are the characters which may appear in the args field of an
 204    instruction.  They appear in the order in which the fields appear
 205    when the instruction is used.  Commas and parentheses in the args
 206    string are ignored when assembling, and written into the output
 207    when disassembling.
 208
 209    Each of these characters corresponds to a mask field defined above.
 210
 211    "<" 5 bit shift amount (OP_*_SHAMT)
 212    ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
 213    "a" 26 bit target address (OP_*_TARGET)
 214    "b" 5 bit base register (OP_*_RS)
 215    "c" 10 bit breakpoint code (OP_*_CODE)
 216    "d" 5 bit destination register specifier (OP_*_RD)
 217    "h" 5 bit prefx hint (OP_*_PREFX)
 218    "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
 219    "j" 16 bit signed immediate (OP_*_DELTA)
 220    "k" 5 bit cache opcode in target register position (OP_*_CACHE)
 221        Also used for immediate operands in vr5400 vector insns.
 222    "o" 16 bit signed offset (OP_*_DELTA)
 223    "p" 16 bit PC relative branch target address (OP_*_DELTA)
 224    "q" 10 bit extra breakpoint code (OP_*_CODE2)
 225    "r" 5 bit same register used as both source and target (OP_*_RS)
 226    "s" 5 bit source register specifier (OP_*_RS)
 227    "t" 5 bit target register (OP_*_RT)
 228    "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
 229    "v" 5 bit same register used as both source and destination (OP_*_RS)
 230    "w" 5 bit same register used as both target and destination (OP_*_RT)
 231    "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
 232        (used by clo and clz)
 233    "C" 25 bit coprocessor function code (OP_*_COPZ)
 234    "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
 235    "J" 19 bit wait function code (OP_*_CODE19)
 236    "x" accept and ignore register name
 237    "z" must be zero register
 238    "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
 239    "+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT).
 240         Enforces: 0 <= pos < 32.
 241    "+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB).
 242         Requires that "+A" or "+E" occur first to set position.
 243         Enforces: 0 < (pos+size) <= 32.
 244    "+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD).
 245         Requires that "+A" or "+E" occur first to set position.
 246         Enforces: 0 < (pos+size) <= 32.
 247         (Also used by "dext" w/ different limits, but limits for
 248         that are checked by the M_DEXT macro.)
 249    "+E" 5 bit dins/dext position, which becomes LSB-32 (OP_*_SHAMT).
 250         Enforces: 32 <= pos < 64.
 251    "+F" 5 bit "dinsm" size, which becomes MSB-32 (OP_*_INSMSB).
 252         Requires that "+A" or "+E" occur first to set position.
 253         Enforces: 32 < (pos+size) <= 64.
 254    "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
 255         Requires that "+A" or "+E" occur first to set position.
 256         Enforces: 32 < (pos+size) <= 64.
 257    "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
 258         Requires that "+A" or "+E" occur first to set position.
 259         Enforces: 32 < (pos+size) <= 64.
 260
 261    Floating point instructions:
 262    "D" 5 bit destination register (OP_*_FD)
 263    "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
 264    "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
 265    "S" 5 bit fs source 1 register (OP_*_FS)
 266    "T" 5 bit ft source 2 register (OP_*_FT)
 267    "R" 5 bit fr source 3 register (OP_*_FR)
 268    "V" 5 bit same register used as floating source and destination (OP_*_FS)
 269    "W" 5 bit same register used as floating target and destination (OP_*_FT)
 270
 271    Coprocessor instructions:
 272    "E" 5 bit target register (OP_*_RT)
 273    "G" 5 bit destination register (OP_*_RD)
 274    "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
 275    "P" 5 bit performance-monitor register (OP_*_PERFREG)
 276    "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
 277    "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
 278    see also "k" above
 279    "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
 280         for pretty-printing in disassembly only.
 281
 282    Macro instructions:
 283    "A" General 32 bit expression
 284    "I" 32 bit immediate (value placed in imm_expr).
 285    "+I" 32 bit immediate (value placed in imm2_expr).
 286    "F" 64 bit floating point constant in .rdata
 287    "L" 64 bit floating point constant in .lit8
 288    "f" 32 bit floating point constant
 289    "l" 32 bit floating point constant in .lit4
 290
 291    MDMX instruction operands (note that while these use the FP register
 292    fields, they accept both $fN and $vN names for the registers):
 293    "O"  MDMX alignment offset (OP_*_ALN)
 294    "Q"  MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
 295    "X"  MDMX destination register (OP_*_FD)
 296    "Y"  MDMX source register (OP_*_FS)
 297    "Z"  MDMX source register (OP_*_FT)
 298
 299    Other:
 300    "()" parens surrounding optional value
 301    ","  separates operands
 302    "[]" brackets around index for vector-op scalar operand specifier (vr5400)
 303    "+"  Start of extension sequence.
 304
 305    Characters used so far, for quick reference when adding more:
 306    "%[]<>(),+"
 307    "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
 308    "abcdefhijklopqrstuvwxz"
 309
 310    Extension character sequences used so far ("+" followed by the
 311    following), for quick reference when adding more:
 312    "ABCDEFGHI"
 313 */
 314
 315 /* These are the bits which may be set in the pinfo field of an
 316    instructions, if it is not equal to INSN_MACRO.  */
 317
 318 /* Modifies the general purpose register in OP_*_RD.  */
 319 #define INSN_WRITE_GPR_D            0x00000001
 320 /* Modifies the general purpose register in OP_*_RT.  */
 321 #define INSN_WRITE_GPR_T            0x00000002
 322 /* Modifies general purpose register 31.  */
 323 #define INSN_WRITE_GPR_31           0x00000004
 324 /* Modifies the floating point register in OP_*_FD.  */
 325 #define INSN_WRITE_FPR_D            0x00000008
 326 /* Modifies the floating point register in OP_*_FS.  */
 327 #define INSN_WRITE_FPR_S            0x00000010
 328 /* Modifies the floating point register in OP_*_FT.  */
 329 #define INSN_WRITE_FPR_T            0x00000020
 330 /* Reads the general purpose register in OP_*_RS.  */
 331 #define INSN_READ_GPR_S             0x00000040
 332 /* Reads the general purpose register in OP_*_RT.  */
 333 #define INSN_READ_GPR_T             0x00000080
 334 /* Reads the floating point register in OP_*_FS.  */
 335 #define INSN_READ_FPR_S             0x00000100
 336 /* Reads the floating point register in OP_*_FT.  */
 337 #define INSN_READ_FPR_T             0x00000200
 338 /* Reads the floating point register in OP_*_FR.  */
 339 #define INSN_READ_FPR_R             0x00000400
 340 /* Modifies coprocessor condition code.  */
 341 #define INSN_WRITE_COND_CODE        0x00000800
 342 /* Reads coprocessor condition code.  */
 343 #define INSN_READ_COND_CODE         0x00001000
 344 /* TLB operation.  */
 345 #define INSN_TLB                    0x00002000
 346 /* Reads coprocessor register other than floating point register.  */
 347 #define INSN_COP                    0x00004000
 348 /* Instruction loads value from memory, requiring delay.  */
 349 #define INSN_LOAD_MEMORY_DELAY      0x00008000
 350 /* Instruction loads value from coprocessor, requiring delay.  */
 351 #define INSN_LOAD_COPROC_DELAY      0x00010000
 352 /* Instruction has unconditional branch delay slot.  */
 353 #define INSN_UNCOND_BRANCH_DELAY    0x00020000
 354 /* Instruction has conditional branch delay slot.  */
 355 #define INSN_COND_BRANCH_DELAY      0x00040000
 356 /* Conditional branch likely: if branch not taken, insn nullified.  */
 357 #define INSN_COND_BRANCH_LIKELY     0x00080000
 358 /* Moves to coprocessor register, requiring delay.  */
 359 #define INSN_COPROC_MOVE_DELAY      0x00100000
 360 /* Loads coprocessor register from memory, requiring delay.  */
 361 #define INSN_COPROC_MEMORY_DELAY    0x00200000
 362 /* Reads the HI register.  */
 363 #define INSN_READ_HI                0x00400000
 364 /* Reads the LO register.  */
 365 #define INSN_READ_LO                0x00800000
 366 /* Modifies the HI register.  */
 367 #define INSN_WRITE_HI               0x01000000
 368 /* Modifies the LO register.  */
 369 #define INSN_WRITE_LO               0x02000000
 370 /* Takes a trap (easier to keep out of delay slot).  */
 371 #define INSN_TRAP                   0x04000000
 372 /* Instruction stores value into memory.  */
 373 #define INSN_STORE_MEMORY           0x08000000
 374 /* Instruction uses single precision floating point.  */
 375 #define FP_S                        0x10000000
 376 /* Instruction uses double precision floating point.  */
 377 #define FP_D                        0x20000000
 378 /* Instruction is part of the tx39's integer multiply family.    */
 379 #define INSN_MULT                   0x40000000
 380 /* Instruction synchronize shared memory.  */
 381 #define INSN_SYNC                   0x80000000
 382
 383 /* These are the bits which may be set in the pinfo2 field of an
 384    instruction. */
 385
 386 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
 387 #define INSN2_ALIAS                 0x00000001
 388 /* Instruction reads MDMX accumulator. */
 389 #define INSN2_READ_MDMX_ACC         0x00000002
 390 /* Instruction writes MDMX accumulator. */
 391 #define INSN2_WRITE_MDMX_ACC        0x00000004
 392
 393 /* Instruction is actually a macro.  It should be ignored by the
 394    disassembler, and requires special treatment by the assembler.  */
 395 #define INSN_MACRO                  0xffffffff
 396
 397 /* Masks used to mark instructions to indicate which MIPS ISA level
 398    they were introduced in.  ISAs, as defined below, are logical
 399    ORs of these bits, indicating that they support the instructions
 400    defined at the given level.  */
 401
 402 #define INSN_ISA_MASK             0x00000fff
 403 #define INSN_ISA1                 0x00000001
 404 #define INSN_ISA2                 0x00000002
 405 #define INSN_ISA3                 0x00000004
 406 #define INSN_ISA4                 0x00000008
 407 #define INSN_ISA5                 0x00000010
 408 #define INSN_ISA32                0x00000020
 409 #define INSN_ISA64                0x00000040
 410 #define INSN_ISA32R2              0x00000080
 411 #define INSN_ISA64R2              0x00000100
 412
 413 /* Masks used for MIPS-defined ASEs.  */
 414 #define INSN_ASE_MASK             0x0000f000
 415
 416 /* MIPS 16 ASE */
 417 #define INSN_MIPS16               0x00002000
 418 /* MIPS-3D ASE */
 419 #define INSN_MIPS3D               0x00004000
 420 /* MDMX ASE */
 421 #define INSN_MDMX                 0x00008000
 422
 423 /* Chip specific instructions.  These are bitmasks.  */
 424
 425 /* MIPS R4650 instruction.  */
 426 #define INSN_4650                 0x00010000
 427 /* LSI R4010 instruction.  */
 428 #define INSN_4010                 0x00020000
 429 /* NEC VR4100 instruction.  */
 430 #define INSN_4100                 0x00040000
 431 /* Toshiba R3900 instruction.  */
 432 #define INSN_3900                 0x00080000
 433 /* MIPS R10000 instruction.  */
 434 #define INSN_10000                0x00100000
 435 /* Broadcom SB-1 instruction.  */
 436 #define INSN_SB1                  0x00200000
 437 /* NEC VR4111/VR4181 instruction.  */
 438 #define INSN_4111                 0x00400000
 439 /* NEC VR4120 instruction.  */
 440 #define INSN_4120                 0x00800000
 441 /* NEC VR5400 instruction.  */
 442 #define INSN_5400                 0x01000000
 443 /* NEC VR5500 instruction.  */
 444 #define INSN_5500                 0x02000000
 445
 446 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 447
 448 #define       ISA_UNKNOWN     0               /* Gas internal use.  */
 449 #define       ISA_MIPS1       (INSN_ISA1)
 450 #define       ISA_MIPS2       (ISA_MIPS1 | INSN_ISA2)
 451 #define       ISA_MIPS3       (ISA_MIPS2 | INSN_ISA3)
 452 #define       ISA_MIPS4       (ISA_MIPS3 | INSN_ISA4)
 453 #define       ISA_MIPS5       (ISA_MIPS4 | INSN_ISA5)
 454
 455 #define       ISA_MIPS32      (ISA_MIPS2 | INSN_ISA32)
 456 #define       ISA_MIPS64      (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
 457
 458 #define       ISA_MIPS32R2    (ISA_MIPS32 | INSN_ISA32R2)
 459 #define       ISA_MIPS64R2    (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
 460
 461
 462 /* CPU defines, use instead of hardcoding processor number. Keep this
 463    in sync with bfd/archures.c in order for machine selection to work.  */
 464 #define CPU_UNKNOWN     0               /* Gas internal use.  */
 465 #define CPU_R3000       3000
 466 #define CPU_R3900       3900
 467 #define CPU_R4000       4000
 468 #define CPU_R4010       4010
 469 #define CPU_VR4100      4100
 470 #define CPU_R4111       4111
 471 #define CPU_VR4120      4120
 472 #define CPU_R4300       4300
 473 #define CPU_R4400       4400
 474 #define CPU_R4600       4600
 475 #define CPU_R4650       4650
 476 #define CPU_R5000       5000
 477 #define CPU_VR5400      5400
 478 #define CPU_VR5500      5500
 479 #define CPU_R6000       6000
 480 #define CPU_RM7000      7000
 481 #define CPU_R8000       8000
 482 #define CPU_RM9000      9000
 483 #define CPU_R10000      10000
 484 #define CPU_R12000      12000
 485 #define CPU_MIPS16      16
 486 #define CPU_MIPS32      32
 487 #define CPU_MIPS32R2    33
 488 #define CPU_MIPS5       5
 489 #define CPU_MIPS64      64
 490 #define CPU_MIPS64R2    65
 491 #define CPU_SB1         12310201        /* octal 'SB', 01.  */
 492
 493 /* Test for membership in an ISA including chip specific ISAs.  INSN
 494    is pointer to an element of the opcode table; ISA is the specified
 495    ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
 496    test, or zero if no CPU specific ISA test is desired.  */
 497
 498 #define OPCODE_IS_MEMBER(insn, isa, cpu)                                \
 499     (((insn)->membership & isa) != 0                                    \
 500      || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)     \
 501      || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0)    \
 502      || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0)    \
 503      || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)     \
 504      || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0)    \
 505      || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)     \
 506      || ((cpu == CPU_R10000 || cpu == CPU_R12000)                       \
 507          && ((insn)->membership & INSN_10000) != 0)                     \
 508      || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0)        \
 509      || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0)     \
 510      || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0)    \
 511      || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0)    \
 512      || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0)    \
 513      || 0)      /* Please keep this term for easier source merging.  */
 514
 515 /* This is a list of macro expanded instructions.
 516
 517    _I appended means immediate
 518    _A appended means address
 519    _AB appended means address with base register
 520    _D appended means 64 bit floating point constant
 521    _S appended means 32 bit floating point constant.  */
 522
 523 enum
 524 {
 525   M_ABS,
 526   M_ADD_I,
 527   M_ADDU_I,
 528   M_AND_I,
 529   M_BEQ,
 530   M_BEQ_I,
 531   M_BEQL_I,
 532   M_BGE,
 533   M_BGEL,
 534   M_BGE_I,
 535   M_BGEL_I,
 536   M_BGEU,
 537   M_BGEUL,
 538   M_BGEU_I,
 539   M_BGEUL_I,
 540   M_BGT,
 541   M_BGTL,
 542   M_BGT_I,
 543   M_BGTL_I,
 544   M_BGTU,
 545   M_BGTUL,
 546   M_BGTU_I,
 547   M_BGTUL_I,
 548   M_BLE,
 549   M_BLEL,
 550   M_BLE_I,
 551   M_BLEL_I,
 552   M_BLEU,
 553   M_BLEUL,
 554   M_BLEU_I,
 555   M_BLEUL_I,
 556   M_BLT,
 557   M_BLTL,
 558   M_BLT_I,
 559   M_BLTL_I,
 560   M_BLTU,
 561   M_BLTUL,
 562   M_BLTU_I,
 563   M_BLTUL_I,
 564   M_BNE,
 565   M_BNE_I,
 566   M_BNEL_I,
 567   M_DABS,
 568   M_DADD_I,
 569   M_DADDU_I,
 570   M_DDIV_3,
 571   M_DDIV_3I,
 572   M_DDIVU_3,
 573   M_DDIVU_3I,
 574   M_DEXT,
 575   M_DINS,
 576   M_DIV_3,
 577   M_DIV_3I,
 578   M_DIVU_3,
 579   M_DIVU_3I,
 580   M_DLA_AB,
 581   M_DLCA_AB,
 582   M_DLI,
 583   M_DMUL,
 584   M_DMUL_I,
 585   M_DMULO,
 586   M_DMULO_I,
 587   M_DMULOU,
 588   M_DMULOU_I,
 589   M_DREM_3,
 590   M_DREM_3I,
 591   M_DREMU_3,
 592   M_DREMU_3I,
 593   M_DSUB_I,
 594   M_DSUBU_I,
 595   M_DSUBU_I_2,
 596   M_J_A,
 597   M_JAL_1,
 598   M_JAL_2,
 599   M_JAL_A,
 600   M_L_DOB,
 601   M_L_DAB,
 602   M_LA_AB,
 603   M_LB_A,
 604   M_LB_AB,
 605   M_LBU_A,
 606   M_LBU_AB,
 607   M_LCA_AB,
 608   M_LD_A,
 609   M_LD_OB,
 610   M_LD_AB,
 611   M_LDC1_AB,
 612   M_LDC2_AB,
 613   M_LDC3_AB,
 614   M_LDL_AB,
 615   M_LDR_AB,
 616   M_LH_A,
 617   M_LH_AB,
 618   M_LHU_A,
 619   M_LHU_AB,
 620   M_LI,
 621   M_LI_D,
 622   M_LI_DD,
 623   M_LI_S,
 624   M_LI_SS,
 625   M_LL_AB,
 626   M_LLD_AB,
 627   M_LS_A,
 628   M_LW_A,
 629   M_LW_AB,
 630   M_LWC0_A,
 631   M_LWC0_AB,
 632   M_LWC1_A,
 633   M_LWC1_AB,
 634   M_LWC2_A,
 635   M_LWC2_AB,
 636   M_LWC3_A,
 637   M_LWC3_AB,
 638   M_LWL_A,
 639   M_LWL_AB,
 640   M_LWR_A,
 641   M_LWR_AB,
 642   M_LWU_AB,
 643   M_MOVE,
 644   M_MUL,
 645   M_MUL_I,
 646   M_MULO,
 647   M_MULO_I,
 648   M_MULOU,
 649   M_MULOU_I,
 650   M_NOR_I,
 651   M_OR_I,
 652   M_REM_3,
 653   M_REM_3I,
 654   M_REMU_3,
 655   M_REMU_3I,
 656   M_DROL,
 657   M_ROL,
 658   M_DROL_I,
 659   M_ROL_I,
 660   M_DROR,
 661   M_ROR,
 662   M_DROR_I,
 663   M_ROR_I,
 664   M_S_DA,
 665   M_S_DOB,
 666   M_S_DAB,
 667   M_S_S,
 668   M_SC_AB,
 669   M_SCD_AB,
 670   M_SD_A,
 671   M_SD_OB,
 672   M_SD_AB,
 673   M_SDC1_AB,
 674   M_SDC2_AB,
 675   M_SDC3_AB,
 676   M_SDL_AB,
 677   M_SDR_AB,
 678   M_SEQ,
 679   M_SEQ_I,
 680   M_SGE,
 681   M_SGE_I,
 682   M_SGEU,
 683   M_SGEU_I,
 684   M_SGT,
 685   M_SGT_I,
 686   M_SGTU,
 687   M_SGTU_I,
 688   M_SLE,
 689   M_SLE_I,
 690   M_SLEU,
 691   M_SLEU_I,
 692   M_SLT_I,
 693   M_SLTU_I,
 694   M_SNE,
 695   M_SNE_I,
 696   M_SB_A,
 697   M_SB_AB,
 698   M_SH_A,
 699   M_SH_AB,
 700   M_SW_A,
 701   M_SW_AB,
 702   M_SWC0_A,
 703   M_SWC0_AB,
 704   M_SWC1_A,
 705   M_SWC1_AB,
 706   M_SWC2_A,
 707   M_SWC2_AB,
 708   M_SWC3_A,
 709   M_SWC3_AB,
 710   M_SWL_A,
 711   M_SWL_AB,
 712   M_SWR_A,
 713   M_SWR_AB,
 714   M_SUB_I,
 715   M_SUBU_I,
 716   M_SUBU_I_2,
 717   M_TEQ_I,
 718   M_TGE_I,
 719   M_TGEU_I,
 720   M_TLT_I,
 721   M_TLTU_I,
 722   M_TNE_I,
 723   M_TRUNCWD,
 724   M_TRUNCWS,
 725   M_ULD,
 726   M_ULD_A,
 727   M_ULH,
 728   M_ULH_A,
 729   M_ULHU,
 730   M_ULHU_A,
 731   M_ULW,
 732   M_ULW_A,
 733   M_USH,
 734   M_USH_A,
 735   M_USW,
 736   M_USW_A,
 737   M_USD,
 738   M_USD_A,
 739   M_XOR_I,
 740   M_COP0,
 741   M_COP1,
 742   M_COP2,
 743   M_COP3,
 744   M_NUM_MACROS
 745 };
 746
 747
 748 /* The order of overloaded instructions matters.  Label arguments and
 749    register arguments look the same. Instructions that can have either
 750    for arguments must apear in the correct order in this table for the
 751    assembler to pick the right one. In other words, entries with
 752    immediate operands must apear after the same instruction with
 753    registers.
 754
 755    Many instructions are short hand for other instructions (i.e., The
 756    jal <register> instruction is short for jalr <register>).  */
 757
 758 extern const struct mips_opcode mips_builtin_opcodes[];
 759 extern const int bfd_mips_num_builtin_opcodes;
 760 extern struct mips_opcode *mips_opcodes;
 761 extern int bfd_mips_num_opcodes;
 762 #define NUMOPCODES bfd_mips_num_opcodes
 763
 764 \f
 765 /* The rest of this file adds definitions for the mips16 TinyRISC
 766    processor.  */
 767
 768 /* These are the bitmasks and shift counts used for the different
 769    fields in the instruction formats.  Other than OP, no masks are
 770    provided for the fixed portions of an instruction, since they are
 771    not needed.
 772
 773    The I format uses IMM11.
 774
 775    The RI format uses RX and IMM8.
 776
 777    The RR format uses RX, and RY.
 778
 779    The RRI format uses RX, RY, and IMM5.
 780
 781    The RRR format uses RX, RY, and RZ.
 782
 783    The RRI_A format uses RX, RY, and IMM4.
 784
 785    The SHIFT format uses RX, RY, and SHAMT.
 786
 787    The I8 format uses IMM8.
 788
 789    The I8_MOVR32 format uses RY and REGR32.
 790
 791    The IR_MOV32R format uses REG32R and MOV32Z.
 792
 793    The I64 format uses IMM8.
 794
 795    The RI64 format uses RY and IMM5.
 796    */
 797
 798 #define MIPS16OP_MASK_OP        0x1f
 799 #define MIPS16OP_SH_OP          11
 800 #define MIPS16OP_MASK_IMM11     0x7ff
 801 #define MIPS16OP_SH_IMM11       0
 802 #define MIPS16OP_MASK_RX        0x7
 803 #define MIPS16OP_SH_RX          8
 804 #define MIPS16OP_MASK_IMM8      0xff
 805 #define MIPS16OP_SH_IMM8        0
 806 #define MIPS16OP_MASK_RY        0x7
 807 #define MIPS16OP_SH_RY          5
 808 #define MIPS16OP_MASK_IMM5      0x1f
 809 #define MIPS16OP_SH_IMM5        0
 810 #define MIPS16OP_MASK_RZ        0x7
 811 #define MIPS16OP_SH_RZ          2
 812 #define MIPS16OP_MASK_IMM4      0xf
 813 #define MIPS16OP_SH_IMM4        0
 814 #define MIPS16OP_MASK_REGR32    0x1f
 815 #define MIPS16OP_SH_REGR32      0
 816 #define MIPS16OP_MASK_REG32R    0x1f
 817 #define MIPS16OP_SH_REG32R      3
 818 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
 819 #define MIPS16OP_MASK_MOVE32Z   0x7
 820 #define MIPS16OP_SH_MOVE32Z     0
 821 #define MIPS16OP_MASK_IMM6      0x3f
 822 #define MIPS16OP_SH_IMM6        5
 823
 824 /* These are the characters which may appears in the args field of an
 825    instruction.  They appear in the order in which the fields appear
 826    when the instruction is used.  Commas and parentheses in the args
 827    string are ignored when assembling, and written into the output
 828    when disassembling.
 829
 830    "y" 3 bit register (MIPS16OP_*_RY)
 831    "x" 3 bit register (MIPS16OP_*_RX)
 832    "z" 3 bit register (MIPS16OP_*_RZ)
 833    "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
 834    "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
 835    "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
 836    "0" zero register ($0)
 837    "S" stack pointer ($sp or $29)
 838    "P" program counter
 839    "R" return address register ($ra or $31)
 840    "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
 841    "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
 842    "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
 843    "a" 26 bit jump address
 844    "e" 11 bit extension value
 845    "l" register list for entry instruction
 846    "L" register list for exit instruction
 847
 848    The remaining codes may be extended.  Except as otherwise noted,
 849    the full extended operand is a 16 bit signed value.
 850    "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
 851    ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
 852    "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
 853    "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
 854    "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
 855    "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
 856    "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
 857    "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
 858    "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
 859    "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
 860    "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
 861    "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
 862    "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
 863    "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
 864    "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
 865    "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
 866    "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
 867    "q" 11 bit branch address (MIPS16OP_*_IMM11)
 868    "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
 869    "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
 870    "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
 871    */
 872
 873 /* For the mips16, we use the same opcode table format and a few of
 874    the same flags.  However, most of the flags are different.  */
 875
 876 /* Modifies the register in MIPS16OP_*_RX.  */
 877 #define MIPS16_INSN_WRITE_X                 0x00000001
 878 /* Modifies the register in MIPS16OP_*_RY.  */
 879 #define MIPS16_INSN_WRITE_Y                 0x00000002
 880 /* Modifies the register in MIPS16OP_*_RZ.  */
 881 #define MIPS16_INSN_WRITE_Z                 0x00000004
 882 /* Modifies the T ($24) register.  */
 883 #define MIPS16_INSN_WRITE_T                 0x00000008
 884 /* Modifies the SP ($29) register.  */
 885 #define MIPS16_INSN_WRITE_SP                0x00000010
 886 /* Modifies the RA ($31) register.  */
 887 #define MIPS16_INSN_WRITE_31                0x00000020
 888 /* Modifies the general purpose register in MIPS16OP_*_REG32R.  */
 889 #define MIPS16_INSN_WRITE_GPR_Y             0x00000040
 890 /* Reads the register in MIPS16OP_*_RX.  */
 891 #define MIPS16_INSN_READ_X                  0x00000080
 892 /* Reads the register in MIPS16OP_*_RY.  */
 893 #define MIPS16_INSN_READ_Y                  0x00000100
 894 /* Reads the register in MIPS16OP_*_MOVE32Z.  */
 895 #define MIPS16_INSN_READ_Z                  0x00000200
 896 /* Reads the T ($24) register.  */
 897 #define MIPS16_INSN_READ_T                  0x00000400
 898 /* Reads the SP ($29) register.  */
 899 #define MIPS16_INSN_READ_SP                 0x00000800
 900 /* Reads the RA ($31) register.  */
 901 #define MIPS16_INSN_READ_31                 0x00001000
 902 /* Reads the program counter.  */
 903 #define MIPS16_INSN_READ_PC                 0x00002000
 904 /* Reads the general purpose register in MIPS16OP_*_REGR32.  */
 905 #define MIPS16_INSN_READ_GPR_X              0x00004000
 906 /* Is a branch insn. */
 907 #define MIPS16_INSN_BRANCH                  0x00010000
 908
 909 /* The following flags have the same value for the mips16 opcode
 910    table:
 911    INSN_UNCOND_BRANCH_DELAY
 912    INSN_COND_BRANCH_DELAY
 913    INSN_COND_BRANCH_LIKELY (never used)
 914    INSN_READ_HI
 915    INSN_READ_LO
 916    INSN_WRITE_HI
 917    INSN_WRITE_LO
 918    INSN_TRAP
 919    INSN_ISA3
 920    */
 921
 922 extern const struct mips_opcode mips16_opcodes[];
 923 extern const int bfd_mips16_num_opcodes;
 924
 925 #endif /* _MIPS_H_ */