include/opcode/m68k.h

   1 /* Opcode table header for m680[01234]0/m6888[12]/m68851.
   2    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001,
   3    2003, 2004 Free Software Foundation, Inc.
   4
   5    This file is part of GDB, GAS, and the GNU binutils.
   6
   7    GDB, GAS, and the GNU binutils are free software; you can redistribute
   8    them and/or modify them under the terms of the GNU General Public
   9    License as published by the Free Software Foundation; either version
  10    1, or (at your option) any later version.
  11
  12    GDB, GAS, and the GNU binutils are distributed in the hope that they
  13    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15    the GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  20    02111-1307, USA.  */
  21
  22 /* These are used as bit flags for the arch field in the m68k_opcode
  23    structure.  */
  24 #define _m68k_undef  0
  25 #define m68000   0x001
  26 #define m68008   m68000 /* Synonym for -m68000.  otherwise unused.  */
  27 #define m68010   0x002
  28 #define m68020   0x004
  29 #define m68030   0x008
  30 #define m68ec030 m68030 /* Similar enough to -m68030 to ignore differences;
  31                            gas will deal with the few differences.  */
  32 #define m68040   0x010
  33 /* There is no 68050.  */
  34 #define m68060   0x020
  35 #define m68881   0x040
  36 #define m68882   m68881 /* Synonym for -m68881.  otherwise unused.  */
  37 #define m68851   0x080
  38 #define cpu32    0x100          /* e.g., 68332 */
  39
  40 #define mcfmac   0x200          /* ColdFire MAC. */
  41 #define mcfemac  0x400          /* ColdFire EMAC. */
  42 #define cfloat   0x800          /* ColdFire FPU.  */
  43 #define mcfhwdiv 0x1000         /* ColdFire hardware divide.  */
  44
  45 #define mcfisa_a 0x2000         /* ColdFire ISA_A.  */
  46 #define mcfisa_aa 0x4000        /* ColdFire ISA_A+.  */
  47 #define mcfisa_b 0x8000         /* ColdFire ISA_B.  */
  48 #define mcfusp   0x10000        /* ColdFire USP instructions.  */
  49
  50 #define mcf5200  0x20000
  51 #define mcf5206e 0x40000
  52 #define mcf521x  0x80000
  53 #define mcf5249  0x100000
  54 #define mcf528x  0x200000
  55 #define mcf5307  0x400000
  56 #define mcf5407  0x800000
  57 #define mcf5470  0x1000000
  58 #define mcf5480  0x2000000
  59
  60  /* Handy aliases.  */
  61 #define m68040up   (m68040 | m68060)
  62 #define m68030up   (m68030 | m68040up)
  63 #define m68020up   (m68020 | m68030up)
  64 #define m68010up   (m68010 | cpu32 | m68020up)
  65 #define m68000up   (m68000 | m68010up)
  66
  67 #define mfloat  (m68881 | m68882 | m68040 | m68060)
  68 #define mmmu    (m68851 | m68030 | m68040 | m68060)
  69
  70 /* The structure used to hold information for an opcode.  */
  71
  72 struct m68k_opcode
  73 {
  74   /* The opcode name.  */
  75   const char *name;
  76   /* The pseudo-size of the instruction(in bytes).  Used to determine
  77      number of bytes necessary to disassemble the instruction.  */
  78   unsigned int size;
  79   /* The opcode itself.  */
  80   unsigned long opcode;
  81   /* The mask used by the disassembler.  */
  82   unsigned long match;
  83   /* The arguments.  */
  84   const char *args;
  85   /* The architectures which support this opcode.  */
  86   unsigned int arch;
  87 };
  88
  89 /* The structure used to hold information for an opcode alias.  */
  90
  91 struct m68k_opcode_alias
  92 {
  93   /* The alias name.  */
  94   const char *alias;
  95   /* The instruction for which this is an alias.  */
  96   const char *primary;
  97 };
  98
  99 /* We store four bytes of opcode for all opcodes because that is the
 100    most any of them need.  The actual length of an instruction is
 101    always at least 2 bytes, and is as much longer as necessary to hold
 102    the operands it has.
 103
 104    The match field is a mask saying which bits must match particular
 105    opcode in order for an instruction to be an instance of that
 106    opcode.
 107
 108    The args field is a string containing two characters for each
 109    operand of the instruction.  The first specifies the kind of
 110    operand; the second, the place it is stored.  */
 111
 112 /* Kinds of operands:
 113    Characters used: AaBbCcDdEeFfGgHIiJkLlMmnOopQqRrSsTtU VvWwXxYyZz01234|*~%;@!&$?/<>#^+-
 114
 115    D  data register only.  Stored as 3 bits.
 116    A  address register only.  Stored as 3 bits.
 117    a  address register indirect only.  Stored as 3 bits.
 118    R  either kind of register.  Stored as 4 bits.
 119    r  either kind of register indirect only.  Stored as 4 bits.
 120       At the moment, used only for cas2 instruction.
 121    F  floating point coprocessor register only.   Stored as 3 bits.
 122    O  an offset (or width): immediate data 0-31 or data register.
 123       Stored as 6 bits in special format for BF... insns.
 124    +  autoincrement only.  Stored as 3 bits (number of the address register).
 125    -  autodecrement only.  Stored as 3 bits (number of the address register).
 126    Q  quick immediate data.  Stored as 3 bits.
 127       This matches an immediate operand only when value is in range 1 .. 8.
 128    M  moveq immediate data.  Stored as 8 bits.
 129       This matches an immediate operand only when value is in range -128..127
 130    T  trap vector immediate data.  Stored as 4 bits.
 131
 132    k  K-factor for fmove.p instruction.   Stored as a 7-bit constant or
 133       a three bit register offset, depending on the field type.
 134
 135    #  immediate data.  Stored in special places (b, w or l)
 136       which say how many bits to store.
 137    ^  immediate data for floating point instructions.   Special places
 138       are offset by 2 bytes from '#'...
 139    B  pc-relative address, converted to an offset
 140       that is treated as immediate data.
 141    d  displacement and register.  Stores the register as 3 bits
 142       and stores the displacement in the entire second word.
 143
 144    C  the CCR.  No need to store it; this is just for filtering validity.
 145    S  the SR.  No need to store, just as with CCR.
 146    U  the USP.  No need to store, just as with CCR.
 147    E  the MAC ACC.  No need to store, just as with CCR.
 148    e  the EMAC ACC[0123].
 149    G  the MAC/EMAC MACSR.  No need to store, just as with CCR.
 150    g  the EMAC ACCEXT{01,23}.
 151    H  the MASK.  No need to store, just as with CCR.
 152    i  the MAC/EMAC scale factor.
 153
 154    I  Coprocessor ID.   Not printed if 1.   The Coprocessor ID is always
 155       extracted from the 'd' field of word one, which means that an extended
 156       coprocessor opcode can be skipped using the 'i' place, if needed.
 157
 158    s  System Control register for the floating point coprocessor.
 159
 160    J  Misc register for movec instruction, stored in 'j' format.
 161         Possible values:
 162         0x000   SFC     Source Function Code reg        [60, 40, 30, 20, 10]
 163         0x001   DFC     Data Function Code reg          [60, 40, 30, 20, 10]
 164         0x002   CACR    Cache Control Register          [60, 40, 30, 20, mcf]
 165         0x003   TC      MMU Translation Control         [60, 40]
 166         0x004   ITT0    Instruction Transparent
 167                                 Translation reg 0       [60, 40]
 168         0x005   ITT1    Instruction Transparent
 169                                 Translation reg 1       [60, 40]
 170         0x006   DTT0    Data Transparent
 171                                 Translation reg 0       [60, 40]
 172         0x007   DTT1    Data Transparent
 173                                 Translation reg 1       [60, 40]
 174         0x008   BUSCR   Bus Control Register            [60]
 175         0x800   USP     User Stack Pointer              [60, 40, 30, 20, 10]
 176         0x801   VBR     Vector Base reg                 [60, 40, 30, 20, 10, mcf]
 177         0x802   CAAR    Cache Address Register          [        30, 20]
 178         0x803   MSP     Master Stack Pointer            [    40, 30, 20]
 179         0x804   ISP     Interrupt Stack Pointer         [    40, 30, 20]
 180         0x805   MMUSR   MMU Status reg                  [    40]
 181         0x806   URP     User Root Pointer               [60, 40]
 182         0x807   SRP     Supervisor Root Pointer         [60, 40]
 183         0x808   PCR     Processor Configuration reg     [60]
 184         0xC00   ROMBAR  ROM Base Address Register       [520X]
 185         0xC04   RAMBAR0 RAM Base Address Register 0     [520X]
 186         0xC05   RAMBAR1 RAM Base Address Register 0     [520X]
 187         0xC0F   MBAR0   RAM Base Address Register 0     [520X]
 188         0xC04   FLASHBAR FLASH Base Address Register    [mcf528x]
 189         0xC05   RAMBAR  Static RAM Base Address Register [mcf528x]
 190
 191     L  Register list of the type d0-d7/a0-a7 etc.
 192        (New!  Improved!  Can also hold fp0-fp7, as well!)
 193        The assembler tries to see if the registers match the insn by
 194        looking at where the insn wants them stored.
 195
 196     l  Register list like L, but with all the bits reversed.
 197        Used for going the other way. . .
 198
 199     c  cache identifier which may be "nc" for no cache, "ic"
 200        for instruction cache, "dc" for data cache, or "bc"
 201        for both caches.  Used in cinv and cpush.  Always
 202        stored in position "d".
 203
 204     u  Any register, with ``upper'' or ``lower'' specification.  Used
 205        in the mac instructions with size word.
 206
 207  The remainder are all stored as 6 bits using an address mode and a
 208  register number; they differ in which addressing modes they match.
 209
 210    *  all                                       (modes 0-6,7.0-4)
 211    ~  alterable memory                          (modes 2-6,7.0,7.1)
 212                                                 (not 0,1,7.2-4)
 213    %  alterable                                 (modes 0-6,7.0,7.1)
 214                                                 (not 7.2-4)
 215    ;  data                                      (modes 0,2-6,7.0-4)
 216                                                 (not 1)
 217    @  data, but not immediate                   (modes 0,2-6,7.0-3)
 218                                                 (not 1,7.4)
 219    !  control                                   (modes 2,5,6,7.0-3)
 220                                                 (not 0,1,3,4,7.4)
 221    &  alterable control                         (modes 2,5,6,7.0,7.1)
 222                                                 (not 0,1,3,4,7.2-4)
 223    $  alterable data                            (modes 0,2-6,7.0,7.1)
 224                                                 (not 1,7.2-4)
 225    ?  alterable control, or data register       (modes 0,2,5,6,7.0,7.1)
 226                                                 (not 1,3,4,7.2-4)
 227    /  control, or data register                 (modes 0,2,5,6,7.0-3)
 228                                                 (not 1,3,4,7.4)
 229    >  *save operands                            (modes 2,4,5,6,7.0,7.1)
 230                                                 (not 0,1,3,7.2-4)
 231    <  *restore operands                         (modes 2,3,5,6,7.0-3)
 232                                                 (not 0,1,4,7.4)
 233
 234    coldfire move operands:
 235    m                                            (modes 0-4)
 236    n                                            (modes 5,7.2)
 237    o                                            (modes 6,7.0,7.1,7.3,7.4)
 238    p                                            (modes 0-5)
 239
 240    coldfire bset/bclr/btst/mulsl/mulul operands:
 241    q                                            (modes 0,2-5)
 242    v                                            (modes 0,2-5,7.0,7.1)
 243    b                                            (modes 0,2-5,7.2)
 244    w                                            (modes 2-5,7.2)
 245    y                                            (modes 2,5)
 246    z                                            (modes 2,5,7.2)
 247    x  mov3q immediate operand.
 248    4                                            (modes 2,3,4,5)
 249   */
 250
 251 /* For the 68851:  */
 252 /* I didn't use much imagination in choosing the
 253    following codes, so many of them aren't very
 254    mnemonic. -rab
 255
 256    0  32 bit pmmu register
 257         Possible values:
 258         000     TC      Translation Control Register (68030, 68851)
 259
 260    1  16 bit pmmu register
 261         111     AC      Access Control (68851)
 262
 263    2  8 bit pmmu register
 264         100     CAL     Current Access Level (68851)
 265         101     VAL     Validate Access Level (68851)
 266         110     SCC     Stack Change Control (68851)
 267
 268    3  68030-only pmmu registers (32 bit)
 269         010     TT0     Transparent Translation reg 0
 270                         (aka Access Control reg 0 -- AC0 -- on 68ec030)
 271         011     TT1     Transparent Translation reg 1
 272                         (aka Access Control reg 1 -- AC1 -- on 68ec030)
 273
 274    W  wide pmmu registers
 275         Possible values:
 276         001     DRP     Dma Root Pointer (68851)
 277         010     SRP     Supervisor Root Pointer (68030, 68851)
 278         011     CRP     Cpu Root Pointer (68030, 68851)
 279
 280    f    function code register (68030, 68851)
 281         0       SFC
 282         1       DFC
 283
 284    V    VAL register only (68851)
 285
 286    X    BADx, BACx (16 bit)
 287         100     BAD     Breakpoint Acknowledge Data (68851)
 288         101     BAC     Breakpoint Acknowledge Control (68851)
 289
 290    Y    PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030)
 291    Z    PCSR (68851)
 292
 293    |    memory          (modes 2-6, 7.*)
 294
 295    t  address test level (68030 only)
 296       Stored as 3 bits, range 0-7.
 297       Also used for breakpoint instruction now.
 298
 299 */
 300
 301 /* Places to put an operand, for non-general operands:
 302    Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/
 303
 304    s  source, low bits of first word.
 305    d  dest, shifted 9 in first word
 306    1  second word, shifted 12
 307    2  second word, shifted 6
 308    3  second word, shifted 0
 309    4  third word, shifted 12
 310    5  third word, shifted 6
 311    6  third word, shifted 0
 312    7  second word, shifted 7
 313    8  second word, shifted 10
 314    9  second word, shifted 5
 315    D  store in both place 1 and place 3; for divul and divsl.
 316    B  first word, low byte, for branch displacements
 317    W  second word (entire), for branch displacements
 318    L  second and third words (entire), for branch displacements
 319       (also overloaded for move16)
 320    b  second word, low byte
 321    w  second word (entire) [variable word/long branch offset for dbra]
 322    W  second word (entire) (must be signed 16 bit value)
 323    l  second and third word (entire)
 324    g  variable branch offset for bra and similar instructions.
 325       The place to store depends on the magnitude of offset.
 326    t  store in both place 7 and place 8; for floating point operations
 327    c  branch offset for cpBcc operations.
 328       The place to store is word two if bit six of word one is zero,
 329       and words two and three if bit six of word one is one.
 330    i  Increment by two, to skip over coprocessor extended operands.   Only
 331       works with the 'I' format.
 332    k  Dynamic K-factor field.   Bits 6-4 of word 2, used as a register number.
 333       Also used for dynamic fmovem instruction.
 334    C  floating point coprocessor constant - 7 bits.  Also used for static
 335       K-factors...
 336    j  Movec register #, stored in 12 low bits of second word.
 337    m  For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word
 338       and remaining 3 bits of register shifted 9 bits in first word.
 339       Indicate upper/lower in 1 bit shifted 7 bits in second word.
 340       Use with `R' or `u' format.
 341    n  `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split
 342       with MSB shifted 6 bits in first word and remaining 3 bits of
 343       register shifted 9 bits in first word.  No upper/lower
 344       indication is done.)  Use with `R' or `u' format.
 345    o  For M[S]ACw; 4 bits shifted 12 in second word (like `1').
 346       Indicate upper/lower in 1 bit shifted 7 bits in second word.
 347       Use with `R' or `u' format.
 348    M  For M[S]ACw; 4 bits in low bits of first word.  Indicate
 349       upper/lower in 1 bit shifted 6 bits in second word.  Use with
 350       `R' or `u' format.
 351    N  For M[S]ACw; 4 bits in low bits of second word.  Indicate
 352       upper/lower in 1 bit shifted 6 bits in second word.  Use with
 353       `R' or `u' format.
 354    h  shift indicator (scale factor), 1 bit shifted 10 in second word
 355
 356  Places to put operand, for general operands:
 357    d  destination, shifted 6 bits in first word
 358    b  source, at low bit of first word, and immediate uses one byte
 359    w  source, at low bit of first word, and immediate uses two bytes
 360    l  source, at low bit of first word, and immediate uses four bytes
 361    s  source, at low bit of first word.
 362       Used sometimes in contexts where immediate is not allowed anyway.
 363    f  single precision float, low bit of 1st word, immediate uses 4 bytes
 364    F  double precision float, low bit of 1st word, immediate uses 8 bytes
 365    x  extended precision float, low bit of 1st word, immediate uses 12 bytes
 366    p  packed float, low bit of 1st word, immediate uses 12 bytes
 367    G  EMAC accumulator, load  (bit 4 2nd word, !bit8 first word)
 368    H  EMAC accumulator, non load  (bit 4 2nd word, bit 8 first word)
 369    F  EMAC ACCx
 370    f  EMAC ACCy
 371    I  MAC/EMAC scale factor
 372    /  Like 's', but set 2nd word, bit 5 if trailing_ampersand set
 373    ]  first word, bit 10
 374 */
 375
 376 extern const struct m68k_opcode m68k_opcodes[];
 377 extern const struct m68k_opcode_alias m68k_opcode_aliases[];
 378
 379 extern const int m68k_numopcodes, m68k_numaliases;
 380
 381 /* end of m68k-opcode.h */