1 /* DO NOT EDIT! -*- buffer-read-only: t -*-
2 This file is automatically generated by z8kgen. */
15 #define ARG_IMM16 0x03
16 #define ARG_IMM32 0x04
18 #define ARG_IMMNMINUS1 0x05
19 #define ARG_IMM_1 0x06
20 #define ARG_IMM_2 0x07
21 #define ARG_DISP16 0x08
24 #define ARG_IMM1OR2 0x0b
25 #define ARG_DISP12 0x0b
27 #define ARG_DISP8 0x0c
28 #define ARG_IMM4M1 0x0d
33 #define CLASS_DISP 0x50
34 #define CLASS_IMM 0x60
36 #define CLASS_CTRL 0x80
37 #define CLASS_IGNORE 0x90
38 #define CLASS_ADDRESS 0xd0
39 #define CLASS_0CCC 0xe0
40 #define CLASS_1CCC 0xf0
41 #define CLASS_0DISP7 0x100
42 #define CLASS_1DISP7 0x200
43 #define CLASS_01II 0x300
44 #define CLASS_00II 0x400
45 #define CLASS_BIT 0x500
46 #define CLASS_FLAGS 0x600
47 #define CLASS_IR 0x700
48 #define CLASS_IRO 0x800
49 #define CLASS_DISP8 0x900
50 #define CLASS_BIT_1OR2 0xa00
51 #define CLASS_REG 0x7000
52 #define CLASS_REG_BYTE 0x2000
53 #define CLASS_REG_WORD 0x3000
54 #define CLASS_REG_QUAD 0x4000
55 #define CLASS_REG_LONG 0x5000
56 #define CLASS_REGN0 0x8000
57 #define CLASS_PR 0x10000
58 #define CLASS_MASK 0x1fff0
162 #define OPC_pushl 103
165 #define OPC_resflg 106
187 #define OPC_setflg 128
191 #define OPC_sindb 132
192 #define OPC_sindr 133
193 #define OPC_sindrb 134
195 #define OPC_sinib 136
196 #define OPC_sinir 137
197 #define OPC_sinirb 138
204 #define OPC_sotdr 145
205 #define OPC_sotdrb 146
206 #define OPC_sotir 147
207 #define OPC_sotirb 148
209 #define OPC_soutb 150
210 #define OPC_soutd 151
211 #define OPC_soutdb 152
212 #define OPC_souti 153
213 #define OPC_soutib 154
226 #define OPC_testb 167
227 #define OPC_testl 168
229 #define OPC_trdrb 170
231 #define OPC_trirb 172
232 #define OPC_trtdrb 173
233 #define OPC_trtib 174
234 #define OPC_trtirb 175
235 #define OPC_trtrb 176
237 #define OPC_tsetb 178
243 #define OPC_lddrb 184
248 #define OPC_ext0e 188
249 #define OPC_ext0f 188
250 #define OPC_ext8e 188
251 #define OPC_ext8f 188
252 #define OPC_rsvd36 188
253 #define OPC_rsvd38 188
254 #define OPC_rsvd78 188
255 #define OPC_rsvd7e 188
256 #define OPC_rsvd9d 188
257 #define OPC_rsvd9f 188
258 #define OPC_rsvdb9 188
259 #define OPC_rsvdbf 188
260 #define OPC_ldctlb 189
261 #define OPC_trtdb 190
266 const char *nicename
;
272 unsigned char opcode
;
273 void (*func
) PARAMS ((void));
274 unsigned int arg_info
[4];
275 unsigned int byte_info
[10];
282 const opcode_entry_type z8k_table
[] = {
284 /* 1011 0101 ssss dddd *** adc rd,rs */
287 "adc rd,rs",16,5,0x3c,
289 "adc",OPC_adc
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
290 {CLASS_BIT
+0xb,CLASS_BIT
+5,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,0},
292 /* 1011 0100 ssss dddd *** adcb rbd,rbs */
295 "adcb rbd,rbs",8,5,0x3f,
297 "adcb",OPC_adcb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_REG_BYTE
+(ARG_RS
),},
298 {CLASS_BIT
+0xb,CLASS_BIT
+4,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,1},
300 /* 0000 0001 ssN0 dddd *** add rd,@rs */
303 "add rd,@rs",16,7,0x3c,
305 "add",OPC_add
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
306 {CLASS_BIT
+0,CLASS_BIT
+1,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,2},
308 /* 0100 0001 0000 dddd address_src *** add rd,address_src */
311 "add rd,address_src",16,9,0x3c,
313 "add",OPC_add
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_DA
+(ARG_SRC
),},
314 {CLASS_BIT
+4,CLASS_BIT
+1,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,2},
316 /* 0100 0001 ssN0 dddd address_src *** add rd,address_src(rs) */
319 "add rd,address_src(rs)",16,10,0x3c,
321 "add",OPC_add
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_X
+(ARG_RS
),},
322 {CLASS_BIT
+4,CLASS_BIT
+1,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,2},
324 /* 0000 0001 0000 dddd imm16 *** add rd,imm16 */
327 "add rd,imm16",16,7,0x3c,
329 "add",OPC_add
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),},
330 {CLASS_BIT
+0,CLASS_BIT
+1,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),0,0,0,0,},2,4,2},
332 /* 1000 0001 ssss dddd *** add rd,rs */
335 "add rd,rs",16,4,0x3c,
337 "add",OPC_add
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
338 {CLASS_BIT
+8,CLASS_BIT
+1,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,2},
340 /* 0000 0000 ssN0 dddd *** addb rbd,@rs */
343 "addb rbd,@rs",8,7,0x3f,
345 "addb",OPC_addb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
346 {CLASS_BIT
+0,CLASS_BIT
+0,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,3},
348 /* 0100 0000 0000 dddd address_src *** addb rbd,address_src */
351 "addb rbd,address_src",8,9,0x3f,
353 "addb",OPC_addb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_DA
+(ARG_SRC
),},
354 {CLASS_BIT
+4,CLASS_BIT
+0,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,3},
356 /* 0100 0000 ssN0 dddd address_src *** addb rbd,address_src(rs) */
359 "addb rbd,address_src(rs)",8,10,0x3f,
361 "addb",OPC_addb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_X
+(ARG_RS
),},
362 {CLASS_BIT
+4,CLASS_BIT
+0,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,3},
364 /* 0000 0000 0000 dddd imm8 imm8 *** addb rbd,imm8 */
367 "addb rbd,imm8",8,7,0x3f,
369 "addb",OPC_addb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IMM
+(ARG_IMM8
),},
370 {CLASS_BIT
+0,CLASS_BIT
+0,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM8
),CLASS_IMM
+(ARG_IMM8
),0,0,0,},2,4,3},
372 /* 1000 0000 ssss dddd *** addb rbd,rbs */
375 "addb rbd,rbs",8,4,0x3f,
377 "addb",OPC_addb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_REG_BYTE
+(ARG_RS
),},
378 {CLASS_BIT
+8,CLASS_BIT
+0,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,3},
380 /* 0001 0110 ssN0 dddd *** addl rrd,@rs */
383 "addl rrd,@rs",32,14,0x3c,
385 "addl",OPC_addl
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
386 {CLASS_BIT
+1,CLASS_BIT
+6,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,4},
388 /* 0101 0110 0000 dddd address_src *** addl rrd,address_src */
391 "addl rrd,address_src",32,15,0x3c,
393 "addl",OPC_addl
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_DA
+(ARG_SRC
),},
394 {CLASS_BIT
+5,CLASS_BIT
+6,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,4},
396 /* 0101 0110 ssN0 dddd address_src *** addl rrd,address_src(rs) */
399 "addl rrd,address_src(rs)",32,16,0x3c,
401 "addl",OPC_addl
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_X
+(ARG_RS
),},
402 {CLASS_BIT
+5,CLASS_BIT
+6,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,4},
404 /* 0001 0110 0000 dddd imm32 *** addl rrd,imm32 */
407 "addl rrd,imm32",32,14,0x3c,
409 "addl",OPC_addl
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM32
),},
410 {CLASS_BIT
+1,CLASS_BIT
+6,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM32
),0,0,0,0,},2,6,4},
412 /* 1001 0110 ssss dddd *** addl rrd,rrs */
415 "addl rrd,rrs",32,8,0x3c,
417 "addl",OPC_addl
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_REG_LONG
+(ARG_RS
),},
418 {CLASS_BIT
+9,CLASS_BIT
+6,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,4},
420 /* 0000 0111 ssN0 dddd *** and rd,@rs */
423 "and rd,@rs",16,7,0x18,
425 "and",OPC_and
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
426 {CLASS_BIT
+0,CLASS_BIT
+7,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,5},
428 /* 0100 0111 0000 dddd address_src *** and rd,address_src */
431 "and rd,address_src",16,9,0x18,
433 "and",OPC_and
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_DA
+(ARG_SRC
),},
434 {CLASS_BIT
+4,CLASS_BIT
+7,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,5},
436 /* 0100 0111 ssN0 dddd address_src *** and rd,address_src(rs) */
439 "and rd,address_src(rs)",16,10,0x18,
441 "and",OPC_and
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_X
+(ARG_RS
),},
442 {CLASS_BIT
+4,CLASS_BIT
+7,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,5},
444 /* 0000 0111 0000 dddd imm16 *** and rd,imm16 */
447 "and rd,imm16",16,7,0x18,
449 "and",OPC_and
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),},
450 {CLASS_BIT
+0,CLASS_BIT
+7,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),0,0,0,0,},2,4,5},
452 /* 1000 0111 ssss dddd *** and rd,rs */
455 "and rd,rs",16,4,0x18,
457 "and",OPC_and
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
458 {CLASS_BIT
+8,CLASS_BIT
+7,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,5},
460 /* 0000 0110 ssN0 dddd *** andb rbd,@rs */
463 "andb rbd,@rs",8,7,0x1c,
465 "andb",OPC_andb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
466 {CLASS_BIT
+0,CLASS_BIT
+6,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,6},
468 /* 0100 0110 0000 dddd address_src *** andb rbd,address_src */
471 "andb rbd,address_src",8,9,0x1c,
473 "andb",OPC_andb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_DA
+(ARG_SRC
),},
474 {CLASS_BIT
+4,CLASS_BIT
+6,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,6},
476 /* 0100 0110 ssN0 dddd address_src *** andb rbd,address_src(rs) */
479 "andb rbd,address_src(rs)",8,10,0x1c,
481 "andb",OPC_andb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_X
+(ARG_RS
),},
482 {CLASS_BIT
+4,CLASS_BIT
+6,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,6},
484 /* 0000 0110 0000 dddd imm8 imm8 *** andb rbd,imm8 */
487 "andb rbd,imm8",8,7,0x1c,
489 "andb",OPC_andb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IMM
+(ARG_IMM8
),},
490 {CLASS_BIT
+0,CLASS_BIT
+6,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM8
),CLASS_IMM
+(ARG_IMM8
),0,0,0,},2,4,6},
492 /* 1000 0110 ssss dddd *** andb rbd,rbs */
495 "andb rbd,rbs",8,4,0x1c,
497 "andb",OPC_andb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_REG_BYTE
+(ARG_RS
),},
498 {CLASS_BIT
+8,CLASS_BIT
+6,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,6},
500 /* 0010 0111 ddN0 imm4 *** bit @rd,imm4 */
503 "bit @rd,imm4",16,8,0x10,
505 "bit",OPC_bit
,0,{CLASS_IR
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),},
506 {CLASS_BIT
+2,CLASS_BIT
+7,CLASS_REGN0
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),0,0,0,0,0,},2,2,7},
508 /* 0110 0111 ddN0 imm4 address_dst *** bit address_dst(rd),imm4 */
511 "bit address_dst(rd),imm4",16,11,0x10,
513 "bit",OPC_bit
,0,{CLASS_X
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),},
514 {CLASS_BIT
+6,CLASS_BIT
+7,CLASS_REGN0
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,7},
516 /* 0110 0111 0000 imm4 address_dst *** bit address_dst,imm4 */
519 "bit address_dst,imm4",16,10,0x10,
521 "bit",OPC_bit
,0,{CLASS_DA
+(ARG_DST
),CLASS_IMM
+(ARG_IMM4
),},
522 {CLASS_BIT
+6,CLASS_BIT
+7,CLASS_BIT
+0,CLASS_IMM
+(ARG_IMM4
),CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,7},
524 /* 1010 0111 dddd imm4 *** bit rd,imm4 */
527 "bit rd,imm4",16,4,0x10,
529 "bit",OPC_bit
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),},
530 {CLASS_BIT
+0xa,CLASS_BIT
+7,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),0,0,0,0,0,},2,2,7},
532 /* 0010 0111 0000 ssss 0000 dddd 0000 0000 *** bit rd,rs */
535 "bit rd,rs",16,10,0x10,
537 "bit",OPC_bit
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
538 {CLASS_BIT
+2,CLASS_BIT
+7,CLASS_BIT
+0,CLASS_REG
+(ARG_RS
),CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_BIT
+0,CLASS_BIT
+0,0,},2,4,7},
540 /* 0010 0110 ddN0 imm4 *** bitb @rd,imm4 */
543 "bitb @rd,imm4",8,8,0x10,
545 "bitb",OPC_bitb
,0,{CLASS_IR
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),},
546 {CLASS_BIT
+2,CLASS_BIT
+6,CLASS_REGN0
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),0,0,0,0,0,},2,2,8},
548 /* 0110 0110 ddN0 imm4 address_dst *** bitb address_dst(rd),imm4 */
551 "bitb address_dst(rd),imm4",8,11,0x10,
553 "bitb",OPC_bitb
,0,{CLASS_X
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),},
554 {CLASS_BIT
+6,CLASS_BIT
+6,CLASS_REGN0
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,8},
556 /* 0110 0110 0000 imm4 address_dst *** bitb address_dst,imm4 */
559 "bitb address_dst,imm4",8,10,0x10,
561 "bitb",OPC_bitb
,0,{CLASS_DA
+(ARG_DST
),CLASS_IMM
+(ARG_IMM4
),},
562 {CLASS_BIT
+6,CLASS_BIT
+6,CLASS_BIT
+0,CLASS_IMM
+(ARG_IMM4
),CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,8},
564 /* 1010 0110 dddd imm4 *** bitb rbd,imm4 */
567 "bitb rbd,imm4",8,4,0x10,
569 "bitb",OPC_bitb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),},
570 {CLASS_BIT
+0xa,CLASS_BIT
+6,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),0,0,0,0,0,},2,2,8},
572 /* 0010 0110 0000 ssss 0000 dddd 0000 0000 *** bitb rbd,rs */
575 "bitb rbd,rs",8,10,0x10,
577 "bitb",OPC_bitb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
578 {CLASS_BIT
+2,CLASS_BIT
+6,CLASS_BIT
+0,CLASS_REG
+(ARG_RS
),CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_BIT
+0,CLASS_BIT
+0,0,},2,4,8},
580 /* 0011 0110 0000 0000 *** bpt */
586 {CLASS_BIT
+3,CLASS_BIT
+6,CLASS_BIT
+0,CLASS_BIT
+0,0,0,0,0,0,},0,2,9},
588 /* 0000 1111 0000 1100 *** brk */
594 {CLASS_BIT
+0,CLASS_BIT
+0xf,CLASS_BIT
+0,CLASS_BIT
+0xc,0,0,0,0,0,},0,2,10},
596 /* 0001 1111 ddN0 0000 *** call @rd */
599 "call @rd",32,10,0x00,
601 "call",OPC_call
,0,{CLASS_IR
+(ARG_RD
),},
602 {CLASS_BIT
+1,CLASS_BIT
+0xf,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+0,0,0,0,0,0,},1,2,11},
604 /* 0101 1111 0000 0000 address_dst *** call address_dst */
607 "call address_dst",32,12,0x00,
609 "call",OPC_call
,0,{CLASS_DA
+(ARG_DST
),},
610 {CLASS_BIT
+5,CLASS_BIT
+0xf,CLASS_BIT
+0,CLASS_BIT
+0,CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},1,4,11},
612 /* 0101 1111 ddN0 0000 address_dst *** call address_dst(rd) */
615 "call address_dst(rd)",32,13,0x00,
617 "call",OPC_call
,0,{CLASS_X
+(ARG_RD
),},
618 {CLASS_BIT
+5,CLASS_BIT
+0xf,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+0,CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},1,4,11},
620 /* 1101 disp12 *** calr disp12 */
623 "calr disp12",16,10,0x00,
625 "calr",OPC_calr
,0,{CLASS_DISP
,},
626 {CLASS_BIT
+0xd,CLASS_DISP
+(ARG_DISP12
),0,0,0,0,0,0,0,},1,2,12},
628 /* 0000 1101 ddN0 1000 *** clr @rd */
633 "clr",OPC_clr
,0,{CLASS_IR
+(ARG_RD
),},
634 {CLASS_BIT
+0,CLASS_BIT
+0xd,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+8,0,0,0,0,0,},1,2,13},
636 /* 0100 1101 0000 1000 address_dst *** clr address_dst */
639 "clr address_dst",16,11,0x00,
641 "clr",OPC_clr
,0,{CLASS_DA
+(ARG_DST
),},
642 {CLASS_BIT
+4,CLASS_BIT
+0xd,CLASS_BIT
+0,CLASS_BIT
+8,CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},1,4,13},
644 /* 0100 1101 ddN0 1000 address_dst *** clr address_dst(rd) */
647 "clr address_dst(rd)",16,12,0x00,
649 "clr",OPC_clr
,0,{CLASS_X
+(ARG_RD
),},
650 {CLASS_BIT
+4,CLASS_BIT
+0xd,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+8,CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},1,4,13},
652 /* 1000 1101 dddd 1000 *** clr rd */
657 "clr",OPC_clr
,0,{CLASS_REG_WORD
+(ARG_RD
),},
658 {CLASS_BIT
+8,CLASS_BIT
+0xd,CLASS_REG
+(ARG_RD
),CLASS_BIT
+8,0,0,0,0,0,},1,2,13},
660 /* 0000 1100 ddN0 1000 *** clrb @rd */
665 "clrb",OPC_clrb
,0,{CLASS_IR
+(ARG_RD
),},
666 {CLASS_BIT
+0,CLASS_BIT
+0xc,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+8,0,0,0,0,0,},1,2,14},
668 /* 0100 1100 0000 1000 address_dst *** clrb address_dst */
671 "clrb address_dst",8,11,0x00,
673 "clrb",OPC_clrb
,0,{CLASS_DA
+(ARG_DST
),},
674 {CLASS_BIT
+4,CLASS_BIT
+0xc,CLASS_BIT
+0,CLASS_BIT
+8,CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},1,4,14},
676 /* 0100 1100 ddN0 1000 address_dst *** clrb address_dst(rd) */
679 "clrb address_dst(rd)",8,12,0x00,
681 "clrb",OPC_clrb
,0,{CLASS_X
+(ARG_RD
),},
682 {CLASS_BIT
+4,CLASS_BIT
+0xc,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+8,CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},1,4,14},
684 /* 1000 1100 dddd 1000 *** clrb rbd */
689 "clrb",OPC_clrb
,0,{CLASS_REG_BYTE
+(ARG_RD
),},
690 {CLASS_BIT
+8,CLASS_BIT
+0xc,CLASS_REG
+(ARG_RD
),CLASS_BIT
+8,0,0,0,0,0,},1,2,14},
692 /* 0000 1101 ddN0 0000 *** com @rd */
695 "com @rd",16,12,0x18,
697 "com",OPC_com
,0,{CLASS_IR
+(ARG_RD
),},
698 {CLASS_BIT
+0,CLASS_BIT
+0xd,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+0,0,0,0,0,0,},1,2,15},
700 /* 0100 1101 0000 0000 address_dst *** com address_dst */
703 "com address_dst",16,15,0x18,
705 "com",OPC_com
,0,{CLASS_DA
+(ARG_DST
),},
706 {CLASS_BIT
+4,CLASS_BIT
+0xd,CLASS_BIT
+0,CLASS_BIT
+0,CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},1,4,15},
708 /* 0100 1101 ddN0 0000 address_dst *** com address_dst(rd) */
711 "com address_dst(rd)",16,16,0x18,
713 "com",OPC_com
,0,{CLASS_X
+(ARG_RD
),},
714 {CLASS_BIT
+4,CLASS_BIT
+0xd,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+0,CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},1,4,15},
716 /* 1000 1101 dddd 0000 *** com rd */
721 "com",OPC_com
,0,{CLASS_REG_WORD
+(ARG_RD
),},
722 {CLASS_BIT
+8,CLASS_BIT
+0xd,CLASS_REG
+(ARG_RD
),CLASS_BIT
+0,0,0,0,0,0,},1,2,15},
724 /* 0000 1100 ddN0 0000 *** comb @rd */
727 "comb @rd",8,12,0x1c,
729 "comb",OPC_comb
,0,{CLASS_IR
+(ARG_RD
),},
730 {CLASS_BIT
+0,CLASS_BIT
+0xc,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+0,0,0,0,0,0,},1,2,16},
732 /* 0100 1100 0000 0000 address_dst *** comb address_dst */
735 "comb address_dst",8,15,0x1c,
737 "comb",OPC_comb
,0,{CLASS_DA
+(ARG_DST
),},
738 {CLASS_BIT
+4,CLASS_BIT
+0xc,CLASS_BIT
+0,CLASS_BIT
+0,CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},1,4,16},
740 /* 0100 1100 ddN0 0000 address_dst *** comb address_dst(rd) */
743 "comb address_dst(rd)",8,16,0x1c,
745 "comb",OPC_comb
,0,{CLASS_X
+(ARG_RD
),},
746 {CLASS_BIT
+4,CLASS_BIT
+0xc,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+0,CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},1,4,16},
748 /* 1000 1100 dddd 0000 *** comb rbd */
753 "comb",OPC_comb
,0,{CLASS_REG_BYTE
+(ARG_RD
),},
754 {CLASS_BIT
+8,CLASS_BIT
+0xc,CLASS_REG
+(ARG_RD
),CLASS_BIT
+0,0,0,0,0,0,},1,2,16},
756 /* 1000 1101 flags 0101 *** comflg flags */
759 "comflg flags",16,7,0x3c,
761 "comflg",OPC_comflg
,0,{CLASS_FLAGS
,},
762 {CLASS_BIT
+8,CLASS_BIT
+0xd,CLASS_FLAGS
,CLASS_BIT
+5,0,0,0,0,0,},1,2,17},
764 /* 0000 1101 ddN0 0001 imm16 *** cp @rd,imm16 */
767 "cp @rd,imm16",16,11,0x3c,
769 "cp",OPC_cp
,0,{CLASS_IR
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),},
770 {CLASS_BIT
+0,CLASS_BIT
+0xd,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+1,CLASS_IMM
+(ARG_IMM16
),0,0,0,0,},2,4,18},
772 /* 0100 1101 ddN0 0001 address_dst imm16 *** cp address_dst(rd),imm16 */
775 "cp address_dst(rd),imm16",16,15,0x3c,
777 "cp",OPC_cp
,0,{CLASS_X
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),},
778 {CLASS_BIT
+4,CLASS_BIT
+0xd,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+1,CLASS_ADDRESS
+(ARG_DST
),CLASS_IMM
+(ARG_IMM16
),0,0,0,},2,6,18},
780 /* 0100 1101 0000 0001 address_dst imm16 *** cp address_dst,imm16 */
783 "cp address_dst,imm16",16,14,0x3c,
785 "cp",OPC_cp
,0,{CLASS_DA
+(ARG_DST
),CLASS_IMM
+(ARG_IMM16
),},
786 {CLASS_BIT
+4,CLASS_BIT
+0xd,CLASS_BIT
+0,CLASS_BIT
+1,CLASS_ADDRESS
+(ARG_DST
),CLASS_IMM
+(ARG_IMM16
),0,0,0,},2,6,18},
788 /* 0000 1011 ssN0 dddd *** cp rd,@rs */
791 "cp rd,@rs",16,7,0x3c,
793 "cp",OPC_cp
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
794 {CLASS_BIT
+0,CLASS_BIT
+0xb,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,18},
796 /* 0100 1011 0000 dddd address_src *** cp rd,address_src */
799 "cp rd,address_src",16,9,0x3c,
801 "cp",OPC_cp
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_DA
+(ARG_SRC
),},
802 {CLASS_BIT
+4,CLASS_BIT
+0xb,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,18},
804 /* 0100 1011 ssN0 dddd address_src *** cp rd,address_src(rs) */
807 "cp rd,address_src(rs)",16,10,0x3c,
809 "cp",OPC_cp
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_X
+(ARG_RS
),},
810 {CLASS_BIT
+4,CLASS_BIT
+0xb,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,18},
812 /* 0000 1011 0000 dddd imm16 *** cp rd,imm16 */
815 "cp rd,imm16",16,7,0x3c,
817 "cp",OPC_cp
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),},
818 {CLASS_BIT
+0,CLASS_BIT
+0xb,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),0,0,0,0,},2,4,18},
820 /* 1000 1011 ssss dddd *** cp rd,rs */
823 "cp rd,rs",16,4,0x3c,
825 "cp",OPC_cp
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
826 {CLASS_BIT
+8,CLASS_BIT
+0xb,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,18},
828 /* 0000 1100 ddN0 0001 imm8 imm8 *** cpb @rd,imm8 */
831 "cpb @rd,imm8",8,11,0x3c,
833 "cpb",OPC_cpb
,0,{CLASS_IR
+(ARG_RD
),CLASS_IMM
+(ARG_IMM8
),},
834 {CLASS_BIT
+0,CLASS_BIT
+0xc,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+1,CLASS_IMM
+(ARG_IMM8
),CLASS_IMM
+(ARG_IMM8
),0,0,0,},2,4,19},
836 /* 0100 1100 ddN0 0001 address_dst imm8 imm8 *** cpb address_dst(rd),imm8 */
839 "cpb address_dst(rd),imm8",8,15,0x3c,
841 "cpb",OPC_cpb
,0,{CLASS_X
+(ARG_RD
),CLASS_IMM
+(ARG_IMM8
),},
842 {CLASS_BIT
+4,CLASS_BIT
+0xc,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+1,CLASS_ADDRESS
+(ARG_DST
),CLASS_IMM
+(ARG_IMM8
),CLASS_IMM
+(ARG_IMM8
),0,0,},2,6,19},
844 /* 0100 1100 0000 0001 address_dst imm8 imm8 *** cpb address_dst,imm8 */
847 "cpb address_dst,imm8",8,14,0x3c,
849 "cpb",OPC_cpb
,0,{CLASS_DA
+(ARG_DST
),CLASS_IMM
+(ARG_IMM8
),},
850 {CLASS_BIT
+4,CLASS_BIT
+0xc,CLASS_BIT
+0,CLASS_BIT
+1,CLASS_ADDRESS
+(ARG_DST
),CLASS_IMM
+(ARG_IMM8
),CLASS_IMM
+(ARG_IMM8
),0,0,},2,6,19},
852 /* 0000 1010 ssN0 dddd *** cpb rbd,@rs */
855 "cpb rbd,@rs",8,7,0x3c,
857 "cpb",OPC_cpb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
858 {CLASS_BIT
+0,CLASS_BIT
+0xa,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,19},
860 /* 0100 1010 0000 dddd address_src *** cpb rbd,address_src */
863 "cpb rbd,address_src",8,9,0x3c,
865 "cpb",OPC_cpb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_DA
+(ARG_SRC
),},
866 {CLASS_BIT
+4,CLASS_BIT
+0xa,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,19},
868 /* 0100 1010 ssN0 dddd address_src *** cpb rbd,address_src(rs) */
871 "cpb rbd,address_src(rs)",8,10,0x3c,
873 "cpb",OPC_cpb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_X
+(ARG_RS
),},
874 {CLASS_BIT
+4,CLASS_BIT
+0xa,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,19},
876 /* 0000 1010 0000 dddd imm8 imm8 *** cpb rbd,imm8 */
879 "cpb rbd,imm8",8,7,0x3c,
881 "cpb",OPC_cpb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IMM
+(ARG_IMM8
),},
882 {CLASS_BIT
+0,CLASS_BIT
+0xa,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM8
),CLASS_IMM
+(ARG_IMM8
),0,0,0,},2,4,19},
884 /* 1000 1010 ssss dddd *** cpb rbd,rbs */
887 "cpb rbd,rbs",8,4,0x3c,
889 "cpb",OPC_cpb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_REG_BYTE
+(ARG_RS
),},
890 {CLASS_BIT
+8,CLASS_BIT
+0xa,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,19},
892 /* 1011 1011 ssN0 1000 0000 rrrr dddd cccc *** cpd rd,@rs,rr,cc */
895 "cpd rd,@rs,rr,cc",16,11,0x3c,
897 "cpd",OPC_cpd
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RR
),CLASS_CC
,},
898 {CLASS_BIT
+0xb,CLASS_BIT
+0xb,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+8,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REG
+(ARG_RD
),CLASS_CC
,0,},4,4,20},
900 /* 1011 1010 ssN0 1000 0000 rrrr dddd cccc *** cpdb rbd,@rs,rr,cc */
903 "cpdb rbd,@rs,rr,cc",8,11,0x3c,
905 "cpdb",OPC_cpdb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RR
),CLASS_CC
,},
906 {CLASS_BIT
+0xb,CLASS_BIT
+0xa,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+8,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REG
+(ARG_RD
),CLASS_CC
,0,},4,4,21},
908 /* 1011 1011 ssN0 1100 0000 rrrr dddd cccc *** cpdr rd,@rs,rr,cc */
911 "cpdr rd,@rs,rr,cc",16,11,0x3c,
913 "cpdr",OPC_cpdr
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RR
),CLASS_CC
,},
914 {CLASS_BIT
+0xb,CLASS_BIT
+0xb,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+0xc,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REG
+(ARG_RD
),CLASS_CC
,0,},4,4,22},
916 /* 1011 1010 ssN0 1100 0000 rrrr dddd cccc *** cpdrb rbd,@rs,rr,cc */
919 "cpdrb rbd,@rs,rr,cc",8,11,0x3c,
921 "cpdrb",OPC_cpdrb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RR
),CLASS_CC
,},
922 {CLASS_BIT
+0xb,CLASS_BIT
+0xa,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+0xc,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REG
+(ARG_RD
),CLASS_CC
,0,},4,4,23},
924 /* 1011 1011 ssN0 0000 0000 rrrr dddd cccc *** cpi rd,@rs,rr,cc */
927 "cpi rd,@rs,rr,cc",16,11,0x3c,
929 "cpi",OPC_cpi
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RR
),CLASS_CC
,},
930 {CLASS_BIT
+0xb,CLASS_BIT
+0xb,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+0,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REG
+(ARG_RD
),CLASS_CC
,0,},4,4,24},
932 /* 1011 1010 ssN0 0000 0000 rrrr dddd cccc *** cpib rbd,@rs,rr,cc */
935 "cpib rbd,@rs,rr,cc",8,11,0x3c,
937 "cpib",OPC_cpib
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RR
),CLASS_CC
,},
938 {CLASS_BIT
+0xb,CLASS_BIT
+0xa,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+0,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REG
+(ARG_RD
),CLASS_CC
,0,},4,4,25},
940 /* 1011 1011 ssN0 0100 0000 rrrr dddd cccc *** cpir rd,@rs,rr,cc */
943 "cpir rd,@rs,rr,cc",16,11,0x3c,
945 "cpir",OPC_cpir
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RR
),CLASS_CC
,},
946 {CLASS_BIT
+0xb,CLASS_BIT
+0xb,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+4,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REG
+(ARG_RD
),CLASS_CC
,0,},4,4,26},
948 /* 1011 1010 ssN0 0100 0000 rrrr dddd cccc *** cpirb rbd,@rs,rr,cc */
951 "cpirb rbd,@rs,rr,cc",8,11,0x3c,
953 "cpirb",OPC_cpirb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RR
),CLASS_CC
,},
954 {CLASS_BIT
+0xb,CLASS_BIT
+0xa,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+4,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REG
+(ARG_RD
),CLASS_CC
,0,},4,4,27},
956 /* 0001 0000 ssN0 dddd *** cpl rrd,@rs */
959 "cpl rrd,@rs",32,14,0x3c,
961 "cpl",OPC_cpl
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
962 {CLASS_BIT
+1,CLASS_BIT
+0,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,28},
964 /* 0101 0000 0000 dddd address_src *** cpl rrd,address_src */
967 "cpl rrd,address_src",32,15,0x3c,
969 "cpl",OPC_cpl
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_DA
+(ARG_SRC
),},
970 {CLASS_BIT
+5,CLASS_BIT
+0,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,28},
972 /* 0101 0000 ssN0 dddd address_src *** cpl rrd,address_src(rs) */
975 "cpl rrd,address_src(rs)",32,16,0x3c,
977 "cpl",OPC_cpl
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_X
+(ARG_RS
),},
978 {CLASS_BIT
+5,CLASS_BIT
+0,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,28},
980 /* 0001 0000 0000 dddd imm32 *** cpl rrd,imm32 */
983 "cpl rrd,imm32",32,14,0x3c,
985 "cpl",OPC_cpl
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM32
),},
986 {CLASS_BIT
+1,CLASS_BIT
+0,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM32
),0,0,0,0,},2,6,28},
988 /* 1001 0000 ssss dddd *** cpl rrd,rrs */
991 "cpl rrd,rrs",32,8,0x3c,
993 "cpl",OPC_cpl
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_REG_LONG
+(ARG_RS
),},
994 {CLASS_BIT
+9,CLASS_BIT
+0,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,28},
996 /* 1011 1011 ssN0 1010 0000 rrrr ddN0 cccc *** cpsd @rd,@rs,rr,cc */
999 "cpsd @rd,@rs,rr,cc",16,11,0x3c,
1001 "cpsd",OPC_cpsd
,0,{CLASS_IR
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RR
),CLASS_CC
,},
1002 {CLASS_BIT
+0xb,CLASS_BIT
+0xb,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+0xa,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REGN0
+(ARG_RD
),CLASS_CC
,0,},4,4,29},
1004 /* 1011 1010 ssN0 1010 0000 rrrr ddN0 cccc *** cpsdb @rd,@rs,rr,cc */
1007 "cpsdb @rd,@rs,rr,cc",8,11,0x3c,
1009 "cpsdb",OPC_cpsdb
,0,{CLASS_IR
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RR
),CLASS_CC
,},
1010 {CLASS_BIT
+0xb,CLASS_BIT
+0xa,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+0xa,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REGN0
+(ARG_RD
),CLASS_CC
,0,},4,4,30},
1012 /* 1011 1011 ssN0 1110 0000 rrrr ddN0 cccc *** cpsdr @rd,@rs,rr,cc */
1015 "cpsdr @rd,@rs,rr,cc",16,11,0x3c,
1017 "cpsdr",OPC_cpsdr
,0,{CLASS_IR
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RR
),CLASS_CC
,},
1018 {CLASS_BIT
+0xb,CLASS_BIT
+0xb,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+0xe,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REGN0
+(ARG_RD
),CLASS_CC
,0,},4,4,31},
1020 /* 1011 1010 ssN0 1110 0000 rrrr ddN0 cccc *** cpsdrb @rd,@rs,rr,cc */
1023 "cpsdrb @rd,@rs,rr,cc",8,11,0x3c,
1025 "cpsdrb",OPC_cpsdrb
,0,{CLASS_IR
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RR
),CLASS_CC
,},
1026 {CLASS_BIT
+0xb,CLASS_BIT
+0xa,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+0xe,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REGN0
+(ARG_RD
),CLASS_CC
,0,},4,4,32},
1028 /* 1011 1011 ssN0 0010 0000 rrrr ddN0 cccc *** cpsi @rd,@rs,rr,cc */
1031 "cpsi @rd,@rs,rr,cc",16,11,0x3c,
1033 "cpsi",OPC_cpsi
,0,{CLASS_IR
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RR
),CLASS_CC
,},
1034 {CLASS_BIT
+0xb,CLASS_BIT
+0xb,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+2,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REGN0
+(ARG_RD
),CLASS_CC
,0,},4,4,33},
1036 /* 1011 1010 ssN0 0010 0000 rrrr ddN0 cccc *** cpsib @rd,@rs,rr,cc */
1039 "cpsib @rd,@rs,rr,cc",8,11,0x3c,
1041 "cpsib",OPC_cpsib
,0,{CLASS_IR
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RR
),CLASS_CC
,},
1042 {CLASS_BIT
+0xb,CLASS_BIT
+0xa,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+2,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REGN0
+(ARG_RD
),CLASS_CC
,0,},4,4,34},
1044 /* 1011 1011 ssN0 0110 0000 rrrr ddN0 cccc *** cpsir @rd,@rs,rr,cc */
1047 "cpsir @rd,@rs,rr,cc",16,11,0x3c,
1049 "cpsir",OPC_cpsir
,0,{CLASS_IR
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RR
),CLASS_CC
,},
1050 {CLASS_BIT
+0xb,CLASS_BIT
+0xb,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+6,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REGN0
+(ARG_RD
),CLASS_CC
,0,},4,4,35},
1052 /* 1011 1010 ssN0 0110 0000 rrrr ddN0 cccc *** cpsirb @rd,@rs,rr,cc */
1055 "cpsirb @rd,@rs,rr,cc",8,11,0x3c,
1057 "cpsirb",OPC_cpsirb
,0,{CLASS_IR
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RR
),CLASS_CC
,},
1058 {CLASS_BIT
+0xb,CLASS_BIT
+0xa,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+6,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REGN0
+(ARG_RD
),CLASS_CC
,0,},4,4,36},
1060 /* 1011 0000 dddd 0000 *** dab rbd */
1065 "dab",OPC_dab
,0,{CLASS_REG_BYTE
+(ARG_RD
),},
1066 {CLASS_BIT
+0xb,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_BIT
+0,0,0,0,0,0,},1,2,37},
1068 /* 1111 dddd 0disp7 *** dbjnz rbd,disp7 */
1071 "dbjnz rbd,disp7",16,11,0x00,
1073 "dbjnz",OPC_dbjnz
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_DISP
,},
1074 {CLASS_BIT
+0xf,CLASS_REG
+(ARG_RD
),CLASS_0DISP7
,0,0,0,0,0,0,},2,2,38},
1076 /* 0010 1011 ddN0 imm4m1 *** dec @rd,imm4m1 */
1079 "dec @rd,imm4m1",16,11,0x1c,
1081 "dec",OPC_dec
,0,{CLASS_IR
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4M1
),},
1082 {CLASS_BIT
+2,CLASS_BIT
+0xb,CLASS_REGN0
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4M1
),0,0,0,0,0,},2,2,39},
1084 /* 0110 1011 ddN0 imm4m1 address_dst *** dec address_dst(rd),imm4m1 */
1087 "dec address_dst(rd),imm4m1",16,14,0x1c,
1089 "dec",OPC_dec
,0,{CLASS_X
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4M1
),},
1090 {CLASS_BIT
+6,CLASS_BIT
+0xb,CLASS_REGN0
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4M1
),CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,39},
1092 /* 0110 1011 0000 imm4m1 address_dst *** dec address_dst,imm4m1 */
1095 "dec address_dst,imm4m1",16,13,0x1c,
1097 "dec",OPC_dec
,0,{CLASS_DA
+(ARG_DST
),CLASS_IMM
+(ARG_IMM4M1
),},
1098 {CLASS_BIT
+6,CLASS_BIT
+0xb,CLASS_BIT
+0,CLASS_IMM
+(ARG_IMM4M1
),CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,39},
1100 /* 1010 1011 dddd imm4m1 *** dec rd,imm4m1 */
1103 "dec rd,imm4m1",16,4,0x1c,
1105 "dec",OPC_dec
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4M1
),},
1106 {CLASS_BIT
+0xa,CLASS_BIT
+0xb,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4M1
),0,0,0,0,0,},2,2,39},
1108 /* 0010 1010 ddN0 imm4m1 *** decb @rd,imm4m1 */
1111 "decb @rd,imm4m1",8,11,0x1c,
1113 "decb",OPC_decb
,0,{CLASS_IR
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4M1
),},
1114 {CLASS_BIT
+2,CLASS_BIT
+0xa,CLASS_REGN0
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4M1
),0,0,0,0,0,},2,2,40},
1116 /* 0110 1010 ddN0 imm4m1 address_dst *** decb address_dst(rd),imm4m1 */
1119 "decb address_dst(rd),imm4m1",8,14,0x1c,
1121 "decb",OPC_decb
,0,{CLASS_X
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4M1
),},
1122 {CLASS_BIT
+6,CLASS_BIT
+0xa,CLASS_REGN0
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4M1
),CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,40},
1124 /* 0110 1010 0000 imm4m1 address_dst *** decb address_dst,imm4m1 */
1127 "decb address_dst,imm4m1",8,13,0x1c,
1129 "decb",OPC_decb
,0,{CLASS_DA
+(ARG_DST
),CLASS_IMM
+(ARG_IMM4M1
),},
1130 {CLASS_BIT
+6,CLASS_BIT
+0xa,CLASS_BIT
+0,CLASS_IMM
+(ARG_IMM4M1
),CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,40},
1132 /* 1010 1010 dddd imm4m1 *** decb rbd,imm4m1 */
1135 "decb rbd,imm4m1",8,4,0x1c,
1137 "decb",OPC_decb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4M1
),},
1138 {CLASS_BIT
+0xa,CLASS_BIT
+0xa,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4M1
),0,0,0,0,0,},2,2,40},
1140 /* 0111 1100 0000 00ii *** di i2 */
1145 "di",OPC_di
,0,{CLASS_IMM
+(ARG_IMM2
),},
1146 {CLASS_BIT
+7,CLASS_BIT
+0xc,CLASS_BIT
+0,CLASS_00II
,0,0,0,0,0,},1,2,41},
1148 /* 0001 1011 ssN0 dddd *** div rrd,@rs */
1151 "div rrd,@rs",16,107,0x3c,
1153 "div",OPC_div
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
1154 {CLASS_BIT
+1,CLASS_BIT
+0xb,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,42},
1156 /* 0101 1011 0000 dddd address_src *** div rrd,address_src */
1159 "div rrd,address_src",16,107,0x3c,
1161 "div",OPC_div
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_DA
+(ARG_SRC
),},
1162 {CLASS_BIT
+5,CLASS_BIT
+0xb,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,42},
1164 /* 0101 1011 ssN0 dddd address_src *** div rrd,address_src(rs) */
1167 "div rrd,address_src(rs)",16,107,0x3c,
1169 "div",OPC_div
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_X
+(ARG_RS
),},
1170 {CLASS_BIT
+5,CLASS_BIT
+0xb,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,42},
1172 /* 0001 1011 0000 dddd imm16 *** div rrd,imm16 */
1175 "div rrd,imm16",16,107,0x3c,
1177 "div",OPC_div
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),},
1178 {CLASS_BIT
+1,CLASS_BIT
+0xb,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),0,0,0,0,},2,4,42},
1180 /* 1001 1011 ssss dddd *** div rrd,rs */
1183 "div rrd,rs",16,107,0x3c,
1185 "div",OPC_div
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
1186 {CLASS_BIT
+9,CLASS_BIT
+0xb,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,42},
1188 /* 0001 1010 ssN0 dddd *** divl rqd,@rs */
1191 "divl rqd,@rs",32,744,0x3c,
1193 "divl",OPC_divl
,0,{CLASS_REG_QUAD
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
1194 {CLASS_BIT
+1,CLASS_BIT
+0xa,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,43},
1196 /* 0101 1010 0000 dddd address_src *** divl rqd,address_src */
1199 "divl rqd,address_src",32,745,0x3c,
1201 "divl",OPC_divl
,0,{CLASS_REG_QUAD
+(ARG_RD
),CLASS_DA
+(ARG_SRC
),},
1202 {CLASS_BIT
+5,CLASS_BIT
+0xa,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,43},
1204 /* 0101 1010 ssN0 dddd address_src *** divl rqd,address_src(rs) */
1207 "divl rqd,address_src(rs)",32,746,0x3c,
1209 "divl",OPC_divl
,0,{CLASS_REG_QUAD
+(ARG_RD
),CLASS_X
+(ARG_RS
),},
1210 {CLASS_BIT
+5,CLASS_BIT
+0xa,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,43},
1212 /* 0001 1010 0000 dddd imm32 *** divl rqd,imm32 */
1215 "divl rqd,imm32",32,744,0x3c,
1217 "divl",OPC_divl
,0,{CLASS_REG_QUAD
+(ARG_RD
),CLASS_IMM
+(ARG_IMM32
),},
1218 {CLASS_BIT
+1,CLASS_BIT
+0xa,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM32
),0,0,0,0,},2,6,43},
1220 /* 1001 1010 ssss dddd *** divl rqd,rrs */
1223 "divl rqd,rrs",32,744,0x3c,
1225 "divl",OPC_divl
,0,{CLASS_REG_QUAD
+(ARG_RD
),CLASS_REG_LONG
+(ARG_RS
),},
1226 {CLASS_BIT
+9,CLASS_BIT
+0xa,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,43},
1228 /* 1111 dddd 1disp7 *** djnz rd,disp7 */
1231 "djnz rd,disp7",16,11,0x00,
1233 "djnz",OPC_djnz
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_DISP
,},
1234 {CLASS_BIT
+0xf,CLASS_REG
+(ARG_RD
),CLASS_1DISP7
,0,0,0,0,0,0,},2,2,44},
1236 /* 0111 1100 0000 01ii *** ei i2 */
1241 "ei",OPC_ei
,0,{CLASS_IMM
+(ARG_IMM2
),},
1242 {CLASS_BIT
+7,CLASS_BIT
+0xc,CLASS_BIT
+0,CLASS_01II
,0,0,0,0,0,},1,2,45},
1244 /* 0010 1101 ssN0 dddd *** ex rd,@rs */
1247 "ex rd,@rs",16,12,0x00,
1249 "ex",OPC_ex
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
1250 {CLASS_BIT
+2,CLASS_BIT
+0xd,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,46},
1252 /* 0110 1101 0000 dddd address_src *** ex rd,address_src */
1255 "ex rd,address_src",16,15,0x00,
1257 "ex",OPC_ex
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_DA
+(ARG_SRC
),},
1258 {CLASS_BIT
+6,CLASS_BIT
+0xd,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,46},
1260 /* 0110 1101 ssN0 dddd address_src *** ex rd,address_src(rs) */
1263 "ex rd,address_src(rs)",16,16,0x00,
1265 "ex",OPC_ex
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_X
+(ARG_RS
),},
1266 {CLASS_BIT
+6,CLASS_BIT
+0xd,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,46},
1268 /* 1010 1101 ssss dddd *** ex rd,rs */
1271 "ex rd,rs",16,6,0x00,
1273 "ex",OPC_ex
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
1274 {CLASS_BIT
+0xa,CLASS_BIT
+0xd,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,46},
1276 /* 0010 1100 ssN0 dddd *** exb rbd,@rs */
1279 "exb rbd,@rs",8,12,0x00,
1281 "exb",OPC_exb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
1282 {CLASS_BIT
+2,CLASS_BIT
+0xc,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,47},
1284 /* 0110 1100 0000 dddd address_src *** exb rbd,address_src */
1287 "exb rbd,address_src",8,15,0x00,
1289 "exb",OPC_exb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_DA
+(ARG_SRC
),},
1290 {CLASS_BIT
+6,CLASS_BIT
+0xc,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,47},
1292 /* 0110 1100 ssN0 dddd address_src *** exb rbd,address_src(rs) */
1295 "exb rbd,address_src(rs)",8,16,0x00,
1297 "exb",OPC_exb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_X
+(ARG_RS
),},
1298 {CLASS_BIT
+6,CLASS_BIT
+0xc,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,47},
1300 /* 1010 1100 ssss dddd *** exb rbd,rbs */
1303 "exb rbd,rbs",8,6,0x00,
1305 "exb",OPC_exb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_REG_BYTE
+(ARG_RS
),},
1306 {CLASS_BIT
+0xa,CLASS_BIT
+0xc,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,47},
1308 /* 0000 1110 imm8 *** ext0e imm8 */
1311 "ext0e imm8",8,10,0x00,
1313 "ext0e",OPC_ext0e
,0,{CLASS_IMM
+(ARG_IMM8
),},
1314 {CLASS_BIT
+0,CLASS_BIT
+0xe,CLASS_IMM
+(ARG_IMM8
),0,0,0,0,0,0,},1,2,48},
1316 /* 0000 1111 imm8 *** ext0f imm8 */
1319 "ext0f imm8",8,10,0x00,
1321 "ext0f",OPC_ext0f
,0,{CLASS_IMM
+(ARG_IMM8
),},
1322 {CLASS_BIT
+0,CLASS_BIT
+0xf,CLASS_IMM
+(ARG_IMM8
),0,0,0,0,0,0,},1,2,49},
1324 /* 1000 1110 imm8 *** ext8e imm8 */
1327 "ext8e imm8",8,10,0x00,
1329 "ext8e",OPC_ext8e
,0,{CLASS_IMM
+(ARG_IMM8
),},
1330 {CLASS_BIT
+8,CLASS_BIT
+0xe,CLASS_IMM
+(ARG_IMM8
),0,0,0,0,0,0,},1,2,50},
1332 /* 1000 1111 imm8 *** ext8f imm8 */
1335 "ext8f imm8",8,10,0x00,
1337 "ext8f",OPC_ext8f
,0,{CLASS_IMM
+(ARG_IMM8
),},
1338 {CLASS_BIT
+8,CLASS_BIT
+0xf,CLASS_IMM
+(ARG_IMM8
),0,0,0,0,0,0,},1,2,51},
1340 /* 1011 0001 dddd 1010 *** exts rrd */
1343 "exts rrd",16,11,0x00,
1345 "exts",OPC_exts
,0,{CLASS_REG_LONG
+(ARG_RD
),},
1346 {CLASS_BIT
+0xb,CLASS_BIT
+1,CLASS_REG
+(ARG_RD
),CLASS_BIT
+0xa,0,0,0,0,0,},1,2,52},
1348 /* 1011 0001 dddd 0000 *** extsb rd */
1351 "extsb rd",8,11,0x00,
1353 "extsb",OPC_extsb
,0,{CLASS_REG_WORD
+(ARG_RD
),},
1354 {CLASS_BIT
+0xb,CLASS_BIT
+1,CLASS_REG
+(ARG_RD
),CLASS_BIT
+0,0,0,0,0,0,},1,2,53},
1356 /* 1011 0001 dddd 0111 *** extsl rqd */
1359 "extsl rqd",32,11,0x00,
1361 "extsl",OPC_extsl
,0,{CLASS_REG_QUAD
+(ARG_RD
),},
1362 {CLASS_BIT
+0xb,CLASS_BIT
+1,CLASS_REG
+(ARG_RD
),CLASS_BIT
+7,0,0,0,0,0,},1,2,54},
1364 /* 0111 1010 0000 0000 *** halt */
1369 "halt",OPC_halt
,0,{0},
1370 {CLASS_BIT
+7,CLASS_BIT
+0xa,CLASS_BIT
+0,CLASS_BIT
+0,0,0,0,0,0,},0,2,55},
1372 /* 0011 1101 ssss dddd *** in rd,@ri */
1375 "in rd,@ri",16,10,0x00,
1377 "in",OPC_in
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IRO
+(ARG_RS
),},
1378 {CLASS_BIT
+3,CLASS_BIT
+0xd,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,56},
1380 /* 0011 1011 dddd 0100 imm16 *** in rd,imm16 */
1383 "in rd,imm16",16,12,0x00,
1385 "in",OPC_in
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),},
1386 {CLASS_BIT
+3,CLASS_BIT
+0xb,CLASS_REG
+(ARG_RD
),CLASS_BIT
+4,CLASS_IMM
+(ARG_IMM16
),0,0,0,0,},2,4,56},
1388 /* 0011 1100 ssss dddd *** inb rbd,@ri */
1391 "inb rbd,@ri",8,12,0x00,
1393 "inb",OPC_inb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IRO
+(ARG_RS
),},
1394 {CLASS_BIT
+3,CLASS_BIT
+0xc,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,57},
1396 /* 0011 1010 dddd 0100 imm16 *** inb rbd,imm16 */
1399 "inb rbd,imm16",8,10,0x00,
1401 "inb",OPC_inb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),},
1402 {CLASS_BIT
+3,CLASS_BIT
+0xa,CLASS_REG
+(ARG_RD
),CLASS_BIT
+4,CLASS_IMM
+(ARG_IMM16
),0,0,0,0,},2,4,57},
1404 /* 0010 1001 ddN0 imm4m1 *** inc @rd,imm4m1 */
1407 "inc @rd,imm4m1",16,11,0x1c,
1409 "inc",OPC_inc
,0,{CLASS_IR
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4M1
),},
1410 {CLASS_BIT
+2,CLASS_BIT
+9,CLASS_REGN0
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4M1
),0,0,0,0,0,},2,2,58},
1412 /* 0110 1001 ddN0 imm4m1 address_dst *** inc address_dst(rd),imm4m1 */
1415 "inc address_dst(rd),imm4m1",16,14,0x1c,
1417 "inc",OPC_inc
,0,{CLASS_X
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4M1
),},
1418 {CLASS_BIT
+6,CLASS_BIT
+9,CLASS_REGN0
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4M1
),CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,58},
1420 /* 0110 1001 0000 imm4m1 address_dst *** inc address_dst,imm4m1 */
1423 "inc address_dst,imm4m1",16,13,0x1c,
1425 "inc",OPC_inc
,0,{CLASS_DA
+(ARG_DST
),CLASS_IMM
+(ARG_IMM4M1
),},
1426 {CLASS_BIT
+6,CLASS_BIT
+9,CLASS_BIT
+0,CLASS_IMM
+(ARG_IMM4M1
),CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,58},
1428 /* 1010 1001 dddd imm4m1 *** inc rd,imm4m1 */
1431 "inc rd,imm4m1",16,4,0x1c,
1433 "inc",OPC_inc
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4M1
),},
1434 {CLASS_BIT
+0xa,CLASS_BIT
+9,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4M1
),0,0,0,0,0,},2,2,58},
1436 /* 0010 1000 ddN0 imm4m1 *** incb @rd,imm4m1 */
1439 "incb @rd,imm4m1",8,11,0x1c,
1441 "incb",OPC_incb
,0,{CLASS_IR
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4M1
),},
1442 {CLASS_BIT
+2,CLASS_BIT
+8,CLASS_REGN0
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4M1
),0,0,0,0,0,},2,2,59},
1444 /* 0110 1000 ddN0 imm4m1 address_dst *** incb address_dst(rd),imm4m1 */
1447 "incb address_dst(rd),imm4m1",8,14,0x1c,
1449 "incb",OPC_incb
,0,{CLASS_X
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4M1
),},
1450 {CLASS_BIT
+6,CLASS_BIT
+8,CLASS_REGN0
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4M1
),CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,59},
1452 /* 0110 1000 0000 imm4m1 address_dst *** incb address_dst,imm4m1 */
1455 "incb address_dst,imm4m1",8,13,0x1c,
1457 "incb",OPC_incb
,0,{CLASS_DA
+(ARG_DST
),CLASS_IMM
+(ARG_IMM4M1
),},
1458 {CLASS_BIT
+6,CLASS_BIT
+8,CLASS_BIT
+0,CLASS_IMM
+(ARG_IMM4M1
),CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,59},
1460 /* 1010 1000 dddd imm4m1 *** incb rbd,imm4m1 */
1463 "incb rbd,imm4m1",8,4,0x1c,
1465 "incb",OPC_incb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4M1
),},
1466 {CLASS_BIT
+0xa,CLASS_BIT
+8,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4M1
),0,0,0,0,0,},2,2,59},
1468 /* 0011 1011 ssss 1000 0000 aaaa ddN0 1000 *** ind @rd,@ri,ra */
1471 "ind @rd,@ri,ra",16,21,0x04,
1473 "ind",OPC_ind
,0,{CLASS_IR
+(ARG_RD
),CLASS_IRO
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
1474 {CLASS_BIT
+3,CLASS_BIT
+0xb,CLASS_REG
+(ARG_RS
),CLASS_BIT
+8,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+8,0,},3,4,60},
1476 /* 0011 1010 ssss 1000 0000 aaaa ddN0 1000 *** indb @rd,@ri,ra */
1479 "indb @rd,@ri,ra",8,21,0x04,
1481 "indb",OPC_indb
,0,{CLASS_IR
+(ARG_RD
),CLASS_IRO
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
1482 {CLASS_BIT
+3,CLASS_BIT
+0xa,CLASS_REG
+(ARG_RS
),CLASS_BIT
+8,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+8,0,},3,4,61},
1484 /* 0011 1011 ssss 1000 0000 aaaa ddN0 0000 *** indr @rd,@ri,ra */
1487 "indr @rd,@ri,ra",16,11,0x04,
1489 "indr",OPC_indr
,0,{CLASS_IR
+(ARG_RD
),CLASS_IRO
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
1490 {CLASS_BIT
+3,CLASS_BIT
+0xb,CLASS_REG
+(ARG_RS
),CLASS_BIT
+8,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+0,0,},3,4,62},
1492 /* 0011 1010 ssss 1000 0000 aaaa ddN0 0000 *** indrb @rd,@ri,ra */
1495 "indrb @rd,@ri,ra",8,11,0x04,
1497 "indrb",OPC_indrb
,0,{CLASS_IR
+(ARG_RD
),CLASS_IRO
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
1498 {CLASS_BIT
+3,CLASS_BIT
+0xa,CLASS_REG
+(ARG_RS
),CLASS_BIT
+8,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+0,0,},3,4,63},
1500 /* 0011 1011 ssss 0000 0000 aaaa ddN0 1000 *** ini @rd,@ri,ra */
1503 "ini @rd,@ri,ra",16,21,0x04,
1505 "ini",OPC_ini
,0,{CLASS_IR
+(ARG_RD
),CLASS_IRO
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
1506 {CLASS_BIT
+3,CLASS_BIT
+0xb,CLASS_REG
+(ARG_RS
),CLASS_BIT
+0,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+8,0,},3,4,64},
1508 /* 0011 1010 ssss 0000 0000 aaaa ddN0 1000 *** inib @rd,@ri,ra */
1511 "inib @rd,@ri,ra",8,21,0x04,
1513 "inib",OPC_inib
,0,{CLASS_IR
+(ARG_RD
),CLASS_IRO
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
1514 {CLASS_BIT
+3,CLASS_BIT
+0xa,CLASS_REG
+(ARG_RS
),CLASS_BIT
+0,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+8,0,},3,4,65},
1516 /* 0011 1011 ssss 0000 0000 aaaa ddN0 0000 *** inir @rd,@ri,ra */
1519 "inir @rd,@ri,ra",16,11,0x04,
1521 "inir",OPC_inir
,0,{CLASS_IR
+(ARG_RD
),CLASS_IRO
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
1522 {CLASS_BIT
+3,CLASS_BIT
+0xb,CLASS_REG
+(ARG_RS
),CLASS_BIT
+0,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+0,0,},3,4,66},
1524 /* 0011 1010 ssss 0000 0000 aaaa ddN0 0000 *** inirb @rd,@ri,ra */
1527 "inirb @rd,@ri,ra",8,11,0x04,
1529 "inirb",OPC_inirb
,0,{CLASS_IR
+(ARG_RD
),CLASS_IRO
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
1530 {CLASS_BIT
+3,CLASS_BIT
+0xa,CLASS_REG
+(ARG_RS
),CLASS_BIT
+0,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+0,0,},3,4,67},
1532 /* 0111 1011 0000 0000 *** iret */
1537 "iret",OPC_iret
,0,{0},
1538 {CLASS_BIT
+7,CLASS_BIT
+0xb,CLASS_BIT
+0,CLASS_BIT
+0,0,0,0,0,0,},0,2,68},
1540 /* 0001 1110 ddN0 cccc *** jp cc,@rd */
1543 "jp cc,@rd",16,10,0x00,
1545 "jp",OPC_jp
,0,{CLASS_CC
,CLASS_IR
+(ARG_RD
),},
1546 {CLASS_BIT
+1,CLASS_BIT
+0xe,CLASS_REGN0
+(ARG_RD
),CLASS_CC
,0,0,0,0,0,},2,2,69},
1548 /* 0101 1110 0000 cccc address_dst *** jp cc,address_dst */
1551 "jp cc,address_dst",16,7,0x00,
1553 "jp",OPC_jp
,0,{CLASS_CC
,CLASS_DA
+(ARG_DST
),},
1554 {CLASS_BIT
+5,CLASS_BIT
+0xe,CLASS_BIT
+0,CLASS_CC
,CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,69},
1556 /* 0101 1110 ddN0 cccc address_dst *** jp cc,address_dst(rd) */
1559 "jp cc,address_dst(rd)",16,8,0x00,
1561 "jp",OPC_jp
,0,{CLASS_CC
,CLASS_X
+(ARG_RD
),},
1562 {CLASS_BIT
+5,CLASS_BIT
+0xe,CLASS_REGN0
+(ARG_RD
),CLASS_CC
,CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,69},
1564 /* 1110 cccc disp8 *** jr cc,disp8 */
1567 "jr cc,disp8",16,6,0x00,
1569 "jr",OPC_jr
,0,{CLASS_CC
,CLASS_DISP
,},
1570 {CLASS_BIT
+0xe,CLASS_CC
,CLASS_DISP8
,0,0,0,0,0,0,},2,2,70},
1572 /* 0000 1101 ddN0 0101 imm16 *** ld @rd,imm16 */
1575 "ld @rd,imm16",16,7,0x00,
1577 "ld",OPC_ld
,0,{CLASS_IR
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),},
1578 {CLASS_BIT
+0,CLASS_BIT
+0xd,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+5,CLASS_IMM
+(ARG_IMM16
),0,0,0,0,},2,4,71},
1580 /* 0010 1111 ddN0 ssss *** ld @rd,rs */
1583 "ld @rd,rs",16,8,0x00,
1585 "ld",OPC_ld
,0,{CLASS_IR
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
1586 {CLASS_BIT
+2,CLASS_BIT
+0xf,CLASS_REGN0
+(ARG_RD
),CLASS_REG
+(ARG_RS
),0,0,0,0,0,},2,2,71},
1588 /* 0100 1101 ddN0 0101 address_dst imm16 *** ld address_dst(rd),imm16 */
1591 "ld address_dst(rd),imm16",16,15,0x00,
1593 "ld",OPC_ld
,0,{CLASS_X
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),},
1594 {CLASS_BIT
+4,CLASS_BIT
+0xd,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+5,CLASS_ADDRESS
+(ARG_DST
),CLASS_IMM
+(ARG_IMM16
),0,0,0,},2,6,71},
1596 /* 0110 1111 ddN0 ssss address_dst *** ld address_dst(rd),rs */
1599 "ld address_dst(rd),rs",16,12,0x00,
1601 "ld",OPC_ld
,0,{CLASS_X
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
1602 {CLASS_BIT
+6,CLASS_BIT
+0xf,CLASS_REGN0
+(ARG_RD
),CLASS_REG
+(ARG_RS
),CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,71},
1604 /* 0100 1101 0000 0101 address_dst imm16 *** ld address_dst,imm16 */
1607 "ld address_dst,imm16",16,14,0x00,
1609 "ld",OPC_ld
,0,{CLASS_DA
+(ARG_DST
),CLASS_IMM
+(ARG_IMM16
),},
1610 {CLASS_BIT
+4,CLASS_BIT
+0xd,CLASS_BIT
+0,CLASS_BIT
+5,CLASS_ADDRESS
+(ARG_DST
),CLASS_IMM
+(ARG_IMM16
),0,0,0,},2,6,71},
1612 /* 0110 1111 0000 ssss address_dst *** ld address_dst,rs */
1615 "ld address_dst,rs",16,11,0x00,
1617 "ld",OPC_ld
,0,{CLASS_DA
+(ARG_DST
),CLASS_REG_WORD
+(ARG_RS
),},
1618 {CLASS_BIT
+6,CLASS_BIT
+0xf,CLASS_BIT
+0,CLASS_REG
+(ARG_RS
),CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,71},
1620 /* 0011 0011 ddN0 ssss imm16 *** ld rd(imm16),rs */
1623 "ld rd(imm16),rs",16,14,0x00,
1625 "ld",OPC_ld
,0,{CLASS_BA
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
1626 {CLASS_BIT
+3,CLASS_BIT
+3,CLASS_REGN0
+(ARG_RD
),CLASS_REG
+(ARG_RS
),CLASS_IMM
+(ARG_IMM16
),0,0,0,0,},2,4,71},
1628 /* 0111 0011 ddN0 ssss 0000 xxxx 0000 0000 *** ld rd(rx),rs */
1631 "ld rd(rx),rs",16,14,0x00,
1633 "ld",OPC_ld
,0,{CLASS_BX
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
1634 {CLASS_BIT
+7,CLASS_BIT
+3,CLASS_REGN0
+(ARG_RD
),CLASS_REG
+(ARG_RS
),CLASS_BIT
+0,CLASS_REG
+(ARG_RX
),CLASS_BIT
+0,CLASS_BIT
+0,0,},2,4,71},
1636 /* 0010 0001 ssN0 dddd *** ld rd,@rs */
1639 "ld rd,@rs",16,7,0x00,
1641 "ld",OPC_ld
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
1642 {CLASS_BIT
+2,CLASS_BIT
+1,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,71},
1644 /* 0110 0001 0000 dddd address_src *** ld rd,address_src */
1647 "ld rd,address_src",16,9,0x00,
1649 "ld",OPC_ld
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_DA
+(ARG_SRC
),},
1650 {CLASS_BIT
+6,CLASS_BIT
+1,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,71},
1652 /* 0110 0001 ssN0 dddd address_src *** ld rd,address_src(rs) */
1655 "ld rd,address_src(rs)",16,10,0x00,
1657 "ld",OPC_ld
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_X
+(ARG_RS
),},
1658 {CLASS_BIT
+6,CLASS_BIT
+1,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,71},
1660 /* 0010 0001 0000 dddd imm16 *** ld rd,imm16 */
1663 "ld rd,imm16",16,7,0x00,
1665 "ld",OPC_ld
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),},
1666 {CLASS_BIT
+2,CLASS_BIT
+1,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),0,0,0,0,},2,4,71},
1668 /* 1010 0001 ssss dddd *** ld rd,rs */
1671 "ld rd,rs",16,3,0x00,
1673 "ld",OPC_ld
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
1674 {CLASS_BIT
+0xa,CLASS_BIT
+1,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,71},
1676 /* 0011 0001 ssN0 dddd imm16 *** ld rd,rs(imm16) */
1679 "ld rd,rs(imm16)",16,14,0x00,
1681 "ld",OPC_ld
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_BA
+(ARG_RS
),},
1682 {CLASS_BIT
+3,CLASS_BIT
+1,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),0,0,0,0,},2,4,71},
1684 /* 0111 0001 ssN0 dddd 0000 xxxx 0000 0000 *** ld rd,rs(rx) */
1687 "ld rd,rs(rx)",16,14,0x00,
1689 "ld",OPC_ld
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_BX
+(ARG_RS
),},
1690 {CLASS_BIT
+7,CLASS_BIT
+1,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_BIT
+0,CLASS_REG
+(ARG_RX
),CLASS_BIT
+0,CLASS_BIT
+0,0,},2,4,71},
1692 /* 0111 0110 0000 dddd address_src *** lda prd,address_src */
1695 "lda prd,address_src",16,12,0x00,
1697 "lda",OPC_lda
,0,{CLASS_PR
+(ARG_RD
),CLASS_DA
+(ARG_SRC
),},
1698 {CLASS_BIT
+7,CLASS_BIT
+6,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,72},
1700 /* 0111 0110 ssN0 dddd address_src *** lda prd,address_src(rs) */
1703 "lda prd,address_src(rs)",16,13,0x00,
1705 "lda",OPC_lda
,0,{CLASS_PR
+(ARG_RD
),CLASS_X
+(ARG_RS
),},
1706 {CLASS_BIT
+7,CLASS_BIT
+6,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,72},
1708 /* 0011 0100 ssN0 dddd imm16 *** lda prd,rs(imm16) */
1711 "lda prd,rs(imm16)",16,15,0x00,
1713 "lda",OPC_lda
,0,{CLASS_PR
+(ARG_RD
),CLASS_BA
+(ARG_RS
),},
1714 {CLASS_BIT
+3,CLASS_BIT
+4,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),0,0,0,0,},2,4,72},
1716 /* 0111 0100 ssN0 dddd 0000 xxxx 0000 0000 *** lda prd,rs(rx) */
1719 "lda prd,rs(rx)",16,15,0x00,
1721 "lda",OPC_lda
,0,{CLASS_PR
+(ARG_RD
),CLASS_BX
+(ARG_RS
),},
1722 {CLASS_BIT
+7,CLASS_BIT
+4,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_BIT
+0,CLASS_REG
+(ARG_RX
),CLASS_BIT
+0,CLASS_BIT
+0,0,},2,4,72},
1724 /* 0011 0100 0000 dddd disp16 *** ldar prd,disp16 */
1727 "ldar prd,disp16",16,15,0x00,
1729 "ldar",OPC_ldar
,0,{CLASS_PR
+(ARG_RD
),CLASS_DISP
,},
1730 {CLASS_BIT
+3,CLASS_BIT
+4,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_DISP
+(ARG_DISP16
),0,0,0,0,},2,4,73},
1732 /* 0000 1100 ddN0 0101 imm8 imm8 *** ldb @rd,imm8 */
1735 "ldb @rd,imm8",8,7,0x00,
1737 "ldb",OPC_ldb
,0,{CLASS_IR
+(ARG_RD
),CLASS_IMM
+(ARG_IMM8
),},
1738 {CLASS_BIT
+0,CLASS_BIT
+0xc,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+5,CLASS_IMM
+(ARG_IMM8
),CLASS_IMM
+(ARG_IMM8
),0,0,0,},2,4,74},
1740 /* 0010 1110 ddN0 ssss *** ldb @rd,rbs */
1743 "ldb @rd,rbs",8,8,0x00,
1745 "ldb",OPC_ldb
,0,{CLASS_IR
+(ARG_RD
),CLASS_REG_BYTE
+(ARG_RS
),},
1746 {CLASS_BIT
+2,CLASS_BIT
+0xe,CLASS_REGN0
+(ARG_RD
),CLASS_REG
+(ARG_RS
),0,0,0,0,0,},2,2,74},
1748 /* 0100 1100 ddN0 0101 address_dst imm8 imm8 *** ldb address_dst(rd),imm8 */
1751 "ldb address_dst(rd),imm8",8,15,0x00,
1753 "ldb",OPC_ldb
,0,{CLASS_X
+(ARG_RD
),CLASS_IMM
+(ARG_IMM8
),},
1754 {CLASS_BIT
+4,CLASS_BIT
+0xc,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+5,CLASS_ADDRESS
+(ARG_DST
),CLASS_IMM
+(ARG_IMM8
),CLASS_IMM
+(ARG_IMM8
),0,0,},2,6,74},
1756 /* 0110 1110 ddN0 ssss address_dst *** ldb address_dst(rd),rbs */
1759 "ldb address_dst(rd),rbs",8,12,0x00,
1761 "ldb",OPC_ldb
,0,{CLASS_X
+(ARG_RD
),CLASS_REG_BYTE
+(ARG_RS
),},
1762 {CLASS_BIT
+6,CLASS_BIT
+0xe,CLASS_REGN0
+(ARG_RD
),CLASS_REG
+(ARG_RS
),CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,74},
1764 /* 0100 1100 0000 0101 address_dst imm8 imm8 *** ldb address_dst,imm8 */
1767 "ldb address_dst,imm8",8,14,0x00,
1769 "ldb",OPC_ldb
,0,{CLASS_DA
+(ARG_DST
),CLASS_IMM
+(ARG_IMM8
),},
1770 {CLASS_BIT
+4,CLASS_BIT
+0xc,CLASS_BIT
+0,CLASS_BIT
+5,CLASS_ADDRESS
+(ARG_DST
),CLASS_IMM
+(ARG_IMM8
),CLASS_IMM
+(ARG_IMM8
),0,0,},2,6,74},
1772 /* 0110 1110 0000 ssss address_dst *** ldb address_dst,rbs */
1775 "ldb address_dst,rbs",8,11,0x00,
1777 "ldb",OPC_ldb
,0,{CLASS_DA
+(ARG_DST
),CLASS_REG_BYTE
+(ARG_RS
),},
1778 {CLASS_BIT
+6,CLASS_BIT
+0xe,CLASS_BIT
+0,CLASS_REG
+(ARG_RS
),CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,74},
1780 /* 0010 0000 ssN0 dddd *** ldb rbd,@rs */
1783 "ldb rbd,@rs",8,7,0x00,
1785 "ldb",OPC_ldb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
1786 {CLASS_BIT
+2,CLASS_BIT
+0,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,74},
1788 /* 0110 0000 0000 dddd address_src *** ldb rbd,address_src */
1791 "ldb rbd,address_src",8,9,0x00,
1793 "ldb",OPC_ldb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_DA
+(ARG_SRC
),},
1794 {CLASS_BIT
+6,CLASS_BIT
+0,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,74},
1796 /* 0110 0000 ssN0 dddd address_src *** ldb rbd,address_src(rs) */
1799 "ldb rbd,address_src(rs)",8,10,0x00,
1801 "ldb",OPC_ldb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_X
+(ARG_RS
),},
1802 {CLASS_BIT
+6,CLASS_BIT
+0,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,74},
1804 /* 0010 0000 0000 dddd imm8 imm8 *** ldb rbd,imm8 */
1807 "ldb rbd,imm8",8,7,0x00,
1809 "ldb",OPC_ldb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IMM
+(ARG_IMM8
),},
1810 {CLASS_BIT
+2,CLASS_BIT
+0,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM8
),CLASS_IMM
+(ARG_IMM8
),0,0,0,},2,4,74},
1812 /* 1100 dddd imm8 *** ldb rbd,imm8 */
1815 "ldb rbd,imm8",8,5,0x00,
1817 "ldb",OPC_ldb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IMM
+(ARG_IMM8
),},
1818 {CLASS_BIT
+0xc,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM8
),0,0,0,0,0,0,},2,2,74},
1820 /* 1010 0000 ssss dddd *** ldb rbd,rbs */
1823 "ldb rbd,rbs",8,3,0x00,
1825 "ldb",OPC_ldb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_REG_BYTE
+(ARG_RS
),},
1826 {CLASS_BIT
+0xa,CLASS_BIT
+0,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,74},
1828 /* 0011 0000 ssN0 dddd imm16 *** ldb rbd,rs(imm16) */
1831 "ldb rbd,rs(imm16)",8,14,0x00,
1833 "ldb",OPC_ldb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_BA
+(ARG_RS
),},
1834 {CLASS_BIT
+3,CLASS_BIT
+0,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),0,0,0,0,},2,4,74},
1836 /* 0111 0000 ssN0 dddd 0000 xxxx 0000 0000 *** ldb rbd,rs(rx) */
1839 "ldb rbd,rs(rx)",8,14,0x00,
1841 "ldb",OPC_ldb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_BX
+(ARG_RS
),},
1842 {CLASS_BIT
+7,CLASS_BIT
+0,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_BIT
+0,CLASS_REG
+(ARG_RX
),CLASS_BIT
+0,CLASS_BIT
+0,0,},2,4,74},
1844 /* 0011 0010 ddN0 ssss imm16 *** ldb rd(imm16),rbs */
1847 "ldb rd(imm16),rbs",8,14,0x00,
1849 "ldb",OPC_ldb
,0,{CLASS_BA
+(ARG_RD
),CLASS_REG_BYTE
+(ARG_RS
),},
1850 {CLASS_BIT
+3,CLASS_BIT
+2,CLASS_REGN0
+(ARG_RD
),CLASS_REG
+(ARG_RS
),CLASS_IMM
+(ARG_IMM16
),0,0,0,0,},2,4,74},
1852 /* 0111 0010 ddN0 ssss 0000 xxxx 0000 0000 *** ldb rd(rx),rbs */
1855 "ldb rd(rx),rbs",8,14,0x00,
1857 "ldb",OPC_ldb
,0,{CLASS_BX
+(ARG_RD
),CLASS_REG_BYTE
+(ARG_RS
),},
1858 {CLASS_BIT
+7,CLASS_BIT
+2,CLASS_REGN0
+(ARG_RD
),CLASS_REG
+(ARG_RS
),CLASS_BIT
+0,CLASS_REG
+(ARG_RX
),CLASS_BIT
+0,CLASS_BIT
+0,0,},2,4,74},
1860 /* 0111 1101 ssss 1ccc *** ldctl ctrl,rs */
1863 "ldctl ctrl,rs",32,7,0x00,
1865 "ldctl",OPC_ldctl
,0,{CLASS_CTRL
,CLASS_REG_WORD
+(ARG_RS
),},
1866 {CLASS_BIT
+7,CLASS_BIT
+0xd,CLASS_REG
+(ARG_RS
),CLASS_1CCC
,0,0,0,0,0,},2,2,75},
1868 /* 0111 1101 dddd 0ccc *** ldctl rd,ctrl */
1871 "ldctl rd,ctrl",32,7,0x00,
1873 "ldctl",OPC_ldctl
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_CTRL
,},
1874 {CLASS_BIT
+7,CLASS_BIT
+0xd,CLASS_REG
+(ARG_RD
),CLASS_0CCC
,0,0,0,0,0,},2,2,75},
1876 /* 1000 1100 ssss 1001 *** ldctlb ctrl,rbs */
1879 "ldctlb ctrl,rbs",32,7,0x3f,
1881 "ldctlb",OPC_ldctlb
,0,{CLASS_CTRL
,CLASS_REG_BYTE
+(ARG_RS
),},
1882 {CLASS_BIT
+8,CLASS_BIT
+0xc,CLASS_REG
+(ARG_RS
),CLASS_BIT
+9,0,0,0,0,0,},2,2,76},
1884 /* 1000 1100 dddd 0001 *** ldctlb rbd,ctrl */
1887 "ldctlb rbd,ctrl",32,7,0x00,
1889 "ldctlb",OPC_ldctlb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_CTRL
,},
1890 {CLASS_BIT
+8,CLASS_BIT
+0xc,CLASS_REG
+(ARG_RD
),CLASS_BIT
+1,0,0,0,0,0,},2,2,76},
1892 /* 1011 1011 ssN0 1001 0000 rrrr ddN0 1000 *** ldd @rd,@rs,rr */
1895 "ldd @rd,@rs,rr",16,11,0x04,
1897 "ldd",OPC_ldd
,0,{CLASS_IR
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RR
),},
1898 {CLASS_BIT
+0xb,CLASS_BIT
+0xb,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+9,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+8,0,},3,4,77},
1900 /* 1011 1010 ssN0 1001 0000 rrrr ddN0 1000 *** lddb @rd,@rs,rr */
1903 "lddb @rd,@rs,rr",8,11,0x04,
1905 "lddb",OPC_lddb
,0,{CLASS_IR
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RR
),},
1906 {CLASS_BIT
+0xb,CLASS_BIT
+0xa,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+9,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+8,0,},3,4,78},
1908 /* 1011 1011 ssN0 1001 0000 rrrr ddN0 0000 *** lddr @rd,@rs,rr */
1911 "lddr @rd,@rs,rr",16,11,0x04,
1913 "lddr",OPC_lddr
,0,{CLASS_IR
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RR
),},
1914 {CLASS_BIT
+0xb,CLASS_BIT
+0xb,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+9,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+0,0,},3,4,79},
1916 /* 1011 1010 ssN0 1001 0000 rrrr ddN0 0000 *** lddrb @rd,@rs,rr */
1919 "lddrb @rd,@rs,rr",8,11,0x04,
1921 "lddrb",OPC_lddrb
,0,{CLASS_IR
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RR
),},
1922 {CLASS_BIT
+0xb,CLASS_BIT
+0xa,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+9,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+0,0,},3,4,80},
1924 /* 1011 1011 ssN0 0001 0000 rrrr ddN0 1000 *** ldi @rd,@rs,rr */
1927 "ldi @rd,@rs,rr",16,11,0x04,
1929 "ldi",OPC_ldi
,0,{CLASS_IR
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RR
),},
1930 {CLASS_BIT
+0xb,CLASS_BIT
+0xb,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+1,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+8,0,},3,4,81},
1932 /* 1011 1010 ssN0 0001 0000 rrrr ddN0 1000 *** ldib @rd,@rs,rr */
1935 "ldib @rd,@rs,rr",8,11,0x04,
1937 "ldib",OPC_ldib
,0,{CLASS_IR
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RR
),},
1938 {CLASS_BIT
+0xb,CLASS_BIT
+0xa,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+1,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+8,0,},3,4,82},
1940 /* 1011 1011 ssN0 0001 0000 rrrr ddN0 0000 *** ldir @rd,@rs,rr */
1943 "ldir @rd,@rs,rr",16,11,0x04,
1945 "ldir",OPC_ldir
,0,{CLASS_IR
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RR
),},
1946 {CLASS_BIT
+0xb,CLASS_BIT
+0xb,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+1,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+0,0,},3,4,83},
1948 /* 1011 1010 ssN0 0001 0000 rrrr ddN0 0000 *** ldirb @rd,@rs,rr */
1951 "ldirb @rd,@rs,rr",8,11,0x04,
1953 "ldirb",OPC_ldirb
,0,{CLASS_IR
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RR
),},
1954 {CLASS_BIT
+0xb,CLASS_BIT
+0xa,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+1,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+0,0,},3,4,84},
1956 /* 1011 1101 dddd imm4 *** ldk rd,imm4 */
1959 "ldk rd,imm4",16,5,0x00,
1961 "ldk",OPC_ldk
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),},
1962 {CLASS_BIT
+0xb,CLASS_BIT
+0xd,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),0,0,0,0,0,},2,2,85},
1964 /* 0001 1101 ddN0 ssss *** ldl @rd,rrs */
1967 "ldl @rd,rrs",32,11,0x00,
1969 "ldl",OPC_ldl
,0,{CLASS_IR
+(ARG_RD
),CLASS_REG_LONG
+(ARG_RS
),},
1970 {CLASS_BIT
+1,CLASS_BIT
+0xd,CLASS_REGN0
+(ARG_RD
),CLASS_REG
+(ARG_RS
),0,0,0,0,0,},2,2,86},
1972 /* 0101 1101 ddN0 ssss address_dst *** ldl address_dst(rd),rrs */
1975 "ldl address_dst(rd),rrs",32,14,0x00,
1977 "ldl",OPC_ldl
,0,{CLASS_X
+(ARG_RD
),CLASS_REG_LONG
+(ARG_RS
),},
1978 {CLASS_BIT
+5,CLASS_BIT
+0xd,CLASS_REGN0
+(ARG_RD
),CLASS_REG
+(ARG_RS
),CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,86},
1980 /* 0101 1101 0000 ssss address_dst *** ldl address_dst,rrs */
1983 "ldl address_dst,rrs",32,15,0x00,
1985 "ldl",OPC_ldl
,0,{CLASS_DA
+(ARG_DST
),CLASS_REG_LONG
+(ARG_RS
),},
1986 {CLASS_BIT
+5,CLASS_BIT
+0xd,CLASS_BIT
+0,CLASS_REG
+(ARG_RS
),CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,86},
1988 /* 0011 0111 ddN0 ssss imm16 *** ldl rd(imm16),rrs */
1991 "ldl rd(imm16),rrs",32,17,0x00,
1993 "ldl",OPC_ldl
,0,{CLASS_BA
+(ARG_RD
),CLASS_REG_LONG
+(ARG_RS
),},
1994 {CLASS_BIT
+3,CLASS_BIT
+7,CLASS_REGN0
+(ARG_RD
),CLASS_REG
+(ARG_RS
),CLASS_IMM
+(ARG_IMM16
),0,0,0,0,},2,4,86},
1996 /* 0111 0111 ddN0 ssss 0000 xxxx 0000 0000 *** ldl rd(rx),rrs */
1999 "ldl rd(rx),rrs",32,17,0x00,
2001 "ldl",OPC_ldl
,0,{CLASS_BX
+(ARG_RD
),CLASS_REG_LONG
+(ARG_RS
),},
2002 {CLASS_BIT
+7,CLASS_BIT
+7,CLASS_REGN0
+(ARG_RD
),CLASS_REG
+(ARG_RS
),CLASS_BIT
+0,CLASS_REG
+(ARG_RX
),CLASS_BIT
+0,CLASS_BIT
+0,0,},2,4,86},
2004 /* 0001 0100 ssN0 dddd *** ldl rrd,@rs */
2007 "ldl rrd,@rs",32,11,0x00,
2009 "ldl",OPC_ldl
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
2010 {CLASS_BIT
+1,CLASS_BIT
+4,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,86},
2012 /* 0101 0100 0000 dddd address_src *** ldl rrd,address_src */
2015 "ldl rrd,address_src",32,12,0x00,
2017 "ldl",OPC_ldl
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_DA
+(ARG_SRC
),},
2018 {CLASS_BIT
+5,CLASS_BIT
+4,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,86},
2020 /* 0101 0100 ssN0 dddd address_src *** ldl rrd,address_src(rs) */
2023 "ldl rrd,address_src(rs)",32,13,0x00,
2025 "ldl",OPC_ldl
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_X
+(ARG_RS
),},
2026 {CLASS_BIT
+5,CLASS_BIT
+4,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,86},
2028 /* 0001 0100 0000 dddd imm32 *** ldl rrd,imm32 */
2031 "ldl rrd,imm32",32,11,0x00,
2033 "ldl",OPC_ldl
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM32
),},
2034 {CLASS_BIT
+1,CLASS_BIT
+4,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM32
),0,0,0,0,},2,6,86},
2036 /* 1001 0100 ssss dddd *** ldl rrd,rrs */
2039 "ldl rrd,rrs",32,5,0x00,
2041 "ldl",OPC_ldl
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_REG_LONG
+(ARG_RS
),},
2042 {CLASS_BIT
+9,CLASS_BIT
+4,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,86},
2044 /* 0011 0101 ssN0 dddd imm16 *** ldl rrd,rs(imm16) */
2047 "ldl rrd,rs(imm16)",32,17,0x00,
2049 "ldl",OPC_ldl
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_BA
+(ARG_RS
),},
2050 {CLASS_BIT
+3,CLASS_BIT
+5,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),0,0,0,0,},2,4,86},
2052 /* 0111 0101 ssN0 dddd 0000 xxxx 0000 0000 *** ldl rrd,rs(rx) */
2055 "ldl rrd,rs(rx)",32,17,0x00,
2057 "ldl",OPC_ldl
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_BX
+(ARG_RS
),},
2058 {CLASS_BIT
+7,CLASS_BIT
+5,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_BIT
+0,CLASS_REG
+(ARG_RX
),CLASS_BIT
+0,CLASS_BIT
+0,0,},2,4,86},
2060 /* 0001 1100 ddN0 1001 0000 ssss 0000 imm4m1 *** ldm @rd,rs,n */
2063 "ldm @rd,rs,n",16,11,0x00,
2065 "ldm",OPC_ldm
,0,{CLASS_IR
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),CLASS_IMM
+ (ARG_IMM4M1
),},
2066 {CLASS_BIT
+1,CLASS_BIT
+0xc,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+9,CLASS_BIT
+0,CLASS_REG
+(ARG_RS
),CLASS_BIT
+0,CLASS_IMM
+(ARG_IMM4M1
),0,},3,4,87},
2068 /* 0101 1100 ddN0 1001 0000 ssss 0000 imm4m1 address_dst *** ldm address_dst(rd),rs,n */
2071 "ldm address_dst(rd),rs,n",16,15,0x00,
2073 "ldm",OPC_ldm
,0,{CLASS_X
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),CLASS_IMM
+ (ARG_IMM4M1
),},
2074 {CLASS_BIT
+5,CLASS_BIT
+0xc,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+9,CLASS_BIT
+0,CLASS_REG
+(ARG_RS
),CLASS_BIT
+0,CLASS_IMM
+(ARG_IMM4M1
),CLASS_ADDRESS
+(ARG_DST
),},3,6,87},
2076 /* 0101 1100 0000 1001 0000 ssss 0000 imm4m1 address_dst *** ldm address_dst,rs,n */
2079 "ldm address_dst,rs,n",16,14,0x00,
2081 "ldm",OPC_ldm
,0,{CLASS_DA
+(ARG_DST
),CLASS_REG_WORD
+(ARG_RS
),CLASS_IMM
+ (ARG_IMM4M1
),},
2082 {CLASS_BIT
+5,CLASS_BIT
+0xc,CLASS_BIT
+0,CLASS_BIT
+9,CLASS_BIT
+0,CLASS_REG
+(ARG_RS
),CLASS_BIT
+0,CLASS_IMM
+(ARG_IMM4M1
),CLASS_ADDRESS
+(ARG_DST
),},3,6,87},
2084 /* 0001 1100 ssN0 0001 0000 dddd 0000 imm4m1 *** ldm rd,@rs,n */
2087 "ldm rd,@rs,n",16,11,0x00,
2089 "ldm",OPC_ldm
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_IMM
+ (ARG_IMM4M1
),},
2090 {CLASS_BIT
+1,CLASS_BIT
+0xc,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+1,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_BIT
+0,CLASS_IMM
+(ARG_IMM4M1
),0,},3,4,87},
2092 /* 0101 1100 ssN0 0001 0000 dddd 0000 imm4m1 address_src *** ldm rd,address_src(rs),n */
2095 "ldm rd,address_src(rs),n",16,15,0x00,
2097 "ldm",OPC_ldm
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_X
+(ARG_RS
),CLASS_IMM
+ (ARG_IMM4M1
),},
2098 {CLASS_BIT
+5,CLASS_BIT
+0xc,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+1,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_BIT
+0,CLASS_IMM
+(ARG_IMM4M1
),CLASS_ADDRESS
+(ARG_SRC
),},3,6,87},
2100 /* 0101 1100 0000 0001 0000 dddd 0000 imm4m1 address_src *** ldm rd,address_src,n */
2103 "ldm rd,address_src,n",16,14,0x00,
2105 "ldm",OPC_ldm
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_DA
+(ARG_SRC
),CLASS_IMM
+ (ARG_IMM4M1
),},
2106 {CLASS_BIT
+5,CLASS_BIT
+0xc,CLASS_BIT
+0,CLASS_BIT
+1,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_BIT
+0,CLASS_IMM
+(ARG_IMM4M1
),CLASS_ADDRESS
+(ARG_SRC
),},3,6,87},
2108 /* 0011 1001 ssN0 0000 *** ldps @rs */
2111 "ldps @rs",16,12,0x3f,
2113 "ldps",OPC_ldps
,0,{CLASS_IR
+(ARG_RS
),},
2114 {CLASS_BIT
+3,CLASS_BIT
+9,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+0,0,0,0,0,0,},1,2,88},
2116 /* 0111 1001 0000 0000 address_src *** ldps address_src */
2119 "ldps address_src",16,16,0x3f,
2121 "ldps",OPC_ldps
,0,{CLASS_DA
+(ARG_SRC
),},
2122 {CLASS_BIT
+7,CLASS_BIT
+9,CLASS_BIT
+0,CLASS_BIT
+0,CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},1,4,88},
2124 /* 0111 1001 ssN0 0000 address_src *** ldps address_src(rs) */
2127 "ldps address_src(rs)",16,17,0x3f,
2129 "ldps",OPC_ldps
,0,{CLASS_X
+(ARG_RS
),},
2130 {CLASS_BIT
+7,CLASS_BIT
+9,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+0,CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},1,4,88},
2132 /* 0011 0011 0000 ssss disp16 *** ldr disp16,rs */
2135 "ldr disp16,rs",16,14,0x00,
2137 "ldr",OPC_ldr
,0,{CLASS_DISP
,CLASS_REG_WORD
+(ARG_RS
),},
2138 {CLASS_BIT
+3,CLASS_BIT
+3,CLASS_BIT
+0,CLASS_REG
+(ARG_RS
),CLASS_DISP
+(ARG_DISP16
),0,0,0,0,},2,4,89},
2140 /* 0011 0001 0000 dddd disp16 *** ldr rd,disp16 */
2143 "ldr rd,disp16",16,14,0x00,
2145 "ldr",OPC_ldr
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_DISP
,},
2146 {CLASS_BIT
+3,CLASS_BIT
+1,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_DISP
+(ARG_DISP16
),0,0,0,0,},2,4,89},
2148 /* 0011 0010 0000 ssss disp16 *** ldrb disp16,rbs */
2151 "ldrb disp16,rbs",8,14,0x00,
2153 "ldrb",OPC_ldrb
,0,{CLASS_DISP
,CLASS_REG_BYTE
+(ARG_RS
),},
2154 {CLASS_BIT
+3,CLASS_BIT
+2,CLASS_BIT
+0,CLASS_REG
+(ARG_RS
),CLASS_DISP
+(ARG_DISP16
),0,0,0,0,},2,4,90},
2156 /* 0011 0000 0000 dddd disp16 *** ldrb rbd,disp16 */
2159 "ldrb rbd,disp16",8,14,0x00,
2161 "ldrb",OPC_ldrb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_DISP
,},
2162 {CLASS_BIT
+3,CLASS_BIT
+0,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_DISP
+(ARG_DISP16
),0,0,0,0,},2,4,90},
2164 /* 0011 0111 0000 ssss disp16 *** ldrl disp16,rrs */
2167 "ldrl disp16,rrs",32,17,0x00,
2169 "ldrl",OPC_ldrl
,0,{CLASS_DISP
,CLASS_REG_LONG
+(ARG_RS
),},
2170 {CLASS_BIT
+3,CLASS_BIT
+7,CLASS_BIT
+0,CLASS_REG
+(ARG_RS
),CLASS_DISP
+(ARG_DISP16
),0,0,0,0,},2,4,91},
2172 /* 0011 0101 0000 dddd disp16 *** ldrl rrd,disp16 */
2175 "ldrl rrd,disp16",32,17,0x00,
2177 "ldrl",OPC_ldrl
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_DISP
,},
2178 {CLASS_BIT
+3,CLASS_BIT
+5,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_DISP
+(ARG_DISP16
),0,0,0,0,},2,4,91},
2180 /* 0111 1011 0000 1010 *** mbit */
2185 "mbit",OPC_mbit
,0,{0},
2186 {CLASS_BIT
+7,CLASS_BIT
+0xb,CLASS_BIT
+0,CLASS_BIT
+0xa,0,0,0,0,0,},0,2,92},
2188 /* 0111 1011 dddd 1101 *** mreq rd */
2191 "mreq rd",16,12,0x18,
2193 "mreq",OPC_mreq
,0,{CLASS_REG_WORD
+(ARG_RD
),},
2194 {CLASS_BIT
+7,CLASS_BIT
+0xb,CLASS_REG
+(ARG_RD
),CLASS_BIT
+0xd,0,0,0,0,0,},1,2,93},
2196 /* 0111 1011 0000 1001 *** mres */
2201 "mres",OPC_mres
,0,{0},
2202 {CLASS_BIT
+7,CLASS_BIT
+0xb,CLASS_BIT
+0,CLASS_BIT
+9,0,0,0,0,0,},0,2,94},
2204 /* 0111 1011 0000 1000 *** mset */
2209 "mset",OPC_mset
,0,{0},
2210 {CLASS_BIT
+7,CLASS_BIT
+0xb,CLASS_BIT
+0,CLASS_BIT
+8,0,0,0,0,0,},0,2,95},
2212 /* 0001 1001 ssN0 dddd *** mult rrd,@rs */
2215 "mult rrd,@rs",16,70,0x3c,
2217 "mult",OPC_mult
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
2218 {CLASS_BIT
+1,CLASS_BIT
+9,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,96},
2220 /* 0101 1001 0000 dddd address_src *** mult rrd,address_src */
2223 "mult rrd,address_src",16,70,0x3c,
2225 "mult",OPC_mult
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_DA
+(ARG_SRC
),},
2226 {CLASS_BIT
+5,CLASS_BIT
+9,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,96},
2228 /* 0101 1001 ssN0 dddd address_src *** mult rrd,address_src(rs) */
2231 "mult rrd,address_src(rs)",16,70,0x3c,
2233 "mult",OPC_mult
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_X
+(ARG_RS
),},
2234 {CLASS_BIT
+5,CLASS_BIT
+9,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,96},
2236 /* 0001 1001 0000 dddd imm16 *** mult rrd,imm16 */
2239 "mult rrd,imm16",16,70,0x3c,
2241 "mult",OPC_mult
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),},
2242 {CLASS_BIT
+1,CLASS_BIT
+9,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),0,0,0,0,},2,4,96},
2244 /* 1001 1001 ssss dddd *** mult rrd,rs */
2247 "mult rrd,rs",16,70,0x3c,
2249 "mult",OPC_mult
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
2250 {CLASS_BIT
+9,CLASS_BIT
+9,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,96},
2252 /* 0001 1000 ssN0 dddd *** multl rqd,@rs */
2255 "multl rqd,@rs",32,282,0x3c,
2257 "multl",OPC_multl
,0,{CLASS_REG_QUAD
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
2258 {CLASS_BIT
+1,CLASS_BIT
+8,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,97},
2260 /* 0101 1000 0000 dddd address_src *** multl rqd,address_src */
2263 "multl rqd,address_src",32,282,0x3c,
2265 "multl",OPC_multl
,0,{CLASS_REG_QUAD
+(ARG_RD
),CLASS_DA
+(ARG_SRC
),},
2266 {CLASS_BIT
+5,CLASS_BIT
+8,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,97},
2268 /* 0101 1000 ssN0 dddd address_src *** multl rqd,address_src(rs) */
2271 "multl rqd,address_src(rs)",32,282,0x3c,
2273 "multl",OPC_multl
,0,{CLASS_REG_QUAD
+(ARG_RD
),CLASS_X
+(ARG_RS
),},
2274 {CLASS_BIT
+5,CLASS_BIT
+8,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,97},
2276 /* 0001 1000 0000 dddd imm32 *** multl rqd,imm32 */
2279 "multl rqd,imm32",32,282,0x3c,
2281 "multl",OPC_multl
,0,{CLASS_REG_QUAD
+(ARG_RD
),CLASS_IMM
+(ARG_IMM32
),},
2282 {CLASS_BIT
+1,CLASS_BIT
+8,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM32
),0,0,0,0,},2,6,97},
2284 /* 1001 1000 ssss dddd *** multl rqd,rrs */
2287 "multl rqd,rrs",32,282,0x3c,
2289 "multl",OPC_multl
,0,{CLASS_REG_QUAD
+(ARG_RD
),CLASS_REG_LONG
+(ARG_RS
),},
2290 {CLASS_BIT
+9,CLASS_BIT
+8,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,97},
2292 /* 0000 1101 ddN0 0010 *** neg @rd */
2295 "neg @rd",16,12,0x3c,
2297 "neg",OPC_neg
,0,{CLASS_IR
+(ARG_RD
),},
2298 {CLASS_BIT
+0,CLASS_BIT
+0xd,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+2,0,0,0,0,0,},1,2,98},
2300 /* 0100 1101 0000 0010 address_dst *** neg address_dst */
2303 "neg address_dst",16,15,0x3c,
2305 "neg",OPC_neg
,0,{CLASS_DA
+(ARG_DST
),},
2306 {CLASS_BIT
+4,CLASS_BIT
+0xd,CLASS_BIT
+0,CLASS_BIT
+2,CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},1,4,98},
2308 /* 0100 1101 ddN0 0010 address_dst *** neg address_dst(rd) */
2311 "neg address_dst(rd)",16,16,0x3c,
2313 "neg",OPC_neg
,0,{CLASS_X
+(ARG_RD
),},
2314 {CLASS_BIT
+4,CLASS_BIT
+0xd,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+2,CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},1,4,98},
2316 /* 1000 1101 dddd 0010 *** neg rd */
2321 "neg",OPC_neg
,0,{CLASS_REG_WORD
+(ARG_RD
),},
2322 {CLASS_BIT
+8,CLASS_BIT
+0xd,CLASS_REG
+(ARG_RD
),CLASS_BIT
+2,0,0,0,0,0,},1,2,98},
2324 /* 0000 1100 ddN0 0010 *** negb @rd */
2327 "negb @rd",8,12,0x3c,
2329 "negb",OPC_negb
,0,{CLASS_IR
+(ARG_RD
),},
2330 {CLASS_BIT
+0,CLASS_BIT
+0xc,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+2,0,0,0,0,0,},1,2,99},
2332 /* 0100 1100 0000 0010 address_dst *** negb address_dst */
2335 "negb address_dst",8,15,0x3c,
2337 "negb",OPC_negb
,0,{CLASS_DA
+(ARG_DST
),},
2338 {CLASS_BIT
+4,CLASS_BIT
+0xc,CLASS_BIT
+0,CLASS_BIT
+2,CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},1,4,99},
2340 /* 0100 1100 ddN0 0010 address_dst *** negb address_dst(rd) */
2343 "negb address_dst(rd)",8,16,0x3c,
2345 "negb",OPC_negb
,0,{CLASS_X
+(ARG_RD
),},
2346 {CLASS_BIT
+4,CLASS_BIT
+0xc,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+2,CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},1,4,99},
2348 /* 1000 1100 dddd 0010 *** negb rbd */
2351 "negb rbd",8,7,0x3c,
2353 "negb",OPC_negb
,0,{CLASS_REG_BYTE
+(ARG_RD
),},
2354 {CLASS_BIT
+8,CLASS_BIT
+0xc,CLASS_REG
+(ARG_RD
),CLASS_BIT
+2,0,0,0,0,0,},1,2,99},
2356 /* 1000 1101 0000 0111 *** nop */
2361 "nop",OPC_nop
,0,{0},
2362 {CLASS_BIT
+8,CLASS_BIT
+0xd,CLASS_BIT
+0,CLASS_BIT
+7,0,0,0,0,0,},0,2,100},
2364 /* 0000 0101 ssN0 dddd *** or rd,@rs */
2367 "or rd,@rs",16,7,0x38,
2369 "or",OPC_or
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
2370 {CLASS_BIT
+0,CLASS_BIT
+5,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,101},
2372 /* 0100 0101 0000 dddd address_src *** or rd,address_src */
2375 "or rd,address_src",16,9,0x38,
2377 "or",OPC_or
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_DA
+(ARG_SRC
),},
2378 {CLASS_BIT
+4,CLASS_BIT
+5,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,101},
2380 /* 0100 0101 ssN0 dddd address_src *** or rd,address_src(rs) */
2383 "or rd,address_src(rs)",16,10,0x38,
2385 "or",OPC_or
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_X
+(ARG_RS
),},
2386 {CLASS_BIT
+4,CLASS_BIT
+5,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,101},
2388 /* 0000 0101 0000 dddd imm16 *** or rd,imm16 */
2391 "or rd,imm16",16,7,0x38,
2393 "or",OPC_or
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),},
2394 {CLASS_BIT
+0,CLASS_BIT
+5,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),0,0,0,0,},2,4,101},
2396 /* 1000 0101 ssss dddd *** or rd,rs */
2399 "or rd,rs",16,4,0x38,
2401 "or",OPC_or
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
2402 {CLASS_BIT
+8,CLASS_BIT
+5,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,101},
2404 /* 0000 0100 ssN0 dddd *** orb rbd,@rs */
2407 "orb rbd,@rs",8,7,0x3c,
2409 "orb",OPC_orb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
2410 {CLASS_BIT
+0,CLASS_BIT
+4,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,102},
2412 /* 0100 0100 0000 dddd address_src *** orb rbd,address_src */
2415 "orb rbd,address_src",8,9,0x3c,
2417 "orb",OPC_orb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_DA
+(ARG_SRC
),},
2418 {CLASS_BIT
+4,CLASS_BIT
+4,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,102},
2420 /* 0100 0100 ssN0 dddd address_src *** orb rbd,address_src(rs) */
2423 "orb rbd,address_src(rs)",8,10,0x3c,
2425 "orb",OPC_orb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_X
+(ARG_RS
),},
2426 {CLASS_BIT
+4,CLASS_BIT
+4,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,102},
2428 /* 0000 0100 0000 dddd imm8 imm8 *** orb rbd,imm8 */
2431 "orb rbd,imm8",8,7,0x3c,
2433 "orb",OPC_orb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IMM
+(ARG_IMM8
),},
2434 {CLASS_BIT
+0,CLASS_BIT
+4,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM8
),CLASS_IMM
+(ARG_IMM8
),0,0,0,},2,4,102},
2436 /* 1000 0100 ssss dddd *** orb rbd,rbs */
2439 "orb rbd,rbs",8,4,0x3c,
2441 "orb",OPC_orb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_REG_BYTE
+(ARG_RS
),},
2442 {CLASS_BIT
+8,CLASS_BIT
+4,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,102},
2444 /* 0011 1011 ssN0 1010 0000 aaaa dddd 0000 *** otdr @ro,@rs,ra */
2447 "otdr @ro,@rs,ra",16,11,0x04,
2449 "otdr",OPC_otdr
,0,{CLASS_IRO
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
2450 {CLASS_BIT
+3,CLASS_BIT
+0xb,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+0xa,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REG
+(ARG_RD
),CLASS_BIT
+0,0,},3,4,103},
2452 /* 0011 1010 ssN0 1010 0000 aaaa dddd 0000 *** otdrb @ro,@rs,ra */
2455 "otdrb @ro,@rs,ra",8,11,0x04,
2457 "otdrb",OPC_otdrb
,0,{CLASS_IRO
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
2458 {CLASS_BIT
+3,CLASS_BIT
+0xa,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+0xa,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REG
+(ARG_RD
),CLASS_BIT
+0,0,},3,4,104},
2460 /* 0011 1011 ssN0 0010 0000 aaaa dddd 0000 *** otir @ro,@rs,ra */
2463 "otir @ro,@rs,ra",16,11,0x04,
2465 "otir",OPC_otir
,0,{CLASS_IRO
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
2466 {CLASS_BIT
+3,CLASS_BIT
+0xb,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+2,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REG
+(ARG_RD
),CLASS_BIT
+0,0,},3,4,105},
2468 /* 0011 1010 ssN0 0010 0000 aaaa dddd 0000 *** otirb @ro,@rs,ra */
2471 "otirb @ro,@rs,ra",8,11,0x04,
2473 "otirb",OPC_otirb
,0,{CLASS_IRO
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
2474 {CLASS_BIT
+3,CLASS_BIT
+0xa,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+2,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REG
+(ARG_RD
),CLASS_BIT
+0,0,},3,4,106},
2476 /* 0011 1111 dddd ssss *** out @ro,rs */
2479 "out @ro,rs",16,10,0x00,
2481 "out",OPC_out
,0,{CLASS_IRO
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
2482 {CLASS_BIT
+3,CLASS_BIT
+0xf,CLASS_REG
+(ARG_RD
),CLASS_REG
+(ARG_RS
),0,0,0,0,0,},2,2,107},
2484 /* 0011 1011 ssss 0110 imm16 *** out imm16,rs */
2487 "out imm16,rs",16,12,0x00,
2489 "out",OPC_out
,0,{CLASS_IMM
+(ARG_IMM16
),CLASS_REG_WORD
+(ARG_RS
),},
2490 {CLASS_BIT
+3,CLASS_BIT
+0xb,CLASS_REG
+(ARG_RS
),CLASS_BIT
+6,CLASS_IMM
+(ARG_IMM16
),0,0,0,0,},2,4,107},
2492 /* 0011 1110 dddd ssss *** outb @ro,rbs */
2495 "outb @ro,rbs",8,10,0x00,
2497 "outb",OPC_outb
,0,{CLASS_IRO
+(ARG_RD
),CLASS_REG_BYTE
+(ARG_RS
),},
2498 {CLASS_BIT
+3,CLASS_BIT
+0xe,CLASS_REG
+(ARG_RD
),CLASS_REG
+(ARG_RS
),0,0,0,0,0,},2,2,108},
2500 /* 0011 1010 ssss 0110 imm16 *** outb imm16,rbs */
2503 "outb imm16,rbs",8,12,0x00,
2505 "outb",OPC_outb
,0,{CLASS_IMM
+(ARG_IMM16
),CLASS_REG_BYTE
+(ARG_RS
),},
2506 {CLASS_BIT
+3,CLASS_BIT
+0xa,CLASS_REG
+(ARG_RS
),CLASS_BIT
+6,CLASS_IMM
+(ARG_IMM16
),0,0,0,0,},2,4,108},
2508 /* 0011 1011 ssN0 1010 0000 aaaa dddd 1000 *** outd @ro,@rs,ra */
2511 "outd @ro,@rs,ra",16,21,0x04,
2513 "outd",OPC_outd
,0,{CLASS_IRO
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
2514 {CLASS_BIT
+3,CLASS_BIT
+0xb,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+0xa,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REG
+(ARG_RD
),CLASS_BIT
+8,0,},3,4,109},
2516 /* 0011 1010 ssN0 1010 0000 aaaa dddd 1000 *** outdb @ro,@rs,ra */
2519 "outdb @ro,@rs,ra",8,21,0x04,
2521 "outdb",OPC_outdb
,0,{CLASS_IRO
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
2522 {CLASS_BIT
+3,CLASS_BIT
+0xa,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+0xa,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REG
+(ARG_RD
),CLASS_BIT
+8,0,},3,4,110},
2524 /* 0011 1011 ssN0 0010 0000 aaaa dddd 1000 *** outi @ro,@rs,ra */
2527 "outi @ro,@rs,ra",16,21,0x04,
2529 "outi",OPC_outi
,0,{CLASS_IRO
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
2530 {CLASS_BIT
+3,CLASS_BIT
+0xb,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+2,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REG
+(ARG_RD
),CLASS_BIT
+8,0,},3,4,111},
2532 /* 0011 1010 ssN0 0010 0000 aaaa dddd 1000 *** outib @ro,@rs,ra */
2535 "outib @ro,@rs,ra",8,21,0x04,
2537 "outib",OPC_outib
,0,{CLASS_IRO
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
2538 {CLASS_BIT
+3,CLASS_BIT
+0xa,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+2,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REG
+(ARG_RD
),CLASS_BIT
+8,0,},3,4,112},
2540 /* 0001 0111 ssN0 ddN0 *** pop @rd,@rs */
2543 "pop @rd,@rs",16,12,0x00,
2545 "pop",OPC_pop
,0,{CLASS_IR
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
2546 {CLASS_BIT
+1,CLASS_BIT
+7,CLASS_REGN0
+(ARG_RS
),CLASS_REGN0
+(ARG_RD
),0,0,0,0,0,},2,2,113},
2548 /* 0101 0111 ssN0 ddN0 address_dst *** pop address_dst(rd),@rs */
2551 "pop address_dst(rd),@rs",16,16,0x00,
2553 "pop",OPC_pop
,0,{CLASS_X
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
2554 {CLASS_BIT
+5,CLASS_BIT
+7,CLASS_REGN0
+(ARG_RS
),CLASS_REGN0
+(ARG_RD
),CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,113},
2556 /* 0101 0111 ssN0 0000 address_dst *** pop address_dst,@rs */
2559 "pop address_dst,@rs",16,16,0x00,
2561 "pop",OPC_pop
,0,{CLASS_DA
+(ARG_DST
),CLASS_IR
+(ARG_RS
),},
2562 {CLASS_BIT
+5,CLASS_BIT
+7,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+0,CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,113},
2564 /* 1001 0111 ssN0 dddd *** pop rd,@rs */
2567 "pop rd,@rs",16,8,0x00,
2569 "pop",OPC_pop
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
2570 {CLASS_BIT
+9,CLASS_BIT
+7,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,113},
2572 /* 0001 0101 ssN0 ddN0 *** popl @rd,@rs */
2575 "popl @rd,@rs",32,19,0x00,
2577 "popl",OPC_popl
,0,{CLASS_IR
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
2578 {CLASS_BIT
+1,CLASS_BIT
+5,CLASS_REGN0
+(ARG_RS
),CLASS_REGN0
+(ARG_RD
),0,0,0,0,0,},2,2,114},
2580 /* 0101 0101 ssN0 ddN0 address_dst *** popl address_dst(rd),@rs */
2583 "popl address_dst(rd),@rs",32,23,0x00,
2585 "popl",OPC_popl
,0,{CLASS_X
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
2586 {CLASS_BIT
+5,CLASS_BIT
+5,CLASS_REGN0
+(ARG_RS
),CLASS_REGN0
+(ARG_RD
),CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,114},
2588 /* 0101 0101 ssN0 0000 address_dst *** popl address_dst,@rs */
2591 "popl address_dst,@rs",32,23,0x00,
2593 "popl",OPC_popl
,0,{CLASS_DA
+(ARG_DST
),CLASS_IR
+(ARG_RS
),},
2594 {CLASS_BIT
+5,CLASS_BIT
+5,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+0,CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,114},
2596 /* 1001 0101 ssN0 dddd *** popl rrd,@rs */
2599 "popl rrd,@rs",32,12,0x00,
2601 "popl",OPC_popl
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
2602 {CLASS_BIT
+9,CLASS_BIT
+5,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,114},
2604 /* 0001 0011 ddN0 ssN0 *** push @rd,@rs */
2607 "push @rd,@rs",16,13,0x00,
2609 "push",OPC_push
,0,{CLASS_IR
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
2610 {CLASS_BIT
+1,CLASS_BIT
+3,CLASS_REGN0
+(ARG_RD
),CLASS_REGN0
+(ARG_RS
),0,0,0,0,0,},2,2,115},
2612 /* 0101 0011 ddN0 0000 address_src *** push @rd,address_src */
2615 "push @rd,address_src",16,14,0x00,
2617 "push",OPC_push
,0,{CLASS_IR
+(ARG_RD
),CLASS_DA
+(ARG_SRC
),},
2618 {CLASS_BIT
+5,CLASS_BIT
+3,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+0,CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,115},
2620 /* 0101 0011 ddN0 ssN0 address_src *** push @rd,address_src(rs) */
2623 "push @rd,address_src(rs)",16,14,0x00,
2625 "push",OPC_push
,0,{CLASS_IR
+(ARG_RD
),CLASS_X
+(ARG_RS
),},
2626 {CLASS_BIT
+5,CLASS_BIT
+3,CLASS_REGN0
+(ARG_RD
),CLASS_REGN0
+(ARG_RS
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,115},
2628 /* 0000 1101 ddN0 1001 imm16 *** push @rd,imm16 */
2631 "push @rd,imm16",16,12,0x00,
2633 "push",OPC_push
,0,{CLASS_IR
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),},
2634 {CLASS_BIT
+0,CLASS_BIT
+0xd,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+9,CLASS_IMM
+(ARG_IMM16
),0,0,0,0,},2,4,115},
2636 /* 1001 0011 ddN0 ssss *** push @rd,rs */
2639 "push @rd,rs",16,9,0x00,
2641 "push",OPC_push
,0,{CLASS_IR
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
2642 {CLASS_BIT
+9,CLASS_BIT
+3,CLASS_REGN0
+(ARG_RD
),CLASS_REG
+(ARG_RS
),0,0,0,0,0,},2,2,115},
2644 /* 0001 0001 ddN0 ssN0 *** pushl @rd,@rs */
2647 "pushl @rd,@rs",32,20,0x00,
2649 "pushl",OPC_pushl
,0,{CLASS_IR
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
2650 {CLASS_BIT
+1,CLASS_BIT
+1,CLASS_REGN0
+(ARG_RD
),CLASS_REGN0
+(ARG_RS
),0,0,0,0,0,},2,2,116},
2652 /* 0101 0001 ddN0 0000 address_src *** pushl @rd,address_src */
2655 "pushl @rd,address_src",32,21,0x00,
2657 "pushl",OPC_pushl
,0,{CLASS_IR
+(ARG_RD
),CLASS_DA
+(ARG_SRC
),},
2658 {CLASS_BIT
+5,CLASS_BIT
+1,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+0,CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,116},
2660 /* 0101 0001 ddN0 ssN0 address_src *** pushl @rd,address_src(rs) */
2663 "pushl @rd,address_src(rs)",32,21,0x00,
2665 "pushl",OPC_pushl
,0,{CLASS_IR
+(ARG_RD
),CLASS_X
+(ARG_RS
),},
2666 {CLASS_BIT
+5,CLASS_BIT
+1,CLASS_REGN0
+(ARG_RD
),CLASS_REGN0
+(ARG_RS
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,116},
2668 /* 1001 0001 ddN0 ssss *** pushl @rd,rrs */
2671 "pushl @rd,rrs",32,12,0x00,
2673 "pushl",OPC_pushl
,0,{CLASS_IR
+(ARG_RD
),CLASS_REG_LONG
+(ARG_RS
),},
2674 {CLASS_BIT
+9,CLASS_BIT
+1,CLASS_REGN0
+(ARG_RD
),CLASS_REG
+(ARG_RS
),0,0,0,0,0,},2,2,116},
2676 /* 0010 0011 ddN0 imm4 *** res @rd,imm4 */
2679 "res @rd,imm4",16,11,0x00,
2681 "res",OPC_res
,0,{CLASS_IR
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),},
2682 {CLASS_BIT
+2,CLASS_BIT
+3,CLASS_REGN0
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),0,0,0,0,0,},2,2,117},
2684 /* 0110 0011 ddN0 imm4 address_dst *** res address_dst(rd),imm4 */
2687 "res address_dst(rd),imm4",16,14,0x00,
2689 "res",OPC_res
,0,{CLASS_X
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),},
2690 {CLASS_BIT
+6,CLASS_BIT
+3,CLASS_REGN0
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,117},
2692 /* 0110 0011 0000 imm4 address_dst *** res address_dst,imm4 */
2695 "res address_dst,imm4",16,13,0x00,
2697 "res",OPC_res
,0,{CLASS_DA
+(ARG_DST
),CLASS_IMM
+(ARG_IMM4
),},
2698 {CLASS_BIT
+6,CLASS_BIT
+3,CLASS_BIT
+0,CLASS_IMM
+(ARG_IMM4
),CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,117},
2700 /* 1010 0011 dddd imm4 *** res rd,imm4 */
2703 "res rd,imm4",16,4,0x00,
2705 "res",OPC_res
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),},
2706 {CLASS_BIT
+0xa,CLASS_BIT
+3,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),0,0,0,0,0,},2,2,117},
2708 /* 0010 0011 0000 ssss 0000 dddd 0000 0000 *** res rd,rs */
2711 "res rd,rs",16,10,0x00,
2713 "res",OPC_res
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
2714 {CLASS_BIT
+2,CLASS_BIT
+3,CLASS_BIT
+0,CLASS_REG
+(ARG_RS
),CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_BIT
+0,CLASS_BIT
+0,0,},2,4,117},
2716 /* 0010 0010 ddN0 imm4 *** resb @rd,imm4 */
2719 "resb @rd,imm4",8,11,0x00,
2721 "resb",OPC_resb
,0,{CLASS_IR
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),},
2722 {CLASS_BIT
+2,CLASS_BIT
+2,CLASS_REGN0
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),0,0,0,0,0,},2,2,118},
2724 /* 0110 0010 ddN0 imm4 address_dst *** resb address_dst(rd),imm4 */
2727 "resb address_dst(rd),imm4",8,14,0x00,
2729 "resb",OPC_resb
,0,{CLASS_X
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),},
2730 {CLASS_BIT
+6,CLASS_BIT
+2,CLASS_REGN0
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,118},
2732 /* 0110 0010 0000 imm4 address_dst *** resb address_dst,imm4 */
2735 "resb address_dst,imm4",8,13,0x00,
2737 "resb",OPC_resb
,0,{CLASS_DA
+(ARG_DST
),CLASS_IMM
+(ARG_IMM4
),},
2738 {CLASS_BIT
+6,CLASS_BIT
+2,CLASS_BIT
+0,CLASS_IMM
+(ARG_IMM4
),CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,118},
2740 /* 1010 0010 dddd imm4 *** resb rbd,imm4 */
2743 "resb rbd,imm4",8,4,0x00,
2745 "resb",OPC_resb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),},
2746 {CLASS_BIT
+0xa,CLASS_BIT
+2,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),0,0,0,0,0,},2,2,118},
2748 /* 0010 0010 0000 ssss 0000 dddd 0000 0000 *** resb rbd,rs */
2751 "resb rbd,rs",8,10,0x00,
2753 "resb",OPC_resb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
2754 {CLASS_BIT
+2,CLASS_BIT
+2,CLASS_BIT
+0,CLASS_REG
+(ARG_RS
),CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_BIT
+0,CLASS_BIT
+0,0,},2,4,118},
2756 /* 1000 1101 flags 0011 *** resflg flags */
2759 "resflg flags",16,7,0x3c,
2761 "resflg",OPC_resflg
,0,{CLASS_FLAGS
,},
2762 {CLASS_BIT
+8,CLASS_BIT
+0xd,CLASS_FLAGS
,CLASS_BIT
+3,0,0,0,0,0,},1,2,119},
2764 /* 1001 1110 0000 cccc *** ret cc */
2767 "ret cc",16,10,0x00,
2769 "ret",OPC_ret
,0,{CLASS_CC
,},
2770 {CLASS_BIT
+9,CLASS_BIT
+0xe,CLASS_BIT
+0,CLASS_CC
,0,0,0,0,0,},1,2,120},
2772 /* 1011 0011 dddd 00I0 *** rl rd,imm1or2 */
2775 "rl rd,imm1or2",16,6,0x3c,
2777 "rl",OPC_rl
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IMM
+(ARG_IMM1OR2
),},
2778 {CLASS_BIT
+0xb,CLASS_BIT
+3,CLASS_REG
+(ARG_RD
),CLASS_BIT_1OR2
+0,0,0,0,0,0,},2,2,121},
2780 /* 1011 0010 dddd 00I0 *** rlb rbd,imm1or2 */
2783 "rlb rbd,imm1or2",8,6,0x3c,
2785 "rlb",OPC_rlb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IMM
+(ARG_IMM1OR2
),},
2786 {CLASS_BIT
+0xb,CLASS_BIT
+2,CLASS_REG
+(ARG_RD
),CLASS_BIT_1OR2
+0,0,0,0,0,0,},2,2,122},
2788 /* 1011 0011 dddd 10I0 *** rlc rd,imm1or2 */
2791 "rlc rd,imm1or2",16,6,0x3c,
2793 "rlc",OPC_rlc
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IMM
+(ARG_IMM1OR2
),},
2794 {CLASS_BIT
+0xb,CLASS_BIT
+3,CLASS_REG
+(ARG_RD
),CLASS_BIT_1OR2
+8,0,0,0,0,0,},2,2,123},
2796 /* 1011 0010 dddd 10I0 *** rlcb rbd,imm1or2 */
2799 "rlcb rbd,imm1or2",8,9,0x10,
2801 "rlcb",OPC_rlcb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IMM
+(ARG_IMM1OR2
),},
2802 {CLASS_BIT
+0xb,CLASS_BIT
+2,CLASS_REG
+(ARG_RD
),CLASS_BIT_1OR2
+8,0,0,0,0,0,},2,2,124},
2804 /* 1011 1110 aaaa bbbb *** rldb rbb,rba */
2807 "rldb rbb,rba",8,9,0x10,
2809 "rldb",OPC_rldb
,0,{CLASS_REG_BYTE
+(ARG_RB
),CLASS_REG_BYTE
+(ARG_RA
),},
2810 {CLASS_BIT
+0xb,CLASS_BIT
+0xe,CLASS_REG
+(ARG_RA
),CLASS_REG
+(ARG_RB
),0,0,0,0,0,},2,2,125},
2812 /* 1011 0011 dddd 01I0 *** rr rd,imm1or2 */
2815 "rr rd,imm1or2",16,6,0x3c,
2817 "rr",OPC_rr
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IMM
+(ARG_IMM1OR2
),},
2818 {CLASS_BIT
+0xb,CLASS_BIT
+3,CLASS_REG
+(ARG_RD
),CLASS_BIT_1OR2
+4,0,0,0,0,0,},2,2,126},
2820 /* 1011 0010 dddd 01I0 *** rrb rbd,imm1or2 */
2823 "rrb rbd,imm1or2",8,6,0x3c,
2825 "rrb",OPC_rrb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IMM
+(ARG_IMM1OR2
),},
2826 {CLASS_BIT
+0xb,CLASS_BIT
+2,CLASS_REG
+(ARG_RD
),CLASS_BIT_1OR2
+4,0,0,0,0,0,},2,2,127},
2828 /* 1011 0011 dddd 11I0 *** rrc rd,imm1or2 */
2831 "rrc rd,imm1or2",16,6,0x3c,
2833 "rrc",OPC_rrc
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IMM
+(ARG_IMM1OR2
),},
2834 {CLASS_BIT
+0xb,CLASS_BIT
+3,CLASS_REG
+(ARG_RD
),CLASS_BIT_1OR2
+0xc,0,0,0,0,0,},2,2,128},
2836 /* 1011 0010 dddd 11I0 *** rrcb rbd,imm1or2 */
2839 "rrcb rbd,imm1or2",8,9,0x10,
2841 "rrcb",OPC_rrcb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IMM
+(ARG_IMM1OR2
),},
2842 {CLASS_BIT
+0xb,CLASS_BIT
+2,CLASS_REG
+(ARG_RD
),CLASS_BIT_1OR2
+0xc,0,0,0,0,0,},2,2,129},
2844 /* 1011 1100 aaaa bbbb *** rrdb rbb,rba */
2847 "rrdb rbb,rba",8,9,0x10,
2849 "rrdb",OPC_rrdb
,0,{CLASS_REG_BYTE
+(ARG_RB
),CLASS_REG_BYTE
+(ARG_RA
),},
2850 {CLASS_BIT
+0xb,CLASS_BIT
+0xc,CLASS_REG
+(ARG_RA
),CLASS_REG
+(ARG_RB
),0,0,0,0,0,},2,2,130},
2852 /* 0011 0110 imm8 *** rsvd36 */
2857 "rsvd36",OPC_rsvd36
,0,{0},
2858 {CLASS_BIT
+3,CLASS_BIT
+6,CLASS_IMM
+(ARG_IMM8
),0,0,0,0,0,0,},0,2,131},
2860 /* 0011 1000 imm8 *** rsvd38 */
2865 "rsvd38",OPC_rsvd38
,0,{0},
2866 {CLASS_BIT
+3,CLASS_BIT
+8,CLASS_IMM
+(ARG_IMM8
),0,0,0,0,0,0,},0,2,132},
2868 /* 0111 1000 imm8 *** rsvd78 */
2873 "rsvd78",OPC_rsvd78
,0,{0},
2874 {CLASS_BIT
+7,CLASS_BIT
+8,CLASS_IMM
+(ARG_IMM8
),0,0,0,0,0,0,},0,2,133},
2876 /* 0111 1110 imm8 *** rsvd7e */
2881 "rsvd7e",OPC_rsvd7e
,0,{0},
2882 {CLASS_BIT
+7,CLASS_BIT
+0xe,CLASS_IMM
+(ARG_IMM8
),0,0,0,0,0,0,},0,2,134},
2884 /* 1001 1101 imm8 *** rsvd9d */
2889 "rsvd9d",OPC_rsvd9d
,0,{0},
2890 {CLASS_BIT
+9,CLASS_BIT
+0xd,CLASS_IMM
+(ARG_IMM8
),0,0,0,0,0,0,},0,2,135},
2892 /* 1001 1111 imm8 *** rsvd9f */
2897 "rsvd9f",OPC_rsvd9f
,0,{0},
2898 {CLASS_BIT
+9,CLASS_BIT
+0xf,CLASS_IMM
+(ARG_IMM8
),0,0,0,0,0,0,},0,2,136},
2900 /* 1011 1001 imm8 *** rsvdb9 */
2905 "rsvdb9",OPC_rsvdb9
,0,{0},
2906 {CLASS_BIT
+0xb,CLASS_BIT
+9,CLASS_IMM
+(ARG_IMM8
),0,0,0,0,0,0,},0,2,137},
2908 /* 1011 1111 imm8 *** rsvdbf */
2913 "rsvdbf",OPC_rsvdbf
,0,{0},
2914 {CLASS_BIT
+0xb,CLASS_BIT
+0xf,CLASS_IMM
+(ARG_IMM8
),0,0,0,0,0,0,},0,2,138},
2916 /* 1011 0111 ssss dddd *** sbc rd,rs */
2919 "sbc rd,rs",16,5,0x3c,
2921 "sbc",OPC_sbc
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
2922 {CLASS_BIT
+0xb,CLASS_BIT
+7,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,139},
2924 /* 1011 0110 ssss dddd *** sbcb rbd,rbs */
2927 "sbcb rbd,rbs",8,5,0x3f,
2929 "sbcb",OPC_sbcb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_REG_BYTE
+(ARG_RS
),},
2930 {CLASS_BIT
+0xb,CLASS_BIT
+6,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,140},
2932 /* 0111 1111 imm8 *** sc imm8 */
2935 "sc imm8",8,33,0x3f,
2937 "sc",OPC_sc
,0,{CLASS_IMM
+(ARG_IMM8
),},
2938 {CLASS_BIT
+7,CLASS_BIT
+0xf,CLASS_IMM
+(ARG_IMM8
),0,0,0,0,0,0,},1,2,141},
2940 /* 1011 0011 dddd 1011 0000 ssss 0000 0000 *** sda rd,rs */
2943 "sda rd,rs",16,15,0x3c,
2945 "sda",OPC_sda
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
2946 {CLASS_BIT
+0xb,CLASS_BIT
+3,CLASS_REG
+(ARG_RD
),CLASS_BIT
+0xb,CLASS_BIT
+0,CLASS_REG
+(ARG_RS
),CLASS_BIT
+0,CLASS_BIT
+0,0,},2,4,142},
2948 /* 1011 0010 dddd 1011 0000 ssss 0000 0000 *** sdab rbd,rs */
2951 "sdab rbd,rs",8,15,0x3c,
2953 "sdab",OPC_sdab
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
2954 {CLASS_BIT
+0xb,CLASS_BIT
+2,CLASS_REG
+(ARG_RD
),CLASS_BIT
+0xb,CLASS_BIT
+0,CLASS_REG
+(ARG_RS
),CLASS_BIT
+0,CLASS_BIT
+0,0,},2,4,143},
2956 /* 1011 0011 dddd 1111 0000 ssss 0000 0000 *** sdal rrd,rs */
2959 "sdal rrd,rs",32,15,0x3c,
2961 "sdal",OPC_sdal
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
2962 {CLASS_BIT
+0xb,CLASS_BIT
+3,CLASS_REG
+(ARG_RD
),CLASS_BIT
+0xf,CLASS_BIT
+0,CLASS_REG
+(ARG_RS
),CLASS_BIT
+0,CLASS_BIT
+0,0,},2,4,144},
2964 /* 1011 0011 dddd 0011 0000 ssss 0000 0000 *** sdl rd,rs */
2967 "sdl rd,rs",16,15,0x38,
2969 "sdl",OPC_sdl
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
2970 {CLASS_BIT
+0xb,CLASS_BIT
+3,CLASS_REG
+(ARG_RD
),CLASS_BIT
+3,CLASS_BIT
+0,CLASS_REG
+(ARG_RS
),CLASS_BIT
+0,CLASS_BIT
+0,0,},2,4,145},
2972 /* 1011 0010 dddd 0011 0000 ssss 0000 0000 *** sdlb rbd,rs */
2975 "sdlb rbd,rs",8,15,0x38,
2977 "sdlb",OPC_sdlb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
2978 {CLASS_BIT
+0xb,CLASS_BIT
+2,CLASS_REG
+(ARG_RD
),CLASS_BIT
+3,CLASS_BIT
+0,CLASS_REG
+(ARG_RS
),CLASS_BIT
+0,CLASS_BIT
+0,0,},2,4,146},
2980 /* 1011 0011 dddd 0111 0000 ssss 0000 0000 *** sdll rrd,rs */
2983 "sdll rrd,rs",32,15,0x38,
2985 "sdll",OPC_sdll
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
2986 {CLASS_BIT
+0xb,CLASS_BIT
+3,CLASS_REG
+(ARG_RD
),CLASS_BIT
+7,CLASS_BIT
+0,CLASS_REG
+(ARG_RS
),CLASS_BIT
+0,CLASS_BIT
+0,0,},2,4,147},
2988 /* 0010 0101 ddN0 imm4 *** set @rd,imm4 */
2991 "set @rd,imm4",16,11,0x00,
2993 "set",OPC_set
,0,{CLASS_IR
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),},
2994 {CLASS_BIT
+2,CLASS_BIT
+5,CLASS_REGN0
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),0,0,0,0,0,},2,2,148},
2996 /* 0110 0101 ddN0 imm4 address_dst *** set address_dst(rd),imm4 */
2999 "set address_dst(rd),imm4",16,14,0x00,
3001 "set",OPC_set
,0,{CLASS_X
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),},
3002 {CLASS_BIT
+6,CLASS_BIT
+5,CLASS_REGN0
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,148},
3004 /* 0110 0101 0000 imm4 address_dst *** set address_dst,imm4 */
3007 "set address_dst,imm4",16,13,0x00,
3009 "set",OPC_set
,0,{CLASS_DA
+(ARG_DST
),CLASS_IMM
+(ARG_IMM4
),},
3010 {CLASS_BIT
+6,CLASS_BIT
+5,CLASS_BIT
+0,CLASS_IMM
+(ARG_IMM4
),CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,148},
3012 /* 1010 0101 dddd imm4 *** set rd,imm4 */
3015 "set rd,imm4",16,4,0x00,
3017 "set",OPC_set
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),},
3018 {CLASS_BIT
+0xa,CLASS_BIT
+5,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),0,0,0,0,0,},2,2,148},
3020 /* 0010 0101 0000 ssss 0000 dddd 0000 0000 *** set rd,rs */
3023 "set rd,rs",16,10,0x00,
3025 "set",OPC_set
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
3026 {CLASS_BIT
+2,CLASS_BIT
+5,CLASS_BIT
+0,CLASS_REG
+(ARG_RS
),CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_BIT
+0,CLASS_BIT
+0,0,},2,4,148},
3028 /* 0010 0100 ddN0 imm4 *** setb @rd,imm4 */
3031 "setb @rd,imm4",8,11,0x00,
3033 "setb",OPC_setb
,0,{CLASS_IR
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),},
3034 {CLASS_BIT
+2,CLASS_BIT
+4,CLASS_REGN0
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),0,0,0,0,0,},2,2,149},
3036 /* 0110 0100 ddN0 imm4 address_dst *** setb address_dst(rd),imm4 */
3039 "setb address_dst(rd),imm4",8,14,0x00,
3041 "setb",OPC_setb
,0,{CLASS_X
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),},
3042 {CLASS_BIT
+6,CLASS_BIT
+4,CLASS_REGN0
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,149},
3044 /* 0110 0100 0000 imm4 address_dst *** setb address_dst,imm4 */
3047 "setb address_dst,imm4",8,13,0x00,
3049 "setb",OPC_setb
,0,{CLASS_DA
+(ARG_DST
),CLASS_IMM
+(ARG_IMM4
),},
3050 {CLASS_BIT
+6,CLASS_BIT
+4,CLASS_BIT
+0,CLASS_IMM
+(ARG_IMM4
),CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},2,4,149},
3052 /* 1010 0100 dddd imm4 *** setb rbd,imm4 */
3055 "setb rbd,imm4",8,4,0x00,
3057 "setb",OPC_setb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),},
3058 {CLASS_BIT
+0xa,CLASS_BIT
+4,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),0,0,0,0,0,},2,2,149},
3060 /* 0010 0100 0000 ssss 0000 dddd 0000 0000 *** setb rbd,rs */
3063 "setb rbd,rs",8,10,0x00,
3065 "setb",OPC_setb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
3066 {CLASS_BIT
+2,CLASS_BIT
+4,CLASS_BIT
+0,CLASS_REG
+(ARG_RS
),CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_BIT
+0,CLASS_BIT
+0,0,},2,4,149},
3068 /* 1000 1101 flags 0001 *** setflg flags */
3071 "setflg flags",16,7,0x3c,
3073 "setflg",OPC_setflg
,0,{CLASS_FLAGS
,},
3074 {CLASS_BIT
+8,CLASS_BIT
+0xd,CLASS_FLAGS
,CLASS_BIT
+1,0,0,0,0,0,},1,2,150},
3076 /* 0011 1011 dddd 0101 imm16 *** sin rd,imm16 */
3079 "sin rd,imm16",16,12,0x00,
3081 "sin",OPC_sin
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),},
3082 {CLASS_BIT
+3,CLASS_BIT
+0xb,CLASS_REG
+(ARG_RD
),CLASS_BIT
+5,CLASS_IMM
+(ARG_IMM16
),0,0,0,0,},2,4,151},
3084 /* 0011 1010 dddd 0101 imm16 *** sinb rbd,imm16 */
3087 "sinb rbd,imm16",8,10,0x00,
3089 "sinb",OPC_sinb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),},
3090 {CLASS_BIT
+3,CLASS_BIT
+0xa,CLASS_REG
+(ARG_RD
),CLASS_BIT
+5,CLASS_IMM
+(ARG_IMM16
),0,0,0,0,},2,4,152},
3092 /* 0011 1011 ssss 1001 0000 aaaa ddN0 1000 *** sind @rd,@ri,ra */
3095 "sind @rd,@ri,ra",16,21,0x04,
3097 "sind",OPC_sind
,0,{CLASS_IR
+(ARG_RD
),CLASS_IRO
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
3098 {CLASS_BIT
+3,CLASS_BIT
+0xb,CLASS_REG
+(ARG_RS
),CLASS_BIT
+9,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+8,0,},3,4,153},
3100 /* 0011 1010 ssss 1001 0000 aaaa ddN0 1000 *** sindb @rd,@ri,ra */
3103 "sindb @rd,@ri,ra",8,21,0x04,
3105 "sindb",OPC_sindb
,0,{CLASS_IR
+(ARG_RD
),CLASS_IRO
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
3106 {CLASS_BIT
+3,CLASS_BIT
+0xa,CLASS_REG
+(ARG_RS
),CLASS_BIT
+9,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+8,0,},3,4,154},
3108 /* 0011 1011 ssss 1001 0000 aaaa ddN0 0000 *** sindr @rd,@ri,ra */
3111 "sindr @rd,@ri,ra",16,11,0x04,
3113 "sindr",OPC_sindr
,0,{CLASS_IR
+(ARG_RD
),CLASS_IRO
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
3114 {CLASS_BIT
+3,CLASS_BIT
+0xb,CLASS_REG
+(ARG_RS
),CLASS_BIT
+9,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+0,0,},3,4,155},
3116 /* 0011 1010 ssss 1001 0000 aaaa ddN0 0000 *** sindrb @rd,@ri,ra */
3119 "sindrb @rd,@ri,ra",8,11,0x04,
3121 "sindrb",OPC_sindrb
,0,{CLASS_IR
+(ARG_RD
),CLASS_IRO
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
3122 {CLASS_BIT
+3,CLASS_BIT
+0xa,CLASS_REG
+(ARG_RS
),CLASS_BIT
+9,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+0,0,},3,4,156},
3124 /* 0011 1011 ssss 0001 0000 aaaa ddN0 1000 *** sini @rd,@ri,ra */
3127 "sini @rd,@ri,ra",16,21,0x04,
3129 "sini",OPC_sini
,0,{CLASS_IR
+(ARG_RD
),CLASS_IRO
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
3130 {CLASS_BIT
+3,CLASS_BIT
+0xb,CLASS_REG
+(ARG_RS
),CLASS_BIT
+1,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+8,0,},3,4,157},
3132 /* 0011 1010 ssss 0001 0000 aaaa ddN0 1000 *** sinib @rd,@ri,ra */
3135 "sinib @rd,@ri,ra",8,21,0x04,
3137 "sinib",OPC_sinib
,0,{CLASS_IR
+(ARG_RD
),CLASS_IRO
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
3138 {CLASS_BIT
+3,CLASS_BIT
+0xa,CLASS_REG
+(ARG_RS
),CLASS_BIT
+1,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+8,0,},3,4,158},
3140 /* 0011 1011 ssss 0001 0000 aaaa ddN0 0000 *** sinir @rd,@ri,ra */
3143 "sinir @rd,@ri,ra",16,11,0x04,
3145 "sinir",OPC_sinir
,0,{CLASS_IR
+(ARG_RD
),CLASS_IRO
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
3146 {CLASS_BIT
+3,CLASS_BIT
+0xb,CLASS_REG
+(ARG_RS
),CLASS_BIT
+1,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+0,0,},3,4,159},
3148 /* 0011 1010 ssss 0001 0000 aaaa ddN0 0000 *** sinirb @rd,@ri,ra */
3151 "sinirb @rd,@ri,ra",8,11,0x04,
3153 "sinirb",OPC_sinirb
,0,{CLASS_IR
+(ARG_RD
),CLASS_IRO
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
3154 {CLASS_BIT
+3,CLASS_BIT
+0xa,CLASS_REG
+(ARG_RS
),CLASS_BIT
+1,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+0,0,},3,4,160},
3156 /* 1011 0011 dddd 1001 0000 0000 imm8 *** sla rd,imm8 */
3159 "sla rd,imm8",16,13,0x3c,
3161 "sla",OPC_sla
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IMM
+(ARG_IMM8
),},
3162 {CLASS_BIT
+0xb,CLASS_BIT
+3,CLASS_REG
+(ARG_RD
),CLASS_BIT
+9,CLASS_BIT
+0,CLASS_BIT
+0,CLASS_IMM
+(ARG_IMM8
),0,0,},2,4,161},
3164 /* 1011 0010 dddd 1001 iiii iiii 0000 imm4 *** slab rbd,imm4 */
3167 "slab rbd,imm4",8,13,0x3c,
3169 "slab",OPC_slab
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),},
3170 {CLASS_BIT
+0xb,CLASS_BIT
+2,CLASS_REG
+(ARG_RD
),CLASS_BIT
+9,CLASS_IGNORE
,CLASS_IGNORE
,CLASS_BIT
+0,CLASS_IMM
+(ARG_IMM4
),0,},2,4,162},
3172 /* 1011 0011 dddd 1101 0000 0000 imm8 *** slal rrd,imm8 */
3175 "slal rrd,imm8",32,13,0x3c,
3177 "slal",OPC_slal
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM8
),},
3178 {CLASS_BIT
+0xb,CLASS_BIT
+3,CLASS_REG
+(ARG_RD
),CLASS_BIT
+0xd,CLASS_BIT
+0,CLASS_BIT
+0,CLASS_IMM
+(ARG_IMM8
),0,0,},2,4,163},
3180 /* 1011 0011 dddd 0001 0000 0000 imm8 *** sll rd,imm8 */
3183 "sll rd,imm8",16,13,0x38,
3185 "sll",OPC_sll
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IMM
+(ARG_IMM8
),},
3186 {CLASS_BIT
+0xb,CLASS_BIT
+3,CLASS_REG
+(ARG_RD
),CLASS_BIT
+1,CLASS_BIT
+0,CLASS_BIT
+0,CLASS_IMM
+(ARG_IMM8
),0,0,},2,4,164},
3188 /* 1011 0010 dddd 0001 iiii iiii 0000 imm4 *** sllb rbd,imm4 */
3191 "sllb rbd,imm4",8,13,0x38,
3193 "sllb",OPC_sllb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),},
3194 {CLASS_BIT
+0xb,CLASS_BIT
+2,CLASS_REG
+(ARG_RD
),CLASS_BIT
+1,CLASS_IGNORE
,CLASS_IGNORE
,CLASS_BIT
+0,CLASS_IMM
+(ARG_IMM4
),0,},2,4,165},
3196 /* 1011 0011 dddd 0101 0000 0000 imm8 *** slll rrd,imm8 */
3199 "slll rrd,imm8",32,13,0x38,
3201 "slll",OPC_slll
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM8
),},
3202 {CLASS_BIT
+0xb,CLASS_BIT
+3,CLASS_REG
+(ARG_RD
),CLASS_BIT
+5,CLASS_BIT
+0,CLASS_BIT
+0,CLASS_IMM
+(ARG_IMM8
),0,0,},2,4,166},
3204 /* 0011 1011 ssN0 1011 0000 aaaa dddd 0000 *** sotdr @ro,@rs,ra */
3207 "sotdr @ro,@rs,ra",16,11,0x04,
3209 "sotdr",OPC_sotdr
,0,{CLASS_IRO
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
3210 {CLASS_BIT
+3,CLASS_BIT
+0xb,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+0xb,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REG
+(ARG_RD
),CLASS_BIT
+0,0,},3,4,167},
3212 /* 0011 1010 ssN0 1011 0000 aaaa dddd 0000 *** sotdrb @ro,@rs,ra */
3215 "sotdrb @ro,@rs,ra",8,11,0x04,
3217 "sotdrb",OPC_sotdrb
,0,{CLASS_IRO
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
3218 {CLASS_BIT
+3,CLASS_BIT
+0xa,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+0xb,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REG
+(ARG_RD
),CLASS_BIT
+0,0,},3,4,168},
3220 /* 0011 1011 ssN0 0011 0000 aaaa dddd 0000 *** sotir @ro,@rs,ra */
3223 "sotir @ro,@rs,ra",16,11,0x04,
3225 "sotir",OPC_sotir
,0,{CLASS_IRO
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
3226 {CLASS_BIT
+3,CLASS_BIT
+0xb,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+3,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REG
+(ARG_RD
),CLASS_BIT
+0,0,},3,4,169},
3228 /* 0011 1010 ssN0 0011 0000 aaaa dddd 0000 *** sotirb @ro,@rs,ra */
3231 "sotirb @ro,@rs,ra",8,11,0x04,
3233 "sotirb",OPC_sotirb
,0,{CLASS_IRO
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
3234 {CLASS_BIT
+3,CLASS_BIT
+0xa,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+3,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REG
+(ARG_RD
),CLASS_BIT
+0,0,},3,4,170},
3236 /* 0011 1011 ssss 0110 imm16 *** sout imm16,rs */
3239 "sout imm16,rs",16,12,0x00,
3241 "sout",OPC_sout
,0,{CLASS_IMM
+(ARG_IMM16
),CLASS_REG_WORD
+(ARG_RS
),},
3242 {CLASS_BIT
+3,CLASS_BIT
+0xb,CLASS_REG
+(ARG_RS
),CLASS_BIT
+6,CLASS_IMM
+(ARG_IMM16
),0,0,0,0,},2,4,171},
3244 /* 0011 1010 ssss 0110 imm16 *** soutb imm16,rbs */
3247 "soutb imm16,rbs",8,12,0x00,
3249 "soutb",OPC_soutb
,0,{CLASS_IMM
+(ARG_IMM16
),CLASS_REG_BYTE
+(ARG_RS
),},
3250 {CLASS_BIT
+3,CLASS_BIT
+0xa,CLASS_REG
+(ARG_RS
),CLASS_BIT
+6,CLASS_IMM
+(ARG_IMM16
),0,0,0,0,},2,4,172},
3252 /* 0011 1011 ssN0 1011 0000 aaaa dddd 1000 *** soutd @ro,@rs,ra */
3255 "soutd @ro,@rs,ra",16,21,0x04,
3257 "soutd",OPC_soutd
,0,{CLASS_IRO
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
3258 {CLASS_BIT
+3,CLASS_BIT
+0xb,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+0xb,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REG
+(ARG_RD
),CLASS_BIT
+8,0,},3,4,173},
3260 /* 0011 1010 ssN0 1011 0000 aaaa dddd 1000 *** soutdb @ro,@rs,ra */
3263 "soutdb @ro,@rs,ra",8,21,0x04,
3265 "soutdb",OPC_soutdb
,0,{CLASS_IRO
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
3266 {CLASS_BIT
+3,CLASS_BIT
+0xa,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+0xb,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REG
+(ARG_RD
),CLASS_BIT
+8,0,},3,4,174},
3268 /* 0011 1011 ssN0 0011 0000 aaaa dddd 1000 *** souti @ro,@rs,ra */
3271 "souti @ro,@rs,ra",16,21,0x04,
3273 "souti",OPC_souti
,0,{CLASS_IRO
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
3274 {CLASS_BIT
+3,CLASS_BIT
+0xb,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+3,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REG
+(ARG_RD
),CLASS_BIT
+8,0,},3,4,175},
3276 /* 0011 1010 ssN0 0011 0000 aaaa dddd 1000 *** soutib @ro,@rs,ra */
3279 "soutib @ro,@rs,ra",8,21,0x04,
3281 "soutib",OPC_soutib
,0,{CLASS_IRO
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_WORD
+(ARG_RA
),},
3282 {CLASS_BIT
+3,CLASS_BIT
+0xa,CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+3,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REG
+(ARG_RD
),CLASS_BIT
+8,0,},3,4,176},
3284 /* 1011 0011 dddd 1001 1111 1111 nim8 *** sra rd,imm8 */
3287 "sra rd,imm8",16,13,0x3c,
3289 "sra",OPC_sra
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IMM
+(ARG_IMM8
),},
3290 {CLASS_BIT
+0xb,CLASS_BIT
+3,CLASS_REG
+(ARG_RD
),CLASS_BIT
+9,CLASS_BIT
+0xf,CLASS_BIT
+0xf,CLASS_IMM
+(ARG_NIM8
),0,0,},2,4,177},
3292 /* 1011 0010 dddd 1001 iiii iiii 1111 nim4 *** srab rbd,imm4 */
3295 "srab rbd,imm4",8,13,0x3c,
3297 "srab",OPC_srab
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),},
3298 {CLASS_BIT
+0xb,CLASS_BIT
+2,CLASS_REG
+(ARG_RD
),CLASS_BIT
+9,CLASS_IGNORE
,CLASS_IGNORE
,CLASS_BIT
+0xf,CLASS_IMM
+(ARG_NIM4
),0,},2,4,178},
3300 /* 1011 0011 dddd 1101 1111 1111 nim8 *** sral rrd,imm8 */
3303 "sral rrd,imm8",32,13,0x3c,
3305 "sral",OPC_sral
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM8
),},
3306 {CLASS_BIT
+0xb,CLASS_BIT
+3,CLASS_REG
+(ARG_RD
),CLASS_BIT
+0xd,CLASS_BIT
+0xf,CLASS_BIT
+0xf,CLASS_IMM
+(ARG_NIM8
),0,0,},2,4,179},
3308 /* 1011 0011 dddd 0001 1111 1111 nim8 *** srl rd,imm8 */
3311 "srl rd,imm8",16,13,0x3c,
3313 "srl",OPC_srl
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IMM
+(ARG_IMM8
),},
3314 {CLASS_BIT
+0xb,CLASS_BIT
+3,CLASS_REG
+(ARG_RD
),CLASS_BIT
+1,CLASS_BIT
+0xf,CLASS_BIT
+0xf,CLASS_IMM
+(ARG_NIM8
),0,0,},2,4,180},
3316 /* 1011 0010 dddd 0001 iiii iiii 1111 nim4 *** srlb rbd,imm4 */
3319 "srlb rbd,imm4",8,13,0x3c,
3321 "srlb",OPC_srlb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IMM
+(ARG_IMM4
),},
3322 {CLASS_BIT
+0xb,CLASS_BIT
+2,CLASS_REG
+(ARG_RD
),CLASS_BIT
+1,CLASS_IGNORE
,CLASS_IGNORE
,CLASS_BIT
+0xf,CLASS_IMM
+(ARG_NIM4
),0,},2,4,181},
3324 /* 1011 0011 dddd 0101 1111 1111 nim8 *** srll rrd,imm8 */
3327 "srll rrd,imm8",32,13,0x3c,
3329 "srll",OPC_srll
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM8
),},
3330 {CLASS_BIT
+0xb,CLASS_BIT
+3,CLASS_REG
+(ARG_RD
),CLASS_BIT
+5,CLASS_BIT
+0xf,CLASS_BIT
+0xf,CLASS_IMM
+(ARG_NIM8
),0,0,},2,4,182},
3332 /* 0000 0011 ssN0 dddd *** sub rd,@rs */
3335 "sub rd,@rs",16,7,0x3c,
3337 "sub",OPC_sub
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
3338 {CLASS_BIT
+0,CLASS_BIT
+3,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,183},
3340 /* 0100 0011 0000 dddd address_src *** sub rd,address_src */
3343 "sub rd,address_src",16,9,0x3c,
3345 "sub",OPC_sub
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_DA
+(ARG_SRC
),},
3346 {CLASS_BIT
+4,CLASS_BIT
+3,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,183},
3348 /* 0100 0011 ssN0 dddd address_src *** sub rd,address_src(rs) */
3351 "sub rd,address_src(rs)",16,10,0x3c,
3353 "sub",OPC_sub
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_X
+(ARG_RS
),},
3354 {CLASS_BIT
+4,CLASS_BIT
+3,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,183},
3356 /* 0000 0011 0000 dddd imm16 *** sub rd,imm16 */
3359 "sub rd,imm16",16,7,0x3c,
3361 "sub",OPC_sub
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),},
3362 {CLASS_BIT
+0,CLASS_BIT
+3,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),0,0,0,0,},2,4,183},
3364 /* 1000 0011 ssss dddd *** sub rd,rs */
3367 "sub rd,rs",16,4,0x3c,
3369 "sub",OPC_sub
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
3370 {CLASS_BIT
+8,CLASS_BIT
+3,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,183},
3372 /* 0000 0010 ssN0 dddd *** subb rbd,@rs */
3375 "subb rbd,@rs",8,7,0x3f,
3377 "subb",OPC_subb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
3378 {CLASS_BIT
+0,CLASS_BIT
+2,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,184},
3380 /* 0100 0010 0000 dddd address_src *** subb rbd,address_src */
3383 "subb rbd,address_src",8,9,0x3f,
3385 "subb",OPC_subb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_DA
+(ARG_SRC
),},
3386 {CLASS_BIT
+4,CLASS_BIT
+2,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,184},
3388 /* 0100 0010 ssN0 dddd address_src *** subb rbd,address_src(rs) */
3391 "subb rbd,address_src(rs)",8,10,0x3f,
3393 "subb",OPC_subb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_X
+(ARG_RS
),},
3394 {CLASS_BIT
+4,CLASS_BIT
+2,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,184},
3396 /* 0000 0010 0000 dddd imm8 imm8 *** subb rbd,imm8 */
3399 "subb rbd,imm8",8,7,0x3f,
3401 "subb",OPC_subb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IMM
+(ARG_IMM8
),},
3402 {CLASS_BIT
+0,CLASS_BIT
+2,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM8
),CLASS_IMM
+(ARG_IMM8
),0,0,0,},2,4,184},
3404 /* 1000 0010 ssss dddd *** subb rbd,rbs */
3407 "subb rbd,rbs",8,4,0x3f,
3409 "subb",OPC_subb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_REG_BYTE
+(ARG_RS
),},
3410 {CLASS_BIT
+8,CLASS_BIT
+2,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,184},
3412 /* 0001 0010 ssN0 dddd *** subl rrd,@rs */
3415 "subl rrd,@rs",32,14,0x3c,
3417 "subl",OPC_subl
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
3418 {CLASS_BIT
+1,CLASS_BIT
+2,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,185},
3420 /* 0101 0010 0000 dddd address_src *** subl rrd,address_src */
3423 "subl rrd,address_src",32,15,0x3c,
3425 "subl",OPC_subl
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_DA
+(ARG_SRC
),},
3426 {CLASS_BIT
+5,CLASS_BIT
+2,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,185},
3428 /* 0101 0010 ssN0 dddd address_src *** subl rrd,address_src(rs) */
3431 "subl rrd,address_src(rs)",32,16,0x3c,
3433 "subl",OPC_subl
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_X
+(ARG_RS
),},
3434 {CLASS_BIT
+5,CLASS_BIT
+2,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,185},
3436 /* 0001 0010 0000 dddd imm32 *** subl rrd,imm32 */
3439 "subl rrd,imm32",32,14,0x3c,
3441 "subl",OPC_subl
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM32
),},
3442 {CLASS_BIT
+1,CLASS_BIT
+2,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM32
),0,0,0,0,},2,6,185},
3444 /* 1001 0010 ssss dddd *** subl rrd,rrs */
3447 "subl rrd,rrs",32,8,0x3c,
3449 "subl",OPC_subl
,0,{CLASS_REG_LONG
+(ARG_RD
),CLASS_REG_LONG
+(ARG_RS
),},
3450 {CLASS_BIT
+9,CLASS_BIT
+2,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,185},
3452 /* 1010 1111 dddd cccc *** tcc cc,rd */
3455 "tcc cc,rd",16,5,0x00,
3457 "tcc",OPC_tcc
,0,{CLASS_CC
,CLASS_REG_WORD
+(ARG_RD
),},
3458 {CLASS_BIT
+0xa,CLASS_BIT
+0xf,CLASS_REG
+(ARG_RD
),CLASS_CC
,0,0,0,0,0,},2,2,186},
3460 /* 1010 1110 dddd cccc *** tccb cc,rbd */
3463 "tccb cc,rbd",8,5,0x00,
3465 "tccb",OPC_tccb
,0,{CLASS_CC
,CLASS_REG_BYTE
+(ARG_RD
),},
3466 {CLASS_BIT
+0xa,CLASS_BIT
+0xe,CLASS_REG
+(ARG_RD
),CLASS_CC
,0,0,0,0,0,},2,2,187},
3468 /* 0000 1101 ddN0 0100 *** test @rd */
3471 "test @rd",16,8,0x18,
3473 "test",OPC_test
,0,{CLASS_IR
+(ARG_RD
),},
3474 {CLASS_BIT
+0,CLASS_BIT
+0xd,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+4,0,0,0,0,0,},1,2,188},
3476 /* 0100 1101 0000 0100 address_dst *** test address_dst */
3479 "test address_dst",16,11,0x00,
3481 "test",OPC_test
,0,{CLASS_DA
+(ARG_DST
),},
3482 {CLASS_BIT
+4,CLASS_BIT
+0xd,CLASS_BIT
+0,CLASS_BIT
+4,CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},1,4,188},
3484 /* 0100 1101 ddN0 0100 address_dst *** test address_dst(rd) */
3487 "test address_dst(rd)",16,12,0x00,
3489 "test",OPC_test
,0,{CLASS_X
+(ARG_RD
),},
3490 {CLASS_BIT
+4,CLASS_BIT
+0xd,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+4,CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},1,4,188},
3492 /* 1000 1101 dddd 0100 *** test rd */
3495 "test rd",16,7,0x00,
3497 "test",OPC_test
,0,{CLASS_REG_WORD
+(ARG_RD
),},
3498 {CLASS_BIT
+8,CLASS_BIT
+0xd,CLASS_REG
+(ARG_RD
),CLASS_BIT
+4,0,0,0,0,0,},1,2,188},
3500 /* 0000 1100 ddN0 0100 *** testb @rd */
3503 "testb @rd",8,8,0x1c,
3505 "testb",OPC_testb
,0,{CLASS_IR
+(ARG_RD
),},
3506 {CLASS_BIT
+0,CLASS_BIT
+0xc,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+4,0,0,0,0,0,},1,2,189},
3508 /* 0100 1100 0000 0100 address_dst *** testb address_dst */
3511 "testb address_dst",8,11,0x1c,
3513 "testb",OPC_testb
,0,{CLASS_DA
+(ARG_DST
),},
3514 {CLASS_BIT
+4,CLASS_BIT
+0xc,CLASS_BIT
+0,CLASS_BIT
+4,CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},1,4,189},
3516 /* 0100 1100 ddN0 0100 address_dst *** testb address_dst(rd) */
3519 "testb address_dst(rd)",8,12,0x1c,
3521 "testb",OPC_testb
,0,{CLASS_X
+(ARG_RD
),},
3522 {CLASS_BIT
+4,CLASS_BIT
+0xc,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+4,CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},1,4,189},
3524 /* 1000 1100 dddd 0100 *** testb rbd */
3527 "testb rbd",8,7,0x1c,
3529 "testb",OPC_testb
,0,{CLASS_REG_BYTE
+(ARG_RD
),},
3530 {CLASS_BIT
+8,CLASS_BIT
+0xc,CLASS_REG
+(ARG_RD
),CLASS_BIT
+4,0,0,0,0,0,},1,2,189},
3532 /* 0001 1100 ddN0 1000 *** testl @rd */
3535 "testl @rd",32,13,0x18,
3537 "testl",OPC_testl
,0,{CLASS_IR
+(ARG_RD
),},
3538 {CLASS_BIT
+1,CLASS_BIT
+0xc,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+8,0,0,0,0,0,},1,2,190},
3540 /* 0101 1100 0000 1000 address_dst *** testl address_dst */
3543 "testl address_dst",32,16,0x18,
3545 "testl",OPC_testl
,0,{CLASS_DA
+(ARG_DST
),},
3546 {CLASS_BIT
+5,CLASS_BIT
+0xc,CLASS_BIT
+0,CLASS_BIT
+8,CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},1,4,190},
3548 /* 0101 1100 ddN0 1000 address_dst *** testl address_dst(rd) */
3551 "testl address_dst(rd)",32,17,0x18,
3553 "testl",OPC_testl
,0,{CLASS_X
+(ARG_RD
),},
3554 {CLASS_BIT
+5,CLASS_BIT
+0xc,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+8,CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},1,4,190},
3556 /* 1001 1100 dddd 1000 *** testl rrd */
3559 "testl rrd",32,13,0x18,
3561 "testl",OPC_testl
,0,{CLASS_REG_LONG
+(ARG_RD
),},
3562 {CLASS_BIT
+9,CLASS_BIT
+0xc,CLASS_REG
+(ARG_RD
),CLASS_BIT
+8,0,0,0,0,0,},1,2,190},
3564 /* 1011 1000 ddN0 1000 0000 aaaa ssN0 0000 *** trdb @rd,@rs,rba */
3567 "trdb @rd,@rs,rba",8,25,0x1c,
3569 "trdb",OPC_trdb
,0,{CLASS_IR
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_BYTE
+(ARG_RA
),},
3570 {CLASS_BIT
+0xb,CLASS_BIT
+8,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+8,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+0,0,},3,4,191},
3572 /* 1011 1000 ddN0 1100 0000 aaaa ssN0 0000 *** trdrb @rd,@rs,rba */
3575 "trdrb @rd,@rs,rba",8,25,0x1c,
3577 "trdrb",OPC_trdrb
,0,{CLASS_IR
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_BYTE
+(ARG_RA
),},
3578 {CLASS_BIT
+0xb,CLASS_BIT
+8,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+0xc,CLASS_BIT
+0,CLASS_REG
+(ARG_RA
),CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+0,0,},3,4,192},
3580 /* 1011 1000 ddN0 0000 0000 rrrr ssN0 0000 *** trib @rd,@rs,rbr */
3583 "trib @rd,@rs,rbr",8,25,0x1c,
3585 "trib",OPC_trib
,0,{CLASS_IR
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_BYTE
+(ARG_RR
),},
3586 {CLASS_BIT
+0xb,CLASS_BIT
+8,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+0,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+0,0,},3,4,193},
3588 /* 1011 1000 ddN0 0100 0000 rrrr ssN0 0000 *** trirb @rd,@rs,rbr */
3591 "trirb @rd,@rs,rbr",8,25,0x1c,
3593 "trirb",OPC_trirb
,0,{CLASS_IR
+(ARG_RD
),CLASS_IR
+(ARG_RS
),CLASS_REG_BYTE
+(ARG_RR
),},
3594 {CLASS_BIT
+0xb,CLASS_BIT
+8,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+4,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REGN0
+(ARG_RS
),CLASS_BIT
+0,0,},3,4,194},
3596 /* 1011 1000 aaN0 1010 0000 rrrr bbN0 0000 *** trtdb @ra,@rb,rbr */
3599 "trtdb @ra,@rb,rbr",8,25,0x1c,
3601 "trtdb",OPC_trtdb
,0,{CLASS_IR
+(ARG_RA
),CLASS_IR
+(ARG_RB
),CLASS_REG_BYTE
+(ARG_RR
),},
3602 {CLASS_BIT
+0xb,CLASS_BIT
+8,CLASS_REGN0
+(ARG_RA
),CLASS_BIT
+0xa,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REGN0
+(ARG_RB
),CLASS_BIT
+0,0,},3,4,195},
3604 /* 1011 1000 aaN0 1110 0000 rrrr bbN0 1110 *** trtdrb @ra,@rb,rbr */
3607 "trtdrb @ra,@rb,rbr",8,25,0x1c,
3609 "trtdrb",OPC_trtdrb
,0,{CLASS_IR
+(ARG_RA
),CLASS_IR
+(ARG_RB
),CLASS_REG_BYTE
+(ARG_RR
),},
3610 {CLASS_BIT
+0xb,CLASS_BIT
+8,CLASS_REGN0
+(ARG_RA
),CLASS_BIT
+0xe,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REGN0
+(ARG_RB
),CLASS_BIT
+0xe,0,},3,4,196},
3612 /* 1011 1000 aaN0 0010 0000 rrrr bbN0 0000 *** trtib @ra,@rb,rbr */
3615 "trtib @ra,@rb,rbr",8,25,0x1c,
3617 "trtib",OPC_trtib
,0,{CLASS_IR
+(ARG_RA
),CLASS_IR
+(ARG_RB
),CLASS_REG_BYTE
+(ARG_RR
),},
3618 {CLASS_BIT
+0xb,CLASS_BIT
+8,CLASS_REGN0
+(ARG_RA
),CLASS_BIT
+2,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REGN0
+(ARG_RB
),CLASS_BIT
+0,0,},3,4,197},
3620 /* 1011 1000 aaN0 0110 0000 rrrr bbN0 1110 *** trtirb @ra,@rb,rbr */
3623 "trtirb @ra,@rb,rbr",8,25,0x1c,
3625 "trtirb",OPC_trtirb
,0,{CLASS_IR
+(ARG_RA
),CLASS_IR
+(ARG_RB
),CLASS_REG_BYTE
+(ARG_RR
),},
3626 {CLASS_BIT
+0xb,CLASS_BIT
+8,CLASS_REGN0
+(ARG_RA
),CLASS_BIT
+6,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REGN0
+(ARG_RB
),CLASS_BIT
+0xe,0,},3,4,198},
3628 /* 1011 1000 aaN0 1010 0000 rrrr bbN0 0000 *** trtrb @ra,@rb,rbr */
3631 "trtrb @ra,@rb,rbr",8,25,0x1c,
3633 "trtrb",OPC_trtrb
,0,{CLASS_IR
+(ARG_RA
),CLASS_IR
+(ARG_RB
),CLASS_REG_BYTE
+(ARG_RR
),},
3634 {CLASS_BIT
+0xb,CLASS_BIT
+8,CLASS_REGN0
+(ARG_RA
),CLASS_BIT
+0xa,CLASS_BIT
+0,CLASS_REG
+(ARG_RR
),CLASS_REGN0
+(ARG_RB
),CLASS_BIT
+0,0,},3,4,199},
3636 /* 0000 1101 ddN0 0110 *** tset @rd */
3639 "tset @rd",16,11,0x08,
3641 "tset",OPC_tset
,0,{CLASS_IR
+(ARG_RD
),},
3642 {CLASS_BIT
+0,CLASS_BIT
+0xd,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+6,0,0,0,0,0,},1,2,200},
3644 /* 0100 1101 0000 0110 address_dst *** tset address_dst */
3647 "tset address_dst",16,14,0x08,
3649 "tset",OPC_tset
,0,{CLASS_DA
+(ARG_DST
),},
3650 {CLASS_BIT
+4,CLASS_BIT
+0xd,CLASS_BIT
+0,CLASS_BIT
+6,CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},1,4,200},
3652 /* 0100 1101 ddN0 0110 address_dst *** tset address_dst(rd) */
3655 "tset address_dst(rd)",16,15,0x08,
3657 "tset",OPC_tset
,0,{CLASS_X
+(ARG_RD
),},
3658 {CLASS_BIT
+4,CLASS_BIT
+0xd,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+6,CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},1,4,200},
3660 /* 1000 1101 dddd 0110 *** tset rd */
3663 "tset rd",16,7,0x08,
3665 "tset",OPC_tset
,0,{CLASS_REG_WORD
+(ARG_RD
),},
3666 {CLASS_BIT
+8,CLASS_BIT
+0xd,CLASS_REG
+(ARG_RD
),CLASS_BIT
+6,0,0,0,0,0,},1,2,200},
3668 /* 0000 1100 ddN0 0110 *** tsetb @rd */
3671 "tsetb @rd",8,11,0x08,
3673 "tsetb",OPC_tsetb
,0,{CLASS_IR
+(ARG_RD
),},
3674 {CLASS_BIT
+0,CLASS_BIT
+0xc,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+6,0,0,0,0,0,},1,2,201},
3676 /* 0100 1100 0000 0110 address_dst *** tsetb address_dst */
3679 "tsetb address_dst",8,14,0x08,
3681 "tsetb",OPC_tsetb
,0,{CLASS_DA
+(ARG_DST
),},
3682 {CLASS_BIT
+4,CLASS_BIT
+0xc,CLASS_BIT
+0,CLASS_BIT
+6,CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},1,4,201},
3684 /* 0100 1100 ddN0 0110 address_dst *** tsetb address_dst(rd) */
3687 "tsetb address_dst(rd)",8,15,0x08,
3689 "tsetb",OPC_tsetb
,0,{CLASS_X
+(ARG_RD
),},
3690 {CLASS_BIT
+4,CLASS_BIT
+0xc,CLASS_REGN0
+(ARG_RD
),CLASS_BIT
+6,CLASS_ADDRESS
+(ARG_DST
),0,0,0,0,},1,4,201},
3692 /* 1000 1100 dddd 0110 *** tsetb rbd */
3695 "tsetb rbd",8,7,0x08,
3697 "tsetb",OPC_tsetb
,0,{CLASS_REG_BYTE
+(ARG_RD
),},
3698 {CLASS_BIT
+8,CLASS_BIT
+0xc,CLASS_REG
+(ARG_RD
),CLASS_BIT
+6,0,0,0,0,0,},1,2,201},
3700 /* 0000 1001 ssN0 dddd *** xor rd,@rs */
3703 "xor rd,@rs",16,7,0x18,
3705 "xor",OPC_xor
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
3706 {CLASS_BIT
+0,CLASS_BIT
+9,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,202},
3708 /* 0100 1001 0000 dddd address_src *** xor rd,address_src */
3711 "xor rd,address_src",16,9,0x18,
3713 "xor",OPC_xor
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_DA
+(ARG_SRC
),},
3714 {CLASS_BIT
+4,CLASS_BIT
+9,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,202},
3716 /* 0100 1001 ssN0 dddd address_src *** xor rd,address_src(rs) */
3719 "xor rd,address_src(rs)",16,10,0x18,
3721 "xor",OPC_xor
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_X
+(ARG_RS
),},
3722 {CLASS_BIT
+4,CLASS_BIT
+9,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,202},
3724 /* 0000 1001 0000 dddd imm16 *** xor rd,imm16 */
3727 "xor rd,imm16",16,7,0x18,
3729 "xor",OPC_xor
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),},
3730 {CLASS_BIT
+0,CLASS_BIT
+9,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM16
),0,0,0,0,},2,4,202},
3732 /* 1000 1001 ssss dddd *** xor rd,rs */
3735 "xor rd,rs",16,4,0x18,
3737 "xor",OPC_xor
,0,{CLASS_REG_WORD
+(ARG_RD
),CLASS_REG_WORD
+(ARG_RS
),},
3738 {CLASS_BIT
+8,CLASS_BIT
+9,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,202},
3740 /* 0000 1000 ssN0 dddd *** xorb rbd,@rs */
3743 "xorb rbd,@rs",8,7,0x1c,
3745 "xorb",OPC_xorb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IR
+(ARG_RS
),},
3746 {CLASS_BIT
+0,CLASS_BIT
+8,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,203},
3748 /* 0100 1000 0000 dddd address_src *** xorb rbd,address_src */
3751 "xorb rbd,address_src",8,9,0x1c,
3753 "xorb",OPC_xorb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_DA
+(ARG_SRC
),},
3754 {CLASS_BIT
+4,CLASS_BIT
+8,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,203},
3756 /* 0100 1000 ssN0 dddd address_src *** xorb rbd,address_src(rs) */
3759 "xorb rbd,address_src(rs)",8,10,0x1c,
3761 "xorb",OPC_xorb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_X
+(ARG_RS
),},
3762 {CLASS_BIT
+4,CLASS_BIT
+8,CLASS_REGN0
+(ARG_RS
),CLASS_REG
+(ARG_RD
),CLASS_ADDRESS
+(ARG_SRC
),0,0,0,0,},2,4,203},
3764 /* 0000 1000 0000 dddd imm8 imm8 *** xorb rbd,imm8 */
3767 "xorb rbd,imm8",8,7,0x1c,
3769 "xorb",OPC_xorb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_IMM
+(ARG_IMM8
),},
3770 {CLASS_BIT
+0,CLASS_BIT
+8,CLASS_BIT
+0,CLASS_REG
+(ARG_RD
),CLASS_IMM
+(ARG_IMM8
),CLASS_IMM
+(ARG_IMM8
),0,0,0,},2,4,203},
3772 /* 1000 1000 ssss dddd *** xorb rbd,rbs */
3775 "xorb rbd,rbs",8,4,0x1c,
3777 "xorb",OPC_xorb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_REG_BYTE
+(ARG_RS
),},
3778 {CLASS_BIT
+8,CLASS_BIT
+8,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,203},
3780 /* 1000 1000 ssss dddd *** xorb rbd,rbs */
3783 "xorb rbd,rbs",8,4,0x01,
3785 "xorb",OPC_xorb
,0,{CLASS_REG_BYTE
+(ARG_RD
),CLASS_REG_BYTE
+(ARG_RS
),},
3786 {CLASS_BIT
+8,CLASS_BIT
+8,CLASS_REG
+(ARG_RS
),CLASS_REG
+(ARG_RD
),0,0,0,0,0,},2,2,203},
3794 NULL
,0,0,{0,0,0,0},{0,0,0,0,0,0,0,0,0,0},0,0,0}