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* config/tc-xtensa.c (xg_translate_sysreg_op): Remove has_underbar
[binutils.git] / gas / config / tc-m68k.c
blob8b112631bd891e85d24bd63f46d39b0f6fc40874
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
21
22 #include "as.h"
23 #include "safe-ctype.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
31
32 #if defined (OBJ_ELF)
33 #include "elf/m68k.h"
34 #endif
35
36 #ifdef M68KCOFF
37 #include "obj-coff.h"
38 #endif
39
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars = "|#";
46 #else
47 const char *m68k_comment_chars = "|";
48 #endif
49
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars[] = "#*";
58
59 const char line_separator_chars[] = ";";
60
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS[] = "eE";
63
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
66
67 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
68
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
72
73 /* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
75 references. Not implemented. For ELF there are other means
76 to denote pic relocations. */
77 int flag_want_pic;
78
79 static int flag_short_refs; /* -l option. */
80 static int flag_long_jumps; /* -S option. */
81 static int flag_keep_pcrel; /* --pcrel option. */
82
83 #ifdef REGISTER_PREFIX_OPTIONAL
84 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
85 #else
86 int flag_reg_prefix_optional;
87 #endif
88
89 /* Whether --register-prefix-optional was used on the command line. */
90 static int reg_prefix_optional_seen;
91
92 /* The floating point coprocessor to use by default. */
93 static enum m68k_register m68k_float_copnum = COP1;
94
95 /* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97 static int m68k_abspcadd;
98
99 /* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101 static int m68k_quick = 1;
102
103 /* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
105 be 32 bits. */
106 static int m68k_rel32 = 1;
107
108 /* This is non-zero if m68k_rel32 was set from the command line. */
109 static int m68k_rel32_from_cmdline;
110
111 /* The default width to use for an index register when using a base
112 displacement. */
113 static enum m68k_size m68k_index_width_default = SIZE_LONG;
114
115 /* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
117 label. */
118 struct label_line
119 {
120 struct label_line *next;
121 symbolS *label;
122 char *file;
123 unsigned int line;
124 int text;
125 };
126
127 /* The list of labels. */
128
129 static struct label_line *labels;
130
131 /* The current label. */
132
133 static struct label_line *current_label;
134
135 /* Pointer to list holding the opcodes sorted by name. */
136 static struct m68k_opcode const ** m68k_sorted_opcodes;
137
138 /* Its an arbitrary name: This means I don't approve of it.
139 See flames below. */
140 static struct obstack robyn;
141
142 struct m68k_incant
143 {
144 const char *m_operands;
145 unsigned long m_opcode;
146 short m_opnum;
147 short m_codenum;
148 int m_arch;
149 struct m68k_incant *m_next;
150 };
151
152 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153 #define gettwo(x) (((x)->m_opcode)&0xffff)
154
155 static const enum m68k_register m68000_control_regs[] = { 0 };
156 static const enum m68k_register m68010_control_regs[] = {
157 SFC, DFC, USP, VBR,
158 0
159 };
160 static const enum m68k_register m68020_control_regs[] = {
161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
162 0
163 };
164 static const enum m68k_register m68040_control_regs[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
167 0
168 };
169 static const enum m68k_register m68060_control_regs[] = {
170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
172 0
173 };
174 static const enum m68k_register mcf_control_regs[] = {
175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
176 RAMBAR0, RAMBAR1, MBAR,
177 0
178 };
179 static const enum m68k_register mcf5208_control_regs[] = {
180 CACR, ACR0, ACR1, VBR, RAMBAR1,
181 0
182 };
183 static const enum m68k_register mcf5213_control_regs[] = {
184 VBR, RAMBAR, FLASHBAR,
185 0
186 };
187 static const enum m68k_register mcf5329_control_regs[] = {
188 CACR, ACR0, ACR1, VBR, RAMBAR,
189 0
190 };
191 static const enum m68k_register mcf5249_control_regs[] = {
192 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR1, MBAR, MBAR2,
193 0
194 };
195 static const enum m68k_register mcf528x_control_regs[] = {
196 CACR, ACR0, ACR1, VBR, FLASHBAR, RAMBAR,
197 0
198 };
199 static const enum m68k_register mcfv4e_control_regs[] = {
200 CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, VBR, PC, ROMBAR,
201 ROMBAR1, RAMBAR0, RAMBAR1, MPCR, EDRAMBAR, SECMBAR, MBAR, MBAR0, MBAR1,
202 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
203 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
204 0
205 };
206 #define cpu32_control_regs m68010_control_regs
207
208 static const enum m68k_register *control_regs;
209
210 /* Internal form of a 68020 instruction. */
211 struct m68k_it
212 {
213 const char *error;
214 const char *args; /* List of opcode info. */
215 int numargs;
216
217 int numo; /* Number of shorts in opcode. */
218 short opcode[11];
219
220 struct m68k_op operands[6];
221
222 int nexp; /* Number of exprs in use. */
223 struct m68k_exp exprs[4];
224
225 int nfrag; /* Number of frags we have to produce. */
226 struct
227 {
228 int fragoff; /* Where in the current opcode the frag ends. */
229 symbolS *fadd;
230 offsetT foff;
231 int fragty;
232 }
233 fragb[4];
234
235 int nrel; /* Num of reloc strucs in use. */
236 struct
237 {
238 int n;
239 expressionS exp;
240 char wid;
241 char pcrel;
242 /* In a pc relative address the difference between the address
243 of the offset and the address that the offset is relative
244 to. This depends on the addressing mode. Basically this
245 is the value to put in the offset field to address the
246 first byte of the offset, without regarding the special
247 significance of some values (in the branch instruction, for
248 example). */
249 int pcrel_fix;
250 #ifdef OBJ_ELF
251 /* Whether this expression needs special pic relocation, and if
252 so, which. */
253 enum pic_relocation pic_reloc;
254 #endif
255 }
256 reloc[5]; /* Five is enough??? */
257 };
258
259 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a))
260 #define float_of_arch(x) ((x) & mfloat)
261 #define mmu_of_arch(x) ((x) & mmmu)
262 #define arch_coldfire_p(x) ((x) & mcfisa_a)
263 #define arch_coldfire_fpu(x) ((x) & cfloat)
264
265 /* Macros for determining if cpu supports a specific addressing mode. */
266 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b))
267
268 static struct m68k_it the_ins; /* The instruction being assembled. */
269
270 #define op(ex) ((ex)->exp.X_op)
271 #define adds(ex) ((ex)->exp.X_add_symbol)
272 #define subs(ex) ((ex)->exp.X_op_symbol)
273 #define offs(ex) ((ex)->exp.X_add_number)
274
275 /* Macros for adding things to the m68k_it struct. */
276 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
277
278 /* Like addword, but goes BEFORE general operands. */
279
280 static void
281 insop (int w, const struct m68k_incant *opcode)
282 {
283 int z;
284 for (z = the_ins.numo; z > opcode->m_codenum; --z)
285 the_ins.opcode[z] = the_ins.opcode[z - 1];
286 for (z = 0; z < the_ins.nrel; z++)
287 the_ins.reloc[z].n += 2;
288 for (z = 0; z < the_ins.nfrag; z++)
289 the_ins.fragb[z].fragoff++;
290 the_ins.opcode[opcode->m_codenum] = w;
291 the_ins.numo++;
292 }
293
294 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
295 Blecch. */
296 static void
297 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
298 {
299 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
300 ? the_ins.numo * 2 - 1
301 : (width == 'b'
302 ? the_ins.numo * 2 + 1
303 : the_ins.numo * 2));
304 the_ins.reloc[the_ins.nrel].exp = exp->exp;
305 the_ins.reloc[the_ins.nrel].wid = width;
306 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
307 #ifdef OBJ_ELF
308 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
309 #endif
310 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
311 }
312
313 /* Cause an extra frag to be generated here, inserting up to 10 bytes
314 (that value is chosen in the frag_var call in md_assemble). TYPE
315 is the subtype of the frag to be generated; its primary type is
316 rs_machine_dependent.
317
318 The TYPE parameter is also used by md_convert_frag_1 and
319 md_estimate_size_before_relax. The appropriate type of fixup will
320 be emitted by md_convert_frag_1.
321
322 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
323 static void
324 add_frag (symbolS *add, offsetT off, int type)
325 {
326 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
327 the_ins.fragb[the_ins.nfrag].fadd = add;
328 the_ins.fragb[the_ins.nfrag].foff = off;
329 the_ins.fragb[the_ins.nfrag++].fragty = type;
330 }
331
332 #define isvar(ex) \
333 (op (ex) != O_constant && op (ex) != O_big)
334
335 static char *crack_operand (char *str, struct m68k_op *opP);
336 static int get_num (struct m68k_exp *exp, int ok);
337 static int reverse_16_bits (int in);
338 static int reverse_8_bits (int in);
339 static void install_gen_operand (int mode, int val);
340 static void install_operand (int mode, int val);
341 static void s_bss (int);
342 static void s_data1 (int);
343 static void s_data2 (int);
344 static void s_even (int);
345 static void s_proc (int);
346 static void s_chip (int);
347 static void s_fopt (int);
348 static void s_opt (int);
349 static void s_reg (int);
350 static void s_restore (int);
351 static void s_save (int);
352 static void s_mri_if (int);
353 static void s_mri_else (int);
354 static void s_mri_endi (int);
355 static void s_mri_break (int);
356 static void s_mri_next (int);
357 static void s_mri_for (int);
358 static void s_mri_endf (int);
359 static void s_mri_repeat (int);
360 static void s_mri_until (int);
361 static void s_mri_while (int);
362 static void s_mri_endw (int);
363 static void s_m68k_cpu (int);
364 static void s_m68k_arch (int);
365
366 struct m68k_cpu
367 {
368 unsigned long arch; /* Architecture features. */
369 unsigned long chip; /* Specific chip */
370 const char *name; /* Name */
371 int alias; /* Alias for a cannonical name. If 1, then
372 succeeds canonical name, if -1 then
373 succeeds canonical name, if <-1 ||>1 this is a
374 deprecated name, and the next/previous name
375 should be used. */
376 };
377
378 /* We hold flags for features explicitly enabled and explicitly
379 disabled. */
380 static int current_architecture;
381 static int not_current_architecture;
382 static int current_chip;
383 static const struct m68k_cpu *selected_arch;
384 static const struct m68k_cpu *selected_cpu;
385 static int initialized;
386
387 /* Architecture models. */
388 static const struct m68k_cpu m68k_archs[] =
389 {
390 {m68000, cpu_m68000, "68000", 0},
391 {m68010, cpu_m68010, "68010", 0},
392 {m68020|m68881|m68851, cpu_m68020, "68020", 0},
393 {m68030|m68881|m68851, cpu_m68030, "68030", 0},
394 {m68040, cpu_m68040, "68040", 0},
395 {m68060, cpu_m68060, "68060", 0},
396 {cpu32|m68881, cpu_cpu32, "cpu32", 0},
397 {mcfisa_a|mcfhwdiv, 0, "isaa", 0},
398 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, 0, "isaaplus", 0},
399 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, 0, "isab", 0},
400 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
401 cpu_cf547x, "cfv4e", 0},
402 {0,0,NULL, 0}
403 };
404
405 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
406 for either. */
407 static const struct m68k_cpu m68k_extensions[] =
408 {
409 {m68851, 0, "68851", -1},
410 {m68881, 0, "68881", -1},
411 {m68881, 0, "68882", -1},
412
413 {cfloat|m68881, 0, "float", 0},
414
415 {mcfhwdiv, 0, "div", 1},
416 {mcfusp, 0, "usp", 1},
417 {mcfmac, 0, "mac", 1},
418 {mcfemac, 0, "emac", 1},
419
420 {0,0,NULL, 0}
421 };
422
423 /* Processor list */
424 static const struct m68k_cpu m68k_cpus[] =
425 {
426 { m68000, cpu_m68000, "68000", 0},
427 { m68010, cpu_m68010, "68010", 0},
428 { m68020|m68881|m68851, cpu_m68020, "68020", 0},
429 { m68030|m68881|m68851, cpu_m68030, "68030", 0},
430 { m68040, cpu_m68040, "68040", 0},
431 { m68060, cpu_m68060, "68060", 0},
432 { cpu32|m68881, cpu_cpu32, "cpu32", 0},
433 { mcfisa_a, cpu_cf5200, "5200", 0},
434 { mcfisa_a|mcfhwdiv|mcfmac, cpu_cf5206e, "5206e", 0},
435 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, cpu_cf5208, "5208", 0},
436 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, cpu_cf5213, "5213", 0},
437 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,cpu_cf521x, "521x", 0},
438 { mcfisa_a|mcfhwdiv|mcfemac, cpu_cf5249, "5249", 0},
439 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,cpu_cf528x, "528x", 0},
440 { mcfisa_a|mcfhwdiv|mcfmac, cpu_cf5307, "5307", 0},
441 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, cpu_cf5329, "5329", 0},
442 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac, cpu_cf5407, "5407",0},
443 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
444 cpu_cf547x, "547x", 0},
445 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
446 cpu_cf548x, "548x", 0},
447 /* Aliases (effectively, so far as gas is concerned) for the above
448 cpus. */
449 { m68020|m68881|m68851, cpu_m68020, "68k", 1},
450 { m68000, cpu_m68000, "68008", 1},
451 { m68000, cpu_m68000, "68302", 1},
452 { m68000, cpu_m68000, "68306", 1},
453 { m68000, cpu_m68000, "68307", 1},
454 { m68000, cpu_m68000, "68322", 1},
455 { m68000, cpu_m68000, "68356", 1},
456 { m68000, cpu_m68000, "68ec000", 1},
457 { m68000, cpu_m68000, "68hc000", 1},
458 { m68000, cpu_m68000, "68hc001", 1},
459 { m68020|m68881|m68851, cpu_m68020, "68ec020", 1},
460 { m68030|m68881|m68851, cpu_m68030, "68ec030", 1},
461 { m68040, cpu_m68040, "68ec040", 1},
462 { m68060, cpu_m68060, "68ec060", 1},
463 { cpu32|m68881, cpu_cpu32, "68330", 1},
464 { cpu32|m68881, cpu_cpu32, "68331", 1},
465 { cpu32|m68881, cpu_cpu32, "68332", 1},
466 { cpu32|m68881, cpu_cpu32, "68333", 1},
467 { cpu32|m68881, cpu_cpu32, "68334", 1},
468 { cpu32|m68881, cpu_cpu32, "68336", 1},
469 { cpu32|m68881, cpu_cpu32, "68340", 1},
470 { cpu32|m68881, cpu_cpu32, "68341", 1},
471 { cpu32|m68881, cpu_cpu32, "68349", 1},
472 { cpu32|m68881, cpu_cpu32, "68360", 1},
473 { mcfisa_a, cpu_cf5200, "5202", 1},
474 { mcfisa_a, cpu_cf5200, "5204", 1},
475 { mcfisa_a, cpu_cf5200, "5206", 1},
476 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, cpu_cf5208, "5207", 1},
477 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, cpu_cf5213, "5211", 1},
478 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, cpu_cf5213, "5212", 1},
479 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, cpu_cf521x, "5214", 1},
480 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, cpu_cf521x, "5216", 1},
481 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, cpu_cf5329, "5327", 1},
482 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, cpu_cf5329, "5328", 1},
483 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, cpu_cf528x, "5280", 1},
484 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, cpu_cf528x, "5281", 1},
485 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, cpu_cf528x, "5282", 1},
486 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac, cpu_cf5407, "cfv4", 1 },
487 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
488 cpu_cf547x, "cfv4e", 1 },
489 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
490 cpu_cf547x, "5470", 1 },
491 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
492 cpu_cf547x, "5471", 1 },
493 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
494 cpu_cf547x, "5472", 1 },
495 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
496 cpu_cf547x, "5473", 1 },
497 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
498 cpu_cf547x, "5474", 1 },
499 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
500 cpu_cf547x, "5475", 1 },
501 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
502 cpu_cf548x, "5480", 1 },
503 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
504 cpu_cf548x, "5481", 1 },
505 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
506 cpu_cf548x, "5482", 1 },
507 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
508 cpu_cf548x, "5483", 1 },
509 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
510 cpu_cf548x, "5484", 1 },
511 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
512 cpu_cf548x, "5485", 1 },
513 {0,0,NULL, 0}
514 };
515
516 #define CPU_ALLOW_MC 1
517 #define CPU_ALLOW_NEGATION 4
518
519 static const struct m68k_cpu *m68k_lookup_cpu
520 (const char *, const struct m68k_cpu *, int, int *);
521 static int m68k_set_arch (const char *, int, int);
522 static int m68k_set_cpu (const char *, int, int);
523 static int m68k_set_extension (const char *, int, int);
524 static void m68k_init_arch (void);
525
526 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
527 architecture and we have a lot of relaxation modes. */
528
529 /* Macros used in the relaxation code. */
530 #define TAB(x,y) (((x) << 2) + (y))
531 #define TABTYPE(x) ((x) >> 2)
532
533 /* Relaxation states. */
534 #define BYTE 0
535 #define SHORT 1
536 #define LONG 2
537 #define SZ_UNDEF 3
538
539 /* Here are all the relaxation modes we support. First we can relax ordinary
540 branches. On 68020 and higher and on CPU32 all branch instructions take
541 three forms, so on these CPUs all branches always remain as such. When we
542 have to expand to the LONG form on a 68000, though, we substitute an
543 absolute jump instead. This is a direct replacement for unconditional
544 branches and a branch over a jump for conditional branches. However, if the
545 user requires PIC and disables this with --pcrel, we can only relax between
546 BYTE and SHORT forms, punting if that isn't enough. This gives us four
547 different relaxation modes for branches: */
548
549 #define BRANCHBWL 0 /* Branch byte, word, or long. */
550 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
551 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
552 #define BRANCHBW 3 /* Branch byte or word. */
553
554 /* We also relax coprocessor branches and DBcc's. All CPUs that support
555 coprocessor branches support them in word and long forms, so we have only
556 one relaxation mode for them. DBcc's are word only on all CPUs. We can
557 relax them to the LONG form with a branch-around sequence. This sequence
558 can use a long branch (if available) or an absolute jump (if acceptable).
559 This gives us two relaxation modes. If long branches are not available and
560 absolute jumps are not acceptable, we don't relax DBcc's. */
561
562 #define FBRANCH 4 /* Coprocessor branch. */
563 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
564 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
565
566 /* That's all for instruction relaxation. However, we also relax PC-relative
567 operands. Specifically, we have three operand relaxation modes. On the
568 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
569 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
570 two. Also PC+displacement+index operands in their simple form (with a non-
571 suppressed index without memory indirection) are supported on all CPUs, but
572 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
573 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
574 form of the PC+displacement+index operand. Finally, some absolute operands
575 can be relaxed down to 16-bit PC-relative. */
576
577 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
578 #define PCINDEX 8 /* PC + displacement + index. */
579 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
580
581 /* Note that calls to frag_var need to specify the maximum expansion
582 needed; this is currently 10 bytes for DBCC. */
583
584 /* The fields are:
585 How far Forward this mode will reach:
586 How far Backward this mode will reach:
587 How many bytes this mode will add to the size of the frag
588 Which mode to go to if the offset won't fit in this one
589
590 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
591 relax_typeS md_relax_table[] =
592 {
593 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
594 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
595 { 0, 0, 4, 0 },
596 { 1, 1, 0, 0 },
597
598 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
599 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
600 { 0, 0, 4, 0 },
601 { 1, 1, 0, 0 },
602
603 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
604 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
605 { 0, 0, 6, 0 },
606 { 1, 1, 0, 0 },
607
608 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
609 { 0, 0, 2, 0 },
610 { 1, 1, 0, 0 },
611 { 1, 1, 0, 0 },
612
613 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
614 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
615 { 0, 0, 4, 0 },
616 { 1, 1, 0, 0 },
617
618 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
619 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
620 { 0, 0, 10, 0 },
621 { 1, 1, 0, 0 },
622
623 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
624 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
625 { 0, 0, 10, 0 },
626 { 1, 1, 0, 0 },
627
628 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
629 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
630 { 0, 0, 6, 0 },
631 { 1, 1, 0, 0 },
632
633 { 125, -130, 0, TAB (PCINDEX, SHORT) },
634 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
635 { 0, 0, 4, 0 },
636 { 1, 1, 0, 0 },
637
638 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
639 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
640 { 0, 0, 4, 0 },
641 { 1, 1, 0, 0 },
642 };
643
644 /* These are the machine dependent pseudo-ops. These are included so
645 the assembler can work on the output from the SUN C compiler, which
646 generates these. */
647
648 /* This table describes all the machine specific pseudo-ops the assembler
649 has to support. The fields are:
650 pseudo-op name without dot
651 function to call to execute this pseudo-op
652 Integer arg to pass to the function. */
653 const pseudo_typeS md_pseudo_table[] =
654 {
655 {"data1", s_data1, 0},
656 {"data2", s_data2, 0},
657 {"bss", s_bss, 0},
658 {"even", s_even, 0},
659 {"skip", s_space, 0},
660 {"proc", s_proc, 0},
661 #if defined (TE_SUN3) || defined (OBJ_ELF)
662 {"align", s_align_bytes, 0},
663 #endif
664 #ifdef OBJ_ELF
665 {"swbeg", s_ignore, 0},
666 #endif
667 {"extend", float_cons, 'x'},
668 {"ldouble", float_cons, 'x'},
669
670 {"arch", s_m68k_arch, 0},
671 {"cpu", s_m68k_cpu, 0},
672
673 /* The following pseudo-ops are supported for MRI compatibility. */
674 {"chip", s_chip, 0},
675 {"comline", s_space, 1},
676 {"fopt", s_fopt, 0},
677 {"mask2", s_ignore, 0},
678 {"opt", s_opt, 0},
679 {"reg", s_reg, 0},
680 {"restore", s_restore, 0},
681 {"save", s_save, 0},
682
683 {"if", s_mri_if, 0},
684 {"if.b", s_mri_if, 'b'},
685 {"if.w", s_mri_if, 'w'},
686 {"if.l", s_mri_if, 'l'},
687 {"else", s_mri_else, 0},
688 {"else.s", s_mri_else, 's'},
689 {"else.l", s_mri_else, 'l'},
690 {"endi", s_mri_endi, 0},
691 {"break", s_mri_break, 0},
692 {"break.s", s_mri_break, 's'},
693 {"break.l", s_mri_break, 'l'},
694 {"next", s_mri_next, 0},
695 {"next.s", s_mri_next, 's'},
696 {"next.l", s_mri_next, 'l'},
697 {"for", s_mri_for, 0},
698 {"for.b", s_mri_for, 'b'},
699 {"for.w", s_mri_for, 'w'},
700 {"for.l", s_mri_for, 'l'},
701 {"endf", s_mri_endf, 0},
702 {"repeat", s_mri_repeat, 0},
703 {"until", s_mri_until, 0},
704 {"until.b", s_mri_until, 'b'},
705 {"until.w", s_mri_until, 'w'},
706 {"until.l", s_mri_until, 'l'},
707 {"while", s_mri_while, 0},
708 {"while.b", s_mri_while, 'b'},
709 {"while.w", s_mri_while, 'w'},
710 {"while.l", s_mri_while, 'l'},
711 {"endw", s_mri_endw, 0},
712
713 {0, 0, 0}
714 };
715
716 /* The mote pseudo ops are put into the opcode table, since they
717 don't start with a . they look like opcodes to gas. */
718
719 const pseudo_typeS mote_pseudo_table[] =
720 {
721
722 {"dcl", cons, 4},
723 {"dc", cons, 2},
724 {"dcw", cons, 2},
725 {"dcb", cons, 1},
726
727 {"dsl", s_space, 4},
728 {"ds", s_space, 2},
729 {"dsw", s_space, 2},
730 {"dsb", s_space, 1},
731
732 {"xdef", s_globl, 0},
733 #ifdef OBJ_ELF
734 {"align", s_align_bytes, 0},
735 #else
736 {"align", s_align_ptwo, 0},
737 #endif
738 #ifdef M68KCOFF
739 {"sect", obj_coff_section, 0},
740 {"section", obj_coff_section, 0},
741 #endif
742 {0, 0, 0}
743 };
744
745 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
746 gives identical results to a 32-bit host. */
747 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
748 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
749
750 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
751 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
752 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
753 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
754
755 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
756 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
757 #define islong(x) (1)
758
759 static char notend_table[256];
760 static char alt_notend_table[256];
761 #define notend(s) \
762 (! (notend_table[(unsigned char) *s] \
763 || (*s == ':' \
764 && alt_notend_table[(unsigned char) s[1]])))
765
766 /* Return a human readable string holding the list of chips that are
767 valid for a particular architecture, suppressing aliases (unless
768 there is only one of them). */
769
770 static char *
771 find_cf_chip (int architecture)
772 {
773 static char buf[1024];
774 int i, j, n_chips, n_alias;
775 char *cp;
776
777 strcpy (buf, " (");
778 cp = buf + strlen (buf);
779
780 for (i = 0, n_chips = 0, n_alias = 0; m68k_cpus[i].name; ++i)
781 if (m68k_cpus[i].arch & architecture)
782 {
783 n_chips++;
784 if (m68k_cpus[i].alias)
785 n_alias++;
786 }
787
788 if (n_chips == 0)
789 as_fatal (_("no matching ColdFire architectures found"));
790
791 if (n_alias > 1)
792 n_chips -= n_alias;
793
794 for (i = 0, j = 0; m68k_cpus[i].name && j < n_chips; ++i)
795 if (m68k_cpus[i].arch & architecture)
796 {
797 if (j)
798 {
799 if ((j == n_chips - 1 && !(n_alias > 1)) || ! n_alias)
800 {
801 if (n_chips == 2)
802 {
803 strncpy (cp, _(" or "), (sizeof (buf) - (cp - buf)));
804 cp += strlen (cp);
805 }
806 else
807 {
808 strncpy (cp, _(", or "), (sizeof (buf) - (cp - buf)));
809 cp += strlen (cp);
810 }
811 }
812 else
813 {
814 strncpy (cp, ", ", (sizeof (buf) - (cp - buf)));
815 cp += strlen (cp);
816 }
817 }
818 strncpy (cp, m68k_cpus[i].name, (sizeof (buf) - (cp - buf)));
819 cp += strlen (cp);
820 j++;
821 }
822
823 if (n_alias > 1)
824 {
825 strncpy (cp, _(", or aliases"), (sizeof (buf) - (cp - buf)));
826 cp += strlen (cp);
827 }
828
829 strncpy (cp, ")", (sizeof (buf) - (cp - buf)));
830
831 return buf;
832 }
833
834 #ifdef OBJ_ELF
835
836 /* Return zero if the reference to SYMBOL from within the same segment may
837 be relaxed. */
838
839 /* On an ELF system, we can't relax an externally visible symbol,
840 because it may be overridden by a shared library. However, if
841 TARGET_OS is "elf", then we presume that we are assembling for an
842 embedded system, in which case we don't have to worry about shared
843 libraries, and we can relax any external sym. */
844
845 #define relaxable_symbol(symbol) \
846 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
847 || S_IS_WEAK (symbol)))
848
849 /* Compute the relocation code for a fixup of SIZE bytes, using pc
850 relative relocation if PCREL is non-zero. PIC says whether a special
851 pic relocation was requested. */
852
853 static bfd_reloc_code_real_type
854 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
855 {
856 switch (pic)
857 {
858 case pic_got_pcrel:
859 switch (size)
860 {
861 case 1:
862 return BFD_RELOC_8_GOT_PCREL;
863 case 2:
864 return BFD_RELOC_16_GOT_PCREL;
865 case 4:
866 return BFD_RELOC_32_GOT_PCREL;
867 }
868 break;
869
870 case pic_got_off:
871 switch (size)
872 {
873 case 1:
874 return BFD_RELOC_8_GOTOFF;
875 case 2:
876 return BFD_RELOC_16_GOTOFF;
877 case 4:
878 return BFD_RELOC_32_GOTOFF;
879 }
880 break;
881
882 case pic_plt_pcrel:
883 switch (size)
884 {
885 case 1:
886 return BFD_RELOC_8_PLT_PCREL;
887 case 2:
888 return BFD_RELOC_16_PLT_PCREL;
889 case 4:
890 return BFD_RELOC_32_PLT_PCREL;
891 }
892 break;
893
894 case pic_plt_off:
895 switch (size)
896 {
897 case 1:
898 return BFD_RELOC_8_PLTOFF;
899 case 2:
900 return BFD_RELOC_16_PLTOFF;
901 case 4:
902 return BFD_RELOC_32_PLTOFF;
903 }
904 break;
905
906 case pic_none:
907 if (pcrel)
908 {
909 switch (size)
910 {
911 case 1:
912 return BFD_RELOC_8_PCREL;
913 case 2:
914 return BFD_RELOC_16_PCREL;
915 case 4:
916 return BFD_RELOC_32_PCREL;
917 }
918 }
919 else
920 {
921 switch (size)
922 {
923 case 1:
924 return BFD_RELOC_8;
925 case 2:
926 return BFD_RELOC_16;
927 case 4:
928 return BFD_RELOC_32;
929 }
930 }
931 }
932
933 if (pcrel)
934 {
935 if (pic == pic_none)
936 as_bad (_("Can not do %d byte pc-relative relocation"), size);
937 else
938 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
939 }
940 else
941 {
942 if (pic == pic_none)
943 as_bad (_("Can not do %d byte relocation"), size);
944 else
945 as_bad (_("Can not do %d byte pic relocation"), size);
946 }
947
948 return BFD_RELOC_NONE;
949 }
950
951 /* Here we decide which fixups can be adjusted to make them relative
952 to the beginning of the section instead of the symbol. Basically
953 we need to make sure that the dynamic relocations are done
954 correctly, so in some cases we force the original symbol to be
955 used. */
956 int
957 tc_m68k_fix_adjustable (fixS *fixP)
958 {
959 /* Adjust_reloc_syms doesn't know about the GOT. */
960 switch (fixP->fx_r_type)
961 {
962 case BFD_RELOC_8_GOT_PCREL:
963 case BFD_RELOC_16_GOT_PCREL:
964 case BFD_RELOC_32_GOT_PCREL:
965 case BFD_RELOC_8_GOTOFF:
966 case BFD_RELOC_16_GOTOFF:
967 case BFD_RELOC_32_GOTOFF:
968 case BFD_RELOC_8_PLT_PCREL:
969 case BFD_RELOC_16_PLT_PCREL:
970 case BFD_RELOC_32_PLT_PCREL:
971 case BFD_RELOC_8_PLTOFF:
972 case BFD_RELOC_16_PLTOFF:
973 case BFD_RELOC_32_PLTOFF:
974 return 0;
975
976 case BFD_RELOC_VTABLE_INHERIT:
977 case BFD_RELOC_VTABLE_ENTRY:
978 return 0;
979
980 default:
981 return 1;
982 }
983 }
984
985 #else /* !OBJ_ELF */
986
987 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
988
989 #define relaxable_symbol(symbol) 1
990
991 #endif /* OBJ_ELF */
992
993 arelent *
994 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
995 {
996 arelent *reloc;
997 bfd_reloc_code_real_type code;
998
999 /* If the tcbit is set, then this was a fixup of a negative value
1000 that was never resolved. We do not have a reloc to handle this,
1001 so just return. We assume that other code will have detected this
1002 situation and produced a helpful error message, so we just tell the
1003 user that the reloc cannot be produced. */
1004 if (fixp->fx_tcbit)
1005 {
1006 if (fixp->fx_addsy)
1007 as_bad_where (fixp->fx_file, fixp->fx_line,
1008 _("Unable to produce reloc against symbol '%s'"),
1009 S_GET_NAME (fixp->fx_addsy));
1010 return NULL;
1011 }
1012
1013 if (fixp->fx_r_type != BFD_RELOC_NONE)
1014 {
1015 code = fixp->fx_r_type;
1016
1017 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1018 that fixup_segment converted a non-PC relative reloc into a
1019 PC relative reloc. In such a case, we need to convert the
1020 reloc code. */
1021 if (fixp->fx_pcrel)
1022 {
1023 switch (code)
1024 {
1025 case BFD_RELOC_8:
1026 code = BFD_RELOC_8_PCREL;
1027 break;
1028 case BFD_RELOC_16:
1029 code = BFD_RELOC_16_PCREL;
1030 break;
1031 case BFD_RELOC_32:
1032 code = BFD_RELOC_32_PCREL;
1033 break;
1034 case BFD_RELOC_8_PCREL:
1035 case BFD_RELOC_16_PCREL:
1036 case BFD_RELOC_32_PCREL:
1037 case BFD_RELOC_8_GOT_PCREL:
1038 case BFD_RELOC_16_GOT_PCREL:
1039 case BFD_RELOC_32_GOT_PCREL:
1040 case BFD_RELOC_8_GOTOFF:
1041 case BFD_RELOC_16_GOTOFF:
1042 case BFD_RELOC_32_GOTOFF:
1043 case BFD_RELOC_8_PLT_PCREL:
1044 case BFD_RELOC_16_PLT_PCREL:
1045 case BFD_RELOC_32_PLT_PCREL:
1046 case BFD_RELOC_8_PLTOFF:
1047 case BFD_RELOC_16_PLTOFF:
1048 case BFD_RELOC_32_PLTOFF:
1049 break;
1050 default:
1051 as_bad_where (fixp->fx_file, fixp->fx_line,
1052 _("Cannot make %s relocation PC relative"),
1053 bfd_get_reloc_code_name (code));
1054 }
1055 }
1056 }
1057 else
1058 {
1059 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1060 switch (F (fixp->fx_size, fixp->fx_pcrel))
1061 {
1062 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1063 MAP (1, 0, BFD_RELOC_8);
1064 MAP (2, 0, BFD_RELOC_16);
1065 MAP (4, 0, BFD_RELOC_32);
1066 MAP (1, 1, BFD_RELOC_8_PCREL);
1067 MAP (2, 1, BFD_RELOC_16_PCREL);
1068 MAP (4, 1, BFD_RELOC_32_PCREL);
1069 default:
1070 abort ();
1071 }
1072 }
1073 #undef F
1074 #undef MAP
1075
1076 reloc = (arelent *) xmalloc (sizeof (arelent));
1077 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1078 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1079 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1080 #ifndef OBJ_ELF
1081 if (fixp->fx_pcrel)
1082 reloc->addend = fixp->fx_addnumber;
1083 else
1084 reloc->addend = 0;
1085 #else
1086 if (!fixp->fx_pcrel)
1087 reloc->addend = fixp->fx_addnumber;
1088 else
1089 reloc->addend = (section->vma
1090 /* Explicit sign extension in case char is
1091 unsigned. */
1092 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1093 + fixp->fx_addnumber
1094 + md_pcrel_from (fixp));
1095 #endif
1096
1097 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1098 assert (reloc->howto != 0);
1099
1100 return reloc;
1101 }
1102
1103 /* Handle of the OPCODE hash table. NULL means any use before
1104 m68k_ip_begin() will crash. */
1105 static struct hash_control *op_hash;
1106 \f
1107 /* Assemble an m68k instruction. */
1108
1109 static void
1110 m68k_ip (char *instring)
1111 {
1112 register char *p;
1113 register struct m68k_op *opP;
1114 register const struct m68k_incant *opcode;
1115 register const char *s;
1116 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1117 char *pdot, *pdotmove;
1118 enum m68k_size siz1, siz2;
1119 char c;
1120 int losing;
1121 int opsfound;
1122 struct m68k_op operands_backup[6];
1123 LITTLENUM_TYPE words[6];
1124 LITTLENUM_TYPE *wordp;
1125 unsigned long ok_arch = 0;
1126
1127 if (*instring == ' ')
1128 instring++; /* Skip leading whitespace. */
1129
1130 /* Scan up to end of operation-code, which MUST end in end-of-string
1131 or exactly 1 space. */
1132 pdot = 0;
1133 for (p = instring; *p != '\0'; p++)
1134 {
1135 if (*p == ' ')
1136 break;
1137 if (*p == '.')
1138 pdot = p;
1139 }
1140
1141 if (p == instring)
1142 {
1143 the_ins.error = _("No operator");
1144 return;
1145 }
1146
1147 /* p now points to the end of the opcode name, probably whitespace.
1148 Make sure the name is null terminated by clobbering the
1149 whitespace, look it up in the hash table, then fix it back.
1150 Remove a dot, first, since the opcode tables have none. */
1151 if (pdot != NULL)
1152 {
1153 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1154 *pdotmove = pdotmove[1];
1155 p--;
1156 }
1157
1158 c = *p;
1159 *p = '\0';
1160 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1161 *p = c;
1162
1163 if (pdot != NULL)
1164 {
1165 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1166 *pdotmove = pdotmove[-1];
1167 *pdot = '.';
1168 ++p;
1169 }
1170
1171 if (opcode == NULL)
1172 {
1173 the_ins.error = _("Unknown operator");
1174 return;
1175 }
1176
1177 /* Found a legitimate opcode, start matching operands. */
1178 while (*p == ' ')
1179 ++p;
1180
1181 if (opcode->m_operands == 0)
1182 {
1183 char *old = input_line_pointer;
1184 *old = '\n';
1185 input_line_pointer = p;
1186 /* Ahh - it's a motorola style psuedo op. */
1187 mote_pseudo_table[opcode->m_opnum].poc_handler
1188 (mote_pseudo_table[opcode->m_opnum].poc_val);
1189 input_line_pointer = old;
1190 *old = 0;
1191
1192 return;
1193 }
1194
1195 if (flag_mri && opcode->m_opnum == 0)
1196 {
1197 /* In MRI mode, random garbage is allowed after an instruction
1198 which accepts no operands. */
1199 the_ins.args = opcode->m_operands;
1200 the_ins.numargs = opcode->m_opnum;
1201 the_ins.numo = opcode->m_codenum;
1202 the_ins.opcode[0] = getone (opcode);
1203 the_ins.opcode[1] = gettwo (opcode);
1204 return;
1205 }
1206
1207 for (opP = &the_ins.operands[0]; *p; opP++)
1208 {
1209 p = crack_operand (p, opP);
1210
1211 if (opP->error)
1212 {
1213 the_ins.error = opP->error;
1214 return;
1215 }
1216 }
1217
1218 opsfound = opP - &the_ins.operands[0];
1219
1220 /* This ugly hack is to support the floating pt opcodes in their
1221 standard form. Essentially, we fake a first enty of type COP#1 */
1222 if (opcode->m_operands[0] == 'I')
1223 {
1224 int n;
1225
1226 for (n = opsfound; n > 0; --n)
1227 the_ins.operands[n] = the_ins.operands[n - 1];
1228
1229 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1230 the_ins.operands[0].mode = CONTROL;
1231 the_ins.operands[0].reg = m68k_float_copnum;
1232 opsfound++;
1233 }
1234
1235 /* We've got the operands. Find an opcode that'll accept them. */
1236 for (losing = 0;;)
1237 {
1238 /* If we didn't get the right number of ops, or we have no
1239 common model with this pattern then reject this pattern. */
1240
1241 ok_arch |= opcode->m_arch;
1242 if (opsfound != opcode->m_opnum
1243 || ((opcode->m_arch & current_architecture) == 0))
1244 ++losing;
1245 else
1246 {
1247 int i;
1248
1249 /* Make a copy of the operands of this insn so that
1250 we can modify them safely, should we want to. */
1251 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1252 for (i = 0; i < opsfound; i++)
1253 operands_backup[i] = the_ins.operands[i];
1254
1255 for (s = opcode->m_operands, opP = &operands_backup[0];
1256 *s && !losing;
1257 s += 2, opP++)
1258 {
1259 /* Warning: this switch is huge! */
1260 /* I've tried to organize the cases into this order:
1261 non-alpha first, then alpha by letter. Lower-case
1262 goes directly before uppercase counterpart. */
1263 /* Code with multiple case ...: gets sorted by the lowest
1264 case ... it belongs to. I hope this makes sense. */
1265 switch (*s)
1266 {
1267 case '!':
1268 switch (opP->mode)
1269 {
1270 case IMMED:
1271 case DREG:
1272 case AREG:
1273 case FPREG:
1274 case CONTROL:
1275 case AINC:
1276 case ADEC:
1277 case REGLST:
1278 losing++;
1279 break;
1280 default:
1281 break;
1282 }
1283 break;
1284
1285 case '<':
1286 switch (opP->mode)
1287 {
1288 case DREG:
1289 case AREG:
1290 case FPREG:
1291 case CONTROL:
1292 case IMMED:
1293 case ADEC:
1294 case REGLST:
1295 losing++;
1296 break;
1297 default:
1298 break;
1299 }
1300 break;
1301
1302 case '>':
1303 switch (opP->mode)
1304 {
1305 case DREG:
1306 case AREG:
1307 case FPREG:
1308 case CONTROL:
1309 case IMMED:
1310 case AINC:
1311 case REGLST:
1312 losing++;
1313 break;
1314 case ABSL:
1315 break;
1316 default:
1317 if (opP->reg == PC
1318 || opP->reg == ZPC)
1319 losing++;
1320 break;
1321 }
1322 break;
1323
1324 case 'm':
1325 switch (opP->mode)
1326 {
1327 case DREG:
1328 case AREG:
1329 case AINDR:
1330 case AINC:
1331 case ADEC:
1332 break;
1333 default:
1334 losing++;
1335 }
1336 break;
1337
1338 case 'n':
1339 switch (opP->mode)
1340 {
1341 case DISP:
1342 break;
1343 default:
1344 losing++;
1345 }
1346 break;
1347
1348 case 'o':
1349 switch (opP->mode)
1350 {
1351 case BASE:
1352 case ABSL:
1353 case IMMED:
1354 break;
1355 default:
1356 losing++;
1357 }
1358 break;
1359
1360 case 'p':
1361 switch (opP->mode)
1362 {
1363 case DREG:
1364 case AREG:
1365 case AINDR:
1366 case AINC:
1367 case ADEC:
1368 break;
1369 case DISP:
1370 if (opP->reg == PC || opP->reg == ZPC)
1371 losing++;
1372 break;
1373 default:
1374 losing++;
1375 }
1376 break;
1377
1378 case 'q':
1379 switch (opP->mode)
1380 {
1381 case DREG:
1382 case AINDR:
1383 case AINC:
1384 case ADEC:
1385 break;
1386 case DISP:
1387 if (opP->reg == PC || opP->reg == ZPC)
1388 losing++;
1389 break;
1390 default:
1391 losing++;
1392 break;
1393 }
1394 break;
1395
1396 case 'v':
1397 switch (opP->mode)
1398 {
1399 case DREG:
1400 case AINDR:
1401 case AINC:
1402 case ADEC:
1403 case ABSL:
1404 break;
1405 case DISP:
1406 if (opP->reg == PC || opP->reg == ZPC)
1407 losing++;
1408 break;
1409 default:
1410 losing++;
1411 break;
1412 }
1413 break;
1414
1415 case '#':
1416 if (opP->mode != IMMED)
1417 losing++;
1418 else if (s[1] == 'b'
1419 && ! isvar (&opP->disp)
1420 && (opP->disp.exp.X_op != O_constant
1421 || ! isbyte (opP->disp.exp.X_add_number)))
1422 losing++;
1423 else if (s[1] == 'B'
1424 && ! isvar (&opP->disp)
1425 && (opP->disp.exp.X_op != O_constant
1426 || ! issbyte (opP->disp.exp.X_add_number)))
1427 losing++;
1428 else if (s[1] == 'w'
1429 && ! isvar (&opP->disp)
1430 && (opP->disp.exp.X_op != O_constant
1431 || ! isword (opP->disp.exp.X_add_number)))
1432 losing++;
1433 else if (s[1] == 'W'
1434 && ! isvar (&opP->disp)
1435 && (opP->disp.exp.X_op != O_constant
1436 || ! issword (opP->disp.exp.X_add_number)))
1437 losing++;
1438 break;
1439
1440 case '^':
1441 case 'T':
1442 if (opP->mode != IMMED)
1443 losing++;
1444 break;
1445
1446 case '$':
1447 if (opP->mode == AREG
1448 || opP->mode == CONTROL
1449 || opP->mode == FPREG
1450 || opP->mode == IMMED
1451 || opP->mode == REGLST
1452 || (opP->mode != ABSL
1453 && (opP->reg == PC
1454 || opP->reg == ZPC)))
1455 losing++;
1456 break;
1457
1458 case '%':
1459 if (opP->mode == CONTROL
1460 || opP->mode == FPREG
1461 || opP->mode == REGLST
1462 || opP->mode == IMMED
1463 || (opP->mode != ABSL
1464 && (opP->reg == PC
1465 || opP->reg == ZPC)))
1466 losing++;
1467 break;
1468
1469 case '&':
1470 switch (opP->mode)
1471 {
1472 case DREG:
1473 case AREG:
1474 case FPREG:
1475 case CONTROL:
1476 case IMMED:
1477 case AINC:
1478 case ADEC:
1479 case REGLST:
1480 losing++;
1481 break;
1482 case ABSL:
1483 break;
1484 default:
1485 if (opP->reg == PC
1486 || opP->reg == ZPC)
1487 losing++;
1488 break;
1489 }
1490 break;
1491
1492 case '*':
1493 if (opP->mode == CONTROL
1494 || opP->mode == FPREG
1495 || opP->mode == REGLST)
1496 losing++;
1497 break;
1498
1499 case '+':
1500 if (opP->mode != AINC)
1501 losing++;
1502 break;
1503
1504 case '-':
1505 if (opP->mode != ADEC)
1506 losing++;
1507 break;
1508
1509 case '/':
1510 switch (opP->mode)
1511 {
1512 case AREG:
1513 case CONTROL:
1514 case FPREG:
1515 case AINC:
1516 case ADEC:
1517 case IMMED:
1518 case REGLST:
1519 losing++;
1520 break;
1521 default:
1522 break;
1523 }
1524 break;
1525
1526 case ';':
1527 switch (opP->mode)
1528 {
1529 case AREG:
1530 case CONTROL:
1531 case FPREG:
1532 case REGLST:
1533 losing++;
1534 break;
1535 default:
1536 break;
1537 }
1538 break;
1539
1540 case '?':
1541 switch (opP->mode)
1542 {
1543 case AREG:
1544 case CONTROL:
1545 case FPREG:
1546 case AINC:
1547 case ADEC:
1548 case IMMED:
1549 case REGLST:
1550 losing++;
1551 break;
1552 case ABSL:
1553 break;
1554 default:
1555 if (opP->reg == PC || opP->reg == ZPC)
1556 losing++;
1557 break;
1558 }
1559 break;
1560
1561 case '@':
1562 switch (opP->mode)
1563 {
1564 case AREG:
1565 case CONTROL:
1566 case FPREG:
1567 case IMMED:
1568 case REGLST:
1569 losing++;
1570 break;
1571 default:
1572 break;
1573 }
1574 break;
1575
1576 case '~': /* For now! (JF FOO is this right?) */
1577 switch (opP->mode)
1578 {
1579 case DREG:
1580 case AREG:
1581 case CONTROL:
1582 case FPREG:
1583 case IMMED:
1584 case REGLST:
1585 losing++;
1586 break;
1587 case ABSL:
1588 break;
1589 default:
1590 if (opP->reg == PC
1591 || opP->reg == ZPC)
1592 losing++;
1593 break;
1594 }
1595 break;
1596
1597 case '3':
1598 if (opP->mode != CONTROL
1599 || (opP->reg != TT0 && opP->reg != TT1))
1600 losing++;
1601 break;
1602
1603 case 'A':
1604 if (opP->mode != AREG)
1605 losing++;
1606 break;
1607
1608 case 'a':
1609 if (opP->mode != AINDR)
1610 ++losing;
1611 break;
1612
1613 case '4':
1614 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1615 && (opP->mode != DISP
1616 || opP->reg < ADDR0
1617 || opP->reg > ADDR7))
1618 ++losing;
1619 break;
1620
1621 case 'B': /* FOO */
1622 if (opP->mode != ABSL
1623 || (flag_long_jumps
1624 && strncmp (instring, "jbsr", 4) == 0))
1625 losing++;
1626 break;
1627
1628 case 'b':
1629 switch (opP->mode)
1630 {
1631 case IMMED:
1632 case ABSL:
1633 case AREG:
1634 case FPREG:
1635 case CONTROL:
1636 case POST:
1637 case PRE:
1638 case REGLST:
1639 losing++;
1640 break;
1641 default:
1642 break;
1643 }
1644 break;
1645
1646 case 'C':
1647 if (opP->mode != CONTROL || opP->reg != CCR)
1648 losing++;
1649 break;
1650
1651 case 'd':
1652 if (opP->mode != DISP
1653 || opP->reg < ADDR0
1654 || opP->reg > ADDR7)
1655 losing++;
1656 break;
1657
1658 case 'D':
1659 if (opP->mode != DREG)
1660 losing++;
1661 break;
1662
1663 case 'E':
1664 if (opP->reg != ACC)
1665 losing++;
1666 break;
1667
1668 case 'e':
1669 if (opP->reg != ACC && opP->reg != ACC1
1670 && opP->reg != ACC2 && opP->reg != ACC3)
1671 losing++;
1672 break;
1673
1674 case 'F':
1675 if (opP->mode != FPREG)
1676 losing++;
1677 break;
1678
1679 case 'G':
1680 if (opP->reg != MACSR)
1681 losing++;
1682 break;
1683
1684 case 'g':
1685 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1686 losing++;
1687 break;
1688
1689 case 'H':
1690 if (opP->reg != MASK)
1691 losing++;
1692 break;
1693
1694 case 'I':
1695 if (opP->mode != CONTROL
1696 || opP->reg < COP0
1697 || opP->reg > COP7)
1698 losing++;
1699 break;
1700
1701 case 'i':
1702 if (opP->mode != LSH && opP->mode != RSH)
1703 losing++;
1704 break;
1705
1706 case 'J':
1707 if (opP->mode != CONTROL
1708 || opP->reg < USP
1709 || opP->reg > last_movec_reg
1710 || !control_regs)
1711 losing++;
1712 else
1713 {
1714 const enum m68k_register *rp;
1715
1716 for (rp = control_regs; *rp; rp++)
1717 if (*rp == opP->reg)
1718 break;
1719 if (*rp == 0)
1720 losing++;
1721 }
1722 break;
1723
1724 case 'k':
1725 if (opP->mode != IMMED)
1726 losing++;
1727 break;
1728
1729 case 'l':
1730 case 'L':
1731 if (opP->mode == DREG
1732 || opP->mode == AREG
1733 || opP->mode == FPREG)
1734 {
1735 if (s[1] == '8')
1736 losing++;
1737 else
1738 {
1739 switch (opP->mode)
1740 {
1741 case DREG:
1742 opP->mask = 1 << (opP->reg - DATA0);
1743 break;
1744 case AREG:
1745 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1746 break;
1747 case FPREG:
1748 opP->mask = 1 << (opP->reg - FP0 + 16);
1749 break;
1750 default:
1751 abort ();
1752 }
1753 opP->mode = REGLST;
1754 }
1755 }
1756 else if (opP->mode == CONTROL)
1757 {
1758 if (s[1] != '8')
1759 losing++;
1760 else
1761 {
1762 switch (opP->reg)
1763 {
1764 case FPI:
1765 opP->mask = 1 << 24;
1766 break;
1767 case FPS:
1768 opP->mask = 1 << 25;
1769 break;
1770 case FPC:
1771 opP->mask = 1 << 26;
1772 break;
1773 default:
1774 losing++;
1775 break;
1776 }
1777 opP->mode = REGLST;
1778 }
1779 }
1780 else if (opP->mode != REGLST)
1781 losing++;
1782 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1783 losing++;
1784 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1785 losing++;
1786 break;
1787
1788 case 'M':
1789 if (opP->mode != IMMED)
1790 losing++;
1791 else if (opP->disp.exp.X_op != O_constant
1792 || ! issbyte (opP->disp.exp.X_add_number))
1793 losing++;
1794 else if (! m68k_quick
1795 && instring[3] != 'q'
1796 && instring[4] != 'q')
1797 losing++;
1798 break;
1799
1800 case 'O':
1801 if (opP->mode != DREG
1802 && opP->mode != IMMED
1803 && opP->mode != ABSL)
1804 losing++;
1805 break;
1806
1807 case 'Q':
1808 if (opP->mode != IMMED)
1809 losing++;
1810 else if (opP->disp.exp.X_op != O_constant
1811 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1812 losing++;
1813 else if (! m68k_quick
1814 && (strncmp (instring, "add", 3) == 0
1815 || strncmp (instring, "sub", 3) == 0)
1816 && instring[3] != 'q')
1817 losing++;
1818 break;
1819
1820 case 'R':
1821 if (opP->mode != DREG && opP->mode != AREG)
1822 losing++;
1823 break;
1824
1825 case 'r':
1826 if (opP->mode != AINDR
1827 && (opP->mode != BASE
1828 || (opP->reg != 0
1829 && opP->reg != ZADDR0)
1830 || opP->disp.exp.X_op != O_absent
1831 || ((opP->index.reg < DATA0
1832 || opP->index.reg > DATA7)
1833 && (opP->index.reg < ADDR0
1834 || opP->index.reg > ADDR7))
1835 || opP->index.size != SIZE_UNSPEC
1836 || opP->index.scale != 1))
1837 losing++;
1838 break;
1839
1840 case 's':
1841 if (opP->mode != CONTROL
1842 || ! (opP->reg == FPI
1843 || opP->reg == FPS
1844 || opP->reg == FPC))
1845 losing++;
1846 break;
1847
1848 case 'S':
1849 if (opP->mode != CONTROL || opP->reg != SR)
1850 losing++;
1851 break;
1852
1853 case 't':
1854 if (opP->mode != IMMED)
1855 losing++;
1856 else if (opP->disp.exp.X_op != O_constant
1857 || TRUNC (opP->disp.exp.X_add_number) > 7)
1858 losing++;
1859 break;
1860
1861 case 'U':
1862 if (opP->mode != CONTROL || opP->reg != USP)
1863 losing++;
1864 break;
1865
1866 case 'x':
1867 if (opP->mode != IMMED)
1868 losing++;
1869 else if (opP->disp.exp.X_op != O_constant
1870 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1871 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
1872 losing++;
1873 break;
1874
1875 /* JF these are out of order. We could put them
1876 in order if we were willing to put up with
1877 bunches of #ifdef m68851s in the code.
1878
1879 Don't forget that you need these operands
1880 to use 68030 MMU instructions. */
1881 #ifndef NO_68851
1882 /* Memory addressing mode used by pflushr. */
1883 case '|':
1884 if (opP->mode == CONTROL
1885 || opP->mode == FPREG
1886 || opP->mode == DREG
1887 || opP->mode == AREG
1888 || opP->mode == REGLST)
1889 losing++;
1890 /* We should accept immediate operands, but they
1891 supposedly have to be quad word, and we don't
1892 handle that. I would like to see what a Motorola
1893 assembler does before doing something here. */
1894 if (opP->mode == IMMED)
1895 losing++;
1896 break;
1897
1898 case 'f':
1899 if (opP->mode != CONTROL
1900 || (opP->reg != SFC && opP->reg != DFC))
1901 losing++;
1902 break;
1903
1904 case '0':
1905 if (opP->mode != CONTROL || opP->reg != TC)
1906 losing++;
1907 break;
1908
1909 case '1':
1910 if (opP->mode != CONTROL || opP->reg != AC)
1911 losing++;
1912 break;
1913
1914 case '2':
1915 if (opP->mode != CONTROL
1916 || (opP->reg != CAL
1917 && opP->reg != VAL
1918 && opP->reg != SCC))
1919 losing++;
1920 break;
1921
1922 case 'V':
1923 if (opP->mode != CONTROL
1924 || opP->reg != VAL)
1925 losing++;
1926 break;
1927
1928 case 'W':
1929 if (opP->mode != CONTROL
1930 || (opP->reg != DRP
1931 && opP->reg != SRP
1932 && opP->reg != CRP))
1933 losing++;
1934 break;
1935
1936 case 'w':
1937 switch (opP->mode)
1938 {
1939 case IMMED:
1940 case ABSL:
1941 case AREG:
1942 case DREG:
1943 case FPREG:
1944 case CONTROL:
1945 case POST:
1946 case PRE:
1947 case REGLST:
1948 losing++;
1949 break;
1950 default:
1951 break;
1952 }
1953 break;
1954
1955 case 'X':
1956 if (opP->mode != CONTROL
1957 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1958 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1959 losing++;
1960 break;
1961
1962 case 'Y':
1963 if (opP->mode != CONTROL || opP->reg != PSR)
1964 losing++;
1965 break;
1966
1967 case 'Z':
1968 if (opP->mode != CONTROL || opP->reg != PCSR)
1969 losing++;
1970 break;
1971 #endif
1972 case 'c':
1973 if (opP->mode != CONTROL
1974 || (opP->reg != NC
1975 && opP->reg != IC
1976 && opP->reg != DC
1977 && opP->reg != BC))
1978 losing++;
1979 break;
1980
1981 case '_':
1982 if (opP->mode != ABSL)
1983 ++losing;
1984 break;
1985
1986 case 'u':
1987 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1988 losing++;
1989 /* FIXME: kludge instead of fixing parser:
1990 upper/lower registers are *not* CONTROL
1991 registers, but ordinary ones. */
1992 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1993 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1994 opP->mode = DREG;
1995 else
1996 opP->mode = AREG;
1997 break;
1998
1999 case 'y':
2000 if (!(opP->mode == AINDR
2001 || (opP->mode == DISP
2002 && !(opP->reg == PC || opP->reg == ZPC))))
2003 losing++;
2004 break;
2005
2006 case 'z':
2007 if (!(opP->mode == AINDR || opP->mode == DISP))
2008 losing++;
2009 break;
2010
2011 default:
2012 abort ();
2013 }
2014
2015 if (losing)
2016 break;
2017 }
2018
2019 /* Since we have found the correct instruction, copy
2020 in the modifications that we may have made. */
2021 if (!losing)
2022 for (i = 0; i < opsfound; i++)
2023 the_ins.operands[i] = operands_backup[i];
2024 }
2025
2026 if (!losing)
2027 break;
2028
2029 opcode = opcode->m_next;
2030
2031 if (!opcode)
2032 {
2033 if (ok_arch
2034 && !(ok_arch & current_architecture))
2035 {
2036 char buf[200], *cp;
2037
2038 strncpy (buf,
2039 _("invalid instruction for this architecture; needs "),
2040 sizeof (buf));
2041 cp = buf + strlen (buf);
2042 switch (ok_arch)
2043 {
2044 case mcfisa_a:
2045 strncpy (cp, _("ColdFire ISA_A"),
2046 sizeof (buf) - (cp - buf));
2047 cp += strlen (cp);
2048 strncpy (cp, find_cf_chip (ok_arch),
2049 sizeof (buf) - (cp - buf));
2050 cp += strlen (cp);
2051 break;
2052 case mcfhwdiv:
2053 strncpy (cp, _("ColdFire hardware divide"),
2054 sizeof (buf) - (cp - buf));
2055 cp += strlen (cp);
2056 strncpy (cp, find_cf_chip (ok_arch),
2057 sizeof (buf) - (cp - buf));
2058 cp += strlen (cp);
2059 break;
2060 case mcfisa_aa:
2061 strncpy (cp, _("ColdFire ISA_A+"),
2062 sizeof (buf) - (cp - buf));
2063 cp += strlen (cp);
2064 strncpy (cp, find_cf_chip (ok_arch),
2065 sizeof (buf) - (cp - buf));
2066 cp += strlen (cp);
2067 break;
2068 case mcfisa_b:
2069 strncpy (cp, _("ColdFire ISA_B"),
2070 sizeof (buf) - (cp - buf));
2071 cp += strlen (cp);
2072 strncpy (cp, find_cf_chip (ok_arch),
2073 sizeof (buf) - (cp - buf));
2074 cp += strlen (cp);
2075 break;
2076 case cfloat:
2077 strncpy (cp, _("ColdFire fpu"), sizeof (buf) - (cp - buf));
2078 cp += strlen (cp);
2079 strncpy (cp, find_cf_chip (ok_arch),
2080 sizeof (buf) - (cp - buf));
2081 cp += strlen (cp);
2082 break;
2083 case mfloat:
2084 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
2085 break;
2086 case mmmu:
2087 strcpy (cp, _("mmu (68030 or 68851)"));
2088 break;
2089 case m68020up:
2090 strcpy (cp, _("68020 or higher"));
2091 break;
2092 case m68000up:
2093 strcpy (cp, _("68000 or higher"));
2094 break;
2095 case m68010up:
2096 strcpy (cp, _("68010 or higher"));
2097 break;
2098 default:
2099 {
2100 int got_one = 0, idx;
2101
2102 for (idx = 0; m68k_cpus[idx].name; idx++)
2103 {
2104 if ((m68k_cpus[idx].arch & ok_arch)
2105 && ! m68k_cpus[idx].alias)
2106 {
2107 if (got_one)
2108 {
2109 strcpy (cp, " or ");
2110 cp += strlen (cp);
2111 }
2112 got_one = 1;
2113 strcpy (cp, m68k_cpus[idx].name);
2114 cp += strlen (cp);
2115 }
2116 }
2117 }
2118 }
2119 cp = xmalloc (strlen (buf) + 1);
2120 strcpy (cp, buf);
2121 the_ins.error = cp;
2122 }
2123 else
2124 the_ins.error = _("operands mismatch");
2125 return;
2126 }
2127
2128 losing = 0;
2129 }
2130
2131 /* Now assemble it. */
2132 the_ins.args = opcode->m_operands;
2133 the_ins.numargs = opcode->m_opnum;
2134 the_ins.numo = opcode->m_codenum;
2135 the_ins.opcode[0] = getone (opcode);
2136 the_ins.opcode[1] = gettwo (opcode);
2137
2138 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2139 {
2140 /* This switch is a doozy.
2141 Watch the first step; its a big one! */
2142 switch (s[0])
2143 {
2144
2145 case '*':
2146 case '~':
2147 case '%':
2148 case ';':
2149 case '@':
2150 case '!':
2151 case '&':
2152 case '$':
2153 case '?':
2154 case '/':
2155 case '<':
2156 case '>':
2157 case 'b':
2158 case 'm':
2159 case 'n':
2160 case 'o':
2161 case 'p':
2162 case 'q':
2163 case 'v':
2164 case 'w':
2165 case 'y':
2166 case 'z':
2167 case '4':
2168 #ifndef NO_68851
2169 case '|':
2170 #endif
2171 switch (opP->mode)
2172 {
2173 case IMMED:
2174 tmpreg = 0x3c; /* 7.4 */
2175 if (strchr ("bwl", s[1]))
2176 nextword = get_num (&opP->disp, 90);
2177 else
2178 nextword = get_num (&opP->disp, 0);
2179 if (isvar (&opP->disp))
2180 add_fix (s[1], &opP->disp, 0, 0);
2181 switch (s[1])
2182 {
2183 case 'b':
2184 if (!isbyte (nextword))
2185 opP->error = _("operand out of range");
2186 addword (nextword);
2187 baseo = 0;
2188 break;
2189 case 'w':
2190 if (!isword (nextword))
2191 opP->error = _("operand out of range");
2192 addword (nextword);
2193 baseo = 0;
2194 break;
2195 case 'W':
2196 if (!issword (nextword))
2197 opP->error = _("operand out of range");
2198 addword (nextword);
2199 baseo = 0;
2200 break;
2201 case 'l':
2202 addword (nextword >> 16);
2203 addword (nextword);
2204 baseo = 0;
2205 break;
2206
2207 case 'f':
2208 baseo = 2;
2209 outro = 8;
2210 break;
2211 case 'F':
2212 baseo = 4;
2213 outro = 11;
2214 break;
2215 case 'x':
2216 baseo = 6;
2217 outro = 15;
2218 break;
2219 case 'p':
2220 baseo = 6;
2221 outro = -1;
2222 break;
2223 default:
2224 abort ();
2225 }
2226 if (!baseo)
2227 break;
2228
2229 /* We gotta put out some float. */
2230 if (op (&opP->disp) != O_big)
2231 {
2232 valueT val;
2233 int gencnt;
2234
2235 /* Can other cases happen here? */
2236 if (op (&opP->disp) != O_constant)
2237 abort ();
2238
2239 val = (valueT) offs (&opP->disp);
2240 gencnt = 0;
2241 do
2242 {
2243 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2244 val >>= LITTLENUM_NUMBER_OF_BITS;
2245 ++gencnt;
2246 }
2247 while (val != 0);
2248 offs (&opP->disp) = gencnt;
2249 }
2250 if (offs (&opP->disp) > 0)
2251 {
2252 if (offs (&opP->disp) > baseo)
2253 {
2254 as_warn (_("Bignum too big for %c format; truncated"),
2255 s[1]);
2256 offs (&opP->disp) = baseo;
2257 }
2258 baseo -= offs (&opP->disp);
2259 while (baseo--)
2260 addword (0);
2261 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2262 offs (&opP->disp)--;
2263 --wordp)
2264 addword (*wordp);
2265 break;
2266 }
2267 gen_to_words (words, baseo, (long) outro);
2268 for (wordp = words; baseo--; wordp++)
2269 addword (*wordp);
2270 break;
2271 case DREG:
2272 tmpreg = opP->reg - DATA; /* 0.dreg */
2273 break;
2274 case AREG:
2275 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2276 break;
2277 case AINDR:
2278 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2279 break;
2280 case ADEC:
2281 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2282 break;
2283 case AINC:
2284 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2285 break;
2286 case DISP:
2287
2288 nextword = get_num (&opP->disp, 90);
2289
2290 /* Convert mode 5 addressing with a zero offset into
2291 mode 2 addressing to reduce the instruction size by a
2292 word. */
2293 if (! isvar (&opP->disp)
2294 && (nextword == 0)
2295 && (opP->disp.size == SIZE_UNSPEC)
2296 && (opP->reg >= ADDR0)
2297 && (opP->reg <= ADDR7))
2298 {
2299 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2300 break;
2301 }
2302
2303 if (opP->reg == PC
2304 && ! isvar (&opP->disp)
2305 && m68k_abspcadd)
2306 {
2307 opP->disp.exp.X_op = O_symbol;
2308 opP->disp.exp.X_add_symbol =
2309 section_symbol (absolute_section);
2310 }
2311
2312 /* Force into index mode. Hope this works. */
2313
2314 /* We do the first bit for 32-bit displacements, and the
2315 second bit for 16 bit ones. It is possible that we
2316 should make the default be WORD instead of LONG, but
2317 I think that'd break GCC, so we put up with a little
2318 inefficiency for the sake of working output. */
2319
2320 if (!issword (nextword)
2321 || (isvar (&opP->disp)
2322 && ((opP->disp.size == SIZE_UNSPEC
2323 && flag_short_refs == 0
2324 && cpu_of_arch (current_architecture) >= m68020
2325 && ! arch_coldfire_p (current_architecture))
2326 || opP->disp.size == SIZE_LONG)))
2327 {
2328 if (cpu_of_arch (current_architecture) < m68020
2329 || arch_coldfire_p (current_architecture))
2330 opP->error =
2331 _("displacement too large for this architecture; needs 68020 or higher");
2332 if (opP->reg == PC)
2333 tmpreg = 0x3B; /* 7.3 */
2334 else
2335 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2336 if (isvar (&opP->disp))
2337 {
2338 if (opP->reg == PC)
2339 {
2340 if (opP->disp.size == SIZE_LONG
2341 #ifdef OBJ_ELF
2342 /* If the displacement needs pic
2343 relocation it cannot be relaxed. */
2344 || opP->disp.pic_reloc != pic_none
2345 #endif
2346 )
2347 {
2348 addword (0x0170);
2349 add_fix ('l', &opP->disp, 1, 2);
2350 }
2351 else
2352 {
2353 add_frag (adds (&opP->disp),
2354 SEXT (offs (&opP->disp)),
2355 TAB (PCREL1632, SZ_UNDEF));
2356 break;
2357 }
2358 }
2359 else
2360 {
2361 addword (0x0170);
2362 add_fix ('l', &opP->disp, 0, 0);
2363 }
2364 }
2365 else
2366 addword (0x0170);
2367 addword (nextword >> 16);
2368 }
2369 else
2370 {
2371 if (opP->reg == PC)
2372 tmpreg = 0x3A; /* 7.2 */
2373 else
2374 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2375
2376 if (isvar (&opP->disp))
2377 {
2378 if (opP->reg == PC)
2379 {
2380 add_fix ('w', &opP->disp, 1, 0);
2381 }
2382 else
2383 add_fix ('w', &opP->disp, 0, 0);
2384 }
2385 }
2386 addword (nextword);
2387 break;
2388
2389 case POST:
2390 case PRE:
2391 case BASE:
2392 nextword = 0;
2393 baseo = get_num (&opP->disp, 90);
2394 if (opP->mode == POST || opP->mode == PRE)
2395 outro = get_num (&opP->odisp, 90);
2396 /* Figure out the `addressing mode'.
2397 Also turn on the BASE_DISABLE bit, if needed. */
2398 if (opP->reg == PC || opP->reg == ZPC)
2399 {
2400 tmpreg = 0x3b; /* 7.3 */
2401 if (opP->reg == ZPC)
2402 nextword |= 0x80;
2403 }
2404 else if (opP->reg == 0)
2405 {
2406 nextword |= 0x80;
2407 tmpreg = 0x30; /* 6.garbage */
2408 }
2409 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2410 {
2411 nextword |= 0x80;
2412 tmpreg = 0x30 + opP->reg - ZADDR0;
2413 }
2414 else
2415 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2416
2417 siz1 = opP->disp.size;
2418 if (opP->mode == POST || opP->mode == PRE)
2419 siz2 = opP->odisp.size;
2420 else
2421 siz2 = SIZE_UNSPEC;
2422
2423 /* Index register stuff. */
2424 if (opP->index.reg != 0
2425 && opP->index.reg >= DATA
2426 && opP->index.reg <= ADDR7)
2427 {
2428 nextword |= (opP->index.reg - DATA) << 12;
2429
2430 if (opP->index.size == SIZE_LONG
2431 || (opP->index.size == SIZE_UNSPEC
2432 && m68k_index_width_default == SIZE_LONG))
2433 nextword |= 0x800;
2434
2435 if ((opP->index.scale != 1
2436 && cpu_of_arch (current_architecture) < m68020)
2437 || (opP->index.scale == 8
2438 && (arch_coldfire_p (current_architecture)
2439 && !arch_coldfire_fpu (current_architecture))))
2440 {
2441 opP->error =
2442 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2443 }
2444
2445 if (arch_coldfire_p (current_architecture)
2446 && opP->index.size == SIZE_WORD)
2447 opP->error = _("invalid index size for coldfire");
2448
2449 switch (opP->index.scale)
2450 {
2451 case 1:
2452 break;
2453 case 2:
2454 nextword |= 0x200;
2455 break;
2456 case 4:
2457 nextword |= 0x400;
2458 break;
2459 case 8:
2460 nextword |= 0x600;
2461 break;
2462 default:
2463 abort ();
2464 }
2465 /* IF its simple,
2466 GET US OUT OF HERE! */
2467
2468 /* Must be INDEX, with an index register. Address
2469 register cannot be ZERO-PC, and either :b was
2470 forced, or we know it will fit. For a 68000 or
2471 68010, force this mode anyways, because the
2472 larger modes aren't supported. */
2473 if (opP->mode == BASE
2474 && ((opP->reg >= ADDR0
2475 && opP->reg <= ADDR7)
2476 || opP->reg == PC))
2477 {
2478 if (siz1 == SIZE_BYTE
2479 || cpu_of_arch (current_architecture) < m68020
2480 || arch_coldfire_p (current_architecture)
2481 || (siz1 == SIZE_UNSPEC
2482 && ! isvar (&opP->disp)
2483 && issbyte (baseo)))
2484 {
2485 nextword += baseo & 0xff;
2486 addword (nextword);
2487 if (isvar (&opP->disp))
2488 {
2489 /* Do a byte relocation. If it doesn't
2490 fit (possible on m68000) let the
2491 fixup processing complain later. */
2492 if (opP->reg == PC)
2493 add_fix ('B', &opP->disp, 1, 1);
2494 else
2495 add_fix ('B', &opP->disp, 0, 0);
2496 }
2497 else if (siz1 != SIZE_BYTE)
2498 {
2499 if (siz1 != SIZE_UNSPEC)
2500 as_warn (_("Forcing byte displacement"));
2501 if (! issbyte (baseo))
2502 opP->error = _("byte displacement out of range");
2503 }
2504
2505 break;
2506 }
2507 else if (siz1 == SIZE_UNSPEC
2508 && opP->reg == PC
2509 && isvar (&opP->disp)
2510 && subs (&opP->disp) == NULL
2511 #ifdef OBJ_ELF
2512 /* If the displacement needs pic
2513 relocation it cannot be relaxed. */
2514 && opP->disp.pic_reloc == pic_none
2515 #endif
2516 )
2517 {
2518 /* The code in md_convert_frag_1 needs to be
2519 able to adjust nextword. Call frag_grow
2520 to ensure that we have enough space in
2521 the frag obstack to make all the bytes
2522 contiguous. */
2523 frag_grow (14);
2524 nextword += baseo & 0xff;
2525 addword (nextword);
2526 add_frag (adds (&opP->disp),
2527 SEXT (offs (&opP->disp)),
2528 TAB (PCINDEX, SZ_UNDEF));
2529
2530 break;
2531 }
2532 }
2533 }
2534 else
2535 {
2536 nextword |= 0x40; /* No index reg. */
2537 if (opP->index.reg >= ZDATA0
2538 && opP->index.reg <= ZDATA7)
2539 nextword |= (opP->index.reg - ZDATA0) << 12;
2540 else if (opP->index.reg >= ZADDR0
2541 || opP->index.reg <= ZADDR7)
2542 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2543 }
2544
2545 /* It isn't simple. */
2546
2547 if (cpu_of_arch (current_architecture) < m68020
2548 || arch_coldfire_p (current_architecture))
2549 opP->error =
2550 _("invalid operand mode for this architecture; needs 68020 or higher");
2551
2552 nextword |= 0x100;
2553 /* If the guy specified a width, we assume that it is
2554 wide enough. Maybe it isn't. If so, we lose. */
2555 switch (siz1)
2556 {
2557 case SIZE_UNSPEC:
2558 if (isvar (&opP->disp)
2559 ? m68k_rel32
2560 : ! issword (baseo))
2561 {
2562 siz1 = SIZE_LONG;
2563 nextword |= 0x30;
2564 }
2565 else if (! isvar (&opP->disp) && baseo == 0)
2566 nextword |= 0x10;
2567 else
2568 {
2569 nextword |= 0x20;
2570 siz1 = SIZE_WORD;
2571 }
2572 break;
2573 case SIZE_BYTE:
2574 as_warn (_(":b not permitted; defaulting to :w"));
2575 /* Fall through. */
2576 case SIZE_WORD:
2577 nextword |= 0x20;
2578 break;
2579 case SIZE_LONG:
2580 nextword |= 0x30;
2581 break;
2582 }
2583
2584 /* Figure out inner displacement stuff. */
2585 if (opP->mode == POST || opP->mode == PRE)
2586 {
2587 if (cpu_of_arch (current_architecture) & cpu32)
2588 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2589 switch (siz2)
2590 {
2591 case SIZE_UNSPEC:
2592 if (isvar (&opP->odisp)
2593 ? m68k_rel32
2594 : ! issword (outro))
2595 {
2596 siz2 = SIZE_LONG;
2597 nextword |= 0x3;
2598 }
2599 else if (! isvar (&opP->odisp) && outro == 0)
2600 nextword |= 0x1;
2601 else
2602 {
2603 nextword |= 0x2;
2604 siz2 = SIZE_WORD;
2605 }
2606 break;
2607 case 1:
2608 as_warn (_(":b not permitted; defaulting to :w"));
2609 /* Fall through. */
2610 case 2:
2611 nextword |= 0x2;
2612 break;
2613 case 3:
2614 nextword |= 0x3;
2615 break;
2616 }
2617 if (opP->mode == POST
2618 && (nextword & 0x40) == 0)
2619 nextword |= 0x04;
2620 }
2621 addword (nextword);
2622
2623 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2624 {
2625 if (opP->reg == PC || opP->reg == ZPC)
2626 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2627 else
2628 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2629 }
2630 if (siz1 == SIZE_LONG)
2631 addword (baseo >> 16);
2632 if (siz1 != SIZE_UNSPEC)
2633 addword (baseo);
2634
2635 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2636 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2637 if (siz2 == SIZE_LONG)
2638 addword (outro >> 16);
2639 if (siz2 != SIZE_UNSPEC)
2640 addword (outro);
2641
2642 break;
2643
2644 case ABSL:
2645 nextword = get_num (&opP->disp, 90);
2646 switch (opP->disp.size)
2647 {
2648 default:
2649 abort ();
2650 case SIZE_UNSPEC:
2651 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2652 {
2653 tmpreg = 0x38; /* 7.0 */
2654 addword (nextword);
2655 break;
2656 }
2657 if (isvar (&opP->disp)
2658 && !subs (&opP->disp)
2659 && adds (&opP->disp)
2660 #ifdef OBJ_ELF
2661 /* If the displacement needs pic relocation it
2662 cannot be relaxed. */
2663 && opP->disp.pic_reloc == pic_none
2664 #endif
2665 && !flag_long_jumps
2666 && !strchr ("~%&$?", s[0]))
2667 {
2668 tmpreg = 0x3A; /* 7.2 */
2669 add_frag (adds (&opP->disp),
2670 SEXT (offs (&opP->disp)),
2671 TAB (ABSTOPCREL, SZ_UNDEF));
2672 break;
2673 }
2674 /* Fall through into long. */
2675 case SIZE_LONG:
2676 if (isvar (&opP->disp))
2677 add_fix ('l', &opP->disp, 0, 0);
2678
2679 tmpreg = 0x39;/* 7.1 mode */
2680 addword (nextword >> 16);
2681 addword (nextword);
2682 break;
2683
2684 case SIZE_BYTE:
2685 as_bad (_("unsupported byte value; use a different suffix"));
2686 /* Fall through. */
2687
2688 case SIZE_WORD:
2689 if (isvar (&opP->disp))
2690 add_fix ('w', &opP->disp, 0, 0);
2691
2692 tmpreg = 0x38;/* 7.0 mode */
2693 addword (nextword);
2694 break;
2695 }
2696 break;
2697 case CONTROL:
2698 case FPREG:
2699 default:
2700 as_bad (_("unknown/incorrect operand"));
2701 /* abort (); */
2702 }
2703
2704 /* If s[0] is '4', then this is for the mac instructions
2705 that can have a trailing_ampersand set. If so, set 0x100
2706 bit on tmpreg so install_gen_operand can check for it and
2707 set the appropriate bit (word2, bit 5). */
2708 if (s[0] == '4')
2709 {
2710 if (opP->trailing_ampersand)
2711 tmpreg |= 0x100;
2712 }
2713 install_gen_operand (s[1], tmpreg);
2714 break;
2715
2716 case '#':
2717 case '^':
2718 switch (s[1])
2719 { /* JF: I hate floating point! */
2720 case 'j':
2721 tmpreg = 70;
2722 break;
2723 case '8':
2724 tmpreg = 20;
2725 break;
2726 case 'C':
2727 tmpreg = 50;
2728 break;
2729 case '3':
2730 default:
2731 tmpreg = 90;
2732 break;
2733 }
2734 tmpreg = get_num (&opP->disp, tmpreg);
2735 if (isvar (&opP->disp))
2736 add_fix (s[1], &opP->disp, 0, 0);
2737 switch (s[1])
2738 {
2739 case 'b': /* Danger: These do no check for
2740 certain types of overflow.
2741 user beware! */
2742 if (!isbyte (tmpreg))
2743 opP->error = _("out of range");
2744 insop (tmpreg, opcode);
2745 if (isvar (&opP->disp))
2746 the_ins.reloc[the_ins.nrel - 1].n =
2747 (opcode->m_codenum) * 2 + 1;
2748 break;
2749 case 'B':
2750 if (!issbyte (tmpreg))
2751 opP->error = _("out of range");
2752 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2753 if (isvar (&opP->disp))
2754 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2755 break;
2756 case 'w':
2757 if (!isword (tmpreg))
2758 opP->error = _("out of range");
2759 insop (tmpreg, opcode);
2760 if (isvar (&opP->disp))
2761 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2762 break;
2763 case 'W':
2764 if (!issword (tmpreg))
2765 opP->error = _("out of range");
2766 insop (tmpreg, opcode);
2767 if (isvar (&opP->disp))
2768 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2769 break;
2770 case 'l':
2771 /* Because of the way insop works, we put these two out
2772 backwards. */
2773 insop (tmpreg, opcode);
2774 insop (tmpreg >> 16, opcode);
2775 if (isvar (&opP->disp))
2776 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2777 break;
2778 case '3':
2779 tmpreg &= 0xFF;
2780 case '8':
2781 case 'C':
2782 case 'j':
2783 install_operand (s[1], tmpreg);
2784 break;
2785 default:
2786 abort ();
2787 }
2788 break;
2789
2790 case '+':
2791 case '-':
2792 case 'A':
2793 case 'a':
2794 install_operand (s[1], opP->reg - ADDR);
2795 break;
2796
2797 case 'B':
2798 tmpreg = get_num (&opP->disp, 90);
2799 switch (s[1])
2800 {
2801 case 'B':
2802 add_fix ('B', &opP->disp, 1, -1);
2803 break;
2804 case 'W':
2805 add_fix ('w', &opP->disp, 1, 0);
2806 addword (0);
2807 break;
2808 case 'L':
2809 long_branch:
2810 if (! HAVE_LONG_BRANCH (current_architecture))
2811 as_warn (_("Can't use long branches on 68000/68010/5200"));
2812 the_ins.opcode[0] |= 0xff;
2813 add_fix ('l', &opP->disp, 1, 0);
2814 addword (0);
2815 addword (0);
2816 break;
2817 case 'g':
2818 if (subs (&opP->disp)) /* We can't relax it. */
2819 goto long_branch;
2820
2821 #ifdef OBJ_ELF
2822 /* If the displacement needs pic relocation it cannot be
2823 relaxed. */
2824 if (opP->disp.pic_reloc != pic_none)
2825 goto long_branch;
2826 #endif
2827 /* This could either be a symbol, or an absolute
2828 address. If it's an absolute address, turn it into
2829 an absolute jump right here and keep it out of the
2830 relaxer. */
2831 if (adds (&opP->disp) == 0)
2832 {
2833 if (the_ins.opcode[0] == 0x6000) /* jbra */
2834 the_ins.opcode[0] = 0x4EF9;
2835 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2836 the_ins.opcode[0] = 0x4EB9;
2837 else /* jCC */
2838 {
2839 the_ins.opcode[0] ^= 0x0100;
2840 the_ins.opcode[0] |= 0x0006;
2841 addword (0x4EF9);
2842 }
2843 add_fix ('l', &opP->disp, 0, 0);
2844 addword (0);
2845 addword (0);
2846 break;
2847 }
2848
2849 /* Now we know it's going into the relaxer. Now figure
2850 out which mode. We try in this order of preference:
2851 long branch, absolute jump, byte/word branches only. */
2852 if (HAVE_LONG_BRANCH (current_architecture))
2853 add_frag (adds (&opP->disp),
2854 SEXT (offs (&opP->disp)),
2855 TAB (BRANCHBWL, SZ_UNDEF));
2856 else if (! flag_keep_pcrel)
2857 {
2858 if ((the_ins.opcode[0] == 0x6000)
2859 || (the_ins.opcode[0] == 0x6100))
2860 add_frag (adds (&opP->disp),
2861 SEXT (offs (&opP->disp)),
2862 TAB (BRABSJUNC, SZ_UNDEF));
2863 else
2864 add_frag (adds (&opP->disp),
2865 SEXT (offs (&opP->disp)),
2866 TAB (BRABSJCOND, SZ_UNDEF));
2867 }
2868 else
2869 add_frag (adds (&opP->disp),
2870 SEXT (offs (&opP->disp)),
2871 TAB (BRANCHBW, SZ_UNDEF));
2872 break;
2873 case 'w':
2874 if (isvar (&opP->disp))
2875 {
2876 /* Check for DBcc instructions. We can relax them,
2877 but only if we have long branches and/or absolute
2878 jumps. */
2879 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2880 && (HAVE_LONG_BRANCH (current_architecture)
2881 || (! flag_keep_pcrel)))
2882 {
2883 if (HAVE_LONG_BRANCH (current_architecture))
2884 add_frag (adds (&opP->disp),
2885 SEXT (offs (&opP->disp)),
2886 TAB (DBCCLBR, SZ_UNDEF));
2887 else
2888 add_frag (adds (&opP->disp),
2889 SEXT (offs (&opP->disp)),
2890 TAB (DBCCABSJ, SZ_UNDEF));
2891 break;
2892 }
2893 add_fix ('w', &opP->disp, 1, 0);
2894 }
2895 addword (0);
2896 break;
2897 case 'C': /* Fixed size LONG coproc branches. */
2898 add_fix ('l', &opP->disp, 1, 0);
2899 addword (0);
2900 addword (0);
2901 break;
2902 case 'c': /* Var size Coprocesssor branches. */
2903 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
2904 {
2905 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2906 add_fix ('l', &opP->disp, 1, 0);
2907 addword (0);
2908 addword (0);
2909 }
2910 else
2911 add_frag (adds (&opP->disp),
2912 SEXT (offs (&opP->disp)),
2913 TAB (FBRANCH, SZ_UNDEF));
2914 break;
2915 default:
2916 abort ();
2917 }
2918 break;
2919
2920 case 'C': /* Ignore it. */
2921 break;
2922
2923 case 'd': /* JF this is a kludge. */
2924 install_operand ('s', opP->reg - ADDR);
2925 tmpreg = get_num (&opP->disp, 90);
2926 if (!issword (tmpreg))
2927 {
2928 as_warn (_("Expression out of range, using 0"));
2929 tmpreg = 0;
2930 }
2931 addword (tmpreg);
2932 break;
2933
2934 case 'D':
2935 install_operand (s[1], opP->reg - DATA);
2936 break;
2937
2938 case 'e': /* EMAC ACCx, reg/reg. */
2939 install_operand (s[1], opP->reg - ACC);
2940 break;
2941
2942 case 'E': /* Ignore it. */
2943 break;
2944
2945 case 'F':
2946 install_operand (s[1], opP->reg - FP0);
2947 break;
2948
2949 case 'g': /* EMAC ACCEXTx. */
2950 install_operand (s[1], opP->reg - ACCEXT01);
2951 break;
2952
2953 case 'G': /* Ignore it. */
2954 case 'H':
2955 break;
2956
2957 case 'I':
2958 tmpreg = opP->reg - COP0;
2959 install_operand (s[1], tmpreg);
2960 break;
2961
2962 case 'i': /* MAC/EMAC scale factor. */
2963 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
2964 break;
2965
2966 case 'J': /* JF foo. */
2967 switch (opP->reg)
2968 {
2969 case SFC:
2970 tmpreg = 0x000;
2971 break;
2972 case DFC:
2973 tmpreg = 0x001;
2974 break;
2975 case CACR:
2976 tmpreg = 0x002;
2977 break;
2978 case TC:
2979 tmpreg = 0x003;
2980 break;
2981 case ACR0:
2982 case ITT0:
2983 tmpreg = 0x004;
2984 break;
2985 case ACR1:
2986 case ITT1:
2987 tmpreg = 0x005;
2988 break;
2989 case ACR2:
2990 case DTT0:
2991 tmpreg = 0x006;
2992 break;
2993 case ACR3:
2994 case DTT1:
2995 tmpreg = 0x007;
2996 break;
2997 case BUSCR:
2998 tmpreg = 0x008;
2999 break;
3000
3001 case USP:
3002 tmpreg = 0x800;
3003 break;
3004 case VBR:
3005 tmpreg = 0x801;
3006 break;
3007 case CAAR:
3008 tmpreg = 0x802;
3009 break;
3010 case MSP:
3011 tmpreg = 0x803;
3012 break;
3013 case ISP:
3014 tmpreg = 0x804;
3015 break;
3016 case MMUSR:
3017 tmpreg = 0x805;
3018 break;
3019 case URP:
3020 tmpreg = 0x806;
3021 break;
3022 case SRP:
3023 tmpreg = 0x807;
3024 break;
3025 case PCR:
3026 tmpreg = 0x808;
3027 break;
3028 case ROMBAR:
3029 tmpreg = 0xC00;
3030 break;
3031 case ROMBAR1:
3032 tmpreg = 0xC01;
3033 break;
3034 case FLASHBAR:
3035 case RAMBAR0:
3036 tmpreg = 0xC04;
3037 break;
3038 case RAMBAR:
3039 case RAMBAR1:
3040 tmpreg = 0xC05;
3041 break;
3042 case MPCR:
3043 tmpreg = 0xC0C;
3044 break;
3045 case EDRAMBAR:
3046 tmpreg = 0xC0D;
3047 break;
3048 case MBAR0:
3049 case MBAR2:
3050 case SECMBAR:
3051 tmpreg = 0xC0E;
3052 break;
3053 case MBAR1:
3054 case MBAR:
3055 tmpreg = 0xC0F;
3056 break;
3057 case PCR1U0:
3058 tmpreg = 0xD02;
3059 break;
3060 case PCR1L0:
3061 tmpreg = 0xD03;
3062 break;
3063 case PCR2U0:
3064 tmpreg = 0xD04;
3065 break;
3066 case PCR2L0:
3067 tmpreg = 0xD05;
3068 break;
3069 case PCR3U0:
3070 tmpreg = 0xD06;
3071 break;
3072 case PCR3L0:
3073 tmpreg = 0xD07;
3074 break;
3075 case PCR1L1:
3076 tmpreg = 0xD0A;
3077 break;
3078 case PCR1U1:
3079 tmpreg = 0xD0B;
3080 break;
3081 case PCR2L1:
3082 tmpreg = 0xD0C;
3083 break;
3084 case PCR2U1:
3085 tmpreg = 0xD0D;
3086 break;
3087 case PCR3L1:
3088 tmpreg = 0xD0E;
3089 break;
3090 case PCR3U1:
3091 tmpreg = 0xD0F;
3092 break;
3093 default:
3094 abort ();
3095 }
3096 install_operand (s[1], tmpreg);
3097 break;
3098
3099 case 'k':
3100 tmpreg = get_num (&opP->disp, 55);
3101 install_operand (s[1], tmpreg & 0x7f);
3102 break;
3103
3104 case 'l':
3105 tmpreg = opP->mask;
3106 if (s[1] == 'w')
3107 {
3108 if (tmpreg & 0x7FF0000)
3109 as_bad (_("Floating point register in register list"));
3110 insop (reverse_16_bits (tmpreg), opcode);
3111 }
3112 else
3113 {
3114 if (tmpreg & 0x700FFFF)
3115 as_bad (_("Wrong register in floating-point reglist"));
3116 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3117 }
3118 break;
3119
3120 case 'L':
3121 tmpreg = opP->mask;
3122 if (s[1] == 'w')
3123 {
3124 if (tmpreg & 0x7FF0000)
3125 as_bad (_("Floating point register in register list"));
3126 insop (tmpreg, opcode);
3127 }
3128 else if (s[1] == '8')
3129 {
3130 if (tmpreg & 0x0FFFFFF)
3131 as_bad (_("incorrect register in reglist"));
3132 install_operand (s[1], tmpreg >> 24);
3133 }
3134 else
3135 {
3136 if (tmpreg & 0x700FFFF)
3137 as_bad (_("wrong register in floating-point reglist"));
3138 else
3139 install_operand (s[1], tmpreg >> 16);
3140 }
3141 break;
3142
3143 case 'M':
3144 install_operand (s[1], get_num (&opP->disp, 60));
3145 break;
3146
3147 case 'O':
3148 tmpreg = ((opP->mode == DREG)
3149 ? 0x20 + (int) (opP->reg - DATA)
3150 : (get_num (&opP->disp, 40) & 0x1F));
3151 install_operand (s[1], tmpreg);
3152 break;
3153
3154 case 'Q':
3155 tmpreg = get_num (&opP->disp, 10);
3156 if (tmpreg == 8)
3157 tmpreg = 0;
3158 install_operand (s[1], tmpreg);
3159 break;
3160
3161 case 'R':
3162 /* This depends on the fact that ADDR registers are eight
3163 more than their corresponding DATA regs, so the result
3164 will have the ADDR_REG bit set. */
3165 install_operand (s[1], opP->reg - DATA);
3166 break;
3167
3168 case 'r':
3169 if (opP->mode == AINDR)
3170 install_operand (s[1], opP->reg - DATA);
3171 else
3172 install_operand (s[1], opP->index.reg - DATA);
3173 break;
3174
3175 case 's':
3176 if (opP->reg == FPI)
3177 tmpreg = 0x1;
3178 else if (opP->reg == FPS)
3179 tmpreg = 0x2;
3180 else if (opP->reg == FPC)
3181 tmpreg = 0x4;
3182 else
3183 abort ();
3184 install_operand (s[1], tmpreg);
3185 break;
3186
3187 case 'S': /* Ignore it. */
3188 break;
3189
3190 case 'T':
3191 install_operand (s[1], get_num (&opP->disp, 30));
3192 break;
3193
3194 case 'U': /* Ignore it. */
3195 break;
3196
3197 case 'c':
3198 switch (opP->reg)
3199 {
3200 case NC:
3201 tmpreg = 0;
3202 break;
3203 case DC:
3204 tmpreg = 1;
3205 break;
3206 case IC:
3207 tmpreg = 2;
3208 break;
3209 case BC:
3210 tmpreg = 3;
3211 break;
3212 default:
3213 as_fatal (_("failed sanity check"));
3214 } /* switch on cache token. */
3215 install_operand (s[1], tmpreg);
3216 break;
3217 #ifndef NO_68851
3218 /* JF: These are out of order, I fear. */
3219 case 'f':
3220 switch (opP->reg)
3221 {
3222 case SFC:
3223 tmpreg = 0;
3224 break;
3225 case DFC:
3226 tmpreg = 1;
3227 break;
3228 default:
3229 abort ();
3230 }
3231 install_operand (s[1], tmpreg);
3232 break;
3233
3234 case '0':
3235 case '1':
3236 case '2':
3237 switch (opP->reg)
3238 {
3239 case TC:
3240 tmpreg = 0;
3241 break;
3242 case CAL:
3243 tmpreg = 4;
3244 break;
3245 case VAL:
3246 tmpreg = 5;
3247 break;
3248 case SCC:
3249 tmpreg = 6;
3250 break;
3251 case AC:
3252 tmpreg = 7;
3253 break;
3254 default:
3255 abort ();
3256 }
3257 install_operand (s[1], tmpreg);
3258 break;
3259
3260 case 'V':
3261 if (opP->reg == VAL)
3262 break;
3263 abort ();
3264
3265 case 'W':
3266 switch (opP->reg)
3267 {
3268 case DRP:
3269 tmpreg = 1;
3270 break;
3271 case SRP:
3272 tmpreg = 2;
3273 break;
3274 case CRP:
3275 tmpreg = 3;
3276 break;
3277 default:
3278 abort ();
3279 }
3280 install_operand (s[1], tmpreg);
3281 break;
3282
3283 case 'X':
3284 switch (opP->reg)
3285 {
3286 case BAD:
3287 case BAD + 1:
3288 case BAD + 2:
3289 case BAD + 3:
3290 case BAD + 4:
3291 case BAD + 5:
3292 case BAD + 6:
3293 case BAD + 7:
3294 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3295 break;
3296
3297 case BAC:
3298 case BAC + 1:
3299 case BAC + 2:
3300 case BAC + 3:
3301 case BAC + 4:
3302 case BAC + 5:
3303 case BAC + 6:
3304 case BAC + 7:
3305 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3306 break;
3307
3308 default:
3309 abort ();
3310 }
3311 install_operand (s[1], tmpreg);
3312 break;
3313 case 'Y':
3314 know (opP->reg == PSR);
3315 break;
3316 case 'Z':
3317 know (opP->reg == PCSR);
3318 break;
3319 #endif /* m68851 */
3320 case '3':
3321 switch (opP->reg)
3322 {
3323 case TT0:
3324 tmpreg = 2;
3325 break;
3326 case TT1:
3327 tmpreg = 3;
3328 break;
3329 default:
3330 abort ();
3331 }
3332 install_operand (s[1], tmpreg);
3333 break;
3334 case 't':
3335 tmpreg = get_num (&opP->disp, 20);
3336 install_operand (s[1], tmpreg);
3337 break;
3338 case '_': /* used only for move16 absolute 32-bit address. */
3339 if (isvar (&opP->disp))
3340 add_fix ('l', &opP->disp, 0, 0);
3341 tmpreg = get_num (&opP->disp, 90);
3342 addword (tmpreg >> 16);
3343 addword (tmpreg & 0xFFFF);
3344 break;
3345 case 'u':
3346 install_operand (s[1], opP->reg - DATA0L);
3347 opP->reg -= (DATA0L);
3348 opP->reg &= 0x0F; /* remove upper/lower bit. */
3349 break;
3350 case 'x':
3351 tmpreg = get_num (&opP->disp, 80);
3352 if (tmpreg == -1)
3353 tmpreg = 0;
3354 install_operand (s[1], tmpreg);
3355 break;
3356 default:
3357 abort ();
3358 }
3359 }
3360
3361 /* By the time whe get here (FINALLY) the_ins contains the complete
3362 instruction, ready to be emitted. . . */
3363 }
3364
3365 static int
3366 reverse_16_bits (int in)
3367 {
3368 int out = 0;
3369 int n;
3370
3371 static int mask[16] =
3372 {
3373 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3374 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3375 };
3376 for (n = 0; n < 16; n++)
3377 {
3378 if (in & mask[n])
3379 out |= mask[15 - n];
3380 }
3381 return out;
3382 } /* reverse_16_bits() */
3383
3384 static int
3385 reverse_8_bits (int in)
3386 {
3387 int out = 0;
3388 int n;
3389
3390 static int mask[8] =
3391 {
3392 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3393 };
3394
3395 for (n = 0; n < 8; n++)
3396 {
3397 if (in & mask[n])
3398 out |= mask[7 - n];
3399 }
3400 return out;
3401 } /* reverse_8_bits() */
3402
3403 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3404 (that value is chosen in the frag_var call in md_assemble). TYPE
3405 is the subtype of the frag to be generated; its primary type is
3406 rs_machine_dependent.
3407
3408 The TYPE parameter is also used by md_convert_frag_1 and
3409 md_estimate_size_before_relax. The appropriate type of fixup will
3410 be emitted by md_convert_frag_1.
3411
3412 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3413 static void
3414 install_operand (int mode, int val)
3415 {
3416 switch (mode)
3417 {
3418 case 's':
3419 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3420 break;
3421 case 'd':
3422 the_ins.opcode[0] |= val << 9;
3423 break;
3424 case '1':
3425 the_ins.opcode[1] |= val << 12;
3426 break;
3427 case '2':
3428 the_ins.opcode[1] |= val << 6;
3429 break;
3430 case '3':
3431 the_ins.opcode[1] |= val;
3432 break;
3433 case '4':
3434 the_ins.opcode[2] |= val << 12;
3435 break;
3436 case '5':
3437 the_ins.opcode[2] |= val << 6;
3438 break;
3439 case '6':
3440 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3441 three words long! */
3442 the_ins.numo++;
3443 the_ins.opcode[2] |= val;
3444 break;
3445 case '7':
3446 the_ins.opcode[1] |= val << 7;
3447 break;
3448 case '8':
3449 the_ins.opcode[1] |= val << 10;
3450 break;
3451 #ifndef NO_68851
3452 case '9':
3453 the_ins.opcode[1] |= val << 5;
3454 break;
3455 #endif
3456
3457 case 't':
3458 the_ins.opcode[1] |= (val << 10) | (val << 7);
3459 break;
3460 case 'D':
3461 the_ins.opcode[1] |= (val << 12) | val;
3462 break;
3463 case 'g':
3464 the_ins.opcode[0] |= val = 0xff;
3465 break;
3466 case 'i':
3467 the_ins.opcode[0] |= val << 9;
3468 break;
3469 case 'C':
3470 the_ins.opcode[1] |= val;
3471 break;
3472 case 'j':
3473 the_ins.opcode[1] |= val;
3474 the_ins.numo++; /* What a hack. */
3475 break;
3476 case 'k':
3477 the_ins.opcode[1] |= val << 4;
3478 break;
3479 case 'b':
3480 case 'w':
3481 case 'W':
3482 case 'l':
3483 break;
3484 case 'e':
3485 the_ins.opcode[0] |= (val << 6);
3486 break;
3487 case 'L':
3488 the_ins.opcode[1] = (val >> 16);
3489 the_ins.opcode[2] = val & 0xffff;
3490 break;
3491 case 'm':
3492 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3493 the_ins.opcode[0] |= ((val & 0x7) << 9);
3494 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3495 break;
3496 case 'n': /* MAC/EMAC Rx on !load. */
3497 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3498 the_ins.opcode[0] |= ((val & 0x7) << 9);
3499 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3500 break;
3501 case 'o': /* MAC/EMAC Rx on load. */
3502 the_ins.opcode[1] |= val << 12;
3503 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3504 break;
3505 case 'M': /* MAC/EMAC Ry on !load. */
3506 the_ins.opcode[0] |= (val & 0xF);
3507 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3508 break;
3509 case 'N': /* MAC/EMAC Ry on load. */
3510 the_ins.opcode[1] |= (val & 0xF);
3511 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3512 break;
3513 case 'h':
3514 the_ins.opcode[1] |= ((val != 1) << 10);
3515 break;
3516 case 'F':
3517 the_ins.opcode[0] |= ((val & 0x3) << 9);
3518 break;
3519 case 'f':
3520 the_ins.opcode[0] |= ((val & 0x3) << 0);
3521 break;
3522 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3523 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3524 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3525 break;
3526 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3527 the_ins.opcode[0] |= ((val & 0x1) << 7);
3528 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3529 break;
3530 case 'I':
3531 the_ins.opcode[1] |= ((val & 0x3) << 9);
3532 break;
3533 case ']':
3534 the_ins.opcode[0] |= (val & 0x1) <<10;
3535 break;
3536 case 'c':
3537 default:
3538 as_fatal (_("failed sanity check."));
3539 }
3540 }
3541
3542 static void
3543 install_gen_operand (int mode, int val)
3544 {
3545 switch (mode)
3546 {
3547 case '/': /* Special for mask loads for mac/msac insns with
3548 possible mask; trailing_ampersend set in bit 8. */
3549 the_ins.opcode[0] |= (val & 0x3f);
3550 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3551 break;
3552 case 's':
3553 the_ins.opcode[0] |= val;
3554 break;
3555 case 'd':
3556 /* This is a kludge!!! */
3557 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3558 break;
3559 case 'b':
3560 case 'w':
3561 case 'l':
3562 case 'f':
3563 case 'F':
3564 case 'x':
3565 case 'p':
3566 the_ins.opcode[0] |= val;
3567 break;
3568 /* more stuff goes here. */
3569 default:
3570 as_fatal (_("failed sanity check."));
3571 }
3572 }
3573
3574 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3575 then deal with the bitfield hack. */
3576
3577 static char *
3578 crack_operand (char *str, struct m68k_op *opP)
3579 {
3580 register int parens;
3581 register int c;
3582 register char *beg_str;
3583 int inquote = 0;
3584
3585 if (!str)
3586 {
3587 return str;
3588 }
3589 beg_str = str;
3590 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3591 {
3592 if (! inquote)
3593 {
3594 if (*str == '(')
3595 parens++;
3596 else if (*str == ')')
3597 {
3598 if (!parens)
3599 { /* ERROR. */
3600 opP->error = _("Extra )");
3601 return str;
3602 }
3603 --parens;
3604 }
3605 }
3606 if (flag_mri && *str == '\'')
3607 inquote = ! inquote;
3608 }
3609 if (!*str && parens)
3610 { /* ERROR. */
3611 opP->error = _("Missing )");
3612 return str;
3613 }
3614 c = *str;
3615 *str = '\0';
3616 if (m68k_ip_op (beg_str, opP) != 0)
3617 {
3618 *str = c;
3619 return str;
3620 }
3621 *str = c;
3622 if (c == '}')
3623 c = *++str; /* JF bitfield hack. */
3624 if (c)
3625 {
3626 c = *++str;
3627 if (!c)
3628 as_bad (_("Missing operand"));
3629 }
3630
3631 /* Detect MRI REG symbols and convert them to REGLSTs. */
3632 if (opP->mode == CONTROL && (int)opP->reg < 0)
3633 {
3634 opP->mode = REGLST;
3635 opP->mask = ~(int)opP->reg;
3636 opP->reg = 0;
3637 }
3638
3639 return str;
3640 }
3641
3642 /* This is the guts of the machine-dependent assembler. STR points to a
3643 machine dependent instruction. This function is supposed to emit
3644 the frags/bytes it assembles to.
3645 */
3646
3647 static void
3648 insert_reg (const char *regname, int regnum)
3649 {
3650 char buf[100];
3651 int i;
3652
3653 #ifdef REGISTER_PREFIX
3654 if (!flag_reg_prefix_optional)
3655 {
3656 buf[0] = REGISTER_PREFIX;
3657 strcpy (buf + 1, regname);
3658 regname = buf;
3659 }
3660 #endif
3661
3662 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3663 &zero_address_frag));
3664
3665 for (i = 0; regname[i]; i++)
3666 buf[i] = TOUPPER (regname[i]);
3667 buf[i] = '\0';
3668
3669 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3670 &zero_address_frag));
3671 }
3672
3673 struct init_entry
3674 {
3675 const char *name;
3676 int number;
3677 };
3678
3679 static const struct init_entry init_table[] =
3680 {
3681 { "d0", DATA0 },
3682 { "d1", DATA1 },
3683 { "d2", DATA2 },
3684 { "d3", DATA3 },
3685 { "d4", DATA4 },
3686 { "d5", DATA5 },
3687 { "d6", DATA6 },
3688 { "d7", DATA7 },
3689 { "a0", ADDR0 },
3690 { "a1", ADDR1 },
3691 { "a2", ADDR2 },
3692 { "a3", ADDR3 },
3693 { "a4", ADDR4 },
3694 { "a5", ADDR5 },
3695 { "a6", ADDR6 },
3696 { "fp", ADDR6 },
3697 { "a7", ADDR7 },
3698 { "sp", ADDR7 },
3699 { "ssp", ADDR7 },
3700 { "fp0", FP0 },
3701 { "fp1", FP1 },
3702 { "fp2", FP2 },
3703 { "fp3", FP3 },
3704 { "fp4", FP4 },
3705 { "fp5", FP5 },
3706 { "fp6", FP6 },
3707 { "fp7", FP7 },
3708 { "fpi", FPI },
3709 { "fpiar", FPI },
3710 { "fpc", FPI },
3711 { "fps", FPS },
3712 { "fpsr", FPS },
3713 { "fpc", FPC },
3714 { "fpcr", FPC },
3715 { "control", FPC },
3716 { "status", FPS },
3717 { "iaddr", FPI },
3718
3719 { "cop0", COP0 },
3720 { "cop1", COP1 },
3721 { "cop2", COP2 },
3722 { "cop3", COP3 },
3723 { "cop4", COP4 },
3724 { "cop5", COP5 },
3725 { "cop6", COP6 },
3726 { "cop7", COP7 },
3727 { "pc", PC },
3728 { "zpc", ZPC },
3729 { "sr", SR },
3730
3731 { "ccr", CCR },
3732 { "cc", CCR },
3733
3734 { "acc", ACC },
3735 { "acc0", ACC },
3736 { "acc1", ACC1 },
3737 { "acc2", ACC2 },
3738 { "acc3", ACC3 },
3739 { "accext01", ACCEXT01 },
3740 { "accext23", ACCEXT23 },
3741 { "macsr", MACSR },
3742 { "mask", MASK },
3743
3744 /* Control registers. */
3745 { "sfc", SFC }, /* Source Function Code. */
3746 { "sfcr", SFC },
3747 { "dfc", DFC }, /* Destination Function Code. */
3748 { "dfcr", DFC },
3749 { "cacr", CACR }, /* Cache Control Register. */
3750 { "caar", CAAR }, /* Cache Address Register. */
3751
3752 { "usp", USP }, /* User Stack Pointer. */
3753 { "vbr", VBR }, /* Vector Base Register. */
3754 { "msp", MSP }, /* Master Stack Pointer. */
3755 { "isp", ISP }, /* Interrupt Stack Pointer. */
3756
3757 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3758 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3759 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3760 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
3761
3762 /* 68ec040 versions of same */
3763 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3764 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3765 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3766 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
3767
3768 /* mcf5200 versions of same. The ColdFire programmer's reference
3769 manual indicated that the order is 2,3,0,1, but Ken Rose
3770 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3771 { "acr0", ACR0 }, /* Access Control Unit 0. */
3772 { "acr1", ACR1 }, /* Access Control Unit 1. */
3773 { "acr2", ACR2 }, /* Access Control Unit 2. */
3774 { "acr3", ACR3 }, /* Access Control Unit 3. */
3775
3776 { "tc", TC }, /* MMU Translation Control Register. */
3777 { "tcr", TC },
3778
3779 { "mmusr", MMUSR }, /* MMU Status Register. */
3780 { "srp", SRP }, /* User Root Pointer. */
3781 { "urp", URP }, /* Supervisor Root Pointer. */
3782
3783 { "buscr", BUSCR },
3784 { "pcr", PCR },
3785
3786 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3787 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3788 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3789 { "mbar", MBAR }, /* Module Base Address Register. */
3790
3791 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3792 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3793 { "rombar0", ROMBAR }, /* mcfv4e registers. */
3794 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3795 { "mpcr", MPCR }, /* mcfv4e registers. */
3796 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3797 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3798 { "asid", TC }, /* mcfv4e registers. */
3799 { "mmubar", BUSCR }, /* mcfv4e registers. */
3800 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3801 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3802 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3803 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3804 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3805 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3806 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3807 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3808 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3809 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3810 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3811 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3812
3813 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3814 { "rambar", RAMBAR }, /* mcf528x registers. */
3815
3816 { "mbar2", MBAR2 }, /* mcf5249 registers. */
3817 /* End of control registers. */
3818
3819 { "ac", AC },
3820 { "bc", BC },
3821 { "cal", CAL },
3822 { "crp", CRP },
3823 { "drp", DRP },
3824 { "pcsr", PCSR },
3825 { "psr", PSR },
3826 { "scc", SCC },
3827 { "val", VAL },
3828 { "bad0", BAD0 },
3829 { "bad1", BAD1 },
3830 { "bad2", BAD2 },
3831 { "bad3", BAD3 },
3832 { "bad4", BAD4 },
3833 { "bad5", BAD5 },
3834 { "bad6", BAD6 },
3835 { "bad7", BAD7 },
3836 { "bac0", BAC0 },
3837 { "bac1", BAC1 },
3838 { "bac2", BAC2 },
3839 { "bac3", BAC3 },
3840 { "bac4", BAC4 },
3841 { "bac5", BAC5 },
3842 { "bac6", BAC6 },
3843 { "bac7", BAC7 },
3844
3845 { "ic", IC },
3846 { "dc", DC },
3847 { "nc", NC },
3848
3849 { "tt0", TT0 },
3850 { "tt1", TT1 },
3851 /* 68ec030 versions of same. */
3852 { "ac0", TT0 },
3853 { "ac1", TT1 },
3854 /* 68ec030 access control unit, identical to 030 MMU status reg. */
3855 { "acusr", PSR },
3856
3857 /* Suppressed data and address registers. */
3858 { "zd0", ZDATA0 },
3859 { "zd1", ZDATA1 },
3860 { "zd2", ZDATA2 },
3861 { "zd3", ZDATA3 },
3862 { "zd4", ZDATA4 },
3863 { "zd5", ZDATA5 },
3864 { "zd6", ZDATA6 },
3865 { "zd7", ZDATA7 },
3866 { "za0", ZADDR0 },
3867 { "za1", ZADDR1 },
3868 { "za2", ZADDR2 },
3869 { "za3", ZADDR3 },
3870 { "za4", ZADDR4 },
3871 { "za5", ZADDR5 },
3872 { "za6", ZADDR6 },
3873 { "za7", ZADDR7 },
3874
3875 /* Upper and lower data and address registers, used by macw and msacw. */
3876 { "d0l", DATA0L },
3877 { "d1l", DATA1L },
3878 { "d2l", DATA2L },
3879 { "d3l", DATA3L },
3880 { "d4l", DATA4L },
3881 { "d5l", DATA5L },
3882 { "d6l", DATA6L },
3883 { "d7l", DATA7L },
3884
3885 { "a0l", ADDR0L },
3886 { "a1l", ADDR1L },
3887 { "a2l", ADDR2L },
3888 { "a3l", ADDR3L },
3889 { "a4l", ADDR4L },
3890 { "a5l", ADDR5L },
3891 { "a6l", ADDR6L },
3892 { "a7l", ADDR7L },
3893
3894 { "d0u", DATA0U },
3895 { "d1u", DATA1U },
3896 { "d2u", DATA2U },
3897 { "d3u", DATA3U },
3898 { "d4u", DATA4U },
3899 { "d5u", DATA5U },
3900 { "d6u", DATA6U },
3901 { "d7u", DATA7U },
3902
3903 { "a0u", ADDR0U },
3904 { "a1u", ADDR1U },
3905 { "a2u", ADDR2U },
3906 { "a3u", ADDR3U },
3907 { "a4u", ADDR4U },
3908 { "a5u", ADDR5U },
3909 { "a6u", ADDR6U },
3910 { "a7u", ADDR7U },
3911
3912 { 0, 0 }
3913 };
3914
3915 static void
3916 init_regtable (void)
3917 {
3918 int i;
3919 for (i = 0; init_table[i].name; i++)
3920 insert_reg (init_table[i].name, init_table[i].number);
3921 }
3922
3923 void
3924 md_assemble (char *str)
3925 {
3926 const char *er;
3927 short *fromP;
3928 char *toP = NULL;
3929 int m, n = 0;
3930 char *to_beg_P;
3931 int shorts_this_frag;
3932 fixS *fixP;
3933
3934 if (!selected_cpu && !selected_arch)
3935 {
3936 /* We've not selected an architecture yet. Set the default
3937 now. We do this lazily so that an initial .cpu or .arch directive
3938 can specify. */
3939 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
3940 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
3941 }
3942 if (!initialized)
3943 m68k_init_arch ();
3944
3945 /* In MRI mode, the instruction and operands are separated by a
3946 space. Anything following the operands is a comment. The label
3947 has already been removed. */
3948 if (flag_mri)
3949 {
3950 char *s;
3951 int fields = 0;
3952 int infield = 0;
3953 int inquote = 0;
3954
3955 for (s = str; *s != '\0'; s++)
3956 {
3957 if ((*s == ' ' || *s == '\t') && ! inquote)
3958 {
3959 if (infield)
3960 {
3961 ++fields;
3962 if (fields >= 2)
3963 {
3964 *s = '\0';
3965 break;
3966 }
3967 infield = 0;
3968 }
3969 }
3970 else
3971 {
3972 if (! infield)
3973 infield = 1;
3974 if (*s == '\'')
3975 inquote = ! inquote;
3976 }
3977 }
3978 }
3979
3980 memset (&the_ins, '\0', sizeof (the_ins));
3981 m68k_ip (str);
3982 er = the_ins.error;
3983 if (!er)
3984 {
3985 for (n = 0; n < the_ins.numargs; n++)
3986 if (the_ins.operands[n].error)
3987 {
3988 er = the_ins.operands[n].error;
3989 break;
3990 }
3991 }
3992 if (er)
3993 {
3994 as_bad (_("%s -- statement `%s' ignored"), er, str);
3995 return;
3996 }
3997
3998 /* If there is a current label, record that it marks an instruction. */
3999 if (current_label != NULL)
4000 {
4001 current_label->text = 1;
4002 current_label = NULL;
4003 }
4004
4005 #ifdef OBJ_ELF
4006 /* Tie dwarf2 debug info to the address at the start of the insn. */
4007 dwarf2_emit_insn (0);
4008 #endif
4009
4010 if (the_ins.nfrag == 0)
4011 {
4012 /* No frag hacking involved; just put it out. */
4013 toP = frag_more (2 * the_ins.numo);
4014 fromP = &the_ins.opcode[0];
4015 for (m = the_ins.numo; m; --m)
4016 {
4017 md_number_to_chars (toP, (long) (*fromP), 2);
4018 toP += 2;
4019 fromP++;
4020 }
4021 /* Put out symbol-dependent info. */
4022 for (m = 0; m < the_ins.nrel; m++)
4023 {
4024 switch (the_ins.reloc[m].wid)
4025 {
4026 case 'B':
4027 n = 1;
4028 break;
4029 case 'b':
4030 n = 1;
4031 break;
4032 case '3':
4033 n = 1;
4034 break;
4035 case 'w':
4036 case 'W':
4037 n = 2;
4038 break;
4039 case 'l':
4040 n = 4;
4041 break;
4042 default:
4043 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4044 the_ins.reloc[m].wid);
4045 }
4046
4047 fixP = fix_new_exp (frag_now,
4048 ((toP - frag_now->fr_literal)
4049 - the_ins.numo * 2 + the_ins.reloc[m].n),
4050 n,
4051 &the_ins.reloc[m].exp,
4052 the_ins.reloc[m].pcrel,
4053 get_reloc_code (n, the_ins.reloc[m].pcrel,
4054 the_ins.reloc[m].pic_reloc));
4055 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4056 if (the_ins.reloc[m].wid == 'B')
4057 fixP->fx_signed = 1;
4058 }
4059 return;
4060 }
4061
4062 /* There's some frag hacking. */
4063 {
4064 /* Calculate the max frag size. */
4065 int wid;
4066
4067 wid = 2 * the_ins.fragb[0].fragoff;
4068 for (n = 1; n < the_ins.nfrag; n++)
4069 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4070 /* frag_var part. */
4071 wid += 10;
4072 /* Make sure the whole insn fits in one chunk, in particular that
4073 the var part is attached, as we access one byte before the
4074 variable frag for byte branches. */
4075 frag_grow (wid);
4076 }
4077
4078 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4079 {
4080 int wid;
4081
4082 if (n == 0)
4083 wid = 2 * the_ins.fragb[n].fragoff;
4084 else
4085 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4086 toP = frag_more (wid);
4087 to_beg_P = toP;
4088 shorts_this_frag = 0;
4089 for (m = wid / 2; m; --m)
4090 {
4091 md_number_to_chars (toP, (long) (*fromP), 2);
4092 toP += 2;
4093 fromP++;
4094 shorts_this_frag++;
4095 }
4096 for (m = 0; m < the_ins.nrel; m++)
4097 {
4098 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4099 {
4100 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4101 break;
4102 }
4103 wid = the_ins.reloc[m].wid;
4104 if (wid == 0)
4105 continue;
4106 the_ins.reloc[m].wid = 0;
4107 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4108
4109 fixP = fix_new_exp (frag_now,
4110 ((toP - frag_now->fr_literal)
4111 - the_ins.numo * 2 + the_ins.reloc[m].n),
4112 wid,
4113 &the_ins.reloc[m].exp,
4114 the_ins.reloc[m].pcrel,
4115 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4116 the_ins.reloc[m].pic_reloc));
4117 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4118 }
4119 (void) frag_var (rs_machine_dependent, 10, 0,
4120 (relax_substateT) (the_ins.fragb[n].fragty),
4121 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4122 }
4123 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4124 shorts_this_frag = 0;
4125 if (n)
4126 {
4127 toP = frag_more (n * 2);
4128 while (n--)
4129 {
4130 md_number_to_chars (toP, (long) (*fromP), 2);
4131 toP += 2;
4132 fromP++;
4133 shorts_this_frag++;
4134 }
4135 }
4136 for (m = 0; m < the_ins.nrel; m++)
4137 {
4138 int wid;
4139
4140 wid = the_ins.reloc[m].wid;
4141 if (wid == 0)
4142 continue;
4143 the_ins.reloc[m].wid = 0;
4144 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4145
4146 fixP = fix_new_exp (frag_now,
4147 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4148 - shorts_this_frag * 2),
4149 wid,
4150 &the_ins.reloc[m].exp,
4151 the_ins.reloc[m].pcrel,
4152 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4153 the_ins.reloc[m].pic_reloc));
4154 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4155 }
4156 }
4157
4158 /* Comparison function used by qsort to rank the opcode entries by name. */
4159
4160 static int
4161 m68k_compare_opcode (const void * v1, const void * v2)
4162 {
4163 struct m68k_opcode * op1, * op2;
4164 int ret;
4165
4166 if (v1 == v2)
4167 return 0;
4168
4169 op1 = *(struct m68k_opcode **) v1;
4170 op2 = *(struct m68k_opcode **) v2;
4171
4172 /* Compare the two names. If different, return the comparison.
4173 If the same, return the order they are in the opcode table. */
4174 ret = strcmp (op1->name, op2->name);
4175 if (ret)
4176 return ret;
4177 if (op1 < op2)
4178 return -1;
4179 return 1;
4180 }
4181
4182 void
4183 md_begin (void)
4184 {
4185 const struct m68k_opcode *ins;
4186 struct m68k_incant *hack, *slak;
4187 const char *retval = 0; /* Empty string, or error msg text. */
4188 int i;
4189
4190 /* Set up hash tables with 68000 instructions.
4191 similar to what the vax assembler does. */
4192 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4193 a copy of it at runtime, adding in the information we want but isn't
4194 there. I think it'd be better to have an awk script hack the table
4195 at compile time. Or even just xstr the table and use it as-is. But
4196 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4197 names. */
4198
4199 if (flag_mri)
4200 {
4201 flag_reg_prefix_optional = 1;
4202 m68k_abspcadd = 1;
4203 if (! m68k_rel32_from_cmdline)
4204 m68k_rel32 = 0;
4205 }
4206
4207 /* First sort the opcode table into alphabetical order to seperate
4208 the order that the assembler wants to see the opcodes from the
4209 order that the disassembler wants to see them. */
4210 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4211 if (!m68k_sorted_opcodes)
4212 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4213 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
4214
4215 for (i = m68k_numopcodes; i--;)
4216 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4217
4218 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4219 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4220
4221 op_hash = hash_new ();
4222
4223 obstack_begin (&robyn, 4000);
4224 for (i = 0; i < m68k_numopcodes; i++)
4225 {
4226 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4227 do
4228 {
4229 ins = m68k_sorted_opcodes[i];
4230
4231 /* We *could* ignore insns that don't match our
4232 arch here by just leaving them out of the hash. */
4233 slak->m_operands = ins->args;
4234 slak->m_opnum = strlen (slak->m_operands) / 2;
4235 slak->m_arch = ins->arch;
4236 slak->m_opcode = ins->opcode;
4237 /* This is kludgey. */
4238 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4239 if (i + 1 != m68k_numopcodes
4240 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4241 {
4242 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4243 i++;
4244 }
4245 else
4246 slak->m_next = 0;
4247 slak = slak->m_next;
4248 }
4249 while (slak);
4250
4251 retval = hash_insert (op_hash, ins->name, (char *) hack);
4252 if (retval)
4253 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4254 }
4255
4256 for (i = 0; i < m68k_numaliases; i++)
4257 {
4258 const char *name = m68k_opcode_aliases[i].primary;
4259 const char *alias = m68k_opcode_aliases[i].alias;
4260 PTR val = hash_find (op_hash, name);
4261
4262 if (!val)
4263 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4264 retval = hash_insert (op_hash, alias, val);
4265 if (retval)
4266 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4267 }
4268
4269 /* In MRI mode, all unsized branches are variable sized. Normally,
4270 they are word sized. */
4271 if (flag_mri)
4272 {
4273 static struct m68k_opcode_alias mri_aliases[] =
4274 {
4275 { "bhi", "jhi", },
4276 { "bls", "jls", },
4277 { "bcc", "jcc", },
4278 { "bcs", "jcs", },
4279 { "bne", "jne", },
4280 { "beq", "jeq", },
4281 { "bvc", "jvc", },
4282 { "bvs", "jvs", },
4283 { "bpl", "jpl", },
4284 { "bmi", "jmi", },
4285 { "bge", "jge", },
4286 { "blt", "jlt", },
4287 { "bgt", "jgt", },
4288 { "ble", "jle", },
4289 { "bra", "jra", },
4290 { "bsr", "jbsr", },
4291 };
4292
4293 for (i = 0;
4294 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4295 i++)
4296 {
4297 const char *name = mri_aliases[i].primary;
4298 const char *alias = mri_aliases[i].alias;
4299 PTR val = hash_find (op_hash, name);
4300
4301 if (!val)
4302 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4303 retval = hash_jam (op_hash, alias, val);
4304 if (retval)
4305 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4306 }
4307 }
4308
4309 for (i = 0; i < (int) sizeof (notend_table); i++)
4310 {
4311 notend_table[i] = 0;
4312 alt_notend_table[i] = 0;
4313 }
4314
4315 notend_table[','] = 1;
4316 notend_table['{'] = 1;
4317 notend_table['}'] = 1;
4318 alt_notend_table['a'] = 1;
4319 alt_notend_table['A'] = 1;
4320 alt_notend_table['d'] = 1;
4321 alt_notend_table['D'] = 1;
4322 alt_notend_table['#'] = 1;
4323 alt_notend_table['&'] = 1;
4324 alt_notend_table['f'] = 1;
4325 alt_notend_table['F'] = 1;
4326 #ifdef REGISTER_PREFIX
4327 alt_notend_table[REGISTER_PREFIX] = 1;
4328 #endif
4329
4330 /* We need to put '(' in alt_notend_table to handle
4331 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4332 alt_notend_table['('] = 1;
4333
4334 /* We need to put '@' in alt_notend_table to handle
4335 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4336 alt_notend_table['@'] = 1;
4337
4338 /* We need to put digits in alt_notend_table to handle
4339 bfextu %d0{24:1},%d0 */
4340 alt_notend_table['0'] = 1;
4341 alt_notend_table['1'] = 1;
4342 alt_notend_table['2'] = 1;
4343 alt_notend_table['3'] = 1;
4344 alt_notend_table['4'] = 1;
4345 alt_notend_table['5'] = 1;
4346 alt_notend_table['6'] = 1;
4347 alt_notend_table['7'] = 1;
4348 alt_notend_table['8'] = 1;
4349 alt_notend_table['9'] = 1;
4350
4351 #ifndef MIT_SYNTAX_ONLY
4352 /* Insert pseudo ops, these have to go into the opcode table since
4353 gas expects pseudo ops to start with a dot. */
4354 {
4355 int n = 0;
4356
4357 while (mote_pseudo_table[n].poc_name)
4358 {
4359 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4360 hash_insert (op_hash,
4361 mote_pseudo_table[n].poc_name, (char *) hack);
4362 hack->m_operands = 0;
4363 hack->m_opnum = n;
4364 n++;
4365 }
4366 }
4367 #endif
4368
4369 init_regtable ();
4370
4371 #ifdef OBJ_ELF
4372 record_alignment (text_section, 2);
4373 record_alignment (data_section, 2);
4374 record_alignment (bss_section, 2);
4375 #endif
4376 }
4377
4378 static void
4379 select_control_regs (void)
4380 {
4381 /* Note which set of "movec" control registers is available. */
4382 switch (current_chip)
4383 {
4384 case 0:
4385 if (verbose)
4386 as_warn (_("architecture not yet selected: defaulting to 68020"));
4387 control_regs = m68020_control_regs;
4388 break;
4389
4390 case cpu_m68000:
4391 control_regs = m68000_control_regs;
4392 break;
4393 case cpu_m68010:
4394 control_regs = m68010_control_regs;
4395 break;
4396 case cpu_m68020:
4397 case cpu_m68030:
4398 control_regs = m68020_control_regs;
4399 break;
4400 case cpu_m68040:
4401 control_regs = m68040_control_regs;
4402 break;
4403 case cpu_m68060:
4404 control_regs = m68060_control_regs;
4405 break;
4406 case cpu_cpu32:
4407 control_regs = cpu32_control_regs;
4408 break;
4409 case cpu_cf5200:
4410 case cpu_cf5206e:
4411 case cpu_cf5307:
4412 case cpu_cf5407:
4413 control_regs = mcf_control_regs;
4414 break;
4415 case cpu_cf5249:
4416 control_regs = mcf5249_control_regs;
4417 break;
4418 case cpu_cf528x:
4419 case cpu_cf521x:
4420 control_regs = mcf528x_control_regs;
4421 break;
4422 case cpu_cf547x:
4423 case cpu_cf548x:
4424 control_regs = mcfv4e_control_regs;
4425 break;
4426 case cpu_cf5208:
4427 control_regs = mcf5208_control_regs;
4428 break;
4429 case cpu_cf5213:
4430 control_regs = mcf5213_control_regs;
4431 break;
4432 case cpu_cf5329:
4433 control_regs = mcf5329_control_regs;
4434 break;
4435 default:
4436 abort ();
4437 }
4438 }
4439
4440 \f
4441 /* This is called when a label is defined. */
4442
4443 void
4444 m68k_frob_label (symbolS *sym)
4445 {
4446 struct label_line *n;
4447
4448 n = (struct label_line *) xmalloc (sizeof *n);
4449 n->next = labels;
4450 n->label = sym;
4451 as_where (&n->file, &n->line);
4452 n->text = 0;
4453 labels = n;
4454 current_label = n;
4455
4456 #ifdef OBJ_ELF
4457 dwarf2_emit_label (sym);
4458 #endif
4459 }
4460
4461 /* This is called when a value that is not an instruction is emitted. */
4462
4463 void
4464 m68k_flush_pending_output (void)
4465 {
4466 current_label = NULL;
4467 }
4468
4469 /* This is called at the end of the assembly, when the final value of
4470 the label is known. We warn if this is a text symbol aligned at an
4471 odd location. */
4472
4473 void
4474 m68k_frob_symbol (symbolS *sym)
4475 {
4476 if (S_GET_SEGMENT (sym) == reg_section
4477 && (int) S_GET_VALUE (sym) < 0)
4478 {
4479 S_SET_SEGMENT (sym, absolute_section);
4480 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4481 }
4482 else if ((S_GET_VALUE (sym) & 1) != 0)
4483 {
4484 struct label_line *l;
4485
4486 for (l = labels; l != NULL; l = l->next)
4487 {
4488 if (l->label == sym)
4489 {
4490 if (l->text)
4491 as_warn_where (l->file, l->line,
4492 _("text label `%s' aligned to odd boundary"),
4493 S_GET_NAME (sym));
4494 break;
4495 }
4496 }
4497 }
4498 }
4499 \f
4500 /* This is called if we go in or out of MRI mode because of the .mri
4501 pseudo-op. */
4502
4503 void
4504 m68k_mri_mode_change (int on)
4505 {
4506 if (on)
4507 {
4508 if (! flag_reg_prefix_optional)
4509 {
4510 flag_reg_prefix_optional = 1;
4511 #ifdef REGISTER_PREFIX
4512 init_regtable ();
4513 #endif
4514 }
4515 m68k_abspcadd = 1;
4516 if (! m68k_rel32_from_cmdline)
4517 m68k_rel32 = 0;
4518 }
4519 else
4520 {
4521 if (! reg_prefix_optional_seen)
4522 {
4523 #ifdef REGISTER_PREFIX_OPTIONAL
4524 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4525 #else
4526 flag_reg_prefix_optional = 0;
4527 #endif
4528 #ifdef REGISTER_PREFIX
4529 init_regtable ();
4530 #endif
4531 }
4532 m68k_abspcadd = 0;
4533 if (! m68k_rel32_from_cmdline)
4534 m68k_rel32 = 1;
4535 }
4536 }
4537
4538 /* Equal to MAX_PRECISION in atof-ieee.c. */
4539 #define MAX_LITTLENUMS 6
4540
4541 /* Turn a string in input_line_pointer into a floating point constant
4542 of type TYPE, and store the appropriate bytes in *LITP. The number
4543 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4544 returned, or NULL on OK. */
4545
4546 char *
4547 md_atof (int type, char *litP, int *sizeP)
4548 {
4549 int prec;
4550 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4551 LITTLENUM_TYPE *wordP;
4552 char *t;
4553
4554 switch (type)
4555 {
4556 case 'f':
4557 case 'F':
4558 case 's':
4559 case 'S':
4560 prec = 2;
4561 break;
4562
4563 case 'd':
4564 case 'D':
4565 case 'r':
4566 case 'R':
4567 prec = 4;
4568 break;
4569
4570 case 'x':
4571 case 'X':
4572 prec = 6;
4573 break;
4574
4575 case 'p':
4576 case 'P':
4577 prec = 6;
4578 break;
4579
4580 default:
4581 *sizeP = 0;
4582 return _("Bad call to MD_ATOF()");
4583 }
4584 t = atof_ieee (input_line_pointer, type, words);
4585 if (t)
4586 input_line_pointer = t;
4587
4588 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4589 for (wordP = words; prec--;)
4590 {
4591 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4592 litP += sizeof (LITTLENUM_TYPE);
4593 }
4594 return 0;
4595 }
4596
4597 void
4598 md_number_to_chars (char *buf, valueT val, int n)
4599 {
4600 number_to_chars_bigendian (buf, val, n);
4601 }
4602
4603 void
4604 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4605 {
4606 offsetT val = *valP;
4607 addressT upper_limit;
4608 offsetT lower_limit;
4609
4610 /* This is unnecessary but it convinces the native rs6000 compiler
4611 to generate the code we want. */
4612 char *buf = fixP->fx_frag->fr_literal;
4613 buf += fixP->fx_where;
4614 /* End ibm compiler workaround. */
4615
4616 val = SEXT (val);
4617
4618 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4619 fixP->fx_done = 1;
4620
4621 #ifdef OBJ_ELF
4622 if (fixP->fx_addsy)
4623 {
4624 memset (buf, 0, fixP->fx_size);
4625 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4626
4627 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4628 && !S_IS_DEFINED (fixP->fx_addsy)
4629 && !S_IS_WEAK (fixP->fx_addsy))
4630 S_SET_WEAK (fixP->fx_addsy);
4631 return;
4632 }
4633 #endif
4634
4635 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4636 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4637 return;
4638
4639 switch (fixP->fx_size)
4640 {
4641 /* The cast to offsetT below are necessary to make code
4642 correct for machines where ints are smaller than offsetT. */
4643 case 1:
4644 *buf++ = val;
4645 upper_limit = 0x7f;
4646 lower_limit = - (offsetT) 0x80;
4647 break;
4648 case 2:
4649 *buf++ = (val >> 8);
4650 *buf++ = val;
4651 upper_limit = 0x7fff;
4652 lower_limit = - (offsetT) 0x8000;
4653 break;
4654 case 4:
4655 *buf++ = (val >> 24);
4656 *buf++ = (val >> 16);
4657 *buf++ = (val >> 8);
4658 *buf++ = val;
4659 upper_limit = 0x7fffffff;
4660 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4661 break;
4662 default:
4663 BAD_CASE (fixP->fx_size);
4664 }
4665
4666 /* Fix up a negative reloc. */
4667 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4668 {
4669 fixP->fx_addsy = fixP->fx_subsy;
4670 fixP->fx_subsy = NULL;
4671 fixP->fx_tcbit = 1;
4672 }
4673
4674 /* For non-pc-relative values, it's conceivable we might get something
4675 like "0xff" for a byte field. So extend the upper part of the range
4676 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4677 so that we can do any range checking at all. */
4678 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4679 upper_limit = upper_limit * 2 + 1;
4680
4681 if ((addressT) val > upper_limit
4682 && (val > 0 || val < lower_limit))
4683 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4684
4685 /* A one byte PC-relative reloc means a short branch. We can't use
4686 a short branch with a value of 0 or -1, because those indicate
4687 different opcodes (branches with longer offsets). fixup_segment
4688 in write.c may have clobbered fx_pcrel, so we need to examine the
4689 reloc type. */
4690 if ((fixP->fx_pcrel
4691 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4692 && fixP->fx_size == 1
4693 && (fixP->fx_addsy == NULL
4694 || S_IS_DEFINED (fixP->fx_addsy))
4695 && (val == 0 || val == -1))
4696 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4697 }
4698
4699 /* *fragP has been relaxed to its final size, and now needs to have
4700 the bytes inside it modified to conform to the new size There is UGLY
4701 MAGIC here. ..
4702 */
4703 static void
4704 md_convert_frag_1 (fragS *fragP)
4705 {
4706 long disp;
4707 fixS *fixP;
4708
4709 /* Address in object code of the displacement. */
4710 register int object_address = fragP->fr_fix + fragP->fr_address;
4711
4712 /* Address in gas core of the place to store the displacement. */
4713 /* This convinces the native rs6000 compiler to generate the code we
4714 want. */
4715 register char *buffer_address = fragP->fr_literal;
4716 buffer_address += fragP->fr_fix;
4717 /* End ibm compiler workaround. */
4718
4719 /* The displacement of the address, from current location. */
4720 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4721 disp = (disp + fragP->fr_offset) - object_address;
4722
4723 switch (fragP->fr_subtype)
4724 {
4725 case TAB (BRANCHBWL, BYTE):
4726 case TAB (BRABSJUNC, BYTE):
4727 case TAB (BRABSJCOND, BYTE):
4728 case TAB (BRANCHBW, BYTE):
4729 know (issbyte (disp));
4730 if (disp == 0)
4731 as_bad_where (fragP->fr_file, fragP->fr_line,
4732 _("short branch with zero offset: use :w"));
4733 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4734 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4735 fixP->fx_pcrel_adjust = -1;
4736 break;
4737 case TAB (BRANCHBWL, SHORT):
4738 case TAB (BRABSJUNC, SHORT):
4739 case TAB (BRABSJCOND, SHORT):
4740 case TAB (BRANCHBW, SHORT):
4741 fragP->fr_opcode[1] = 0x00;
4742 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4743 1, RELAX_RELOC_PC16);
4744 fragP->fr_fix += 2;
4745 break;
4746 case TAB (BRANCHBWL, LONG):
4747 fragP->fr_opcode[1] = (char) 0xFF;
4748 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4749 1, RELAX_RELOC_PC32);
4750 fragP->fr_fix += 4;
4751 break;
4752 case TAB (BRABSJUNC, LONG):
4753 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4754 {
4755 if (flag_keep_pcrel)
4756 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
4757 fragP->fr_opcode[0] = 0x4E;
4758 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4759 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4760 0, RELAX_RELOC_ABS32);
4761 fragP->fr_fix += 4;
4762 }
4763 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4764 {
4765 if (flag_keep_pcrel)
4766 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
4767 fragP->fr_opcode[0] = 0x4E;
4768 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4769 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4770 0, RELAX_RELOC_ABS32);
4771 fragP->fr_fix += 4;
4772 }
4773 else
4774 {
4775 /* This cannot happen, because jbsr and jbra are the only two
4776 unconditional branches. */
4777 abort ();
4778 }
4779 break;
4780 case TAB (BRABSJCOND, LONG):
4781 if (flag_keep_pcrel)
4782 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4783
4784 /* Only Bcc 68000 instructions can come here
4785 Change bcc into b!cc/jmp absl long. */
4786 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4787 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
4788
4789 /* JF: these used to be fr_opcode[2,3], but they may be in a
4790 different frag, in which case referring to them is a no-no.
4791 Only fr_opcode[0,1] are guaranteed to work. */
4792 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4793 *buffer_address++ = (char) 0xf9;
4794 fragP->fr_fix += 2; /* Account for jmp instruction. */
4795 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4796 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4797 fragP->fr_fix += 4;
4798 break;
4799 case TAB (FBRANCH, SHORT):
4800 know ((fragP->fr_opcode[1] & 0x40) == 0);
4801 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4802 1, RELAX_RELOC_PC16);
4803 fragP->fr_fix += 2;
4804 break;
4805 case TAB (FBRANCH, LONG):
4806 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
4807 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4808 1, RELAX_RELOC_PC32);
4809 fragP->fr_fix += 4;
4810 break;
4811 case TAB (DBCCLBR, SHORT):
4812 case TAB (DBCCABSJ, SHORT):
4813 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4814 1, RELAX_RELOC_PC16);
4815 fragP->fr_fix += 2;
4816 break;
4817 case TAB (DBCCLBR, LONG):
4818 /* Only DBcc instructions can come here.
4819 Change dbcc into dbcc/bral.
4820 JF: these used to be fr_opcode[2-7], but that's wrong. */
4821 if (flag_keep_pcrel)
4822 as_fatal (_("Tried to convert DBcc to absolute jump"));
4823
4824 *buffer_address++ = 0x00; /* Branch offset = 4. */
4825 *buffer_address++ = 0x04;
4826 *buffer_address++ = 0x60; /* Put in bra pc+6. */
4827 *buffer_address++ = 0x06;
4828 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4829 *buffer_address++ = (char) 0xff;
4830
4831 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4832 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
4833 RELAX_RELOC_PC32);
4834 fragP->fr_fix += 4;
4835 break;
4836 case TAB (DBCCABSJ, LONG):
4837 /* Only DBcc instructions can come here.
4838 Change dbcc into dbcc/jmp.
4839 JF: these used to be fr_opcode[2-7], but that's wrong. */
4840 if (flag_keep_pcrel)
4841 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4842
4843 *buffer_address++ = 0x00; /* Branch offset = 4. */
4844 *buffer_address++ = 0x04;
4845 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
4846 *buffer_address++ = 0x06;
4847 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4848 *buffer_address++ = (char) 0xf9;
4849
4850 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4851 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
4852 RELAX_RELOC_ABS32);
4853 fragP->fr_fix += 4;
4854 break;
4855 case TAB (PCREL1632, SHORT):
4856 fragP->fr_opcode[1] &= ~0x3F;
4857 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4858 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4859 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4860 fragP->fr_fix += 2;
4861 break;
4862 case TAB (PCREL1632, LONG):
4863 /* Already set to mode 7.3; this indicates: PC indirect with
4864 suppressed index, 32-bit displacement. */
4865 *buffer_address++ = 0x01;
4866 *buffer_address++ = 0x70;
4867 fragP->fr_fix += 2;
4868 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4869 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4870 fixP->fx_pcrel_adjust = 2;
4871 fragP->fr_fix += 4;
4872 break;
4873 case TAB (PCINDEX, BYTE):
4874 assert (fragP->fr_fix >= 2);
4875 buffer_address[-2] &= ~1;
4876 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4877 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4878 fixP->fx_pcrel_adjust = 1;
4879 break;
4880 case TAB (PCINDEX, SHORT):
4881 assert (fragP->fr_fix >= 2);
4882 buffer_address[-2] |= 0x1;
4883 buffer_address[-1] = 0x20;
4884 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4885 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4886 fixP->fx_pcrel_adjust = 2;
4887 fragP->fr_fix += 2;
4888 break;
4889 case TAB (PCINDEX, LONG):
4890 assert (fragP->fr_fix >= 2);
4891 buffer_address[-2] |= 0x1;
4892 buffer_address[-1] = 0x30;
4893 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4894 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4895 fixP->fx_pcrel_adjust = 2;
4896 fragP->fr_fix += 4;
4897 break;
4898 case TAB (ABSTOPCREL, SHORT):
4899 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4900 1, RELAX_RELOC_PC16);
4901 fragP->fr_fix += 2;
4902 break;
4903 case TAB (ABSTOPCREL, LONG):
4904 if (flag_keep_pcrel)
4905 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4906 /* The thing to do here is force it to ABSOLUTE LONG, since
4907 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
4908 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4909 abort ();
4910 fragP->fr_opcode[1] &= ~0x3F;
4911 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4912 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4913 0, RELAX_RELOC_ABS32);
4914 fragP->fr_fix += 4;
4915 break;
4916 }
4917 }
4918
4919 void
4920 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
4921 segT sec ATTRIBUTE_UNUSED,
4922 fragS *fragP)
4923 {
4924 md_convert_frag_1 (fragP);
4925 }
4926
4927 /* Force truly undefined symbols to their maximum size, and generally set up
4928 the frag list to be relaxed
4929 */
4930 int
4931 md_estimate_size_before_relax (fragS *fragP, segT segment)
4932 {
4933 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4934 switch (fragP->fr_subtype)
4935 {
4936 case TAB (BRANCHBWL, SZ_UNDEF):
4937 case TAB (BRABSJUNC, SZ_UNDEF):
4938 case TAB (BRABSJCOND, SZ_UNDEF):
4939 {
4940 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4941 && relaxable_symbol (fragP->fr_symbol))
4942 {
4943 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4944 }
4945 else if (flag_short_refs)
4946 {
4947 /* Symbol is undefined and we want short ref. */
4948 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4949 }
4950 else
4951 {
4952 /* Symbol is still undefined. Make it LONG. */
4953 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4954 }
4955 break;
4956 }
4957
4958 case TAB (BRANCHBW, SZ_UNDEF):
4959 {
4960 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4961 && relaxable_symbol (fragP->fr_symbol))
4962 {
4963 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4964 }
4965 else
4966 {
4967 /* Symbol is undefined and we don't have long branches. */
4968 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4969 }
4970 break;
4971 }
4972
4973 case TAB (FBRANCH, SZ_UNDEF):
4974 case TAB (DBCCLBR, SZ_UNDEF):
4975 case TAB (DBCCABSJ, SZ_UNDEF):
4976 case TAB (PCREL1632, SZ_UNDEF):
4977 {
4978 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4979 && relaxable_symbol (fragP->fr_symbol))
4980 || flag_short_refs)
4981 {
4982 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4983 }
4984 else
4985 {
4986 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4987 }
4988 break;
4989 }
4990
4991 case TAB (PCINDEX, SZ_UNDEF):
4992 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4993 && relaxable_symbol (fragP->fr_symbol)))
4994 {
4995 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4996 }
4997 else
4998 {
4999 fragP->fr_subtype = TAB (PCINDEX, LONG);
5000 }
5001 break;
5002
5003 case TAB (ABSTOPCREL, SZ_UNDEF):
5004 {
5005 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5006 && relaxable_symbol (fragP->fr_symbol)))
5007 {
5008 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5009 }
5010 else
5011 {
5012 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5013 }
5014 break;
5015 }
5016
5017 default:
5018 break;
5019 }
5020
5021 /* Now that SZ_UNDEF are taken care of, check others. */
5022 switch (fragP->fr_subtype)
5023 {
5024 case TAB (BRANCHBWL, BYTE):
5025 case TAB (BRABSJUNC, BYTE):
5026 case TAB (BRABSJCOND, BYTE):
5027 case TAB (BRANCHBW, BYTE):
5028 /* We can't do a short jump to the next instruction, so in that
5029 case we force word mode. If the symbol is at the start of a
5030 frag, and it is the next frag with any data in it (usually
5031 this is just the next frag, but assembler listings may
5032 introduce empty frags), we must use word mode. */
5033 if (fragP->fr_symbol)
5034 {
5035 fragS *sym_frag;
5036
5037 sym_frag = symbol_get_frag (fragP->fr_symbol);
5038 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5039 {
5040 fragS *l;
5041
5042 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5043 if (l->fr_fix != 0)
5044 break;
5045 if (l == sym_frag)
5046 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5047 }
5048 }
5049 break;
5050 default:
5051 break;
5052 }
5053 return md_relax_table[fragP->fr_subtype].rlx_length;
5054 }
5055
5056 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5057 /* the bit-field entries in the relocation_info struct plays hell
5058 with the byte-order problems of cross-assembly. So as a hack,
5059 I added this mach. dependent ri twiddler. Ugly, but it gets
5060 you there. -KWK */
5061 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5062 are symbolnum, most sig. byte first. Last byte is broken up with
5063 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5064 nibble as nuthin. (on Sun 3 at least) */
5065 /* Translate the internal relocation information into target-specific
5066 format. */
5067 #ifdef comment
5068 void
5069 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
5070 {
5071 /* This is easy. */
5072 md_number_to_chars (the_bytes, ri->r_address, 4);
5073 /* Now the fun stuff. */
5074 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5075 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5076 the_bytes[6] = ri->r_symbolnum & 0x0ff;
5077 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5078 | ((ri->r_length << 5) & 0x60)
5079 | ((ri->r_extern << 4) & 0x10));
5080 }
5081
5082 #endif
5083
5084 #endif /* OBJ_AOUT or OBJ_BOUT */
5085
5086 #ifndef WORKING_DOT_WORD
5087 int md_short_jump_size = 4;
5088 int md_long_jump_size = 6;
5089
5090 void
5091 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5092 fragS *frag ATTRIBUTE_UNUSED,
5093 symbolS *to_symbol ATTRIBUTE_UNUSED)
5094 {
5095 valueT offset;
5096
5097 offset = to_addr - (from_addr + 2);
5098
5099 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5100 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5101 }
5102
5103 void
5104 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5105 fragS *frag, symbolS *to_symbol)
5106 {
5107 valueT offset;
5108
5109 if (!HAVE_LONG_BRANCH (current_architecture))
5110 {
5111 if (flag_keep_pcrel)
5112 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5113 offset = to_addr - S_GET_VALUE (to_symbol);
5114 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5115 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5116 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5117 0, NO_RELOC);
5118 }
5119 else
5120 {
5121 offset = to_addr - (from_addr + 2);
5122 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5123 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5124 }
5125 }
5126
5127 #endif
5128
5129 /* Different values of OK tell what its OK to return. Things that
5130 aren't OK are an error (what a shock, no?)
5131
5132 0: Everything is OK
5133 10: Absolute 1:8 only
5134 20: Absolute 0:7 only
5135 30: absolute 0:15 only
5136 40: Absolute 0:31 only
5137 50: absolute 0:127 only
5138 55: absolute -64:63 only
5139 60: absolute -128:127 only
5140 70: absolute 0:4095 only
5141 80: absolute -1, 1:7 only
5142 90: No bignums. */
5143
5144 static int
5145 get_num (struct m68k_exp *exp, int ok)
5146 {
5147 if (exp->exp.X_op == O_absent)
5148 {
5149 /* Do the same thing the VAX asm does. */
5150 op (exp) = O_constant;
5151 adds (exp) = 0;
5152 subs (exp) = 0;
5153 offs (exp) = 0;
5154 if (ok == 10)
5155 {
5156 as_warn (_("expression out of range: defaulting to 1"));
5157 offs (exp) = 1;
5158 }
5159 }
5160 else if (exp->exp.X_op == O_constant)
5161 {
5162 switch (ok)
5163 {
5164 case 10:
5165 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5166 {
5167 as_warn (_("expression out of range: defaulting to 1"));
5168 offs (exp) = 1;
5169 }
5170 break;
5171 case 20:
5172 if ((valueT) TRUNC (offs (exp)) > 7)
5173 goto outrange;
5174 break;
5175 case 30:
5176 if ((valueT) TRUNC (offs (exp)) > 15)
5177 goto outrange;
5178 break;
5179 case 40:
5180 if ((valueT) TRUNC (offs (exp)) > 32)
5181 goto outrange;
5182 break;
5183 case 50:
5184 if ((valueT) TRUNC (offs (exp)) > 127)
5185 goto outrange;
5186 break;
5187 case 55:
5188 if ((valueT) SEXT (offs (exp)) + 64 > 127)
5189 goto outrange;
5190 break;
5191 case 60:
5192 if ((valueT) SEXT (offs (exp)) + 128 > 255)
5193 goto outrange;
5194 break;
5195 case 70:
5196 if ((valueT) TRUNC (offs (exp)) > 4095)
5197 {
5198 outrange:
5199 as_warn (_("expression out of range: defaulting to 0"));
5200 offs (exp) = 0;
5201 }
5202 break;
5203 case 80:
5204 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5205 && (valueT) TRUNC (offs (exp)) - 1 > 6)
5206 {
5207 as_warn (_("expression out of range: defaulting to 1"));
5208 offs (exp) = 1;
5209 }
5210 break;
5211 default:
5212 break;
5213 }
5214 }
5215 else if (exp->exp.X_op == O_big)
5216 {
5217 if (offs (exp) <= 0 /* flonum. */
5218 && (ok == 90 /* no bignums */
5219 || (ok > 10 /* Small-int ranges including 0 ok. */
5220 /* If we have a flonum zero, a zero integer should
5221 do as well (e.g., in moveq). */
5222 && generic_floating_point_number.exponent == 0
5223 && generic_floating_point_number.low[0] == 0)))
5224 {
5225 /* HACK! Turn it into a long. */
5226 LITTLENUM_TYPE words[6];
5227
5228 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5229 op (exp) = O_constant;
5230 adds (exp) = 0;
5231 subs (exp) = 0;
5232 offs (exp) = words[1] | (words[0] << 16);
5233 }
5234 else if (ok != 0)
5235 {
5236 op (exp) = O_constant;
5237 adds (exp) = 0;
5238 subs (exp) = 0;
5239 offs (exp) = (ok == 10) ? 1 : 0;
5240 as_warn (_("Can't deal with expression; defaulting to %ld"),
5241 (long) offs (exp));
5242 }
5243 }
5244 else
5245 {
5246 if (ok >= 10 && ok <= 80)
5247 {
5248 op (exp) = O_constant;
5249 adds (exp) = 0;
5250 subs (exp) = 0;
5251 offs (exp) = (ok == 10) ? 1 : 0;
5252 as_warn (_("Can't deal with expression; defaulting to %ld"),
5253 (long) offs (exp));
5254 }
5255 }
5256
5257 if (exp->size != SIZE_UNSPEC)
5258 {
5259 switch (exp->size)
5260 {
5261 case SIZE_UNSPEC:
5262 case SIZE_LONG:
5263 break;
5264 case SIZE_BYTE:
5265 if (!isbyte (offs (exp)))
5266 as_warn (_("expression doesn't fit in BYTE"));
5267 break;
5268 case SIZE_WORD:
5269 if (!isword (offs (exp)))
5270 as_warn (_("expression doesn't fit in WORD"));
5271 break;
5272 }
5273 }
5274
5275 return offs (exp);
5276 }
5277
5278 /* These are the back-ends for the various machine dependent pseudo-ops. */
5279
5280 static void
5281 s_data1 (int ignore ATTRIBUTE_UNUSED)
5282 {
5283 subseg_set (data_section, 1);
5284 demand_empty_rest_of_line ();
5285 }
5286
5287 static void
5288 s_data2 (int ignore ATTRIBUTE_UNUSED)
5289 {
5290 subseg_set (data_section, 2);
5291 demand_empty_rest_of_line ();
5292 }
5293
5294 static void
5295 s_bss (int ignore ATTRIBUTE_UNUSED)
5296 {
5297 /* We don't support putting frags in the BSS segment, we fake it
5298 by marking in_bss, then looking at s_skip for clues. */
5299
5300 subseg_set (bss_section, 0);
5301 demand_empty_rest_of_line ();
5302 }
5303
5304 static void
5305 s_even (int ignore ATTRIBUTE_UNUSED)
5306 {
5307 register int temp;
5308 register long temp_fill;
5309
5310 temp = 1; /* JF should be 2? */
5311 temp_fill = get_absolute_expression ();
5312 if (!need_pass_2) /* Never make frag if expect extra pass. */
5313 frag_align (temp, (int) temp_fill, 0);
5314 demand_empty_rest_of_line ();
5315 record_alignment (now_seg, temp);
5316 }
5317
5318 static void
5319 s_proc (int ignore ATTRIBUTE_UNUSED)
5320 {
5321 demand_empty_rest_of_line ();
5322 }
5323 \f
5324 /* Pseudo-ops handled for MRI compatibility. */
5325
5326 /* This function returns non-zero if the argument is a conditional
5327 pseudo-op. This is called when checking whether a pending
5328 alignment is needed. */
5329
5330 int
5331 m68k_conditional_pseudoop (pseudo_typeS *pop)
5332 {
5333 return (pop->poc_handler == s_mri_if
5334 || pop->poc_handler == s_mri_else);
5335 }
5336
5337 /* Handle an MRI style chip specification. */
5338
5339 static void
5340 mri_chip (void)
5341 {
5342 char *s;
5343 char c;
5344 int i;
5345
5346 s = input_line_pointer;
5347 /* We can't use get_symbol_end since the processor names are not proper
5348 symbols. */
5349 while (is_part_of_name (c = *input_line_pointer++))
5350 ;
5351 *--input_line_pointer = 0;
5352 for (i = 0; m68k_cpus[i].name; i++)
5353 if (strcasecmp (s, m68k_cpus[i].name) == 0)
5354 break;
5355 if (!m68k_cpus[i].name)
5356 {
5357 as_bad (_("%s: unrecognized processor name"), s);
5358 *input_line_pointer = c;
5359 ignore_rest_of_line ();
5360 return;
5361 }
5362 *input_line_pointer = c;
5363
5364 if (*input_line_pointer == '/')
5365 current_architecture = 0;
5366 else
5367 current_architecture &= m68881 | m68851;
5368 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5369 current_chip = m68k_cpus[i].chip;
5370
5371 while (*input_line_pointer == '/')
5372 {
5373 ++input_line_pointer;
5374 s = input_line_pointer;
5375 /* We can't use get_symbol_end since the processor names are not
5376 proper symbols. */
5377 while (is_part_of_name (c = *input_line_pointer++))
5378 ;
5379 *--input_line_pointer = 0;
5380 if (strcmp (s, "68881") == 0)
5381 current_architecture |= m68881;
5382 else if (strcmp (s, "68851") == 0)
5383 current_architecture |= m68851;
5384 *input_line_pointer = c;
5385 }
5386
5387 /* Update info about available control registers. */
5388 select_control_regs ();
5389 }
5390
5391 /* The MRI CHIP pseudo-op. */
5392
5393 static void
5394 s_chip (int ignore ATTRIBUTE_UNUSED)
5395 {
5396 char *stop = NULL;
5397 char stopc;
5398
5399 if (flag_mri)
5400 stop = mri_comment_field (&stopc);
5401 mri_chip ();
5402 if (flag_mri)
5403 mri_comment_end (stop, stopc);
5404 demand_empty_rest_of_line ();
5405 }
5406
5407 /* The MRI FOPT pseudo-op. */
5408
5409 static void
5410 s_fopt (int ignore ATTRIBUTE_UNUSED)
5411 {
5412 SKIP_WHITESPACE ();
5413
5414 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5415 {
5416 int temp;
5417
5418 input_line_pointer += 3;
5419 temp = get_absolute_expression ();
5420 if (temp < 0 || temp > 7)
5421 as_bad (_("bad coprocessor id"));
5422 else
5423 m68k_float_copnum = COP0 + temp;
5424 }
5425 else
5426 {
5427 as_bad (_("unrecognized fopt option"));
5428 ignore_rest_of_line ();
5429 return;
5430 }
5431
5432 demand_empty_rest_of_line ();
5433 }
5434
5435 /* The structure used to handle the MRI OPT pseudo-op. */
5436
5437 struct opt_action
5438 {
5439 /* The name of the option. */
5440 const char *name;
5441
5442 /* If this is not NULL, just call this function. The first argument
5443 is the ARG field of this structure, the second argument is
5444 whether the option was negated. */
5445 void (*pfn) (int arg, int on);
5446
5447 /* If this is not NULL, and the PFN field is NULL, set the variable
5448 this points to. Set it to the ARG field if the option was not
5449 negated, and the NOTARG field otherwise. */
5450 int *pvar;
5451
5452 /* The value to pass to PFN or to assign to *PVAR. */
5453 int arg;
5454
5455 /* The value to assign to *PVAR if the option is negated. If PFN is
5456 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5457 the option may not be negated. */
5458 int notarg;
5459 };
5460
5461 /* The table used to handle the MRI OPT pseudo-op. */
5462
5463 static void skip_to_comma (int, int);
5464 static void opt_nest (int, int);
5465 static void opt_chip (int, int);
5466 static void opt_list (int, int);
5467 static void opt_list_symbols (int, int);
5468
5469 static const struct opt_action opt_table[] =
5470 {
5471 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5472
5473 /* We do relaxing, so there is little use for these options. */
5474 { "b", 0, 0, 0, 0 },
5475 { "brs", 0, 0, 0, 0 },
5476 { "brb", 0, 0, 0, 0 },
5477 { "brl", 0, 0, 0, 0 },
5478 { "brw", 0, 0, 0, 0 },
5479
5480 { "c", 0, 0, 0, 0 },
5481 { "cex", 0, 0, 0, 0 },
5482 { "case", 0, &symbols_case_sensitive, 1, 0 },
5483 { "cl", 0, 0, 0, 0 },
5484 { "cre", 0, 0, 0, 0 },
5485 { "d", 0, &flag_keep_locals, 1, 0 },
5486 { "e", 0, 0, 0, 0 },
5487 { "f", 0, &flag_short_refs, 1, 0 },
5488 { "frs", 0, &flag_short_refs, 1, 0 },
5489 { "frl", 0, &flag_short_refs, 0, 1 },
5490 { "g", 0, 0, 0, 0 },
5491 { "i", 0, 0, 0, 0 },
5492 { "m", 0, 0, 0, 0 },
5493 { "mex", 0, 0, 0, 0 },
5494 { "mc", 0, 0, 0, 0 },
5495 { "md", 0, 0, 0, 0 },
5496 { "nest", opt_nest, 0, 0, 0 },
5497 { "next", skip_to_comma, 0, 0, 0 },
5498 { "o", 0, 0, 0, 0 },
5499 { "old", 0, 0, 0, 0 },
5500 { "op", skip_to_comma, 0, 0, 0 },
5501 { "pco", 0, 0, 0, 0 },
5502 { "p", opt_chip, 0, 0, 0 },
5503 { "pcr", 0, 0, 0, 0 },
5504 { "pcs", 0, 0, 0, 0 },
5505 { "r", 0, 0, 0, 0 },
5506 { "quick", 0, &m68k_quick, 1, 0 },
5507 { "rel32", 0, &m68k_rel32, 1, 0 },
5508 { "s", opt_list, 0, 0, 0 },
5509 { "t", opt_list_symbols, 0, 0, 0 },
5510 { "w", 0, &flag_no_warnings, 0, 1 },
5511 { "x", 0, 0, 0, 0 }
5512 };
5513
5514 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5515
5516 /* The MRI OPT pseudo-op. */
5517
5518 static void
5519 s_opt (int ignore ATTRIBUTE_UNUSED)
5520 {
5521 do
5522 {
5523 int t;
5524 char *s;
5525 char c;
5526 int i;
5527 const struct opt_action *o;
5528
5529 SKIP_WHITESPACE ();
5530
5531 t = 1;
5532 if (*input_line_pointer == '-')
5533 {
5534 ++input_line_pointer;
5535 t = 0;
5536 }
5537 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5538 {
5539 input_line_pointer += 2;
5540 t = 0;
5541 }
5542
5543 s = input_line_pointer;
5544 c = get_symbol_end ();
5545
5546 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5547 {
5548 if (strcasecmp (s, o->name) == 0)
5549 {
5550 if (o->pfn)
5551 {
5552 /* Restore input_line_pointer now in case the option
5553 takes arguments. */
5554 *input_line_pointer = c;
5555 (*o->pfn) (o->arg, t);
5556 }
5557 else if (o->pvar != NULL)
5558 {
5559 if (! t && o->arg == o->notarg)
5560 as_bad (_("option `%s' may not be negated"), s);
5561 *input_line_pointer = c;
5562 *o->pvar = t ? o->arg : o->notarg;
5563 }
5564 else
5565 *input_line_pointer = c;
5566 break;
5567 }
5568 }
5569 if (i >= OPTCOUNT)
5570 {
5571 as_bad (_("option `%s' not recognized"), s);
5572 *input_line_pointer = c;
5573 }
5574 }
5575 while (*input_line_pointer++ == ',');
5576
5577 /* Move back to terminating character. */
5578 --input_line_pointer;
5579 demand_empty_rest_of_line ();
5580 }
5581
5582 /* Skip ahead to a comma. This is used for OPT options which we do
5583 not support and which take arguments. */
5584
5585 static void
5586 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5587 {
5588 while (*input_line_pointer != ','
5589 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5590 ++input_line_pointer;
5591 }
5592
5593 /* Handle the OPT NEST=depth option. */
5594
5595 static void
5596 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5597 {
5598 if (*input_line_pointer != '=')
5599 {
5600 as_bad (_("bad format of OPT NEST=depth"));
5601 return;
5602 }
5603
5604 ++input_line_pointer;
5605 max_macro_nest = get_absolute_expression ();
5606 }
5607
5608 /* Handle the OPT P=chip option. */
5609
5610 static void
5611 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5612 {
5613 if (*input_line_pointer != '=')
5614 {
5615 /* This is just OPT P, which we do not support. */
5616 return;
5617 }
5618
5619 ++input_line_pointer;
5620 mri_chip ();
5621 }
5622
5623 /* Handle the OPT S option. */
5624
5625 static void
5626 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5627 {
5628 listing_list (on);
5629 }
5630
5631 /* Handle the OPT T option. */
5632
5633 static void
5634 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5635 {
5636 if (on)
5637 listing |= LISTING_SYMBOLS;
5638 else
5639 listing &= ~LISTING_SYMBOLS;
5640 }
5641
5642 /* Handle the MRI REG pseudo-op. */
5643
5644 static void
5645 s_reg (int ignore ATTRIBUTE_UNUSED)
5646 {
5647 char *s;
5648 int c;
5649 struct m68k_op rop;
5650 int mask;
5651 char *stop = NULL;
5652 char stopc;
5653
5654 if (line_label == NULL)
5655 {
5656 as_bad (_("missing label"));
5657 ignore_rest_of_line ();
5658 return;
5659 }
5660
5661 if (flag_mri)
5662 stop = mri_comment_field (&stopc);
5663
5664 SKIP_WHITESPACE ();
5665
5666 s = input_line_pointer;
5667 while (ISALNUM (*input_line_pointer)
5668 #ifdef REGISTER_PREFIX
5669 || *input_line_pointer == REGISTER_PREFIX
5670 #endif
5671 || *input_line_pointer == '/'
5672 || *input_line_pointer == '-')
5673 ++input_line_pointer;
5674 c = *input_line_pointer;
5675 *input_line_pointer = '\0';
5676
5677 if (m68k_ip_op (s, &rop) != 0)
5678 {
5679 if (rop.error == NULL)
5680 as_bad (_("bad register list"));
5681 else
5682 as_bad (_("bad register list: %s"), rop.error);
5683 *input_line_pointer = c;
5684 ignore_rest_of_line ();
5685 return;
5686 }
5687
5688 *input_line_pointer = c;
5689
5690 if (rop.mode == REGLST)
5691 mask = rop.mask;
5692 else if (rop.mode == DREG)
5693 mask = 1 << (rop.reg - DATA0);
5694 else if (rop.mode == AREG)
5695 mask = 1 << (rop.reg - ADDR0 + 8);
5696 else if (rop.mode == FPREG)
5697 mask = 1 << (rop.reg - FP0 + 16);
5698 else if (rop.mode == CONTROL
5699 && rop.reg == FPI)
5700 mask = 1 << 24;
5701 else if (rop.mode == CONTROL
5702 && rop.reg == FPS)
5703 mask = 1 << 25;
5704 else if (rop.mode == CONTROL
5705 && rop.reg == FPC)
5706 mask = 1 << 26;
5707 else
5708 {
5709 as_bad (_("bad register list"));
5710 ignore_rest_of_line ();
5711 return;
5712 }
5713
5714 S_SET_SEGMENT (line_label, reg_section);
5715 S_SET_VALUE (line_label, ~mask);
5716 symbol_set_frag (line_label, &zero_address_frag);
5717
5718 if (flag_mri)
5719 mri_comment_end (stop, stopc);
5720
5721 demand_empty_rest_of_line ();
5722 }
5723
5724 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5725
5726 struct save_opts
5727 {
5728 struct save_opts *next;
5729 int abspcadd;
5730 int symbols_case_sensitive;
5731 int keep_locals;
5732 int short_refs;
5733 int architecture;
5734 int chip;
5735 int quick;
5736 int rel32;
5737 int listing;
5738 int no_warnings;
5739 /* FIXME: We don't save OPT S. */
5740 };
5741
5742 /* This variable holds the stack of saved options. */
5743
5744 static struct save_opts *save_stack;
5745
5746 /* The MRI SAVE pseudo-op. */
5747
5748 static void
5749 s_save (int ignore ATTRIBUTE_UNUSED)
5750 {
5751 struct save_opts *s;
5752
5753 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5754 s->abspcadd = m68k_abspcadd;
5755 s->symbols_case_sensitive = symbols_case_sensitive;
5756 s->keep_locals = flag_keep_locals;
5757 s->short_refs = flag_short_refs;
5758 s->architecture = current_architecture;
5759 s->chip = current_chip;
5760 s->quick = m68k_quick;
5761 s->rel32 = m68k_rel32;
5762 s->listing = listing;
5763 s->no_warnings = flag_no_warnings;
5764
5765 s->next = save_stack;
5766 save_stack = s;
5767
5768 demand_empty_rest_of_line ();
5769 }
5770
5771 /* The MRI RESTORE pseudo-op. */
5772
5773 static void
5774 s_restore (int ignore ATTRIBUTE_UNUSED)
5775 {
5776 struct save_opts *s;
5777
5778 if (save_stack == NULL)
5779 {
5780 as_bad (_("restore without save"));
5781 ignore_rest_of_line ();
5782 return;
5783 }
5784
5785 s = save_stack;
5786 save_stack = s->next;
5787
5788 m68k_abspcadd = s->abspcadd;
5789 symbols_case_sensitive = s->symbols_case_sensitive;
5790 flag_keep_locals = s->keep_locals;
5791 flag_short_refs = s->short_refs;
5792 current_architecture = s->architecture;
5793 current_chip = s->chip;
5794 m68k_quick = s->quick;
5795 m68k_rel32 = s->rel32;
5796 listing = s->listing;
5797 flag_no_warnings = s->no_warnings;
5798
5799 free (s);
5800
5801 demand_empty_rest_of_line ();
5802 }
5803
5804 /* Types of MRI structured control directives. */
5805
5806 enum mri_control_type
5807 {
5808 mri_for,
5809 mri_if,
5810 mri_repeat,
5811 mri_while
5812 };
5813
5814 /* This structure is used to stack the MRI structured control
5815 directives. */
5816
5817 struct mri_control_info
5818 {
5819 /* The directive within which this one is enclosed. */
5820 struct mri_control_info *outer;
5821
5822 /* The type of directive. */
5823 enum mri_control_type type;
5824
5825 /* Whether an ELSE has been in an IF. */
5826 int else_seen;
5827
5828 /* The add or sub statement at the end of a FOR. */
5829 char *incr;
5830
5831 /* The label of the top of a FOR or REPEAT loop. */
5832 char *top;
5833
5834 /* The label to jump to for the next iteration, or the else
5835 expression of a conditional. */
5836 char *next;
5837
5838 /* The label to jump to to break out of the loop, or the label past
5839 the end of a conditional. */
5840 char *bottom;
5841 };
5842
5843 /* The stack of MRI structured control directives. */
5844
5845 static struct mri_control_info *mri_control_stack;
5846
5847 /* The current MRI structured control directive index number, used to
5848 generate label names. */
5849
5850 static int mri_control_index;
5851
5852 /* Assemble an instruction for an MRI structured control directive. */
5853
5854 static void
5855 mri_assemble (char *str)
5856 {
5857 char *s;
5858
5859 /* md_assemble expects the opcode to be in lower case. */
5860 for (s = str; *s != ' ' && *s != '\0'; s++)
5861 *s = TOLOWER (*s);
5862
5863 md_assemble (str);
5864 }
5865
5866 /* Generate a new MRI label structured control directive label name. */
5867
5868 static char *
5869 mri_control_label (void)
5870 {
5871 char *n;
5872
5873 n = (char *) xmalloc (20);
5874 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5875 ++mri_control_index;
5876 return n;
5877 }
5878
5879 /* Create a new MRI structured control directive. */
5880
5881 static struct mri_control_info *
5882 push_mri_control (enum mri_control_type type)
5883 {
5884 struct mri_control_info *n;
5885
5886 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5887
5888 n->type = type;
5889 n->else_seen = 0;
5890 if (type == mri_if || type == mri_while)
5891 n->top = NULL;
5892 else
5893 n->top = mri_control_label ();
5894 n->next = mri_control_label ();
5895 n->bottom = mri_control_label ();
5896
5897 n->outer = mri_control_stack;
5898 mri_control_stack = n;
5899
5900 return n;
5901 }
5902
5903 /* Pop off the stack of MRI structured control directives. */
5904
5905 static void
5906 pop_mri_control (void)
5907 {
5908 struct mri_control_info *n;
5909
5910 n = mri_control_stack;
5911 mri_control_stack = n->outer;
5912 if (n->top != NULL)
5913 free (n->top);
5914 free (n->next);
5915 free (n->bottom);
5916 free (n);
5917 }
5918
5919 /* Recognize a condition code in an MRI structured control expression. */
5920
5921 static int
5922 parse_mri_condition (int *pcc)
5923 {
5924 char c1, c2;
5925
5926 know (*input_line_pointer == '<');
5927
5928 ++input_line_pointer;
5929 c1 = *input_line_pointer++;
5930 c2 = *input_line_pointer++;
5931
5932 if (*input_line_pointer != '>')
5933 {
5934 as_bad (_("syntax error in structured control directive"));
5935 return 0;
5936 }
5937
5938 ++input_line_pointer;
5939 SKIP_WHITESPACE ();
5940
5941 c1 = TOLOWER (c1);
5942 c2 = TOLOWER (c2);
5943
5944 *pcc = (c1 << 8) | c2;
5945
5946 return 1;
5947 }
5948
5949 /* Parse a single operand in an MRI structured control expression. */
5950
5951 static int
5952 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
5953 char **rightstart, char **rightstop)
5954 {
5955 char *s;
5956
5957 SKIP_WHITESPACE ();
5958
5959 *pcc = -1;
5960 *leftstart = NULL;
5961 *leftstop = NULL;
5962 *rightstart = NULL;
5963 *rightstop = NULL;
5964
5965 if (*input_line_pointer == '<')
5966 {
5967 /* It's just a condition code. */
5968 return parse_mri_condition (pcc);
5969 }
5970
5971 /* Look ahead for the condition code. */
5972 for (s = input_line_pointer; *s != '\0'; ++s)
5973 {
5974 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5975 break;
5976 }
5977 if (*s == '\0')
5978 {
5979 as_bad (_("missing condition code in structured control directive"));
5980 return 0;
5981 }
5982
5983 *leftstart = input_line_pointer;
5984 *leftstop = s;
5985 if (*leftstop > *leftstart
5986 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5987 --*leftstop;
5988
5989 input_line_pointer = s;
5990 if (! parse_mri_condition (pcc))
5991 return 0;
5992
5993 /* Look ahead for AND or OR or end of line. */
5994 for (s = input_line_pointer; *s != '\0'; ++s)
5995 {
5996 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5997 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5998 ^^^ ^^ */
5999 if ((s == input_line_pointer
6000 || *(s-1) == ' '
6001 || *(s-1) == '\t')
6002 && ((strncasecmp (s, "AND", 3) == 0
6003 && (s[3] == '.' || ! is_part_of_name (s[3])))
6004 || (strncasecmp (s, "OR", 2) == 0
6005 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6006 break;
6007 }
6008
6009 *rightstart = input_line_pointer;
6010 *rightstop = s;
6011 if (*rightstop > *rightstart
6012 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6013 --*rightstop;
6014
6015 input_line_pointer = s;
6016
6017 return 1;
6018 }
6019
6020 #define MCC(b1, b2) (((b1) << 8) | (b2))
6021
6022 /* Swap the sense of a condition. This changes the condition so that
6023 it generates the same result when the operands are swapped. */
6024
6025 static int
6026 swap_mri_condition (int cc)
6027 {
6028 switch (cc)
6029 {
6030 case MCC ('h', 'i'): return MCC ('c', 's');
6031 case MCC ('l', 's'): return MCC ('c', 'c');
6032 /* <HS> is an alias for <CC>. */
6033 case MCC ('h', 's'):
6034 case MCC ('c', 'c'): return MCC ('l', 's');
6035 /* <LO> is an alias for <CS>. */
6036 case MCC ('l', 'o'):
6037 case MCC ('c', 's'): return MCC ('h', 'i');
6038 case MCC ('p', 'l'): return MCC ('m', 'i');
6039 case MCC ('m', 'i'): return MCC ('p', 'l');
6040 case MCC ('g', 'e'): return MCC ('l', 'e');
6041 case MCC ('l', 't'): return MCC ('g', 't');
6042 case MCC ('g', 't'): return MCC ('l', 't');
6043 case MCC ('l', 'e'): return MCC ('g', 'e');
6044 /* Issue a warning for conditions we can not swap. */
6045 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6046 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6047 case MCC ('v', 'c'):
6048 case MCC ('v', 's'):
6049 default :
6050 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6051 (char) (cc >> 8), (char) (cc));
6052 break;
6053 }
6054 return cc;
6055 }
6056
6057 /* Reverse the sense of a condition. */
6058
6059 static int
6060 reverse_mri_condition (int cc)
6061 {
6062 switch (cc)
6063 {
6064 case MCC ('h', 'i'): return MCC ('l', 's');
6065 case MCC ('l', 's'): return MCC ('h', 'i');
6066 /* <HS> is an alias for <CC> */
6067 case MCC ('h', 's'): return MCC ('l', 'o');
6068 case MCC ('c', 'c'): return MCC ('c', 's');
6069 /* <LO> is an alias for <CS> */
6070 case MCC ('l', 'o'): return MCC ('h', 's');
6071 case MCC ('c', 's'): return MCC ('c', 'c');
6072 case MCC ('n', 'e'): return MCC ('e', 'q');
6073 case MCC ('e', 'q'): return MCC ('n', 'e');
6074 case MCC ('v', 'c'): return MCC ('v', 's');
6075 case MCC ('v', 's'): return MCC ('v', 'c');
6076 case MCC ('p', 'l'): return MCC ('m', 'i');
6077 case MCC ('m', 'i'): return MCC ('p', 'l');
6078 case MCC ('g', 'e'): return MCC ('l', 't');
6079 case MCC ('l', 't'): return MCC ('g', 'e');
6080 case MCC ('g', 't'): return MCC ('l', 'e');
6081 case MCC ('l', 'e'): return MCC ('g', 't');
6082 }
6083 return cc;
6084 }
6085
6086 /* Build an MRI structured control expression. This generates test
6087 and branch instructions. It goes to TRUELAB if the condition is
6088 true, and to FALSELAB if the condition is false. Exactly one of
6089 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6090 is the size qualifier for the expression. EXTENT is the size to
6091 use for the branch. */
6092
6093 static void
6094 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6095 char *rightstart, char *rightstop,
6096 const char *truelab, const char *falselab,
6097 int extent)
6098 {
6099 char *buf;
6100 char *s;
6101
6102 if (leftstart != NULL)
6103 {
6104 struct m68k_op leftop, rightop;
6105 char c;
6106
6107 /* Swap the compare operands, if necessary, to produce a legal
6108 m68k compare instruction. Comparing a register operand with
6109 a non-register operand requires the register to be on the
6110 right (cmp, cmpa). Comparing an immediate value with
6111 anything requires the immediate value to be on the left
6112 (cmpi). */
6113
6114 c = *leftstop;
6115 *leftstop = '\0';
6116 (void) m68k_ip_op (leftstart, &leftop);
6117 *leftstop = c;
6118
6119 c = *rightstop;
6120 *rightstop = '\0';
6121 (void) m68k_ip_op (rightstart, &rightop);
6122 *rightstop = c;
6123
6124 if (rightop.mode == IMMED
6125 || ((leftop.mode == DREG || leftop.mode == AREG)
6126 && (rightop.mode != DREG && rightop.mode != AREG)))
6127 {
6128 char *temp;
6129
6130 /* Correct conditional handling:
6131 if #1 <lt> d0 then ;means if (1 < d0)
6132 ...
6133 endi
6134
6135 should assemble to:
6136
6137 cmp #1,d0 if we do *not* swap the operands
6138 bgt true we need the swapped condition!
6139 ble false
6140 true:
6141 ...
6142 false:
6143 */
6144 temp = leftstart;
6145 leftstart = rightstart;
6146 rightstart = temp;
6147 temp = leftstop;
6148 leftstop = rightstop;
6149 rightstop = temp;
6150 }
6151 else
6152 {
6153 cc = swap_mri_condition (cc);
6154 }
6155 }
6156
6157 if (truelab == NULL)
6158 {
6159 cc = reverse_mri_condition (cc);
6160 truelab = falselab;
6161 }
6162
6163 if (leftstart != NULL)
6164 {
6165 buf = (char *) xmalloc (20
6166 + (leftstop - leftstart)
6167 + (rightstop - rightstart));
6168 s = buf;
6169 *s++ = 'c';
6170 *s++ = 'm';
6171 *s++ = 'p';
6172 if (qual != '\0')
6173 *s++ = TOLOWER (qual);
6174 *s++ = ' ';
6175 memcpy (s, leftstart, leftstop - leftstart);
6176 s += leftstop - leftstart;
6177 *s++ = ',';
6178 memcpy (s, rightstart, rightstop - rightstart);
6179 s += rightstop - rightstart;
6180 *s = '\0';
6181 mri_assemble (buf);
6182 free (buf);
6183 }
6184
6185 buf = (char *) xmalloc (20 + strlen (truelab));
6186 s = buf;
6187 *s++ = 'b';
6188 *s++ = cc >> 8;
6189 *s++ = cc & 0xff;
6190 if (extent != '\0')
6191 *s++ = TOLOWER (extent);
6192 *s++ = ' ';
6193 strcpy (s, truelab);
6194 mri_assemble (buf);
6195 free (buf);
6196 }
6197
6198 /* Parse an MRI structured control expression. This generates test
6199 and branch instructions. STOP is where the expression ends. It
6200 goes to TRUELAB if the condition is true, and to FALSELAB if the
6201 condition is false. Exactly one of TRUELAB and FALSELAB will be
6202 NULL, meaning to fall through. QUAL is the size qualifier for the
6203 expression. EXTENT is the size to use for the branch. */
6204
6205 static void
6206 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6207 const char *falselab, int extent)
6208 {
6209 int c;
6210 int cc;
6211 char *leftstart;
6212 char *leftstop;
6213 char *rightstart;
6214 char *rightstop;
6215
6216 c = *stop;
6217 *stop = '\0';
6218
6219 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6220 &rightstart, &rightstop))
6221 {
6222 *stop = c;
6223 return;
6224 }
6225
6226 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6227 {
6228 const char *flab;
6229
6230 if (falselab != NULL)
6231 flab = falselab;
6232 else
6233 flab = mri_control_label ();
6234
6235 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6236 rightstop, (const char *) NULL, flab, extent);
6237
6238 input_line_pointer += 3;
6239 if (*input_line_pointer != '.'
6240 || input_line_pointer[1] == '\0')
6241 qual = '\0';
6242 else
6243 {
6244 qual = input_line_pointer[1];
6245 input_line_pointer += 2;
6246 }
6247
6248 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6249 &rightstart, &rightstop))
6250 {
6251 *stop = c;
6252 return;
6253 }
6254
6255 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6256 rightstop, truelab, falselab, extent);
6257
6258 if (falselab == NULL)
6259 colon (flab);
6260 }
6261 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6262 {
6263 const char *tlab;
6264
6265 if (truelab != NULL)
6266 tlab = truelab;
6267 else
6268 tlab = mri_control_label ();
6269
6270 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6271 rightstop, tlab, (const char *) NULL, extent);
6272
6273 input_line_pointer += 2;
6274 if (*input_line_pointer != '.'
6275 || input_line_pointer[1] == '\0')
6276 qual = '\0';
6277 else
6278 {
6279 qual = input_line_pointer[1];
6280 input_line_pointer += 2;
6281 }
6282
6283 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6284 &rightstart, &rightstop))
6285 {
6286 *stop = c;
6287 return;
6288 }
6289
6290 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6291 rightstop, truelab, falselab, extent);
6292
6293 if (truelab == NULL)
6294 colon (tlab);
6295 }
6296 else
6297 {
6298 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6299 rightstop, truelab, falselab, extent);
6300 }
6301
6302 *stop = c;
6303 if (input_line_pointer != stop)
6304 as_bad (_("syntax error in structured control directive"));
6305 }
6306
6307 /* Handle the MRI IF pseudo-op. This may be a structured control
6308 directive, or it may be a regular assembler conditional, depending
6309 on its operands. */
6310
6311 static void
6312 s_mri_if (int qual)
6313 {
6314 char *s;
6315 int c;
6316 struct mri_control_info *n;
6317
6318 /* A structured control directive must end with THEN with an
6319 optional qualifier. */
6320 s = input_line_pointer;
6321 /* We only accept '*' as introduction of comments if preceded by white space
6322 or at first column of a line (I think this can't actually happen here?)
6323 This is important when assembling:
6324 if d0 <ne> 12(a0,d0*2) then
6325 if d0 <ne> #CONST*20 then. */
6326 while (! (is_end_of_line[(unsigned char) *s]
6327 || (flag_mri
6328 && *s == '*'
6329 && (s == input_line_pointer
6330 || *(s-1) == ' '
6331 || *(s-1) == '\t'))))
6332 ++s;
6333 --s;
6334 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6335 --s;
6336
6337 if (s - input_line_pointer > 1
6338 && s[-1] == '.')
6339 s -= 2;
6340
6341 if (s - input_line_pointer < 3
6342 || strncasecmp (s - 3, "THEN", 4) != 0)
6343 {
6344 if (qual != '\0')
6345 {
6346 as_bad (_("missing then"));
6347 ignore_rest_of_line ();
6348 return;
6349 }
6350
6351 /* It's a conditional. */
6352 s_if (O_ne);
6353 return;
6354 }
6355
6356 /* Since this might be a conditional if, this pseudo-op will be
6357 called even if we are supported to be ignoring input. Double
6358 check now. Clobber *input_line_pointer so that ignore_input
6359 thinks that this is not a special pseudo-op. */
6360 c = *input_line_pointer;
6361 *input_line_pointer = 0;
6362 if (ignore_input ())
6363 {
6364 *input_line_pointer = c;
6365 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6366 ++input_line_pointer;
6367 demand_empty_rest_of_line ();
6368 return;
6369 }
6370 *input_line_pointer = c;
6371
6372 n = push_mri_control (mri_if);
6373
6374 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6375 n->next, s[1] == '.' ? s[2] : '\0');
6376
6377 if (s[1] == '.')
6378 input_line_pointer = s + 3;
6379 else
6380 input_line_pointer = s + 1;
6381
6382 if (flag_mri)
6383 {
6384 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6385 ++input_line_pointer;
6386 }
6387
6388 demand_empty_rest_of_line ();
6389 }
6390
6391 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6392 structured IF, associate the ELSE with the IF. Otherwise, assume
6393 it is a conditional else. */
6394
6395 static void
6396 s_mri_else (int qual)
6397 {
6398 int c;
6399 char *buf;
6400 char q[2];
6401
6402 if (qual == '\0'
6403 && (mri_control_stack == NULL
6404 || mri_control_stack->type != mri_if
6405 || mri_control_stack->else_seen))
6406 {
6407 s_else (0);
6408 return;
6409 }
6410
6411 c = *input_line_pointer;
6412 *input_line_pointer = 0;
6413 if (ignore_input ())
6414 {
6415 *input_line_pointer = c;
6416 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6417 ++input_line_pointer;
6418 demand_empty_rest_of_line ();
6419 return;
6420 }
6421 *input_line_pointer = c;
6422
6423 if (mri_control_stack == NULL
6424 || mri_control_stack->type != mri_if
6425 || mri_control_stack->else_seen)
6426 {
6427 as_bad (_("else without matching if"));
6428 ignore_rest_of_line ();
6429 return;
6430 }
6431
6432 mri_control_stack->else_seen = 1;
6433
6434 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6435 q[0] = TOLOWER (qual);
6436 q[1] = '\0';
6437 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6438 mri_assemble (buf);
6439 free (buf);
6440
6441 colon (mri_control_stack->next);
6442
6443 if (flag_mri)
6444 {
6445 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6446 ++input_line_pointer;
6447 }
6448
6449 demand_empty_rest_of_line ();
6450 }
6451
6452 /* Handle the MRI ENDI pseudo-op. */
6453
6454 static void
6455 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6456 {
6457 if (mri_control_stack == NULL
6458 || mri_control_stack->type != mri_if)
6459 {
6460 as_bad (_("endi without matching if"));
6461 ignore_rest_of_line ();
6462 return;
6463 }
6464
6465 /* ignore_input will not return true for ENDI, so we don't need to
6466 worry about checking it again here. */
6467
6468 if (! mri_control_stack->else_seen)
6469 colon (mri_control_stack->next);
6470 colon (mri_control_stack->bottom);
6471
6472 pop_mri_control ();
6473
6474 if (flag_mri)
6475 {
6476 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6477 ++input_line_pointer;
6478 }
6479
6480 demand_empty_rest_of_line ();
6481 }
6482
6483 /* Handle the MRI BREAK pseudo-op. */
6484
6485 static void
6486 s_mri_break (int extent)
6487 {
6488 struct mri_control_info *n;
6489 char *buf;
6490 char ex[2];
6491
6492 n = mri_control_stack;
6493 while (n != NULL
6494 && n->type != mri_for
6495 && n->type != mri_repeat
6496 && n->type != mri_while)
6497 n = n->outer;
6498 if (n == NULL)
6499 {
6500 as_bad (_("break outside of structured loop"));
6501 ignore_rest_of_line ();
6502 return;
6503 }
6504
6505 buf = (char *) xmalloc (20 + strlen (n->bottom));
6506 ex[0] = TOLOWER (extent);
6507 ex[1] = '\0';
6508 sprintf (buf, "bra%s %s", ex, n->bottom);
6509 mri_assemble (buf);
6510 free (buf);
6511
6512 if (flag_mri)
6513 {
6514 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6515 ++input_line_pointer;
6516 }
6517
6518 demand_empty_rest_of_line ();
6519 }
6520
6521 /* Handle the MRI NEXT pseudo-op. */
6522
6523 static void
6524 s_mri_next (int extent)
6525 {
6526 struct mri_control_info *n;
6527 char *buf;
6528 char ex[2];
6529
6530 n = mri_control_stack;
6531 while (n != NULL
6532 && n->type != mri_for
6533 && n->type != mri_repeat
6534 && n->type != mri_while)
6535 n = n->outer;
6536 if (n == NULL)
6537 {
6538 as_bad (_("next outside of structured loop"));
6539 ignore_rest_of_line ();
6540 return;
6541 }
6542
6543 buf = (char *) xmalloc (20 + strlen (n->next));
6544 ex[0] = TOLOWER (extent);
6545 ex[1] = '\0';
6546 sprintf (buf, "bra%s %s", ex, n->next);
6547 mri_assemble (buf);
6548 free (buf);
6549
6550 if (flag_mri)
6551 {
6552 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6553 ++input_line_pointer;
6554 }
6555
6556 demand_empty_rest_of_line ();
6557 }
6558
6559 /* Handle the MRI FOR pseudo-op. */
6560
6561 static void
6562 s_mri_for (int qual)
6563 {
6564 const char *varstart, *varstop;
6565 const char *initstart, *initstop;
6566 const char *endstart, *endstop;
6567 const char *bystart, *bystop;
6568 int up;
6569 int by;
6570 int extent;
6571 struct mri_control_info *n;
6572 char *buf;
6573 char *s;
6574 char ex[2];
6575
6576 /* The syntax is
6577 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6578 */
6579
6580 SKIP_WHITESPACE ();
6581 varstart = input_line_pointer;
6582
6583 /* Look for the '='. */
6584 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6585 && *input_line_pointer != '=')
6586 ++input_line_pointer;
6587 if (*input_line_pointer != '=')
6588 {
6589 as_bad (_("missing ="));
6590 ignore_rest_of_line ();
6591 return;
6592 }
6593
6594 varstop = input_line_pointer;
6595 if (varstop > varstart
6596 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6597 --varstop;
6598
6599 ++input_line_pointer;
6600
6601 initstart = input_line_pointer;
6602
6603 /* Look for TO or DOWNTO. */
6604 up = 1;
6605 initstop = NULL;
6606 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6607 {
6608 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6609 && ! is_part_of_name (input_line_pointer[2]))
6610 {
6611 initstop = input_line_pointer;
6612 input_line_pointer += 2;
6613 break;
6614 }
6615 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6616 && ! is_part_of_name (input_line_pointer[6]))
6617 {
6618 initstop = input_line_pointer;
6619 up = 0;
6620 input_line_pointer += 6;
6621 break;
6622 }
6623 ++input_line_pointer;
6624 }
6625 if (initstop == NULL)
6626 {
6627 as_bad (_("missing to or downto"));
6628 ignore_rest_of_line ();
6629 return;
6630 }
6631 if (initstop > initstart
6632 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6633 --initstop;
6634
6635 SKIP_WHITESPACE ();
6636 endstart = input_line_pointer;
6637
6638 /* Look for BY or DO. */
6639 by = 0;
6640 endstop = NULL;
6641 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6642 {
6643 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6644 && ! is_part_of_name (input_line_pointer[2]))
6645 {
6646 endstop = input_line_pointer;
6647 by = 1;
6648 input_line_pointer += 2;
6649 break;
6650 }
6651 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6652 && (input_line_pointer[2] == '.'
6653 || ! is_part_of_name (input_line_pointer[2])))
6654 {
6655 endstop = input_line_pointer;
6656 input_line_pointer += 2;
6657 break;
6658 }
6659 ++input_line_pointer;
6660 }
6661 if (endstop == NULL)
6662 {
6663 as_bad (_("missing do"));
6664 ignore_rest_of_line ();
6665 return;
6666 }
6667 if (endstop > endstart
6668 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6669 --endstop;
6670
6671 if (! by)
6672 {
6673 bystart = "#1";
6674 bystop = bystart + 2;
6675 }
6676 else
6677 {
6678 SKIP_WHITESPACE ();
6679 bystart = input_line_pointer;
6680
6681 /* Look for DO. */
6682 bystop = NULL;
6683 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6684 {
6685 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6686 && (input_line_pointer[2] == '.'
6687 || ! is_part_of_name (input_line_pointer[2])))
6688 {
6689 bystop = input_line_pointer;
6690 input_line_pointer += 2;
6691 break;
6692 }
6693 ++input_line_pointer;
6694 }
6695 if (bystop == NULL)
6696 {
6697 as_bad (_("missing do"));
6698 ignore_rest_of_line ();
6699 return;
6700 }
6701 if (bystop > bystart
6702 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6703 --bystop;
6704 }
6705
6706 if (*input_line_pointer != '.')
6707 extent = '\0';
6708 else
6709 {
6710 extent = input_line_pointer[1];
6711 input_line_pointer += 2;
6712 }
6713
6714 /* We have fully parsed the FOR operands. Now build the loop. */
6715 n = push_mri_control (mri_for);
6716
6717 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6718
6719 /* Move init,var. */
6720 s = buf;
6721 *s++ = 'm';
6722 *s++ = 'o';
6723 *s++ = 'v';
6724 *s++ = 'e';
6725 if (qual != '\0')
6726 *s++ = TOLOWER (qual);
6727 *s++ = ' ';
6728 memcpy (s, initstart, initstop - initstart);
6729 s += initstop - initstart;
6730 *s++ = ',';
6731 memcpy (s, varstart, varstop - varstart);
6732 s += varstop - varstart;
6733 *s = '\0';
6734 mri_assemble (buf);
6735
6736 colon (n->top);
6737
6738 /* cmp end,var. */
6739 s = buf;
6740 *s++ = 'c';
6741 *s++ = 'm';
6742 *s++ = 'p';
6743 if (qual != '\0')
6744 *s++ = TOLOWER (qual);
6745 *s++ = ' ';
6746 memcpy (s, endstart, endstop - endstart);
6747 s += endstop - endstart;
6748 *s++ = ',';
6749 memcpy (s, varstart, varstop - varstart);
6750 s += varstop - varstart;
6751 *s = '\0';
6752 mri_assemble (buf);
6753
6754 /* bcc bottom. */
6755 ex[0] = TOLOWER (extent);
6756 ex[1] = '\0';
6757 if (up)
6758 sprintf (buf, "blt%s %s", ex, n->bottom);
6759 else
6760 sprintf (buf, "bgt%s %s", ex, n->bottom);
6761 mri_assemble (buf);
6762
6763 /* Put together the add or sub instruction used by ENDF. */
6764 s = buf;
6765 if (up)
6766 strcpy (s, "add");
6767 else
6768 strcpy (s, "sub");
6769 s += 3;
6770 if (qual != '\0')
6771 *s++ = TOLOWER (qual);
6772 *s++ = ' ';
6773 memcpy (s, bystart, bystop - bystart);
6774 s += bystop - bystart;
6775 *s++ = ',';
6776 memcpy (s, varstart, varstop - varstart);
6777 s += varstop - varstart;
6778 *s = '\0';
6779 n->incr = buf;
6780
6781 if (flag_mri)
6782 {
6783 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6784 ++input_line_pointer;
6785 }
6786
6787 demand_empty_rest_of_line ();
6788 }
6789
6790 /* Handle the MRI ENDF pseudo-op. */
6791
6792 static void
6793 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
6794 {
6795 if (mri_control_stack == NULL
6796 || mri_control_stack->type != mri_for)
6797 {
6798 as_bad (_("endf without for"));
6799 ignore_rest_of_line ();
6800 return;
6801 }
6802
6803 colon (mri_control_stack->next);
6804
6805 mri_assemble (mri_control_stack->incr);
6806
6807 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6808 mri_assemble (mri_control_stack->incr);
6809
6810 free (mri_control_stack->incr);
6811
6812 colon (mri_control_stack->bottom);
6813
6814 pop_mri_control ();
6815
6816 if (flag_mri)
6817 {
6818 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6819 ++input_line_pointer;
6820 }
6821
6822 demand_empty_rest_of_line ();
6823 }
6824
6825 /* Handle the MRI REPEAT pseudo-op. */
6826
6827 static void
6828 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
6829 {
6830 struct mri_control_info *n;
6831
6832 n = push_mri_control (mri_repeat);
6833 colon (n->top);
6834 if (flag_mri)
6835 {
6836 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6837 ++input_line_pointer;
6838 }
6839 demand_empty_rest_of_line ();
6840 }
6841
6842 /* Handle the MRI UNTIL pseudo-op. */
6843
6844 static void
6845 s_mri_until (int qual)
6846 {
6847 char *s;
6848
6849 if (mri_control_stack == NULL
6850 || mri_control_stack->type != mri_repeat)
6851 {
6852 as_bad (_("until without repeat"));
6853 ignore_rest_of_line ();
6854 return;
6855 }
6856
6857 colon (mri_control_stack->next);
6858
6859 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6860 ;
6861
6862 parse_mri_control_expression (s, qual, (const char *) NULL,
6863 mri_control_stack->top, '\0');
6864
6865 colon (mri_control_stack->bottom);
6866
6867 input_line_pointer = s;
6868
6869 pop_mri_control ();
6870
6871 if (flag_mri)
6872 {
6873 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6874 ++input_line_pointer;
6875 }
6876
6877 demand_empty_rest_of_line ();
6878 }
6879
6880 /* Handle the MRI WHILE pseudo-op. */
6881
6882 static void
6883 s_mri_while (int qual)
6884 {
6885 char *s;
6886
6887 struct mri_control_info *n;
6888
6889 s = input_line_pointer;
6890 /* We only accept '*' as introduction of comments if preceded by white space
6891 or at first column of a line (I think this can't actually happen here?)
6892 This is important when assembling:
6893 while d0 <ne> 12(a0,d0*2) do
6894 while d0 <ne> #CONST*20 do. */
6895 while (! (is_end_of_line[(unsigned char) *s]
6896 || (flag_mri
6897 && *s == '*'
6898 && (s == input_line_pointer
6899 || *(s-1) == ' '
6900 || *(s-1) == '\t'))))
6901 s++;
6902 --s;
6903 while (*s == ' ' || *s == '\t')
6904 --s;
6905 if (s - input_line_pointer > 1
6906 && s[-1] == '.')
6907 s -= 2;
6908 if (s - input_line_pointer < 2
6909 || strncasecmp (s - 1, "DO", 2) != 0)
6910 {
6911 as_bad (_("missing do"));
6912 ignore_rest_of_line ();
6913 return;
6914 }
6915
6916 n = push_mri_control (mri_while);
6917
6918 colon (n->next);
6919
6920 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6921 s[1] == '.' ? s[2] : '\0');
6922
6923 input_line_pointer = s + 1;
6924 if (*input_line_pointer == '.')
6925 input_line_pointer += 2;
6926
6927 if (flag_mri)
6928 {
6929 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6930 ++input_line_pointer;
6931 }
6932
6933 demand_empty_rest_of_line ();
6934 }
6935
6936 /* Handle the MRI ENDW pseudo-op. */
6937
6938 static void
6939 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
6940 {
6941 char *buf;
6942
6943 if (mri_control_stack == NULL
6944 || mri_control_stack->type != mri_while)
6945 {
6946 as_bad (_("endw without while"));
6947 ignore_rest_of_line ();
6948 return;
6949 }
6950
6951 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6952 sprintf (buf, "bra %s", mri_control_stack->next);
6953 mri_assemble (buf);
6954 free (buf);
6955
6956 colon (mri_control_stack->bottom);
6957
6958 pop_mri_control ();
6959
6960 if (flag_mri)
6961 {
6962 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6963 ++input_line_pointer;
6964 }
6965
6966 demand_empty_rest_of_line ();
6967 }
6968 \f
6969 /* Parse a .cpu directive. */
6970
6971 static void
6972 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
6973 {
6974 char saved_char;
6975 char *name;
6976
6977 if (initialized)
6978 {
6979 as_bad (_("already assembled instructions"));
6980 ignore_rest_of_line ();
6981 return;
6982 }
6983
6984 name = input_line_pointer;
6985 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
6986 input_line_pointer++;
6987 saved_char = *input_line_pointer;
6988 *input_line_pointer = 0;
6989
6990 m68k_set_cpu (name, 1, 0);
6991
6992 *input_line_pointer = saved_char;
6993 demand_empty_rest_of_line ();
6994 return;
6995 }
6996
6997 /* Parse a .arch directive. */
6998
6999 static void
7000 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7001 {
7002 char saved_char;
7003 char *name;
7004
7005 if (initialized)
7006 {
7007 as_bad (_("already assembled instructions"));
7008 ignore_rest_of_line ();
7009 return;
7010 }
7011
7012 name = input_line_pointer;
7013 while (*input_line_pointer && *input_line_pointer != ','
7014 && !ISSPACE (*input_line_pointer))
7015 input_line_pointer++;
7016 saved_char = *input_line_pointer;
7017 *input_line_pointer = 0;
7018
7019 if (m68k_set_arch (name, 1, 0))
7020 {
7021 /* Scan extensions. */
7022 do
7023 {
7024 *input_line_pointer++ = saved_char;
7025 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7026 break;
7027 name = input_line_pointer;
7028 while (*input_line_pointer && *input_line_pointer != ','
7029 && !ISSPACE (*input_line_pointer))
7030 input_line_pointer++;
7031 saved_char = *input_line_pointer;
7032 *input_line_pointer = 0;
7033 }
7034 while (m68k_set_extension (name, 1, 0));
7035 }
7036
7037 *input_line_pointer = saved_char;
7038 demand_empty_rest_of_line ();
7039 return;
7040 }
7041 \f
7042 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7043 if none is found, the caller is responsible for emitting an error
7044 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7045 cpu name, if it begins with a '6' (possibly skipping an intervening
7046 'c'. We also allow a 'c' in the same place. if NEGATED is
7047 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7048 the option is indeed negated. */
7049
7050 static const struct m68k_cpu *
7051 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7052 int allow_m, int *negated)
7053 {
7054 /* allow negated value? */
7055 if (negated)
7056 {
7057 *negated = 0;
7058
7059 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7060 {
7061 arg += 3;
7062 *negated = 1;
7063 }
7064 }
7065
7066 /* Remove 'm' or 'mc' prefix from 68k variants. */
7067 if (allow_m)
7068 {
7069 if (arg[0] == 'm')
7070 {
7071 if (arg[1] == '6')
7072 arg += 1;
7073 else if (arg[1] == 'c' && arg[2] == '6')
7074 arg += 2;
7075 }
7076 }
7077 else if (arg[0] == 'c' && arg[1] == '6')
7078 arg += 1;
7079
7080 for (; table->name; table++)
7081 if (!strcmp (arg, table->name))
7082 return table;
7083 return 0;
7084 }
7085
7086 /* Set the cpu, issuing errors if it is unrecognized, or invalid */
7087
7088 static int
7089 m68k_set_cpu (char const *name, int allow_m, int silent)
7090 {
7091 const struct m68k_cpu *cpu;
7092
7093 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7094
7095 if (!cpu)
7096 {
7097 if (!silent)
7098 as_bad (_("cpu `%s' unrecognized"), name);
7099 return 0;
7100 }
7101
7102 if (selected_cpu && selected_cpu != cpu)
7103 {
7104 as_bad (_("already selected `%s' processor"),
7105 selected_cpu->name);
7106 return 0;
7107 }
7108 selected_cpu = cpu;
7109 return 1;
7110 }
7111
7112 /* Set the architecture, issuing errors if it is unrecognized, or invalid */
7113
7114 static int
7115 m68k_set_arch (char const *name, int allow_m, int silent)
7116 {
7117 const struct m68k_cpu *arch;
7118
7119 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7120
7121 if (!arch)
7122 {
7123 if (!silent)
7124 as_bad (_("architecture `%s' unrecognized"), name);
7125 return 0;
7126 }
7127
7128 if (selected_arch && selected_arch != arch)
7129 {
7130 as_bad (_("already selected `%s' architecture"),
7131 selected_arch->name);
7132 return 0;
7133 }
7134
7135 selected_arch = arch;
7136 return 1;
7137 }
7138
7139 /* Set the architecture extension, issuing errors if it is
7140 unrecognized, or invalid */
7141
7142 static int
7143 m68k_set_extension (char const *name, int allow_m, int silent)
7144 {
7145 int negated;
7146 const struct m68k_cpu *ext;
7147
7148 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7149
7150 if (!ext)
7151 {
7152 if (!silent)
7153 as_bad (_("extension `%s' unrecognized"), name);
7154 return 0;
7155 }
7156
7157 if (negated)
7158 not_current_architecture |= ext->arch;
7159 else
7160 current_architecture |= ext->arch;
7161 return 1;
7162 }
7163
7164 /* md_parse_option
7165 Invocation line includes a switch not recognized by the base assembler.
7166 */
7167
7168 #ifdef OBJ_ELF
7169 const char *md_shortopts = "lSA:m:kQ:V";
7170 #else
7171 const char *md_shortopts = "lSA:m:k";
7172 #endif
7173
7174 struct option md_longopts[] = {
7175 #define OPTION_PIC (OPTION_MD_BASE)
7176 {"pic", no_argument, NULL, OPTION_PIC},
7177 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7178 {"register-prefix-optional", no_argument, NULL,
7179 OPTION_REGISTER_PREFIX_OPTIONAL},
7180 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7181 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7182 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7183 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7184 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7185 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7186 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7187 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7188 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7189 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7190 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7191 {"pcrel", no_argument, NULL, OPTION_PCREL},
7192 {NULL, no_argument, NULL, 0}
7193 };
7194 size_t md_longopts_size = sizeof (md_longopts);
7195
7196 int
7197 md_parse_option (int c, char *arg)
7198 {
7199 switch (c)
7200 {
7201 case 'l': /* -l means keep external to 2 bit offset
7202 rather than 16 bit one. */
7203 flag_short_refs = 1;
7204 break;
7205
7206 case 'S': /* -S means that jbsr's always turn into
7207 jsr's. */
7208 flag_long_jumps = 1;
7209 break;
7210
7211 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7212 branches into absolute jumps. */
7213 flag_keep_pcrel = 1;
7214 break;
7215
7216 case OPTION_PIC:
7217 case 'k':
7218 flag_want_pic = 1;
7219 break; /* -pic, Position Independent Code. */
7220
7221 case OPTION_REGISTER_PREFIX_OPTIONAL:
7222 flag_reg_prefix_optional = 1;
7223 reg_prefix_optional_seen = 1;
7224 break;
7225
7226 /* -V: SVR4 argument to print version ID. */
7227 case 'V':
7228 print_version_id ();
7229 break;
7230
7231 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7232 should be emitted or not. FIXME: Not implemented. */
7233 case 'Q':
7234 break;
7235
7236 case OPTION_BITWISE_OR:
7237 {
7238 char *n, *t;
7239 const char *s;
7240
7241 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7242 t = n;
7243 for (s = m68k_comment_chars; *s != '\0'; s++)
7244 if (*s != '|')
7245 *t++ = *s;
7246 *t = '\0';
7247 m68k_comment_chars = n;
7248 }
7249 break;
7250
7251 case OPTION_BASE_SIZE_DEFAULT_16:
7252 m68k_index_width_default = SIZE_WORD;
7253 break;
7254
7255 case OPTION_BASE_SIZE_DEFAULT_32:
7256 m68k_index_width_default = SIZE_LONG;
7257 break;
7258
7259 case OPTION_DISP_SIZE_DEFAULT_16:
7260 m68k_rel32 = 0;
7261 m68k_rel32_from_cmdline = 1;
7262 break;
7263
7264 case OPTION_DISP_SIZE_DEFAULT_32:
7265 m68k_rel32 = 1;
7266 m68k_rel32_from_cmdline = 1;
7267 break;
7268
7269 case 'A':
7270 #if WARN_DEPRECATED
7271 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7272 arg, arg));
7273 #endif
7274 /* Intentional fall-through. */
7275 case 'm':
7276 if (!strncmp (arg, "arch=", 5))
7277 m68k_set_arch (arg + 5, 1, 0);
7278 else if (!strncmp (arg, "cpu=", 4))
7279 m68k_set_cpu (arg + 4, 1, 0);
7280 else if (m68k_set_extension (arg, 0, 1))
7281 ;
7282 else if (m68k_set_arch (arg, 0, 1))
7283 ;
7284 else if (m68k_set_cpu (arg, 0, 1))
7285 ;
7286 else
7287 return 0;
7288 break;
7289
7290 default:
7291 return 0;
7292 }
7293
7294 return 1;
7295 }
7296
7297 /* Setup tables from the selected arch and/or cpu */
7298
7299 static void
7300 m68k_init_arch (void)
7301 {
7302 if (not_current_architecture & current_architecture)
7303 {
7304 as_bad (_("architecture features both enabled and disabled"));
7305 not_current_architecture &= ~current_architecture;
7306 }
7307 if (selected_arch)
7308 current_architecture |= selected_arch->arch;
7309 else
7310 current_architecture |= selected_cpu->arch;
7311
7312 current_architecture &= ~not_current_architecture;
7313
7314 if (selected_cpu)
7315 {
7316 if (current_architecture & ~selected_cpu->arch)
7317 {
7318 as_bad (_("selected processor does not have all features of selected architecture"));
7319 current_architecture
7320 = selected_cpu->arch & ~not_current_architecture;
7321 }
7322 }
7323
7324 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7325 {
7326 /* Determine which float is really meant. */
7327 if (current_architecture & (m68k_mask & ~m68881))
7328 current_architecture ^= cfloat;
7329 else
7330 current_architecture ^= m68881;
7331 }
7332
7333 if ((current_architecture & m68k_mask)
7334 && (current_architecture & ~m68k_mask))
7335 {
7336 as_bad (_ ("m68k and cf features both selected"));
7337 if (current_architecture & m68k_mask)
7338 current_architecture &= m68k_mask;
7339 else
7340 current_architecture &= ~m68k_mask;
7341 }
7342
7343 /* Permit m68881 specification with all cpus; those that can't work
7344 with a coprocessor could be doing emulation. */
7345 if (current_architecture & m68851)
7346 {
7347 if (current_architecture & m68040)
7348 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7349 }
7350 /* What other incompatibilities could we check for? */
7351
7352 /* Note which set of "movec" control registers is available. */
7353 select_control_regs ();
7354
7355 if (cpu_of_arch (current_architecture) < m68020
7356 || arch_coldfire_p (current_architecture))
7357 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7358
7359 initialized = 1;
7360 }
7361
7362 void
7363 md_show_usage (FILE *stream)
7364 {
7365 const char *default_cpu = TARGET_CPU;
7366 int i;
7367 unsigned int default_arch;
7368
7369 /* Get the canonical name for the default target CPU. */
7370 if (*default_cpu == 'm')
7371 default_cpu++;
7372 for (i = 0; m68k_cpus[i].name; i++)
7373 {
7374 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7375 {
7376 default_arch = m68k_cpus[i].arch;
7377 for (i = 0; m68k_cpus[i].name; i++)
7378 {
7379 if (m68k_cpus[i].arch == default_arch
7380 && !m68k_cpus[i].alias)
7381 {
7382 default_cpu = m68k_cpus[i].name;
7383 break;
7384 }
7385 }
7386 }
7387 }
7388
7389 fprintf (stream, _("\
7390 -march=<arch> set architecture\n\
7391 -mcpu=<cpu> set cpu [default %s]\n\
7392 "), default_cpu);
7393 for (i = 0; m68k_extensions[i].name; i++)
7394 fprintf (stream, _("\
7395 -m[no-]%-16s enable/disable%s architecture extension\n\
7396 "), m68k_extensions[i].name,
7397 m68k_extensions[i].alias > 0 ? " ColdFire"
7398 : m68k_extensions[i].alias < 0 ? " m68k" : "");
7399
7400 fprintf (stream, _("\
7401 -l use 1 word for refs to undefined symbols [default 2]\n\
7402 -pic, -k generate position independent code\n\
7403 -S turn jbsr into jsr\n\
7404 --pcrel never turn PC-relative branches into absolute jumps\n\
7405 --register-prefix-optional\n\
7406 recognize register names without prefix character\n\
7407 --bitwise-or do not treat `|' as a comment character\n\
7408 --base-size-default-16 base reg without size is 16 bits\n\
7409 --base-size-default-32 base reg without size is 32 bits (default)\n\
7410 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7411 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7412 "));
7413
7414 fprintf (stream, _("Architecture variants are: "));
7415 for (i = 0; m68k_archs[i].name; i++)
7416 {
7417 if (i)
7418 fprintf (stream, " | ");
7419 fprintf (stream, m68k_archs[i].name);
7420 }
7421 fprintf (stream, "\n");
7422
7423 fprintf (stream, _("Processor variants are: "));
7424 for (i = 0; m68k_cpus[i].name; i++)
7425 {
7426 if (i)
7427 fprintf (stream, " | ");
7428 fprintf (stream, m68k_cpus[i].name);
7429 }
7430 fprintf (stream, _("\n"));
7431 }
7432 \f
7433 #ifdef TEST2
7434
7435 /* TEST2: Test md_assemble() */
7436 /* Warning, this routine probably doesn't work anymore. */
7437 int
7438 main (void)
7439 {
7440 struct m68k_it the_ins;
7441 char buf[120];
7442 char *cp;
7443 int n;
7444
7445 m68k_ip_begin ();
7446 for (;;)
7447 {
7448 if (!gets (buf) || !*buf)
7449 break;
7450 if (buf[0] == '|' || buf[1] == '.')
7451 continue;
7452 for (cp = buf; *cp; cp++)
7453 if (*cp == '\t')
7454 *cp = ' ';
7455 if (is_label (buf))
7456 continue;
7457 memset (&the_ins, '\0', sizeof (the_ins));
7458 m68k_ip (&the_ins, buf);
7459 if (the_ins.error)
7460 {
7461 printf (_("Error %s in %s\n"), the_ins.error, buf);
7462 }
7463 else
7464 {
7465 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7466 for (n = 0; n < the_ins.numo; n++)
7467 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7468 printf (" ");
7469 print_the_insn (&the_ins.opcode[0], stdout);
7470 (void) putchar ('\n');
7471 }
7472 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7473 {
7474 if (the_ins.operands[n].error)
7475 {
7476 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7477 continue;
7478 }
7479 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7480 the_ins.operands[n].reg);
7481 if (the_ins.operands[n].b_const)
7482 printf ("Constant: '%.*s', ",
7483 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7484 the_ins.operands[n].b_const);
7485 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7486 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7487 if (the_ins.operands[n].b_iadd)
7488 printf ("Iadd: '%.*s',",
7489 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7490 the_ins.operands[n].b_iadd);
7491 putchar ('\n');
7492 }
7493 }
7494 m68k_ip_end ();
7495 return 0;
7496 }
7497
7498 int
7499 is_label (char *str)
7500 {
7501 while (*str == ' ')
7502 str++;
7503 while (*str && *str != ' ')
7504 str++;
7505 if (str[-1] == ':' || str[1] == '=')
7506 return 1;
7507 return 0;
7508 }
7509
7510 #endif
7511
7512 /* Possible states for relaxation:
7513
7514 0 0 branch offset byte (bra, etc)
7515 0 1 word
7516 0 2 long
7517
7518 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7519 1 1 word
7520 1 2 long
7521
7522 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7523 2 1 word-long
7524 2 2 long-word
7525 2 3 long-long
7526
7527 */
7528
7529 /* We have no need to default values of symbols. */
7530
7531 symbolS *
7532 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7533 {
7534 return 0;
7535 }
7536
7537 /* Round up a section size to the appropriate boundary. */
7538 valueT
7539 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7540 {
7541 #ifdef OBJ_AOUT
7542 /* For a.out, force the section size to be aligned. If we don't do
7543 this, BFD will align it for us, but it will not write out the
7544 final bytes of the section. This may be a bug in BFD, but it is
7545 easier to fix it here since that is how the other a.out targets
7546 work. */
7547 int align;
7548
7549 align = bfd_get_section_alignment (stdoutput, segment);
7550 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7551 #endif
7552
7553 return size;
7554 }
7555
7556 /* Exactly what point is a PC-relative offset relative TO?
7557 On the 68k, it is relative to the address of the first extension
7558 word. The difference between the addresses of the offset and the
7559 first extension word is stored in fx_pcrel_adjust. */
7560 long
7561 md_pcrel_from (fixS *fixP)
7562 {
7563 int adjust;
7564
7565 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7566 sign extend the value here. */
7567 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7568 if (adjust == 64)
7569 adjust = -1;
7570 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7571 }
7572
7573 #ifdef OBJ_ELF
7574 void
7575 m68k_elf_final_processing (void)
7576 {
7577 unsigned flags = 0;
7578
7579 if (arch_coldfire_fpu (current_architecture))
7580 flags |= EF_M68K_CFV4E;
7581 /* Set file-specific flags if this is a cpu32 processor. */
7582 if (cpu_of_arch (current_architecture) & cpu32)
7583 flags |= EF_M68K_CPU32;
7584 else if ((cpu_of_arch (current_architecture) & m68000up)
7585 && !(cpu_of_arch (current_architecture) & m68020up))
7586 flags |= EF_M68K_M68000;
7587
7588 if (current_architecture & mcfisa_a)
7589 {
7590 static const unsigned isa_features[][2] =
7591 {
7592 {EF_M68K_ISA_A_NODIV, mcfisa_a},
7593 {EF_M68K_ISA_A, mcfisa_a|mcfhwdiv},
7594 {EF_M68K_ISA_A_PLUS,mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7595 {EF_M68K_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7596 {EF_M68K_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7597 {0,0},
7598 };
7599 static const unsigned mac_features[][2] =
7600 {
7601 {EF_M68K_MAC, mcfmac},
7602 {EF_M68K_EMAC, mcfemac},
7603 {0,0},
7604 };
7605 unsigned ix;
7606 unsigned pattern;
7607
7608 pattern = (current_architecture
7609 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfhwdiv|mcfusp));
7610 for (ix = 0; isa_features[ix][1]; ix++)
7611 {
7612 if (pattern == isa_features[ix][1])
7613 {
7614 flags |= isa_features[ix][0];
7615 break;
7616 }
7617 }
7618 if (!isa_features[ix][1])
7619 {
7620 cf_bad:
7621 as_warn (_("Not a defined coldfire architecture"));
7622 }
7623 else
7624 {
7625 if (current_architecture & cfloat)
7626 flags |= EF_M68K_FLOAT | EF_M68K_CFV4E;
7627
7628 pattern = current_architecture & (mcfmac|mcfemac);
7629 if (pattern)
7630 {
7631 for (ix = 0; mac_features[ix][1]; ix++)
7632 {
7633 if (pattern == mac_features[ix][1])
7634 {
7635 flags |= mac_features[ix][0];
7636 break;
7637 }
7638 }
7639 if (!mac_features[ix][1])
7640 goto cf_bad;
7641 }
7642 }
7643 }
7644 elf_elfheader (stdoutput)->e_flags |= flags;
7645 }
7646 #endif
7647
7648 int
7649 tc_m68k_regname_to_dw2regnum (const char *regname)
7650 {
7651 unsigned int regnum;
7652 static const char *const regnames[] =
7653 {
7654 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7655 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7656 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7657 "pc"
7658 };
7659
7660 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7661 if (strcmp (regname, regnames[regnum]) == 0)
7662 return regnum;
7663
7664 return -1;
7665 }
7666
7667 void
7668 tc_m68k_frame_initial_instructions (void)
7669 {
7670 static int sp_regno = -1;
7671
7672 if (sp_regno < 0)
7673 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7674
7675 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7676 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7677 }
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