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* config/tc-xtensa.c (xg_translate_sysreg_op): Remove has_underbar
[binutils.git] / gas / config / tc-sparc.c
blob04bfb53638eafc1505dc9d818fe4473960221ae0
1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005
4 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public
18 License along with GAS; see the file COPYING. If not, write
19 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
20 Boston, MA 02110-1301, USA. */
21
22 #include <stdio.h>
23
24 #include "as.h"
25 #include "safe-ctype.h"
26 #include "subsegs.h"
27
28 #include "opcode/sparc.h"
29 #include "dw2gencfi.h"
30
31 #ifdef OBJ_ELF
32 #include "elf/sparc.h"
33 #include "dwarf2dbg.h"
34 #endif
35
36 /* Some ancient Sun C compilers would not take such hex constants as
37 unsigned, and would end up sign-extending them to form an offsetT,
38 so use these constants instead. */
39 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
40 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
41
42 static struct sparc_arch *lookup_arch PARAMS ((char *));
43 static void init_default_arch PARAMS ((void));
44 static int sparc_ip PARAMS ((char *, const struct sparc_opcode **));
45 static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
46 static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma));
47 static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
48 static int sparc_ffs PARAMS ((unsigned int));
49 static void synthetize_setuw PARAMS ((const struct sparc_opcode *));
50 static void synthetize_setsw PARAMS ((const struct sparc_opcode *));
51 static void synthetize_setx PARAMS ((const struct sparc_opcode *));
52 static bfd_vma BSR PARAMS ((bfd_vma, int));
53 static int cmp_reg_entry PARAMS ((const PTR, const PTR));
54 static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *));
55 static int parse_const_expr_arg PARAMS ((char **, int *));
56 static int get_expression PARAMS ((char *str));
57
58 /* Default architecture. */
59 /* ??? The default value should be V8, but sparclite support was added
60 by making it the default. GCC now passes -Asparclite, so maybe sometime in
61 the future we can set this to V8. */
62 #ifndef DEFAULT_ARCH
63 #define DEFAULT_ARCH "sparclite"
64 #endif
65 static char *default_arch = DEFAULT_ARCH;
66
67 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
68 have been set. */
69 static int default_init_p;
70
71 /* Current architecture. We don't bump up unless necessary. */
72 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
73
74 /* The maximum architecture level we can bump up to.
75 In a 32 bit environment, don't allow bumping up to v9 by default.
76 The native assembler works this way. The user is required to pass
77 an explicit argument before we'll create v9 object files. However, if
78 we don't see any v9 insns, a v8plus object file is not created. */
79 static enum sparc_opcode_arch_val max_architecture;
80
81 /* Either 32 or 64, selects file format. */
82 static int sparc_arch_size;
83 /* Initial (default) value, recorded separately in case a user option
84 changes the value before md_show_usage is called. */
85 static int default_arch_size;
86
87 #ifdef OBJ_ELF
88 /* The currently selected v9 memory model. Currently only used for
89 ELF. */
90 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
91 #endif
92
93 static int architecture_requested;
94 static int warn_on_bump;
95
96 /* If warn_on_bump and the needed architecture is higher than this
97 architecture, issue a warning. */
98 static enum sparc_opcode_arch_val warn_after_architecture;
99
100 /* Non-zero if as should generate error if an undeclared g[23] register
101 has been used in -64. */
102 static int no_undeclared_regs;
103
104 /* Non-zero if we should try to relax jumps and calls. */
105 static int sparc_relax;
106
107 /* Non-zero if we are generating PIC code. */
108 int sparc_pic_code;
109
110 /* Non-zero if we should give an error when misaligned data is seen. */
111 static int enforce_aligned_data;
112
113 extern int target_big_endian;
114
115 static int target_little_endian_data;
116
117 /* Symbols for global registers on v9. */
118 static symbolS *globals[8];
119
120 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
121 int sparc_cie_data_alignment;
122
123 /* V9 and 86x have big and little endian data, but instructions are always big
124 endian. The sparclet has bi-endian support but both data and insns have
125 the same endianness. Global `target_big_endian' is used for data.
126 The following macro is used for instructions. */
127 #ifndef INSN_BIG_ENDIAN
128 #define INSN_BIG_ENDIAN (target_big_endian \
129 || default_arch_type == sparc86x \
130 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
131 #endif
132
133 /* Handle of the OPCODE hash table. */
134 static struct hash_control *op_hash;
135
136 static int mylog2 PARAMS ((int));
137 static void s_data1 PARAMS ((void));
138 static void s_seg PARAMS ((int));
139 static void s_proc PARAMS ((int));
140 static void s_reserve PARAMS ((int));
141 static void s_common PARAMS ((int));
142 static void s_empty PARAMS ((int));
143 static void s_uacons PARAMS ((int));
144 static void s_ncons PARAMS ((int));
145 #ifdef OBJ_ELF
146 static void s_register PARAMS ((int));
147 #endif
148
149 const pseudo_typeS md_pseudo_table[] =
150 {
151 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
152 {"common", s_common, 0},
153 {"empty", s_empty, 0},
154 {"global", s_globl, 0},
155 {"half", cons, 2},
156 {"nword", s_ncons, 0},
157 {"optim", s_ignore, 0},
158 {"proc", s_proc, 0},
159 {"reserve", s_reserve, 0},
160 {"seg", s_seg, 0},
161 {"skip", s_space, 0},
162 {"word", cons, 4},
163 {"xword", cons, 8},
164 {"uahalf", s_uacons, 2},
165 {"uaword", s_uacons, 4},
166 {"uaxword", s_uacons, 8},
167 #ifdef OBJ_ELF
168 /* These are specific to sparc/svr4. */
169 {"2byte", s_uacons, 2},
170 {"4byte", s_uacons, 4},
171 {"8byte", s_uacons, 8},
172 {"register", s_register, 0},
173 #endif
174 {NULL, 0, 0},
175 };
176
177 /* This array holds the chars that always start a comment. If the
178 pre-processor is disabled, these aren't very useful. */
179 const char comment_chars[] = "!"; /* JF removed '|' from
180 comment_chars. */
181
182 /* This array holds the chars that only start a comment at the beginning of
183 a line. If the line seems to have the form '# 123 filename'
184 .line and .file directives will appear in the pre-processed output. */
185 /* Note that input_file.c hand checks for '#' at the beginning of the
186 first line of the input file. This is because the compiler outputs
187 #NO_APP at the beginning of its output. */
188 /* Also note that comments started like this one will always
189 work if '/' isn't otherwise defined. */
190 const char line_comment_chars[] = "#";
191
192 const char line_separator_chars[] = ";";
193
194 /* Chars that can be used to separate mant from exp in floating point
195 nums. */
196 const char EXP_CHARS[] = "eE";
197
198 /* Chars that mean this number is a floating point constant.
199 As in 0f12.456
200 or 0d1.2345e12 */
201 const char FLT_CHARS[] = "rRsSfFdDxXpP";
202
203 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
204 changed in read.c. Ideally it shouldn't have to know about it at all,
205 but nothing is ideal around here. */
206
207 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
208
209 struct sparc_it
210 {
211 char *error;
212 unsigned long opcode;
213 struct nlist *nlistp;
214 expressionS exp;
215 expressionS exp2;
216 int pcrel;
217 bfd_reloc_code_real_type reloc;
218 };
219
220 struct sparc_it the_insn, set_insn;
221
222 static void output_insn
223 PARAMS ((const struct sparc_opcode *, struct sparc_it *));
224 \f
225 /* Table of arguments to -A.
226 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
227 for this use. That table is for opcodes only. This table is for opcodes
228 and file formats. */
229
230 enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
231 v8plusa, v9, v9a, v9b, v9_64};
232
233 static struct sparc_arch {
234 char *name;
235 char *opcode_arch;
236 enum sparc_arch_types arch_type;
237 /* Default word size, as specified during configuration.
238 A value of zero means can't be used to specify default architecture. */
239 int default_arch_size;
240 /* Allowable arg to -A? */
241 int user_option_p;
242 } sparc_arch_table[] = {
243 { "v6", "v6", v6, 0, 1 },
244 { "v7", "v7", v7, 0, 1 },
245 { "v8", "v8", v8, 32, 1 },
246 { "sparclet", "sparclet", sparclet, 32, 1 },
247 { "sparclite", "sparclite", sparclite, 32, 1 },
248 { "sparc86x", "sparclite", sparc86x, 32, 1 },
249 { "v8plus", "v9", v9, 0, 1 },
250 { "v8plusa", "v9a", v9, 0, 1 },
251 { "v8plusb", "v9b", v9, 0, 1 },
252 { "v9", "v9", v9, 0, 1 },
253 { "v9a", "v9a", v9, 0, 1 },
254 { "v9b", "v9b", v9, 0, 1 },
255 /* This exists to allow configure.in/Makefile.in to pass one
256 value to specify both the default machine and default word size. */
257 { "v9-64", "v9", v9, 64, 0 },
258 { NULL, NULL, v8, 0, 0 }
259 };
260
261 /* Variant of default_arch */
262 static enum sparc_arch_types default_arch_type;
263
264 static struct sparc_arch *
265 lookup_arch (name)
266 char *name;
267 {
268 struct sparc_arch *sa;
269
270 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
271 if (strcmp (sa->name, name) == 0)
272 break;
273 if (sa->name == NULL)
274 return NULL;
275 return sa;
276 }
277
278 /* Initialize the default opcode arch and word size from the default
279 architecture name. */
280
281 static void
282 init_default_arch ()
283 {
284 struct sparc_arch *sa = lookup_arch (default_arch);
285
286 if (sa == NULL
287 || sa->default_arch_size == 0)
288 as_fatal (_("Invalid default architecture, broken assembler."));
289
290 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
291 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
292 as_fatal (_("Bad opcode table, broken assembler."));
293 default_arch_size = sparc_arch_size = sa->default_arch_size;
294 default_init_p = 1;
295 default_arch_type = sa->arch_type;
296 }
297
298 /* Called by TARGET_FORMAT. */
299
300 const char *
301 sparc_target_format ()
302 {
303 /* We don't get a chance to initialize anything before we're called,
304 so handle that now. */
305 if (! default_init_p)
306 init_default_arch ();
307
308 #ifdef OBJ_AOUT
309 #ifdef TE_NetBSD
310 return "a.out-sparc-netbsd";
311 #else
312 #ifdef TE_SPARCAOUT
313 if (target_big_endian)
314 return "a.out-sunos-big";
315 else if (default_arch_type == sparc86x && target_little_endian_data)
316 return "a.out-sunos-big";
317 else
318 return "a.out-sparc-little";
319 #else
320 return "a.out-sunos-big";
321 #endif
322 #endif
323 #endif
324
325 #ifdef OBJ_BOUT
326 return "b.out.big";
327 #endif
328
329 #ifdef OBJ_COFF
330 #ifdef TE_LYNX
331 return "coff-sparc-lynx";
332 #else
333 return "coff-sparc";
334 #endif
335 #endif
336
337 #ifdef OBJ_ELF
338 return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc";
339 #endif
340
341 abort ();
342 }
343 \f
344 /* md_parse_option
345 * Invocation line includes a switch not recognized by the base assembler.
346 * See if it's a processor-specific option. These are:
347 *
348 * -bump
349 * Warn on architecture bumps. See also -A.
350 *
351 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
352 * Standard 32 bit architectures.
353 * -Av9, -Av9a, -Av9b
354 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
355 * This used to only mean 64 bits, but properly specifying it
356 * complicated gcc's ASM_SPECs, so now opcode selection is
357 * specified orthogonally to word size (except when specifying
358 * the default, but that is an internal implementation detail).
359 * -Av8plus, -Av8plusa, -Av8plusb
360 * Same as -Av9{,a,b}.
361 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
362 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
363 * assembler.
364 * -xarch=v9, -xarch=v9a, -xarch=v9b
365 * Same as -Av9{,a,b} -64, for compatibility with Sun's
366 * assembler.
367 *
368 * Select the architecture and possibly the file format.
369 * Instructions or features not supported by the selected
370 * architecture cause fatal errors.
371 *
372 * The default is to start at v6, and bump the architecture up
373 * whenever an instruction is seen at a higher level. In 32 bit
374 * environments, v9 is not bumped up to, the user must pass
375 * -Av8plus{,a,b}.
376 *
377 * If -bump is specified, a warning is printing when bumping to
378 * higher levels.
379 *
380 * If an architecture is specified, all instructions must match
381 * that architecture. Any higher level instructions are flagged
382 * as errors. Note that in the 32 bit environment specifying
383 * -Av8plus does not automatically create a v8plus object file, a
384 * v9 insn must be seen.
385 *
386 * If both an architecture and -bump are specified, the
387 * architecture starts at the specified level, but bumps are
388 * warnings. Note that we can't set `current_architecture' to
389 * the requested level in this case: in the 32 bit environment,
390 * we still must avoid creating v8plus object files unless v9
391 * insns are seen.
392 *
393 * Note:
394 * Bumping between incompatible architectures is always an
395 * error. For example, from sparclite to v9.
396 */
397
398 #ifdef OBJ_ELF
399 const char *md_shortopts = "A:K:VQ:sq";
400 #else
401 #ifdef OBJ_AOUT
402 const char *md_shortopts = "A:k";
403 #else
404 const char *md_shortopts = "A:";
405 #endif
406 #endif
407 struct option md_longopts[] = {
408 #define OPTION_BUMP (OPTION_MD_BASE)
409 {"bump", no_argument, NULL, OPTION_BUMP},
410 #define OPTION_SPARC (OPTION_MD_BASE + 1)
411 {"sparc", no_argument, NULL, OPTION_SPARC},
412 #define OPTION_XARCH (OPTION_MD_BASE + 2)
413 {"xarch", required_argument, NULL, OPTION_XARCH},
414 #ifdef OBJ_ELF
415 #define OPTION_32 (OPTION_MD_BASE + 3)
416 {"32", no_argument, NULL, OPTION_32},
417 #define OPTION_64 (OPTION_MD_BASE + 4)
418 {"64", no_argument, NULL, OPTION_64},
419 #define OPTION_TSO (OPTION_MD_BASE + 5)
420 {"TSO", no_argument, NULL, OPTION_TSO},
421 #define OPTION_PSO (OPTION_MD_BASE + 6)
422 {"PSO", no_argument, NULL, OPTION_PSO},
423 #define OPTION_RMO (OPTION_MD_BASE + 7)
424 {"RMO", no_argument, NULL, OPTION_RMO},
425 #endif
426 #ifdef SPARC_BIENDIAN
427 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
428 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
429 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
430 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
431 #endif
432 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
433 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
434 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
435 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
436 #ifdef OBJ_ELF
437 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
438 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
439 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
440 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
441 #endif
442 #define OPTION_RELAX (OPTION_MD_BASE + 14)
443 {"relax", no_argument, NULL, OPTION_RELAX},
444 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
445 {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
446 {NULL, no_argument, NULL, 0}
447 };
448
449 size_t md_longopts_size = sizeof (md_longopts);
450
451 int
452 md_parse_option (c, arg)
453 int c;
454 char *arg;
455 {
456 /* We don't get a chance to initialize anything before we're called,
457 so handle that now. */
458 if (! default_init_p)
459 init_default_arch ();
460
461 switch (c)
462 {
463 case OPTION_BUMP:
464 warn_on_bump = 1;
465 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
466 break;
467
468 case OPTION_XARCH:
469 #ifdef OBJ_ELF
470 if (strncmp (arg, "v9", 2) != 0)
471 md_parse_option (OPTION_32, NULL);
472 else
473 md_parse_option (OPTION_64, NULL);
474 #endif
475 /* Fall through. */
476
477 case 'A':
478 {
479 struct sparc_arch *sa;
480 enum sparc_opcode_arch_val opcode_arch;
481
482 sa = lookup_arch (arg);
483 if (sa == NULL
484 || ! sa->user_option_p)
485 {
486 if (c == OPTION_XARCH)
487 as_bad (_("invalid architecture -xarch=%s"), arg);
488 else
489 as_bad (_("invalid architecture -A%s"), arg);
490 return 0;
491 }
492
493 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
494 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
495 as_fatal (_("Bad opcode table, broken assembler."));
496
497 max_architecture = opcode_arch;
498 architecture_requested = 1;
499 }
500 break;
501
502 case OPTION_SPARC:
503 /* Ignore -sparc, used by SunOS make default .s.o rule. */
504 break;
505
506 case OPTION_ENFORCE_ALIGNED_DATA:
507 enforce_aligned_data = 1;
508 break;
509
510 #ifdef SPARC_BIENDIAN
511 case OPTION_LITTLE_ENDIAN:
512 target_big_endian = 0;
513 if (default_arch_type != sparclet)
514 as_fatal ("This target does not support -EL");
515 break;
516 case OPTION_LITTLE_ENDIAN_DATA:
517 target_little_endian_data = 1;
518 target_big_endian = 0;
519 if (default_arch_type != sparc86x
520 && default_arch_type != v9)
521 as_fatal ("This target does not support --little-endian-data");
522 break;
523 case OPTION_BIG_ENDIAN:
524 target_big_endian = 1;
525 break;
526 #endif
527
528 #ifdef OBJ_AOUT
529 case 'k':
530 sparc_pic_code = 1;
531 break;
532 #endif
533
534 #ifdef OBJ_ELF
535 case OPTION_32:
536 case OPTION_64:
537 {
538 const char **list, **l;
539
540 sparc_arch_size = c == OPTION_32 ? 32 : 64;
541 list = bfd_target_list ();
542 for (l = list; *l != NULL; l++)
543 {
544 if (sparc_arch_size == 32)
545 {
546 if (strcmp (*l, "elf32-sparc") == 0)
547 break;
548 }
549 else
550 {
551 if (strcmp (*l, "elf64-sparc") == 0)
552 break;
553 }
554 }
555 if (*l == NULL)
556 as_fatal (_("No compiled in support for %d bit object file format"),
557 sparc_arch_size);
558 free (list);
559 }
560 break;
561
562 case OPTION_TSO:
563 sparc_memory_model = MM_TSO;
564 break;
565
566 case OPTION_PSO:
567 sparc_memory_model = MM_PSO;
568 break;
569
570 case OPTION_RMO:
571 sparc_memory_model = MM_RMO;
572 break;
573
574 case 'V':
575 print_version_id ();
576 break;
577
578 case 'Q':
579 /* Qy - do emit .comment
580 Qn - do not emit .comment. */
581 break;
582
583 case 's':
584 /* Use .stab instead of .stab.excl. */
585 break;
586
587 case 'q':
588 /* quick -- Native assembler does fewer checks. */
589 break;
590
591 case 'K':
592 if (strcmp (arg, "PIC") != 0)
593 as_warn (_("Unrecognized option following -K"));
594 else
595 sparc_pic_code = 1;
596 break;
597
598 case OPTION_NO_UNDECLARED_REGS:
599 no_undeclared_regs = 1;
600 break;
601
602 case OPTION_UNDECLARED_REGS:
603 no_undeclared_regs = 0;
604 break;
605 #endif
606
607 case OPTION_RELAX:
608 sparc_relax = 1;
609 break;
610
611 case OPTION_NO_RELAX:
612 sparc_relax = 0;
613 break;
614
615 default:
616 return 0;
617 }
618
619 return 1;
620 }
621
622 void
623 md_show_usage (stream)
624 FILE *stream;
625 {
626 const struct sparc_arch *arch;
627 int column;
628
629 /* We don't get a chance to initialize anything before we're called,
630 so handle that now. */
631 if (! default_init_p)
632 init_default_arch ();
633
634 fprintf (stream, _("SPARC options:\n"));
635 column = 0;
636 for (arch = &sparc_arch_table[0]; arch->name; arch++)
637 {
638 if (!arch->user_option_p)
639 continue;
640 if (arch != &sparc_arch_table[0])
641 fprintf (stream, " | ");
642 if (column + strlen (arch->name) > 70)
643 {
644 column = 0;
645 fputc ('\n', stream);
646 }
647 column += 5 + 2 + strlen (arch->name);
648 fprintf (stream, "-A%s", arch->name);
649 }
650 for (arch = &sparc_arch_table[0]; arch->name; arch++)
651 {
652 if (!arch->user_option_p)
653 continue;
654 fprintf (stream, " | ");
655 if (column + strlen (arch->name) > 65)
656 {
657 column = 0;
658 fputc ('\n', stream);
659 }
660 column += 5 + 7 + strlen (arch->name);
661 fprintf (stream, "-xarch=%s", arch->name);
662 }
663 fprintf (stream, _("\n\
664 specify variant of SPARC architecture\n\
665 -bump warn when assembler switches architectures\n\
666 -sparc ignored\n\
667 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
668 -relax relax jumps and branches (default)\n\
669 -no-relax avoid changing any jumps and branches\n"));
670 #ifdef OBJ_AOUT
671 fprintf (stream, _("\
672 -k generate PIC\n"));
673 #endif
674 #ifdef OBJ_ELF
675 fprintf (stream, _("\
676 -32 create 32 bit object file\n\
677 -64 create 64 bit object file\n"));
678 fprintf (stream, _("\
679 [default is %d]\n"), default_arch_size);
680 fprintf (stream, _("\
681 -TSO use Total Store Ordering\n\
682 -PSO use Partial Store Ordering\n\
683 -RMO use Relaxed Memory Ordering\n"));
684 fprintf (stream, _("\
685 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
686 fprintf (stream, _("\
687 -KPIC generate PIC\n\
688 -V print assembler version number\n\
689 -undeclared-regs ignore application global register usage without\n\
690 appropriate .register directive (default)\n\
691 -no-undeclared-regs force error on application global register usage\n\
692 without appropriate .register directive\n\
693 -q ignored\n\
694 -Qy, -Qn ignored\n\
695 -s ignored\n"));
696 #endif
697 #ifdef SPARC_BIENDIAN
698 fprintf (stream, _("\
699 -EL generate code for a little endian machine\n\
700 -EB generate code for a big endian machine\n\
701 --little-endian-data generate code for a machine having big endian\n\
702 instructions and little endian data.\n"));
703 #endif
704 }
705 \f
706 /* Native operand size opcode translation. */
707 struct
708 {
709 char *name;
710 char *name32;
711 char *name64;
712 } native_op_table[] =
713 {
714 {"ldn", "ld", "ldx"},
715 {"ldna", "lda", "ldxa"},
716 {"stn", "st", "stx"},
717 {"stna", "sta", "stxa"},
718 {"slln", "sll", "sllx"},
719 {"srln", "srl", "srlx"},
720 {"sran", "sra", "srax"},
721 {"casn", "cas", "casx"},
722 {"casna", "casa", "casxa"},
723 {"clrn", "clr", "clrx"},
724 {NULL, NULL, NULL},
725 };
726 \f
727 /* sparc64 privileged and hyperprivileged registers. */
728
729 struct priv_reg_entry
730 {
731 char *name;
732 int regnum;
733 };
734
735 struct priv_reg_entry priv_reg_table[] =
736 {
737 {"tpc", 0},
738 {"tnpc", 1},
739 {"tstate", 2},
740 {"tt", 3},
741 {"tick", 4},
742 {"tba", 5},
743 {"pstate", 6},
744 {"tl", 7},
745 {"pil", 8},
746 {"cwp", 9},
747 {"cansave", 10},
748 {"canrestore", 11},
749 {"cleanwin", 12},
750 {"otherwin", 13},
751 {"wstate", 14},
752 {"fq", 15},
753 {"gl", 16},
754 {"ver", 31},
755 {"", -1}, /* End marker. */
756 };
757
758 struct priv_reg_entry hpriv_reg_table[] =
759 {
760 {"hpstate", 0},
761 {"htstate", 1},
762 {"hintp", 3},
763 {"htba", 5},
764 {"hver", 6},
765 {"hstick_cmpr", 31},
766 {"", -1}, /* End marker. */
767 };
768
769 /* v9a specific asrs. */
770
771 struct priv_reg_entry v9a_asr_table[] =
772 {
773 {"tick_cmpr", 23},
774 {"sys_tick_cmpr", 25},
775 {"sys_tick", 24},
776 {"softint", 22},
777 {"set_softint", 20},
778 {"pic", 17},
779 {"pcr", 16},
780 {"gsr", 19},
781 {"dcr", 18},
782 {"clear_softint", 21},
783 {"", -1}, /* End marker. */
784 };
785
786 static int
787 cmp_reg_entry (parg, qarg)
788 const PTR parg;
789 const PTR qarg;
790 {
791 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
792 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
793
794 return strcmp (q->name, p->name);
795 }
796 \f
797 /* This function is called once, at assembler startup time. It should
798 set up all the tables, etc. that the MD part of the assembler will
799 need. */
800
801 void
802 md_begin ()
803 {
804 register const char *retval = NULL;
805 int lose = 0;
806 register unsigned int i = 0;
807
808 /* We don't get a chance to initialize anything before md_parse_option
809 is called, and it may not be called, so handle default initialization
810 now if not already done. */
811 if (! default_init_p)
812 init_default_arch ();
813
814 sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4;
815 op_hash = hash_new ();
816
817 while (i < (unsigned int) sparc_num_opcodes)
818 {
819 const char *name = sparc_opcodes[i].name;
820 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]);
821 if (retval != NULL)
822 {
823 as_bad (_("Internal error: can't hash `%s': %s\n"),
824 sparc_opcodes[i].name, retval);
825 lose = 1;
826 }
827 do
828 {
829 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
830 {
831 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
832 sparc_opcodes[i].name, sparc_opcodes[i].args);
833 lose = 1;
834 }
835 ++i;
836 }
837 while (i < (unsigned int) sparc_num_opcodes
838 && !strcmp (sparc_opcodes[i].name, name));
839 }
840
841 for (i = 0; native_op_table[i].name; i++)
842 {
843 const struct sparc_opcode *insn;
844 char *name = ((sparc_arch_size == 32)
845 ? native_op_table[i].name32
846 : native_op_table[i].name64);
847 insn = (struct sparc_opcode *) hash_find (op_hash, name);
848 if (insn == NULL)
849 {
850 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
851 name, native_op_table[i].name);
852 lose = 1;
853 }
854 else
855 {
856 retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn);
857 if (retval != NULL)
858 {
859 as_bad (_("Internal error: can't hash `%s': %s\n"),
860 sparc_opcodes[i].name, retval);
861 lose = 1;
862 }
863 }
864 }
865
866 if (lose)
867 as_fatal (_("Broken assembler. No assembly attempted."));
868
869 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
870 sizeof (priv_reg_table[0]), cmp_reg_entry);
871
872 /* If -bump, record the architecture level at which we start issuing
873 warnings. The behaviour is different depending upon whether an
874 architecture was explicitly specified. If it wasn't, we issue warnings
875 for all upwards bumps. If it was, we don't start issuing warnings until
876 we need to bump beyond the requested architecture or when we bump between
877 conflicting architectures. */
878
879 if (warn_on_bump
880 && architecture_requested)
881 {
882 /* `max_architecture' records the requested architecture.
883 Issue warnings if we go above it. */
884 warn_after_architecture = max_architecture;
885
886 /* Find the highest architecture level that doesn't conflict with
887 the requested one. */
888 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
889 max_architecture > warn_after_architecture;
890 --max_architecture)
891 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
892 warn_after_architecture))
893 break;
894 }
895 }
896
897 /* Called after all assembly has been done. */
898
899 void
900 sparc_md_end ()
901 {
902 unsigned long mach = bfd_mach_sparc;
903
904 if (sparc_arch_size == 64)
905 switch (current_architecture)
906 {
907 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
908 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
909 default: mach = bfd_mach_sparc_v9; break;
910 }
911 else
912 switch (current_architecture)
913 {
914 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
915 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
916 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
917 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
918 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
919 be but for now it is (since that's the way it's always been
920 treated). */
921 default: break;
922 }
923 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
924 }
925 \f
926 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
927
928 static INLINE int
929 in_signed_range (val, max)
930 bfd_signed_vma val, max;
931 {
932 if (max <= 0)
933 abort ();
934 /* Sign-extend the value from the architecture word size, so that
935 0xffffffff is always considered -1 on sparc32. */
936 if (sparc_arch_size == 32)
937 {
938 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
939 val = ((val & U0xffffffff) ^ sign) - sign;
940 }
941 if (val > max)
942 return 0;
943 if (val < ~max)
944 return 0;
945 return 1;
946 }
947
948 /* Return non-zero if VAL is in the range 0 to MAX. */
949
950 static INLINE int
951 in_unsigned_range (val, max)
952 bfd_vma val, max;
953 {
954 if (val > max)
955 return 0;
956 return 1;
957 }
958
959 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
960 (e.g. -15 to +31). */
961
962 static INLINE int
963 in_bitfield_range (val, max)
964 bfd_signed_vma val, max;
965 {
966 if (max <= 0)
967 abort ();
968 if (val > max)
969 return 0;
970 if (val < ~(max >> 1))
971 return 0;
972 return 1;
973 }
974
975 static int
976 sparc_ffs (mask)
977 unsigned int mask;
978 {
979 int i;
980
981 if (mask == 0)
982 return -1;
983
984 for (i = 0; (mask & 1) == 0; ++i)
985 mask >>= 1;
986 return i;
987 }
988
989 /* Implement big shift right. */
990 static bfd_vma
991 BSR (val, amount)
992 bfd_vma val;
993 int amount;
994 {
995 if (sizeof (bfd_vma) <= 4 && amount >= 32)
996 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
997 return val >> amount;
998 }
999 \f
1000 /* For communication between sparc_ip and get_expression. */
1001 static char *expr_end;
1002
1003 /* Values for `special_case'.
1004 Instructions that require wierd handling because they're longer than
1005 4 bytes. */
1006 #define SPECIAL_CASE_NONE 0
1007 #define SPECIAL_CASE_SET 1
1008 #define SPECIAL_CASE_SETSW 2
1009 #define SPECIAL_CASE_SETX 3
1010 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1011 #define SPECIAL_CASE_FDIV 4
1012
1013 /* Bit masks of various insns. */
1014 #define NOP_INSN 0x01000000
1015 #define OR_INSN 0x80100000
1016 #define XOR_INSN 0x80180000
1017 #define FMOVS_INSN 0x81A00020
1018 #define SETHI_INSN 0x01000000
1019 #define SLLX_INSN 0x81281000
1020 #define SRA_INSN 0x81380000
1021
1022 /* The last instruction to be assembled. */
1023 static const struct sparc_opcode *last_insn;
1024 /* The assembled opcode of `last_insn'. */
1025 static unsigned long last_opcode;
1026 \f
1027 /* Handle the set and setuw synthetic instructions. */
1028
1029 static void
1030 synthetize_setuw (insn)
1031 const struct sparc_opcode *insn;
1032 {
1033 int need_hi22_p = 0;
1034 int rd = (the_insn.opcode & RD (~0)) >> 25;
1035
1036 if (the_insn.exp.X_op == O_constant)
1037 {
1038 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1039 {
1040 if (sizeof (offsetT) > 4
1041 && (the_insn.exp.X_add_number < 0
1042 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1043 as_warn (_("set: number not in 0..4294967295 range"));
1044 }
1045 else
1046 {
1047 if (sizeof (offsetT) > 4
1048 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1049 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1050 as_warn (_("set: number not in -2147483648..4294967295 range"));
1051 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
1052 }
1053 }
1054
1055 /* See if operand is absolute and small; skip sethi if so. */
1056 if (the_insn.exp.X_op != O_constant
1057 || the_insn.exp.X_add_number >= (1 << 12)
1058 || the_insn.exp.X_add_number < -(1 << 12))
1059 {
1060 the_insn.opcode = (SETHI_INSN | RD (rd)
1061 | ((the_insn.exp.X_add_number >> 10)
1062 & (the_insn.exp.X_op == O_constant
1063 ? 0x3fffff : 0)));
1064 the_insn.reloc = (the_insn.exp.X_op != O_constant
1065 ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
1066 output_insn (insn, &the_insn);
1067 need_hi22_p = 1;
1068 }
1069
1070 /* See if operand has no low-order bits; skip OR if so. */
1071 if (the_insn.exp.X_op != O_constant
1072 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1073 || ! need_hi22_p)
1074 {
1075 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1076 | RD (rd) | IMMED
1077 | (the_insn.exp.X_add_number
1078 & (the_insn.exp.X_op != O_constant
1079 ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
1080 the_insn.reloc = (the_insn.exp.X_op != O_constant
1081 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1082 output_insn (insn, &the_insn);
1083 }
1084 }
1085
1086 /* Handle the setsw synthetic instruction. */
1087
1088 static void
1089 synthetize_setsw (insn)
1090 const struct sparc_opcode *insn;
1091 {
1092 int low32, rd, opc;
1093
1094 rd = (the_insn.opcode & RD (~0)) >> 25;
1095
1096 if (the_insn.exp.X_op != O_constant)
1097 {
1098 synthetize_setuw (insn);
1099
1100 /* Need to sign extend it. */
1101 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1102 the_insn.reloc = BFD_RELOC_NONE;
1103 output_insn (insn, &the_insn);
1104 return;
1105 }
1106
1107 if (sizeof (offsetT) > 4
1108 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1109 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1110 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1111
1112 low32 = the_insn.exp.X_add_number;
1113
1114 if (low32 >= 0)
1115 {
1116 synthetize_setuw (insn);
1117 return;
1118 }
1119
1120 opc = OR_INSN;
1121
1122 the_insn.reloc = BFD_RELOC_NONE;
1123 /* See if operand is absolute and small; skip sethi if so. */
1124 if (low32 < -(1 << 12))
1125 {
1126 the_insn.opcode = (SETHI_INSN | RD (rd)
1127 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1128 output_insn (insn, &the_insn);
1129 low32 = 0x1c00 | (low32 & 0x3ff);
1130 opc = RS1 (rd) | XOR_INSN;
1131 }
1132
1133 the_insn.opcode = (opc | RD (rd) | IMMED
1134 | (low32 & 0x1fff));
1135 output_insn (insn, &the_insn);
1136 }
1137
1138 /* Handle the setsw synthetic instruction. */
1139
1140 static void
1141 synthetize_setx (insn)
1142 const struct sparc_opcode *insn;
1143 {
1144 int upper32, lower32;
1145 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1146 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1147 int upper_dstreg;
1148 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1149 int need_xor10_p = 0;
1150
1151 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1152 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1153 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1154 #undef SIGNEXT32
1155
1156 upper_dstreg = tmpreg;
1157 /* The tmp reg should not be the dst reg. */
1158 if (tmpreg == dstreg)
1159 as_warn (_("setx: temporary register same as destination register"));
1160
1161 /* ??? Obviously there are other optimizations we can do
1162 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1163 doing some of these. Later. If you do change things, try to
1164 change all of this to be table driven as well. */
1165 /* What to output depends on the number if it's constant.
1166 Compute that first, then output what we've decided upon. */
1167 if (the_insn.exp.X_op != O_constant)
1168 {
1169 if (sparc_arch_size == 32)
1170 {
1171 /* When arch size is 32, we want setx to be equivalent
1172 to setuw for anything but constants. */
1173 the_insn.exp.X_add_number &= 0xffffffff;
1174 synthetize_setuw (insn);
1175 return;
1176 }
1177 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1178 lower32 = 0;
1179 upper32 = 0;
1180 }
1181 else
1182 {
1183 /* Reset X_add_number, we've extracted it as upper32/lower32.
1184 Otherwise fixup_segment will complain about not being able to
1185 write an 8 byte number in a 4 byte field. */
1186 the_insn.exp.X_add_number = 0;
1187
1188 /* Only need hh22 if `or' insn can't handle constant. */
1189 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1190 need_hh22_p = 1;
1191
1192 /* Does bottom part (after sethi) have bits? */
1193 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1194 /* No hh22, but does upper32 still have bits we can't set
1195 from lower32? */
1196 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1197 need_hm10_p = 1;
1198
1199 /* If the lower half is all zero, we build the upper half directly
1200 into the dst reg. */
1201 if (lower32 != 0
1202 /* Need lower half if number is zero or 0xffffffff00000000. */
1203 || (! need_hh22_p && ! need_hm10_p))
1204 {
1205 /* No need for sethi if `or' insn can handle constant. */
1206 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1207 /* Note that we can't use a negative constant in the `or'
1208 insn unless the upper 32 bits are all ones. */
1209 || (lower32 < 0 && upper32 != -1)
1210 || (lower32 >= 0 && upper32 == -1))
1211 need_hi22_p = 1;
1212
1213 if (need_hi22_p && upper32 == -1)
1214 need_xor10_p = 1;
1215
1216 /* Does bottom part (after sethi) have bits? */
1217 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1218 /* No sethi. */
1219 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1220 /* Need `or' if we didn't set anything else. */
1221 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1222 need_lo10_p = 1;
1223 }
1224 else
1225 /* Output directly to dst reg if lower 32 bits are all zero. */
1226 upper_dstreg = dstreg;
1227 }
1228
1229 if (!upper_dstreg && dstreg)
1230 as_warn (_("setx: illegal temporary register g0"));
1231
1232 if (need_hh22_p)
1233 {
1234 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1235 | ((upper32 >> 10) & 0x3fffff));
1236 the_insn.reloc = (the_insn.exp.X_op != O_constant
1237 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1238 output_insn (insn, &the_insn);
1239 }
1240
1241 if (need_hi22_p)
1242 {
1243 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1244 | (((need_xor10_p ? ~lower32 : lower32)
1245 >> 10) & 0x3fffff));
1246 the_insn.reloc = (the_insn.exp.X_op != O_constant
1247 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1248 output_insn (insn, &the_insn);
1249 }
1250
1251 if (need_hm10_p)
1252 {
1253 the_insn.opcode = (OR_INSN
1254 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1255 | RD (upper_dstreg)
1256 | IMMED
1257 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1258 the_insn.reloc = (the_insn.exp.X_op != O_constant
1259 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1260 output_insn (insn, &the_insn);
1261 }
1262
1263 if (need_lo10_p)
1264 {
1265 /* FIXME: One nice optimization to do here is to OR the low part
1266 with the highpart if hi22 isn't needed and the low part is
1267 positive. */
1268 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1269 | RD (dstreg)
1270 | IMMED
1271 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1272 the_insn.reloc = (the_insn.exp.X_op != O_constant
1273 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1274 output_insn (insn, &the_insn);
1275 }
1276
1277 /* If we needed to build the upper part, shift it into place. */
1278 if (need_hh22_p || need_hm10_p)
1279 {
1280 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1281 | IMMED | 32);
1282 the_insn.reloc = BFD_RELOC_NONE;
1283 output_insn (insn, &the_insn);
1284 }
1285
1286 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1287 if (need_xor10_p)
1288 {
1289 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1290 | 0x1c00 | (lower32 & 0x3ff));
1291 the_insn.reloc = BFD_RELOC_NONE;
1292 output_insn (insn, &the_insn);
1293 }
1294
1295 /* If we needed to build both upper and lower parts, OR them together. */
1296 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1297 {
1298 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1299 | RD (dstreg));
1300 the_insn.reloc = BFD_RELOC_NONE;
1301 output_insn (insn, &the_insn);
1302 }
1303 }
1304 \f
1305 /* Main entry point to assemble one instruction. */
1306
1307 void
1308 md_assemble (str)
1309 char *str;
1310 {
1311 const struct sparc_opcode *insn;
1312 int special_case;
1313
1314 know (str);
1315 special_case = sparc_ip (str, &insn);
1316 if (insn == NULL)
1317 return;
1318
1319 /* We warn about attempts to put a floating point branch in a delay slot,
1320 unless the delay slot has been annulled. */
1321 if (last_insn != NULL
1322 && (insn->flags & F_FBR) != 0
1323 && (last_insn->flags & F_DELAYED) != 0
1324 /* ??? This test isn't completely accurate. We assume anything with
1325 F_{UNBR,CONDBR,FBR} set is annullable. */
1326 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1327 || (last_opcode & ANNUL) == 0))
1328 as_warn (_("FP branch in delay slot"));
1329
1330 /* SPARC before v9 requires a nop instruction between a floating
1331 point instruction and a floating point branch. We insert one
1332 automatically, with a warning. */
1333 if (max_architecture < SPARC_OPCODE_ARCH_V9
1334 && last_insn != NULL
1335 && (insn->flags & F_FBR) != 0
1336 && (last_insn->flags & F_FLOAT) != 0)
1337 {
1338 struct sparc_it nop_insn;
1339
1340 nop_insn.opcode = NOP_INSN;
1341 nop_insn.reloc = BFD_RELOC_NONE;
1342 output_insn (insn, &nop_insn);
1343 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1344 }
1345
1346 switch (special_case)
1347 {
1348 case SPECIAL_CASE_NONE:
1349 /* Normal insn. */
1350 output_insn (insn, &the_insn);
1351 break;
1352
1353 case SPECIAL_CASE_SETSW:
1354 synthetize_setsw (insn);
1355 break;
1356
1357 case SPECIAL_CASE_SET:
1358 synthetize_setuw (insn);
1359 break;
1360
1361 case SPECIAL_CASE_SETX:
1362 synthetize_setx (insn);
1363 break;
1364
1365 case SPECIAL_CASE_FDIV:
1366 {
1367 int rd = (the_insn.opcode >> 25) & 0x1f;
1368
1369 output_insn (insn, &the_insn);
1370
1371 /* According to information leaked from Sun, the "fdiv" instructions
1372 on early SPARC machines would produce incorrect results sometimes.
1373 The workaround is to add an fmovs of the destination register to
1374 itself just after the instruction. This was true on machines
1375 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1376 assert (the_insn.reloc == BFD_RELOC_NONE);
1377 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1378 output_insn (insn, &the_insn);
1379 return;
1380 }
1381
1382 default:
1383 as_fatal (_("failed special case insn sanity check"));
1384 }
1385 }
1386
1387 /* Subroutine of md_assemble to do the actual parsing. */
1388
1389 static int
1390 sparc_ip (str, pinsn)
1391 char *str;
1392 const struct sparc_opcode **pinsn;
1393 {
1394 char *error_message = "";
1395 char *s;
1396 const char *args;
1397 char c;
1398 const struct sparc_opcode *insn;
1399 char *argsStart;
1400 unsigned long opcode;
1401 unsigned int mask = 0;
1402 int match = 0;
1403 int comma = 0;
1404 int v9_arg_p;
1405 int special_case = SPECIAL_CASE_NONE;
1406
1407 s = str;
1408 if (ISLOWER (*s))
1409 {
1410 do
1411 ++s;
1412 while (ISLOWER (*s) || ISDIGIT (*s));
1413 }
1414
1415 switch (*s)
1416 {
1417 case '\0':
1418 break;
1419
1420 case ',':
1421 comma = 1;
1422 /* Fall through. */
1423
1424 case ' ':
1425 *s++ = '\0';
1426 break;
1427
1428 default:
1429 as_bad (_("Unknown opcode: `%s'"), str);
1430 *pinsn = NULL;
1431 return special_case;
1432 }
1433 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1434 *pinsn = insn;
1435 if (insn == NULL)
1436 {
1437 as_bad (_("Unknown opcode: `%s'"), str);
1438 return special_case;
1439 }
1440 if (comma)
1441 {
1442 *--s = ',';
1443 }
1444
1445 argsStart = s;
1446 for (;;)
1447 {
1448 opcode = insn->match;
1449 memset (&the_insn, '\0', sizeof (the_insn));
1450 the_insn.reloc = BFD_RELOC_NONE;
1451 v9_arg_p = 0;
1452
1453 /* Build the opcode, checking as we go to make sure that the
1454 operands match. */
1455 for (args = insn->args;; ++args)
1456 {
1457 switch (*args)
1458 {
1459 case 'K':
1460 {
1461 int kmask = 0;
1462
1463 /* Parse a series of masks. */
1464 if (*s == '#')
1465 {
1466 while (*s == '#')
1467 {
1468 int mask;
1469
1470 if (! parse_keyword_arg (sparc_encode_membar, &s,
1471 &mask))
1472 {
1473 error_message = _(": invalid membar mask name");
1474 goto error;
1475 }
1476 kmask |= mask;
1477 while (*s == ' ')
1478 ++s;
1479 if (*s == '|' || *s == '+')
1480 ++s;
1481 while (*s == ' ')
1482 ++s;
1483 }
1484 }
1485 else
1486 {
1487 if (! parse_const_expr_arg (&s, &kmask))
1488 {
1489 error_message = _(": invalid membar mask expression");
1490 goto error;
1491 }
1492 if (kmask < 0 || kmask > 127)
1493 {
1494 error_message = _(": invalid membar mask number");
1495 goto error;
1496 }
1497 }
1498
1499 opcode |= MEMBAR (kmask);
1500 continue;
1501 }
1502
1503 case '3':
1504 {
1505 int smask = 0;
1506
1507 if (! parse_const_expr_arg (&s, &smask))
1508 {
1509 error_message = _(": invalid siam mode expression");
1510 goto error;
1511 }
1512 if (smask < 0 || smask > 7)
1513 {
1514 error_message = _(": invalid siam mode number");
1515 goto error;
1516 }
1517 opcode |= smask;
1518 continue;
1519 }
1520
1521 case '*':
1522 {
1523 int fcn = 0;
1524
1525 /* Parse a prefetch function. */
1526 if (*s == '#')
1527 {
1528 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1529 {
1530 error_message = _(": invalid prefetch function name");
1531 goto error;
1532 }
1533 }
1534 else
1535 {
1536 if (! parse_const_expr_arg (&s, &fcn))
1537 {
1538 error_message = _(": invalid prefetch function expression");
1539 goto error;
1540 }
1541 if (fcn < 0 || fcn > 31)
1542 {
1543 error_message = _(": invalid prefetch function number");
1544 goto error;
1545 }
1546 }
1547 opcode |= RD (fcn);
1548 continue;
1549 }
1550
1551 case '!':
1552 case '?':
1553 /* Parse a sparc64 privileged register. */
1554 if (*s == '%')
1555 {
1556 struct priv_reg_entry *p = priv_reg_table;
1557 unsigned int len = 9999999; /* Init to make gcc happy. */
1558
1559 s += 1;
1560 while (p->name[0] > s[0])
1561 p++;
1562 while (p->name[0] == s[0])
1563 {
1564 len = strlen (p->name);
1565 if (strncmp (p->name, s, len) == 0)
1566 break;
1567 p++;
1568 }
1569 if (p->name[0] != s[0])
1570 {
1571 error_message = _(": unrecognizable privileged register");
1572 goto error;
1573 }
1574 if (*args == '?')
1575 opcode |= (p->regnum << 14);
1576 else
1577 opcode |= (p->regnum << 25);
1578 s += len;
1579 continue;
1580 }
1581 else
1582 {
1583 error_message = _(": unrecognizable privileged register");
1584 goto error;
1585 }
1586
1587 case '$':
1588 case '%':
1589 /* Parse a sparc64 hyperprivileged register. */
1590 if (*s == '%')
1591 {
1592 struct priv_reg_entry *p = hpriv_reg_table;
1593 unsigned int len = 9999999; /* Init to make gcc happy. */
1594
1595 s += 1;
1596 while (p->name[0] > s[0])
1597 p++;
1598 while (p->name[0] == s[0])
1599 {
1600 len = strlen (p->name);
1601 if (strncmp (p->name, s, len) == 0)
1602 break;
1603 p++;
1604 }
1605 if (p->name[0] != s[0])
1606 {
1607 error_message = _(": unrecognizable hyperprivileged register");
1608 goto error;
1609 }
1610 if (*args == '$')
1611 opcode |= (p->regnum << 14);
1612 else
1613 opcode |= (p->regnum << 25);
1614 s += len;
1615 continue;
1616 }
1617 else
1618 {
1619 error_message = _(": unrecognizable hyperprivileged register");
1620 goto error;
1621 }
1622
1623 case '_':
1624 case '/':
1625 /* Parse a v9a/v9b ancillary state register. */
1626 if (*s == '%')
1627 {
1628 struct priv_reg_entry *p = v9a_asr_table;
1629 unsigned int len = 9999999; /* Init to make gcc happy. */
1630
1631 s += 1;
1632 while (p->name[0] > s[0])
1633 p++;
1634 while (p->name[0] == s[0])
1635 {
1636 len = strlen (p->name);
1637 if (strncmp (p->name, s, len) == 0)
1638 break;
1639 p++;
1640 }
1641 if (p->name[0] != s[0])
1642 {
1643 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1644 goto error;
1645 }
1646 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1647 {
1648 error_message = _(": rd on write only ancillary state register");
1649 goto error;
1650 }
1651 if (p->regnum >= 24
1652 && (insn->architecture
1653 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
1654 {
1655 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1656 error_message = _(": unrecognizable v9a ancillary state register");
1657 goto error;
1658 }
1659 if (*args == '/')
1660 opcode |= (p->regnum << 14);
1661 else
1662 opcode |= (p->regnum << 25);
1663 s += len;
1664 continue;
1665 }
1666 else
1667 {
1668 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1669 goto error;
1670 }
1671
1672 case 'M':
1673 case 'm':
1674 if (strncmp (s, "%asr", 4) == 0)
1675 {
1676 s += 4;
1677
1678 if (ISDIGIT (*s))
1679 {
1680 long num = 0;
1681
1682 while (ISDIGIT (*s))
1683 {
1684 num = num * 10 + *s - '0';
1685 ++s;
1686 }
1687
1688 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1689 {
1690 if (num < 16 || 31 < num)
1691 {
1692 error_message = _(": asr number must be between 16 and 31");
1693 goto error;
1694 }
1695 }
1696 else
1697 {
1698 if (num < 0 || 31 < num)
1699 {
1700 error_message = _(": asr number must be between 0 and 31");
1701 goto error;
1702 }
1703 }
1704
1705 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1706 continue;
1707 }
1708 else
1709 {
1710 error_message = _(": expecting %asrN");
1711 goto error;
1712 }
1713 } /* if %asr */
1714 break;
1715
1716 case 'I':
1717 the_insn.reloc = BFD_RELOC_SPARC_11;
1718 goto immediate;
1719
1720 case 'j':
1721 the_insn.reloc = BFD_RELOC_SPARC_10;
1722 goto immediate;
1723
1724 case 'X':
1725 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1726 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1727 the_insn.reloc = BFD_RELOC_SPARC_5;
1728 else
1729 the_insn.reloc = BFD_RELOC_SPARC13;
1730 /* These fields are unsigned, but for upward compatibility,
1731 allow negative values as well. */
1732 goto immediate;
1733
1734 case 'Y':
1735 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1736 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1737 the_insn.reloc = BFD_RELOC_SPARC_6;
1738 else
1739 the_insn.reloc = BFD_RELOC_SPARC13;
1740 /* These fields are unsigned, but for upward compatibility,
1741 allow negative values as well. */
1742 goto immediate;
1743
1744 case 'k':
1745 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1746 the_insn.pcrel = 1;
1747 goto immediate;
1748
1749 case 'G':
1750 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1751 the_insn.pcrel = 1;
1752 goto immediate;
1753
1754 case 'N':
1755 if (*s == 'p' && s[1] == 'n')
1756 {
1757 s += 2;
1758 continue;
1759 }
1760 break;
1761
1762 case 'T':
1763 if (*s == 'p' && s[1] == 't')
1764 {
1765 s += 2;
1766 continue;
1767 }
1768 break;
1769
1770 case 'z':
1771 if (*s == ' ')
1772 {
1773 ++s;
1774 }
1775 if (strncmp (s, "%icc", 4) == 0)
1776 {
1777 s += 4;
1778 continue;
1779 }
1780 break;
1781
1782 case 'Z':
1783 if (*s == ' ')
1784 {
1785 ++s;
1786 }
1787 if (strncmp (s, "%xcc", 4) == 0)
1788 {
1789 s += 4;
1790 continue;
1791 }
1792 break;
1793
1794 case '6':
1795 if (*s == ' ')
1796 {
1797 ++s;
1798 }
1799 if (strncmp (s, "%fcc0", 5) == 0)
1800 {
1801 s += 5;
1802 continue;
1803 }
1804 break;
1805
1806 case '7':
1807 if (*s == ' ')
1808 {
1809 ++s;
1810 }
1811 if (strncmp (s, "%fcc1", 5) == 0)
1812 {
1813 s += 5;
1814 continue;
1815 }
1816 break;
1817
1818 case '8':
1819 if (*s == ' ')
1820 {
1821 ++s;
1822 }
1823 if (strncmp (s, "%fcc2", 5) == 0)
1824 {
1825 s += 5;
1826 continue;
1827 }
1828 break;
1829
1830 case '9':
1831 if (*s == ' ')
1832 {
1833 ++s;
1834 }
1835 if (strncmp (s, "%fcc3", 5) == 0)
1836 {
1837 s += 5;
1838 continue;
1839 }
1840 break;
1841
1842 case 'P':
1843 if (strncmp (s, "%pc", 3) == 0)
1844 {
1845 s += 3;
1846 continue;
1847 }
1848 break;
1849
1850 case 'W':
1851 if (strncmp (s, "%tick", 5) == 0)
1852 {
1853 s += 5;
1854 continue;
1855 }
1856 break;
1857
1858 case '\0': /* End of args. */
1859 if (s[0] == ',' && s[1] == '%')
1860 {
1861 static const struct tls_ops {
1862 /* The name as it appears in assembler. */
1863 char *name;
1864 /* strlen (name), precomputed for speed */
1865 int len;
1866 /* The reloc this pseudo-op translates to. */
1867 int reloc;
1868 /* 1 if call. */
1869 int call;
1870 } tls_ops[] = {
1871 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 },
1872 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 },
1873 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 },
1874 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 },
1875 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 },
1876 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 },
1877 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 },
1878 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 }
1879 };
1880 const struct tls_ops *o;
1881 char *s1;
1882 int npar = 0;
1883
1884 for (o = tls_ops; o->name; o++)
1885 if (strncmp (s + 2, o->name, o->len) == 0)
1886 break;
1887 if (o->name == NULL)
1888 break;
1889
1890 if (s[o->len + 2] != '(')
1891 {
1892 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
1893 return special_case;
1894 }
1895
1896 if (! o->call && the_insn.reloc != BFD_RELOC_NONE)
1897 {
1898 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
1899 o->name);
1900 return special_case;
1901 }
1902
1903 if (o->call
1904 && (the_insn.reloc != BFD_RELOC_32_PCREL_S2
1905 || the_insn.exp.X_add_number != 0
1906 || the_insn.exp.X_add_symbol
1907 != symbol_find_or_make ("__tls_get_addr")))
1908 {
1909 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
1910 o->name);
1911 return special_case;
1912 }
1913
1914 the_insn.reloc = o->reloc;
1915 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
1916 s += o->len + 3;
1917
1918 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
1919 if (*s1 == '(')
1920 npar++;
1921 else if (*s1 == ')')
1922 {
1923 if (!npar)
1924 break;
1925 npar--;
1926 }
1927
1928 if (*s1 != ')')
1929 {
1930 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
1931 return special_case;
1932 }
1933
1934 *s1 = '\0';
1935 (void) get_expression (s);
1936 *s1 = ')';
1937 s = s1 + 1;
1938 }
1939 if (*s == '\0')
1940 match = 1;
1941 break;
1942
1943 case '+':
1944 if (*s == '+')
1945 {
1946 ++s;
1947 continue;
1948 }
1949 if (*s == '-')
1950 {
1951 continue;
1952 }
1953 break;
1954
1955 case '[': /* These must match exactly. */
1956 case ']':
1957 case ',':
1958 case ' ':
1959 if (*s++ == *args)
1960 continue;
1961 break;
1962
1963 case '#': /* Must be at least one digit. */
1964 if (ISDIGIT (*s++))
1965 {
1966 while (ISDIGIT (*s))
1967 {
1968 ++s;
1969 }
1970 continue;
1971 }
1972 break;
1973
1974 case 'C': /* Coprocessor state register. */
1975 if (strncmp (s, "%csr", 4) == 0)
1976 {
1977 s += 4;
1978 continue;
1979 }
1980 break;
1981
1982 case 'b': /* Next operand is a coprocessor register. */
1983 case 'c':
1984 case 'D':
1985 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s))
1986 {
1987 mask = *s++;
1988 if (ISDIGIT (*s))
1989 {
1990 mask = 10 * (mask - '0') + (*s++ - '0');
1991 if (mask >= 32)
1992 {
1993 break;
1994 }
1995 }
1996 else
1997 {
1998 mask -= '0';
1999 }
2000 switch (*args)
2001 {
2002
2003 case 'b':
2004 opcode |= mask << 14;
2005 continue;
2006
2007 case 'c':
2008 opcode |= mask;
2009 continue;
2010
2011 case 'D':
2012 opcode |= mask << 25;
2013 continue;
2014 }
2015 }
2016 break;
2017
2018 case 'r': /* next operand must be a register */
2019 case 'O':
2020 case '1':
2021 case '2':
2022 case 'd':
2023 if (*s++ == '%')
2024 {
2025 switch (c = *s++)
2026 {
2027
2028 case 'f': /* frame pointer */
2029 if (*s++ == 'p')
2030 {
2031 mask = 0x1e;
2032 break;
2033 }
2034 goto error;
2035
2036 case 'g': /* global register */
2037 c = *s++;
2038 if (isoctal (c))
2039 {
2040 mask = c - '0';
2041 break;
2042 }
2043 goto error;
2044
2045 case 'i': /* in register */
2046 c = *s++;
2047 if (isoctal (c))
2048 {
2049 mask = c - '0' + 24;
2050 break;
2051 }
2052 goto error;
2053
2054 case 'l': /* local register */
2055 c = *s++;
2056 if (isoctal (c))
2057 {
2058 mask = (c - '0' + 16);
2059 break;
2060 }
2061 goto error;
2062
2063 case 'o': /* out register */
2064 c = *s++;
2065 if (isoctal (c))
2066 {
2067 mask = (c - '0' + 8);
2068 break;
2069 }
2070 goto error;
2071
2072 case 's': /* stack pointer */
2073 if (*s++ == 'p')
2074 {
2075 mask = 0xe;
2076 break;
2077 }
2078 goto error;
2079
2080 case 'r': /* any register */
2081 if (!ISDIGIT ((c = *s++)))
2082 {
2083 goto error;
2084 }
2085 /* FALLTHROUGH */
2086 case '0':
2087 case '1':
2088 case '2':
2089 case '3':
2090 case '4':
2091 case '5':
2092 case '6':
2093 case '7':
2094 case '8':
2095 case '9':
2096 if (ISDIGIT (*s))
2097 {
2098 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
2099 {
2100 goto error;
2101 }
2102 }
2103 else
2104 {
2105 c -= '0';
2106 }
2107 mask = c;
2108 break;
2109
2110 default:
2111 goto error;
2112 }
2113
2114 if ((mask & ~1) == 2 && sparc_arch_size == 64
2115 && no_undeclared_regs && ! globals[mask])
2116 as_bad (_("detected global register use not covered by .register pseudo-op"));
2117
2118 /* Got the register, now figure out where
2119 it goes in the opcode. */
2120 switch (*args)
2121 {
2122 case '1':
2123 opcode |= mask << 14;
2124 continue;
2125
2126 case '2':
2127 opcode |= mask;
2128 continue;
2129
2130 case 'd':
2131 opcode |= mask << 25;
2132 continue;
2133
2134 case 'r':
2135 opcode |= (mask << 25) | (mask << 14);
2136 continue;
2137
2138 case 'O':
2139 opcode |= (mask << 25) | (mask << 0);
2140 continue;
2141 }
2142 }
2143 break;
2144
2145 case 'e': /* next operand is a floating point register */
2146 case 'v':
2147 case 'V':
2148
2149 case 'f':
2150 case 'B':
2151 case 'R':
2152
2153 case 'g':
2154 case 'H':
2155 case 'J':
2156 {
2157 char format;
2158
2159 if (*s++ == '%'
2160 && ((format = *s) == 'f')
2161 && ISDIGIT (*++s))
2162 {
2163 for (mask = 0; ISDIGIT (*s); ++s)
2164 {
2165 mask = 10 * mask + (*s - '0');
2166 } /* read the number */
2167
2168 if ((*args == 'v'
2169 || *args == 'B'
2170 || *args == 'H')
2171 && (mask & 1))
2172 {
2173 break;
2174 } /* register must be even numbered */
2175
2176 if ((*args == 'V'
2177 || *args == 'R'
2178 || *args == 'J')
2179 && (mask & 3))
2180 {
2181 break;
2182 } /* register must be multiple of 4 */
2183
2184 if (mask >= 64)
2185 {
2186 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2187 error_message = _(": There are only 64 f registers; [0-63]");
2188 else
2189 error_message = _(": There are only 32 f registers; [0-31]");
2190 goto error;
2191 } /* on error */
2192 else if (mask >= 32)
2193 {
2194 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2195 {
2196 if (*args == 'e' || *args == 'f' || *args == 'g')
2197 {
2198 error_message
2199 = _(": There are only 32 single precision f registers; [0-31]");
2200 goto error;
2201 }
2202 v9_arg_p = 1;
2203 mask -= 31; /* wrap high bit */
2204 }
2205 else
2206 {
2207 error_message = _(": There are only 32 f registers; [0-31]");
2208 goto error;
2209 }
2210 }
2211 }
2212 else
2213 {
2214 break;
2215 } /* if not an 'f' register. */
2216
2217 switch (*args)
2218 {
2219 case 'v':
2220 case 'V':
2221 case 'e':
2222 opcode |= RS1 (mask);
2223 continue;
2224
2225 case 'f':
2226 case 'B':
2227 case 'R':
2228 opcode |= RS2 (mask);
2229 continue;
2230
2231 case 'g':
2232 case 'H':
2233 case 'J':
2234 opcode |= RD (mask);
2235 continue;
2236 } /* Pack it in. */
2237
2238 know (0);
2239 break;
2240 } /* float arg */
2241
2242 case 'F':
2243 if (strncmp (s, "%fsr", 4) == 0)
2244 {
2245 s += 4;
2246 continue;
2247 }
2248 break;
2249
2250 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2251 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
2252 goto immediate;
2253
2254 case 'l': /* 22 bit PC relative immediate */
2255 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2256 the_insn.pcrel = 1;
2257 goto immediate;
2258
2259 case 'L': /* 30 bit immediate */
2260 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2261 the_insn.pcrel = 1;
2262 goto immediate;
2263
2264 case 'h':
2265 case 'n': /* 22 bit immediate */
2266 the_insn.reloc = BFD_RELOC_SPARC22;
2267 goto immediate;
2268
2269 case 'i': /* 13 bit immediate */
2270 the_insn.reloc = BFD_RELOC_SPARC13;
2271
2272 /* fallthrough */
2273
2274 immediate:
2275 if (*s == ' ')
2276 s++;
2277
2278 {
2279 char *s1;
2280 char *op_arg = NULL;
2281 static expressionS op_exp;
2282 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2283
2284 /* Check for %hi, etc. */
2285 if (*s == '%')
2286 {
2287 static const struct ops {
2288 /* The name as it appears in assembler. */
2289 char *name;
2290 /* strlen (name), precomputed for speed */
2291 int len;
2292 /* The reloc this pseudo-op translates to. */
2293 int reloc;
2294 /* Non-zero if for v9 only. */
2295 int v9_p;
2296 /* Non-zero if can be used in pc-relative contexts. */
2297 int pcrel_p;/*FIXME:wip*/
2298 } ops[] = {
2299 /* hix/lox must appear before hi/lo so %hix won't be
2300 mistaken for %hi. */
2301 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2302 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2303 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2304 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
2305 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2306 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2307 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2308 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2309 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2310 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2311 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2312 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
2313 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 },
2314 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 },
2315 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 },
2316 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 },
2317 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0,
2318 0 },
2319 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0,
2320 0 },
2321 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 },
2322 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 },
2323 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 },
2324 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 },
2325 { NULL, 0, 0, 0, 0 }
2326 };
2327 const struct ops *o;
2328
2329 for (o = ops; o->name; o++)
2330 if (strncmp (s + 1, o->name, o->len) == 0)
2331 break;
2332 if (o->name == NULL)
2333 break;
2334
2335 if (s[o->len + 1] != '(')
2336 {
2337 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2338 return special_case;
2339 }
2340
2341 op_arg = o->name;
2342 the_insn.reloc = o->reloc;
2343 s += o->len + 2;
2344 v9_arg_p = o->v9_p;
2345 }
2346
2347 /* Note that if the get_expression() fails, we will still
2348 have created U entries in the symbol table for the
2349 'symbols' in the input string. Try not to create U
2350 symbols for registers, etc. */
2351
2352 /* This stuff checks to see if the expression ends in
2353 +%reg. If it does, it removes the register from
2354 the expression, and re-sets 's' to point to the
2355 right place. */
2356
2357 if (op_arg)
2358 {
2359 int npar = 0;
2360
2361 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2362 if (*s1 == '(')
2363 npar++;
2364 else if (*s1 == ')')
2365 {
2366 if (!npar)
2367 break;
2368 npar--;
2369 }
2370
2371 if (*s1 != ')')
2372 {
2373 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
2374 return special_case;
2375 }
2376
2377 *s1 = '\0';
2378 (void) get_expression (s);
2379 *s1 = ')';
2380 s = s1 + 1;
2381 if (*s == ',' || *s == ']' || !*s)
2382 continue;
2383 if (*s != '+' && *s != '-')
2384 {
2385 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
2386 return special_case;
2387 }
2388 *s1 = '0';
2389 s = s1;
2390 op_exp = the_insn.exp;
2391 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2392 }
2393
2394 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2395 ;
2396
2397 if (s1 != s && ISDIGIT (s1[-1]))
2398 {
2399 if (s1[-2] == '%' && s1[-3] == '+')
2400 s1 -= 3;
2401 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2402 s1 -= 4;
2403 else
2404 s1 = NULL;
2405 if (s1)
2406 {
2407 *s1 = '\0';
2408 if (op_arg && s1 == s + 1)
2409 the_insn.exp.X_op = O_absent;
2410 else
2411 (void) get_expression (s);
2412 *s1 = '+';
2413 if (op_arg)
2414 *s = ')';
2415 s = s1;
2416 }
2417 }
2418 else
2419 s1 = NULL;
2420
2421 if (!s1)
2422 {
2423 (void) get_expression (s);
2424 if (op_arg)
2425 *s = ')';
2426 s = expr_end;
2427 }
2428
2429 if (op_arg)
2430 {
2431 the_insn.exp2 = the_insn.exp;
2432 the_insn.exp = op_exp;
2433 if (the_insn.exp2.X_op == O_absent)
2434 the_insn.exp2.X_op = O_illegal;
2435 else if (the_insn.exp.X_op == O_absent)
2436 {
2437 the_insn.exp = the_insn.exp2;
2438 the_insn.exp2.X_op = O_illegal;
2439 }
2440 else if (the_insn.exp.X_op == O_constant)
2441 {
2442 valueT val = the_insn.exp.X_add_number;
2443 switch (the_insn.reloc)
2444 {
2445 default:
2446 break;
2447
2448 case BFD_RELOC_SPARC_HH22:
2449 val = BSR (val, 32);
2450 /* Fall through. */
2451
2452 case BFD_RELOC_SPARC_LM22:
2453 case BFD_RELOC_HI22:
2454 val = (val >> 10) & 0x3fffff;
2455 break;
2456
2457 case BFD_RELOC_SPARC_HM10:
2458 val = BSR (val, 32);
2459 /* Fall through. */
2460
2461 case BFD_RELOC_LO10:
2462 val &= 0x3ff;
2463 break;
2464
2465 case BFD_RELOC_SPARC_H44:
2466 val >>= 22;
2467 val &= 0x3fffff;
2468 break;
2469
2470 case BFD_RELOC_SPARC_M44:
2471 val >>= 12;
2472 val &= 0x3ff;
2473 break;
2474
2475 case BFD_RELOC_SPARC_L44:
2476 val &= 0xfff;
2477 break;
2478
2479 case BFD_RELOC_SPARC_HIX22:
2480 val = ~val;
2481 val = (val >> 10) & 0x3fffff;
2482 break;
2483
2484 case BFD_RELOC_SPARC_LOX10:
2485 val = (val & 0x3ff) | 0x1c00;
2486 break;
2487 }
2488 the_insn.exp = the_insn.exp2;
2489 the_insn.exp.X_add_number += val;
2490 the_insn.exp2.X_op = O_illegal;
2491 the_insn.reloc = old_reloc;
2492 }
2493 else if (the_insn.exp2.X_op != O_constant)
2494 {
2495 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
2496 return special_case;
2497 }
2498 else
2499 {
2500 if (old_reloc != BFD_RELOC_SPARC13
2501 || the_insn.reloc != BFD_RELOC_LO10
2502 || sparc_arch_size != 64
2503 || sparc_pic_code)
2504 {
2505 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
2506 return special_case;
2507 }
2508 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
2509 }
2510 }
2511 }
2512 /* Check for constants that don't require emitting a reloc. */
2513 if (the_insn.exp.X_op == O_constant
2514 && the_insn.exp.X_add_symbol == 0
2515 && the_insn.exp.X_op_symbol == 0)
2516 {
2517 /* For pc-relative call instructions, we reject
2518 constants to get better code. */
2519 if (the_insn.pcrel
2520 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2521 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2522 {
2523 error_message = _(": PC-relative operand can't be a constant");
2524 goto error;
2525 }
2526
2527 if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22
2528 && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64)
2529 {
2530 error_message = _(": TLS operand can't be a constant");
2531 goto error;
2532 }
2533
2534 /* Constants that won't fit are checked in md_apply_fix
2535 and bfd_install_relocation.
2536 ??? It would be preferable to install the constants
2537 into the insn here and save having to create a fixS
2538 for each one. There already exists code to handle
2539 all the various cases (e.g. in md_apply_fix and
2540 bfd_install_relocation) so duplicating all that code
2541 here isn't right. */
2542 }
2543
2544 continue;
2545
2546 case 'a':
2547 if (*s++ == 'a')
2548 {
2549 opcode |= ANNUL;
2550 continue;
2551 }
2552 break;
2553
2554 case 'A':
2555 {
2556 int asi = 0;
2557
2558 /* Parse an asi. */
2559 if (*s == '#')
2560 {
2561 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2562 {
2563 error_message = _(": invalid ASI name");
2564 goto error;
2565 }
2566 }
2567 else
2568 {
2569 if (! parse_const_expr_arg (&s, &asi))
2570 {
2571 error_message = _(": invalid ASI expression");
2572 goto error;
2573 }
2574 if (asi < 0 || asi > 255)
2575 {
2576 error_message = _(": invalid ASI number");
2577 goto error;
2578 }
2579 }
2580 opcode |= ASI (asi);
2581 continue;
2582 } /* Alternate space. */
2583
2584 case 'p':
2585 if (strncmp (s, "%psr", 4) == 0)
2586 {
2587 s += 4;
2588 continue;
2589 }
2590 break;
2591
2592 case 'q': /* Floating point queue. */
2593 if (strncmp (s, "%fq", 3) == 0)
2594 {
2595 s += 3;
2596 continue;
2597 }
2598 break;
2599
2600 case 'Q': /* Coprocessor queue. */
2601 if (strncmp (s, "%cq", 3) == 0)
2602 {
2603 s += 3;
2604 continue;
2605 }
2606 break;
2607
2608 case 'S':
2609 if (strcmp (str, "set") == 0
2610 || strcmp (str, "setuw") == 0)
2611 {
2612 special_case = SPECIAL_CASE_SET;
2613 continue;
2614 }
2615 else if (strcmp (str, "setsw") == 0)
2616 {
2617 special_case = SPECIAL_CASE_SETSW;
2618 continue;
2619 }
2620 else if (strcmp (str, "setx") == 0)
2621 {
2622 special_case = SPECIAL_CASE_SETX;
2623 continue;
2624 }
2625 else if (strncmp (str, "fdiv", 4) == 0)
2626 {
2627 special_case = SPECIAL_CASE_FDIV;
2628 continue;
2629 }
2630 break;
2631
2632 case 'o':
2633 if (strncmp (s, "%asi", 4) != 0)
2634 break;
2635 s += 4;
2636 continue;
2637
2638 case 's':
2639 if (strncmp (s, "%fprs", 5) != 0)
2640 break;
2641 s += 5;
2642 continue;
2643
2644 case 'E':
2645 if (strncmp (s, "%ccr", 4) != 0)
2646 break;
2647 s += 4;
2648 continue;
2649
2650 case 't':
2651 if (strncmp (s, "%tbr", 4) != 0)
2652 break;
2653 s += 4;
2654 continue;
2655
2656 case 'w':
2657 if (strncmp (s, "%wim", 4) != 0)
2658 break;
2659 s += 4;
2660 continue;
2661
2662 case 'x':
2663 {
2664 char *push = input_line_pointer;
2665 expressionS e;
2666
2667 input_line_pointer = s;
2668 expression (&e);
2669 if (e.X_op == O_constant)
2670 {
2671 int n = e.X_add_number;
2672 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2673 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2674 else
2675 opcode |= e.X_add_number << 5;
2676 }
2677 else
2678 as_bad (_("non-immediate OPF operand, ignored"));
2679 s = input_line_pointer;
2680 input_line_pointer = push;
2681 continue;
2682 }
2683
2684 case 'y':
2685 if (strncmp (s, "%y", 2) != 0)
2686 break;
2687 s += 2;
2688 continue;
2689
2690 case 'u':
2691 case 'U':
2692 {
2693 /* Parse a sparclet cpreg. */
2694 int cpreg;
2695 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2696 {
2697 error_message = _(": invalid cpreg name");
2698 goto error;
2699 }
2700 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2701 continue;
2702 }
2703
2704 default:
2705 as_fatal (_("failed sanity check."));
2706 } /* switch on arg code. */
2707
2708 /* Break out of for() loop. */
2709 break;
2710 } /* For each arg that we expect. */
2711
2712 error:
2713 if (match == 0)
2714 {
2715 /* Args don't match. */
2716 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2717 && (insn->name == insn[1].name
2718 || !strcmp (insn->name, insn[1].name)))
2719 {
2720 ++insn;
2721 s = argsStart;
2722 continue;
2723 }
2724 else
2725 {
2726 as_bad (_("Illegal operands%s"), error_message);
2727 return special_case;
2728 }
2729 }
2730 else
2731 {
2732 /* We have a match. Now see if the architecture is OK. */
2733 int needed_arch_mask = insn->architecture;
2734
2735 if (v9_arg_p)
2736 {
2737 needed_arch_mask &=
2738 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
2739 if (! needed_arch_mask)
2740 needed_arch_mask =
2741 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
2742 }
2743
2744 if (needed_arch_mask
2745 & SPARC_OPCODE_SUPPORTED (current_architecture))
2746 /* OK. */
2747 ;
2748 /* Can we bump up the architecture? */
2749 else if (needed_arch_mask
2750 & SPARC_OPCODE_SUPPORTED (max_architecture))
2751 {
2752 enum sparc_opcode_arch_val needed_architecture =
2753 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2754 & needed_arch_mask);
2755
2756 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2757 if (warn_on_bump
2758 && needed_architecture > warn_after_architecture)
2759 {
2760 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2761 sparc_opcode_archs[current_architecture].name,
2762 sparc_opcode_archs[needed_architecture].name,
2763 str);
2764 warn_after_architecture = needed_architecture;
2765 }
2766 current_architecture = needed_architecture;
2767 }
2768 /* Conflict. */
2769 /* ??? This seems to be a bit fragile. What if the next entry in
2770 the opcode table is the one we want and it is supported?
2771 It is possible to arrange the table today so that this can't
2772 happen but what about tomorrow? */
2773 else
2774 {
2775 int arch, printed_one_p = 0;
2776 char *p;
2777 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2778
2779 /* Create a list of the architectures that support the insn. */
2780 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
2781 p = required_archs;
2782 arch = sparc_ffs (needed_arch_mask);
2783 while ((1 << arch) <= needed_arch_mask)
2784 {
2785 if ((1 << arch) & needed_arch_mask)
2786 {
2787 if (printed_one_p)
2788 *p++ = '|';
2789 strcpy (p, sparc_opcode_archs[arch].name);
2790 p += strlen (p);
2791 printed_one_p = 1;
2792 }
2793 ++arch;
2794 }
2795
2796 as_bad (_("Architecture mismatch on \"%s\"."), str);
2797 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2798 required_archs,
2799 sparc_opcode_archs[max_architecture].name);
2800 return special_case;
2801 }
2802 } /* If no match. */
2803
2804 break;
2805 } /* Forever looking for a match. */
2806
2807 the_insn.opcode = opcode;
2808 return special_case;
2809 }
2810
2811 /* Parse an argument that can be expressed as a keyword.
2812 (eg: #StoreStore or %ccfr).
2813 The result is a boolean indicating success.
2814 If successful, INPUT_POINTER is updated. */
2815
2816 static int
2817 parse_keyword_arg (lookup_fn, input_pointerP, valueP)
2818 int (*lookup_fn) PARAMS ((const char *));
2819 char **input_pointerP;
2820 int *valueP;
2821 {
2822 int value;
2823 char c, *p, *q;
2824
2825 p = *input_pointerP;
2826 for (q = p + (*p == '#' || *p == '%');
2827 ISALNUM (*q) || *q == '_';
2828 ++q)
2829 continue;
2830 c = *q;
2831 *q = 0;
2832 value = (*lookup_fn) (p);
2833 *q = c;
2834 if (value == -1)
2835 return 0;
2836 *valueP = value;
2837 *input_pointerP = q;
2838 return 1;
2839 }
2840
2841 /* Parse an argument that is a constant expression.
2842 The result is a boolean indicating success. */
2843
2844 static int
2845 parse_const_expr_arg (input_pointerP, valueP)
2846 char **input_pointerP;
2847 int *valueP;
2848 {
2849 char *save = input_line_pointer;
2850 expressionS exp;
2851
2852 input_line_pointer = *input_pointerP;
2853 /* The next expression may be something other than a constant
2854 (say if we're not processing the right variant of the insn).
2855 Don't call expression unless we're sure it will succeed as it will
2856 signal an error (which we want to defer until later). */
2857 /* FIXME: It might be better to define md_operand and have it recognize
2858 things like %asi, etc. but continuing that route through to the end
2859 is a lot of work. */
2860 if (*input_line_pointer == '%')
2861 {
2862 input_line_pointer = save;
2863 return 0;
2864 }
2865 expression (&exp);
2866 *input_pointerP = input_line_pointer;
2867 input_line_pointer = save;
2868 if (exp.X_op != O_constant)
2869 return 0;
2870 *valueP = exp.X_add_number;
2871 return 1;
2872 }
2873
2874 /* Subroutine of sparc_ip to parse an expression. */
2875
2876 static int
2877 get_expression (str)
2878 char *str;
2879 {
2880 char *save_in;
2881 segT seg;
2882
2883 save_in = input_line_pointer;
2884 input_line_pointer = str;
2885 seg = expression (&the_insn.exp);
2886 if (seg != absolute_section
2887 && seg != text_section
2888 && seg != data_section
2889 && seg != bss_section
2890 && seg != undefined_section)
2891 {
2892 the_insn.error = _("bad segment");
2893 expr_end = input_line_pointer;
2894 input_line_pointer = save_in;
2895 return 1;
2896 }
2897 expr_end = input_line_pointer;
2898 input_line_pointer = save_in;
2899 return 0;
2900 }
2901
2902 /* Subroutine of md_assemble to output one insn. */
2903
2904 static void
2905 output_insn (insn, the_insn)
2906 const struct sparc_opcode *insn;
2907 struct sparc_it *the_insn;
2908 {
2909 char *toP = frag_more (4);
2910
2911 /* Put out the opcode. */
2912 if (INSN_BIG_ENDIAN)
2913 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
2914 else
2915 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
2916
2917 /* Put out the symbol-dependent stuff. */
2918 if (the_insn->reloc != BFD_RELOC_NONE)
2919 {
2920 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
2921 (toP - frag_now->fr_literal), /* Where. */
2922 4, /* Size. */
2923 &the_insn->exp,
2924 the_insn->pcrel,
2925 the_insn->reloc);
2926 /* Turn off overflow checking in fixup_segment. We'll do our
2927 own overflow checking in md_apply_fix. This is necessary because
2928 the insn size is 4 and fixup_segment will signal an overflow for
2929 large 8 byte quantities. */
2930 fixP->fx_no_overflow = 1;
2931 if (the_insn->reloc == BFD_RELOC_SPARC_OLO10)
2932 fixP->tc_fix_data = the_insn->exp2.X_add_number;
2933 }
2934
2935 last_insn = insn;
2936 last_opcode = the_insn->opcode;
2937
2938 #ifdef OBJ_ELF
2939 dwarf2_emit_insn (4);
2940 #endif
2941 }
2942 \f
2943 /* This is identical to the md_atof in m68k.c. I think this is right,
2944 but I'm not sure.
2945
2946 Turn a string in input_line_pointer into a floating point constant
2947 of type TYPE, and store the appropriate bytes in *LITP. The number
2948 of LITTLENUMS emitted is stored in *SIZEP. An error message is
2949 returned, or NULL on OK. */
2950
2951 /* Equal to MAX_PRECISION in atof-ieee.c. */
2952 #define MAX_LITTLENUMS 6
2953
2954 char *
2955 md_atof (type, litP, sizeP)
2956 char type;
2957 char *litP;
2958 int *sizeP;
2959 {
2960 int i, prec;
2961 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2962 char *t;
2963
2964 switch (type)
2965 {
2966 case 'f':
2967 case 'F':
2968 case 's':
2969 case 'S':
2970 prec = 2;
2971 break;
2972
2973 case 'd':
2974 case 'D':
2975 case 'r':
2976 case 'R':
2977 prec = 4;
2978 break;
2979
2980 case 'x':
2981 case 'X':
2982 prec = 6;
2983 break;
2984
2985 case 'p':
2986 case 'P':
2987 prec = 6;
2988 break;
2989
2990 default:
2991 *sizeP = 0;
2992 return _("Bad call to MD_ATOF()");
2993 }
2994
2995 t = atof_ieee (input_line_pointer, type, words);
2996 if (t)
2997 input_line_pointer = t;
2998 *sizeP = prec * sizeof (LITTLENUM_TYPE);
2999
3000 if (target_big_endian)
3001 {
3002 for (i = 0; i < prec; i++)
3003 {
3004 md_number_to_chars (litP, (valueT) words[i],
3005 sizeof (LITTLENUM_TYPE));
3006 litP += sizeof (LITTLENUM_TYPE);
3007 }
3008 }
3009 else
3010 {
3011 for (i = prec - 1; i >= 0; i--)
3012 {
3013 md_number_to_chars (litP, (valueT) words[i],
3014 sizeof (LITTLENUM_TYPE));
3015 litP += sizeof (LITTLENUM_TYPE);
3016 }
3017 }
3018
3019 return 0;
3020 }
3021
3022 /* Write a value out to the object file, using the appropriate
3023 endianness. */
3024
3025 void
3026 md_number_to_chars (buf, val, n)
3027 char *buf;
3028 valueT val;
3029 int n;
3030 {
3031 if (target_big_endian)
3032 number_to_chars_bigendian (buf, val, n);
3033 else if (target_little_endian_data
3034 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
3035 /* Output debug words, which are not in allocated sections, as big
3036 endian. */
3037 number_to_chars_bigendian (buf, val, n);
3038 else if (target_little_endian_data || ! target_big_endian)
3039 number_to_chars_littleendian (buf, val, n);
3040 }
3041 \f
3042 /* Apply a fixS to the frags, now that we know the value it ought to
3043 hold. */
3044
3045 void
3046 md_apply_fix (fixP, valP, segment)
3047 fixS *fixP;
3048 valueT *valP;
3049 segT segment ATTRIBUTE_UNUSED;
3050 {
3051 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
3052 offsetT val = * (offsetT *) valP;
3053 long insn;
3054
3055 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
3056
3057 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
3058
3059 #ifdef OBJ_ELF
3060 /* SPARC ELF relocations don't use an addend in the data field. */
3061 if (fixP->fx_addsy != NULL)
3062 {
3063 switch (fixP->fx_r_type)
3064 {
3065 case BFD_RELOC_SPARC_TLS_GD_HI22:
3066 case BFD_RELOC_SPARC_TLS_GD_LO10:
3067 case BFD_RELOC_SPARC_TLS_GD_ADD:
3068 case BFD_RELOC_SPARC_TLS_GD_CALL:
3069 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3070 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3071 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3072 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3073 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3074 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3075 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3076 case BFD_RELOC_SPARC_TLS_IE_HI22:
3077 case BFD_RELOC_SPARC_TLS_IE_LO10:
3078 case BFD_RELOC_SPARC_TLS_IE_LD:
3079 case BFD_RELOC_SPARC_TLS_IE_LDX:
3080 case BFD_RELOC_SPARC_TLS_IE_ADD:
3081 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3082 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3083 case BFD_RELOC_SPARC_TLS_DTPMOD32:
3084 case BFD_RELOC_SPARC_TLS_DTPMOD64:
3085 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3086 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3087 case BFD_RELOC_SPARC_TLS_TPOFF32:
3088 case BFD_RELOC_SPARC_TLS_TPOFF64:
3089 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3090
3091 default:
3092 break;
3093 }
3094
3095 return;
3096 }
3097 #endif
3098
3099 /* This is a hack. There should be a better way to
3100 handle this. Probably in terms of howto fields, once
3101 we can look at these fixups in terms of howtos. */
3102 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
3103 val += fixP->fx_where + fixP->fx_frag->fr_address;
3104
3105 #ifdef OBJ_AOUT
3106 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3107 generate a reloc, then we just want to let the reloc addend set
3108 the value. We do not want to also stuff the addend into the
3109 object file. Including the addend in the object file works when
3110 doing a static link, because the linker will ignore the object
3111 file contents. However, the dynamic linker does not ignore the
3112 object file contents. */
3113 if (fixP->fx_addsy != NULL
3114 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
3115 val = 0;
3116
3117 /* When generating PIC code, we do not want an addend for a reloc
3118 against a local symbol. We adjust fx_addnumber to cancel out the
3119 value already included in val, and to also cancel out the
3120 adjustment which bfd_install_relocation will create. */
3121 if (sparc_pic_code
3122 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
3123 && fixP->fx_addsy != NULL
3124 && ! S_IS_COMMON (fixP->fx_addsy)
3125 && symbol_section_p (fixP->fx_addsy))
3126 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3127
3128 /* When generating PIC code, we need to fiddle to get
3129 bfd_install_relocation to do the right thing for a PC relative
3130 reloc against a local symbol which we are going to keep. */
3131 if (sparc_pic_code
3132 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
3133 && fixP->fx_addsy != NULL
3134 && (S_IS_EXTERNAL (fixP->fx_addsy)
3135 || S_IS_WEAK (fixP->fx_addsy))
3136 && S_IS_DEFINED (fixP->fx_addsy)
3137 && ! S_IS_COMMON (fixP->fx_addsy))
3138 {
3139 val = 0;
3140 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3141 }
3142 #endif
3143
3144 /* If this is a data relocation, just output VAL. */
3145
3146 if (fixP->fx_r_type == BFD_RELOC_16
3147 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16)
3148 {
3149 md_number_to_chars (buf, val, 2);
3150 }
3151 else if (fixP->fx_r_type == BFD_RELOC_32
3152 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32
3153 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
3154 {
3155 md_number_to_chars (buf, val, 4);
3156 }
3157 else if (fixP->fx_r_type == BFD_RELOC_64
3158 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64)
3159 {
3160 md_number_to_chars (buf, val, 8);
3161 }
3162 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3163 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3164 {
3165 fixP->fx_done = 0;
3166 return;
3167 }
3168 else
3169 {
3170 /* It's a relocation against an instruction. */
3171
3172 if (INSN_BIG_ENDIAN)
3173 insn = bfd_getb32 ((unsigned char *) buf);
3174 else
3175 insn = bfd_getl32 ((unsigned char *) buf);
3176
3177 switch (fixP->fx_r_type)
3178 {
3179 case BFD_RELOC_32_PCREL_S2:
3180 val = val >> 2;
3181 /* FIXME: This increment-by-one deserves a comment of why it's
3182 being done! */
3183 if (! sparc_pic_code
3184 || fixP->fx_addsy == NULL
3185 || symbol_section_p (fixP->fx_addsy))
3186 ++val;
3187
3188 insn |= val & 0x3fffffff;
3189
3190 /* See if we have a delay slot. */
3191 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
3192 {
3193 #define G0 0
3194 #define O7 15
3195 #define XCC (2 << 20)
3196 #define COND(x) (((x)&0xf)<<25)
3197 #define CONDA COND(0x8)
3198 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3199 #define INSN_BA (F2(0,2) | CONDA)
3200 #define INSN_OR F3(2, 0x2, 0)
3201 #define INSN_NOP F2(0,4)
3202
3203 long delay;
3204
3205 /* If the instruction is a call with either:
3206 restore
3207 arithmetic instruction with rd == %o7
3208 where rs1 != %o7 and rs2 if it is register != %o7
3209 then we can optimize if the call destination is near
3210 by changing the call into a branch always. */
3211 if (INSN_BIG_ENDIAN)
3212 delay = bfd_getb32 ((unsigned char *) buf + 4);
3213 else
3214 delay = bfd_getl32 ((unsigned char *) buf + 4);
3215 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
3216 break;
3217 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
3218 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
3219 || ((delay & RD (~0)) != RD (O7))))
3220 break;
3221 if ((delay & RS1 (~0)) == RS1 (O7)
3222 || ((delay & F3I (~0)) == 0
3223 && (delay & RS2 (~0)) == RS2 (O7)))
3224 break;
3225 /* Ensure the branch will fit into simm22. */
3226 if ((val & 0x3fe00000)
3227 && (val & 0x3fe00000) != 0x3fe00000)
3228 break;
3229 /* Check if the arch is v9 and branch will fit
3230 into simm19. */
3231 if (((val & 0x3c0000) == 0
3232 || (val & 0x3c0000) == 0x3c0000)
3233 && (sparc_arch_size == 64
3234 || current_architecture >= SPARC_OPCODE_ARCH_V9))
3235 /* ba,pt %xcc */
3236 insn = INSN_BPA | (val & 0x7ffff);
3237 else
3238 /* ba */
3239 insn = INSN_BA | (val & 0x3fffff);
3240 if (fixP->fx_where >= 4
3241 && ((delay & (0xffffffff ^ RS1 (~0)))
3242 == (INSN_OR | RD (O7) | RS2 (G0))))
3243 {
3244 long setter;
3245 int reg;
3246
3247 if (INSN_BIG_ENDIAN)
3248 setter = bfd_getb32 ((unsigned char *) buf - 4);
3249 else
3250 setter = bfd_getl32 ((unsigned char *) buf - 4);
3251 if ((setter & (0xffffffff ^ RD (~0)))
3252 != (INSN_OR | RS1 (O7) | RS2 (G0)))
3253 break;
3254 /* The sequence was
3255 or %o7, %g0, %rN
3256 call foo
3257 or %rN, %g0, %o7
3258
3259 If call foo was replaced with ba, replace
3260 or %rN, %g0, %o7 with nop. */
3261 reg = (delay & RS1 (~0)) >> 14;
3262 if (reg != ((setter & RD (~0)) >> 25)
3263 || reg == G0 || reg == O7)
3264 break;
3265
3266 if (INSN_BIG_ENDIAN)
3267 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3268 else
3269 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3270 }
3271 }
3272 break;
3273
3274 case BFD_RELOC_SPARC_11:
3275 if (! in_signed_range (val, 0x7ff))
3276 as_bad_where (fixP->fx_file, fixP->fx_line,
3277 _("relocation overflow"));
3278 insn |= val & 0x7ff;
3279 break;
3280
3281 case BFD_RELOC_SPARC_10:
3282 if (! in_signed_range (val, 0x3ff))
3283 as_bad_where (fixP->fx_file, fixP->fx_line,
3284 _("relocation overflow"));
3285 insn |= val & 0x3ff;
3286 break;
3287
3288 case BFD_RELOC_SPARC_7:
3289 if (! in_bitfield_range (val, 0x7f))
3290 as_bad_where (fixP->fx_file, fixP->fx_line,
3291 _("relocation overflow"));
3292 insn |= val & 0x7f;
3293 break;
3294
3295 case BFD_RELOC_SPARC_6:
3296 if (! in_bitfield_range (val, 0x3f))
3297 as_bad_where (fixP->fx_file, fixP->fx_line,
3298 _("relocation overflow"));
3299 insn |= val & 0x3f;
3300 break;
3301
3302 case BFD_RELOC_SPARC_5:
3303 if (! in_bitfield_range (val, 0x1f))
3304 as_bad_where (fixP->fx_file, fixP->fx_line,
3305 _("relocation overflow"));
3306 insn |= val & 0x1f;
3307 break;
3308
3309 case BFD_RELOC_SPARC_WDISP16:
3310 /* FIXME: simplify. */
3311 if (((val > 0) && (val & ~0x3fffc))
3312 || ((val < 0) && (~(val - 1) & ~0x3fffc)))
3313 as_bad_where (fixP->fx_file, fixP->fx_line,
3314 _("relocation overflow"));
3315 /* FIXME: The +1 deserves a comment. */
3316 val = (val >> 2) + 1;
3317 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3318 break;
3319
3320 case BFD_RELOC_SPARC_WDISP19:
3321 /* FIXME: simplify. */
3322 if (((val > 0) && (val & ~0x1ffffc))
3323 || ((val < 0) && (~(val - 1) & ~0x1ffffc)))
3324 as_bad_where (fixP->fx_file, fixP->fx_line,
3325 _("relocation overflow"));
3326 /* FIXME: The +1 deserves a comment. */
3327 val = (val >> 2) + 1;
3328 insn |= val & 0x7ffff;
3329 break;
3330
3331 case BFD_RELOC_SPARC_HH22:
3332 val = BSR (val, 32);
3333 /* Fall through. */
3334
3335 case BFD_RELOC_SPARC_LM22:
3336 case BFD_RELOC_HI22:
3337 if (!fixP->fx_addsy)
3338 insn |= (val >> 10) & 0x3fffff;
3339 else
3340 /* FIXME: Need comment explaining why we do this. */
3341 insn &= ~0xffff;
3342 break;
3343
3344 case BFD_RELOC_SPARC22:
3345 if (val & ~0x003fffff)
3346 as_bad_where (fixP->fx_file, fixP->fx_line,
3347 _("relocation overflow"));
3348 insn |= (val & 0x3fffff);
3349 break;
3350
3351 case BFD_RELOC_SPARC_HM10:
3352 val = BSR (val, 32);
3353 /* Fall through. */
3354
3355 case BFD_RELOC_LO10:
3356 if (!fixP->fx_addsy)
3357 insn |= val & 0x3ff;
3358 else
3359 /* FIXME: Need comment explaining why we do this. */
3360 insn &= ~0xff;
3361 break;
3362
3363 case BFD_RELOC_SPARC_OLO10:
3364 val &= 0x3ff;
3365 val += fixP->tc_fix_data;
3366 /* Fall through. */
3367
3368 case BFD_RELOC_SPARC13:
3369 if (! in_signed_range (val, 0x1fff))
3370 as_bad_where (fixP->fx_file, fixP->fx_line,
3371 _("relocation overflow"));
3372 insn |= val & 0x1fff;
3373 break;
3374
3375 case BFD_RELOC_SPARC_WDISP22:
3376 val = (val >> 2) + 1;
3377 /* Fall through. */
3378 case BFD_RELOC_SPARC_BASE22:
3379 insn |= val & 0x3fffff;
3380 break;
3381
3382 case BFD_RELOC_SPARC_H44:
3383 if (!fixP->fx_addsy)
3384 {
3385 bfd_vma tval = val;
3386 tval >>= 22;
3387 insn |= tval & 0x3fffff;
3388 }
3389 break;
3390
3391 case BFD_RELOC_SPARC_M44:
3392 if (!fixP->fx_addsy)
3393 insn |= (val >> 12) & 0x3ff;
3394 break;
3395
3396 case BFD_RELOC_SPARC_L44:
3397 if (!fixP->fx_addsy)
3398 insn |= val & 0xfff;
3399 break;
3400
3401 case BFD_RELOC_SPARC_HIX22:
3402 if (!fixP->fx_addsy)
3403 {
3404 val ^= ~(offsetT) 0;
3405 insn |= (val >> 10) & 0x3fffff;
3406 }
3407 break;
3408
3409 case BFD_RELOC_SPARC_LOX10:
3410 if (!fixP->fx_addsy)
3411 insn |= 0x1c00 | (val & 0x3ff);
3412 break;
3413
3414 case BFD_RELOC_NONE:
3415 default:
3416 as_bad_where (fixP->fx_file, fixP->fx_line,
3417 _("bad or unhandled relocation type: 0x%02x"),
3418 fixP->fx_r_type);
3419 break;
3420 }
3421
3422 if (INSN_BIG_ENDIAN)
3423 bfd_putb32 (insn, (unsigned char *) buf);
3424 else
3425 bfd_putl32 (insn, (unsigned char *) buf);
3426 }
3427
3428 /* Are we finished with this relocation now? */
3429 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3430 fixP->fx_done = 1;
3431 }
3432
3433 /* Translate internal representation of relocation info to BFD target
3434 format. */
3435
3436 arelent **
3437 tc_gen_reloc (section, fixp)
3438 asection *section ATTRIBUTE_UNUSED;
3439 fixS *fixp;
3440 {
3441 static arelent *relocs[3];
3442 arelent *reloc;
3443 bfd_reloc_code_real_type code;
3444
3445 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3446 relocs[1] = NULL;
3447
3448 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3449 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3450 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3451
3452 switch (fixp->fx_r_type)
3453 {
3454 case BFD_RELOC_16:
3455 case BFD_RELOC_32:
3456 case BFD_RELOC_HI22:
3457 case BFD_RELOC_LO10:
3458 case BFD_RELOC_32_PCREL_S2:
3459 case BFD_RELOC_SPARC13:
3460 case BFD_RELOC_SPARC22:
3461 case BFD_RELOC_SPARC_BASE13:
3462 case BFD_RELOC_SPARC_WDISP16:
3463 case BFD_RELOC_SPARC_WDISP19:
3464 case BFD_RELOC_SPARC_WDISP22:
3465 case BFD_RELOC_64:
3466 case BFD_RELOC_SPARC_5:
3467 case BFD_RELOC_SPARC_6:
3468 case BFD_RELOC_SPARC_7:
3469 case BFD_RELOC_SPARC_10:
3470 case BFD_RELOC_SPARC_11:
3471 case BFD_RELOC_SPARC_HH22:
3472 case BFD_RELOC_SPARC_HM10:
3473 case BFD_RELOC_SPARC_LM22:
3474 case BFD_RELOC_SPARC_PC_HH22:
3475 case BFD_RELOC_SPARC_PC_HM10:
3476 case BFD_RELOC_SPARC_PC_LM22:
3477 case BFD_RELOC_SPARC_H44:
3478 case BFD_RELOC_SPARC_M44:
3479 case BFD_RELOC_SPARC_L44:
3480 case BFD_RELOC_SPARC_HIX22:
3481 case BFD_RELOC_SPARC_LOX10:
3482 case BFD_RELOC_SPARC_REV32:
3483 case BFD_RELOC_SPARC_OLO10:
3484 case BFD_RELOC_SPARC_UA16:
3485 case BFD_RELOC_SPARC_UA32:
3486 case BFD_RELOC_SPARC_UA64:
3487 case BFD_RELOC_8_PCREL:
3488 case BFD_RELOC_16_PCREL:
3489 case BFD_RELOC_32_PCREL:
3490 case BFD_RELOC_64_PCREL:
3491 case BFD_RELOC_SPARC_PLT32:
3492 case BFD_RELOC_SPARC_PLT64:
3493 case BFD_RELOC_VTABLE_ENTRY:
3494 case BFD_RELOC_VTABLE_INHERIT:
3495 case BFD_RELOC_SPARC_TLS_GD_HI22:
3496 case BFD_RELOC_SPARC_TLS_GD_LO10:
3497 case BFD_RELOC_SPARC_TLS_GD_ADD:
3498 case BFD_RELOC_SPARC_TLS_GD_CALL:
3499 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3500 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3501 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3502 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3503 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3504 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3505 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3506 case BFD_RELOC_SPARC_TLS_IE_HI22:
3507 case BFD_RELOC_SPARC_TLS_IE_LO10:
3508 case BFD_RELOC_SPARC_TLS_IE_LD:
3509 case BFD_RELOC_SPARC_TLS_IE_LDX:
3510 case BFD_RELOC_SPARC_TLS_IE_ADD:
3511 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3512 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3513 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3514 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3515 code = fixp->fx_r_type;
3516 break;
3517 default:
3518 abort ();
3519 return NULL;
3520 }
3521
3522 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3523 /* If we are generating PIC code, we need to generate a different
3524 set of relocs. */
3525
3526 #ifdef OBJ_ELF
3527 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3528 #else
3529 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3530 #endif
3531
3532 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3533
3534 if (sparc_pic_code)
3535 {
3536 switch (code)
3537 {
3538 case BFD_RELOC_32_PCREL_S2:
3539 if (generic_force_reloc (fixp))
3540 code = BFD_RELOC_SPARC_WPLT30;
3541 break;
3542 case BFD_RELOC_HI22:
3543 if (fixp->fx_addsy != NULL
3544 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3545 code = BFD_RELOC_SPARC_PC22;
3546 else
3547 code = BFD_RELOC_SPARC_GOT22;
3548 break;
3549 case BFD_RELOC_LO10:
3550 if (fixp->fx_addsy != NULL
3551 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3552 code = BFD_RELOC_SPARC_PC10;
3553 else
3554 code = BFD_RELOC_SPARC_GOT10;
3555 break;
3556 case BFD_RELOC_SPARC13:
3557 code = BFD_RELOC_SPARC_GOT13;
3558 break;
3559 default:
3560 break;
3561 }
3562 }
3563 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3564
3565 if (code == BFD_RELOC_SPARC_OLO10)
3566 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3567 else
3568 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3569 if (reloc->howto == 0)
3570 {
3571 as_bad_where (fixp->fx_file, fixp->fx_line,
3572 _("internal error: can't export reloc type %d (`%s')"),
3573 fixp->fx_r_type, bfd_get_reloc_code_name (code));
3574 xfree (reloc);
3575 relocs[0] = NULL;
3576 return relocs;
3577 }
3578
3579 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3580 #ifdef OBJ_AOUT
3581
3582 if (reloc->howto->pc_relative == 0
3583 || code == BFD_RELOC_SPARC_PC10
3584 || code == BFD_RELOC_SPARC_PC22)
3585 reloc->addend = fixp->fx_addnumber;
3586 else if (sparc_pic_code
3587 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3588 && fixp->fx_addsy != NULL
3589 && (S_IS_EXTERNAL (fixp->fx_addsy)
3590 || S_IS_WEAK (fixp->fx_addsy))
3591 && S_IS_DEFINED (fixp->fx_addsy)
3592 && ! S_IS_COMMON (fixp->fx_addsy))
3593 reloc->addend = fixp->fx_addnumber;
3594 else
3595 reloc->addend = fixp->fx_offset - reloc->address;
3596
3597 #else /* elf or coff */
3598
3599 if (code != BFD_RELOC_32_PCREL_S2
3600 && code != BFD_RELOC_SPARC_WDISP22
3601 && code != BFD_RELOC_SPARC_WDISP16
3602 && code != BFD_RELOC_SPARC_WDISP19
3603 && code != BFD_RELOC_SPARC_WPLT30
3604 && code != BFD_RELOC_SPARC_TLS_GD_CALL
3605 && code != BFD_RELOC_SPARC_TLS_LDM_CALL)
3606 reloc->addend = fixp->fx_addnumber;
3607 else if (symbol_section_p (fixp->fx_addsy))
3608 reloc->addend = (section->vma
3609 + fixp->fx_addnumber
3610 + md_pcrel_from (fixp));
3611 else
3612 reloc->addend = fixp->fx_offset;
3613 #endif
3614
3615 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3616 on the same location. */
3617 if (code == BFD_RELOC_SPARC_OLO10)
3618 {
3619 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3620 relocs[2] = NULL;
3621
3622 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3623 *reloc->sym_ptr_ptr
3624 = symbol_get_bfdsym (section_symbol (absolute_section));
3625 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3626 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3627 reloc->addend = fixp->tc_fix_data;
3628 }
3629
3630 return relocs;
3631 }
3632 \f
3633 /* We have no need to default values of symbols. */
3634
3635 symbolS *
3636 md_undefined_symbol (name)
3637 char *name ATTRIBUTE_UNUSED;
3638 {
3639 return 0;
3640 }
3641
3642 /* Round up a section size to the appropriate boundary. */
3643
3644 valueT
3645 md_section_align (segment, size)
3646 segT segment ATTRIBUTE_UNUSED;
3647 valueT size;
3648 {
3649 #ifndef OBJ_ELF
3650 /* This is not right for ELF; a.out wants it, and COFF will force
3651 the alignment anyways. */
3652 valueT align = ((valueT) 1
3653 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3654 valueT newsize;
3655
3656 /* Turn alignment value into a mask. */
3657 align--;
3658 newsize = (size + align) & ~align;
3659 return newsize;
3660 #else
3661 return size;
3662 #endif
3663 }
3664
3665 /* Exactly what point is a PC-relative offset relative TO?
3666 On the sparc, they're relative to the address of the offset, plus
3667 its size. This gets us to the following instruction.
3668 (??? Is this right? FIXME-SOON) */
3669 long
3670 md_pcrel_from (fixP)
3671 fixS *fixP;
3672 {
3673 long ret;
3674
3675 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3676 if (! sparc_pic_code
3677 || fixP->fx_addsy == NULL
3678 || symbol_section_p (fixP->fx_addsy))
3679 ret += fixP->fx_size;
3680 return ret;
3681 }
3682 \f
3683 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3684 of two. */
3685
3686 static int
3687 mylog2 (value)
3688 int value;
3689 {
3690 int shift;
3691
3692 if (value <= 0)
3693 return -1;
3694
3695 for (shift = 0; (value & 1) == 0; value >>= 1)
3696 ++shift;
3697
3698 return (value == 1) ? shift : -1;
3699 }
3700
3701 /* Sort of like s_lcomm. */
3702
3703 #ifndef OBJ_ELF
3704 static int max_alignment = 15;
3705 #endif
3706
3707 static void
3708 s_reserve (ignore)
3709 int ignore ATTRIBUTE_UNUSED;
3710 {
3711 char *name;
3712 char *p;
3713 char c;
3714 int align;
3715 int size;
3716 int temp;
3717 symbolS *symbolP;
3718
3719 name = input_line_pointer;
3720 c = get_symbol_end ();
3721 p = input_line_pointer;
3722 *p = c;
3723 SKIP_WHITESPACE ();
3724
3725 if (*input_line_pointer != ',')
3726 {
3727 as_bad (_("Expected comma after name"));
3728 ignore_rest_of_line ();
3729 return;
3730 }
3731
3732 ++input_line_pointer;
3733
3734 if ((size = get_absolute_expression ()) < 0)
3735 {
3736 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3737 ignore_rest_of_line ();
3738 return;
3739 } /* Bad length. */
3740
3741 *p = 0;
3742 symbolP = symbol_find_or_make (name);
3743 *p = c;
3744
3745 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3746 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3747 {
3748 as_bad (_("bad .reserve segment -- expected BSS segment"));
3749 return;
3750 }
3751
3752 if (input_line_pointer[2] == '.')
3753 input_line_pointer += 7;
3754 else
3755 input_line_pointer += 6;
3756 SKIP_WHITESPACE ();
3757
3758 if (*input_line_pointer == ',')
3759 {
3760 ++input_line_pointer;
3761
3762 SKIP_WHITESPACE ();
3763 if (*input_line_pointer == '\n')
3764 {
3765 as_bad (_("missing alignment"));
3766 ignore_rest_of_line ();
3767 return;
3768 }
3769
3770 align = (int) get_absolute_expression ();
3771
3772 #ifndef OBJ_ELF
3773 if (align > max_alignment)
3774 {
3775 align = max_alignment;
3776 as_warn (_("alignment too large; assuming %d"), align);
3777 }
3778 #endif
3779
3780 if (align < 0)
3781 {
3782 as_bad (_("negative alignment"));
3783 ignore_rest_of_line ();
3784 return;
3785 }
3786
3787 if (align != 0)
3788 {
3789 temp = mylog2 (align);
3790 if (temp < 0)
3791 {
3792 as_bad (_("alignment not a power of 2"));
3793 ignore_rest_of_line ();
3794 return;
3795 }
3796
3797 align = temp;
3798 }
3799
3800 record_alignment (bss_section, align);
3801 }
3802 else
3803 align = 0;
3804
3805 if (!S_IS_DEFINED (symbolP)
3806 #ifdef OBJ_AOUT
3807 && S_GET_OTHER (symbolP) == 0
3808 && S_GET_DESC (symbolP) == 0
3809 #endif
3810 )
3811 {
3812 if (! need_pass_2)
3813 {
3814 char *pfrag;
3815 segT current_seg = now_seg;
3816 subsegT current_subseg = now_subseg;
3817
3818 /* Switch to bss. */
3819 subseg_set (bss_section, 1);
3820
3821 if (align)
3822 /* Do alignment. */
3823 frag_align (align, 0, 0);
3824
3825 /* Detach from old frag. */
3826 if (S_GET_SEGMENT (symbolP) == bss_section)
3827 symbol_get_frag (symbolP)->fr_symbol = NULL;
3828
3829 symbol_set_frag (symbolP, frag_now);
3830 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3831 (offsetT) size, (char *) 0);
3832 *pfrag = 0;
3833
3834 S_SET_SEGMENT (symbolP, bss_section);
3835
3836 subseg_set (current_seg, current_subseg);
3837
3838 #ifdef OBJ_ELF
3839 S_SET_SIZE (symbolP, size);
3840 #endif
3841 }
3842 }
3843 else
3844 {
3845 as_warn ("Ignoring attempt to re-define symbol %s",
3846 S_GET_NAME (symbolP));
3847 } /* if not redefining. */
3848
3849 demand_empty_rest_of_line ();
3850 }
3851
3852 static void
3853 s_common (ignore)
3854 int ignore ATTRIBUTE_UNUSED;
3855 {
3856 char *name;
3857 char c;
3858 char *p;
3859 offsetT temp, size;
3860 symbolS *symbolP;
3861
3862 name = input_line_pointer;
3863 c = get_symbol_end ();
3864 /* Just after name is now '\0'. */
3865 p = input_line_pointer;
3866 *p = c;
3867 SKIP_WHITESPACE ();
3868 if (*input_line_pointer != ',')
3869 {
3870 as_bad (_("Expected comma after symbol-name"));
3871 ignore_rest_of_line ();
3872 return;
3873 }
3874
3875 /* Skip ','. */
3876 input_line_pointer++;
3877
3878 if ((temp = get_absolute_expression ()) < 0)
3879 {
3880 as_bad (_(".COMMon length (%lu) out of range ignored"),
3881 (unsigned long) temp);
3882 ignore_rest_of_line ();
3883 return;
3884 }
3885 size = temp;
3886 *p = 0;
3887 symbolP = symbol_find_or_make (name);
3888 *p = c;
3889 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
3890 {
3891 as_bad (_("Ignoring attempt to re-define symbol"));
3892 ignore_rest_of_line ();
3893 return;
3894 }
3895 if (S_GET_VALUE (symbolP) != 0)
3896 {
3897 if (S_GET_VALUE (symbolP) != (valueT) size)
3898 {
3899 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
3900 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size);
3901 }
3902 }
3903 else
3904 {
3905 #ifndef OBJ_ELF
3906 S_SET_VALUE (symbolP, (valueT) size);
3907 S_SET_EXTERNAL (symbolP);
3908 #endif
3909 }
3910 know (symbol_get_frag (symbolP) == &zero_address_frag);
3911 if (*input_line_pointer != ',')
3912 {
3913 as_bad (_("Expected comma after common length"));
3914 ignore_rest_of_line ();
3915 return;
3916 }
3917 input_line_pointer++;
3918 SKIP_WHITESPACE ();
3919 if (*input_line_pointer != '"')
3920 {
3921 temp = get_absolute_expression ();
3922
3923 #ifndef OBJ_ELF
3924 if (temp > max_alignment)
3925 {
3926 temp = max_alignment;
3927 as_warn (_("alignment too large; assuming %ld"), (long) temp);
3928 }
3929 #endif
3930
3931 if (temp < 0)
3932 {
3933 as_bad (_("negative alignment"));
3934 ignore_rest_of_line ();
3935 return;
3936 }
3937
3938 #ifdef OBJ_ELF
3939 if (symbol_get_obj (symbolP)->local)
3940 {
3941 segT old_sec;
3942 int old_subsec;
3943 char *p;
3944 int align;
3945
3946 old_sec = now_seg;
3947 old_subsec = now_subseg;
3948
3949 if (temp == 0)
3950 align = 0;
3951 else
3952 align = mylog2 (temp);
3953
3954 if (align < 0)
3955 {
3956 as_bad (_("alignment not a power of 2"));
3957 ignore_rest_of_line ();
3958 return;
3959 }
3960
3961 record_alignment (bss_section, align);
3962 subseg_set (bss_section, 0);
3963 if (align)
3964 frag_align (align, 0, 0);
3965 if (S_GET_SEGMENT (symbolP) == bss_section)
3966 symbol_get_frag (symbolP)->fr_symbol = 0;
3967 symbol_set_frag (symbolP, frag_now);
3968 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3969 (offsetT) size, (char *) 0);
3970 *p = 0;
3971 S_SET_SEGMENT (symbolP, bss_section);
3972 S_CLEAR_EXTERNAL (symbolP);
3973 S_SET_SIZE (symbolP, size);
3974 subseg_set (old_sec, old_subsec);
3975 }
3976 else
3977 #endif /* OBJ_ELF */
3978 {
3979 allocate_common:
3980 S_SET_VALUE (symbolP, (valueT) size);
3981 #ifdef OBJ_ELF
3982 S_SET_ALIGN (symbolP, temp);
3983 S_SET_SIZE (symbolP, size);
3984 #endif
3985 S_SET_EXTERNAL (symbolP);
3986 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
3987 }
3988 }
3989 else
3990 {
3991 input_line_pointer++;
3992 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3993 if (*input_line_pointer == '.')
3994 input_line_pointer++;
3995 /* @@ Some say data, some say bss. */
3996 if (strncmp (input_line_pointer, "bss\"", 4)
3997 && strncmp (input_line_pointer, "data\"", 5))
3998 {
3999 while (*--input_line_pointer != '"')
4000 ;
4001 input_line_pointer--;
4002 goto bad_common_segment;
4003 }
4004 while (*input_line_pointer++ != '"')
4005 ;
4006 goto allocate_common;
4007 }
4008
4009 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
4010
4011 demand_empty_rest_of_line ();
4012 return;
4013
4014 {
4015 bad_common_segment:
4016 p = input_line_pointer;
4017 while (*p && *p != '\n')
4018 p++;
4019 c = *p;
4020 *p = '\0';
4021 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
4022 *p = c;
4023 input_line_pointer = p;
4024 ignore_rest_of_line ();
4025 return;
4026 }
4027 }
4028
4029 /* Handle the .empty pseudo-op. This suppresses the warnings about
4030 invalid delay slot usage. */
4031
4032 static void
4033 s_empty (ignore)
4034 int ignore ATTRIBUTE_UNUSED;
4035 {
4036 /* The easy way to implement is to just forget about the last
4037 instruction. */
4038 last_insn = NULL;
4039 }
4040
4041 static void
4042 s_seg (ignore)
4043 int ignore ATTRIBUTE_UNUSED;
4044 {
4045
4046 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
4047 {
4048 input_line_pointer += 6;
4049 s_text (0);
4050 return;
4051 }
4052 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
4053 {
4054 input_line_pointer += 6;
4055 s_data (0);
4056 return;
4057 }
4058 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
4059 {
4060 input_line_pointer += 7;
4061 s_data1 ();
4062 return;
4063 }
4064 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
4065 {
4066 input_line_pointer += 5;
4067 /* We only support 2 segments -- text and data -- for now, so
4068 things in the "bss segment" will have to go into data for now.
4069 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4070 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
4071 return;
4072 }
4073 as_bad (_("Unknown segment type"));
4074 demand_empty_rest_of_line ();
4075 }
4076
4077 static void
4078 s_data1 ()
4079 {
4080 subseg_set (data_section, 1);
4081 demand_empty_rest_of_line ();
4082 }
4083
4084 static void
4085 s_proc (ignore)
4086 int ignore ATTRIBUTE_UNUSED;
4087 {
4088 while (!is_end_of_line[(unsigned char) *input_line_pointer])
4089 {
4090 ++input_line_pointer;
4091 }
4092 ++input_line_pointer;
4093 }
4094
4095 /* This static variable is set by s_uacons to tell sparc_cons_align
4096 that the expression does not need to be aligned. */
4097
4098 static int sparc_no_align_cons = 0;
4099
4100 /* This static variable is set by sparc_cons to emit requested types
4101 of relocations in cons_fix_new_sparc. */
4102
4103 static const char *sparc_cons_special_reloc;
4104
4105 /* This handles the unaligned space allocation pseudo-ops, such as
4106 .uaword. .uaword is just like .word, but the value does not need
4107 to be aligned. */
4108
4109 static void
4110 s_uacons (bytes)
4111 int bytes;
4112 {
4113 /* Tell sparc_cons_align not to align this value. */
4114 sparc_no_align_cons = 1;
4115 cons (bytes);
4116 sparc_no_align_cons = 0;
4117 }
4118
4119 /* This handles the native word allocation pseudo-op .nword.
4120 For sparc_arch_size 32 it is equivalent to .word, for
4121 sparc_arch_size 64 it is equivalent to .xword. */
4122
4123 static void
4124 s_ncons (bytes)
4125 int bytes ATTRIBUTE_UNUSED;
4126 {
4127 cons (sparc_arch_size == 32 ? 4 : 8);
4128 }
4129
4130 #ifdef OBJ_ELF
4131 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4132 global register.
4133 The syntax is:
4134
4135 .register %g[2367],{#scratch|symbolname|#ignore}
4136 */
4137
4138 static void
4139 s_register (ignore)
4140 int ignore ATTRIBUTE_UNUSED;
4141 {
4142 char c;
4143 int reg;
4144 int flags;
4145 const char *regname;
4146
4147 if (input_line_pointer[0] != '%'
4148 || input_line_pointer[1] != 'g'
4149 || ((input_line_pointer[2] & ~1) != '2'
4150 && (input_line_pointer[2] & ~1) != '6')
4151 || input_line_pointer[3] != ',')
4152 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4153 reg = input_line_pointer[2] - '0';
4154 input_line_pointer += 4;
4155
4156 if (*input_line_pointer == '#')
4157 {
4158 ++input_line_pointer;
4159 regname = input_line_pointer;
4160 c = get_symbol_end ();
4161 if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
4162 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4163 if (regname[0] == 'i')
4164 regname = NULL;
4165 else
4166 regname = "";
4167 }
4168 else
4169 {
4170 regname = input_line_pointer;
4171 c = get_symbol_end ();
4172 }
4173 if (sparc_arch_size == 64)
4174 {
4175 if (globals[reg])
4176 {
4177 if ((regname && globals[reg] != (symbolS *) 1
4178 && strcmp (S_GET_NAME (globals[reg]), regname))
4179 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
4180 as_bad (_("redefinition of global register"));
4181 }
4182 else
4183 {
4184 if (regname == NULL)
4185 globals[reg] = (symbolS *) 1;
4186 else
4187 {
4188 if (*regname)
4189 {
4190 if (symbol_find (regname))
4191 as_bad (_("Register symbol %s already defined."),
4192 regname);
4193 }
4194 globals[reg] = symbol_make (regname);
4195 flags = symbol_get_bfdsym (globals[reg])->flags;
4196 if (! *regname)
4197 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
4198 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
4199 flags |= BSF_GLOBAL;
4200 symbol_get_bfdsym (globals[reg])->flags = flags;
4201 S_SET_VALUE (globals[reg], (valueT) reg);
4202 S_SET_ALIGN (globals[reg], reg);
4203 S_SET_SIZE (globals[reg], 0);
4204 /* Although we actually want undefined_section here,
4205 we have to use absolute_section, because otherwise
4206 generic as code will make it a COM section.
4207 We fix this up in sparc_adjust_symtab. */
4208 S_SET_SEGMENT (globals[reg], absolute_section);
4209 S_SET_OTHER (globals[reg], 0);
4210 elf_symbol (symbol_get_bfdsym (globals[reg]))
4211 ->internal_elf_sym.st_info =
4212 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
4213 elf_symbol (symbol_get_bfdsym (globals[reg]))
4214 ->internal_elf_sym.st_shndx = SHN_UNDEF;
4215 }
4216 }
4217 }
4218
4219 *input_line_pointer = c;
4220
4221 demand_empty_rest_of_line ();
4222 }
4223
4224 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4225 symbols which need it. */
4226
4227 void
4228 sparc_adjust_symtab ()
4229 {
4230 symbolS *sym;
4231
4232 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4233 {
4234 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4235 ->internal_elf_sym.st_info) != STT_REGISTER)
4236 continue;
4237
4238 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4239 ->internal_elf_sym.st_shndx != SHN_UNDEF))
4240 continue;
4241
4242 S_SET_SEGMENT (sym, undefined_section);
4243 }
4244 }
4245 #endif
4246
4247 /* If the --enforce-aligned-data option is used, we require .word,
4248 et. al., to be aligned correctly. We do it by setting up an
4249 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4250 no unexpected alignment was introduced.
4251
4252 The SunOS and Solaris native assemblers enforce aligned data by
4253 default. We don't want to do that, because gcc can deliberately
4254 generate misaligned data if the packed attribute is used. Instead,
4255 we permit misaligned data by default, and permit the user to set an
4256 option to check for it. */
4257
4258 void
4259 sparc_cons_align (nbytes)
4260 int nbytes;
4261 {
4262 int nalign;
4263 char *p;
4264
4265 /* Only do this if we are enforcing aligned data. */
4266 if (! enforce_aligned_data)
4267 return;
4268
4269 /* Don't align if this is an unaligned pseudo-op. */
4270 if (sparc_no_align_cons)
4271 return;
4272
4273 nalign = mylog2 (nbytes);
4274 if (nalign == 0)
4275 return;
4276
4277 assert (nalign > 0);
4278
4279 if (now_seg == absolute_section)
4280 {
4281 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4282 as_bad (_("misaligned data"));
4283 return;
4284 }
4285
4286 p = frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
4287 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
4288
4289 record_alignment (now_seg, nalign);
4290 }
4291
4292 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4293
4294 void
4295 sparc_handle_align (fragp)
4296 fragS *fragp;
4297 {
4298 int count, fix;
4299 char *p;
4300
4301 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
4302
4303 switch (fragp->fr_type)
4304 {
4305 case rs_align_test:
4306 if (count != 0)
4307 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4308 break;
4309
4310 case rs_align_code:
4311 p = fragp->fr_literal + fragp->fr_fix;
4312 fix = 0;
4313
4314 if (count & 3)
4315 {
4316 fix = count & 3;
4317 memset (p, 0, fix);
4318 p += fix;
4319 count -= fix;
4320 }
4321
4322 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4323 {
4324 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
4325 if (INSN_BIG_ENDIAN)
4326 number_to_chars_bigendian (p, wval, 4);
4327 else
4328 number_to_chars_littleendian (p, wval, 4);
4329 p += 4;
4330 count -= 4;
4331 fix += 4;
4332 }
4333
4334 if (INSN_BIG_ENDIAN)
4335 number_to_chars_bigendian (p, 0x01000000, 4);
4336 else
4337 number_to_chars_littleendian (p, 0x01000000, 4);
4338
4339 fragp->fr_fix += fix;
4340 fragp->fr_var = 4;
4341 break;
4342
4343 default:
4344 break;
4345 }
4346 }
4347
4348 #ifdef OBJ_ELF
4349 /* Some special processing for a Sparc ELF file. */
4350
4351 void
4352 sparc_elf_final_processing ()
4353 {
4354 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4355 sort of BFD interface for this. */
4356 if (sparc_arch_size == 64)
4357 {
4358 switch (sparc_memory_model)
4359 {
4360 case MM_RMO:
4361 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4362 break;
4363 case MM_PSO:
4364 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4365 break;
4366 default:
4367 break;
4368 }
4369 }
4370 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4371 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4372 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4373 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
4374 else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
4375 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
4376 }
4377
4378 void
4379 sparc_cons (exp, size)
4380 expressionS *exp;
4381 int size;
4382 {
4383 char *save;
4384
4385 SKIP_WHITESPACE ();
4386 sparc_cons_special_reloc = NULL;
4387 save = input_line_pointer;
4388 if (input_line_pointer[0] == '%'
4389 && input_line_pointer[1] == 'r'
4390 && input_line_pointer[2] == '_')
4391 {
4392 if (strncmp (input_line_pointer + 3, "disp", 4) == 0)
4393 {
4394 input_line_pointer += 7;
4395 sparc_cons_special_reloc = "disp";
4396 }
4397 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0)
4398 {
4399 if (size != 4 && size != 8)
4400 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size);
4401 else
4402 {
4403 input_line_pointer += 6;
4404 sparc_cons_special_reloc = "plt";
4405 }
4406 }
4407 else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0)
4408 {
4409 if (size != 4 && size != 8)
4410 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size);
4411 else
4412 {
4413 input_line_pointer += 13;
4414 sparc_cons_special_reloc = "tls_dtpoff";
4415 }
4416 }
4417 if (sparc_cons_special_reloc)
4418 {
4419 int bad = 0;
4420
4421 switch (size)
4422 {
4423 case 1:
4424 if (*input_line_pointer != '8')
4425 bad = 1;
4426 input_line_pointer--;
4427 break;
4428 case 2:
4429 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6')
4430 bad = 1;
4431 break;
4432 case 4:
4433 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2')
4434 bad = 1;
4435 break;
4436 case 8:
4437 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4')
4438 bad = 1;
4439 break;
4440 default:
4441 bad = 1;
4442 break;
4443 }
4444
4445 if (bad)
4446 {
4447 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4448 sparc_cons_special_reloc, size * 8, size);
4449 }
4450 else
4451 {
4452 input_line_pointer += 2;
4453 if (*input_line_pointer != '(')
4454 {
4455 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4456 sparc_cons_special_reloc, size * 8);
4457 bad = 1;
4458 }
4459 }
4460
4461 if (bad)
4462 {
4463 input_line_pointer = save;
4464 sparc_cons_special_reloc = NULL;
4465 }
4466 else
4467 {
4468 int c;
4469 char *end = ++input_line_pointer;
4470 int npar = 0;
4471
4472 while (! is_end_of_line[(c = *end)])
4473 {
4474 if (c == '(')
4475 npar++;
4476 else if (c == ')')
4477 {
4478 if (!npar)
4479 break;
4480 npar--;
4481 }
4482 end++;
4483 }
4484
4485 if (c != ')')
4486 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4487 sparc_cons_special_reloc, size * 8);
4488 else
4489 {
4490 *end = '\0';
4491 expression (exp);
4492 *end = c;
4493 if (input_line_pointer != end)
4494 {
4495 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4496 sparc_cons_special_reloc, size * 8);
4497 }
4498 else
4499 {
4500 input_line_pointer++;
4501 SKIP_WHITESPACE ();
4502 c = *input_line_pointer;
4503 if (! is_end_of_line[c] && c != ',')
4504 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4505 sparc_cons_special_reloc, size * 8);
4506 }
4507 }
4508 }
4509 }
4510 }
4511 if (sparc_cons_special_reloc == NULL)
4512 expression (exp);
4513 }
4514
4515 #endif
4516
4517 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4518 reloc for a cons. We could use the definition there, except that
4519 we want to handle little endian relocs specially. */
4520
4521 void
4522 cons_fix_new_sparc (frag, where, nbytes, exp)
4523 fragS *frag;
4524 int where;
4525 unsigned int nbytes;
4526 expressionS *exp;
4527 {
4528 bfd_reloc_code_real_type r;
4529
4530 r = (nbytes == 1 ? BFD_RELOC_8 :
4531 (nbytes == 2 ? BFD_RELOC_16 :
4532 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4533
4534 if (target_little_endian_data
4535 && nbytes == 4
4536 && now_seg->flags & SEC_ALLOC)
4537 r = BFD_RELOC_SPARC_REV32;
4538
4539 if (sparc_cons_special_reloc)
4540 {
4541 if (*sparc_cons_special_reloc == 'd')
4542 switch (nbytes)
4543 {
4544 case 1: r = BFD_RELOC_8_PCREL; break;
4545 case 2: r = BFD_RELOC_16_PCREL; break;
4546 case 4: r = BFD_RELOC_32_PCREL; break;
4547 case 8: r = BFD_RELOC_64_PCREL; break;
4548 default: abort ();
4549 }
4550 else if (*sparc_cons_special_reloc == 'p')
4551 switch (nbytes)
4552 {
4553 case 4: r = BFD_RELOC_SPARC_PLT32; break;
4554 case 8: r = BFD_RELOC_SPARC_PLT64; break;
4555 }
4556 else
4557 switch (nbytes)
4558 {
4559 case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break;
4560 case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break;
4561 }
4562 }
4563 else if (sparc_no_align_cons)
4564 {
4565 switch (nbytes)
4566 {
4567 case 2: r = BFD_RELOC_SPARC_UA16; break;
4568 case 4: r = BFD_RELOC_SPARC_UA32; break;
4569 case 8: r = BFD_RELOC_SPARC_UA64; break;
4570 default: abort ();
4571 }
4572 }
4573
4574 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
4575 sparc_cons_special_reloc = NULL;
4576 }
4577
4578 void
4579 sparc_cfi_frame_initial_instructions ()
4580 {
4581 cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0);
4582 }
4583
4584 int
4585 sparc_regname_to_dw2regnum (const char *regname)
4586 {
4587 char *p, *q;
4588
4589 if (!regname[0])
4590 return -1;
4591
4592 q = "goli";
4593 p = strchr (q, regname[0]);
4594 if (p)
4595 {
4596 if (regname[1] < '0' || regname[1] > '8' || regname[2])
4597 return -1;
4598 return (p - q) * 8 + regname[1] - '0';
4599 }
4600 if (regname[0] == 's' && regname[1] == 'p' && !regname[2])
4601 return 14;
4602 if (regname[0] == 'f' && regname[1] == 'p' && !regname[2])
4603 return 30;
4604 if (regname[0] == 'f' || regname[0] == 'r')
4605 {
4606 unsigned int regnum;
4607
4608 regnum = strtoul (regname + 1, &q, 10);
4609 if (p == q || *q)
4610 return -1;
4611 if (regnum >= ((regname[0] == 'f'
4612 && SPARC_OPCODE_ARCH_V9_P (max_architecture))
4613 ? 64 : 32))
4614 return -1;
4615 if (regname[0] == 'f')
4616 {
4617 regnum += 32;
4618 if (regnum >= 64 && (regnum & 1))
4619 return -1;
4620 }
4621 return regnum;
4622 }
4623 return -1;
4624 }
4625
4626 void
4627 sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes)
4628 {
4629 sparc_cons_special_reloc = "disp";
4630 sparc_no_align_cons = 1;
4631 emit_expr (exp, nbytes);
4632 sparc_no_align_cons = 0;
4633 sparc_cons_special_reloc = NULL;
4634 }
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