opcodes/xstormy16-opc.c

   1 /* Instruction opcode table for xstormy16.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #include "sysdep.h"
  26 #include "ansidecl.h"
  27 #include "bfd.h"
  28 #include "symcat.h"
  29 #include "xstormy16-desc.h"
  30 #include "xstormy16-opc.h"
  31 #include "libiberty.h"
  32
  33 /* The hash functions are recorded here to help keep assembler code out of
  34    the disassembler and vice versa.  */
  35
  36 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
  37 static unsigned int asm_hash_insn PARAMS ((const char *));
  38 static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
  39 static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
  40
  41 /* Instruction formats.  */
  42
  43 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
  44 #define F(f) & xstormy16_cgen_ifld_table[XSTORMY16_##f]
  45 #else
  46 #define F(f) & xstormy16_cgen_ifld_table[XSTORMY16_/**/f]
  47 #endif
  48 static const CGEN_IFMT ifmt_empty = {
  49   0, 0, 0x0, { { 0 } }
  50 };
  51
  52 static const CGEN_IFMT ifmt_movlmemimm = {
  53   32, 32, 0xfe000000, { { F (F_OP1) }, { F (F_OP2A) }, { F (F_OP2M) }, { F (F_LMEM8) }, { F (F_IMM16) }, { 0 } }
  54 };
  55
  56 static const CGEN_IFMT ifmt_movhmemimm = {
  57   32, 32, 0xfe000000, { { F (F_OP1) }, { F (F_OP2A) }, { F (F_OP2M) }, { F (F_HMEM8) }, { F (F_IMM16) }, { 0 } }
  58 };
  59
  60 static const CGEN_IFMT ifmt_movlgrmem = {
  61   16, 16, 0xf000, { { F (F_OP1) }, { F (F_RM) }, { F (F_OP2M) }, { F (F_LMEM8) }, { 0 } }
  62 };
  63
  64 static const CGEN_IFMT ifmt_movhgrmem = {
  65   16, 16, 0xf000, { { F (F_OP1) }, { F (F_RM) }, { F (F_OP2M) }, { F (F_HMEM8) }, { 0 } }
  66 };
  67
  68 static const CGEN_IFMT ifmt_movgrgri = {
  69   16, 16, 0xfe08, { { F (F_OP1) }, { F (F_OP2A) }, { F (F_OP2M) }, { F (F_RS) }, { F (F_OP4M) }, { F (F_RDM) }, { 0 } }
  70 };
  71
  72 static const CGEN_IFMT ifmt_movgrgrii = {
  73   32, 32, 0xfe08f000, { { F (F_OP1) }, { F (F_OP2A) }, { F (F_OP2M) }, { F (F_RS) }, { F (F_OP4M) }, { F (F_RDM) }, { F (F_OP5) }, { F (F_IMM12) }, { 0 } }
  74 };
  75
  76 static const CGEN_IFMT ifmt_movgrgr = {
  77   16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_RS) }, { F (F_RD) }, { 0 } }
  78 };
  79
  80 static const CGEN_IFMT ifmt_movwimm8 = {
  81   16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_IMM8) }, { 0 } }
  82 };
  83
  84 static const CGEN_IFMT ifmt_movwgrimm8 = {
  85   16, 16, 0xf100, { { F (F_OP1) }, { F (F_RM) }, { F (F_OP2M) }, { F (F_IMM8) }, { 0 } }
  86 };
  87
  88 static const CGEN_IFMT ifmt_movwgrimm16 = {
  89   32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RD) }, { F (F_IMM16) }, { 0 } }
  90 };
  91
  92 static const CGEN_IFMT ifmt_movlowgr = {
  93   16, 16, 0xfff0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RD) }, { 0 } }
  94 };
  95
  96 static const CGEN_IFMT ifmt_movfgrgrii = {
  97   32, 32, 0xfe088000, { { F (F_OP1) }, { F (F_OP2A) }, { F (F_OP2M) }, { F (F_RS) }, { F (F_OP4M) }, { F (F_RDM) }, { F (F_OP5A) }, { F (F_RB) }, { F (F_IMM12) }, { 0 } }
  98 };
  99
 100 static const CGEN_IFMT ifmt_addgrimm4 = {
 101   16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_IMM4) }, { F (F_RD) }, { 0 } }
 102 };
 103
 104 static const CGEN_IFMT ifmt_incgrimm2 = {
 105   16, 16, 0xffc0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3A) }, { F (F_IMM2) }, { F (F_RD) }, { 0 } }
 106 };
 107
 108 static const CGEN_IFMT ifmt_set1lmemimm = {
 109   16, 16, 0xf100, { { F (F_OP1) }, { F (F_IMM3) }, { F (F_OP2M) }, { F (F_LMEM8) }, { 0 } }
 110 };
 111
 112 static const CGEN_IFMT ifmt_set1hmemimm = {
 113   16, 16, 0xf100, { { F (F_OP1) }, { F (F_IMM3) }, { F (F_OP2M) }, { F (F_HMEM8) }, { 0 } }
 114 };
 115
 116 static const CGEN_IFMT ifmt_bccgrgr = {
 117   32, 32, 0xff000000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_RS) }, { F (F_RD) }, { F (F_OP5) }, { F (F_REL12) }, { 0 } }
 118 };
 119
 120 static const CGEN_IFMT ifmt_bccgrimm8 = {
 121   32, 32, 0xf1000000, { { F (F_OP1) }, { F (F_RM) }, { F (F_OP2M) }, { F (F_IMM8) }, { F (F_OP5) }, { F (F_REL12) }, { 0 } }
 122 };
 123
 124 static const CGEN_IFMT ifmt_bccimm16 = {
 125   32, 32, 0xf0000000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_REL8_4) }, { F (F_IMM16) }, { 0 } }
 126 };
 127
 128 static const CGEN_IFMT ifmt_bngrimm4 = {
 129   32, 32, 0xff00f000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_IMM4) }, { F (F_RD) }, { F (F_OP5) }, { F (F_REL12) }, { 0 } }
 130 };
 131
 132 static const CGEN_IFMT ifmt_bngrgr = {
 133   32, 32, 0xff00f000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_RS) }, { F (F_RD) }, { F (F_OP5) }, { F (F_REL12) }, { 0 } }
 134 };
 135
 136 static const CGEN_IFMT ifmt_bnlmemimm = {
 137   32, 32, 0xff008000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_LMEM8) }, { F (F_OP5A) }, { F (F_IMM3B) }, { F (F_REL12) }, { 0 } }
 138 };
 139
 140 static const CGEN_IFMT ifmt_bnhmemimm = {
 141   32, 32, 0xff008000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_HMEM8) }, { F (F_OP5A) }, { F (F_IMM3B) }, { F (F_REL12) }, { 0 } }
 142 };
 143
 144 static const CGEN_IFMT ifmt_bcc = {
 145   16, 16, 0xf000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_REL8_2) }, { 0 } }
 146 };
 147
 148 static const CGEN_IFMT ifmt_br = {
 149   16, 16, 0xf001, { { F (F_OP1) }, { F (F_REL12A) }, { F (F_OP4B) }, { 0 } }
 150 };
 151
 152 static const CGEN_IFMT ifmt_jmp = {
 153   16, 16, 0xffe0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3B) }, { F (F_RBJ) }, { F (F_RD) }, { 0 } }
 154 };
 155
 156 static const CGEN_IFMT ifmt_jmpf = {
 157   32, 32, 0xff000000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_ABS24) }, { 0 } }
 158 };
 159
 160 static const CGEN_IFMT ifmt_iret = {
 161   16, 16, 0xffff, { { F (F_OP) }, { 0 } }
 162 };
 163
 164 #undef F
 165
 166 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 167 #define A(a) (1 << CGEN_INSN_##a)
 168 #else
 169 #define A(a) (1 << CGEN_INSN_/**/a)
 170 #endif
 171 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 172 #define OPERAND(op) XSTORMY16_OPERAND_##op
 173 #else
 174 #define OPERAND(op) XSTORMY16_OPERAND_/**/op
 175 #endif
 176 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
 177 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 178
 179 /* The instruction table.  */
 180
 181 static const CGEN_OPCODE xstormy16_cgen_insn_opcode_table[MAX_INSNS] =
 182 {
 183   /* Special null first entry.
 184      A `num' value of zero is thus invalid.
 185      Also, the special `invalid' insn resides here.  */
 186   { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
 187 /* mov$ws2 $lmem8,#$imm16 */
 188   {
 189     { 0, 0, 0, 0 },
 190     { { MNEM, OP (WS2), ' ', OP (LMEM8), ',', '#', OP (IMM16), 0 } },
 191     & ifmt_movlmemimm, { 0x78000000 }
 192   },
 193 /* mov$ws2 $hmem8,#$imm16 */
 194   {
 195     { 0, 0, 0, 0 },
 196     { { MNEM, OP (WS2), ' ', OP (HMEM8), ',', '#', OP (IMM16), 0 } },
 197     & ifmt_movhmemimm, { 0x7a000000 }
 198   },
 199 /* mov$ws2 $Rm,$lmem8 */
 200   {
 201     { 0, 0, 0, 0 },
 202     { { MNEM, OP (WS2), ' ', OP (RM), ',', OP (LMEM8), 0 } },
 203     & ifmt_movlgrmem, { 0x8000 }
 204   },
 205 /* mov$ws2 $Rm,$hmem8 */
 206   {
 207     { 0, 0, 0, 0 },
 208     { { MNEM, OP (WS2), ' ', OP (RM), ',', OP (HMEM8), 0 } },
 209     & ifmt_movhgrmem, { 0xa000 }
 210   },
 211 /* mov$ws2 $lmem8,$Rm */
 212   {
 213     { 0, 0, 0, 0 },
 214     { { MNEM, OP (WS2), ' ', OP (LMEM8), ',', OP (RM), 0 } },
 215     & ifmt_movlgrmem, { 0x9000 }
 216   },
 217 /* mov$ws2 $hmem8,$Rm */
 218   {
 219     { 0, 0, 0, 0 },
 220     { { MNEM, OP (WS2), ' ', OP (HMEM8), ',', OP (RM), 0 } },
 221     & ifmt_movhgrmem, { 0xb000 }
 222   },
 223 /* mov$ws2 $Rdm,($Rs) */
 224   {
 225     { 0, 0, 0, 0 },
 226     { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), ')', 0 } },
 227     & ifmt_movgrgri, { 0x7000 }
 228   },
 229 /* mov$ws2 $Rdm,($Rs++) */
 230   {
 231     { 0, 0, 0, 0 },
 232     { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), '+', '+', ')', 0 } },
 233     & ifmt_movgrgri, { 0x6000 }
 234   },
 235 /* mov$ws2 $Rdm,(--$Rs) */
 236   {
 237     { 0, 0, 0, 0 },
 238     { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', '-', '-', OP (RS), ')', 0 } },
 239     & ifmt_movgrgri, { 0x6800 }
 240   },
 241 /* mov$ws2 ($Rs),$Rdm */
 242   {
 243     { 0, 0, 0, 0 },
 244     { { MNEM, OP (WS2), ' ', '(', OP (RS), ')', ',', OP (RDM), 0 } },
 245     & ifmt_movgrgri, { 0x7200 }
 246   },
 247 /* mov$ws2 ($Rs++),$Rdm */
 248   {
 249     { 0, 0, 0, 0 },
 250     { { MNEM, OP (WS2), ' ', '(', OP (RS), '+', '+', ')', ',', OP (RDM), 0 } },
 251     & ifmt_movgrgri, { 0x6200 }
 252   },
 253 /* mov$ws2 (--$Rs),$Rdm */
 254   {
 255     { 0, 0, 0, 0 },
 256     { { MNEM, OP (WS2), ' ', '(', '-', '-', OP (RS), ')', ',', OP (RDM), 0 } },
 257     & ifmt_movgrgri, { 0x6a00 }
 258   },
 259 /* mov$ws2 $Rdm,($Rs,$imm12) */
 260   {
 261     { 0, 0, 0, 0 },
 262     { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), ',', OP (IMM12), ')', 0 } },
 263     & ifmt_movgrgrii, { 0x70080000 }
 264   },
 265 /* mov$ws2 $Rdm,($Rs++,$imm12) */
 266   {
 267     { 0, 0, 0, 0 },
 268     { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), '+', '+', ',', OP (IMM12), ')', 0 } },
 269     & ifmt_movgrgrii, { 0x60080000 }
 270   },
 271 /* mov$ws2 $Rdm,(--$Rs,$imm12) */
 272   {
 273     { 0, 0, 0, 0 },
 274     { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', '-', '-', OP (RS), ',', OP (IMM12), ')', 0 } },
 275     & ifmt_movgrgrii, { 0x68080000 }
 276   },
 277 /* mov$ws2 ($Rs,$imm12),$Rdm */
 278   {
 279     { 0, 0, 0, 0 },
 280     { { MNEM, OP (WS2), ' ', '(', OP (RS), ',', OP (IMM12), ')', ',', OP (RDM), 0 } },
 281     & ifmt_movgrgrii, { 0x72080000 }
 282   },
 283 /* mov$ws2 ($Rs++,$imm12),$Rdm */
 284   {
 285     { 0, 0, 0, 0 },
 286     { { MNEM, OP (WS2), ' ', '(', OP (RS), '+', '+', ',', OP (IMM12), ')', ',', OP (RDM), 0 } },
 287     & ifmt_movgrgrii, { 0x62080000 }
 288   },
 289 /* mov$ws2 (--$Rs,$imm12),$Rdm */
 290   {
 291     { 0, 0, 0, 0 },
 292     { { MNEM, OP (WS2), ' ', '(', '-', '-', OP (RS), ',', OP (IMM12), ')', ',', OP (RDM), 0 } },
 293     & ifmt_movgrgrii, { 0x6a080000 }
 294   },
 295 /* mov $Rd,$Rs */
 296   {
 297     { 0, 0, 0, 0 },
 298     { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
 299     & ifmt_movgrgr, { 0x4600 }
 300   },
 301 /* mov.w Rx,#$imm8 */
 302   {
 303     { 0, 0, 0, 0 },
 304     { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } },
 305     & ifmt_movwimm8, { 0x4700 }
 306   },
 307 /* mov.w $Rm,#$imm8small */
 308   {
 309     { 0, 0, 0, 0 },
 310     { { MNEM, ' ', OP (RM), ',', '#', OP (IMM8SMALL), 0 } },
 311     & ifmt_movwgrimm8, { 0x2100 }
 312   },
 313 /* mov.w $Rd,#$imm16 */
 314   {
 315     { 0, 0, 0, 0 },
 316     { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } },
 317     & ifmt_movwgrimm16, { 0x31300000 }
 318   },
 319 /* mov.b $Rd,RxL */
 320   {
 321     { 0, 0, 0, 0 },
 322     { { MNEM, ' ', OP (RD), ',', 'R', 'x', 'L', 0 } },
 323     & ifmt_movlowgr, { 0x30c0 }
 324   },
 325 /* mov.b $Rd,RxH */
 326   {
 327     { 0, 0, 0, 0 },
 328     { { MNEM, ' ', OP (RD), ',', 'R', 'x', 'H', 0 } },
 329     & ifmt_movlowgr, { 0x30d0 }
 330   },
 331 /* movf$ws2 $Rdm,($Rs) */
 332   {
 333     { 0, 0, 0, 0 },
 334     { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), ')', 0 } },
 335     & ifmt_movgrgri, { 0x7400 }
 336   },
 337 /* movf$ws2 $Rdm,($Rs++) */
 338   {
 339     { 0, 0, 0, 0 },
 340     { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), '+', '+', ')', 0 } },
 341     & ifmt_movgrgri, { 0x6400 }
 342   },
 343 /* movf$ws2 $Rdm,(--$Rs) */
 344   {
 345     { 0, 0, 0, 0 },
 346     { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', '-', '-', OP (RS), ')', 0 } },
 347     & ifmt_movgrgri, { 0x6c00 }
 348   },
 349 /* movf$ws2 ($Rs),$Rdm */
 350   {
 351     { 0, 0, 0, 0 },
 352     { { MNEM, OP (WS2), ' ', '(', OP (RS), ')', ',', OP (RDM), 0 } },
 353     & ifmt_movgrgri, { 0x7600 }
 354   },
 355 /* movf$ws2 ($Rs++),$Rdm */
 356   {
 357     { 0, 0, 0, 0 },
 358     { { MNEM, OP (WS2), ' ', '(', OP (RS), '+', '+', ')', ',', OP (RDM), 0 } },
 359     & ifmt_movgrgri, { 0x6600 }
 360   },
 361 /* movf$ws2 (--$Rs),$Rdm */
 362   {
 363     { 0, 0, 0, 0 },
 364     { { MNEM, OP (WS2), ' ', '(', '-', '-', OP (RS), ')', ',', OP (RDM), 0 } },
 365     & ifmt_movgrgri, { 0x6e00 }
 366   },
 367 /* movf$ws2 $Rdm,($Rb,$Rs,$imm12) */
 368   {
 369     { 0, 0, 0, 0 },
 370     { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RB), ',', OP (RS), ',', OP (IMM12), ')', 0 } },
 371     & ifmt_movfgrgrii, { 0x74080000 }
 372   },
 373 /* movf$ws2 $Rdm,($Rb,$Rs++,$imm12) */
 374   {
 375     { 0, 0, 0, 0 },
 376     { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RB), ',', OP (RS), '+', '+', ',', OP (IMM12), ')', 0 } },
 377     & ifmt_movfgrgrii, { 0x64080000 }
 378   },
 379 /* movf$ws2 $Rdm,($Rb,--$Rs,$imm12) */
 380   {
 381     { 0, 0, 0, 0 },
 382     { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RB), ',', '-', '-', OP (RS), ',', OP (IMM12), ')', 0 } },
 383     & ifmt_movfgrgrii, { 0x6c080000 }
 384   },
 385 /* movf$ws2 ($Rb,$Rs,$imm12),$Rdm */
 386   {
 387     { 0, 0, 0, 0 },
 388     { { MNEM, OP (WS2), ' ', '(', OP (RB), ',', OP (RS), ',', OP (IMM12), ')', ',', OP (RDM), 0 } },
 389     & ifmt_movfgrgrii, { 0x76080000 }
 390   },
 391 /* movf$ws2 ($Rb,$Rs++,$imm12),$Rdm */
 392   {
 393     { 0, 0, 0, 0 },
 394     { { MNEM, OP (WS2), ' ', '(', OP (RB), ',', OP (RS), '+', '+', ',', OP (IMM12), ')', ',', OP (RDM), 0 } },
 395     & ifmt_movfgrgrii, { 0x66080000 }
 396   },
 397 /* movf$ws2 ($Rb,--$Rs,$imm12),$Rdm */
 398   {
 399     { 0, 0, 0, 0 },
 400     { { MNEM, OP (WS2), ' ', '(', OP (RB), ',', '-', '-', OP (RS), ',', OP (IMM12), ')', ',', OP (RDM), 0 } },
 401     & ifmt_movfgrgrii, { 0x6e080000 }
 402   },
 403 /* mask $Rd,$Rs */
 404   {
 405     { 0, 0, 0, 0 },
 406     { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
 407     & ifmt_movgrgr, { 0x3300 }
 408   },
 409 /* mask $Rd,#$imm16 */
 410   {
 411     { 0, 0, 0, 0 },
 412     { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } },
 413     & ifmt_movwgrimm16, { 0x30e00000 }
 414   },
 415 /* push $Rd */
 416   {
 417     { 0, 0, 0, 0 },
 418     { { MNEM, ' ', OP (RD), 0 } },
 419     & ifmt_movlowgr, { 0x80 }
 420   },
 421 /* pop $Rd */
 422   {
 423     { 0, 0, 0, 0 },
 424     { { MNEM, ' ', OP (RD), 0 } },
 425     & ifmt_movlowgr, { 0x90 }
 426   },
 427 /* swpn $Rd */
 428   {
 429     { 0, 0, 0, 0 },
 430     { { MNEM, ' ', OP (RD), 0 } },
 431     & ifmt_movlowgr, { 0x3090 }
 432   },
 433 /* swpb $Rd */
 434   {
 435     { 0, 0, 0, 0 },
 436     { { MNEM, ' ', OP (RD), 0 } },
 437     & ifmt_movlowgr, { 0x3080 }
 438   },
 439 /* swpw $Rd,$Rs */
 440   {
 441     { 0, 0, 0, 0 },
 442     { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
 443     & ifmt_movgrgr, { 0x3200 }
 444   },
 445 /* and $Rd,$Rs */
 446   {
 447     { 0, 0, 0, 0 },
 448     { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
 449     & ifmt_movgrgr, { 0x4000 }
 450   },
 451 /* and Rx,#$imm8 */
 452   {
 453     { 0, 0, 0, 0 },
 454     { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } },
 455     & ifmt_movwimm8, { 0x4100 }
 456   },
 457 /* and $Rd,#$imm16 */
 458   {
 459     { 0, 0, 0, 0 },
 460     { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } },
 461     & ifmt_movwgrimm16, { 0x31000000 }
 462   },
 463 /* or $Rd,$Rs */
 464   {
 465     { 0, 0, 0, 0 },
 466     { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
 467     & ifmt_movgrgr, { 0x4200 }
 468   },
 469 /* or Rx,#$imm8 */
 470   {
 471     { 0, 0, 0, 0 },
 472     { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } },
 473     & ifmt_movwimm8, { 0x4300 }
 474   },
 475 /* or $Rd,#$imm16 */
 476   {
 477     { 0, 0, 0, 0 },
 478     { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } },
 479     & ifmt_movwgrimm16, { 0x31100000 }
 480   },
 481 /* xor $Rd,$Rs */
 482   {
 483     { 0, 0, 0, 0 },
 484     { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
 485     & ifmt_movgrgr, { 0x4400 }
 486   },
 487 /* xor Rx,#$imm8 */
 488   {
 489     { 0, 0, 0, 0 },
 490     { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } },
 491     & ifmt_movwimm8, { 0x4500 }
 492   },
 493 /* xor $Rd,#$imm16 */
 494   {
 495     { 0, 0, 0, 0 },
 496     { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } },
 497     & ifmt_movwgrimm16, { 0x31200000 }
 498   },
 499 /* not $Rd */
 500   {
 501     { 0, 0, 0, 0 },
 502     { { MNEM, ' ', OP (RD), 0 } },
 503     & ifmt_movlowgr, { 0x30b0 }
 504   },
 505 /* add $Rd,$Rs */
 506   {
 507     { 0, 0, 0, 0 },
 508     { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
 509     & ifmt_movgrgr, { 0x4900 }
 510   },
 511 /* add $Rd,#$imm4 */
 512   {
 513     { 0, 0, 0, 0 },
 514     { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } },
 515     & ifmt_addgrimm4, { 0x5100 }
 516   },
 517 /* add Rx,#$imm8 */
 518   {
 519     { 0, 0, 0, 0 },
 520     { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } },
 521     & ifmt_movwimm8, { 0x5900 }
 522   },
 523 /* add $Rd,#$imm16 */
 524   {
 525     { 0, 0, 0, 0 },
 526     { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } },
 527     & ifmt_movwgrimm16, { 0x31400000 }
 528   },
 529 /* adc $Rd,$Rs */
 530   {
 531     { 0, 0, 0, 0 },
 532     { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
 533     & ifmt_movgrgr, { 0x4b00 }
 534   },
 535 /* adc $Rd,#$imm4 */
 536   {
 537     { 0, 0, 0, 0 },
 538     { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } },
 539     & ifmt_addgrimm4, { 0x5300 }
 540   },
 541 /* adc Rx,#$imm8 */
 542   {
 543     { 0, 0, 0, 0 },
 544     { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } },
 545     & ifmt_movwimm8, { 0x5b00 }
 546   },
 547 /* adc $Rd,#$imm16 */
 548   {
 549     { 0, 0, 0, 0 },
 550     { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } },
 551     & ifmt_movwgrimm16, { 0x31500000 }
 552   },
 553 /* sub $Rd,$Rs */
 554   {
 555     { 0, 0, 0, 0 },
 556     { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
 557     & ifmt_movgrgr, { 0x4d00 }
 558   },
 559 /* sub $Rd,#$imm4 */
 560   {
 561     { 0, 0, 0, 0 },
 562     { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } },
 563     & ifmt_addgrimm4, { 0x5500 }
 564   },
 565 /* sub Rx,#$imm8 */
 566   {
 567     { 0, 0, 0, 0 },
 568     { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } },
 569     & ifmt_movwimm8, { 0x5d00 }
 570   },
 571 /* sub $Rd,#$imm16 */
 572   {
 573     { 0, 0, 0, 0 },
 574     { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } },
 575     & ifmt_movwgrimm16, { 0x31600000 }
 576   },
 577 /* sbc $Rd,$Rs */
 578   {
 579     { 0, 0, 0, 0 },
 580     { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
 581     & ifmt_movgrgr, { 0x4f00 }
 582   },
 583 /* sbc $Rd,#$imm4 */
 584   {
 585     { 0, 0, 0, 0 },
 586     { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } },
 587     & ifmt_addgrimm4, { 0x5700 }
 588   },
 589 /* sbc Rx,#$imm8 */
 590   {
 591     { 0, 0, 0, 0 },
 592     { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } },
 593     & ifmt_movwimm8, { 0x5f00 }
 594   },
 595 /* sbc $Rd,#$imm16 */
 596   {
 597     { 0, 0, 0, 0 },
 598     { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } },
 599     & ifmt_movwgrimm16, { 0x31700000 }
 600   },
 601 /* inc $Rd,#$imm2 */
 602   {
 603     { 0, 0, 0, 0 },
 604     { { MNEM, ' ', OP (RD), ',', '#', OP (IMM2), 0 } },
 605     & ifmt_incgrimm2, { 0x3000 }
 606   },
 607 /* dec $Rd,#$imm2 */
 608   {
 609     { 0, 0, 0, 0 },
 610     { { MNEM, ' ', OP (RD), ',', '#', OP (IMM2), 0 } },
 611     & ifmt_incgrimm2, { 0x3040 }
 612   },
 613 /* rrc $Rd,$Rs */
 614   {
 615     { 0, 0, 0, 0 },
 616     { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
 617     & ifmt_movgrgr, { 0x3800 }
 618   },
 619 /* rrc $Rd,#$imm4 */
 620   {
 621     { 0, 0, 0, 0 },
 622     { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } },
 623     & ifmt_addgrimm4, { 0x3900 }
 624   },
 625 /* rlc $Rd,$Rs */
 626   {
 627     { 0, 0, 0, 0 },
 628     { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
 629     & ifmt_movgrgr, { 0x3a00 }
 630   },
 631 /* rlc $Rd,#$imm4 */
 632   {
 633     { 0, 0, 0, 0 },
 634     { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } },
 635     & ifmt_addgrimm4, { 0x3b00 }
 636   },
 637 /* shr $Rd,$Rs */
 638   {
 639     { 0, 0, 0, 0 },
 640     { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
 641     & ifmt_movgrgr, { 0x3c00 }
 642   },
 643 /* shr $Rd,#$imm4 */
 644   {
 645     { 0, 0, 0, 0 },
 646     { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } },
 647     & ifmt_addgrimm4, { 0x3d00 }
 648   },
 649 /* shl $Rd,$Rs */
 650   {
 651     { 0, 0, 0, 0 },
 652     { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
 653     & ifmt_movgrgr, { 0x3e00 }
 654   },
 655 /* shl $Rd,#$imm4 */
 656   {
 657     { 0, 0, 0, 0 },
 658     { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } },
 659     & ifmt_addgrimm4, { 0x3f00 }
 660   },
 661 /* asr $Rd,$Rs */
 662   {
 663     { 0, 0, 0, 0 },
 664     { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
 665     & ifmt_movgrgr, { 0x3600 }
 666   },
 667 /* asr $Rd,#$imm4 */
 668   {
 669     { 0, 0, 0, 0 },
 670     { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } },
 671     & ifmt_addgrimm4, { 0x3700 }
 672   },
 673 /* set1 $Rd,#$imm4 */
 674   {
 675     { 0, 0, 0, 0 },
 676     { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } },
 677     & ifmt_addgrimm4, { 0x900 }
 678   },
 679 /* set1 $Rd,$Rs */
 680   {
 681     { 0, 0, 0, 0 },
 682     { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
 683     & ifmt_movgrgr, { 0xb00 }
 684   },
 685 /* set1 $lmem8,#$imm3 */
 686   {
 687     { 0, 0, 0, 0 },
 688     { { MNEM, ' ', OP (LMEM8), ',', '#', OP (IMM3), 0 } },
 689     & ifmt_set1lmemimm, { 0xe100 }
 690   },
 691 /* set1 $hmem8,#$imm3 */
 692   {
 693     { 0, 0, 0, 0 },
 694     { { MNEM, ' ', OP (HMEM8), ',', '#', OP (IMM3), 0 } },
 695     & ifmt_set1hmemimm, { 0xf100 }
 696   },
 697 /* clr1 $Rd,#$imm4 */
 698   {
 699     { 0, 0, 0, 0 },
 700     { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } },
 701     & ifmt_addgrimm4, { 0x800 }
 702   },
 703 /* clr1 $Rd,$Rs */
 704   {
 705     { 0, 0, 0, 0 },
 706     { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
 707     & ifmt_movgrgr, { 0xa00 }
 708   },
 709 /* clr1 $lmem8,#$imm3 */
 710   {
 711     { 0, 0, 0, 0 },
 712     { { MNEM, ' ', OP (LMEM8), ',', '#', OP (IMM3), 0 } },
 713     & ifmt_set1lmemimm, { 0xe000 }
 714   },
 715 /* clr1 $hmem8,#$imm3 */
 716   {
 717     { 0, 0, 0, 0 },
 718     { { MNEM, ' ', OP (HMEM8), ',', '#', OP (IMM3), 0 } },
 719     & ifmt_set1hmemimm, { 0xf000 }
 720   },
 721 /* cbw $Rd */
 722   {
 723     { 0, 0, 0, 0 },
 724     { { MNEM, ' ', OP (RD), 0 } },
 725     & ifmt_movlowgr, { 0x30a0 }
 726   },
 727 /* rev $Rd */
 728   {
 729     { 0, 0, 0, 0 },
 730     { { MNEM, ' ', OP (RD), 0 } },
 731     & ifmt_movlowgr, { 0x30f0 }
 732   },
 733 /* b$bcond5 $Rd,$Rs,$rel12 */
 734   {
 735     { 0, 0, 0, 0 },
 736     { { MNEM, OP (BCOND5), ' ', OP (RD), ',', OP (RS), ',', OP (REL12), 0 } },
 737     & ifmt_bccgrgr, { 0xd000000 }
 738   },
 739 /* b$bcond5 $Rm,#$imm8,$rel12 */
 740   {
 741     { 0, 0, 0, 0 },
 742     { { MNEM, OP (BCOND5), ' ', OP (RM), ',', '#', OP (IMM8), ',', OP (REL12), 0 } },
 743     & ifmt_bccgrimm8, { 0x20000000 }
 744   },
 745 /* b$bcond2 Rx,#$imm16,${rel8-4} */
 746   {
 747     { 0, 0, 0, 0 },
 748     { { MNEM, OP (BCOND2), ' ', 'R', 'x', ',', '#', OP (IMM16), ',', OP (REL8_4), 0 } },
 749     & ifmt_bccimm16, { 0xc0000000 }
 750   },
 751 /* bn $Rd,#$imm4,$rel12 */
 752   {
 753     { 0, 0, 0, 0 },
 754     { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), ',', OP (REL12), 0 } },
 755     & ifmt_bngrimm4, { 0x4000000 }
 756   },
 757 /* bn $Rd,$Rs,$rel12 */
 758   {
 759     { 0, 0, 0, 0 },
 760     { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (REL12), 0 } },
 761     & ifmt_bngrgr, { 0x6000000 }
 762   },
 763 /* bn $lmem8,#$imm3b,$rel12 */
 764   {
 765     { 0, 0, 0, 0 },
 766     { { MNEM, ' ', OP (LMEM8), ',', '#', OP (IMM3B), ',', OP (REL12), 0 } },
 767     & ifmt_bnlmemimm, { 0x7c000000 }
 768   },
 769 /* bn $hmem8,#$imm3b,$rel12 */
 770   {
 771     { 0, 0, 0, 0 },
 772     { { MNEM, ' ', OP (HMEM8), ',', '#', OP (IMM3B), ',', OP (REL12), 0 } },
 773     & ifmt_bnhmemimm, { 0x7e000000 }
 774   },
 775 /* bp $Rd,#$imm4,$rel12 */
 776   {
 777     { 0, 0, 0, 0 },
 778     { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), ',', OP (REL12), 0 } },
 779     & ifmt_bngrimm4, { 0x5000000 }
 780   },
 781 /* bp $Rd,$Rs,$rel12 */
 782   {
 783     { 0, 0, 0, 0 },
 784     { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (REL12), 0 } },
 785     & ifmt_bngrgr, { 0x7000000 }
 786   },
 787 /* bp $lmem8,#$imm3b,$rel12 */
 788   {
 789     { 0, 0, 0, 0 },
 790     { { MNEM, ' ', OP (LMEM8), ',', '#', OP (IMM3B), ',', OP (REL12), 0 } },
 791     & ifmt_bnlmemimm, { 0x7d000000 }
 792   },
 793 /* bp $hmem8,#$imm3b,$rel12 */
 794   {
 795     { 0, 0, 0, 0 },
 796     { { MNEM, ' ', OP (HMEM8), ',', '#', OP (IMM3B), ',', OP (REL12), 0 } },
 797     & ifmt_bnhmemimm, { 0x7f000000 }
 798   },
 799 /* b$bcond2 ${rel8-2} */
 800   {
 801     { 0, 0, 0, 0 },
 802     { { MNEM, OP (BCOND2), ' ', OP (REL8_2), 0 } },
 803     & ifmt_bcc, { 0xd000 }
 804   },
 805 /* br $Rd */
 806   {
 807     { 0, 0, 0, 0 },
 808     { { MNEM, ' ', OP (RD), 0 } },
 809     & ifmt_movlowgr, { 0x20 }
 810   },
 811 /* br $rel12a */
 812   {
 813     { 0, 0, 0, 0 },
 814     { { MNEM, ' ', OP (REL12A), 0 } },
 815     & ifmt_br, { 0x1000 }
 816   },
 817 /* jmp $Rbj,$Rd */
 818   {
 819     { 0, 0, 0, 0 },
 820     { { MNEM, ' ', OP (RBJ), ',', OP (RD), 0 } },
 821     & ifmt_jmp, { 0x40 }
 822   },
 823 /* jmpf $abs24 */
 824   {
 825     { 0, 0, 0, 0 },
 826     { { MNEM, ' ', OP (ABS24), 0 } },
 827     & ifmt_jmpf, { 0x2000000 }
 828   },
 829 /* callr $Rd */
 830   {
 831     { 0, 0, 0, 0 },
 832     { { MNEM, ' ', OP (RD), 0 } },
 833     & ifmt_movlowgr, { 0x10 }
 834   },
 835 /* callr $rel12a */
 836   {
 837     { 0, 0, 0, 0 },
 838     { { MNEM, ' ', OP (REL12A), 0 } },
 839     & ifmt_br, { 0x1001 }
 840   },
 841 /* call $Rbj,$Rd */
 842   {
 843     { 0, 0, 0, 0 },
 844     { { MNEM, ' ', OP (RBJ), ',', OP (RD), 0 } },
 845     & ifmt_jmp, { 0xa0 }
 846   },
 847 /* callf $abs24 */
 848   {
 849     { 0, 0, 0, 0 },
 850     { { MNEM, ' ', OP (ABS24), 0 } },
 851     & ifmt_jmpf, { 0x1000000 }
 852   },
 853 /* icallr $Rd */
 854   {
 855     { 0, 0, 0, 0 },
 856     { { MNEM, ' ', OP (RD), 0 } },
 857     & ifmt_movlowgr, { 0x30 }
 858   },
 859 /* icall $Rbj,$Rd */
 860   {
 861     { 0, 0, 0, 0 },
 862     { { MNEM, ' ', OP (RBJ), ',', OP (RD), 0 } },
 863     & ifmt_jmp, { 0x60 }
 864   },
 865 /* icallf $abs24 */
 866   {
 867     { 0, 0, 0, 0 },
 868     { { MNEM, ' ', OP (ABS24), 0 } },
 869     & ifmt_jmpf, { 0x3000000 }
 870   },
 871 /* iret */
 872   {
 873     { 0, 0, 0, 0 },
 874     { { MNEM, 0 } },
 875     & ifmt_iret, { 0x2 }
 876   },
 877 /* ret */
 878   {
 879     { 0, 0, 0, 0 },
 880     { { MNEM, 0 } },
 881     & ifmt_iret, { 0x3 }
 882   },
 883 /* mul */
 884   {
 885     { 0, 0, 0, 0 },
 886     { { MNEM, 0 } },
 887     & ifmt_iret, { 0xd0 }
 888   },
 889 /* div */
 890   {
 891     { 0, 0, 0, 0 },
 892     { { MNEM, 0 } },
 893     & ifmt_iret, { 0xc0 }
 894   },
 895 /* sdiv */
 896   {
 897     { 0, 0, 0, 0 },
 898     { { MNEM, 0 } },
 899     & ifmt_iret, { 0xc8 }
 900   },
 901 /* sdivlh */
 902   {
 903     { 0, 0, 0, 0 },
 904     { { MNEM, 0 } },
 905     & ifmt_iret, { 0xe8 }
 906   },
 907 /* divlh */
 908   {
 909     { 0, 0, 0, 0 },
 910     { { MNEM, 0 } },
 911     & ifmt_iret, { 0xe0 }
 912   },
 913 /* reset */
 914   {
 915     { 0, 0, 0, 0 },
 916     { { MNEM, 0 } },
 917     & ifmt_iret, { 0xf }
 918   },
 919 /* nop */
 920   {
 921     { 0, 0, 0, 0 },
 922     { { MNEM, 0 } },
 923     & ifmt_iret, { 0x0 }
 924   },
 925 /* halt */
 926   {
 927     { 0, 0, 0, 0 },
 928     { { MNEM, 0 } },
 929     & ifmt_iret, { 0x8 }
 930   },
 931 /* hold */
 932   {
 933     { 0, 0, 0, 0 },
 934     { { MNEM, 0 } },
 935     & ifmt_iret, { 0xa }
 936   },
 937 /* holdx */
 938   {
 939     { 0, 0, 0, 0 },
 940     { { MNEM, 0 } },
 941     & ifmt_iret, { 0xb }
 942   },
 943 /* brk */
 944   {
 945     { 0, 0, 0, 0 },
 946     { { MNEM, 0 } },
 947     & ifmt_iret, { 0x5 }
 948   },
 949 /* --unused-- */
 950   {
 951     { 0, 0, 0, 0 },
 952     { { MNEM, 0 } },
 953     & ifmt_iret, { 0x1 }
 954   },
 955 };
 956
 957 #undef A
 958 #undef OPERAND
 959 #undef MNEM
 960 #undef OP
 961
 962 /* Formats for ALIAS macro-insns.  */
 963
 964 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 965 #define F(f) & xstormy16_cgen_ifld_table[XSTORMY16_##f]
 966 #else
 967 #define F(f) & xstormy16_cgen_ifld_table[XSTORMY16_/**/f]
 968 #endif
 969 static const CGEN_IFMT ifmt_movimm8 = {
 970   16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_IMM8) }, { 0 } }
 971 };
 972
 973 static const CGEN_IFMT ifmt_movgrimm8 = {
 974   16, 16, 0xf100, { { F (F_OP1) }, { F (F_RM) }, { F (F_OP2M) }, { F (F_IMM8) }, { 0 } }
 975 };
 976
 977 static const CGEN_IFMT ifmt_movgrimm16 = {
 978   32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RD) }, { F (F_IMM16) }, { 0 } }
 979 };
 980
 981 static const CGEN_IFMT ifmt_incgr = {
 982   16, 16, 0xfff0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3A) }, { F (F_IMM2) }, { F (F_RD) }, { 0 } }
 983 };
 984
 985 static const CGEN_IFMT ifmt_decgr = {
 986   16, 16, 0xfff0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3A) }, { F (F_IMM2) }, { F (F_RD) }, { 0 } }
 987 };
 988
 989 #undef F
 990
 991 /* Each non-simple macro entry points to an array of expansion possibilities.  */
 992
 993 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 994 #define A(a) (1 << CGEN_INSN_##a)
 995 #else
 996 #define A(a) (1 << CGEN_INSN_/**/a)
 997 #endif
 998 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 999 #define OPERAND(op) XSTORMY16_OPERAND_##op
1000 #else
1001 #define OPERAND(op) XSTORMY16_OPERAND_/**/op
1002 #endif
1003 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
1004 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1005
1006 /* The macro instruction table.  */
1007
1008 static const CGEN_IBASE xstormy16_cgen_macro_insn_table[] =
1009 {
1010 /* mov Rx,#$imm8 */
1011   {
1012     -1, "movimm8", "mov", 16,
1013     { 0|A(ALIAS), { (1<<MACH_BASE) } }
1014   },
1015 /* mov $Rm,#$imm8small */
1016   {
1017     -1, "movgrimm8", "mov", 16,
1018     { 0|A(ALIAS), { (1<<MACH_BASE) } }
1019   },
1020 /* mov $Rd,#$imm16 */
1021   {
1022     -1, "movgrimm16", "mov", 32,
1023     { 0|A(ALIAS), { (1<<MACH_BASE) } }
1024   },
1025 /* inc $Rd */
1026   {
1027     -1, "incgr", "inc", 16,
1028     { 0|A(ALIAS), { (1<<MACH_BASE) } }
1029   },
1030 /* dec $Rd */
1031   {
1032     -1, "decgr", "dec", 16,
1033     { 0|A(ALIAS), { (1<<MACH_BASE) } }
1034   },
1035 };
1036
1037 /* The macro instruction opcode table.  */
1038
1039 static const CGEN_OPCODE xstormy16_cgen_macro_insn_opcode_table[] =
1040 {
1041 /* mov Rx,#$imm8 */
1042   {
1043     { 0, 0, 0, 0 },
1044     { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } },
1045     & ifmt_movimm8, { 0x4700 }
1046   },
1047 /* mov $Rm,#$imm8small */
1048   {
1049     { 0, 0, 0, 0 },
1050     { { MNEM, ' ', OP (RM), ',', '#', OP (IMM8SMALL), 0 } },
1051     & ifmt_movgrimm8, { 0x2100 }
1052   },
1053 /* mov $Rd,#$imm16 */
1054   {
1055     { 0, 0, 0, 0 },
1056     { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } },
1057     & ifmt_movgrimm16, { 0x31300000 }
1058   },
1059 /* inc $Rd */
1060   {
1061     { 0, 0, 0, 0 },
1062     { { MNEM, ' ', OP (RD), 0 } },
1063     & ifmt_incgr, { 0x3000 }
1064   },
1065 /* dec $Rd */
1066   {
1067     { 0, 0, 0, 0 },
1068     { { MNEM, ' ', OP (RD), 0 } },
1069     & ifmt_decgr, { 0x3040 }
1070   },
1071 };
1072
1073 #undef A
1074 #undef OPERAND
1075 #undef MNEM
1076 #undef OP
1077
1078 #ifndef CGEN_ASM_HASH_P
1079 #define CGEN_ASM_HASH_P(insn) 1
1080 #endif
1081
1082 #ifndef CGEN_DIS_HASH_P
1083 #define CGEN_DIS_HASH_P(insn) 1
1084 #endif
1085
1086 /* Return non-zero if INSN is to be added to the hash table.
1087    Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file.  */
1088
1089 static int
1090 asm_hash_insn_p (insn)
1091      const CGEN_INSN *insn ATTRIBUTE_UNUSED;
1092 {
1093   return CGEN_ASM_HASH_P (insn);
1094 }
1095
1096 static int
1097 dis_hash_insn_p (insn)
1098      const CGEN_INSN *insn;
1099 {
1100   /* If building the hash table and the NO-DIS attribute is present,
1101      ignore.  */
1102   if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS))
1103     return 0;
1104   return CGEN_DIS_HASH_P (insn);
1105 }
1106
1107 #ifndef CGEN_ASM_HASH
1108 #define CGEN_ASM_HASH_SIZE 127
1109 #ifdef CGEN_MNEMONIC_OPERANDS
1110 #define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
1111 #else
1112 #define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
1113 #endif
1114 #endif
1115
1116 /* It doesn't make much sense to provide a default here,
1117    but while this is under development we do.
1118    BUFFER is a pointer to the bytes of the insn, target order.
1119    VALUE is the first base_insn_bitsize bits as an int in host order.  */
1120
1121 #ifndef CGEN_DIS_HASH
1122 #define CGEN_DIS_HASH_SIZE 256
1123 #define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
1124 #endif
1125
1126 /* The result is the hash value of the insn.
1127    Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file.  */
1128
1129 static unsigned int
1130 asm_hash_insn (mnem)
1131      const char * mnem;
1132 {
1133   return CGEN_ASM_HASH (mnem);
1134 }
1135
1136 /* BUF is a pointer to the bytes of the insn, target order.
1137    VALUE is the first base_insn_bitsize bits as an int in host order.  */
1138
1139 static unsigned int
1140 dis_hash_insn (buf, value)
1141      const char * buf ATTRIBUTE_UNUSED;
1142      CGEN_INSN_INT value ATTRIBUTE_UNUSED;
1143 {
1144   return CGEN_DIS_HASH (buf, value);
1145 }
1146
1147 static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
1148
1149 /* Set the recorded length of the insn in the CGEN_FIELDS struct.  */
1150
1151 static void
1152 set_fields_bitsize (fields, size)
1153      CGEN_FIELDS *fields;
1154      int size;
1155 {
1156   CGEN_FIELDS_BITSIZE (fields) = size;
1157 }
1158
1159 /* Function to call before using the operand instance table.
1160    This plugs the opcode entries and macro instructions into the cpu table.  */
1161
1162 void
1163 xstormy16_cgen_init_opcode_table (cd)
1164      CGEN_CPU_DESC cd;
1165 {
1166   int i;
1167   int num_macros = (sizeof (xstormy16_cgen_macro_insn_table) /
1168                     sizeof (xstormy16_cgen_macro_insn_table[0]));
1169   const CGEN_IBASE *ib = & xstormy16_cgen_macro_insn_table[0];
1170   const CGEN_OPCODE *oc = & xstormy16_cgen_macro_insn_opcode_table[0];
1171   CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN));
1172   memset (insns, 0, num_macros * sizeof (CGEN_INSN));
1173   for (i = 0; i < num_macros; ++i)
1174     {
1175       insns[i].base = &ib[i];
1176       insns[i].opcode = &oc[i];
1177       xstormy16_cgen_build_insn_regex (& insns[i]);
1178     }
1179   cd->macro_insn_table.init_entries = insns;
1180   cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE);
1181   cd->macro_insn_table.num_init_entries = num_macros;
1182
1183   oc = & xstormy16_cgen_insn_opcode_table[0];
1184   insns = (CGEN_INSN *) cd->insn_table.init_entries;
1185   for (i = 0; i < MAX_INSNS; ++i)
1186     {
1187       insns[i].opcode = &oc[i];
1188       xstormy16_cgen_build_insn_regex (& insns[i]);
1189     }
1190
1191   cd->sizeof_fields = sizeof (CGEN_FIELDS);
1192   cd->set_fields_bitsize = set_fields_bitsize;
1193
1194   cd->asm_hash_p = asm_hash_insn_p;
1195   cd->asm_hash = asm_hash_insn;
1196   cd->asm_hash_size = CGEN_ASM_HASH_SIZE;
1197
1198   cd->dis_hash_p = dis_hash_insn_p;
1199   cd->dis_hash = dis_hash_insn;
1200   cd->dis_hash_size = CGEN_DIS_HASH_SIZE;
1201 }