include/opcode/ia64.h

   1 /* ia64.h -- Header file for ia64 opcode table
   2    Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com>
   3
   4    See the file HP-COPYRIGHT for additional information.  */
   5
   6 #ifndef opcode_ia64_h
   7 #define opcode_ia64_h
   8
   9 #include <sys/types.h>
  10
  11 #include <bfd.h>
  12
  13
  14 typedef BFD_HOST_U_64_BIT ia64_insn;
  15
  16 enum ia64_insn_type
  17   {
  18     IA64_TYPE_NIL = 0,  /* illegal type */
  19     IA64_TYPE_A,        /* integer alu (I- or M-unit) */
  20     IA64_TYPE_I,        /* non-alu integer (I-unit) */
  21     IA64_TYPE_M,        /* memory (M-unit) */
  22     IA64_TYPE_B,        /* branch (B-unit) */
  23     IA64_TYPE_F,        /* floating-point (F-unit) */
  24     IA64_TYPE_X,        /* long encoding (X-unit) */
  25     IA64_TYPE_DYN,      /* Dynamic opcode */
  26     IA64_NUM_TYPES
  27   };
  28
  29 enum ia64_unit
  30   {
  31     IA64_UNIT_NIL = 0,  /* illegal unit */
  32     IA64_UNIT_I,        /* integer unit */
  33     IA64_UNIT_M,        /* memory unit */
  34     IA64_UNIT_B,        /* branching unit */
  35     IA64_UNIT_F,        /* floating-point unit */
  36     IA64_UNIT_L,        /* long "unit" */
  37     IA64_UNIT_X,        /* may be integer or branch unit */
  38     IA64_NUM_UNITS
  39   };
  40
  41 /* Changes to this enumeration must be propagated to the operand table in
  42    bfd/cpu-ia64-opc.c
  43  */
  44 enum ia64_opnd
  45   {
  46     IA64_OPND_NIL,      /* no operand---MUST BE FIRST!*/
  47
  48     /* constants */
  49     IA64_OPND_AR_CCV,   /* application register ccv (ar.ccv) */
  50     IA64_OPND_AR_PFS,   /* application register pfs (ar.pfs) */
  51     IA64_OPND_C1,       /* the constant 1 */
  52     IA64_OPND_C8,       /* the constant 8 */
  53     IA64_OPND_C16,      /* the constant 16 */
  54     IA64_OPND_GR0,      /* gr0 */
  55     IA64_OPND_IP,       /* instruction pointer (ip) */
  56     IA64_OPND_PR,       /* predicate register (pr) */
  57     IA64_OPND_PR_ROT,   /* rotating predicate register (pr.rot) */
  58     IA64_OPND_PSR,      /* processor status register (psr) */
  59     IA64_OPND_PSR_L,    /* processor status register L (psr.l) */
  60     IA64_OPND_PSR_UM,   /* processor status register UM (psr.um) */
  61
  62     /* register operands: */
  63     IA64_OPND_AR3,      /* third application register # (bits 20-26) */
  64     IA64_OPND_B1,       /* branch register # (bits 6-8) */
  65     IA64_OPND_B2,       /* branch register # (bits 13-15) */
  66     IA64_OPND_CR3,      /* third control register # (bits 20-26) */
  67     IA64_OPND_F1,       /* first floating-point register # */
  68     IA64_OPND_F2,       /* second floating-point register # */
  69     IA64_OPND_F3,       /* third floating-point register # */
  70     IA64_OPND_F4,       /* fourth floating-point register # */
  71     IA64_OPND_P1,       /* first predicate # */
  72     IA64_OPND_P2,       /* second predicate # */
  73     IA64_OPND_R1,       /* first register # */
  74     IA64_OPND_R2,       /* second register # */
  75     IA64_OPND_R3,       /* third register # */
  76     IA64_OPND_R3_2,     /* third register # (limited to gr0-gr3) */
  77
  78     /* indirect operands: */
  79     IA64_OPND_CPUID_R3, /* cpuid[reg] */
  80     IA64_OPND_DBR_R3,   /* dbr[reg] */
  81     IA64_OPND_DTR_R3,   /* dtr[reg] */
  82     IA64_OPND_ITR_R3,   /* itr[reg] */
  83     IA64_OPND_IBR_R3,   /* ibr[reg] */
  84     IA64_OPND_MR3,      /* memory at addr of third register # */
  85     IA64_OPND_MSR_R3,   /* msr[reg] */
  86     IA64_OPND_PKR_R3,   /* pkr[reg] */
  87     IA64_OPND_PMC_R3,   /* pmc[reg] */
  88     IA64_OPND_PMD_R3,   /* pmd[reg] */
  89     IA64_OPND_RR_R3,    /* rr[reg] */
  90
  91     /* immediate operands: */
  92     IA64_OPND_CCNT5,    /* 5-bit count (31 - bits 20-24) */
  93     IA64_OPND_CNT2a,    /* 2-bit count (1 + bits 27-28) */
  94     IA64_OPND_CNT2b,    /* 2-bit count (bits 27-28): 1, 2, 3 */
  95     IA64_OPND_CNT2c,    /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */
  96     IA64_OPND_CNT5,     /* 5-bit count (bits 14-18) */
  97     IA64_OPND_CNT6,     /* 6-bit count (bits 27-32) */
  98     IA64_OPND_CPOS6a,   /* 6-bit count (63 - bits 20-25) */
  99     IA64_OPND_CPOS6b,   /* 6-bit count (63 - bits 14-19) */
 100     IA64_OPND_CPOS6c,   /* 6-bit count (63 - bits 31-36) */
 101     IA64_OPND_IMM1,     /* signed 1-bit immediate (bit 36) */
 102     IA64_OPND_IMMU2,    /* unsigned 2-bit immediate (bits 13-14) */
 103     IA64_OPND_IMMU7a,   /* unsigned 7-bit immediate (bits 13-19) */
 104     IA64_OPND_IMMU7b,   /* unsigned 7-bit immediate (bits 20-26) */
 105     IA64_OPND_SOF,      /* 8-bit stack frame size */
 106     IA64_OPND_SOL,      /* 8-bit size of locals */
 107     IA64_OPND_SOR,      /* 6-bit number of rotating registers (scaled by 8) */
 108     IA64_OPND_IMM8,     /* signed 8-bit immediate (bits 13-19 & 36) */
 109     IA64_OPND_IMM8U4,   /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */
 110     IA64_OPND_IMM8M1,   /* signed 8-bit immediate -1 (bits 13-19 & 36) */
 111     IA64_OPND_IMM8M1U4, /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/
 112     IA64_OPND_IMM8M1U8, /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */
 113     IA64_OPND_IMMU9,    /* unsigned 9-bit immediate (bits 33-34, 20-26) */
 114     IA64_OPND_IMM9a,    /* signed 9-bit immediate (bits 6-12, 27, 36) */
 115     IA64_OPND_IMM9b,    /* signed 9-bit immediate (bits 13-19, 27, 36) */
 116     IA64_OPND_IMM14,    /* signed 14-bit immediate (bits 13-19, 27-32, 36) */
 117     IA64_OPND_IMM17,    /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */
 118     IA64_OPND_IMMU21,   /* unsigned 21-bit immediate (bits 6-25, 36) */
 119     IA64_OPND_IMM22,    /* signed 22-bit immediate (bits 13-19, 22-36) */
 120     IA64_OPND_IMMU24,   /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */
 121     IA64_OPND_IMM44,    /* signed 44-bit immediate (2^16*bits 6-32, 36) */
 122     IA64_OPND_IMMU62,   /* unsigned 62-bit immediate */
 123     IA64_OPND_IMMU64,   /* unsigned 64-bit immediate (lotsa bits...) */
 124     IA64_OPND_INC3,     /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */
 125     IA64_OPND_LEN4,     /* 4-bit count (bits 27-30 + 1) */
 126     IA64_OPND_LEN6,     /* 6-bit count (bits 27-32 + 1) */
 127     IA64_OPND_MBTYPE4,  /* 4-bit mux type (bits 20-23) */
 128     IA64_OPND_MHTYPE8,  /* 8-bit mux type (bits 20-27) */
 129     IA64_OPND_POS6,     /* 6-bit count (bits 14-19) */
 130     IA64_OPND_TAG13,    /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */
 131     IA64_OPND_TAG13b,   /* signed 13-bit tag (ip + 16*bits 24-32) */
 132     IA64_OPND_TGT25,    /* signed 25-bit (ip + 16*bits 6-25, 36) */
 133     IA64_OPND_TGT25b,   /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */
 134     IA64_OPND_TGT25c,   /* signed 25-bit (ip + 16*bits 13-32, 36) */
 135     IA64_OPND_TGT64,    /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */
 136
 137     IA64_OPND_COUNT     /* # of operand types (MUST BE LAST!) */
 138   };
 139
 140 enum ia64_dependency_mode
 141 {
 142   IA64_DV_RAW,
 143   IA64_DV_WAW,
 144   IA64_DV_WAR,
 145 };
 146
 147 enum ia64_dependency_semantics
 148 {
 149   IA64_DVS_NONE,
 150   IA64_DVS_IMPLIED,
 151   IA64_DVS_IMPLIEDF,
 152   IA64_DVS_DATA,
 153   IA64_DVS_INSTR,
 154   IA64_DVS_SPECIFIC,
 155   IA64_DVS_OTHER,
 156 };
 157
 158 enum ia64_resource_specifier
 159 {
 160   IA64_RS_ANY,
 161   IA64_RS_AR_K,
 162   IA64_RS_AR_UNAT,
 163   IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */
 164   IA64_RS_ARb, /* 48-63, 112-127 */
 165   IA64_RS_BR,
 166   IA64_RS_CFM,
 167   IA64_RS_CPUID,
 168   IA64_RS_CR_IRR,
 169   IA64_RS_CR_LRR,
 170   IA64_RS_CR, /* 3-7,10-15,18,26-63,75-79,82-127 */
 171   IA64_RS_DBR,
 172   IA64_RS_FR,
 173   IA64_RS_FRb,
 174   IA64_RS_GR0,
 175   IA64_RS_GR,
 176   IA64_RS_IBR,
 177   IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */
 178   IA64_RS_MSR,
 179   IA64_RS_PKR,
 180   IA64_RS_PMC,
 181   IA64_RS_PMD,
 182   IA64_RS_PR,
 183   IA64_RS_PR63,
 184   IA64_RS_RR,
 185
 186   IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */
 187   IA64_RS_CRX, /* CRs not in RS_CR */
 188   IA64_RS_PSR, /* PSR bits */
 189   IA64_RS_RSE, /* implementation-specific RSE resources */
 190   IA64_RS_AR_FPSR,
 191 };
 192
 193 enum ia64_rse_resource
 194 {
 195   IA64_RSE_N_STACKED_PHYS,
 196   IA64_RSE_BOF,
 197   IA64_RSE_STORE_REG,
 198   IA64_RSE_LOAD_REG,
 199   IA64_RSE_BSPLOAD,
 200   IA64_RSE_RNATBITINDEX,
 201   IA64_RSE_CFLE,
 202   IA64_RSE_NDIRTY,
 203 };
 204
 205 /* Information about a given resource dependency */
 206 struct ia64_dependency
 207 {
 208   /* Name of the resource */
 209   const char *name;
 210   /* Does this dependency need further specification? */
 211   enum ia64_resource_specifier specifier;
 212   /* Mode of dependency */
 213   enum ia64_dependency_mode mode;
 214   /* Dependency semantics */
 215   enum ia64_dependency_semantics semantics;
 216   /* Register index, if applicable (distinguishes AR, CR, and PSR deps) */
 217 #define REG_NONE (-1)
 218   int regindex;
 219   /* Special info on semantics */
 220   const char *info;
 221 };
 222
 223 /* Two arrays of indexes into the ia64_dependency table.
 224    chks are dependencies to check for conflicts when an opcode is
 225    encountered; regs are dependencies to register (mark as used) when an
 226    opcode is used.  chks correspond to readers (RAW) or writers (WAW or
 227    WAR) of a resource, while regs correspond to writers (RAW or WAW) and
 228    readers (WAR) of a resource.  */
 229 struct ia64_opcode_dependency
 230 {
 231   int nchks;
 232   const unsigned short *chks;
 233   int nregs;
 234   const unsigned short *regs;
 235 };
 236
 237 /* encode/extract the note/index for a dependency */
 238 #define RDEP(N,X) (((N)<<11)|(X))
 239 #define NOTE(X) (((X)>>11)&0x1F)
 240 #define DEP(X) ((X)&0x7FF)
 241
 242 /* A template descriptor describes the execution units that are active
 243    for each of the three slots.  It also specifies the location of
 244    instruction group boundaries that may be present between two slots.  */
 245 struct ia64_templ_desc
 246   {
 247     int group_boundary; /* 0=no boundary, 1=between slot 0 & 1, etc. */
 248     enum ia64_unit exec_unit[3];
 249     const char *name;
 250   };
 251
 252 /* The opcode table is an array of struct ia64_opcode.  */
 253
 254 struct ia64_opcode
 255   {
 256     /* The opcode name.  */
 257     const char *name;
 258
 259     /* The type of the instruction: */
 260     enum ia64_insn_type type;
 261
 262     /* Number of output operands: */
 263     int num_outputs;
 264
 265     /* The opcode itself.  Those bits which will be filled in with
 266        operands are zeroes.  */
 267     ia64_insn opcode;
 268
 269     /* The opcode mask.  This is used by the disassembler.  This is a
 270        mask containing ones indicating those bits which must match the
 271        opcode field, and zeroes indicating those bits which need not
 272        match (and are presumably filled in by operands).  */
 273     ia64_insn mask;
 274
 275     /* An array of operand codes.  Each code is an index into the
 276        operand table.  They appear in the order which the operands must
 277        appear in assembly code, and are terminated by a zero.  */
 278     enum ia64_opnd operands[5];
 279
 280     /* One bit flags for the opcode.  These are primarily used to
 281        indicate specific processors and environments support the
 282        instructions.  The defined values are listed below. */
 283     unsigned int flags;
 284
 285     /* Used by ia64_find_next_opcode (). */
 286     short ent_index;
 287
 288     /* Opcode dependencies. */
 289     const struct ia64_opcode_dependency *dependencies;
 290   };
 291
 292 /* Values defined for the flags field of a struct ia64_opcode.  */
 293
 294 #define IA64_OPCODE_FIRST       (1<<0)  /* must be first in an insn group */
 295 #define IA64_OPCODE_X_IN_MLX    (1<<1)  /* insn is allowed in X slot of MLX */
 296 #define IA64_OPCODE_LAST        (1<<2)  /* must be last in an insn group */
 297 #define IA64_OPCODE_PRIV        (1<<3)  /* privileged instruct */
 298 #define IA64_OPCODE_SLOT2       (1<<4)  /* insn allowed in slot 2 only */
 299 #define IA64_OPCODE_NO_PRED     (1<<5)  /* insn cannot be predicated */
 300 #define IA64_OPCODE_PSEUDO      (1<<6)  /* insn is a pseudo-op */
 301 #define IA64_OPCODE_F2_EQ_F3    (1<<7)  /* constraint: F2 == F3 */
 302 #define IA64_OPCODE_LEN_EQ_64MCNT       (1<<8)  /* constraint: LEN == 64-CNT */
 303 #define IA64_OPCODE_MOD_RRBS    (1<<9) /* modifies all rrbs in CFM */
 304
 305 /* A macro to extract the major opcode from an instruction.  */
 306 #define IA64_OP(i)      (((i) >> 37) & 0xf)
 307
 308 enum ia64_operand_class
 309   {
 310     IA64_OPND_CLASS_CST,        /* constant */
 311     IA64_OPND_CLASS_REG,        /* register */
 312     IA64_OPND_CLASS_IND,        /* indirect register */
 313     IA64_OPND_CLASS_ABS,        /* absolute value */
 314     IA64_OPND_CLASS_REL,        /* IP-relative value */
 315   };
 316
 317 /* The operands table is an array of struct ia64_operand.  */
 318
 319 struct ia64_operand
 320 {
 321   enum ia64_operand_class class;
 322
 323   /* Set VALUE as the operand bits for the operand of type SELF in the
 324      instruction pointed to by CODE.  If an error occurs, *CODE is not
 325      modified and the returned string describes the cause of the
 326      error.  If no error occurs, NULL is returned.  */
 327   const char *(*insert) (const struct ia64_operand *self, ia64_insn value,
 328                          ia64_insn *code);
 329
 330   /* Extract the operand bits for an operand of type SELF from
 331      instruction CODE store them in *VALUE.  If an error occurs, the
 332      cause of the error is described by the string returned.  If no
 333      error occurs, NULL is returned.  */
 334   const char *(*extract) (const struct ia64_operand *self, ia64_insn code,
 335                           ia64_insn *value);
 336
 337   /* A string whose meaning depends on the operand class.  */
 338
 339   const char *str;
 340
 341   struct bit_field
 342     {
 343       /* The number of bits in the operand.  */
 344       int bits;
 345
 346       /* How far the operand is left shifted in the instruction.  */
 347       int shift;
 348     }
 349   field[4];             /* no operand has more than this many bit-fields */
 350
 351   unsigned int flags;
 352
 353   const char *desc;     /* brief description */
 354 };
 355
 356 /* Values defined for the flags field of a struct ia64_operand.  */
 357
 358 /* Disassemble as signed decimal (instead of hex): */
 359 #define IA64_OPND_FLAG_DECIMAL_SIGNED   (1<<0)
 360 /* Disassemble as unsigned decimal (instead of hex): */
 361 #define IA64_OPND_FLAG_DECIMAL_UNSIGNED (1<<1)
 362
 363 extern const struct ia64_templ_desc ia64_templ_desc[16];
 364
 365 /* The tables are sorted by major opcode number and are otherwise in
 366    the order in which the disassembler should consider instructions.  */
 367 extern struct ia64_opcode ia64_opcodes_a[];
 368 extern struct ia64_opcode ia64_opcodes_i[];
 369 extern struct ia64_opcode ia64_opcodes_m[];
 370 extern struct ia64_opcode ia64_opcodes_b[];
 371 extern struct ia64_opcode ia64_opcodes_f[];
 372 extern struct ia64_opcode ia64_opcodes_d[];
 373
 374
 375 extern struct ia64_opcode *ia64_find_opcode (const char *name);
 376 extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *ent);
 377
 378 extern struct ia64_opcode *ia64_dis_opcode (ia64_insn insn,
 379                                             enum ia64_insn_type type);
 380
 381 extern void ia64_free_opcode (struct ia64_opcode *ent);
 382 extern const struct ia64_dependency *ia64_find_dependency (int index);
 383
 384 /* To avoid circular library dependencies, this array is implemented
 385    in bfd/cpu-ia64-opc.c: */
 386 extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT];
 387
 388 #endif /* opcode_ia64_h */