opcodes/ia64-opc-i.c

   1 /* ia64-opc-i.c -- IA-64 `I' opcode table.
   2    Copyright (C) 1998, 1999 Free Software Foundation, Inc.
   3    Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
   4
   5    This file is part of GDB, GAS, and the GNU binutils.
   6
   7    GDB, GAS, and the GNU binutils are free software; you can redistribute
   8    them and/or modify them under the terms of the GNU General Public
   9    License as published by the Free Software Foundation; either version
  10    2, or (at your option) any later version.
  11
  12    GDB, GAS, and the GNU binutils are distributed in the hope that they
  13    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15    the GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING.  If not, write to the
  19    Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  20    02111-1307, USA.  */
  21
  22 #include "ia64-opc.h"
  23
  24 #define I0      IA64_TYPE_I, 0
  25 #define I       IA64_TYPE_I, 1
  26 #define I2      IA64_TYPE_I, 2
  27
  28 /* instruction bit fields: */
  29 #define bC(x)           (((ia64_insn) ((x) & 0x1)) << 12)
  30 #define bIh(x)          (((ia64_insn) ((x) & 0x1)) << 23)
  31 #define bTa(x)          (((ia64_insn) ((x) & 0x1)) << 33)
  32 #define bTag13(x)       (((ia64_insn) ((x) & 0x1)) << 33)
  33 #define bTb(x)          (((ia64_insn) ((x) & 0x1)) << 36)
  34 #define bVc(x)          (((ia64_insn) ((x) & 0x1)) << 20)
  35 #define bVe(x)          (((ia64_insn) ((x) & 0x1)) << 32)
  36 #define bWh(x)          (((ia64_insn) ((x) & 0x3)) << 20)
  37 #define bX(x)           (((ia64_insn) ((x) & 0x1)) << 33)
  38 #define bXb(x)          (((ia64_insn) ((x) & 0x1)) << 22)
  39 #define bX2(x)          (((ia64_insn) ((x) & 0x3)) << 34)
  40 #define bX2a(x)         (((ia64_insn) ((x) & 0x3)) << 34)
  41 #define bX2b(x)         (((ia64_insn) ((x) & 0x3)) << 28)
  42 #define bX2c(x)         (((ia64_insn) ((x) & 0x3)) << 30)
  43 #define bX3(x)          (((ia64_insn) ((x) & 0x7)) << 33)
  44 #define bX6(x)          (((ia64_insn) ((x) & 0x3f)) << 27)
  45 #define bYa(x)          (((ia64_insn) ((x) & 0x1)) << 13)
  46 #define bYb(x)          (((ia64_insn) ((x) & 0x1)) << 26)
  47 #define bZa(x)          (((ia64_insn) ((x) & 0x1)) << 36)
  48 #define bZb(x)          (((ia64_insn) ((x) & 0x1)) << 33)
  49
  50 /* instruction bit masks: */
  51 #define mC      bC (-1)
  52 #define mIh     bIh (-1)
  53 #define mTa     bTa (-1)
  54 #define mTag13  bTag13 (-1)
  55 #define mTb     bTb (-1)
  56 #define mVc     bVc (-1)
  57 #define mVe     bVe (-1)
  58 #define mWh     bWh (-1)
  59 #define mX      bX (-1)
  60 #define mXb     bXb (-1)
  61 #define mX2     bX2 (-1)
  62 #define mX2a    bX2a (-1)
  63 #define mX2b    bX2b (-1)
  64 #define mX2c    bX2c (-1)
  65 #define mX3     bX3 (-1)
  66 #define mX6     bX6 (-1)
  67 #define mYa     bYa (-1)
  68 #define mYb     bYb (-1)
  69 #define mZa     bZa (-1)
  70 #define mZb     bZb (-1)
  71
  72 #define OpZaZbVeX2aX2b(a,b,c,d,e,f) \
  73         (bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f)), \
  74         (mOp | mZa | mZb | mVe | mX2a | mX2b)
  75 #define OpZaZbVeX2aX2bX2c(a,b,c,d,e,f,g) \
  76   (bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f) | bX2c (g)), \
  77         (mOp | mZa | mZb | mVe | mX2a | mX2b | mX2c)
  78 #define OpX2X(a,b,c)            (bOp (a) | bX2 (b) | bX (c)), (mOp | mX2 | mX)
  79 #define OpX2XYa(a,b,c,d)        (bOp (a) | bX2 (b) | bX (c) | bYa (d)), \
  80                                 (mOp | mX2 | mX | mYa)
  81 #define OpX2XYb(a,b,c,d)        (bOp (a) | bX2 (b) | bX (c) | bYb (d)), \
  82                                 (mOp | mX2 | mX | mYb)
  83 #define OpX2TaTbYaC(a,b,c,d,e,f) \
  84         (bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bC (f)), \
  85         (mOp | mX2 | mTa | mTb | mYa | mC)
  86 #define OpX3(a,b)               (bOp (a) | bX3 (b)), (mOp | mX3)
  87 #define OpX3X6(a,b,c)           (bOp (a) | bX3 (b) | bX6(c)), \
  88                                 (mOp | mX3 | mX6)
  89 #define OpX3XbIhWh(a,b,c,d,e) \
  90   (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e)), \
  91   (mOp | mX3 | mXb | mIh | mWh)
  92 #define OpX3XbIhWhTag13(a,b,c,d,e,f) \
  93      (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e) | bTag13 (f)), \
  94      (mOp | mX3 | mXb | mIh | mWh | mTag13)
  95
  96 struct ia64_opcode ia64_opcodes_i[] =
  97   {
  98     /* I-type instruction encodings (sorted according to major opcode) */
  99
 100     {"break.i", I0, OpX3X6 (0, 0, 0x00), {IMMU21}, X_IN_MLX},
 101     {"nop.i",   I0, OpX3X6 (0, 0, 0x01), {IMMU21}, X_IN_MLX},
 102     {"chk.s.i", I0, OpX3 (0, 1), {R2, TGT25b}},
 103
 104     {"mov", I, OpX3XbIhWhTag13 (0, 7, 0, 0, 1, 0), {B1, R2}, PSEUDO},
 105 #define MOV(a,b,c,d) \
 106     I, OpX3XbIhWh (0, a, b, c, d), {B1, R2, TAG13b}
 107     {"mov.sptk",                MOV (7, 0, 0, 0)},
 108     {"mov.sptk.imp",            MOV (7, 0, 1, 0)},
 109     {"mov",                     MOV (7, 0, 0, 1)},
 110     {"mov.imp",                 MOV (7, 0, 1, 1)},
 111     {"mov.dptk",                MOV (7, 0, 0, 2)},
 112     {"mov.dptk.imp",            MOV (7, 0, 1, 2)},
 113     {"mov.ret.sptk",            MOV (7, 1, 0, 0)},
 114     {"mov.ret.sptk.imp",        MOV (7, 1, 1, 0)},
 115     {"mov.ret",                 MOV (7, 1, 0, 1)},
 116     {"mov.ret.imp",             MOV (7, 1, 1, 1)},
 117     {"mov.ret.dptk",            MOV (7, 1, 0, 2)},
 118     {"mov.ret.dptk.imp",        MOV (7, 1, 1, 2)},
 119 #undef MOV
 120     {"mov",     I, OpX3X6 (0, 0, 0x31), {R1, B2}},
 121     {"mov",     I, OpX3 (0, 3), {PR, R2, IMM17}},
 122     {"mov",     I, OpX3 (0, 2), {PR_ROT, IMM44}},
 123     {"mov",     I, OpX3X6 (0, 0, 0x30), {R1, IP}},
 124     {"mov",     I, OpX3X6 (0, 0, 0x33), {R1, PR}},
 125     {"mov.i",   I, OpX3X6 (0, 0, 0x2a), {AR3, R2}},
 126     {"mov.i",   I, OpX3X6 (0, 0, 0x0a), {AR3, IMM8}},
 127     {"mov.i",   I, OpX3X6 (0, 0, 0x32), {R1, AR3}},
 128     {"zxt1",    I, OpX3X6 (0, 0, 0x10), {R1, R3}},
 129     {"zxt2",    I, OpX3X6 (0, 0, 0x11), {R1, R3}},
 130     {"zxt4",    I, OpX3X6 (0, 0, 0x12), {R1, R3}},
 131     {"sxt1",    I, OpX3X6 (0, 0, 0x14), {R1, R3}},
 132     {"sxt2",    I, OpX3X6 (0, 0, 0x15), {R1, R3}},
 133     {"sxt4",    I, OpX3X6 (0, 0, 0x16), {R1, R3}},
 134     {"czx1.l",  I, OpX3X6 (0, 0, 0x18), {R1, R3}},
 135     {"czx2.l",  I, OpX3X6 (0, 0, 0x19), {R1, R3}},
 136     {"czx1.r",  I, OpX3X6 (0, 0, 0x1c), {R1, R3}},
 137     {"czx2.r",  I, OpX3X6 (0, 0, 0x1d), {R1, R3}},
 138
 139     {"dep",     I, Op (4), {R1, R2, R3, CPOS6c, LEN4}},
 140
 141     {"shrp",    I, OpX2X (5, 3, 0), {R1, R2, R3, CNT6}},
 142
 143     {"shr.u",   I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6},
 144      PSEUDO | LEN_EQ_64MCNT},
 145     {"extr.u",  I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6, LEN6}},
 146
 147     {"shr",     I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6},
 148      PSEUDO | LEN_EQ_64MCNT},
 149     {"extr",    I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6, LEN6}},
 150
 151     {"shl",     I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a},
 152      PSEUDO | LEN_EQ_64MCNT},
 153     {"dep.z",   I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a, LEN6}},
 154     {"dep.z",   I, OpX2XYb (5, 1, 1, 1), {R1, IMM8, CPOS6a, LEN6}},
 155     {"dep",     I, OpX2X (5, 3, 1), {R1, IMM1, R3, CPOS6b, LEN6}},
 156 #define TBIT(a,b,c,d) \
 157         I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3, POS6}
 158 #define TBITCM(a,b,c,d) \
 159         I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3, POS6}, PSEUDO
 160     {"tbit.z",           TBIT   (0, 0, 0, 0)},
 161     {"tbit.nz",          TBITCM (0, 0, 0, 0)},
 162     {"tbit.z.unc",       TBIT   (0, 0, 0, 1)},
 163     {"tbit.nz.unc",      TBITCM (0, 0, 0, 1)},
 164     {"tbit.z.and",       TBIT   (0, 1, 0, 0)},
 165     {"tbit.nz.andcm",    TBITCM (0, 1, 0, 0)},
 166     {"tbit.nz.and",      TBIT   (0, 1, 0, 1)},
 167     {"tbit.z.andcm",     TBITCM (0, 1, 0, 1)},
 168     {"tbit.z.or",        TBIT   (1, 0, 0, 0)},
 169     {"tbit.nz.orcm",     TBITCM (1, 0, 0, 0)},
 170     {"tbit.nz.or",       TBIT   (1, 0, 0, 1)},
 171     {"tbit.z.orcm",      TBITCM (1, 0, 0, 1)},
 172     {"tbit.z.or.andcm",  TBIT   (1, 1, 0, 0)},
 173     {"tbit.nz.and.orcm", TBITCM (1, 1, 0, 0)},
 174     {"tbit.nz.or.andcm", TBIT   (1, 1, 0, 1)},
 175     {"tbit.z.and.orcm",  TBITCM (1, 1, 0, 1)},
 176 #undef TBIT
 177 #define TNAT(a,b,c,d) \
 178         I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3}
 179 #define TNATCM(a,b,c,d) \
 180         I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3}, PSEUDO
 181     {"tnat.z",           TNAT   (0, 0, 1, 0)},
 182     {"tnat.nz",          TNATCM (0, 0, 1, 0)},
 183     {"tnat.z.unc",       TNAT   (0, 0, 1, 1)},
 184     {"tnat.nz.unc",      TNATCM (0, 0, 1, 1)},
 185     {"tnat.z.and",       TNAT   (0, 1, 1, 0)},
 186     {"tnat.nz.andcm",    TNATCM (0, 1, 1, 0)},
 187     {"tnat.nz.and",      TNAT   (0, 1, 1, 1)},
 188     {"tnat.z.andcm",     TNATCM (0, 1, 1, 1)},
 189     {"tnat.z.or",        TNAT   (1, 0, 1, 0)},
 190     {"tnat.nz.orcm",     TNATCM (1, 0, 1, 0)},
 191     {"tnat.nz.or",       TNAT   (1, 0, 1, 1)},
 192     {"tnat.z.orcm",      TNATCM (1, 0, 1, 1)},
 193     {"tnat.z.or.andcm",  TNAT   (1, 1, 1, 0)},
 194     {"tnat.nz.and.orcm", TNATCM (1, 1, 1, 0)},
 195     {"tnat.nz.or.andcm", TNAT   (1, 1, 1, 1)},
 196     {"tnat.z.and.orcm",  TNATCM (1, 1, 1, 1)},
 197 #undef TNAT
 198
 199     {"pmpyshr2",   I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 3), {R1, R2, R3, CNT2c}},
 200     {"pmpyshr2.u", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 1), {R1, R2, R3, CNT2c}},
 201     {"pmpy2.r",    I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 1, 3), {R1, R2, R3}},
 202     {"pmpy2.l",    I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 3), {R1, R2, R3}},
 203     {"mix1.r",     I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 2), {R1, R2, R3}},
 204     {"mix2.r",     I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 2), {R1, R2, R3}},
 205     {"mix4.r",     I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 2), {R1, R2, R3}},
 206     {"mix1.l",     I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 2), {R1, R2, R3}},
 207     {"mix2.l",     I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 2), {R1, R2, R3}},
 208     {"mix4.l",     I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 2), {R1, R2, R3}},
 209     {"pack2.uss",  I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 0), {R1, R2, R3}},
 210     {"pack2.sss",  I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 0), {R1, R2, R3}},
 211     {"pack4.sss",  I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 0), {R1, R2, R3}},
 212     {"unpack1.h",  I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 1), {R1, R2, R3}},
 213     {"unpack2.h",  I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 1), {R1, R2, R3}},
 214     {"unpack4.h",  I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 1), {R1, R2, R3}},
 215     {"unpack1.l",  I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 1), {R1, R2, R3}},
 216     {"unpack2.l",  I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 1), {R1, R2, R3}},
 217     {"unpack4.l",  I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 1), {R1, R2, R3}},
 218     {"pmin1.u",    I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 0), {R1, R2, R3}},
 219     {"pmax1.u",    I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 1), {R1, R2, R3}},
 220     {"pmin2",      I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 0), {R1, R2, R3}},
 221     {"pmax2",      I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 1), {R1, R2, R3}},
 222     {"psad1",      I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 3, 2), {R1, R2, R3}},
 223     {"mux1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 3, 2, 2), {R1, R2, MBTYPE4}},
 224     {"mux2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 2, 2), {R1, R2, MHTYPE8}},
 225     {"pshr2",   I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 2, 0), {R1, R3, R2}},
 226     {"pshr4",   I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 2, 0), {R1, R3, R2}},
 227     {"shr",     I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 2, 0), {R1, R3, R2}},
 228     {"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 0), {R1, R3, R2}},
 229     {"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 0), {R1, R3, R2}},
 230     {"shr.u",   I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 0), {R1, R3, R2}},
 231     {"pshr2",   I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 3, 0), {R1, R3, CNT5}},
 232     {"pshr4",   I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 3, 0), {R1, R3, CNT5}},
 233     {"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 0), {R1, R3, CNT5}},
 234     {"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 1, 0), {R1, R3, CNT5}},
 235     {"pshl2",   I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 1), {R1, R2, R3}},
 236     {"pshl4",   I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 1), {R1, R2, R3}},
 237     {"shl",     I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 1), {R1, R2, R3}},
 238     {"pshl2",   I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 1, 1), {R1, R2, CCNT5}},
 239     {"pshl4",   I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 3, 1, 1), {R1, R2, CCNT5}},
 240     {"popcnt",  I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 2), {R1, R3}},
 241
 242     {0}
 243   };
 244
 245 #undef I0
 246 #undef I
 247 #undef I2
 248 #undef L
 249 #undef bC
 250 #undef bIh
 251 #undef bTa
 252 #undef bTag13
 253 #undef bTb
 254 #undef bVc
 255 #undef bVe
 256 #undef bWh
 257 #undef bX
 258 #undef bXb
 259 #undef bX2
 260 #undef bX2a
 261 #undef bX2b
 262 #undef bX2c
 263 #undef bX3
 264 #undef bX6
 265 #undef bY
 266 #undef bZa
 267 #undef bZb
 268 #undef mC
 269 #undef mIh
 270 #undef mTa
 271 #undef mTag13
 272 #undef mTb
 273 #undef mVc
 274 #undef mVe
 275 #undef mWh
 276 #undef mX
 277 #undef mXb
 278 #undef mX2
 279 #undef mX2a
 280 #undef mX2b
 281 #undef mX2c
 282 #undef mX3
 283 #undef mX6
 284 #undef mY
 285 #undef mZa
 286 #undef mZb
 287 #undef OpZaZbVeX2aX2b
 288 #undef OpZaZbVeX2aX2bX2c
 289 #undef OpX2X
 290 #undef OpX2XYa
 291 #undef OpX2XYb
 292 #undef OpX2TaTbYaC
 293 #undef OpX3
 294 #undef OpX3X6
 295 #undef OpX3XbIhWh
 296 #undef OpX3XbIhWhTag13