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[binutils.git] / gas / config / bfin-parse.y
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1 /* bfin-parse.y ADI Blackfin parser
2 Copyright 2005
3 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
21 %{
22
23 #include <stdio.h>
24 #include "bfin-aux.h"
25 #include <stdarg.h>
26 #include <obstack.h>
27
28 #define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \
29 bfin_gen_dsp32alu (HL, aopcde, aop, s, x, dst0, dst1, src0, src1)
30
31 #define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
32 bfin_gen_dsp32mac (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
33 dst, src0, src1, w0)
34
35 #define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
36 bfin_gen_dsp32mult (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
37 dst, src0, src1, w0)
38
39 #define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls) \
40 bfin_gen_dsp32shift (sopcde, dst0, src0, src1, sop, hls)
41
42 #define DSP32SHIFTIMM(sopcde, dst0, immag, src1, sop, hls) \
43 bfin_gen_dsp32shiftimm (sopcde, dst0, immag, src1, sop, hls)
44
45 #define LDIMMHALF_R(reg, h, s, z, hword) \
46 bfin_gen_ldimmhalf (reg, h, s, z, hword, 1)
47
48 #define LDIMMHALF_R5(reg, h, s, z, hword) \
49 bfin_gen_ldimmhalf (reg, h, s, z, hword, 2)
50
51 #define LDSTIDXI(ptr, reg, w, sz, z, offset) \
52 bfin_gen_ldstidxi (ptr, reg, w, sz, z, offset)
53
54 #define LDST(ptr, reg, aop, sz, z, w) \
55 bfin_gen_ldst (ptr, reg, aop, sz, z, w)
56
57 #define LDSTII(ptr, reg, offset, w, op) \
58 bfin_gen_ldstii (ptr, reg, offset, w, op)
59
60 #define DSPLDST(i, m, reg, aop, w) \
61 bfin_gen_dspldst (i, reg, aop, w, m)
62
63 #define LDSTPMOD(ptr, reg, idx, aop, w) \
64 bfin_gen_ldstpmod (ptr, reg, aop, w, idx)
65
66 #define LDSTIIFP(offset, reg, w) \
67 bfin_gen_ldstiifp (reg, offset, w)
68
69 #define LOGI2OP(dst, src, opc) \
70 bfin_gen_logi2op (opc, src, dst.regno & CODE_MASK)
71
72 #define ALU2OP(dst, src, opc) \
73 bfin_gen_alu2op (dst, src, opc)
74
75 #define BRCC(t, b, offset) \
76 bfin_gen_brcc (t, b, offset)
77
78 #define UJUMP(offset) \
79 bfin_gen_ujump (offset)
80
81 #define PROGCTRL(prgfunc, poprnd) \
82 bfin_gen_progctrl (prgfunc, poprnd)
83
84 #define PUSHPOPMULTIPLE(dr, pr, d, p, w) \
85 bfin_gen_pushpopmultiple (dr, pr, d, p, w)
86
87 #define PUSHPOPREG(reg, w) \
88 bfin_gen_pushpopreg (reg, w)
89
90 #define CALLA(addr, s) \
91 bfin_gen_calla (addr, s)
92
93 #define LINKAGE(r, framesize) \
94 bfin_gen_linkage (r, framesize)
95
96 #define COMPI2OPD(dst, src, op) \
97 bfin_gen_compi2opd (dst, src, op)
98
99 #define COMPI2OPP(dst, src, op) \
100 bfin_gen_compi2opp (dst, src, op)
101
102 #define DAGMODIK(i, op) \
103 bfin_gen_dagmodik (i, op)
104
105 #define DAGMODIM(i, m, op, br) \
106 bfin_gen_dagmodim (i, m, op, br)
107
108 #define COMP3OP(dst, src0, src1, opc) \
109 bfin_gen_comp3op (src0, src1, dst, opc)
110
111 #define PTR2OP(dst, src, opc) \
112 bfin_gen_ptr2op (dst, src, opc)
113
114 #define CCFLAG(x, y, opc, i, g) \
115 bfin_gen_ccflag (x, y, opc, i, g)
116
117 #define CCMV(src, dst, t) \
118 bfin_gen_ccmv (src, dst, t)
119
120 #define CACTRL(reg, a, op) \
121 bfin_gen_cactrl (reg, a, op)
122
123 #define LOOPSETUP(soffset, c, rop, eoffset, reg) \
124 bfin_gen_loopsetup (soffset, c, rop, eoffset, reg)
125
126 #define HL2(r1, r0) (IS_H (r1) << 1 | IS_H (r0))
127 #define IS_RANGE(bits, expr, sign, mul) \
128 value_match(expr, bits, sign, mul, 1)
129 #define IS_URANGE(bits, expr, sign, mul) \
130 value_match(expr, bits, sign, mul, 0)
131 #define IS_CONST(expr) (expr->type == Expr_Node_Constant)
132 #define IS_RELOC(expr) (expr->type != Expr_Node_Constant)
133 #define IS_IMM(expr, bits) value_match (expr, bits, 0, 1, 1)
134 #define IS_UIMM(expr, bits) value_match (expr, bits, 0, 1, 0)
135
136 #define IS_PCREL4(expr) \
137 (value_match (expr, 4, 0, 2, 0))
138
139 #define IS_LPPCREL10(expr) \
140 (value_match (expr, 10, 0, 2, 0))
141
142 #define IS_PCREL10(expr) \
143 (value_match (expr, 10, 0, 2, 1))
144
145 #define IS_PCREL12(expr) \
146 (value_match (expr, 12, 0, 2, 1))
147
148 #define IS_PCREL24(expr) \
149 (value_match (expr, 24, 0, 2, 1))
150
151
152 static int value_match (Expr_Node *expr, int sz, int sign, int mul, int issigned);
153
154 extern FILE *errorf;
155 extern INSTR_T insn;
156
157 static Expr_Node *binary (Expr_Op_Type, Expr_Node *, Expr_Node *);
158 static Expr_Node *unary (Expr_Op_Type, Expr_Node *);
159
160 static void notethat (char *format, ...);
161
162 char *current_inputline;
163 extern char *yytext;
164 int yyerror (char *msg);
165
166 void error (char *format, ...)
167 {
168 va_list ap;
169 char buffer[2000];
170
171 va_start (ap, format);
172 vsprintf (buffer, format, ap);
173 va_end (ap);
174
175 as_bad (buffer);
176 }
177
178 int
179 yyerror (char *msg)
180 {
181 if (msg[0] == '\0')
182 error ("%s", msg);
183
184 else if (yytext[0] != ';')
185 error ("%s. Input text was %s.", msg, yytext);
186 else
187 error ("%s.", msg);
188
189 return -1;
190 }
191
192 static int
193 in_range_p (Expr_Node *expr, int from, int to, unsigned int mask)
194 {
195 int val = EXPR_VALUE (expr);
196 if (expr->type != Expr_Node_Constant)
197 return 0;
198 if (val < from || val > to)
199 return 0;
200 return (val & mask) == 0;
201 }
202
203 extern int yylex (void);
204
205 #define imm3(x) EXPR_VALUE (x)
206 #define imm4(x) EXPR_VALUE (x)
207 #define uimm4(x) EXPR_VALUE (x)
208 #define imm5(x) EXPR_VALUE (x)
209 #define uimm5(x) EXPR_VALUE (x)
210 #define imm6(x) EXPR_VALUE (x)
211 #define imm7(x) EXPR_VALUE (x)
212 #define imm16(x) EXPR_VALUE (x)
213 #define uimm16s4(x) ((EXPR_VALUE (x)) >> 2)
214 #define uimm16(x) EXPR_VALUE (x)
215
216 /* Return true if a value is inside a range. */
217 #define IN_RANGE(x, low, high) \
218 (((EXPR_VALUE(x)) >= (low)) && (EXPR_VALUE(x)) <= ((high)))
219
220 /* Auxiliary functions. */
221
222 static void
223 neg_value (Expr_Node *expr)
224 {
225 expr->value.i_value = -expr->value.i_value;
226 }
227
228 static int
229 valid_dreg_pair (Register *reg1, Expr_Node *reg2)
230 {
231 if (!IS_DREG (*reg1))
232 {
233 yyerror ("Dregs expected");
234 return 0;
235 }
236
237 if (reg1->regno != 1 && reg1->regno != 3)
238 {
239 yyerror ("Bad register pair");
240 return 0;
241 }
242
243 if (imm7 (reg2) != reg1->regno - 1)
244 {
245 yyerror ("Bad register pair");
246 return 0;
247 }
248
249 reg1->regno--;
250 return 1;
251 }
252
253 static int
254 check_multiply_halfregs (Macfunc *aa, Macfunc *ab)
255 {
256 if ((!REG_EQUAL (aa->s0, ab->s0) && !REG_EQUAL (aa->s0, ab->s1))
257 || (!REG_EQUAL (aa->s1, ab->s1) && !REG_EQUAL (aa->s1, ab->s0)))
258 return yyerror ("Source multiplication register mismatch");
259
260 return 0;
261 }
262
263
264 /* Check (vector) mac funcs and ops. */
265
266 static int
267 check_macfuncs (Macfunc *aa, Opt_mode *opa,
268 Macfunc *ab, Opt_mode *opb)
269 {
270 /* Variables for swapping. */
271 Macfunc mtmp;
272 Opt_mode otmp;
273
274 /* If a0macfunc comes before a1macfunc, swap them. */
275
276 if (aa->n == 0)
277 {
278 /* (M) is not allowed here. */
279 if (opa->MM != 0)
280 return yyerror ("(M) not allowed with A0MAC");
281 if (ab->n != 1)
282 return yyerror ("Vector AxMACs can't be same");
283
284 mtmp = *aa; *aa = *ab; *ab = mtmp;
285 otmp = *opa; *opa = *opb; *opb = otmp;
286 }
287 else
288 {
289 if (opb->MM != 0)
290 return yyerror ("(M) not allowed with A0MAC");
291 if (opa->mod != 0)
292 return yyerror ("Bad opt mode");
293 if (ab->n != 0)
294 return yyerror ("Vector AxMACs can't be same");
295 }
296
297 /* If both ops are != 3, we have multiply_halfregs in both
298 assignment_or_macfuncs. */
299 if (aa->op == ab->op && aa->op != 3)
300 {
301 if (check_multiply_halfregs (aa, ab) < 0)
302 return -1;
303 }
304 else
305 {
306 /* Only one of the assign_macfuncs has a half reg multiply
307 Evil trick: Just 'OR' their source register codes:
308 We can do that, because we know they were initialized to 0
309 in the rules that don't use multiply_halfregs. */
310 aa->s0.regno |= (ab->s0.regno & CODE_MASK);
311 aa->s1.regno |= (ab->s1.regno & CODE_MASK);
312 }
313
314 if (aa->w == ab->w && aa->P != ab->P)
315 {
316 return yyerror ("macfuncs must differ");
317 if (aa->w && (aa->dst.regno - ab->dst.regno != 1))
318 return yyerror ("Destination Dregs must differ by one");
319 }
320 /* We assign to full regs, thus obey even/odd rules. */
321 else if ((aa->w && aa->P && IS_EVEN (aa->dst))
322 || (ab->w && ab->P && !IS_EVEN (ab->dst)))
323 return yyerror ("Even/Odd register assignment mismatch");
324 /* We assign to half regs, thus obey hi/low rules. */
325 else if ( (aa->w && !aa->P && !IS_H (aa->dst))
326 || (ab->w && !aa->P && IS_H (ab->dst)))
327 return yyerror ("High/Low register assignment mismatch");
328
329 /* Make sure first macfunc has got both P flags ORed. */
330 aa->P |= ab->P;
331
332 /* Make sure mod flags get ORed, too. */
333 opb->mod |= opa->mod;
334 return 0;
335 }
336
337
338 static int
339 is_group1 (INSTR_T x)
340 {
341 /* Group1 is dpsLDST, LDSTpmod, LDST, LDSTiiFP, LDSTii. */
342 if ((x->value & 0xc000) == 0x8000 || (x->value == 0x0000))
343 return 1;
344
345 return 0;
346 }
347
348 static int
349 is_group2 (INSTR_T x)
350 {
351 if ((((x->value & 0xfc00) == 0x9c00) /* dspLDST. */
352 && !((x->value & 0xfde0) == 0x9c60) /* dagMODim. */
353 && !((x->value & 0xfde0) == 0x9ce0) /* dagMODim with bit rev. */
354 && !((x->value & 0xfde0) == 0x9d60)) /* pick dagMODik. */
355 || (x->value == 0x0000))
356 return 1;
357 return 0;
358 }
359
360 %}
361
362 %union {
363 INSTR_T instr;
364 Expr_Node *expr;
365 SYMBOL_T symbol;
366 long value;
367 Register reg;
368 Macfunc macfunc;
369 struct { int r0; int s0; int x0; int aop; } modcodes;
370 struct { int r0; } r0;
371 Opt_mode mod;
372 }
373
374
375 /* Tokens. */
376
377 /* Vector Specific. */
378 %token BYTEOP16P BYTEOP16M
379 %token BYTEOP1P BYTEOP2P BYTEOP2M BYTEOP3P
380 %token BYTEUNPACK BYTEPACK
381 %token PACK
382 %token SAA
383 %token ALIGN8 ALIGN16 ALIGN24
384 %token VIT_MAX
385 %token EXTRACT DEPOSIT EXPADJ SEARCH
386 %token ONES SIGN SIGNBITS
387
388 /* Stack. */
389 %token LINK UNLINK
390
391 /* Registers. */
392 %token REG
393 %token PC
394 %token CCREG BYTE_DREG
395 %token REG_A_DOUBLE_ZERO REG_A_DOUBLE_ONE
396 %token A_ZERO_DOT_L A_ZERO_DOT_H A_ONE_DOT_L A_ONE_DOT_H
397 %token HALF_REG
398
399 /* Progctrl. */
400 %token NOP
401 %token RTI RTS RTX RTN RTE
402 %token HLT IDLE
403 %token STI CLI
404 %token CSYNC SSYNC
405 %token EMUEXCPT
406 %token RAISE EXCPT
407 %token LSETUP
408 %token LOOP
409 %token LOOP_BEGIN
410 %token LOOP_END
411 %token DISALGNEXCPT
412 %token JUMP JUMP_DOT_S JUMP_DOT_L
413 %token CALL
414
415 /* Emulator only. */
416 %token ABORT
417
418 /* Operators. */
419 %token NOT TILDA BANG
420 %token AMPERSAND BAR
421 %token PERCENT
422 %token CARET
423 %token BXOR
424
425 %token MINUS PLUS STAR SLASH
426 %token NEG
427 %token MIN MAX ABS
428 %token DOUBLE_BAR
429 %token _PLUS_BAR_PLUS _PLUS_BAR_MINUS _MINUS_BAR_PLUS _MINUS_BAR_MINUS
430 %token _MINUS_MINUS _PLUS_PLUS
431
432 /* Shift/rotate ops. */
433 %token SHIFT LSHIFT ASHIFT BXORSHIFT
434 %token _GREATER_GREATER_GREATER_THAN_ASSIGN
435 %token ROT
436 %token LESS_LESS GREATER_GREATER
437 %token _GREATER_GREATER_GREATER
438 %token _LESS_LESS_ASSIGN _GREATER_GREATER_ASSIGN
439 %token DIVS DIVQ
440
441 /* In place operators. */
442 %token ASSIGN _STAR_ASSIGN
443 %token _BAR_ASSIGN _CARET_ASSIGN _AMPERSAND_ASSIGN
444 %token _MINUS_ASSIGN _PLUS_ASSIGN
445
446 /* Assignments, comparisons. */
447 %token _ASSIGN_BANG _LESS_THAN_ASSIGN _ASSIGN_ASSIGN
448 %token GE LT LE GT
449 %token LESS_THAN
450
451 /* Cache. */
452 %token FLUSHINV FLUSH
453 %token IFLUSH PREFETCH
454
455 /* Misc. */
456 %token PRNT
457 %token OUTC
458 %token WHATREG
459 %token TESTSET
460
461 /* Modifiers. */
462 %token ASL ASR
463 %token B W
464 %token NS S CO SCO
465 %token TH TL
466 %token BP
467 %token BREV
468 %token X Z
469 %token M MMOD
470 %token R RND RNDL RNDH RND12 RND20
471 %token V
472 %token LO HI
473
474 /* Bit ops. */
475 %token BITTGL BITCLR BITSET BITTST BITMUX
476
477 /* Debug. */
478 %token DBGAL DBGAH DBGHALT DBG DBGA DBGCMPLX
479
480 /* Semantic auxiliaries. */
481
482 %token IF COMMA BY
483 %token COLON SEMICOLON
484 %token RPAREN LPAREN LBRACK RBRACK
485 %token STATUS_REG
486 %token MNOP
487 %token SYMBOL NUMBER
488 %token GOT AT PLTPC
489
490 /* Types. */
491 %type <instr> asm
492 %type <value> MMOD
493 %type <mod> opt_mode
494
495 %type <value> NUMBER
496 %type <r0> aligndir
497 %type <modcodes> byteop_mod
498 %type <reg> a_assign
499 %type <reg> a_plusassign
500 %type <reg> a_minusassign
501 %type <macfunc> multiply_halfregs
502 %type <macfunc> assign_macfunc
503 %type <macfunc> a_macfunc
504 %type <expr> expr_1
505 %type <instr> asm_1
506 %type <r0> vmod
507 %type <modcodes> vsmod
508 %type <modcodes> ccstat
509 %type <r0> cc_op
510 %type <reg> CCREG
511 %type <reg> reg_with_postinc
512 %type <reg> reg_with_predec
513
514 %type <r0> searchmod
515 %type <expr> symbol
516 %type <symbol> SYMBOL
517 %type <expr> eterm
518 %type <reg> REG
519 %type <reg> BYTE_DREG
520 %type <reg> REG_A_DOUBLE_ZERO
521 %type <reg> REG_A_DOUBLE_ONE
522 %type <reg> REG_A
523 %type <reg> STATUS_REG
524 %type <expr> expr
525 %type <r0> xpmod
526 %type <r0> xpmod1
527 %type <modcodes> smod
528 %type <modcodes> b3_op
529 %type <modcodes> rnd_op
530 %type <modcodes> post_op
531 %type <reg> HALF_REG
532 %type <r0> iu_or_nothing
533 %type <r0> plus_minus
534 %type <r0> asr_asl
535 %type <r0> asr_asl_0
536 %type <modcodes> sco
537 %type <modcodes> amod0
538 %type <modcodes> amod1
539 %type <modcodes> amod2
540 %type <r0> op_bar_op
541 %type <r0> w32_or_nothing
542 %type <r0> c_align
543 %type <r0> min_max
544 %type <expr> got
545 %type <expr> got_or_expr
546 %type <expr> pltpc
547
548
549 /* Precedence rules. */
550 %left BAR
551 %left CARET
552 %left AMPERSAND
553 %left LESS_LESS GREATER_GREATER
554 %left PLUS MINUS
555 %left STAR SLASH PERCENT
556
557 %right ASSIGN
558
559 %right TILDA BANG
560 %start statement
561 %%
562 statement:
563 | asm
564 {
565 insn = $1;
566 if (insn == (INSTR_T) 0)
567 return NO_INSN_GENERATED;
568 else if (insn == (INSTR_T) - 1)
569 return SEMANTIC_ERROR;
570 else
571 return INSN_GENERATED;
572 }
573 ;
574
575 asm: asm_1 SEMICOLON
576 /* Parallel instructions. */
577 | asm_1 DOUBLE_BAR asm_1 DOUBLE_BAR asm_1 SEMICOLON
578 {
579 if (($1->value & 0xf800) == 0xc000)
580 {
581 if (is_group1 ($3) && is_group2 ($5))
582 $$ = bfin_gen_multi_instr ($1, $3, $5);
583 else if (is_group2 ($3) && is_group1 ($5))
584 $$ = bfin_gen_multi_instr ($1, $5, $3);
585 else
586 return yyerror ("Wrong 16 bit instructions groups, slot 2 and slot 3 must be 16-bit instrution group");
587 }
588 else if (($3->value & 0xf800) == 0xc000)
589 {
590 if (is_group1 ($1) && is_group2 ($5))
591 $$ = bfin_gen_multi_instr ($3, $1, $5);
592 else if (is_group2 ($1) && is_group1 ($5))
593 $$ = bfin_gen_multi_instr ($3, $5, $1);
594 else
595 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 3 must be 16-bit instrution group");
596 }
597 else if (($5->value & 0xf800) == 0xc000)
598 {
599 if (is_group1 ($1) && is_group2 ($3))
600 $$ = bfin_gen_multi_instr ($5, $1, $3);
601 else if (is_group2 ($1) && is_group1 ($3))
602 $$ = bfin_gen_multi_instr ($5, $3, $1);
603 else
604 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be 16-bit instrution group");
605 }
606 else
607 error ("\nIllegal Multi Issue Construct, at least any one of the slot must be DSP32 instruction group\n");
608 }
609
610 | asm_1 DOUBLE_BAR asm_1 SEMICOLON
611 {
612 if (($1->value & 0xf800) == 0xc000)
613 {
614 if (is_group1 ($3))
615 $$ = bfin_gen_multi_instr ($1, $3, 0);
616 else if (is_group2 ($3))
617 $$ = bfin_gen_multi_instr ($1, 0, $3);
618 else
619 return yyerror ("Wrong 16 bit instructions groups, slot 2 must be the 16-bit instruction group");
620 }
621 else if (($3->value & 0xf800) == 0xc000)
622 {
623 if (is_group1 ($1))
624 $$ = bfin_gen_multi_instr ($3, $1, 0);
625 else if (is_group2 ($1))
626 $$ = bfin_gen_multi_instr ($3, 0, $1);
627 else
628 return yyerror ("Wrong 16 bit instructions groups, slot 1 must be the 16-bit instruction group");
629 }
630 else if (is_group1 ($1) && is_group2 ($3))
631 $$ = bfin_gen_multi_instr (0, $1, $3);
632 else if (is_group2 ($1) && is_group1 ($3))
633 $$ = bfin_gen_multi_instr (0, $3, $1);
634 else
635 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be the 16-bit instruction group");
636 }
637 | error
638 {
639 $$ = 0;
640 yyerror ("");
641 yyerrok;
642 }
643 ;
644
645 /* DSPMAC. */
646
647 asm_1:
648 MNOP
649 {
650 $$ = DSP32MAC (3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0);
651 }
652 | assign_macfunc opt_mode
653 {
654 int op0, op1;
655 int w0 = 0, w1 = 0;
656 int h00, h10, h01, h11;
657
658 if ($1.n == 0)
659 {
660 if ($2.MM)
661 return yyerror ("(m) not allowed with a0 unit");
662 op1 = 3;
663 op0 = $1.op;
664 w1 = 0;
665 w0 = $1.w;
666 h00 = IS_H ($1.s0);
667 h10 = IS_H ($1.s1);
668 h01 = h11 = 0;
669 }
670 else
671 {
672 op1 = $1.op;
673 op0 = 3;
674 w1 = $1.w;
675 w0 = 0;
676 h00 = h10 = 0;
677 h01 = IS_H ($1.s0);
678 h11 = IS_H ($1.s1);
679 }
680 $$ = DSP32MAC (op1, $2.MM, $2.mod, w1, $1.P, h01, h11, h00, h10,
681 &$1.dst, op0, &$1.s0, &$1.s1, w0);
682 }
683
684
685 /* VECTOR MACs. */
686
687 | assign_macfunc opt_mode COMMA assign_macfunc opt_mode
688 {
689 Register *dst;
690
691 if (check_macfuncs (&$1, &$2, &$4, &$5) < 0)
692 return -1;
693 notethat ("assign_macfunc (.), assign_macfunc (.)\n");
694
695 if ($1.w)
696 dst = &$1.dst;
697 else
698 dst = &$4.dst;
699
700 $$ = DSP32MAC ($1.op, $2.MM, $5.mod, $1.w, $1.P,
701 IS_H ($1.s0), IS_H ($1.s1), IS_H ($4.s0), IS_H ($4.s1),
702 dst, $4.op, &$1.s0, &$1.s1, $4.w);
703 }
704
705 /* DSPALU. */
706
707 | DISALGNEXCPT
708 {
709 notethat ("dsp32alu: DISALGNEXCPT\n");
710 $$ = DSP32ALU (18, 0, 0, 0, 0, 0, 0, 0, 3);
711 }
712 | REG ASSIGN LPAREN a_plusassign REG_A RPAREN
713 {
714 if (IS_DREG ($1) && !IS_A1 ($4) && IS_A1 ($5))
715 {
716 notethat ("dsp32alu: dregs = ( A0 += A1 )\n");
717 $$ = DSP32ALU (11, 0, 0, &$1, 0, 0, 0, 0, 0);
718 }
719 else
720 return yyerror ("Register mismatch");
721 }
722 | HALF_REG ASSIGN LPAREN a_plusassign REG_A RPAREN
723 {
724 if (!IS_A1 ($4) && IS_A1 ($5))
725 {
726 notethat ("dsp32alu: dregs_half = ( A0 += A1 )\n");
727 $$ = DSP32ALU (11, IS_H ($1), 0, &$1, 0, 0, 0, 0, 1);
728 }
729 else
730 return yyerror ("Register mismatch");
731 }
732 | A_ZERO_DOT_H ASSIGN HALF_REG
733 {
734 notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
735 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
736 }
737 | A_ONE_DOT_H ASSIGN HALF_REG
738 {
739 notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
740 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
741 }
742 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16P LPAREN REG
743 COLON expr COMMA REG COLON expr RPAREN aligndir
744 {
745 if (!IS_DREG ($2) || !IS_DREG ($4))
746 return yyerror ("Dregs expected");
747 else if (!valid_dreg_pair (&$9, $11))
748 return yyerror ("Bad dreg pair");
749 else if (!valid_dreg_pair (&$13, $15))
750 return yyerror ("Bad dreg pair");
751 else
752 {
753 notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16P (dregs_pair , dregs_pair ) (half)\n");
754 $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 0);
755 }
756 }
757
758 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16M LPAREN REG COLON expr COMMA
759 REG COLON expr RPAREN aligndir
760 {
761 if (!IS_DREG ($2) || !IS_DREG($4))
762 return yyerror ("Dregs expected");
763 else if (!valid_dreg_pair (&$9, $11))
764 return yyerror ("Bad dreg pair");
765 else if (!valid_dreg_pair (&$13, $15))
766 return yyerror ("Bad dreg pair");
767 else
768 {
769 notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16M (dregs_pair , dregs_pair ) (aligndir)\n");
770 $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 1);
771 }
772 }
773
774 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEUNPACK REG COLON expr aligndir
775 {
776 if (!IS_DREG ($2) || !IS_DREG ($4))
777 return yyerror ("Dregs expected");
778 else if (!valid_dreg_pair (&$8, $10))
779 return yyerror ("Bad dreg pair");
780 else
781 {
782 notethat ("dsp32alu: (dregs , dregs ) = BYTEUNPACK dregs_pair (aligndir)\n");
783 $$ = DSP32ALU (24, 0, &$2, &$4, &$8, 0, $11.r0, 0, 1);
784 }
785 }
786 | LPAREN REG COMMA REG RPAREN ASSIGN SEARCH REG LPAREN searchmod RPAREN
787 {
788 if (IS_DREG ($2) && IS_DREG ($4) && IS_DREG ($8))
789 {
790 notethat ("dsp32alu: (dregs , dregs ) = SEARCH dregs (searchmod)\n");
791 $$ = DSP32ALU (13, 0, &$2, &$4, &$8, 0, 0, 0, $10.r0);
792 }
793 else
794 return yyerror ("Register mismatch");
795 }
796 | REG ASSIGN A_ONE_DOT_L PLUS A_ONE_DOT_H COMMA
797 REG ASSIGN A_ZERO_DOT_L PLUS A_ZERO_DOT_H
798 {
799 if (IS_DREG ($1) && IS_DREG ($7))
800 {
801 notethat ("dsp32alu: dregs = A1.l + A1.h, dregs = A0.l + A0.h \n");
802 $$ = DSP32ALU (12, 0, &$1, &$7, 0, 0, 0, 0, 1);
803 }
804 else
805 return yyerror ("Register mismatch");
806 }
807
808
809 | REG ASSIGN REG_A PLUS REG_A COMMA REG ASSIGN REG_A MINUS REG_A amod1
810 {
811 if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
812 && IS_A1 ($9) && !IS_A1 ($11))
813 {
814 notethat ("dsp32alu: dregs = A1 + A0 , dregs = A1 - A0 (amod1)\n");
815 $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 0);
816
817 }
818 else if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
819 && !IS_A1 ($9) && IS_A1 ($11))
820 {
821 notethat ("dsp32alu: dregs = A0 + A1 , dregs = A0 - A1 (amod1)\n");
822 $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 1);
823 }
824 else
825 return yyerror ("Register mismatch");
826 }
827
828 | REG ASSIGN REG plus_minus REG COMMA REG ASSIGN REG plus_minus REG amod1
829 {
830 if ($4.r0 == $10.r0)
831 return yyerror ("Operators must differ");
832
833 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5)
834 && REG_SAME ($3, $9) && REG_SAME ($5, $11))
835 {
836 notethat ("dsp32alu: dregs = dregs + dregs,"
837 "dregs = dregs - dregs (amod1)\n");
838 $$ = DSP32ALU (4, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, 2);
839 }
840 else
841 return yyerror ("Register mismatch");
842 }
843
844 /* Bar Operations. */
845
846 | REG ASSIGN REG op_bar_op REG COMMA REG ASSIGN REG op_bar_op REG amod2
847 {
848 if (!REG_SAME ($3, $9) || !REG_SAME ($5, $11))
849 return yyerror ("Differing source registers");
850
851 if (!IS_DREG ($1) || !IS_DREG ($3) || !IS_DREG ($5) || !IS_DREG ($7))
852 return yyerror ("Dregs expected");
853
854
855 if ($4.r0 == 1 && $10.r0 == 2)
856 {
857 notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
858 $$ = DSP32ALU (1, 1, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
859 }
860 else if ($4.r0 == 0 && $10.r0 == 3)
861 {
862 notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
863 $$ = DSP32ALU (1, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
864 }
865 else
866 return yyerror ("Bar operand mismatch");
867 }
868
869 | REG ASSIGN ABS REG vmod
870 {
871 int op;
872
873 if (IS_DREG ($1) && IS_DREG ($4))
874 {
875 if ($5.r0)
876 {
877 notethat ("dsp32alu: dregs = ABS dregs (v)\n");
878 op = 6;
879 }
880 else
881 {
882 /* Vector version of ABS. */
883 notethat ("dsp32alu: dregs = ABS dregs\n");
884 op = 7;
885 }
886 $$ = DSP32ALU (op, 0, 0, &$1, &$4, 0, 0, 0, 2);
887 }
888 else
889 return yyerror ("Dregs expected");
890 }
891 | a_assign ABS REG_A
892 {
893 notethat ("dsp32alu: Ax = ABS Ax\n");
894 $$ = DSP32ALU (16, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
895 }
896 | A_ZERO_DOT_L ASSIGN HALF_REG
897 {
898 if (IS_DREG_L ($3))
899 {
900 notethat ("dsp32alu: A0.l = reg_half\n");
901 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
902 }
903 else
904 return yyerror ("A0.l = Rx.l expected");
905 }
906 | A_ONE_DOT_L ASSIGN HALF_REG
907 {
908 if (IS_DREG_L ($3))
909 {
910 notethat ("dsp32alu: A1.l = reg_half\n");
911 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
912 }
913 else
914 return yyerror ("A1.l = Rx.l expected");
915 }
916
917 | REG ASSIGN c_align LPAREN REG COMMA REG RPAREN
918 {
919 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
920 {
921 notethat ("dsp32shift: dregs = ALIGN8 (dregs , dregs )\n");
922 $$ = DSP32SHIFT (13, &$1, &$7, &$5, $3.r0, 0);
923 }
924 else
925 return yyerror ("Dregs expected");
926 }
927
928 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN byteop_mod
929 {
930 if (!IS_DREG ($1))
931 return yyerror ("Dregs expected");
932 else if (!valid_dreg_pair (&$5, $7))
933 return yyerror ("Bad dreg pair");
934 else if (!valid_dreg_pair (&$9, $11))
935 return yyerror ("Bad dreg pair");
936 else
937 {
938 notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
939 $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, $13.s0, 0, $13.r0);
940 }
941 }
942 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
943 {
944 if (!IS_DREG ($1))
945 return yyerror ("Dregs expected");
946 else if (!valid_dreg_pair (&$5, $7))
947 return yyerror ("Bad dreg pair");
948 else if (!valid_dreg_pair (&$9, $11))
949 return yyerror ("Bad dreg pair");
950 else
951 {
952 notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
953 $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, 0, 0, 0);
954 }
955 }
956
957 | REG ASSIGN BYTEOP2P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
958 rnd_op
959 {
960 if (!IS_DREG ($1))
961 return yyerror ("Dregs expected");
962 else if (!valid_dreg_pair (&$5, $7))
963 return yyerror ("Bad dreg pair");
964 else if (!valid_dreg_pair (&$9, $11))
965 return yyerror ("Bad dreg pair");
966 else
967 {
968 notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
969 $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, $13.x0, $13.aop);
970 }
971 }
972
973 | REG ASSIGN BYTEOP2M LPAREN REG COLON expr COMMA REG COLON expr RPAREN
974 rnd_op
975 {
976 if (!IS_DREG ($1))
977 return yyerror ("Dregs expected");
978 else if (!valid_dreg_pair (&$5, $7))
979 return yyerror ("Bad dreg pair");
980 else if (!valid_dreg_pair (&$9, $11))
981 return yyerror ("Bad dreg pair");
982 else
983 {
984 notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
985 $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, 0, $13.x0);
986 }
987 }
988
989 | REG ASSIGN BYTEOP3P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
990 b3_op
991 {
992 if (!IS_DREG ($1))
993 return yyerror ("Dregs expected");
994 else if (!valid_dreg_pair (&$5, $7))
995 return yyerror ("Bad dreg pair");
996 else if (!valid_dreg_pair (&$9, $11))
997 return yyerror ("Bad dreg pair");
998 else
999 {
1000 notethat ("dsp32alu: dregs = BYTEOP3P (dregs_pair , dregs_pair ) (b3_op)\n");
1001 $$ = DSP32ALU (23, $13.x0, 0, &$1, &$5, &$9, $13.s0, 0, 0);
1002 }
1003 }
1004
1005 | REG ASSIGN BYTEPACK LPAREN REG COMMA REG RPAREN
1006 {
1007 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1008 {
1009 notethat ("dsp32alu: dregs = BYTEPACK (dregs , dregs )\n");
1010 $$ = DSP32ALU (24, 0, 0, &$1, &$5, &$7, 0, 0, 0);
1011 }
1012 else
1013 return yyerror ("Dregs expected");
1014 }
1015
1016 | HALF_REG ASSIGN HALF_REG ASSIGN SIGN LPAREN HALF_REG RPAREN STAR
1017 HALF_REG PLUS SIGN LPAREN HALF_REG RPAREN STAR HALF_REG
1018 {
1019 if (IS_HCOMPL ($1, $3) && IS_HCOMPL ($7, $14) && IS_HCOMPL ($10, $17))
1020 {
1021 notethat ("dsp32alu: dregs_hi = dregs_lo ="
1022 "SIGN (dregs_hi) * dregs_hi + "
1023 "SIGN (dregs_lo) * dregs_lo \n");
1024
1025 $$ = DSP32ALU (12, 0, 0, &$1, &$7, &$10, 0, 0, 0);
1026 }
1027 else
1028 return yyerror ("Dregs expected");
1029 }
1030 | REG ASSIGN REG plus_minus REG amod1
1031 {
1032 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1033 {
1034 if ($6.aop == 0)
1035 {
1036 /* No saturation flag specified, generate the 16 bit variant. */
1037 notethat ("COMP3op: dregs = dregs +- dregs\n");
1038 $$ = COMP3OP (&$1, &$3, &$5, $4.r0);
1039 }
1040 else
1041 {
1042 /* Saturation flag specified, generate the 32 bit variant. */
1043 notethat ("dsp32alu: dregs = dregs +- dregs (amod1)\n");
1044 $$ = DSP32ALU (4, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1045 }
1046 }
1047 else
1048 if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($5) && $4.r0 == 0)
1049 {
1050 notethat ("COMP3op: pregs = pregs + pregs\n");
1051 $$ = COMP3OP (&$1, &$3, &$5, 5);
1052 }
1053 else
1054 return yyerror ("Dregs expected");
1055 }
1056 | REG ASSIGN min_max LPAREN REG COMMA REG RPAREN vmod
1057 {
1058 int op;
1059
1060 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1061 {
1062 if ($9.r0)
1063 op = 6;
1064 else
1065 op = 7;
1066
1067 notethat ("dsp32alu: dregs = {MIN|MAX} (dregs, dregs)\n");
1068 $$ = DSP32ALU (op, 0, 0, &$1, &$5, &$7, 0, 0, $3.r0);
1069 }
1070 else
1071 return yyerror ("Dregs expected");
1072 }
1073
1074 | a_assign MINUS REG_A
1075 {
1076 notethat ("dsp32alu: Ax = - Ax\n");
1077 $$ = DSP32ALU (14, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
1078 }
1079 | HALF_REG ASSIGN HALF_REG plus_minus HALF_REG amod1
1080 {
1081 notethat ("dsp32alu: dregs_lo = dregs_lo +- dregs_lo (amod1)\n");
1082 $$ = DSP32ALU (2 | $4.r0, IS_H ($1), 0, &$1, &$3, &$5,
1083 $6.s0, $6.x0, HL2 ($3, $5));
1084 }
1085 | a_assign a_assign expr
1086 {
1087 if (EXPR_VALUE ($3) == 0 && !REG_SAME ($1, $2))
1088 {
1089 notethat ("dsp32alu: A1 = A0 = 0\n");
1090 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, 2);
1091 }
1092 else
1093 return yyerror ("Bad value, 0 expected");
1094 }
1095
1096 /* Saturating. */
1097 | a_assign REG_A LPAREN S RPAREN
1098 {
1099 if (REG_SAME ($1, $2))
1100 {
1101 notethat ("dsp32alu: Ax = Ax (S)\n");
1102 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, IS_A1 ($1));
1103 }
1104 else
1105 return yyerror ("Registers must be equal");
1106 }
1107
1108 | HALF_REG ASSIGN REG LPAREN RND RPAREN
1109 {
1110 if (IS_DREG ($3))
1111 {
1112 notethat ("dsp32alu: dregs_half = dregs (RND)\n");
1113 $$ = DSP32ALU (12, IS_H ($1), 0, &$1, &$3, 0, 0, 0, 3);
1114 }
1115 else
1116 return yyerror ("Dregs expected");
1117 }
1118
1119 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND12 RPAREN
1120 {
1121 if (IS_DREG ($3) && IS_DREG ($5))
1122 {
1123 notethat ("dsp32alu: dregs_half = dregs (+-) dregs (RND12)\n");
1124 $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 0, $4.r0);
1125 }
1126 else
1127 return yyerror ("Dregs expected");
1128 }
1129
1130 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND20 RPAREN
1131 {
1132 if (IS_DREG ($3) && IS_DREG ($5))
1133 {
1134 notethat ("dsp32alu: dregs_half = dregs -+ dregs (RND20)\n");
1135 $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 1, $4.r0 | 2);
1136 }
1137 else
1138 return yyerror ("Dregs expected");
1139 }
1140
1141 | a_assign REG_A
1142 {
1143 if (!REG_SAME ($1, $2))
1144 {
1145 notethat ("dsp32alu: An = Am\n");
1146 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, IS_A1 ($1), 0, 3);
1147 }
1148 else
1149 return yyerror ("Accu reg arguments must differ");
1150 }
1151
1152 | a_assign REG
1153 {
1154 if (IS_DREG ($2))
1155 {
1156 notethat ("dsp32alu: An = dregs\n");
1157 $$ = DSP32ALU (9, 0, 0, 0, &$2, 0, 1, 0, IS_A1 ($1) << 1);
1158 }
1159 else
1160 return yyerror ("Dregs expected");
1161 }
1162
1163 | REG ASSIGN HALF_REG xpmod
1164 {
1165 if (!IS_H ($3))
1166 {
1167 if ($1.regno == REG_A0x && IS_DREG ($3))
1168 {
1169 notethat ("dsp32alu: A0.x = dregs_lo\n");
1170 $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 1);
1171 }
1172 else if ($1.regno == REG_A1x && IS_DREG ($3))
1173 {
1174 notethat ("dsp32alu: A1.x = dregs_lo\n");
1175 $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 3);
1176 }
1177 else if (IS_DREG ($1) && IS_DREG ($3))
1178 {
1179 notethat ("ALU2op: dregs = dregs_lo\n");
1180 $$ = ALU2OP (&$1, &$3, 10 | ($4.r0 ? 0: 1));
1181 }
1182 else
1183 return yyerror ("Register mismatch");
1184 }
1185 else
1186 return yyerror ("Low reg expected");
1187 }
1188
1189 | HALF_REG ASSIGN expr
1190 {
1191 notethat ("LDIMMhalf: pregs_half = imm16\n");
1192
1193 if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1194 && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1195 return yyerror ("Wrong register for load immediate");
1196
1197 if (!IS_IMM ($3, 16) && !IS_UIMM ($3, 16))
1198 return yyerror ("Constant out of range");
1199
1200 $$ = LDIMMHALF_R (&$1, IS_H ($1), 0, 0, $3);
1201 }
1202
1203 | a_assign expr
1204 {
1205 notethat ("dsp32alu: An = 0\n");
1206
1207 if (imm7 ($2) != 0)
1208 return yyerror ("0 expected");
1209
1210 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, IS_A1 ($1));
1211 }
1212
1213 | REG ASSIGN expr xpmod1
1214 {
1215 if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1216 && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1217 return yyerror ("Wrong register for load immediate");
1218
1219 if ($4.r0 == 0)
1220 {
1221 /* 7 bit immediate value if possible.
1222 We will check for that constant value for efficiency
1223 If it goes to reloc, it will be 16 bit. */
1224 if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_DREG ($1))
1225 {
1226 notethat ("COMPI2opD: dregs = imm7 (x) \n");
1227 $$ = COMPI2OPD (&$1, imm7 ($3), 0);
1228 }
1229 else if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_PREG ($1))
1230 {
1231 notethat ("COMPI2opP: pregs = imm7 (x)\n");
1232 $$ = COMPI2OPP (&$1, imm7 ($3), 0);
1233 }
1234 else
1235 {
1236 if (IS_CONST ($3) && !IS_IMM ($3, 16))
1237 return yyerror ("Immediate value out of range");
1238
1239 notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1240 /* reg, H, S, Z. */
1241 $$ = LDIMMHALF_R5 (&$1, 0, 1, 0, $3);
1242 }
1243 }
1244 else
1245 {
1246 /* (z) There is no 7 bit zero extended instruction.
1247 If the expr is a relocation, generate it. */
1248
1249 if (IS_CONST ($3) && !IS_UIMM ($3, 16))
1250 return yyerror ("Immediate value out of range");
1251
1252 notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1253 /* reg, H, S, Z. */
1254 $$ = LDIMMHALF_R5 (&$1, 0, 0, 1, $3);
1255 }
1256 }
1257
1258 | HALF_REG ASSIGN REG
1259 {
1260 if (IS_H ($1))
1261 return yyerror ("Low reg expected");
1262
1263 if (IS_DREG ($1) && $3.regno == REG_A0x)
1264 {
1265 notethat ("dsp32alu: dregs_lo = A0.x\n");
1266 $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 0);
1267 }
1268 else if (IS_DREG ($1) && $3.regno == REG_A1x)
1269 {
1270 notethat ("dsp32alu: dregs_lo = A1.x\n");
1271 $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 1);
1272 }
1273 else
1274 return yyerror ("Register mismatch");
1275 }
1276
1277 | REG ASSIGN REG op_bar_op REG amod0
1278 {
1279 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1280 {
1281 notethat ("dsp32alu: dregs = dregs .|. dregs (amod0)\n");
1282 $$ = DSP32ALU (0, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1283 }
1284 else
1285 return yyerror ("Register mismatch");
1286 }
1287
1288 | REG ASSIGN BYTE_DREG xpmod
1289 {
1290 if (IS_DREG ($1) && IS_DREG ($3))
1291 {
1292 notethat ("ALU2op: dregs = dregs_byte\n");
1293 $$ = ALU2OP (&$1, &$3, 12 | ($4.r0 ? 0: 1));
1294 }
1295 else
1296 return yyerror ("Register mismatch");
1297 }
1298
1299 | a_assign ABS REG_A COMMA a_assign ABS REG_A
1300 {
1301 if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1302 {
1303 notethat ("dsp32alu: A1 = ABS A1 , A0 = ABS A0\n");
1304 $$ = DSP32ALU (16, 0, 0, 0, 0, 0, 0, 0, 3);
1305 }
1306 else
1307 return yyerror ("Register mismatch");
1308 }
1309
1310 | a_assign MINUS REG_A COMMA a_assign MINUS REG_A
1311 {
1312 if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1313 {
1314 notethat ("dsp32alu: A1 = - A1 , A0 = - A0\n");
1315 $$ = DSP32ALU (14, 0, 0, 0, 0, 0, 0, 0, 3);
1316 }
1317 else
1318 return yyerror ("Register mismatch");
1319 }
1320
1321 | a_minusassign REG_A w32_or_nothing
1322 {
1323 if (!IS_A1 ($1) && IS_A1 ($2))
1324 {
1325 notethat ("dsp32alu: A0 -= A1\n");
1326 $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $3.r0, 0, 3);
1327 }
1328 else
1329 return yyerror ("Register mismatch");
1330 }
1331
1332 | REG _MINUS_ASSIGN expr
1333 {
1334 if (IS_IREG ($1) && EXPR_VALUE ($3) == 4)
1335 {
1336 notethat ("dagMODik: iregs -= 4\n");
1337 $$ = DAGMODIK (&$1, 3);
1338 }
1339 else if (IS_IREG ($1) && EXPR_VALUE ($3) == 2)
1340 {
1341 notethat ("dagMODik: iregs -= 2\n");
1342 $$ = DAGMODIK (&$1, 1);
1343 }
1344 else
1345 return yyerror ("Register or value mismatch");
1346 }
1347
1348 | REG _PLUS_ASSIGN REG LPAREN BREV RPAREN
1349 {
1350 if (IS_IREG ($1) && IS_MREG ($3))
1351 {
1352 notethat ("dagMODim: iregs += mregs (opt_brev)\n");
1353 /* i, m, op, br. */
1354 $$ = DAGMODIM (&$1, &$3, 0, 1);
1355 }
1356 else if (IS_PREG ($1) && IS_PREG ($3))
1357 {
1358 notethat ("PTR2op: pregs += pregs (BREV )\n");
1359 $$ = PTR2OP (&$1, &$3, 5);
1360 }
1361 else
1362 return yyerror ("Register mismatch");
1363 }
1364
1365 | REG _MINUS_ASSIGN REG
1366 {
1367 if (IS_IREG ($1) && IS_MREG ($3))
1368 {
1369 notethat ("dagMODim: iregs -= mregs\n");
1370 $$ = DAGMODIM (&$1, &$3, 1, 0);
1371 }
1372 else if (IS_PREG ($1) && IS_PREG ($3))
1373 {
1374 notethat ("PTR2op: pregs -= pregs\n");
1375 $$ = PTR2OP (&$1, &$3, 0);
1376 }
1377 else
1378 return yyerror ("Register mismatch");
1379 }
1380
1381 | REG_A _PLUS_ASSIGN REG_A w32_or_nothing
1382 {
1383 if (!IS_A1 ($1) && IS_A1 ($3))
1384 {
1385 notethat ("dsp32alu: A0 += A1 (W32)\n");
1386 $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $4.r0, 0, 2);
1387 }
1388 else
1389 return yyerror ("Register mismatch");
1390 }
1391
1392 | REG _PLUS_ASSIGN REG
1393 {
1394 if (IS_IREG ($1) && IS_MREG ($3))
1395 {
1396 notethat ("dagMODim: iregs += mregs\n");
1397 $$ = DAGMODIM (&$1, &$3, 0, 0);
1398 }
1399 else
1400 return yyerror ("iregs += mregs expected");
1401 }
1402
1403 | REG _PLUS_ASSIGN expr
1404 {
1405 if (IS_IREG ($1))
1406 {
1407 if (EXPR_VALUE ($3) == 4)
1408 {
1409 notethat ("dagMODik: iregs += 4\n");
1410 $$ = DAGMODIK (&$1, 2);
1411 }
1412 else if (EXPR_VALUE ($3) == 2)
1413 {
1414 notethat ("dagMODik: iregs += 2\n");
1415 $$ = DAGMODIK (&$1, 0);
1416 }
1417 else
1418 return yyerror ("iregs += [ 2 | 4 ");
1419 }
1420 else if (IS_PREG ($1) && IS_IMM ($3, 7))
1421 {
1422 notethat ("COMPI2opP: pregs += imm7\n");
1423 $$ = COMPI2OPP (&$1, imm7 ($3), 1);
1424 }
1425 else if (IS_DREG ($1) && IS_IMM ($3, 7))
1426 {
1427 notethat ("COMPI2opD: dregs += imm7\n");
1428 $$ = COMPI2OPD (&$1, imm7 ($3), 1);
1429 }
1430 else
1431 return yyerror ("Register mismatch");
1432 }
1433
1434 | REG _STAR_ASSIGN REG
1435 {
1436 if (IS_DREG ($1) && IS_DREG ($3))
1437 {
1438 notethat ("ALU2op: dregs *= dregs\n");
1439 $$ = ALU2OP (&$1, &$3, 3);
1440 }
1441 else
1442 return yyerror ("Register mismatch");
1443 }
1444
1445 | SAA LPAREN REG COLON expr COMMA REG COLON expr RPAREN aligndir
1446 {
1447 if (!valid_dreg_pair (&$3, $5))
1448 return yyerror ("Bad dreg pair");
1449 else if (!valid_dreg_pair (&$7, $9))
1450 return yyerror ("Bad dreg pair");
1451 else
1452 {
1453 notethat ("dsp32alu: SAA (dregs_pair , dregs_pair ) (aligndir)\n");
1454 $$ = DSP32ALU (18, 0, 0, 0, &$3, &$7, $11.r0, 0, 0);
1455 }
1456 }
1457
1458 | a_assign REG_A LPAREN S RPAREN COMMA a_assign REG_A LPAREN S RPAREN
1459 {
1460 if (REG_SAME ($1, $2) && REG_SAME ($7, $8) && !REG_SAME ($1, $7))
1461 {
1462 notethat ("dsp32alu: A1 = A1 (S) , A0 = A0 (S)\n");
1463 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, 2);
1464 }
1465 else
1466 return yyerror ("Register mismatch");
1467 }
1468
1469 | REG ASSIGN LPAREN REG PLUS REG RPAREN LESS_LESS expr
1470 {
1471 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6)
1472 && REG_SAME ($1, $4))
1473 {
1474 if (EXPR_VALUE ($9) == 1)
1475 {
1476 notethat ("ALU2op: dregs = (dregs + dregs) << 1\n");
1477 $$ = ALU2OP (&$1, &$6, 4);
1478 }
1479 else if (EXPR_VALUE ($9) == 2)
1480 {
1481 notethat ("ALU2op: dregs = (dregs + dregs) << 2\n");
1482 $$ = ALU2OP (&$1, &$6, 5);
1483 }
1484 else
1485 return yyerror ("Bad shift value");
1486 }
1487 else if (IS_PREG ($1) && IS_PREG ($4) && IS_PREG ($6)
1488 && REG_SAME ($1, $4))
1489 {
1490 if (EXPR_VALUE ($9) == 1)
1491 {
1492 notethat ("PTR2op: pregs = (pregs + pregs) << 1\n");
1493 $$ = PTR2OP (&$1, &$6, 6);
1494 }
1495 else if (EXPR_VALUE ($9) == 2)
1496 {
1497 notethat ("PTR2op: pregs = (pregs + pregs) << 2\n");
1498 $$ = PTR2OP (&$1, &$6, 7);
1499 }
1500 else
1501 return yyerror ("Bad shift value");
1502 }
1503 else
1504 return yyerror ("Register mismatch");
1505 }
1506
1507 /* COMP3 CCFLAG. */
1508 | REG ASSIGN REG BAR REG
1509 {
1510 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1511 {
1512 notethat ("COMP3op: dregs = dregs | dregs\n");
1513 $$ = COMP3OP (&$1, &$3, &$5, 3);
1514 }
1515 else
1516 return yyerror ("Dregs expected");
1517 }
1518 | REG ASSIGN REG CARET REG
1519 {
1520 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1521 {
1522 notethat ("COMP3op: dregs = dregs ^ dregs\n");
1523 $$ = COMP3OP (&$1, &$3, &$5, 4);
1524 }
1525 else
1526 return yyerror ("Dregs expected");
1527 }
1528 | REG ASSIGN REG PLUS LPAREN REG LESS_LESS expr RPAREN
1529 {
1530 if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($6))
1531 {
1532 if (EXPR_VALUE ($8) == 1)
1533 {
1534 notethat ("COMP3op: pregs = pregs + (pregs << 1)\n");
1535 $$ = COMP3OP (&$1, &$3, &$6, 6);
1536 }
1537 else if (EXPR_VALUE ($8) == 2)
1538 {
1539 notethat ("COMP3op: pregs = pregs + (pregs << 2)\n");
1540 $$ = COMP3OP (&$1, &$3, &$6, 7);
1541 }
1542 else
1543 return yyerror ("Bad shift value");
1544 }
1545 else
1546 return yyerror ("Dregs expected");
1547 }
1548 | CCREG ASSIGN REG_A _ASSIGN_ASSIGN REG_A
1549 {
1550 if (!REG_SAME ($3, $5))
1551 {
1552 notethat ("CCflag: CC = A0 == A1\n");
1553 $$ = CCFLAG (0, 0, 5, 0, 0);
1554 }
1555 else
1556 return yyerror ("CC register expected");
1557 }
1558 | CCREG ASSIGN REG_A LESS_THAN REG_A
1559 {
1560 if (!REG_SAME ($3, $5))
1561 {
1562 notethat ("CCflag: CC = A0 < A1\n");
1563 $$ = CCFLAG (0, 0, 6, 0, 0);
1564 }
1565 else
1566 return yyerror ("Register mismatch");
1567 }
1568 | CCREG ASSIGN REG LESS_THAN REG iu_or_nothing
1569 {
1570 if (REG_CLASS($3) == REG_CLASS($5))
1571 {
1572 notethat ("CCflag: CC = dpregs < dpregs\n");
1573 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1574 }
1575 else
1576 return yyerror ("Compare only of same register class");
1577 }
1578 | CCREG ASSIGN REG LESS_THAN expr iu_or_nothing
1579 {
1580 if (($6.r0 == 1 && IS_IMM ($5, 3))
1581 || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1582 {
1583 notethat ("CCflag: CC = dpregs < (u)imm3\n");
1584 $$ = CCFLAG (&$3, imm3 ($5), $6.r0, 1, IS_PREG ($3) ? 1 : 0);
1585 }
1586 else
1587 return yyerror ("Bad constant value");
1588 }
1589 | CCREG ASSIGN REG _ASSIGN_ASSIGN REG
1590 {
1591 if (REG_CLASS($3) == REG_CLASS($5))
1592 {
1593 notethat ("CCflag: CC = dpregs == dpregs\n");
1594 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, 0, 0, IS_PREG ($3) ? 1 : 0);
1595 }
1596 }
1597 | CCREG ASSIGN REG _ASSIGN_ASSIGN expr
1598 {
1599 if (IS_IMM ($5, 3))
1600 {
1601 notethat ("CCflag: CC = dpregs == imm3\n");
1602 $$ = CCFLAG (&$3, imm3 ($5), 0, 1, IS_PREG ($3) ? 1 : 0);
1603 }
1604 else
1605 return yyerror ("Bad constant range");
1606 }
1607 | CCREG ASSIGN REG_A _LESS_THAN_ASSIGN REG_A
1608 {
1609 if (!REG_SAME ($3, $5))
1610 {
1611 notethat ("CCflag: CC = A0 <= A1\n");
1612 $$ = CCFLAG (0, 0, 7, 0, 0);
1613 }
1614 else
1615 return yyerror ("CC register expected");
1616 }
1617 | CCREG ASSIGN REG _LESS_THAN_ASSIGN REG iu_or_nothing
1618 {
1619 if (REG_CLASS($3) == REG_CLASS($5))
1620 {
1621 notethat ("CCflag: CC = pregs <= pregs (..)\n");
1622 $$ = CCFLAG (&$3, $5.regno & CODE_MASK,
1623 1 + $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1624 }
1625 else
1626 return yyerror ("Compare only of same register class");
1627 }
1628 | CCREG ASSIGN REG _LESS_THAN_ASSIGN expr iu_or_nothing
1629 {
1630 if (($6.r0 == 1 && IS_IMM ($5, 3))
1631 || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1632 {
1633 if (IS_DREG ($3))
1634 {
1635 notethat ("CCflag: CC = dregs <= (u)imm3\n");
1636 /* x y opc I G */
1637 $$ = CCFLAG (&$3, imm3 ($5), 1 + $6.r0, 1, 0);
1638 }
1639 else if (IS_PREG ($3))
1640 {
1641 notethat ("CCflag: CC = pregs <= (u)imm3\n");
1642 /* x y opc I G */
1643 $$ = CCFLAG (&$3, imm3 ($5), 1 + $6.r0, 1, 1);
1644 }
1645 else
1646 return yyerror ("Dreg or Preg expected");
1647 }
1648 else
1649 return yyerror ("Bad constant value");
1650 }
1651
1652 | REG ASSIGN REG AMPERSAND REG
1653 {
1654 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1655 {
1656 notethat ("COMP3op: dregs = dregs & dregs\n");
1657 $$ = COMP3OP (&$1, &$3, &$5, 2);
1658 }
1659 else
1660 return yyerror ("Dregs expected");
1661 }
1662
1663 | ccstat
1664 {
1665 notethat ("CC2stat operation\n");
1666 $$ = bfin_gen_cc2stat ($1.r0, $1.x0, $1.s0);
1667 }
1668
1669 | REG ASSIGN REG
1670 {
1671 if (IS_ALLREG ($1) && IS_ALLREG ($3))
1672 {
1673 notethat ("REGMV: allregs = allregs\n");
1674 $$ = bfin_gen_regmv (&$3, &$1);
1675 }
1676 else
1677 return yyerror ("Register mismatch");
1678 }
1679
1680 | CCREG ASSIGN REG
1681 {
1682 if (IS_DREG ($3))
1683 {
1684 notethat ("CC2dreg: CC = dregs\n");
1685 $$ = bfin_gen_cc2dreg (1, &$3);
1686 }
1687 else
1688 return yyerror ("Register mismatch");
1689 }
1690
1691 | REG ASSIGN CCREG
1692 {
1693 if (IS_DREG ($1))
1694 {
1695 notethat ("CC2dreg: dregs = CC\n");
1696 $$ = bfin_gen_cc2dreg (0, &$1);
1697 }
1698 else
1699 return yyerror ("Register mismatch");
1700 }
1701
1702 | CCREG _ASSIGN_BANG CCREG
1703 {
1704 notethat ("CC2dreg: CC =! CC\n");
1705 $$ = bfin_gen_cc2dreg (3, 0);
1706 }
1707
1708 /* DSPMULT. */
1709
1710 | HALF_REG ASSIGN multiply_halfregs opt_mode
1711 {
1712 notethat ("dsp32mult: dregs_half = multiply_halfregs (opt_mode)\n");
1713
1714 if (!IS_H ($1) && $4.MM)
1715 return yyerror ("(M) not allowed with MAC0");
1716
1717 if (IS_H ($1))
1718 {
1719 $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 0,
1720 IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1721 &$1, 0, &$3.s0, &$3.s1, 0);
1722 }
1723 else
1724 {
1725 $$ = DSP32MULT (0, 0, $4.mod, 0, 0,
1726 0, 0, IS_H ($3.s0), IS_H ($3.s1),
1727 &$1, 0, &$3.s0, &$3.s1, 1);
1728 }
1729 }
1730
1731 | REG ASSIGN multiply_halfregs opt_mode
1732 {
1733 /* Odd registers can use (M). */
1734 if (!IS_DREG ($1))
1735 return yyerror ("Dreg expected");
1736
1737 if (!IS_EVEN ($1))
1738 {
1739 notethat ("dsp32mult: dregs = multiply_halfregs (opt_mode)\n");
1740
1741 $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 1,
1742 IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1743 &$1, 0, &$3.s0, &$3.s1, 0);
1744 }
1745 else if ($4.MM == 0)
1746 {
1747 notethat ("dsp32mult: dregs = multiply_halfregs opt_mode\n");
1748 $$ = DSP32MULT (0, 0, $4.mod, 0, 1,
1749 0, 0, IS_H ($3.s0), IS_H ($3.s1),
1750 &$1, 0, &$3.s0, &$3.s1, 1);
1751 }
1752 else
1753 return yyerror ("Register or mode mismatch");
1754 }
1755
1756 | HALF_REG ASSIGN multiply_halfregs opt_mode COMMA
1757 HALF_REG ASSIGN multiply_halfregs opt_mode
1758 {
1759 if (!IS_DREG ($1) || !IS_DREG ($6))
1760 return yyerror ("Dregs expected");
1761
1762 if (check_multiply_halfregs (&$3, &$8) < 0)
1763 return -1;
1764
1765 if (IS_H ($1) && !IS_H ($6))
1766 {
1767 notethat ("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, "
1768 "dregs_lo = multiply_halfregs opt_mode\n");
1769 $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 0,
1770 IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1771 &$1, 0, &$3.s0, &$3.s1, 1);
1772 }
1773 else if (!IS_H ($1) && IS_H ($6) && $4.MM == 0)
1774 {
1775 $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 0,
1776 IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1777 &$1, 0, &$3.s0, &$3.s1, 1);
1778 }
1779 else
1780 return yyerror ("Multfunc Register or mode mismatch");
1781 }
1782
1783 | REG ASSIGN multiply_halfregs opt_mode COMMA REG ASSIGN multiply_halfregs opt_mode
1784 {
1785 if (!IS_DREG ($1) || !IS_DREG ($6))
1786 return yyerror ("Dregs expected");
1787
1788 if (check_multiply_halfregs (&$3, &$8) < 0)
1789 return -1;
1790
1791 notethat ("dsp32mult: dregs = multiply_halfregs mxd_mod, "
1792 "dregs = multiply_halfregs opt_mode\n");
1793 if (IS_EVEN ($1))
1794 {
1795 if ($6.regno - $1.regno != 1 || $4.MM != 0)
1796 return yyerror ("Dest registers or mode mismatch");
1797
1798 /* op1 MM mmod */
1799 $$ = DSP32MULT (0, 0, $9.mod, 1, 1,
1800 IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1801 &$1, 0, &$3.s0, &$3.s1, 1);
1802
1803 }
1804 else
1805 {
1806 if ($1.regno - $6.regno != 1)
1807 return yyerror ("Dest registers mismatch");
1808
1809 $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 1,
1810 IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1811 &$1, 0, &$3.s0, &$3.s1, 1);
1812 }
1813 }
1814
1815 \f
1816 /* SHIFTs. */
1817 | a_assign ASHIFT REG_A BY HALF_REG
1818 {
1819 if (!REG_SAME ($1, $3))
1820 return yyerror ("Aregs must be same");
1821
1822 if (IS_DREG ($5) && !IS_H ($5))
1823 {
1824 notethat ("dsp32shift: A0 = ASHIFT A0 BY dregs_lo\n");
1825 $$ = DSP32SHIFT (3, 0, &$5, 0, 0, IS_A1 ($1));
1826 }
1827 else
1828 return yyerror ("Dregs expected");
1829 }
1830
1831 | HALF_REG ASSIGN ASHIFT HALF_REG BY HALF_REG smod
1832 {
1833 if (IS_DREG ($6) && !IS_H ($6))
1834 {
1835 notethat ("dsp32shift: dregs_half = ASHIFT dregs_half BY dregs_lo\n");
1836 $$ = DSP32SHIFT (0, &$1, &$6, &$4, $7.s0, HL2 ($1, $4));
1837 }
1838 else
1839 return yyerror ("Dregs expected");
1840 }
1841
1842 | a_assign REG_A LESS_LESS expr
1843 {
1844 if (!REG_SAME ($1, $2))
1845 return yyerror ("Aregs must be same");
1846
1847 if (IS_UIMM ($4, 5))
1848 {
1849 notethat ("dsp32shiftimm: A0 = A0 << uimm5\n");
1850 $$ = DSP32SHIFTIMM (3, 0, imm5 ($4), 0, 0, IS_A1 ($1));
1851 }
1852 else
1853 return yyerror ("Bad shift value");
1854 }
1855
1856 | REG ASSIGN REG LESS_LESS expr vsmod
1857 {
1858 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
1859 {
1860 if ($6.r0)
1861 {
1862 /* Vector? */
1863 notethat ("dsp32shiftimm: dregs = dregs << expr (V, .)\n");
1864 $$ = DSP32SHIFTIMM (1, &$1, imm4 ($5), &$3, $6.s0 ? 1 : 2, 0);
1865 }
1866 else
1867 {
1868 notethat ("dsp32shiftimm: dregs = dregs << uimm5 (.)\n");
1869 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($5), &$3, $6.s0 ? 1 : 2, 0);
1870 }
1871 }
1872 else if ($6.s0 == 0 && IS_PREG ($1) && IS_PREG ($3))
1873 {
1874 if (EXPR_VALUE ($5) == 2)
1875 {
1876 notethat ("PTR2op: pregs = pregs << 2\n");
1877 $$ = PTR2OP (&$1, &$3, 1);
1878 }
1879 else if (EXPR_VALUE ($5) == 1)
1880 {
1881 notethat ("COMP3op: pregs = pregs << 1\n");
1882 $$ = COMP3OP (&$1, &$3, &$3, 5);
1883 }
1884 else
1885 return yyerror ("Bad shift value");
1886 }
1887 else
1888 return yyerror ("Bad shift value or register");
1889 }
1890 | HALF_REG ASSIGN HALF_REG LESS_LESS expr
1891 {
1892 if (IS_UIMM ($5, 4))
1893 {
1894 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
1895 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3));
1896 }
1897 else
1898 return yyerror ("Bad shift value");
1899 }
1900 | HALF_REG ASSIGN HALF_REG LESS_LESS expr smod
1901 {
1902 if (IS_UIMM ($5, 4))
1903 {
1904 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
1905 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3));
1906 }
1907 else
1908 return yyerror ("Bad shift value");
1909 }
1910 | REG ASSIGN ASHIFT REG BY HALF_REG vsmod
1911 {
1912 int op;
1913
1914 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6) && !IS_H ($6))
1915 {
1916 if ($7.r0)
1917 {
1918 op = 1;
1919 notethat ("dsp32shift: dregs = ASHIFT dregs BY "
1920 "dregs_lo (V, .)\n");
1921 }
1922 else
1923 {
1924
1925 op = 2;
1926 notethat ("dsp32shift: dregs = ASHIFT dregs BY dregs_lo (.)\n");
1927 }
1928 $$ = DSP32SHIFT (op, &$1, &$6, &$4, $7.s0, 0);
1929 }
1930 else
1931 return yyerror ("Dregs expected");
1932 }
1933
1934 /* EXPADJ. */
1935 | HALF_REG ASSIGN EXPADJ LPAREN REG COMMA HALF_REG RPAREN vmod
1936 {
1937 if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
1938 {
1939 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs , dregs_lo )\n");
1940 $$ = DSP32SHIFT (7, &$1, &$7, &$5, $9.r0, 0);
1941 }
1942 else
1943 return yyerror ("Bad shift value or register");
1944 }
1945
1946
1947 | HALF_REG ASSIGN EXPADJ LPAREN HALF_REG COMMA HALF_REG RPAREN
1948 {
1949 if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
1950 {
1951 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_lo, dregs_lo)\n");
1952 $$ = DSP32SHIFT (7, &$1, &$7, &$5, 2, 0);
1953 }
1954 else if (IS_DREG_L ($1) && IS_DREG_H ($5) && IS_DREG_L ($7))
1955 {
1956 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_hi, dregs_lo)\n");
1957 $$ = DSP32SHIFT (7, &$1, &$7, &$5, 3, 0);
1958 }
1959 else
1960 return yyerror ("Bad shift value or register");
1961 }
1962
1963 /* DEPOSIT. */
1964
1965 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN
1966 {
1967 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1968 {
1969 notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs )\n");
1970 $$ = DSP32SHIFT (10, &$1, &$7, &$5, 2, 0);
1971 }
1972 else
1973 return yyerror ("Register mismatch");
1974 }
1975
1976 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN LPAREN X RPAREN
1977 {
1978 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1979 {
1980 notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs ) (X)\n");
1981 $$ = DSP32SHIFT (10, &$1, &$7, &$5, 3, 0);
1982 }
1983 else
1984 return yyerror ("Register mismatch");
1985 }
1986
1987 | REG ASSIGN EXTRACT LPAREN REG COMMA HALF_REG RPAREN xpmod
1988 {
1989 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG_L ($7))
1990 {
1991 notethat ("dsp32shift: dregs = EXTRACT (dregs, dregs_lo ) (.)\n");
1992 $$ = DSP32SHIFT (10, &$1, &$7, &$5, $9.r0, 0);
1993 }
1994 else
1995 return yyerror ("Register mismatch");
1996 }
1997
1998 | a_assign REG_A _GREATER_GREATER_GREATER expr
1999 {
2000 if (!REG_SAME ($1, $2))
2001 return yyerror ("Aregs must be same");
2002
2003 if (IS_UIMM ($4, 5))
2004 {
2005 notethat ("dsp32shiftimm: Ax = Ax >>> uimm5\n");
2006 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 0, IS_A1 ($1));
2007 }
2008 else
2009 return yyerror ("Shift value range error");
2010 }
2011 | a_assign LSHIFT REG_A BY HALF_REG
2012 {
2013 if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2014 {
2015 notethat ("dsp32shift: Ax = LSHIFT Ax BY dregs_lo\n");
2016 $$ = DSP32SHIFT (3, 0, &$5, 0, 1, IS_A1 ($1));
2017 }
2018 else
2019 return yyerror ("Register mismatch");
2020 }
2021
2022 | HALF_REG ASSIGN LSHIFT HALF_REG BY HALF_REG
2023 {
2024 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2025 {
2026 notethat ("dsp32shift: dregs_lo = LSHIFT dregs_hi BY dregs_lo\n");
2027 $$ = DSP32SHIFT (0, &$1, &$6, &$4, 2, HL2 ($1, $4));
2028 }
2029 else
2030 return yyerror ("Register mismatch");
2031 }
2032
2033 | REG ASSIGN LSHIFT REG BY HALF_REG vmod
2034 {
2035 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2036 {
2037 notethat ("dsp32shift: dregs = LSHIFT dregs BY dregs_lo (V )\n");
2038 $$ = DSP32SHIFT ($7.r0 ? 1: 2, &$1, &$6, &$4, 2, 0);
2039 }
2040 else
2041 return yyerror ("Register mismatch");
2042 }
2043
2044 | REG ASSIGN SHIFT REG BY HALF_REG
2045 {
2046 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2047 {
2048 notethat ("dsp32shift: dregs = SHIFT dregs BY dregs_lo\n");
2049 $$ = DSP32SHIFT (2, &$1, &$6, &$4, 2, 0);
2050 }
2051 else
2052 return yyerror ("Register mismatch");
2053 }
2054
2055 | a_assign REG_A GREATER_GREATER expr
2056 {
2057 if (REG_SAME ($1, $2) && IS_IMM ($4, 6) >= 0)
2058 {
2059 notethat ("dsp32shiftimm: Ax = Ax >> imm6\n");
2060 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 1, IS_A1 ($1));
2061 }
2062 else
2063 return yyerror ("Accu register expected");
2064 }
2065
2066 | REG ASSIGN REG GREATER_GREATER expr vmod
2067 {
2068 if ($6.r0 == 1)
2069 {
2070 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2071 {
2072 notethat ("dsp32shiftimm: dregs = dregs >> uimm5 (V)\n");
2073 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, 2, 0);
2074 }
2075 else
2076 return yyerror ("Register mismatch");
2077 }
2078 else
2079 {
2080 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2081 {
2082 notethat ("dsp32shiftimm: dregs = dregs >> uimm5\n");
2083 $$ = DSP32SHIFTIMM (2, &$1, -imm6 ($5), &$3, 2, 0);
2084 }
2085 else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 2)
2086 {
2087 notethat ("PTR2op: pregs = pregs >> 2\n");
2088 $$ = PTR2OP (&$1, &$3, 3);
2089 }
2090 else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 1)
2091 {
2092 notethat ("PTR2op: pregs = pregs >> 1\n");
2093 $$ = PTR2OP (&$1, &$3, 4);
2094 }
2095 else
2096 return yyerror ("Register mismatch");
2097 }
2098 }
2099 | HALF_REG ASSIGN HALF_REG GREATER_GREATER expr
2100 {
2101 if (IS_UIMM ($5, 5))
2102 {
2103 notethat ("dsp32shiftimm: dregs_half = dregs_half >> uimm5\n");
2104 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3, 2, HL2 ($1, $3));
2105 }
2106 else
2107 return yyerror ("Register mismatch");
2108 }
2109 | HALF_REG ASSIGN HALF_REG _GREATER_GREATER_GREATER expr smod
2110 {
2111 if (IS_UIMM ($5, 5))
2112 {
2113 notethat ("dsp32shiftimm: dregs_half = dregs_half >>> uimm5\n");
2114 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3,
2115 $6.s0, HL2 ($1, $3));
2116 }
2117 else
2118 return yyerror ("Register or modifier mismatch");
2119 }
2120
2121
2122 | REG ASSIGN REG _GREATER_GREATER_GREATER expr vsmod
2123 {
2124 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2125 {
2126 if ($6.r0)
2127 {
2128 /* Vector? */
2129 notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (V, .)\n");
2130 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2131 }
2132 else
2133 {
2134 notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (.)\n");
2135 $$ = DSP32SHIFTIMM (2, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2136 }
2137 }
2138 else
2139 return yyerror ("Register mismatch");
2140 }
2141
2142 | HALF_REG ASSIGN ONES REG
2143 {
2144 if (IS_DREG_L ($1) && IS_DREG ($4))
2145 {
2146 notethat ("dsp32shift: dregs_lo = ONES dregs\n");
2147 $$ = DSP32SHIFT (6, &$1, 0, &$4, 3, 0);
2148 }
2149 else
2150 return yyerror ("Register mismatch");
2151 }
2152
2153 | REG ASSIGN PACK LPAREN HALF_REG COMMA HALF_REG RPAREN
2154 {
2155 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2156 {
2157 notethat ("dsp32shift: dregs = PACK (dregs_hi , dregs_hi )\n");
2158 $$ = DSP32SHIFT (4, &$1, &$7, &$5, HL2 ($5, $7), 0);
2159 }
2160 else
2161 return yyerror ("Register mismatch");
2162 }
2163
2164 | HALF_REG ASSIGN CCREG ASSIGN BXORSHIFT LPAREN REG_A COMMA REG RPAREN
2165 {
2166 if (IS_DREG ($1)
2167 && $7.regno == REG_A0
2168 && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2169 {
2170 notethat ("dsp32shift: dregs_lo = CC = BXORSHIFT (A0 , dregs )\n");
2171 $$ = DSP32SHIFT (11, &$1, &$9, 0, 0, 0);
2172 }
2173 else
2174 return yyerror ("Register mismatch");
2175 }
2176
2177 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG RPAREN
2178 {
2179 if (IS_DREG ($1)
2180 && $7.regno == REG_A0
2181 && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2182 {
2183 notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , dregs)\n");
2184 $$ = DSP32SHIFT (11, &$1, &$9, 0, 1, 0);
2185 }
2186 else
2187 return yyerror ("Register mismatch");
2188 }
2189
2190 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2191 {
2192 if (IS_DREG ($1) && !IS_H ($1) && !REG_SAME ($7, $9))
2193 {
2194 notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , A1 , CC)\n");
2195 $$ = DSP32SHIFT (12, &$1, 0, 0, 1, 0);
2196 }
2197 else
2198 return yyerror ("Register mismatch");
2199 }
2200
2201 | a_assign ROT REG_A BY HALF_REG
2202 {
2203 if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2204 {
2205 notethat ("dsp32shift: Ax = ROT Ax BY dregs_lo\n");
2206 $$ = DSP32SHIFT (3, 0, &$5, 0, 2, IS_A1 ($1));
2207 }
2208 else
2209 return yyerror ("Register mismatch");
2210 }
2211
2212 | REG ASSIGN ROT REG BY HALF_REG
2213 {
2214 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2215 {
2216 notethat ("dsp32shift: dregs = ROT dregs BY dregs_lo\n");
2217 $$ = DSP32SHIFT (2, &$1, &$6, &$4, 3, 0);
2218 }
2219 else
2220 return yyerror ("Register mismatch");
2221 }
2222
2223 | a_assign ROT REG_A BY expr
2224 {
2225 if (IS_IMM ($5, 6))
2226 {
2227 notethat ("dsp32shiftimm: An = ROT An BY imm6\n");
2228 $$ = DSP32SHIFTIMM (3, 0, imm6 ($5), 0, 2, IS_A1 ($1));
2229 }
2230 else
2231 return yyerror ("Register mismatch");
2232 }
2233
2234 | REG ASSIGN ROT REG BY expr
2235 {
2236 if (IS_DREG ($1) && IS_DREG ($4) && IS_IMM ($6, 6))
2237 {
2238 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($6), &$4, 3, IS_A1 ($1));
2239 }
2240 else
2241 return yyerror ("Register mismatch");
2242 }
2243
2244 | HALF_REG ASSIGN SIGNBITS REG_A
2245 {
2246 if (IS_DREG_L ($1))
2247 {
2248 notethat ("dsp32shift: dregs_lo = SIGNBITS An\n");
2249 $$ = DSP32SHIFT (6, &$1, 0, 0, IS_A1 ($4), 0);
2250 }
2251 else
2252 return yyerror ("Register mismatch");
2253 }
2254
2255 | HALF_REG ASSIGN SIGNBITS REG
2256 {
2257 if (IS_DREG_L ($1) && IS_DREG ($4))
2258 {
2259 notethat ("dsp32shift: dregs_lo = SIGNBITS dregs\n");
2260 $$ = DSP32SHIFT (5, &$1, 0, &$4, 0, 0);
2261 }
2262 else
2263 return yyerror ("Register mismatch");
2264 }
2265
2266 | HALF_REG ASSIGN SIGNBITS HALF_REG
2267 {
2268 if (IS_DREG_L ($1))
2269 {
2270 notethat ("dsp32shift: dregs_lo = SIGNBITS dregs_lo\n");
2271 $$ = DSP32SHIFT (5, &$1, 0, &$4, 1 + IS_H ($4), 0);
2272 }
2273 else
2274 return yyerror ("Register mismatch");
2275 }
2276
2277 /* The ASR bit is just inverted here. */
2278 | HALF_REG ASSIGN VIT_MAX LPAREN REG RPAREN asr_asl
2279 {
2280 if (IS_DREG_L ($1) && IS_DREG ($5))
2281 {
2282 notethat ("dsp32shift: dregs_lo = VIT_MAX (dregs) (..)\n");
2283 $$ = DSP32SHIFT (9, &$1, 0, &$5, ($7.r0 ? 0 : 1), 0);
2284 }
2285 else
2286 return yyerror ("Register mismatch");
2287 }
2288
2289 | REG ASSIGN VIT_MAX LPAREN REG COMMA REG RPAREN asr_asl
2290 {
2291 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2292 {
2293 notethat ("dsp32shift: dregs = VIT_MAX (dregs, dregs) (ASR)\n");
2294 $$ = DSP32SHIFT (9, &$1, &$7, &$5, 2 | ($9.r0 ? 0 : 1), 0);
2295 }
2296 else
2297 return yyerror ("Register mismatch");
2298 }
2299
2300 | BITMUX LPAREN REG COMMA REG COMMA REG_A RPAREN asr_asl
2301 {
2302 if (IS_DREG ($3) && IS_DREG ($5) && !IS_A1 ($7))
2303 {
2304 notethat ("dsp32shift: BITMUX (dregs , dregs , A0) (ASR)\n");
2305 $$ = DSP32SHIFT (8, 0, &$3, &$5, $9.r0, 0);
2306 }
2307 else
2308 return yyerror ("Register mismatch");
2309 }
2310
2311 | a_assign BXORSHIFT LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2312 {
2313 if (!IS_A1 ($1) && !IS_A1 ($4) && IS_A1 ($6))
2314 {
2315 notethat ("dsp32shift: A0 = BXORSHIFT (A0 , A1 , CC )\n");
2316 $$ = DSP32SHIFT (12, 0, 0, 0, 0, 0);
2317 }
2318 else
2319 return yyerror ("Dregs expected");
2320 }
2321
2322
2323 /* LOGI2op: BITCLR (dregs, uimm5). */
2324 | BITCLR LPAREN REG COMMA expr RPAREN
2325 {
2326 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2327 {
2328 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2329 $$ = LOGI2OP ($3, uimm5 ($5), 4);
2330 }
2331 else
2332 return yyerror ("Register mismatch");
2333 }
2334
2335 /* LOGI2op: BITSET (dregs, uimm5). */
2336 | BITSET LPAREN REG COMMA expr RPAREN
2337 {
2338 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2339 {
2340 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2341 $$ = LOGI2OP ($3, uimm5 ($5), 2);
2342 }
2343 else
2344 return yyerror ("Register mismatch");
2345 }
2346
2347 /* LOGI2op: BITTGL (dregs, uimm5). */
2348 | BITTGL LPAREN REG COMMA expr RPAREN
2349 {
2350 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2351 {
2352 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2353 $$ = LOGI2OP ($3, uimm5 ($5), 3);
2354 }
2355 else
2356 return yyerror ("Register mismatch");
2357 }
2358
2359 | CCREG _ASSIGN_BANG BITTST LPAREN REG COMMA expr RPAREN
2360 {
2361 if (IS_DREG ($5) && IS_UIMM ($7, 5))
2362 {
2363 notethat ("LOGI2op: CC =! BITTST (dregs , uimm5 )\n");
2364 $$ = LOGI2OP ($5, uimm5 ($7), 0);
2365 }
2366 else
2367 return yyerror ("Register mismatch or value error");
2368 }
2369
2370 | CCREG ASSIGN BITTST LPAREN REG COMMA expr RPAREN
2371 {
2372 if (IS_DREG ($5) && IS_UIMM ($7, 5))
2373 {
2374 notethat ("LOGI2op: CC = BITTST (dregs , uimm5 )\n");
2375 $$ = LOGI2OP ($5, uimm5 ($7), 1);
2376 }
2377 else
2378 return yyerror ("Register mismatch or value error");
2379 }
2380
2381 | IF BANG CCREG REG ASSIGN REG
2382 {
2383 if ((IS_DREG ($4) || IS_PREG ($4))
2384 && (IS_DREG ($6) || IS_PREG ($6)))
2385 {
2386 notethat ("ccMV: IF ! CC gregs = gregs\n");
2387 $$ = CCMV (&$6, &$4, 0);
2388 }
2389 else
2390 return yyerror ("Register mismatch");
2391 }
2392
2393 | IF CCREG REG ASSIGN REG
2394 {
2395 if ((IS_DREG ($5) || IS_PREG ($5))
2396 && (IS_DREG ($3) || IS_PREG ($3)))
2397 {
2398 notethat ("ccMV: IF CC gregs = gregs\n");
2399 $$ = CCMV (&$5, &$3, 1);
2400 }
2401 else
2402 return yyerror ("Register mismatch");
2403 }
2404
2405 | IF BANG CCREG JUMP expr
2406 {
2407 if (IS_PCREL10 ($5))
2408 {
2409 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2410 $$ = BRCC (0, 0, $5);
2411 }
2412 else
2413 return yyerror ("Bad jump offset");
2414 }
2415
2416 | IF BANG CCREG JUMP expr LPAREN BP RPAREN
2417 {
2418 if (IS_PCREL10 ($5))
2419 {
2420 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2421 $$ = BRCC (0, 1, $5);
2422 }
2423 else
2424 return yyerror ("Bad jump offset");
2425 }
2426
2427 | IF CCREG JUMP expr
2428 {
2429 if (IS_PCREL10 ($4))
2430 {
2431 notethat ("BRCC: IF CC JUMP pcrel11m2\n");
2432 $$ = BRCC (1, 0, $4);
2433 }
2434 else
2435 return yyerror ("Bad jump offset");
2436 }
2437
2438 | IF CCREG JUMP expr LPAREN BP RPAREN
2439 {
2440 if (IS_PCREL10 ($4))
2441 {
2442 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2443 $$ = BRCC (1, 1, $4);
2444 }
2445 else
2446 return yyerror ("Bad jump offset");
2447 }
2448 | NOP
2449 {
2450 notethat ("ProgCtrl: NOP\n");
2451 $$ = PROGCTRL (0, 0);
2452 }
2453
2454 | RTS
2455 {
2456 notethat ("ProgCtrl: RTS\n");
2457 $$ = PROGCTRL (1, 0);
2458 }
2459
2460 | RTI
2461 {
2462 notethat ("ProgCtrl: RTI\n");
2463 $$ = PROGCTRL (1, 1);
2464 }
2465
2466 | RTX
2467 {
2468 notethat ("ProgCtrl: RTX\n");
2469 $$ = PROGCTRL (1, 2);
2470 }
2471
2472 | RTN
2473 {
2474 notethat ("ProgCtrl: RTN\n");
2475 $$ = PROGCTRL (1, 3);
2476 }
2477
2478 | RTE
2479 {
2480 notethat ("ProgCtrl: RTE\n");
2481 $$ = PROGCTRL (1, 4);
2482 }
2483
2484 | IDLE
2485 {
2486 notethat ("ProgCtrl: IDLE\n");
2487 $$ = PROGCTRL (2, 0);
2488 }
2489
2490 | CSYNC
2491 {
2492 notethat ("ProgCtrl: CSYNC\n");
2493 $$ = PROGCTRL (2, 3);
2494 }
2495
2496 | SSYNC
2497 {
2498 notethat ("ProgCtrl: SSYNC\n");
2499 $$ = PROGCTRL (2, 4);
2500 }
2501
2502 | EMUEXCPT
2503 {
2504 notethat ("ProgCtrl: EMUEXCPT\n");
2505 $$ = PROGCTRL (2, 5);
2506 }
2507
2508 | CLI REG
2509 {
2510 if (IS_DREG ($2))
2511 {
2512 notethat ("ProgCtrl: CLI dregs\n");
2513 $$ = PROGCTRL (3, $2.regno & CODE_MASK);
2514 }
2515 else
2516 return yyerror ("Dreg expected for CLI");
2517 }
2518
2519 | STI REG
2520 {
2521 if (IS_DREG ($2))
2522 {
2523 notethat ("ProgCtrl: STI dregs\n");
2524 $$ = PROGCTRL (4, $2.regno & CODE_MASK);
2525 }
2526 else
2527 return yyerror ("Dreg expected for STI");
2528 }
2529
2530 | JUMP LPAREN REG RPAREN
2531 {
2532 if (IS_PREG ($3))
2533 {
2534 notethat ("ProgCtrl: JUMP (pregs )\n");
2535 $$ = PROGCTRL (5, $3.regno & CODE_MASK);
2536 }
2537 else
2538 return yyerror ("Bad register for indirect jump");
2539 }
2540
2541 | CALL LPAREN REG RPAREN
2542 {
2543 if (IS_PREG ($3))
2544 {
2545 notethat ("ProgCtrl: CALL (pregs )\n");
2546 $$ = PROGCTRL (6, $3.regno & CODE_MASK);
2547 }
2548 else
2549 return yyerror ("Bad register for indirect call");
2550 }
2551
2552 | CALL LPAREN PC PLUS REG RPAREN
2553 {
2554 if (IS_PREG ($5))
2555 {
2556 notethat ("ProgCtrl: CALL (PC + pregs )\n");
2557 $$ = PROGCTRL (7, $5.regno & CODE_MASK);
2558 }
2559 else
2560 return yyerror ("Bad register for indirect call");
2561 }
2562
2563 | JUMP LPAREN PC PLUS REG RPAREN
2564 {
2565 if (IS_PREG ($5))
2566 {
2567 notethat ("ProgCtrl: JUMP (PC + pregs )\n");
2568 $$ = PROGCTRL (8, $5.regno & CODE_MASK);
2569 }
2570 else
2571 return yyerror ("Bad register for indirect jump");
2572 }
2573
2574 | RAISE expr
2575 {
2576 if (IS_UIMM ($2, 4))
2577 {
2578 notethat ("ProgCtrl: RAISE uimm4\n");
2579 $$ = PROGCTRL (9, uimm4 ($2));
2580 }
2581 else
2582 return yyerror ("Bad value for RAISE");
2583 }
2584
2585 | EXCPT expr
2586 {
2587 notethat ("ProgCtrl: EMUEXCPT\n");
2588 $$ = PROGCTRL (10, uimm4 ($2));
2589 }
2590
2591 | TESTSET LPAREN REG RPAREN
2592 {
2593 if (IS_PREG ($3))
2594 {
2595 notethat ("ProgCtrl: TESTSET (pregs )\n");
2596 $$ = PROGCTRL (11, $3.regno & CODE_MASK);
2597 }
2598 else
2599 return yyerror ("Preg expected");
2600 }
2601
2602 | JUMP expr
2603 {
2604 if (IS_PCREL12 ($2))
2605 {
2606 notethat ("UJUMP: JUMP pcrel12\n");
2607 $$ = UJUMP ($2);
2608 }
2609 else
2610 return yyerror ("Bad value for relative jump");
2611 }
2612
2613 | JUMP_DOT_S expr
2614 {
2615 if (IS_PCREL12 ($2))
2616 {
2617 notethat ("UJUMP: JUMP_DOT_S pcrel12\n");
2618 $$ = UJUMP($2);
2619 }
2620 else
2621 return yyerror ("Bad value for relative jump");
2622 }
2623
2624 | JUMP_DOT_L expr
2625 {
2626 if (IS_PCREL24 ($2))
2627 {
2628 notethat ("CALLa: jump.l pcrel24\n");
2629 $$ = CALLA ($2, 0);
2630 }
2631 else
2632 return yyerror ("Bad value for long jump");
2633 }
2634
2635 | JUMP_DOT_L pltpc
2636 {
2637 if (IS_PCREL24 ($2))
2638 {
2639 notethat ("CALLa: jump.l pcrel24\n");
2640 $$ = CALLA ($2, 2);
2641 }
2642 else
2643 return yyerror ("Bad value for long jump");
2644 }
2645
2646 | CALL expr
2647 {
2648 if (IS_PCREL24 ($2))
2649 {
2650 notethat ("CALLa: CALL pcrel25m2\n");
2651 $$ = CALLA ($2, 1);
2652 }
2653 else
2654 return yyerror ("Bad call address");
2655 }
2656 | CALL pltpc
2657 {
2658 if (IS_PCREL24 ($2))
2659 {
2660 notethat ("CALLa: CALL pcrel25m2\n");
2661 $$ = CALLA ($2, 2);
2662 }
2663 else
2664 return yyerror ("Bad call address");
2665 }
2666
2667 /* ALU2ops. */
2668 /* ALU2op: DIVQ (dregs, dregs). */
2669 | DIVQ LPAREN REG COMMA REG RPAREN
2670 {
2671 if (IS_DREG ($3) && IS_DREG ($5))
2672 $$ = ALU2OP (&$3, &$5, 8);
2673 else
2674 return yyerror ("Bad registers for DIVQ");
2675 }
2676
2677 | DIVS LPAREN REG COMMA REG RPAREN
2678 {
2679 if (IS_DREG ($3) && IS_DREG ($5))
2680 $$ = ALU2OP (&$3, &$5, 9);
2681 else
2682 return yyerror ("Bad registers for DIVS");
2683 }
2684
2685 | REG ASSIGN MINUS REG vsmod
2686 {
2687 if (IS_DREG ($1) && IS_DREG ($4))
2688 {
2689 if ($5.r0 == 0 && $5.s0 == 0 && $5.aop == 0)
2690 {
2691 notethat ("ALU2op: dregs = - dregs\n");
2692 $$ = ALU2OP (&$1, &$4, 14);
2693 }
2694 else if ($5.r0 == 1 && $5.s0 == 0 && $5.aop == 3)
2695 {
2696 notethat ("dsp32alu: dregs = - dregs (.)\n");
2697 $$ = DSP32ALU (15, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2698 }
2699 else
2700 {
2701 notethat ("dsp32alu: dregs = - dregs (.)\n");
2702 $$ = DSP32ALU (7, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2703 }
2704 }
2705 else
2706 return yyerror ("Dregs expected");
2707 }
2708
2709 | REG ASSIGN TILDA REG
2710 {
2711 if (IS_DREG ($1) && IS_DREG ($4))
2712 {
2713 notethat ("ALU2op: dregs = ~dregs\n");
2714 $$ = ALU2OP (&$1, &$4, 15);
2715 }
2716 else
2717 return yyerror ("Dregs expected");
2718 }
2719
2720 | REG _GREATER_GREATER_ASSIGN REG
2721 {
2722 if (IS_DREG ($1) && IS_DREG ($3))
2723 {
2724 notethat ("ALU2op: dregs >>= dregs\n");
2725 $$ = ALU2OP (&$1, &$3, 1);
2726 }
2727 else
2728 return yyerror ("Dregs expected");
2729 }
2730
2731 | REG _GREATER_GREATER_ASSIGN expr
2732 {
2733 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2734 {
2735 notethat ("LOGI2op: dregs >>= uimm5\n");
2736 $$ = LOGI2OP ($1, uimm5 ($3), 6);
2737 }
2738 else
2739 return yyerror ("Dregs expected or value error");
2740 }
2741
2742 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN REG
2743 {
2744 if (IS_DREG ($1) && IS_DREG ($3))
2745 {
2746 notethat ("ALU2op: dregs >>>= dregs\n");
2747 $$ = ALU2OP (&$1, &$3, 0);
2748 }
2749 else
2750 return yyerror ("Dregs expected");
2751 }
2752
2753 | REG _LESS_LESS_ASSIGN REG
2754 {
2755 if (IS_DREG ($1) && IS_DREG ($3))
2756 {
2757 notethat ("ALU2op: dregs <<= dregs\n");
2758 $$ = ALU2OP (&$1, &$3, 2);
2759 }
2760 else
2761 return yyerror ("Dregs expected");
2762 }
2763
2764 | REG _LESS_LESS_ASSIGN expr
2765 {
2766 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2767 {
2768 notethat ("LOGI2op: dregs <<= uimm5\n");
2769 $$ = LOGI2OP ($1, uimm5 ($3), 7);
2770 }
2771 else
2772 return yyerror ("Dregs expected or const value error");
2773 }
2774
2775
2776 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN expr
2777 {
2778 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2779 {
2780 notethat ("LOGI2op: dregs >>>= uimm5\n");
2781 $$ = LOGI2OP ($1, uimm5 ($3), 5);
2782 }
2783 else
2784 return yyerror ("Dregs expected");
2785 }
2786
2787 /* Cache Control. */
2788
2789 | FLUSH LBRACK REG RBRACK
2790 {
2791 notethat ("CaCTRL: FLUSH [ pregs ]\n");
2792 if (IS_PREG ($3))
2793 $$ = CACTRL (&$3, 0, 2);
2794 else
2795 return yyerror ("Bad register(s) for FLUSH");
2796 }
2797
2798 | FLUSH reg_with_postinc
2799 {
2800 if (IS_PREG ($2))
2801 {
2802 notethat ("CaCTRL: FLUSH [ pregs ++ ]\n");
2803 $$ = CACTRL (&$2, 1, 2);
2804 }
2805 else
2806 return yyerror ("Bad register(s) for FLUSH");
2807 }
2808
2809 | FLUSHINV LBRACK REG RBRACK
2810 {
2811 if (IS_PREG ($3))
2812 {
2813 notethat ("CaCTRL: FLUSHINV [ pregs ]\n");
2814 $$ = CACTRL (&$3, 0, 1);
2815 }
2816 else
2817 return yyerror ("Bad register(s) for FLUSH");
2818 }
2819
2820 | FLUSHINV reg_with_postinc
2821 {
2822 if (IS_PREG ($2))
2823 {
2824 notethat ("CaCTRL: FLUSHINV [ pregs ++ ]\n");
2825 $$ = CACTRL (&$2, 1, 1);
2826 }
2827 else
2828 return yyerror ("Bad register(s) for FLUSH");
2829 }
2830
2831 /* CaCTRL: IFLUSH [pregs]. */
2832 | IFLUSH LBRACK REG RBRACK
2833 {
2834 if (IS_PREG ($3))
2835 {
2836 notethat ("CaCTRL: IFLUSH [ pregs ]\n");
2837 $$ = CACTRL (&$3, 0, 3);
2838 }
2839 else
2840 return yyerror ("Bad register(s) for FLUSH");
2841 }
2842
2843 | IFLUSH reg_with_postinc
2844 {
2845 if (IS_PREG ($2))
2846 {
2847 notethat ("CaCTRL: IFLUSH [ pregs ++ ]\n");
2848 $$ = CACTRL (&$2, 1, 3);
2849 }
2850 else
2851 return yyerror ("Bad register(s) for FLUSH");
2852 }
2853
2854 | PREFETCH LBRACK REG RBRACK
2855 {
2856 if (IS_PREG ($3))
2857 {
2858 notethat ("CaCTRL: PREFETCH [ pregs ]\n");
2859 $$ = CACTRL (&$3, 0, 0);
2860 }
2861 else
2862 return yyerror ("Bad register(s) for PREFETCH");
2863 }
2864
2865 | PREFETCH reg_with_postinc
2866 {
2867 if (IS_PREG ($2))
2868 {
2869 notethat ("CaCTRL: PREFETCH [ pregs ++ ]\n");
2870 $$ = CACTRL (&$2, 1, 0);
2871 }
2872 else
2873 return yyerror ("Bad register(s) for PREFETCH");
2874 }
2875
2876 /* LOAD/STORE. */
2877 /* LDST: B [ pregs <post_op> ] = dregs. */
2878
2879 | B LBRACK REG post_op RBRACK ASSIGN REG
2880 {
2881 if (IS_PREG ($3) && IS_DREG ($7))
2882 {
2883 notethat ("LDST: B [ pregs <post_op> ] = dregs\n");
2884 $$ = LDST (&$3, &$7, $4.x0, 2, 0, 1);
2885 }
2886 else
2887 return yyerror ("Register mismatch");
2888 }
2889
2890 /* LDSTidxI: B [ pregs + imm16 ] = dregs. */
2891 | B LBRACK REG plus_minus expr RBRACK ASSIGN REG
2892 {
2893 if (IS_PREG ($3) && IS_RANGE(16, $5, $4.r0, 1) && IS_DREG ($8))
2894 {
2895 notethat ("LDST: B [ pregs + imm16 ] = dregs\n");
2896 if ($4.r0)
2897 neg_value ($5);
2898 $$ = LDSTIDXI (&$3, &$8, 1, 2, 0, $5);
2899 }
2900 else
2901 return yyerror ("Register mismatch or const size wrong");
2902 }
2903
2904
2905 /* LDSTii: W [ pregs + uimm4s2 ] = dregs. */
2906 | W LBRACK REG plus_minus expr RBRACK ASSIGN REG
2907 {
2908 if (IS_PREG ($3) && IS_URANGE (4, $5, $4.r0, 2) && IS_DREG ($8))
2909 {
2910 notethat ("LDSTii: W [ pregs +- uimm5m2 ] = dregs\n");
2911 $$ = LDSTII (&$3, &$8, $5, 1, 1);
2912 }
2913 else if (IS_PREG ($3) && IS_RANGE(16, $5, $4.r0, 2) && IS_DREG ($8))
2914 {
2915 notethat ("LDSTidxI: W [ pregs + imm17m2 ] = dregs\n");
2916 if ($4.r0)
2917 neg_value ($5);
2918 $$ = LDSTIDXI (&$3, &$8, 1, 1, 0, $5);
2919 }
2920 else
2921 return yyerror ("Bad register(s) or wrong constant size");
2922 }
2923
2924 /* LDST: W [ pregs <post_op> ] = dregs. */
2925 | W LBRACK REG post_op RBRACK ASSIGN REG
2926 {
2927 if (IS_PREG ($3) && IS_DREG ($7))
2928 {
2929 notethat ("LDST: W [ pregs <post_op> ] = dregs\n");
2930 $$ = LDST (&$3, &$7, $4.x0, 1, 0, 1);
2931 }
2932 else
2933 return yyerror ("Bad register(s) for STORE");
2934 }
2935
2936 | W LBRACK REG post_op RBRACK ASSIGN HALF_REG
2937 {
2938 if (IS_IREG ($3))
2939 {
2940 notethat ("dspLDST: W [ iregs <post_op> ] = dregs_half\n");
2941 $$ = DSPLDST (&$3, 1 + IS_H ($7), &$7, $4.x0, 1);
2942 }
2943 else if ($4.x0 == 2 && IS_PREG ($3) && IS_DREG ($7))
2944 {
2945 notethat ("LDSTpmod: W [ pregs <post_op>] = dregs_half\n");
2946 $$ = LDSTPMOD (&$3, &$7, &$3, 1 + IS_H ($7), 1);
2947
2948 }
2949 else
2950 return yyerror ("Bad register(s) for STORE");
2951 }
2952
2953 /* LDSTiiFP: [ FP - const ] = dpregs. */
2954 | LBRACK REG plus_minus expr RBRACK ASSIGN REG
2955 {
2956 Expr_Node *tmp = $4;
2957 int ispreg = IS_PREG ($7);
2958
2959 if (!IS_PREG ($2))
2960 return yyerror ("Preg expected for indirect");
2961
2962 if (!IS_DREG ($7) && !ispreg)
2963 return yyerror ("Bad source register for STORE");
2964
2965 if ($3.r0)
2966 tmp = unary (Expr_Op_Type_NEG, tmp);
2967
2968 if (in_range_p (tmp, 0, 63, 3))
2969 {
2970 notethat ("LDSTii: dpregs = [ pregs + uimm6m4 ]\n");
2971 $$ = LDSTII (&$2, &$7, tmp, 1, ispreg ? 3 : 0);
2972 }
2973 else if ($2.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
2974 {
2975 notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
2976 tmp = unary (Expr_Op_Type_NEG, tmp);
2977 $$ = LDSTIIFP (tmp, &$7, 1);
2978 }
2979 else if (in_range_p (tmp, -131072, 131071, 3))
2980 {
2981 notethat ("LDSTidxI: [ pregs + imm18m4 ] = dpregs\n");
2982 $$ = LDSTIDXI (&$2, &$7, 1, 0, ispreg ? 1: 0, tmp);
2983 }
2984 else
2985 return yyerror ("Displacement out of range for store");
2986 }
2987
2988 | REG ASSIGN W LBRACK REG plus_minus expr RBRACK xpmod
2989 {
2990 if (IS_DREG ($1) && IS_PREG ($5) && IS_URANGE (4, $7, $6.r0, 2))
2991 {
2992 notethat ("LDSTii: dregs = W [ pregs + uimm4s2 ] (.)\n");
2993 $$ = LDSTII (&$5, &$1, $7, 0, 1 << $9.r0);
2994 }
2995 else if (IS_DREG ($1) && IS_PREG ($5) && IS_RANGE(16, $7, $6.r0, 2))
2996 {
2997 notethat ("LDSTidxI: dregs = W [ pregs + imm17m2 ] (.)\n");
2998 if ($6.r0)
2999 neg_value ($7);
3000 $$ = LDSTIDXI (&$5, &$1, 0, 1, $9.r0, $7);
3001 }
3002 else
3003 return yyerror ("Bad register or constant for LOAD");
3004 }
3005
3006 | HALF_REG ASSIGN W LBRACK REG post_op RBRACK
3007 {
3008 if (IS_IREG ($5))
3009 {
3010 notethat ("dspLDST: dregs_half = W [ iregs ]\n");
3011 $$ = DSPLDST(&$5, 1 + IS_H ($1), &$1, $6.x0, 0);
3012 }
3013 else if ($6.x0 == 2 && IS_DREG ($1) && IS_PREG ($5))
3014 {
3015 notethat ("LDSTpmod: dregs_half = W [ pregs ]\n");
3016 $$ = LDSTPMOD (&$5, &$1, &$5, 1 + IS_H ($1), 0);
3017 }
3018 else
3019 return yyerror ("Bad register or post_op for LOAD");
3020 }
3021
3022
3023 | REG ASSIGN W LBRACK REG post_op RBRACK xpmod
3024 {
3025 if (IS_DREG ($1) && IS_PREG ($5))
3026 {
3027 notethat ("LDST: dregs = W [ pregs <post_op> ] (.)\n");
3028 $$ = LDST (&$5, &$1, $6.x0, 1, $8.r0, 0);
3029 }
3030 else
3031 return yyerror ("Bad register for LOAD");
3032 }
3033
3034 | REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK xpmod
3035 {
3036 if (IS_DREG ($1) && IS_PREG ($5) && IS_PREG ($7))
3037 {
3038 notethat ("LDSTpmod: dregs = W [ pregs ++ pregs ] (.)\n");
3039 $$ = LDSTPMOD (&$5, &$1, &$7, 3, $9.r0);
3040 }
3041 else
3042 return yyerror ("Bad register for LOAD");
3043 }
3044
3045 | HALF_REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK
3046 {
3047 if (IS_DREG ($1) && IS_PREG ($5) && IS_PREG ($7))
3048 {
3049 notethat ("LDSTpmod: dregs_half = W [ pregs ++ pregs ]\n");
3050 $$ = LDSTPMOD (&$5, &$1, &$7, 1 + IS_H ($1), 0);
3051 }
3052 else
3053 return yyerror ("Bad register for LOAD");
3054 }
3055
3056 | LBRACK REG post_op RBRACK ASSIGN REG
3057 {
3058 if (IS_IREG ($2) && IS_DREG ($6))
3059 {
3060 notethat ("dspLDST: [ iregs <post_op> ] = dregs\n");
3061 $$ = DSPLDST(&$2, 0, &$6, $3.x0, 1);
3062 }
3063 else if (IS_PREG ($2) && IS_DREG ($6))
3064 {
3065 notethat ("LDST: [ pregs <post_op> ] = dregs\n");
3066 $$ = LDST (&$2, &$6, $3.x0, 0, 0, 1);
3067 }
3068 else if (IS_PREG ($2) && IS_PREG ($6))
3069 {
3070 notethat ("LDST: [ pregs <post_op> ] = pregs\n");
3071 $$ = LDST (&$2, &$6, $3.x0, 0, 1, 1);
3072 }
3073 else
3074 return yyerror ("Bad register for STORE");
3075 }
3076
3077 | LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN REG
3078 {
3079 if (! IS_DREG ($7))
3080 return yyerror ("Expected Dreg for last argument");
3081
3082 if (IS_IREG ($2) && IS_MREG ($4))
3083 {
3084 notethat ("dspLDST: [ iregs ++ mregs ] = dregs\n");
3085 $$ = DSPLDST(&$2, $4.regno & CODE_MASK, &$7, 3, 1);
3086 }
3087 else if (IS_PREG ($2) && IS_PREG ($4))
3088 {
3089 notethat ("LDSTpmod: [ pregs ++ pregs ] = dregs\n");
3090 $$ = LDSTPMOD (&$2, &$7, &$4, 0, 1);
3091 }
3092 else
3093 return yyerror ("Bad register for STORE");
3094 }
3095
3096 | W LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN HALF_REG
3097 {
3098 if (!IS_DREG ($8))
3099 return yyerror ("Expect Dreg as last argument");
3100 if (IS_PREG ($3) && IS_PREG ($5))
3101 {
3102 notethat ("LDSTpmod: W [ pregs ++ pregs ] = dregs_half\n");
3103 $$ = LDSTPMOD (&$3, &$8, &$5, 1 + IS_H ($8), 1);
3104 }
3105 else
3106 return yyerror ("Bad register for STORE");
3107 }
3108
3109 | REG ASSIGN B LBRACK REG plus_minus expr RBRACK xpmod
3110 {
3111 if (IS_DREG ($1) && IS_PREG ($5) && IS_RANGE(16, $7, $6.r0, 1))
3112 {
3113 notethat ("LDSTidxI: dregs = B [ pregs + imm16 ] (%c)\n",
3114 $9.r0 ? 'X' : 'Z');
3115 if ($6.r0)
3116 neg_value ($7);
3117 $$ = LDSTIDXI (&$5, &$1, 0, 2, $9.r0, $7);
3118 }
3119 else
3120 return yyerror ("Bad register or value for LOAD");
3121 }
3122
3123 | REG ASSIGN B LBRACK REG post_op RBRACK xpmod
3124 {
3125 if (IS_DREG ($1) && IS_PREG ($5))
3126 {
3127 notethat ("LDST: dregs = B [ pregs <post_op> ] (%c)\n",
3128 $8.r0 ? 'X' : 'Z');
3129 $$ = LDST (&$5, &$1, $6.x0, 2, $8.r0, 0);
3130 }
3131 else
3132 return yyerror ("Bad register for LOAD");
3133 }
3134
3135 | REG ASSIGN LBRACK REG _PLUS_PLUS REG RBRACK
3136 {
3137 if (IS_DREG ($1) && IS_IREG ($4) && IS_MREG ($6))
3138 {
3139 notethat ("dspLDST: dregs = [ iregs ++ mregs ]\n");
3140 $$ = DSPLDST(&$4, $6.regno & CODE_MASK, &$1, 3, 0);
3141 }
3142 else if (IS_DREG ($1) && IS_PREG ($4) && IS_PREG ($6))
3143 {
3144 notethat ("LDSTpmod: dregs = [ pregs ++ pregs ]\n");
3145 $$ = LDSTPMOD (&$4, &$1, &$6, 0, 0);
3146 }
3147 else
3148 return yyerror ("Bad register for LOAD");
3149 }
3150
3151 | REG ASSIGN LBRACK REG plus_minus got_or_expr RBRACK
3152 {
3153 Expr_Node *tmp = $6;
3154 int ispreg = IS_PREG ($1);
3155 int isgot = IS_RELOC($6);
3156
3157 if (!IS_PREG ($4))
3158 return yyerror ("Preg expected for indirect");
3159
3160 if (!IS_DREG ($1) && !ispreg)
3161 return yyerror ("Bad destination register for LOAD");
3162
3163 if ($5.r0)
3164 tmp = unary (Expr_Op_Type_NEG, tmp);
3165
3166 if(isgot){
3167 notethat ("LDSTidxI: dpregs = [ pregs + sym@got ]\n");
3168 $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1: 0, tmp);
3169 }
3170 else if (in_range_p (tmp, 0, 63, 3))
3171 {
3172 notethat ("LDSTii: dpregs = [ pregs + uimm7m4 ]\n");
3173 $$ = LDSTII (&$4, &$1, tmp, 0, ispreg ? 3 : 0);
3174 }
3175 else if ($4.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3176 {
3177 notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3178 tmp = unary (Expr_Op_Type_NEG, tmp);
3179 $$ = LDSTIIFP (tmp, &$1, 0);
3180 }
3181 else if (in_range_p (tmp, -131072, 131071, 3))
3182 {
3183 notethat ("LDSTidxI: dpregs = [ pregs + imm18m4 ]\n");
3184 $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1: 0, tmp);
3185
3186 }
3187 else
3188 return yyerror ("Displacement out of range for load");
3189 }
3190
3191 | REG ASSIGN LBRACK REG post_op RBRACK
3192 {
3193 if (IS_DREG ($1) && IS_IREG ($4))
3194 {
3195 notethat ("dspLDST: dregs = [ iregs <post_op> ]\n");
3196 $$ = DSPLDST (&$4, 0, &$1, $5.x0, 0);
3197 }
3198 else if (IS_DREG ($1) && IS_PREG ($4))
3199 {
3200 notethat ("LDST: dregs = [ pregs <post_op> ]\n");
3201 $$ = LDST (&$4, &$1, $5.x0, 0, 0, 0);
3202 }
3203 else if (IS_PREG ($1) && IS_PREG ($4))
3204 {
3205 if (REG_SAME ($1, $4) && $5.x0 != 2)
3206 return yyerror ("Pregs can't be same");
3207
3208 notethat ("LDST: pregs = [ pregs <post_op> ]\n");
3209 $$ = LDST (&$4, &$1, $5.x0, 0, 1, 0);
3210 }
3211 else if ($4.regno == REG_SP && IS_ALLREG ($1) && $5.x0 == 0)
3212 {
3213 notethat ("PushPopReg: allregs = [ SP ++ ]\n");
3214 $$ = PUSHPOPREG (&$1, 0);
3215 }
3216 else
3217 return yyerror ("Bad register or value");
3218 }
3219
3220
3221
3222 /* Expression Assignment. */
3223
3224 | expr ASSIGN expr
3225 {
3226 bfin_equals ($1);
3227 $$ = 0;
3228 }
3229
3230
3231 /* PushPopMultiple. */
3232 | reg_with_predec ASSIGN LPAREN REG COLON expr COMMA REG COLON expr RPAREN
3233 {
3234 if ($1.regno != REG_SP)
3235 yyerror ("Stack Pointer expected");
3236 if ($4.regno == REG_R7
3237 && IN_RANGE ($6, 0, 7)
3238 && $8.regno == REG_P5
3239 && IN_RANGE ($10, 0, 5))
3240 {
3241 notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim , P5 : reglim )\n");
3242 $$ = PUSHPOPMULTIPLE (imm5 ($6), imm5 ($10), 1, 1, 1);
3243 }
3244 else
3245 return yyerror ("Bad register for PushPopMultiple");
3246 }
3247
3248 | reg_with_predec ASSIGN LPAREN REG COLON expr RPAREN
3249 {
3250 if ($1.regno != REG_SP)
3251 yyerror ("Stack Pointer expected");
3252
3253 if ($4.regno == REG_R7 && IN_RANGE ($6, 0, 7))
3254 {
3255 notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim )\n");
3256 $$ = PUSHPOPMULTIPLE (imm5 ($6), 0, 1, 0, 1);
3257 }
3258 else if ($4.regno == REG_P5 && IN_RANGE ($6, 0, 6))
3259 {
3260 notethat ("PushPopMultiple: [ -- SP ] = (P5 : reglim )\n");
3261 $$ = PUSHPOPMULTIPLE (0, imm5 ($6), 0, 1, 1);
3262 }
3263 else
3264 return yyerror ("Bad register for PushPopMultiple");
3265 }
3266
3267 | LPAREN REG COLON expr COMMA REG COLON expr RPAREN ASSIGN reg_with_postinc
3268 {
3269 if ($11.regno != REG_SP)
3270 yyerror ("Stack Pointer expected");
3271 if ($2.regno == REG_R7 && (IN_RANGE ($4, 0, 7))
3272 && $6.regno == REG_P5 && (IN_RANGE ($8, 0, 6)))
3273 {
3274 notethat ("PushPopMultiple: (R7 : reglim , P5 : reglim ) = [ SP ++ ]\n");
3275 $$ = PUSHPOPMULTIPLE (imm5 ($4), imm5 ($8), 1, 1, 0);
3276 }
3277 else
3278 return yyerror ("Bad register range for PushPopMultiple");
3279 }
3280
3281 | LPAREN REG COLON expr RPAREN ASSIGN reg_with_postinc
3282 {
3283 if ($7.regno != REG_SP)
3284 yyerror ("Stack Pointer expected");
3285
3286 if ($2.regno == REG_R7 && IN_RANGE ($4, 0, 7))
3287 {
3288 notethat ("PushPopMultiple: (R7 : reglim ) = [ SP ++ ]\n");
3289 $$ = PUSHPOPMULTIPLE (imm5 ($4), 0, 1, 0, 0);
3290 }
3291 else if ($2.regno == REG_P5 && IN_RANGE ($4, 0, 6))
3292 {
3293 notethat ("PushPopMultiple: (P5 : reglim ) = [ SP ++ ]\n");
3294 $$ = PUSHPOPMULTIPLE (0, imm5 ($4), 0, 1, 0);
3295 }
3296 else
3297 return yyerror ("Bad register range for PushPopMultiple");
3298 }
3299
3300 | reg_with_predec ASSIGN REG
3301 {
3302 if ($1.regno != REG_SP)
3303 yyerror ("Stack Pointer expected");
3304
3305 if (IS_ALLREG ($3))
3306 {
3307 notethat ("PushPopReg: [ -- SP ] = allregs\n");
3308 $$ = PUSHPOPREG (&$3, 1);
3309 }
3310 else
3311 return yyerror ("Bad register for PushPopReg");
3312 }
3313
3314 /* Linkage. */
3315
3316 | LINK expr
3317 {
3318 if (IS_URANGE (16, $2, 0, 4))
3319 $$ = LINKAGE (0, uimm16s4 ($2));
3320 else
3321 return yyerror ("Bad constant for LINK");
3322 }
3323
3324 | UNLINK
3325 {
3326 notethat ("linkage: UNLINK\n");
3327 $$ = LINKAGE (1, 0);
3328 }
3329
3330
3331 /* LSETUP. */
3332
3333 | LSETUP LPAREN expr COMMA expr RPAREN REG
3334 {
3335 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5) && IS_CREG ($7))
3336 {
3337 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters\n");
3338 $$ = LOOPSETUP ($3, &$7, 0, $5, 0);
3339 }
3340 else
3341 return yyerror ("Bad register or values for LSETUP");
3342
3343 }
3344 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG
3345 {
3346 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3347 && IS_PREG ($9) && IS_CREG ($7))
3348 {
3349 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs\n");
3350 $$ = LOOPSETUP ($3, &$7, 1, $5, &$9);
3351 }
3352 else
3353 return yyerror ("Bad register or values for LSETUP");
3354 }
3355
3356 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG GREATER_GREATER expr
3357 {
3358 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3359 && IS_PREG ($9) && IS_CREG ($7)
3360 && EXPR_VALUE ($11) == 1)
3361 {
3362 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs >> 1\n");
3363 $$ = LOOPSETUP ($3, &$7, 3, $5, &$9);
3364 }
3365 else
3366 return yyerror ("Bad register or values for LSETUP");
3367 }
3368
3369 /* LOOP. */
3370 | LOOP expr REG
3371 {
3372 if (!IS_RELOC ($2))
3373 return yyerror ("Invalid expression in loop statement");
3374 if (!IS_CREG ($3))
3375 return yyerror ("Invalid loop counter register");
3376 $$ = bfin_gen_loop ($2, &$3, 0, 0);
3377 }
3378 | LOOP expr REG ASSIGN REG
3379 {
3380 if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3))
3381 {
3382 notethat ("Loop: LOOP expr counters = pregs\n");
3383 $$ = bfin_gen_loop ($2, &$3, 1, &$5);
3384 }
3385 else
3386 return yyerror ("Bad register or values for LOOP");
3387 }
3388 | LOOP expr REG ASSIGN REG GREATER_GREATER expr
3389 {
3390 if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3) && EXPR_VALUE ($7) == 1)
3391 {
3392 notethat ("Loop: LOOP expr counters = pregs >> 1\n");
3393 $$ = bfin_gen_loop ($2, &$3, 3, &$5);
3394 }
3395 else
3396 return yyerror ("Bad register or values for LOOP");
3397 }
3398 /* pseudoDEBUG. */
3399
3400 | DBG
3401 {
3402 notethat ("pseudoDEBUG: DBG\n");
3403 $$ = bfin_gen_pseudodbg (3, 7, 0);
3404 }
3405 | DBG REG_A
3406 {
3407 notethat ("pseudoDEBUG: DBG REG_A\n");
3408 $$ = bfin_gen_pseudodbg (3, IS_A1 ($2), 0);
3409 }
3410 | DBG REG
3411 {
3412 notethat ("pseudoDEBUG: DBG allregs\n");
3413 $$ = bfin_gen_pseudodbg (0, $2.regno & CODE_MASK, $2.regno & CLASS_MASK);
3414 }
3415
3416 | DBGCMPLX LPAREN REG RPAREN
3417 {
3418 if (!IS_DREG ($3))
3419 return yyerror ("Dregs expected");
3420 notethat ("pseudoDEBUG: DBGCMPLX (dregs )\n");
3421 $$ = bfin_gen_pseudodbg (3, 6, $3.regno & CODE_MASK);
3422 }
3423
3424 | DBGHALT
3425 {
3426 notethat ("psedoDEBUG: DBGHALT\n");
3427 $$ = bfin_gen_pseudodbg (3, 5, 0);
3428 }
3429
3430 | DBGA LPAREN HALF_REG COMMA expr RPAREN
3431 {
3432 notethat ("pseudodbg_assert: DBGA (dregs_lo , uimm16 )\n");
3433 $$ = bfin_gen_pseudodbg_assert (IS_H ($3), &$3, uimm16 ($5));
3434 }
3435
3436 | DBGAH LPAREN REG COMMA expr RPAREN
3437 {
3438 notethat ("pseudodbg_assert: DBGAH (dregs , uimm16 )\n");
3439 $$ = bfin_gen_pseudodbg_assert (3, &$3, uimm16 ($5));
3440 }
3441
3442 | DBGAL LPAREN REG COMMA expr RPAREN
3443 {
3444 notethat ("psedodbg_assert: DBGAL (dregs , uimm16 )\n");
3445 $$ = bfin_gen_pseudodbg_assert (2, &$3, uimm16 ($5));
3446 }
3447
3448
3449 ;
3450
3451 /* AUX RULES. */
3452
3453 /* Register rules. */
3454
3455 REG_A: REG_A_DOUBLE_ZERO
3456 {
3457 $$ = $1;
3458 }
3459 | REG_A_DOUBLE_ONE
3460 {
3461 $$ = $1;
3462 }
3463 ;
3464
3465
3466 /* Modifiers. */
3467
3468 opt_mode:
3469 {
3470 $$.MM = 0;
3471 $$.mod = 0;
3472 }
3473 | LPAREN M COMMA MMOD RPAREN
3474 {
3475 $$.MM = 1;
3476 $$.mod = $4;
3477 }
3478 | LPAREN MMOD COMMA M RPAREN
3479 {
3480 $$.MM = 1;
3481 $$.mod = $2;
3482 }
3483 | LPAREN MMOD RPAREN
3484 {
3485 $$.MM = 0;
3486 $$.mod = $2;
3487 }
3488 | LPAREN M RPAREN
3489 {
3490 $$.MM = 1;
3491 $$.mod = 0;
3492 }
3493 ;
3494
3495 asr_asl: LPAREN ASL RPAREN
3496 {
3497 $$.r0 = 1;
3498 }
3499 | LPAREN ASR RPAREN
3500 {
3501 $$.r0 = 0;
3502 }
3503 ;
3504
3505 sco:
3506 {
3507 $$.s0 = 0;
3508 $$.x0 = 0;
3509 }
3510 | S
3511 {
3512 $$.s0 = 1;
3513 $$.x0 = 0;
3514 }
3515 | CO
3516 {
3517 $$.s0 = 0;
3518 $$.x0 = 1;
3519 }
3520 | SCO
3521 {
3522 $$.s0 = 1;
3523 $$.x0 = 1;
3524 }
3525 ;
3526
3527 asr_asl_0:
3528 ASL
3529 {
3530 $$.r0 = 1;
3531 }
3532 | ASR
3533 {
3534 $$.r0 = 0;
3535 }
3536 ;
3537
3538 amod0:
3539 {
3540 $$.s0 = 0;
3541 $$.x0 = 0;
3542 }
3543 | LPAREN sco RPAREN
3544 {
3545 $$.s0 = $2.s0;
3546 $$.x0 = $2.x0;
3547 }
3548 ;
3549
3550 amod1:
3551 {
3552 $$.s0 = 0;
3553 $$.x0 = 0;
3554 $$.aop = 0;
3555 }
3556 | LPAREN NS RPAREN
3557 {
3558 $$.s0 = 0;
3559 $$.x0 = 0;
3560 $$.aop = 1;
3561 }
3562 | LPAREN S RPAREN
3563 {
3564 $$.s0 = 1;
3565 $$.x0 = 0;
3566 $$.aop = 1;
3567 }
3568 ;
3569
3570 amod2:
3571 {
3572 $$.r0 = 0;
3573 $$.s0 = 0;
3574 $$.x0 = 0;
3575 }
3576 | LPAREN asr_asl_0 RPAREN
3577 {
3578 $$.r0 = 2 + $2.r0;
3579 $$.s0 = 0;
3580 $$.x0 = 0;
3581 }
3582 | LPAREN sco RPAREN
3583 {
3584 $$.r0 = 0;
3585 $$.s0 = $2.s0;
3586 $$.x0 = $2.x0;
3587 }
3588 | LPAREN asr_asl_0 COMMA sco RPAREN
3589 {
3590 $$.r0 = 2 + $2.r0;
3591 $$.s0 = $4.s0;
3592 $$.x0 = $4.x0;
3593 }
3594 | LPAREN sco COMMA asr_asl_0 RPAREN
3595 {
3596 $$.r0 = 2 + $4.r0;
3597 $$.s0 = $2.s0;
3598 $$.x0 = $2.x0;
3599 }
3600 ;
3601
3602 xpmod:
3603 {
3604 $$.r0 = 0;
3605 }
3606 | LPAREN Z RPAREN
3607 {
3608 $$.r0 = 0;
3609 }
3610 | LPAREN X RPAREN
3611 {
3612 $$.r0 = 1;
3613 }
3614 ;
3615
3616 xpmod1:
3617 {
3618 $$.r0 = 0;
3619 }
3620 | LPAREN X RPAREN
3621 {
3622 $$.r0 = 0;
3623 }
3624 | LPAREN Z RPAREN
3625 {
3626 $$.r0 = 1;
3627 }
3628 ;
3629
3630 vsmod:
3631 {
3632 $$.r0 = 0;
3633 $$.s0 = 0;
3634 $$.aop = 0;
3635 }
3636 | LPAREN NS RPAREN
3637 {
3638 $$.r0 = 0;
3639 $$.s0 = 0;
3640 $$.aop = 3;
3641 }
3642 | LPAREN S RPAREN
3643 {
3644 $$.r0 = 0;
3645 $$.s0 = 1;
3646 $$.aop = 3;
3647 }
3648 | LPAREN V RPAREN
3649 {
3650 $$.r0 = 1;
3651 $$.s0 = 0;
3652 $$.aop = 3;
3653 }
3654 | LPAREN V COMMA S RPAREN
3655 {
3656 $$.r0 = 1;
3657 $$.s0 = 1;
3658 }
3659 | LPAREN S COMMA V RPAREN
3660 {
3661 $$.r0 = 1;
3662 $$.s0 = 1;
3663 }
3664 ;
3665
3666 vmod:
3667 {
3668 $$.r0 = 0;
3669 }
3670 | LPAREN V RPAREN
3671 {
3672 $$.r0 = 1;
3673 }
3674 ;
3675
3676 smod:
3677 {
3678 $$.s0 = 0;
3679 }
3680 | LPAREN S RPAREN
3681 {
3682 $$.s0 = 1;
3683 }
3684 ;
3685
3686 searchmod:
3687 GE
3688 {
3689 $$.r0 = 1;
3690 }
3691 | GT
3692 {
3693 $$.r0 = 0;
3694 }
3695 | LE
3696 {
3697 $$.r0 = 3;
3698 }
3699 | LT
3700 {
3701 $$.r0 = 2;
3702 }
3703 ;
3704
3705 aligndir:
3706 {
3707 $$.r0 = 0;
3708 }
3709 | LPAREN R RPAREN
3710 {
3711 $$.r0 = 1;
3712 }
3713 ;
3714
3715 byteop_mod:
3716 LPAREN R RPAREN
3717 {
3718 $$.r0 = 0;
3719 $$.s0 = 1;
3720 }
3721 | LPAREN MMOD RPAREN
3722 {
3723 if ($2 != M_T)
3724 return yyerror ("Bad modifier");
3725 $$.r0 = 1;
3726 $$.s0 = 0;
3727 }
3728 | LPAREN MMOD COMMA R RPAREN
3729 {
3730 if ($2 != M_T)
3731 return yyerror ("Bad modifier");
3732 $$.r0 = 1;
3733 $$.s0 = 1;
3734 }
3735 | LPAREN R COMMA MMOD RPAREN
3736 {
3737 if ($4 != M_T)
3738 return yyerror ("Bad modifier");
3739 $$.r0 = 1;
3740 $$.s0 = 1;
3741 }
3742 ;
3743
3744
3745
3746 c_align:
3747 ALIGN8
3748 {
3749 $$.r0 = 0;
3750 }
3751 | ALIGN16
3752 {
3753 $$.r0 = 1;
3754 }
3755 | ALIGN24
3756 {
3757 $$.r0 = 2;
3758 }
3759 ;
3760
3761 w32_or_nothing:
3762 {
3763 $$.r0 = 0;
3764 }
3765 | LPAREN MMOD RPAREN
3766 {
3767 if ($2 == M_W32)
3768 $$.r0 = 1;
3769 else
3770 return yyerror ("Only (W32) allowed");
3771 }
3772 ;
3773
3774 iu_or_nothing:
3775 {
3776 $$.r0 = 1;
3777 }
3778 | LPAREN MMOD RPAREN
3779 {
3780 if ($2 == M_IU)
3781 $$.r0 = 3;
3782 else
3783 return yyerror ("(IU) expected");
3784 }
3785 ;
3786
3787 reg_with_predec: LBRACK _MINUS_MINUS REG RBRACK
3788 {
3789 $$ = $3;
3790 }
3791 ;
3792
3793 reg_with_postinc: LBRACK REG _PLUS_PLUS RBRACK
3794 {
3795 $$ = $2;
3796 }
3797 ;
3798
3799 /* Operators. */
3800
3801 min_max:
3802 MIN
3803 {
3804 $$.r0 = 1;
3805 }
3806 | MAX
3807 {
3808 $$.r0 = 0;
3809 }
3810 ;
3811
3812 op_bar_op:
3813 _PLUS_BAR_PLUS
3814 {
3815 $$.r0 = 0;
3816 }
3817 | _PLUS_BAR_MINUS
3818 {
3819 $$.r0 = 1;
3820 }
3821 | _MINUS_BAR_PLUS
3822 {
3823 $$.r0 = 2;
3824 }
3825 | _MINUS_BAR_MINUS
3826 {
3827 $$.r0 = 3;
3828 }
3829 ;
3830
3831 plus_minus:
3832 PLUS
3833 {
3834 $$.r0 = 0;
3835 }
3836 | MINUS
3837 {
3838 $$.r0 = 1;
3839 }
3840 ;
3841
3842 rnd_op:
3843 LPAREN RNDH RPAREN
3844 {
3845 $$.r0 = 1; /* HL. */
3846 $$.s0 = 0; /* s. */
3847 $$.x0 = 0; /* x. */
3848 $$.aop = 0; /* aop. */
3849 }
3850
3851 | LPAREN TH RPAREN
3852 {
3853 $$.r0 = 1; /* HL. */
3854 $$.s0 = 0; /* s. */
3855 $$.x0 = 0; /* x. */
3856 $$.aop = 1; /* aop. */
3857 }
3858
3859 | LPAREN RNDL RPAREN
3860 {
3861 $$.r0 = 0; /* HL. */
3862 $$.s0 = 0; /* s. */
3863 $$.x0 = 0; /* x. */
3864 $$.aop = 0; /* aop. */
3865 }
3866
3867 | LPAREN TL RPAREN
3868 {
3869 $$.r0 = 0; /* HL. */
3870 $$.s0 = 0; /* s. */
3871 $$.x0 = 0; /* x. */
3872 $$.aop = 1;
3873 }
3874
3875 | LPAREN RNDH COMMA R RPAREN
3876 {
3877 $$.r0 = 1; /* HL. */
3878 $$.s0 = 1; /* s. */
3879 $$.x0 = 0; /* x. */
3880 $$.aop = 0; /* aop. */
3881 }
3882 | LPAREN TH COMMA R RPAREN
3883 {
3884 $$.r0 = 1; /* HL. */
3885 $$.s0 = 1; /* s. */
3886 $$.x0 = 0; /* x. */
3887 $$.aop = 1; /* aop. */
3888 }
3889 | LPAREN RNDL COMMA R RPAREN
3890 {
3891 $$.r0 = 0; /* HL. */
3892 $$.s0 = 1; /* s. */
3893 $$.x0 = 0; /* x. */
3894 $$.aop = 0; /* aop. */
3895 }
3896
3897 | LPAREN TL COMMA R RPAREN
3898 {
3899 $$.r0 = 0; /* HL. */
3900 $$.s0 = 1; /* s. */
3901 $$.x0 = 0; /* x. */
3902 $$.aop = 1; /* aop. */
3903 }
3904 ;
3905
3906 b3_op:
3907 LPAREN LO RPAREN
3908 {
3909 $$.s0 = 0; /* s. */
3910 $$.x0 = 0; /* HL. */
3911 }
3912 | LPAREN HI RPAREN
3913 {
3914 $$.s0 = 0; /* s. */
3915 $$.x0 = 1; /* HL. */
3916 }
3917 | LPAREN LO COMMA R RPAREN
3918 {
3919 $$.s0 = 1; /* s. */
3920 $$.x0 = 0; /* HL. */
3921 }
3922 | LPAREN HI COMMA R RPAREN
3923 {
3924 $$.s0 = 1; /* s. */
3925 $$.x0 = 1; /* HL. */
3926 }
3927 ;
3928
3929 post_op:
3930 {
3931 $$.x0 = 2;
3932 }
3933 | _PLUS_PLUS
3934 {
3935 $$.x0 = 0;
3936 }
3937 | _MINUS_MINUS
3938 {
3939 $$.x0 = 1;
3940 }
3941 ;
3942
3943 /* Assignments, Macfuncs. */
3944
3945 a_assign:
3946 REG_A ASSIGN
3947 {
3948 $$ = $1;
3949 }
3950 ;
3951
3952 a_minusassign:
3953 REG_A _MINUS_ASSIGN
3954 {
3955 $$ = $1;
3956 }
3957 ;
3958
3959 a_plusassign:
3960 REG_A _PLUS_ASSIGN
3961 {
3962 $$ = $1;
3963 }
3964 ;
3965
3966 assign_macfunc:
3967 REG ASSIGN REG_A
3968 {
3969 $$.w = 1;
3970 $$.P = 1;
3971 $$.n = IS_A1 ($3);
3972 $$.op = 3;
3973 $$.dst = $1;
3974 $$.s0.regno = 0;
3975 $$.s1.regno = 0;
3976
3977 if (IS_A1 ($3) && IS_EVEN ($1))
3978 return yyerror ("Cannot move A1 to even register");
3979 else if (!IS_A1 ($3) && !IS_EVEN ($1))
3980 return yyerror ("Cannot move A0 to odd register");
3981 }
3982 | a_macfunc
3983 {
3984 $$ = $1;
3985 $$.w = 0; $$.P = 0;
3986 $$.dst.regno = 0;
3987 }
3988 | REG ASSIGN LPAREN a_macfunc RPAREN
3989 {
3990 $$ = $4;
3991 $$.w = 1;
3992 $$.P = 1;
3993 $$.dst = $1;
3994 }
3995
3996 | HALF_REG ASSIGN LPAREN a_macfunc RPAREN
3997 {
3998 $$ = $4;
3999 $$.w = 1;
4000 $$.P = 0;
4001 $$.dst = $1;
4002 }
4003
4004 | HALF_REG ASSIGN REG_A
4005 {
4006 $$.w = 1;
4007 $$.P = 0;
4008 $$.n = IS_A1 ($3);
4009 $$.op = 3;
4010 $$.dst = $1;
4011 $$.s0.regno = 0;
4012 $$.s1.regno = 0;
4013
4014 if (IS_A1 ($3) && !IS_H ($1))
4015 return yyerror ("Cannot move A1 to low half of register");
4016 else if (!IS_A1 ($3) && IS_H ($1))
4017 return yyerror ("Cannot move A0 to high half of register");
4018 }
4019 ;
4020
4021 a_macfunc:
4022 a_assign multiply_halfregs
4023 {
4024 $$.n = IS_A1 ($1);
4025 $$.op = 0;
4026 $$.s0 = $2.s0;
4027 $$.s1 = $2.s1;
4028 }
4029 | a_plusassign multiply_halfregs
4030 {
4031 $$.n = IS_A1 ($1);
4032 $$.op = 1;
4033 $$.s0 = $2.s0;
4034 $$.s1 = $2.s1;
4035 }
4036 | a_minusassign multiply_halfregs
4037 {
4038 $$.n = IS_A1 ($1);
4039 $$.op = 2;
4040 $$.s0 = $2.s0;
4041 $$.s1 = $2.s1;
4042 }
4043 ;
4044
4045 multiply_halfregs:
4046 HALF_REG STAR HALF_REG
4047 {
4048 if (IS_DREG ($1) && IS_DREG ($3))
4049 {
4050 $$.s0 = $1;
4051 $$.s1 = $3;
4052 }
4053 else
4054 return yyerror ("Dregs expected");
4055 }
4056 ;
4057
4058 cc_op:
4059 ASSIGN
4060 {
4061 $$.r0 = 0;
4062 }
4063 | _BAR_ASSIGN
4064 {
4065 $$.r0 = 1;
4066 }
4067 | _AMPERSAND_ASSIGN
4068 {
4069 $$.r0 = 2;
4070 }
4071 | _CARET_ASSIGN
4072 {
4073 $$.r0 = 3;
4074 }
4075 ;
4076
4077 ccstat:
4078 CCREG cc_op STATUS_REG
4079 {
4080 $$.r0 = $3.regno;
4081 $$.x0 = $2.r0;
4082 $$.s0 = 0;
4083 }
4084 | CCREG cc_op V
4085 {
4086 $$.r0 = 0x18;
4087 $$.x0 = $2.r0;
4088 $$.s0 = 0;
4089 }
4090 | STATUS_REG cc_op CCREG
4091 {
4092 $$.r0 = $1.regno;
4093 $$.x0 = $2.r0;
4094 $$.s0 = 1;
4095 }
4096 | V cc_op CCREG
4097 {
4098 $$.r0 = 0x18;
4099 $$.x0 = $2.r0;
4100 $$.s0 = 1;
4101 }
4102 ;
4103
4104 /* Expressions and Symbols. */
4105
4106 symbol: SYMBOL
4107 {
4108 Expr_Node_Value val;
4109 val.s_value = S_GET_NAME($1);
4110 $$ = Expr_Node_Create (Expr_Node_Reloc, val, NULL, NULL);
4111 }
4112 ;
4113
4114 got: symbol AT GOT
4115 {
4116 $$ = $1;
4117 }
4118 ;
4119
4120 got_or_expr: got
4121 {
4122 $$ = $1;
4123 }
4124 | expr
4125 {
4126 $$ = $1;
4127 }
4128 ;
4129
4130 pltpc :
4131 symbol AT PLTPC
4132 {
4133 $$ = $1;
4134 }
4135 ;
4136
4137 eterm: NUMBER
4138 {
4139 Expr_Node_Value val;
4140 val.i_value = $1;
4141 $$ = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
4142 }
4143 | symbol
4144 {
4145 $$ = $1;
4146 }
4147 | LPAREN expr_1 RPAREN
4148 {
4149 $$ = $2;
4150 }
4151 | TILDA expr_1
4152 {
4153 $$ = unary (Expr_Op_Type_COMP, $2);
4154 }
4155 | MINUS expr_1 %prec TILDA
4156 {
4157 $$ = unary (Expr_Op_Type_NEG, $2);
4158 }
4159 ;
4160
4161 expr: expr_1
4162 {
4163 $$ = $1;
4164 }
4165 ;
4166
4167 expr_1: expr_1 STAR expr_1
4168 {
4169 $$ = binary (Expr_Op_Type_Mult, $1, $3);
4170 }
4171 | expr_1 SLASH expr_1
4172 {
4173 $$ = binary (Expr_Op_Type_Div, $1, $3);
4174 }
4175 | expr_1 PERCENT expr_1
4176 {
4177 $$ = binary (Expr_Op_Type_Mod, $1, $3);
4178 }
4179 | expr_1 PLUS expr_1
4180 {
4181 $$ = binary (Expr_Op_Type_Add, $1, $3);
4182 }
4183 | expr_1 MINUS expr_1
4184 {
4185 $$ = binary (Expr_Op_Type_Sub, $1, $3);
4186 }
4187 | expr_1 LESS_LESS expr_1
4188 {
4189 $$ = binary (Expr_Op_Type_Lshift, $1, $3);
4190 }
4191 | expr_1 GREATER_GREATER expr_1
4192 {
4193 $$ = binary (Expr_Op_Type_Rshift, $1, $3);
4194 }
4195 | expr_1 AMPERSAND expr_1
4196 {
4197 $$ = binary (Expr_Op_Type_BAND, $1, $3);
4198 }
4199 | expr_1 CARET expr_1
4200 {
4201 $$ = binary (Expr_Op_Type_LOR, $1, $3);
4202 }
4203 | expr_1 BAR expr_1
4204 {
4205 $$ = binary (Expr_Op_Type_BOR, $1, $3);
4206 }
4207 | eterm
4208 {
4209 $$ = $1;
4210 }
4211 ;
4212
4213
4214 %%
4215
4216 EXPR_T
4217 mkexpr (int x, SYMBOL_T s)
4218 {
4219 EXPR_T e = (EXPR_T) ALLOCATE (sizeof (struct expression_cell));
4220 e->value = x;
4221 EXPR_SYMBOL(e) = s;
4222 return e;
4223 }
4224
4225 static int
4226 value_match (Expr_Node *expr, int sz, int sign, int mul, int issigned)
4227 {
4228 long umax = (1L << sz) - 1;
4229 long min = -1L << (sz - 1);
4230 long max = (1L << (sz - 1)) - 1;
4231
4232 long v = EXPR_VALUE (expr);
4233
4234 if ((v % mul) != 0)
4235 {
4236 error ("%s:%d: Value Error -- Must align to %d\n", __FILE__, __LINE__, mul);
4237 return 0;
4238 }
4239
4240 v /= mul;
4241
4242 if (sign)
4243 v = -v;
4244
4245 if (issigned)
4246 {
4247 if (v >= min && v <= max) return 1;
4248
4249 #ifdef DEBUG
4250 fprintf(stderr, "signed value %lx out of range\n", v * mul);
4251 #endif
4252 return 0;
4253 }
4254 if (v <= umax && v >= 0)
4255 return 1;
4256 #ifdef DEBUG
4257 fprintf(stderr, "unsigned value %lx out of range\n", v * mul);
4258 #endif
4259 return 0;
4260 }
4261
4262 /* Return the expression structure that allows symbol operations.
4263 If the left and right children are constants, do the operation. */
4264 static Expr_Node *
4265 binary (Expr_Op_Type op, Expr_Node *x, Expr_Node *y)
4266 {
4267 if (x->type == Expr_Node_Constant && y->type == Expr_Node_Constant)
4268 {
4269 switch (op)
4270 {
4271 case Expr_Op_Type_Add:
4272 x->value.i_value += y->value.i_value;
4273 break;
4274 case Expr_Op_Type_Sub:
4275 x->value.i_value -= y->value.i_value;
4276 break;
4277 case Expr_Op_Type_Mult:
4278 x->value.i_value *= y->value.i_value;
4279 break;
4280 case Expr_Op_Type_Div:
4281 if (y->value.i_value == 0)
4282 error ("Illegal Expression: Division by zero.");
4283 else
4284 x->value.i_value /= y->value.i_value;
4285 break;
4286 case Expr_Op_Type_Mod:
4287 x->value.i_value %= y->value.i_value;
4288 break;
4289 case Expr_Op_Type_Lshift:
4290 x->value.i_value <<= y->value.i_value;
4291 break;
4292 case Expr_Op_Type_Rshift:
4293 x->value.i_value >>= y->value.i_value;
4294 break;
4295 case Expr_Op_Type_BAND:
4296 x->value.i_value &= y->value.i_value;
4297 break;
4298 case Expr_Op_Type_BOR:
4299 x->value.i_value |= y->value.i_value;
4300 break;
4301 case Expr_Op_Type_BXOR:
4302 x->value.i_value ^= y->value.i_value;
4303 break;
4304 case Expr_Op_Type_LAND:
4305 x->value.i_value = x->value.i_value && y->value.i_value;
4306 break;
4307 case Expr_Op_Type_LOR:
4308 x->value.i_value = x->value.i_value || y->value.i_value;
4309 break;
4310
4311 default:
4312 error ("%s:%d: Internal compiler error\n", __FILE__, __LINE__);
4313 }
4314 return x;
4315 }
4316 else
4317 {
4318 /* Create a new expression structure. */
4319 Expr_Node_Value val;
4320 val.op_value = op;
4321 return Expr_Node_Create (Expr_Node_Binop, val, x, y);
4322 }
4323 }
4324
4325 static Expr_Node *
4326 unary (Expr_Op_Type op, Expr_Node *x)
4327 {
4328 if (x->type == Expr_Node_Constant)
4329 {
4330 switch (op)
4331 {
4332 case Expr_Op_Type_NEG:
4333 x->value.i_value = -x->value.i_value;
4334 break;
4335 case Expr_Op_Type_COMP:
4336 x->value.i_value = ~x->value.i_value;
4337 break;
4338 default:
4339 error ("%s:%d: Internal compiler error\n", __FILE__, __LINE__);
4340 }
4341 return x;
4342 }
4343 else
4344 {
4345 /* Create a new expression structure. */
4346 Expr_Node_Value val;
4347 val.op_value = op;
4348 return Expr_Node_Create (Expr_Node_Unop, val, x, NULL);
4349 }
4350 }
4351
4352 int debug_codeselection = 0;
4353 static void
4354 notethat (char *format, ...)
4355 {
4356 va_list ap;
4357 va_start (ap, format);
4358 if (debug_codeselection)
4359 {
4360 vfprintf (errorf, format, ap);
4361 }
4362 va_end (ap);
4363 }
4364
4365 #ifdef TEST
4366 main (int argc, char **argv)
4367 {
4368 yyparse();
4369 }
4370 #endif
4371
git-cvsimport of binutils cvsroot