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[binutils.git] / gas / config / tc-m68k.c
blobb7fb25c1fd42bcb235168bbe451d6ffec06cd4fa
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
21
22 #include "as.h"
23 #include "safe-ctype.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
31
32 #if defined (OBJ_ELF)
33 #include "elf/m68k.h"
34 #endif
35
36 #ifdef M68KCOFF
37 #include "obj-coff.h"
38 #endif
39
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars = "|#";
46 #else
47 const char *m68k_comment_chars = "|";
48 #endif
49
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars[] = "#*";
58
59 const char line_separator_chars[] = ";";
60
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS[] = "eE";
63
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
66
67 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
68
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
72
73 /* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
75 references. Not implemented. For ELF there are other means
76 to denote pic relocations. */
77 int flag_want_pic;
78
79 static int flag_short_refs; /* -l option. */
80 static int flag_long_jumps; /* -S option. */
81 static int flag_keep_pcrel; /* --pcrel option. */
82
83 #ifdef REGISTER_PREFIX_OPTIONAL
84 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
85 #else
86 int flag_reg_prefix_optional;
87 #endif
88
89 /* Whether --register-prefix-optional was used on the command line. */
90 static int reg_prefix_optional_seen;
91
92 /* The floating point coprocessor to use by default. */
93 static enum m68k_register m68k_float_copnum = COP1;
94
95 /* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97 static int m68k_abspcadd;
98
99 /* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101 static int m68k_quick = 1;
102
103 /* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
105 be 32 bits. */
106 static int m68k_rel32 = 1;
107
108 /* This is non-zero if m68k_rel32 was set from the command line. */
109 static int m68k_rel32_from_cmdline;
110
111 /* The default width to use for an index register when using a base
112 displacement. */
113 static enum m68k_size m68k_index_width_default = SIZE_LONG;
114
115 /* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
117 label. */
118 struct label_line
119 {
120 struct label_line *next;
121 symbolS *label;
122 char *file;
123 unsigned int line;
124 int text;
125 };
126
127 /* The list of labels. */
128
129 static struct label_line *labels;
130
131 /* The current label. */
132
133 static struct label_line *current_label;
134
135 /* Pointer to list holding the opcodes sorted by name. */
136 static struct m68k_opcode const ** m68k_sorted_opcodes;
137
138 /* Its an arbitrary name: This means I don't approve of it.
139 See flames below. */
140 static struct obstack robyn;
141
142 struct m68k_incant
143 {
144 const char *m_operands;
145 unsigned long m_opcode;
146 short m_opnum;
147 short m_codenum;
148 int m_arch;
149 struct m68k_incant *m_next;
150 };
151
152 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153 #define gettwo(x) (((x)->m_opcode)&0xffff)
154
155 static const enum m68k_register m68000_control_regs[] = { 0 };
156 static const enum m68k_register m68010_control_regs[] = {
157 SFC, DFC, USP, VBR,
158 0
159 };
160 static const enum m68k_register m68020_control_regs[] = {
161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
162 0
163 };
164 static const enum m68k_register m68040_control_regs[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
167 0
168 };
169 static const enum m68k_register m68060_control_regs[] = {
170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
172 0
173 };
174 static const enum m68k_register mcf_control_regs[] = {
175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
176 RAMBAR0, RAMBAR1, MBAR,
177 0
178 };
179 static const enum m68k_register mcf5208_control_regs[] = {
180 CACR, ACR0, ACR1, VBR, RAMBAR1,
181 0
182 };
183 static const enum m68k_register mcf5213_control_regs[] = {
184 VBR, RAMBAR, FLASHBAR,
185 0
186 };
187 static const enum m68k_register mcf5329_control_regs[] = {
188 CACR, ACR0, ACR1, VBR, RAMBAR,
189 0
190 };
191 static const enum m68k_register mcf5249_control_regs[] = {
192 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR1, MBAR, MBAR2,
193 0
194 };
195 static const enum m68k_register mcf528x_control_regs[] = {
196 CACR, ACR0, ACR1, VBR, FLASHBAR, RAMBAR,
197 0
198 };
199 static const enum m68k_register mcfv4e_control_regs[] = {
200 CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, VBR, PC, ROMBAR,
201 ROMBAR1, RAMBAR0, RAMBAR1, MPCR, EDRAMBAR, SECMBAR, MBAR, MBAR0, MBAR1,
202 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
203 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
204 0
205 };
206 #define cpu32_control_regs m68010_control_regs
207
208 static const enum m68k_register *control_regs;
209
210 /* Internal form of a 68020 instruction. */
211 struct m68k_it
212 {
213 const char *error;
214 const char *args; /* List of opcode info. */
215 int numargs;
216
217 int numo; /* Number of shorts in opcode. */
218 short opcode[11];
219
220 struct m68k_op operands[6];
221
222 int nexp; /* Number of exprs in use. */
223 struct m68k_exp exprs[4];
224
225 int nfrag; /* Number of frags we have to produce. */
226 struct
227 {
228 int fragoff; /* Where in the current opcode the frag ends. */
229 symbolS *fadd;
230 offsetT foff;
231 int fragty;
232 }
233 fragb[4];
234
235 int nrel; /* Num of reloc strucs in use. */
236 struct
237 {
238 int n;
239 expressionS exp;
240 char wid;
241 char pcrel;
242 /* In a pc relative address the difference between the address
243 of the offset and the address that the offset is relative
244 to. This depends on the addressing mode. Basically this
245 is the value to put in the offset field to address the
246 first byte of the offset, without regarding the special
247 significance of some values (in the branch instruction, for
248 example). */
249 int pcrel_fix;
250 #ifdef OBJ_ELF
251 /* Whether this expression needs special pic relocation, and if
252 so, which. */
253 enum pic_relocation pic_reloc;
254 #endif
255 }
256 reloc[5]; /* Five is enough??? */
257 };
258
259 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a))
260 #define float_of_arch(x) ((x) & mfloat)
261 #define mmu_of_arch(x) ((x) & mmmu)
262 #define arch_coldfire_p(x) ((x) & mcfisa_a)
263 #define arch_coldfire_fpu(x) ((x) & cfloat)
264
265 /* Macros for determining if cpu supports a specific addressing mode. */
266 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b))
267
268 static struct m68k_it the_ins; /* The instruction being assembled. */
269
270 #define op(ex) ((ex)->exp.X_op)
271 #define adds(ex) ((ex)->exp.X_add_symbol)
272 #define subs(ex) ((ex)->exp.X_op_symbol)
273 #define offs(ex) ((ex)->exp.X_add_number)
274
275 /* Macros for adding things to the m68k_it struct. */
276 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
277
278 /* Like addword, but goes BEFORE general operands. */
279
280 static void
281 insop (int w, const struct m68k_incant *opcode)
282 {
283 int z;
284 for (z = the_ins.numo; z > opcode->m_codenum; --z)
285 the_ins.opcode[z] = the_ins.opcode[z - 1];
286 for (z = 0; z < the_ins.nrel; z++)
287 the_ins.reloc[z].n += 2;
288 for (z = 0; z < the_ins.nfrag; z++)
289 the_ins.fragb[z].fragoff++;
290 the_ins.opcode[opcode->m_codenum] = w;
291 the_ins.numo++;
292 }
293
294 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
295 Blecch. */
296 static void
297 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
298 {
299 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
300 ? the_ins.numo * 2 - 1
301 : (width == 'b'
302 ? the_ins.numo * 2 + 1
303 : the_ins.numo * 2));
304 the_ins.reloc[the_ins.nrel].exp = exp->exp;
305 the_ins.reloc[the_ins.nrel].wid = width;
306 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
307 #ifdef OBJ_ELF
308 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
309 #endif
310 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
311 }
312
313 /* Cause an extra frag to be generated here, inserting up to 10 bytes
314 (that value is chosen in the frag_var call in md_assemble). TYPE
315 is the subtype of the frag to be generated; its primary type is
316 rs_machine_dependent.
317
318 The TYPE parameter is also used by md_convert_frag_1 and
319 md_estimate_size_before_relax. The appropriate type of fixup will
320 be emitted by md_convert_frag_1.
321
322 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
323 static void
324 add_frag (symbolS *add, offsetT off, int type)
325 {
326 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
327 the_ins.fragb[the_ins.nfrag].fadd = add;
328 the_ins.fragb[the_ins.nfrag].foff = off;
329 the_ins.fragb[the_ins.nfrag++].fragty = type;
330 }
331
332 #define isvar(ex) \
333 (op (ex) != O_constant && op (ex) != O_big)
334
335 static char *crack_operand (char *str, struct m68k_op *opP);
336 static int get_num (struct m68k_exp *exp, int ok);
337 static int reverse_16_bits (int in);
338 static int reverse_8_bits (int in);
339 static void install_gen_operand (int mode, int val);
340 static void install_operand (int mode, int val);
341 static void s_bss (int);
342 static void s_data1 (int);
343 static void s_data2 (int);
344 static void s_even (int);
345 static void s_proc (int);
346 static void s_chip (int);
347 static void s_fopt (int);
348 static void s_opt (int);
349 static void s_reg (int);
350 static void s_restore (int);
351 static void s_save (int);
352 static void s_mri_if (int);
353 static void s_mri_else (int);
354 static void s_mri_endi (int);
355 static void s_mri_break (int);
356 static void s_mri_next (int);
357 static void s_mri_for (int);
358 static void s_mri_endf (int);
359 static void s_mri_repeat (int);
360 static void s_mri_until (int);
361 static void s_mri_while (int);
362 static void s_mri_endw (int);
363 static void s_m68k_cpu (int);
364 static void s_m68k_arch (int);
365
366 struct m68k_cpu
367 {
368 unsigned long arch; /* Architecture features. */
369 unsigned long chip; /* Specific chip */
370 const char *name; /* Name */
371 unsigned alias;
372 };
373
374 /* We hold flags for features explicitly enabled and explicitly
375 disabled. */
376 static int current_architecture;
377 static int not_current_architecture;
378 static int current_chip;
379 static const struct m68k_cpu *selected_arch;
380 static const struct m68k_cpu *selected_cpu;
381 static int initialized;
382
383 /* Architecture models. */
384 static const struct m68k_cpu m68k_archs[] =
385 {
386 {m68000, cpu_m68000, "68000", 0},
387 {m68010, cpu_m68010, "68010", 0},
388 {m68020|m68881|m68851, cpu_m68020, "68020", 0},
389 {m68030|m68881|m68851, cpu_m68030, "68030", 0},
390 {m68040, cpu_m68040, "68040", 0},
391 {m68060, cpu_m68060, "68060", 0},
392 {cpu32|m68881, cpu_cpu32, "cpu32", 0},
393 {mcfisa_a|mcfhwdiv, 0, "isaa", 0},
394 {mcfisa_a|mcfhwdiv|mcfisa_aa, 0, "isaaplus", 0},
395 {mcfisa_a|mcfhwdiv|mcfisa_b, 0, "isab", 0},
396 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
397 cpu_cf547x, "cfv4e", 0},
398 {0,0,NULL, 0}
399 };
400
401 /* Architecture extensions. */
402 static const struct m68k_cpu m68k_extensions[] =
403 {
404 {m68851, 0, "68851", 0},
405 {m68881, 0, "68881", 0},
406 {m68881, 0, "68882", 0},
407
408 {mcfhwdiv, 0, "div", 1},
409 {mcfusp, 0, "usp", 1},
410 {cfloat, 0, "float", 1},
411 {mcfmac, 0, "mac", 1},
412 {mcfemac, 0, "emac", 1},
413
414 {0,0,NULL, 0}
415 };
416
417 /* Processor list */
418 static const struct m68k_cpu m68k_cpus[] =
419 {
420 { m68000, cpu_m68000, "68000", 0},
421 { m68010, cpu_m68010, "68010", 0},
422 { m68020|m68881|m68851, cpu_m68020, "68020", 0},
423 { m68030|m68881|m68851, cpu_m68030, "68030", 0},
424 { m68040, cpu_m68040, "68040", 0},
425 { m68060, cpu_m68060, "68060", 0},
426 { cpu32|m68881, cpu_cpu32, "cpu32", 0},
427 { mcfisa_a, cpu_cf5200, "5200", 0},
428 { mcfisa_a|mcfhwdiv|mcfmac, cpu_cf5206e, "5206e", 0},
429 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac, cpu_cf5208, "5208", 0},
430 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac, cpu_cf5213, "5213", 0},
431 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,cpu_cf521x, "521x", 0},
432 { mcfisa_a|mcfhwdiv|mcfemac, cpu_cf5249, "5249", 0},
433 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,cpu_cf528x, "528x", 0},
434 { mcfisa_a|mcfhwdiv|mcfmac, cpu_cf5307, "5307", 0},
435 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, cpu_cf5329, "5329", 0},
436 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac, cpu_cf5407, "5407",0},
437 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
438 cpu_cf547x, "547x", 0},
439 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
440 cpu_cf548x, "548x", 0},
441 /* Aliases (effectively, so far as gas is concerned) for the above
442 cpus. */
443 { m68020|m68881|m68851, cpu_m68020, "68k", 1},
444 { m68000, cpu_m68000, "68008", 1},
445 { m68000, cpu_m68000, "68302", 1},
446 { m68000, cpu_m68000, "68306", 1},
447 { m68000, cpu_m68000, "68307", 1},
448 { m68000, cpu_m68000, "68322", 1},
449 { m68000, cpu_m68000, "68356", 1},
450 { m68000, cpu_m68000, "68ec000", 1},
451 { m68000, cpu_m68000, "68hc000", 1},
452 { m68000, cpu_m68000, "68hc001", 1},
453 { m68020|m68881|m68851, cpu_m68020, "68ec020", 1},
454 { m68030|m68881|m68851, cpu_m68030, "68ec030", 1},
455 { m68040, cpu_m68040, "68ec040", 1},
456 { m68060, cpu_m68060, "68ec060", 1},
457 { cpu32|m68881, cpu_cpu32, "68330", 1},
458 { cpu32|m68881, cpu_cpu32, "68331", 1},
459 { cpu32|m68881, cpu_cpu32, "68332", 1},
460 { cpu32|m68881, cpu_cpu32, "68333", 1},
461 { cpu32|m68881, cpu_cpu32, "68334", 1},
462 { cpu32|m68881, cpu_cpu32, "68336", 1},
463 { cpu32|m68881, cpu_cpu32, "68340", 1},
464 { cpu32|m68881, cpu_cpu32, "68341", 1},
465 { cpu32|m68881, cpu_cpu32, "68349", 1},
466 { cpu32|m68881, cpu_cpu32, "68360", 1},
467 { mcfisa_a, cpu_cf5200, "5202", 1},
468 { mcfisa_a, cpu_cf5200, "5204", 1},
469 { mcfisa_a, cpu_cf5200, "5206", 1},
470 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac, cpu_cf5208, "5207", 1},
471 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac, cpu_cf5213, "5211", 1},
472 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac, cpu_cf5213, "5212", 1},
473 { mcfisa_a|mcfhwdiv|mcfisa_aa|mcfemac, cpu_cf521x, "5214", 1},
474 { mcfisa_a|mcfhwdiv|mcfisa_aa|mcfemac, cpu_cf521x, "5216", 1},
475 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, cpu_cf5329, "5327", 1},
476 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, cpu_cf5329, "5328", 1},
477 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, cpu_cf528x, "5280", 1},
478 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, cpu_cf528x, "5281", 1},
479 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, cpu_cf528x, "5282", 1},
480 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac, cpu_cf5407, "cfv4", 1 },
481 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
482 cpu_cf547x, "cfv4e", 1 },
483 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
484 cpu_cf547x, "5470", 1 },
485 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
486 cpu_cf547x, "5471", 1 },
487 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
488 cpu_cf547x, "5472", 1 },
489 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
490 cpu_cf547x, "5473", 1 },
491 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
492 cpu_cf547x, "5474", 1 },
493 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
494 cpu_cf547x, "5475", 1 },
495 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
496 cpu_cf548x, "5480", 1 },
497 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
498 cpu_cf548x, "5481", 1 },
499 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
500 cpu_cf548x, "5482", 1 },
501 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
502 cpu_cf548x, "5483", 1 },
503 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
504 cpu_cf548x, "5484", 1 },
505 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat,
506 cpu_cf548x, "5485", 1 },
507 {0,0,NULL, 0}
508 };
509
510 #define CPU_ALLOW_MC 1
511 #define CPU_ALLOW_NEGATION 4
512
513 static const struct m68k_cpu *m68k_lookup_cpu
514 (const char *, const struct m68k_cpu *, int, int *);
515 static int m68k_set_arch (const char *, int, int);
516 static int m68k_set_cpu (const char *, int, int);
517 static int m68k_set_extension (const char *, int, int);
518 static void m68k_init_arch (void);
519
520 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
521 architecture and we have a lot of relaxation modes. */
522
523 /* Macros used in the relaxation code. */
524 #define TAB(x,y) (((x) << 2) + (y))
525 #define TABTYPE(x) ((x) >> 2)
526
527 /* Relaxation states. */
528 #define BYTE 0
529 #define SHORT 1
530 #define LONG 2
531 #define SZ_UNDEF 3
532
533 /* Here are all the relaxation modes we support. First we can relax ordinary
534 branches. On 68020 and higher and on CPU32 all branch instructions take
535 three forms, so on these CPUs all branches always remain as such. When we
536 have to expand to the LONG form on a 68000, though, we substitute an
537 absolute jump instead. This is a direct replacement for unconditional
538 branches and a branch over a jump for conditional branches. However, if the
539 user requires PIC and disables this with --pcrel, we can only relax between
540 BYTE and SHORT forms, punting if that isn't enough. This gives us four
541 different relaxation modes for branches: */
542
543 #define BRANCHBWL 0 /* Branch byte, word, or long. */
544 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
545 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
546 #define BRANCHBW 3 /* Branch byte or word. */
547
548 /* We also relax coprocessor branches and DBcc's. All CPUs that support
549 coprocessor branches support them in word and long forms, so we have only
550 one relaxation mode for them. DBcc's are word only on all CPUs. We can
551 relax them to the LONG form with a branch-around sequence. This sequence
552 can use a long branch (if available) or an absolute jump (if acceptable).
553 This gives us two relaxation modes. If long branches are not available and
554 absolute jumps are not acceptable, we don't relax DBcc's. */
555
556 #define FBRANCH 4 /* Coprocessor branch. */
557 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
558 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
559
560 /* That's all for instruction relaxation. However, we also relax PC-relative
561 operands. Specifically, we have three operand relaxation modes. On the
562 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
563 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
564 two. Also PC+displacement+index operands in their simple form (with a non-
565 suppressed index without memory indirection) are supported on all CPUs, but
566 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
567 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
568 form of the PC+displacement+index operand. Finally, some absolute operands
569 can be relaxed down to 16-bit PC-relative. */
570
571 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
572 #define PCINDEX 8 /* PC + displacement + index. */
573 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
574
575 /* Note that calls to frag_var need to specify the maximum expansion
576 needed; this is currently 10 bytes for DBCC. */
577
578 /* The fields are:
579 How far Forward this mode will reach:
580 How far Backward this mode will reach:
581 How many bytes this mode will add to the size of the frag
582 Which mode to go to if the offset won't fit in this one
583
584 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
585 relax_typeS md_relax_table[] =
586 {
587 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
588 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
589 { 0, 0, 4, 0 },
590 { 1, 1, 0, 0 },
591
592 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
593 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
594 { 0, 0, 4, 0 },
595 { 1, 1, 0, 0 },
596
597 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
598 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
599 { 0, 0, 6, 0 },
600 { 1, 1, 0, 0 },
601
602 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
603 { 0, 0, 2, 0 },
604 { 1, 1, 0, 0 },
605 { 1, 1, 0, 0 },
606
607 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
608 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
609 { 0, 0, 4, 0 },
610 { 1, 1, 0, 0 },
611
612 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
613 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
614 { 0, 0, 10, 0 },
615 { 1, 1, 0, 0 },
616
617 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
618 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
619 { 0, 0, 10, 0 },
620 { 1, 1, 0, 0 },
621
622 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
623 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
624 { 0, 0, 6, 0 },
625 { 1, 1, 0, 0 },
626
627 { 125, -130, 0, TAB (PCINDEX, SHORT) },
628 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
629 { 0, 0, 4, 0 },
630 { 1, 1, 0, 0 },
631
632 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
633 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
634 { 0, 0, 4, 0 },
635 { 1, 1, 0, 0 },
636 };
637
638 /* These are the machine dependent pseudo-ops. These are included so
639 the assembler can work on the output from the SUN C compiler, which
640 generates these. */
641
642 /* This table describes all the machine specific pseudo-ops the assembler
643 has to support. The fields are:
644 pseudo-op name without dot
645 function to call to execute this pseudo-op
646 Integer arg to pass to the function. */
647 const pseudo_typeS md_pseudo_table[] =
648 {
649 {"data1", s_data1, 0},
650 {"data2", s_data2, 0},
651 {"bss", s_bss, 0},
652 {"even", s_even, 0},
653 {"skip", s_space, 0},
654 {"proc", s_proc, 0},
655 #if defined (TE_SUN3) || defined (OBJ_ELF)
656 {"align", s_align_bytes, 0},
657 #endif
658 #ifdef OBJ_ELF
659 {"swbeg", s_ignore, 0},
660 #endif
661 {"extend", float_cons, 'x'},
662 {"ldouble", float_cons, 'x'},
663
664 {"arch", s_m68k_arch, 0},
665 {"cpu", s_m68k_cpu, 0},
666
667 /* The following pseudo-ops are supported for MRI compatibility. */
668 {"chip", s_chip, 0},
669 {"comline", s_space, 1},
670 {"fopt", s_fopt, 0},
671 {"mask2", s_ignore, 0},
672 {"opt", s_opt, 0},
673 {"reg", s_reg, 0},
674 {"restore", s_restore, 0},
675 {"save", s_save, 0},
676
677 {"if", s_mri_if, 0},
678 {"if.b", s_mri_if, 'b'},
679 {"if.w", s_mri_if, 'w'},
680 {"if.l", s_mri_if, 'l'},
681 {"else", s_mri_else, 0},
682 {"else.s", s_mri_else, 's'},
683 {"else.l", s_mri_else, 'l'},
684 {"endi", s_mri_endi, 0},
685 {"break", s_mri_break, 0},
686 {"break.s", s_mri_break, 's'},
687 {"break.l", s_mri_break, 'l'},
688 {"next", s_mri_next, 0},
689 {"next.s", s_mri_next, 's'},
690 {"next.l", s_mri_next, 'l'},
691 {"for", s_mri_for, 0},
692 {"for.b", s_mri_for, 'b'},
693 {"for.w", s_mri_for, 'w'},
694 {"for.l", s_mri_for, 'l'},
695 {"endf", s_mri_endf, 0},
696 {"repeat", s_mri_repeat, 0},
697 {"until", s_mri_until, 0},
698 {"until.b", s_mri_until, 'b'},
699 {"until.w", s_mri_until, 'w'},
700 {"until.l", s_mri_until, 'l'},
701 {"while", s_mri_while, 0},
702 {"while.b", s_mri_while, 'b'},
703 {"while.w", s_mri_while, 'w'},
704 {"while.l", s_mri_while, 'l'},
705 {"endw", s_mri_endw, 0},
706
707 {0, 0, 0}
708 };
709
710 /* The mote pseudo ops are put into the opcode table, since they
711 don't start with a . they look like opcodes to gas. */
712
713 const pseudo_typeS mote_pseudo_table[] =
714 {
715
716 {"dcl", cons, 4},
717 {"dc", cons, 2},
718 {"dcw", cons, 2},
719 {"dcb", cons, 1},
720
721 {"dsl", s_space, 4},
722 {"ds", s_space, 2},
723 {"dsw", s_space, 2},
724 {"dsb", s_space, 1},
725
726 {"xdef", s_globl, 0},
727 #ifdef OBJ_ELF
728 {"align", s_align_bytes, 0},
729 #else
730 {"align", s_align_ptwo, 0},
731 #endif
732 #ifdef M68KCOFF
733 {"sect", obj_coff_section, 0},
734 {"section", obj_coff_section, 0},
735 #endif
736 {0, 0, 0}
737 };
738
739 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
740 gives identical results to a 32-bit host. */
741 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
742 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
743
744 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
745 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
746 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
747 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
748
749 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
750 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
751 #define islong(x) (1)
752
753 static char notend_table[256];
754 static char alt_notend_table[256];
755 #define notend(s) \
756 (! (notend_table[(unsigned char) *s] \
757 || (*s == ':' \
758 && alt_notend_table[(unsigned char) s[1]])))
759
760 /* Return a human readable string holding the list of chips that are
761 valid for a particular architecture, suppressing aliases (unless
762 there is only one of them). */
763
764 static char *
765 find_cf_chip (int architecture)
766 {
767 static char buf[1024];
768 int i, j, n_chips, n_alias;
769 char *cp;
770
771 strcpy (buf, " (");
772 cp = buf + strlen (buf);
773
774 for (i = 0, n_chips = 0, n_alias = 0; m68k_cpus[i].name; ++i)
775 if (m68k_cpus[i].arch & architecture)
776 {
777 n_chips++;
778 if (m68k_cpus[i].alias)
779 n_alias++;
780 }
781
782 if (n_chips == 0)
783 as_fatal (_("no matching ColdFire architectures found"));
784
785 if (n_alias > 1)
786 n_chips -= n_alias;
787
788 for (i = 0, j = 0; m68k_cpus[i].name && j < n_chips; ++i)
789 if (m68k_cpus[i].arch & architecture)
790 {
791 if (j)
792 {
793 if ((j == n_chips - 1 && !(n_alias > 1)) || ! n_alias)
794 {
795 if (n_chips == 2)
796 {
797 strncpy (cp, _(" or "), (sizeof (buf) - (cp - buf)));
798 cp += strlen (cp);
799 }
800 else
801 {
802 strncpy (cp, _(", or "), (sizeof (buf) - (cp - buf)));
803 cp += strlen (cp);
804 }
805 }
806 else
807 {
808 strncpy (cp, ", ", (sizeof (buf) - (cp - buf)));
809 cp += strlen (cp);
810 }
811 }
812 strncpy (cp, m68k_cpus[i].name, (sizeof (buf) - (cp - buf)));
813 cp += strlen (cp);
814 j++;
815 }
816
817 if (n_alias > 1)
818 {
819 strncpy (cp, _(", or aliases"), (sizeof (buf) - (cp - buf)));
820 cp += strlen (cp);
821 }
822
823 strncpy (cp, ")", (sizeof (buf) - (cp - buf)));
824
825 return buf;
826 }
827
828 #ifdef OBJ_ELF
829
830 /* Return zero if the reference to SYMBOL from within the same segment may
831 be relaxed. */
832
833 /* On an ELF system, we can't relax an externally visible symbol,
834 because it may be overridden by a shared library. However, if
835 TARGET_OS is "elf", then we presume that we are assembling for an
836 embedded system, in which case we don't have to worry about shared
837 libraries, and we can relax any external sym. */
838
839 #define relaxable_symbol(symbol) \
840 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
841 || S_IS_WEAK (symbol)))
842
843 /* Compute the relocation code for a fixup of SIZE bytes, using pc
844 relative relocation if PCREL is non-zero. PIC says whether a special
845 pic relocation was requested. */
846
847 static bfd_reloc_code_real_type
848 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
849 {
850 switch (pic)
851 {
852 case pic_got_pcrel:
853 switch (size)
854 {
855 case 1:
856 return BFD_RELOC_8_GOT_PCREL;
857 case 2:
858 return BFD_RELOC_16_GOT_PCREL;
859 case 4:
860 return BFD_RELOC_32_GOT_PCREL;
861 }
862 break;
863
864 case pic_got_off:
865 switch (size)
866 {
867 case 1:
868 return BFD_RELOC_8_GOTOFF;
869 case 2:
870 return BFD_RELOC_16_GOTOFF;
871 case 4:
872 return BFD_RELOC_32_GOTOFF;
873 }
874 break;
875
876 case pic_plt_pcrel:
877 switch (size)
878 {
879 case 1:
880 return BFD_RELOC_8_PLT_PCREL;
881 case 2:
882 return BFD_RELOC_16_PLT_PCREL;
883 case 4:
884 return BFD_RELOC_32_PLT_PCREL;
885 }
886 break;
887
888 case pic_plt_off:
889 switch (size)
890 {
891 case 1:
892 return BFD_RELOC_8_PLTOFF;
893 case 2:
894 return BFD_RELOC_16_PLTOFF;
895 case 4:
896 return BFD_RELOC_32_PLTOFF;
897 }
898 break;
899
900 case pic_none:
901 if (pcrel)
902 {
903 switch (size)
904 {
905 case 1:
906 return BFD_RELOC_8_PCREL;
907 case 2:
908 return BFD_RELOC_16_PCREL;
909 case 4:
910 return BFD_RELOC_32_PCREL;
911 }
912 }
913 else
914 {
915 switch (size)
916 {
917 case 1:
918 return BFD_RELOC_8;
919 case 2:
920 return BFD_RELOC_16;
921 case 4:
922 return BFD_RELOC_32;
923 }
924 }
925 }
926
927 if (pcrel)
928 {
929 if (pic == pic_none)
930 as_bad (_("Can not do %d byte pc-relative relocation"), size);
931 else
932 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
933 }
934 else
935 {
936 if (pic == pic_none)
937 as_bad (_("Can not do %d byte relocation"), size);
938 else
939 as_bad (_("Can not do %d byte pic relocation"), size);
940 }
941
942 return BFD_RELOC_NONE;
943 }
944
945 /* Here we decide which fixups can be adjusted to make them relative
946 to the beginning of the section instead of the symbol. Basically
947 we need to make sure that the dynamic relocations are done
948 correctly, so in some cases we force the original symbol to be
949 used. */
950 int
951 tc_m68k_fix_adjustable (fixS *fixP)
952 {
953 /* Adjust_reloc_syms doesn't know about the GOT. */
954 switch (fixP->fx_r_type)
955 {
956 case BFD_RELOC_8_GOT_PCREL:
957 case BFD_RELOC_16_GOT_PCREL:
958 case BFD_RELOC_32_GOT_PCREL:
959 case BFD_RELOC_8_GOTOFF:
960 case BFD_RELOC_16_GOTOFF:
961 case BFD_RELOC_32_GOTOFF:
962 case BFD_RELOC_8_PLT_PCREL:
963 case BFD_RELOC_16_PLT_PCREL:
964 case BFD_RELOC_32_PLT_PCREL:
965 case BFD_RELOC_8_PLTOFF:
966 case BFD_RELOC_16_PLTOFF:
967 case BFD_RELOC_32_PLTOFF:
968 return 0;
969
970 case BFD_RELOC_VTABLE_INHERIT:
971 case BFD_RELOC_VTABLE_ENTRY:
972 return 0;
973
974 default:
975 return 1;
976 }
977 }
978
979 #else /* !OBJ_ELF */
980
981 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
982
983 #define relaxable_symbol(symbol) 1
984
985 #endif /* OBJ_ELF */
986
987 arelent *
988 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
989 {
990 arelent *reloc;
991 bfd_reloc_code_real_type code;
992
993 /* If the tcbit is set, then this was a fixup of a negative value
994 that was never resolved. We do not have a reloc to handle this,
995 so just return. We assume that other code will have detected this
996 situation and produced a helpful error message, so we just tell the
997 user that the reloc cannot be produced. */
998 if (fixp->fx_tcbit)
999 {
1000 if (fixp->fx_addsy)
1001 as_bad_where (fixp->fx_file, fixp->fx_line,
1002 _("Unable to produce reloc against symbol '%s'"),
1003 S_GET_NAME (fixp->fx_addsy));
1004 return NULL;
1005 }
1006
1007 if (fixp->fx_r_type != BFD_RELOC_NONE)
1008 {
1009 code = fixp->fx_r_type;
1010
1011 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1012 that fixup_segment converted a non-PC relative reloc into a
1013 PC relative reloc. In such a case, we need to convert the
1014 reloc code. */
1015 if (fixp->fx_pcrel)
1016 {
1017 switch (code)
1018 {
1019 case BFD_RELOC_8:
1020 code = BFD_RELOC_8_PCREL;
1021 break;
1022 case BFD_RELOC_16:
1023 code = BFD_RELOC_16_PCREL;
1024 break;
1025 case BFD_RELOC_32:
1026 code = BFD_RELOC_32_PCREL;
1027 break;
1028 case BFD_RELOC_8_PCREL:
1029 case BFD_RELOC_16_PCREL:
1030 case BFD_RELOC_32_PCREL:
1031 case BFD_RELOC_8_GOT_PCREL:
1032 case BFD_RELOC_16_GOT_PCREL:
1033 case BFD_RELOC_32_GOT_PCREL:
1034 case BFD_RELOC_8_GOTOFF:
1035 case BFD_RELOC_16_GOTOFF:
1036 case BFD_RELOC_32_GOTOFF:
1037 case BFD_RELOC_8_PLT_PCREL:
1038 case BFD_RELOC_16_PLT_PCREL:
1039 case BFD_RELOC_32_PLT_PCREL:
1040 case BFD_RELOC_8_PLTOFF:
1041 case BFD_RELOC_16_PLTOFF:
1042 case BFD_RELOC_32_PLTOFF:
1043 break;
1044 default:
1045 as_bad_where (fixp->fx_file, fixp->fx_line,
1046 _("Cannot make %s relocation PC relative"),
1047 bfd_get_reloc_code_name (code));
1048 }
1049 }
1050 }
1051 else
1052 {
1053 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1054 switch (F (fixp->fx_size, fixp->fx_pcrel))
1055 {
1056 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1057 MAP (1, 0, BFD_RELOC_8);
1058 MAP (2, 0, BFD_RELOC_16);
1059 MAP (4, 0, BFD_RELOC_32);
1060 MAP (1, 1, BFD_RELOC_8_PCREL);
1061 MAP (2, 1, BFD_RELOC_16_PCREL);
1062 MAP (4, 1, BFD_RELOC_32_PCREL);
1063 default:
1064 abort ();
1065 }
1066 }
1067 #undef F
1068 #undef MAP
1069
1070 reloc = (arelent *) xmalloc (sizeof (arelent));
1071 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1072 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1073 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1074 #ifndef OBJ_ELF
1075 if (fixp->fx_pcrel)
1076 reloc->addend = fixp->fx_addnumber;
1077 else
1078 reloc->addend = 0;
1079 #else
1080 if (!fixp->fx_pcrel)
1081 reloc->addend = fixp->fx_addnumber;
1082 else
1083 reloc->addend = (section->vma
1084 /* Explicit sign extension in case char is
1085 unsigned. */
1086 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1087 + fixp->fx_addnumber
1088 + md_pcrel_from (fixp));
1089 #endif
1090
1091 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1092 assert (reloc->howto != 0);
1093
1094 return reloc;
1095 }
1096
1097 /* Handle of the OPCODE hash table. NULL means any use before
1098 m68k_ip_begin() will crash. */
1099 static struct hash_control *op_hash;
1100 \f
1101 /* Assemble an m68k instruction. */
1102
1103 static void
1104 m68k_ip (char *instring)
1105 {
1106 register char *p;
1107 register struct m68k_op *opP;
1108 register const struct m68k_incant *opcode;
1109 register const char *s;
1110 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1111 char *pdot, *pdotmove;
1112 enum m68k_size siz1, siz2;
1113 char c;
1114 int losing;
1115 int opsfound;
1116 struct m68k_op operands_backup[6];
1117 LITTLENUM_TYPE words[6];
1118 LITTLENUM_TYPE *wordp;
1119 unsigned long ok_arch = 0;
1120
1121 if (*instring == ' ')
1122 instring++; /* Skip leading whitespace. */
1123
1124 /* Scan up to end of operation-code, which MUST end in end-of-string
1125 or exactly 1 space. */
1126 pdot = 0;
1127 for (p = instring; *p != '\0'; p++)
1128 {
1129 if (*p == ' ')
1130 break;
1131 if (*p == '.')
1132 pdot = p;
1133 }
1134
1135 if (p == instring)
1136 {
1137 the_ins.error = _("No operator");
1138 return;
1139 }
1140
1141 /* p now points to the end of the opcode name, probably whitespace.
1142 Make sure the name is null terminated by clobbering the
1143 whitespace, look it up in the hash table, then fix it back.
1144 Remove a dot, first, since the opcode tables have none. */
1145 if (pdot != NULL)
1146 {
1147 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1148 *pdotmove = pdotmove[1];
1149 p--;
1150 }
1151
1152 c = *p;
1153 *p = '\0';
1154 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1155 *p = c;
1156
1157 if (pdot != NULL)
1158 {
1159 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1160 *pdotmove = pdotmove[-1];
1161 *pdot = '.';
1162 ++p;
1163 }
1164
1165 if (opcode == NULL)
1166 {
1167 the_ins.error = _("Unknown operator");
1168 return;
1169 }
1170
1171 /* Found a legitimate opcode, start matching operands. */
1172 while (*p == ' ')
1173 ++p;
1174
1175 if (opcode->m_operands == 0)
1176 {
1177 char *old = input_line_pointer;
1178 *old = '\n';
1179 input_line_pointer = p;
1180 /* Ahh - it's a motorola style psuedo op. */
1181 mote_pseudo_table[opcode->m_opnum].poc_handler
1182 (mote_pseudo_table[opcode->m_opnum].poc_val);
1183 input_line_pointer = old;
1184 *old = 0;
1185
1186 return;
1187 }
1188
1189 if (flag_mri && opcode->m_opnum == 0)
1190 {
1191 /* In MRI mode, random garbage is allowed after an instruction
1192 which accepts no operands. */
1193 the_ins.args = opcode->m_operands;
1194 the_ins.numargs = opcode->m_opnum;
1195 the_ins.numo = opcode->m_codenum;
1196 the_ins.opcode[0] = getone (opcode);
1197 the_ins.opcode[1] = gettwo (opcode);
1198 return;
1199 }
1200
1201 for (opP = &the_ins.operands[0]; *p; opP++)
1202 {
1203 p = crack_operand (p, opP);
1204
1205 if (opP->error)
1206 {
1207 the_ins.error = opP->error;
1208 return;
1209 }
1210 }
1211
1212 opsfound = opP - &the_ins.operands[0];
1213
1214 /* This ugly hack is to support the floating pt opcodes in their
1215 standard form. Essentially, we fake a first enty of type COP#1 */
1216 if (opcode->m_operands[0] == 'I')
1217 {
1218 int n;
1219
1220 for (n = opsfound; n > 0; --n)
1221 the_ins.operands[n] = the_ins.operands[n - 1];
1222
1223 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1224 the_ins.operands[0].mode = CONTROL;
1225 the_ins.operands[0].reg = m68k_float_copnum;
1226 opsfound++;
1227 }
1228
1229 /* We've got the operands. Find an opcode that'll accept them. */
1230 for (losing = 0;;)
1231 {
1232 /* If we didn't get the right number of ops, or we have no
1233 common model with this pattern then reject this pattern. */
1234
1235 ok_arch |= opcode->m_arch;
1236 if (opsfound != opcode->m_opnum
1237 || ((opcode->m_arch & current_architecture) == 0))
1238 ++losing;
1239 else
1240 {
1241 int i;
1242
1243 /* Make a copy of the operands of this insn so that
1244 we can modify them safely, should we want to. */
1245 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1246 for (i = 0; i < opsfound; i++)
1247 operands_backup[i] = the_ins.operands[i];
1248
1249 for (s = opcode->m_operands, opP = &operands_backup[0];
1250 *s && !losing;
1251 s += 2, opP++)
1252 {
1253 /* Warning: this switch is huge! */
1254 /* I've tried to organize the cases into this order:
1255 non-alpha first, then alpha by letter. Lower-case
1256 goes directly before uppercase counterpart. */
1257 /* Code with multiple case ...: gets sorted by the lowest
1258 case ... it belongs to. I hope this makes sense. */
1259 switch (*s)
1260 {
1261 case '!':
1262 switch (opP->mode)
1263 {
1264 case IMMED:
1265 case DREG:
1266 case AREG:
1267 case FPREG:
1268 case CONTROL:
1269 case AINC:
1270 case ADEC:
1271 case REGLST:
1272 losing++;
1273 break;
1274 default:
1275 break;
1276 }
1277 break;
1278
1279 case '<':
1280 switch (opP->mode)
1281 {
1282 case DREG:
1283 case AREG:
1284 case FPREG:
1285 case CONTROL:
1286 case IMMED:
1287 case ADEC:
1288 case REGLST:
1289 losing++;
1290 break;
1291 default:
1292 break;
1293 }
1294 break;
1295
1296 case '>':
1297 switch (opP->mode)
1298 {
1299 case DREG:
1300 case AREG:
1301 case FPREG:
1302 case CONTROL:
1303 case IMMED:
1304 case AINC:
1305 case REGLST:
1306 losing++;
1307 break;
1308 case ABSL:
1309 break;
1310 default:
1311 if (opP->reg == PC
1312 || opP->reg == ZPC)
1313 losing++;
1314 break;
1315 }
1316 break;
1317
1318 case 'm':
1319 switch (opP->mode)
1320 {
1321 case DREG:
1322 case AREG:
1323 case AINDR:
1324 case AINC:
1325 case ADEC:
1326 break;
1327 default:
1328 losing++;
1329 }
1330 break;
1331
1332 case 'n':
1333 switch (opP->mode)
1334 {
1335 case DISP:
1336 break;
1337 default:
1338 losing++;
1339 }
1340 break;
1341
1342 case 'o':
1343 switch (opP->mode)
1344 {
1345 case BASE:
1346 case ABSL:
1347 case IMMED:
1348 break;
1349 default:
1350 losing++;
1351 }
1352 break;
1353
1354 case 'p':
1355 switch (opP->mode)
1356 {
1357 case DREG:
1358 case AREG:
1359 case AINDR:
1360 case AINC:
1361 case ADEC:
1362 break;
1363 case DISP:
1364 if (opP->reg == PC || opP->reg == ZPC)
1365 losing++;
1366 break;
1367 default:
1368 losing++;
1369 }
1370 break;
1371
1372 case 'q':
1373 switch (opP->mode)
1374 {
1375 case DREG:
1376 case AINDR:
1377 case AINC:
1378 case ADEC:
1379 break;
1380 case DISP:
1381 if (opP->reg == PC || opP->reg == ZPC)
1382 losing++;
1383 break;
1384 default:
1385 losing++;
1386 break;
1387 }
1388 break;
1389
1390 case 'v':
1391 switch (opP->mode)
1392 {
1393 case DREG:
1394 case AINDR:
1395 case AINC:
1396 case ADEC:
1397 case ABSL:
1398 break;
1399 case DISP:
1400 if (opP->reg == PC || opP->reg == ZPC)
1401 losing++;
1402 break;
1403 default:
1404 losing++;
1405 break;
1406 }
1407 break;
1408
1409 case '#':
1410 if (opP->mode != IMMED)
1411 losing++;
1412 else if (s[1] == 'b'
1413 && ! isvar (&opP->disp)
1414 && (opP->disp.exp.X_op != O_constant
1415 || ! isbyte (opP->disp.exp.X_add_number)))
1416 losing++;
1417 else if (s[1] == 'B'
1418 && ! isvar (&opP->disp)
1419 && (opP->disp.exp.X_op != O_constant
1420 || ! issbyte (opP->disp.exp.X_add_number)))
1421 losing++;
1422 else if (s[1] == 'w'
1423 && ! isvar (&opP->disp)
1424 && (opP->disp.exp.X_op != O_constant
1425 || ! isword (opP->disp.exp.X_add_number)))
1426 losing++;
1427 else if (s[1] == 'W'
1428 && ! isvar (&opP->disp)
1429 && (opP->disp.exp.X_op != O_constant
1430 || ! issword (opP->disp.exp.X_add_number)))
1431 losing++;
1432 break;
1433
1434 case '^':
1435 case 'T':
1436 if (opP->mode != IMMED)
1437 losing++;
1438 break;
1439
1440 case '$':
1441 if (opP->mode == AREG
1442 || opP->mode == CONTROL
1443 || opP->mode == FPREG
1444 || opP->mode == IMMED
1445 || opP->mode == REGLST
1446 || (opP->mode != ABSL
1447 && (opP->reg == PC
1448 || opP->reg == ZPC)))
1449 losing++;
1450 break;
1451
1452 case '%':
1453 if (opP->mode == CONTROL
1454 || opP->mode == FPREG
1455 || opP->mode == REGLST
1456 || opP->mode == IMMED
1457 || (opP->mode != ABSL
1458 && (opP->reg == PC
1459 || opP->reg == ZPC)))
1460 losing++;
1461 break;
1462
1463 case '&':
1464 switch (opP->mode)
1465 {
1466 case DREG:
1467 case AREG:
1468 case FPREG:
1469 case CONTROL:
1470 case IMMED:
1471 case AINC:
1472 case ADEC:
1473 case REGLST:
1474 losing++;
1475 break;
1476 case ABSL:
1477 break;
1478 default:
1479 if (opP->reg == PC
1480 || opP->reg == ZPC)
1481 losing++;
1482 break;
1483 }
1484 break;
1485
1486 case '*':
1487 if (opP->mode == CONTROL
1488 || opP->mode == FPREG
1489 || opP->mode == REGLST)
1490 losing++;
1491 break;
1492
1493 case '+':
1494 if (opP->mode != AINC)
1495 losing++;
1496 break;
1497
1498 case '-':
1499 if (opP->mode != ADEC)
1500 losing++;
1501 break;
1502
1503 case '/':
1504 switch (opP->mode)
1505 {
1506 case AREG:
1507 case CONTROL:
1508 case FPREG:
1509 case AINC:
1510 case ADEC:
1511 case IMMED:
1512 case REGLST:
1513 losing++;
1514 break;
1515 default:
1516 break;
1517 }
1518 break;
1519
1520 case ';':
1521 switch (opP->mode)
1522 {
1523 case AREG:
1524 case CONTROL:
1525 case FPREG:
1526 case REGLST:
1527 losing++;
1528 break;
1529 default:
1530 break;
1531 }
1532 break;
1533
1534 case '?':
1535 switch (opP->mode)
1536 {
1537 case AREG:
1538 case CONTROL:
1539 case FPREG:
1540 case AINC:
1541 case ADEC:
1542 case IMMED:
1543 case REGLST:
1544 losing++;
1545 break;
1546 case ABSL:
1547 break;
1548 default:
1549 if (opP->reg == PC || opP->reg == ZPC)
1550 losing++;
1551 break;
1552 }
1553 break;
1554
1555 case '@':
1556 switch (opP->mode)
1557 {
1558 case AREG:
1559 case CONTROL:
1560 case FPREG:
1561 case IMMED:
1562 case REGLST:
1563 losing++;
1564 break;
1565 default:
1566 break;
1567 }
1568 break;
1569
1570 case '~': /* For now! (JF FOO is this right?) */
1571 switch (opP->mode)
1572 {
1573 case DREG:
1574 case AREG:
1575 case CONTROL:
1576 case FPREG:
1577 case IMMED:
1578 case REGLST:
1579 losing++;
1580 break;
1581 case ABSL:
1582 break;
1583 default:
1584 if (opP->reg == PC
1585 || opP->reg == ZPC)
1586 losing++;
1587 break;
1588 }
1589 break;
1590
1591 case '3':
1592 if (opP->mode != CONTROL
1593 || (opP->reg != TT0 && opP->reg != TT1))
1594 losing++;
1595 break;
1596
1597 case 'A':
1598 if (opP->mode != AREG)
1599 losing++;
1600 break;
1601
1602 case 'a':
1603 if (opP->mode != AINDR)
1604 ++losing;
1605 break;
1606
1607 case '4':
1608 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1609 && (opP->mode != DISP
1610 || opP->reg < ADDR0
1611 || opP->reg > ADDR7))
1612 ++losing;
1613 break;
1614
1615 case 'B': /* FOO */
1616 if (opP->mode != ABSL
1617 || (flag_long_jumps
1618 && strncmp (instring, "jbsr", 4) == 0))
1619 losing++;
1620 break;
1621
1622 case 'b':
1623 switch (opP->mode)
1624 {
1625 case IMMED:
1626 case ABSL:
1627 case AREG:
1628 case FPREG:
1629 case CONTROL:
1630 case POST:
1631 case PRE:
1632 case REGLST:
1633 losing++;
1634 break;
1635 default:
1636 break;
1637 }
1638 break;
1639
1640 case 'C':
1641 if (opP->mode != CONTROL || opP->reg != CCR)
1642 losing++;
1643 break;
1644
1645 case 'd':
1646 if (opP->mode != DISP
1647 || opP->reg < ADDR0
1648 || opP->reg > ADDR7)
1649 losing++;
1650 break;
1651
1652 case 'D':
1653 if (opP->mode != DREG)
1654 losing++;
1655 break;
1656
1657 case 'E':
1658 if (opP->reg != ACC)
1659 losing++;
1660 break;
1661
1662 case 'e':
1663 if (opP->reg != ACC && opP->reg != ACC1
1664 && opP->reg != ACC2 && opP->reg != ACC3)
1665 losing++;
1666 break;
1667
1668 case 'F':
1669 if (opP->mode != FPREG)
1670 losing++;
1671 break;
1672
1673 case 'G':
1674 if (opP->reg != MACSR)
1675 losing++;
1676 break;
1677
1678 case 'g':
1679 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1680 losing++;
1681 break;
1682
1683 case 'H':
1684 if (opP->reg != MASK)
1685 losing++;
1686 break;
1687
1688 case 'I':
1689 if (opP->mode != CONTROL
1690 || opP->reg < COP0
1691 || opP->reg > COP7)
1692 losing++;
1693 break;
1694
1695 case 'i':
1696 if (opP->mode != LSH && opP->mode != RSH)
1697 losing++;
1698 break;
1699
1700 case 'J':
1701 if (opP->mode != CONTROL
1702 || opP->reg < USP
1703 || opP->reg > last_movec_reg)
1704 losing++;
1705 else
1706 {
1707 const enum m68k_register *rp;
1708 for (rp = control_regs; *rp; rp++)
1709 if (*rp == opP->reg)
1710 break;
1711 if (*rp == 0)
1712 losing++;
1713 }
1714 break;
1715
1716 case 'k':
1717 if (opP->mode != IMMED)
1718 losing++;
1719 break;
1720
1721 case 'l':
1722 case 'L':
1723 if (opP->mode == DREG
1724 || opP->mode == AREG
1725 || opP->mode == FPREG)
1726 {
1727 if (s[1] == '8')
1728 losing++;
1729 else
1730 {
1731 switch (opP->mode)
1732 {
1733 case DREG:
1734 opP->mask = 1 << (opP->reg - DATA0);
1735 break;
1736 case AREG:
1737 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1738 break;
1739 case FPREG:
1740 opP->mask = 1 << (opP->reg - FP0 + 16);
1741 break;
1742 default:
1743 abort ();
1744 }
1745 opP->mode = REGLST;
1746 }
1747 }
1748 else if (opP->mode == CONTROL)
1749 {
1750 if (s[1] != '8')
1751 losing++;
1752 else
1753 {
1754 switch (opP->reg)
1755 {
1756 case FPI:
1757 opP->mask = 1 << 24;
1758 break;
1759 case FPS:
1760 opP->mask = 1 << 25;
1761 break;
1762 case FPC:
1763 opP->mask = 1 << 26;
1764 break;
1765 default:
1766 losing++;
1767 break;
1768 }
1769 opP->mode = REGLST;
1770 }
1771 }
1772 else if (opP->mode != REGLST)
1773 losing++;
1774 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1775 losing++;
1776 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1777 losing++;
1778 break;
1779
1780 case 'M':
1781 if (opP->mode != IMMED)
1782 losing++;
1783 else if (opP->disp.exp.X_op != O_constant
1784 || ! issbyte (opP->disp.exp.X_add_number))
1785 losing++;
1786 else if (! m68k_quick
1787 && instring[3] != 'q'
1788 && instring[4] != 'q')
1789 losing++;
1790 break;
1791
1792 case 'O':
1793 if (opP->mode != DREG
1794 && opP->mode != IMMED
1795 && opP->mode != ABSL)
1796 losing++;
1797 break;
1798
1799 case 'Q':
1800 if (opP->mode != IMMED)
1801 losing++;
1802 else if (opP->disp.exp.X_op != O_constant
1803 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1804 losing++;
1805 else if (! m68k_quick
1806 && (strncmp (instring, "add", 3) == 0
1807 || strncmp (instring, "sub", 3) == 0)
1808 && instring[3] != 'q')
1809 losing++;
1810 break;
1811
1812 case 'R':
1813 if (opP->mode != DREG && opP->mode != AREG)
1814 losing++;
1815 break;
1816
1817 case 'r':
1818 if (opP->mode != AINDR
1819 && (opP->mode != BASE
1820 || (opP->reg != 0
1821 && opP->reg != ZADDR0)
1822 || opP->disp.exp.X_op != O_absent
1823 || ((opP->index.reg < DATA0
1824 || opP->index.reg > DATA7)
1825 && (opP->index.reg < ADDR0
1826 || opP->index.reg > ADDR7))
1827 || opP->index.size != SIZE_UNSPEC
1828 || opP->index.scale != 1))
1829 losing++;
1830 break;
1831
1832 case 's':
1833 if (opP->mode != CONTROL
1834 || ! (opP->reg == FPI
1835 || opP->reg == FPS
1836 || opP->reg == FPC))
1837 losing++;
1838 break;
1839
1840 case 'S':
1841 if (opP->mode != CONTROL || opP->reg != SR)
1842 losing++;
1843 break;
1844
1845 case 't':
1846 if (opP->mode != IMMED)
1847 losing++;
1848 else if (opP->disp.exp.X_op != O_constant
1849 || TRUNC (opP->disp.exp.X_add_number) > 7)
1850 losing++;
1851 break;
1852
1853 case 'U':
1854 if (opP->mode != CONTROL || opP->reg != USP)
1855 losing++;
1856 break;
1857
1858 case 'x':
1859 if (opP->mode != IMMED)
1860 losing++;
1861 else if (opP->disp.exp.X_op != O_constant
1862 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1863 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
1864 losing++;
1865 break;
1866
1867 /* JF these are out of order. We could put them
1868 in order if we were willing to put up with
1869 bunches of #ifdef m68851s in the code.
1870
1871 Don't forget that you need these operands
1872 to use 68030 MMU instructions. */
1873 #ifndef NO_68851
1874 /* Memory addressing mode used by pflushr. */
1875 case '|':
1876 if (opP->mode == CONTROL
1877 || opP->mode == FPREG
1878 || opP->mode == DREG
1879 || opP->mode == AREG
1880 || opP->mode == REGLST)
1881 losing++;
1882 /* We should accept immediate operands, but they
1883 supposedly have to be quad word, and we don't
1884 handle that. I would like to see what a Motorola
1885 assembler does before doing something here. */
1886 if (opP->mode == IMMED)
1887 losing++;
1888 break;
1889
1890 case 'f':
1891 if (opP->mode != CONTROL
1892 || (opP->reg != SFC && opP->reg != DFC))
1893 losing++;
1894 break;
1895
1896 case '0':
1897 if (opP->mode != CONTROL || opP->reg != TC)
1898 losing++;
1899 break;
1900
1901 case '1':
1902 if (opP->mode != CONTROL || opP->reg != AC)
1903 losing++;
1904 break;
1905
1906 case '2':
1907 if (opP->mode != CONTROL
1908 || (opP->reg != CAL
1909 && opP->reg != VAL
1910 && opP->reg != SCC))
1911 losing++;
1912 break;
1913
1914 case 'V':
1915 if (opP->mode != CONTROL
1916 || opP->reg != VAL)
1917 losing++;
1918 break;
1919
1920 case 'W':
1921 if (opP->mode != CONTROL
1922 || (opP->reg != DRP
1923 && opP->reg != SRP
1924 && opP->reg != CRP))
1925 losing++;
1926 break;
1927
1928 case 'w':
1929 switch (opP->mode)
1930 {
1931 case IMMED:
1932 case ABSL:
1933 case AREG:
1934 case DREG:
1935 case FPREG:
1936 case CONTROL:
1937 case POST:
1938 case PRE:
1939 case REGLST:
1940 losing++;
1941 break;
1942 default:
1943 break;
1944 }
1945 break;
1946
1947 case 'X':
1948 if (opP->mode != CONTROL
1949 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1950 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1951 losing++;
1952 break;
1953
1954 case 'Y':
1955 if (opP->mode != CONTROL || opP->reg != PSR)
1956 losing++;
1957 break;
1958
1959 case 'Z':
1960 if (opP->mode != CONTROL || opP->reg != PCSR)
1961 losing++;
1962 break;
1963 #endif
1964 case 'c':
1965 if (opP->mode != CONTROL
1966 || (opP->reg != NC
1967 && opP->reg != IC
1968 && opP->reg != DC
1969 && opP->reg != BC))
1970 losing++;
1971 break;
1972
1973 case '_':
1974 if (opP->mode != ABSL)
1975 ++losing;
1976 break;
1977
1978 case 'u':
1979 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1980 losing++;
1981 /* FIXME: kludge instead of fixing parser:
1982 upper/lower registers are *not* CONTROL
1983 registers, but ordinary ones. */
1984 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1985 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1986 opP->mode = DREG;
1987 else
1988 opP->mode = AREG;
1989 break;
1990
1991 case 'y':
1992 if (!(opP->mode == AINDR
1993 || (opP->mode == DISP
1994 && !(opP->reg == PC || opP->reg == ZPC))))
1995 losing++;
1996 break;
1997
1998 case 'z':
1999 if (!(opP->mode == AINDR || opP->mode == DISP))
2000 losing++;
2001 break;
2002
2003 default:
2004 abort ();
2005 }
2006
2007 if (losing)
2008 break;
2009 }
2010
2011 /* Since we have found the correct instruction, copy
2012 in the modifications that we may have made. */
2013 if (!losing)
2014 for (i = 0; i < opsfound; i++)
2015 the_ins.operands[i] = operands_backup[i];
2016 }
2017
2018 if (!losing)
2019 break;
2020
2021 opcode = opcode->m_next;
2022
2023 if (!opcode)
2024 {
2025 if (ok_arch
2026 && !(ok_arch & current_architecture))
2027 {
2028 char buf[200], *cp;
2029
2030 strncpy (buf,
2031 _("invalid instruction for this architecture; needs "),
2032 sizeof (buf));
2033 cp = buf + strlen (buf);
2034 switch (ok_arch)
2035 {
2036 case mcfisa_a:
2037 strncpy (cp, _("ColdFire ISA_A"),
2038 sizeof (buf) - (cp - buf));
2039 cp += strlen (cp);
2040 strncpy (cp, find_cf_chip (ok_arch),
2041 sizeof (buf) - (cp - buf));
2042 cp += strlen (cp);
2043 break;
2044 case mcfhwdiv:
2045 strncpy (cp, _("ColdFire hardware divide"),
2046 sizeof (buf) - (cp - buf));
2047 cp += strlen (cp);
2048 strncpy (cp, find_cf_chip (ok_arch),
2049 sizeof (buf) - (cp - buf));
2050 cp += strlen (cp);
2051 break;
2052 case mcfisa_aa:
2053 strncpy (cp, _("ColdFire ISA_A+"),
2054 sizeof (buf) - (cp - buf));
2055 cp += strlen (cp);
2056 strncpy (cp, find_cf_chip (ok_arch),
2057 sizeof (buf) - (cp - buf));
2058 cp += strlen (cp);
2059 break;
2060 case mcfisa_b:
2061 strncpy (cp, _("ColdFire ISA_B"),
2062 sizeof (buf) - (cp - buf));
2063 cp += strlen (cp);
2064 strncpy (cp, find_cf_chip (ok_arch),
2065 sizeof (buf) - (cp - buf));
2066 cp += strlen (cp);
2067 break;
2068 case cfloat:
2069 strncpy (cp, _("ColdFire fpu"), sizeof (buf) - (cp - buf));
2070 cp += strlen (cp);
2071 strncpy (cp, find_cf_chip (ok_arch),
2072 sizeof (buf) - (cp - buf));
2073 cp += strlen (cp);
2074 break;
2075 case mfloat:
2076 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
2077 break;
2078 case mmmu:
2079 strcpy (cp, _("mmu (68030 or 68851)"));
2080 break;
2081 case m68020up:
2082 strcpy (cp, _("68020 or higher"));
2083 break;
2084 case m68000up:
2085 strcpy (cp, _("68000 or higher"));
2086 break;
2087 case m68010up:
2088 strcpy (cp, _("68010 or higher"));
2089 break;
2090 default:
2091 {
2092 int got_one = 0, idx;
2093
2094 for (idx = 0; m68k_cpus[idx].name; idx++)
2095 {
2096 if ((m68k_cpus[idx].arch & ok_arch)
2097 && ! m68k_cpus[idx].alias)
2098 {
2099 if (got_one)
2100 {
2101 strcpy (cp, " or ");
2102 cp += strlen (cp);
2103 }
2104 got_one = 1;
2105 strcpy (cp, m68k_cpus[idx].name);
2106 cp += strlen (cp);
2107 }
2108 }
2109 }
2110 }
2111 cp = xmalloc (strlen (buf) + 1);
2112 strcpy (cp, buf);
2113 the_ins.error = cp;
2114 }
2115 else
2116 the_ins.error = _("operands mismatch");
2117 return;
2118 }
2119
2120 losing = 0;
2121 }
2122
2123 /* Now assemble it. */
2124 the_ins.args = opcode->m_operands;
2125 the_ins.numargs = opcode->m_opnum;
2126 the_ins.numo = opcode->m_codenum;
2127 the_ins.opcode[0] = getone (opcode);
2128 the_ins.opcode[1] = gettwo (opcode);
2129
2130 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2131 {
2132 /* This switch is a doozy.
2133 Watch the first step; its a big one! */
2134 switch (s[0])
2135 {
2136
2137 case '*':
2138 case '~':
2139 case '%':
2140 case ';':
2141 case '@':
2142 case '!':
2143 case '&':
2144 case '$':
2145 case '?':
2146 case '/':
2147 case '<':
2148 case '>':
2149 case 'b':
2150 case 'm':
2151 case 'n':
2152 case 'o':
2153 case 'p':
2154 case 'q':
2155 case 'v':
2156 case 'w':
2157 case 'y':
2158 case 'z':
2159 case '4':
2160 #ifndef NO_68851
2161 case '|':
2162 #endif
2163 switch (opP->mode)
2164 {
2165 case IMMED:
2166 tmpreg = 0x3c; /* 7.4 */
2167 if (strchr ("bwl", s[1]))
2168 nextword = get_num (&opP->disp, 90);
2169 else
2170 nextword = get_num (&opP->disp, 0);
2171 if (isvar (&opP->disp))
2172 add_fix (s[1], &opP->disp, 0, 0);
2173 switch (s[1])
2174 {
2175 case 'b':
2176 if (!isbyte (nextword))
2177 opP->error = _("operand out of range");
2178 addword (nextword);
2179 baseo = 0;
2180 break;
2181 case 'w':
2182 if (!isword (nextword))
2183 opP->error = _("operand out of range");
2184 addword (nextword);
2185 baseo = 0;
2186 break;
2187 case 'W':
2188 if (!issword (nextword))
2189 opP->error = _("operand out of range");
2190 addword (nextword);
2191 baseo = 0;
2192 break;
2193 case 'l':
2194 addword (nextword >> 16);
2195 addword (nextword);
2196 baseo = 0;
2197 break;
2198
2199 case 'f':
2200 baseo = 2;
2201 outro = 8;
2202 break;
2203 case 'F':
2204 baseo = 4;
2205 outro = 11;
2206 break;
2207 case 'x':
2208 baseo = 6;
2209 outro = 15;
2210 break;
2211 case 'p':
2212 baseo = 6;
2213 outro = -1;
2214 break;
2215 default:
2216 abort ();
2217 }
2218 if (!baseo)
2219 break;
2220
2221 /* We gotta put out some float. */
2222 if (op (&opP->disp) != O_big)
2223 {
2224 valueT val;
2225 int gencnt;
2226
2227 /* Can other cases happen here? */
2228 if (op (&opP->disp) != O_constant)
2229 abort ();
2230
2231 val = (valueT) offs (&opP->disp);
2232 gencnt = 0;
2233 do
2234 {
2235 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2236 val >>= LITTLENUM_NUMBER_OF_BITS;
2237 ++gencnt;
2238 }
2239 while (val != 0);
2240 offs (&opP->disp) = gencnt;
2241 }
2242 if (offs (&opP->disp) > 0)
2243 {
2244 if (offs (&opP->disp) > baseo)
2245 {
2246 as_warn (_("Bignum too big for %c format; truncated"),
2247 s[1]);
2248 offs (&opP->disp) = baseo;
2249 }
2250 baseo -= offs (&opP->disp);
2251 while (baseo--)
2252 addword (0);
2253 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2254 offs (&opP->disp)--;
2255 --wordp)
2256 addword (*wordp);
2257 break;
2258 }
2259 gen_to_words (words, baseo, (long) outro);
2260 for (wordp = words; baseo--; wordp++)
2261 addword (*wordp);
2262 break;
2263 case DREG:
2264 tmpreg = opP->reg - DATA; /* 0.dreg */
2265 break;
2266 case AREG:
2267 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2268 break;
2269 case AINDR:
2270 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2271 break;
2272 case ADEC:
2273 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2274 break;
2275 case AINC:
2276 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2277 break;
2278 case DISP:
2279
2280 nextword = get_num (&opP->disp, 90);
2281
2282 /* Convert mode 5 addressing with a zero offset into
2283 mode 2 addressing to reduce the instruction size by a
2284 word. */
2285 if (! isvar (&opP->disp)
2286 && (nextword == 0)
2287 && (opP->disp.size == SIZE_UNSPEC)
2288 && (opP->reg >= ADDR0)
2289 && (opP->reg <= ADDR7))
2290 {
2291 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2292 break;
2293 }
2294
2295 if (opP->reg == PC
2296 && ! isvar (&opP->disp)
2297 && m68k_abspcadd)
2298 {
2299 opP->disp.exp.X_op = O_symbol;
2300 opP->disp.exp.X_add_symbol =
2301 section_symbol (absolute_section);
2302 }
2303
2304 /* Force into index mode. Hope this works. */
2305
2306 /* We do the first bit for 32-bit displacements, and the
2307 second bit for 16 bit ones. It is possible that we
2308 should make the default be WORD instead of LONG, but
2309 I think that'd break GCC, so we put up with a little
2310 inefficiency for the sake of working output. */
2311
2312 if (!issword (nextword)
2313 || (isvar (&opP->disp)
2314 && ((opP->disp.size == SIZE_UNSPEC
2315 && flag_short_refs == 0
2316 && cpu_of_arch (current_architecture) >= m68020
2317 && ! arch_coldfire_p (current_architecture))
2318 || opP->disp.size == SIZE_LONG)))
2319 {
2320 if (cpu_of_arch (current_architecture) < m68020
2321 || arch_coldfire_p (current_architecture))
2322 opP->error =
2323 _("displacement too large for this architecture; needs 68020 or higher");
2324 if (opP->reg == PC)
2325 tmpreg = 0x3B; /* 7.3 */
2326 else
2327 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2328 if (isvar (&opP->disp))
2329 {
2330 if (opP->reg == PC)
2331 {
2332 if (opP->disp.size == SIZE_LONG
2333 #ifdef OBJ_ELF
2334 /* If the displacement needs pic
2335 relocation it cannot be relaxed. */
2336 || opP->disp.pic_reloc != pic_none
2337 #endif
2338 )
2339 {
2340 addword (0x0170);
2341 add_fix ('l', &opP->disp, 1, 2);
2342 }
2343 else
2344 {
2345 add_frag (adds (&opP->disp),
2346 SEXT (offs (&opP->disp)),
2347 TAB (PCREL1632, SZ_UNDEF));
2348 break;
2349 }
2350 }
2351 else
2352 {
2353 addword (0x0170);
2354 add_fix ('l', &opP->disp, 0, 0);
2355 }
2356 }
2357 else
2358 addword (0x0170);
2359 addword (nextword >> 16);
2360 }
2361 else
2362 {
2363 if (opP->reg == PC)
2364 tmpreg = 0x3A; /* 7.2 */
2365 else
2366 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2367
2368 if (isvar (&opP->disp))
2369 {
2370 if (opP->reg == PC)
2371 {
2372 add_fix ('w', &opP->disp, 1, 0);
2373 }
2374 else
2375 add_fix ('w', &opP->disp, 0, 0);
2376 }
2377 }
2378 addword (nextword);
2379 break;
2380
2381 case POST:
2382 case PRE:
2383 case BASE:
2384 nextword = 0;
2385 baseo = get_num (&opP->disp, 90);
2386 if (opP->mode == POST || opP->mode == PRE)
2387 outro = get_num (&opP->odisp, 90);
2388 /* Figure out the `addressing mode'.
2389 Also turn on the BASE_DISABLE bit, if needed. */
2390 if (opP->reg == PC || opP->reg == ZPC)
2391 {
2392 tmpreg = 0x3b; /* 7.3 */
2393 if (opP->reg == ZPC)
2394 nextword |= 0x80;
2395 }
2396 else if (opP->reg == 0)
2397 {
2398 nextword |= 0x80;
2399 tmpreg = 0x30; /* 6.garbage */
2400 }
2401 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2402 {
2403 nextword |= 0x80;
2404 tmpreg = 0x30 + opP->reg - ZADDR0;
2405 }
2406 else
2407 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2408
2409 siz1 = opP->disp.size;
2410 if (opP->mode == POST || opP->mode == PRE)
2411 siz2 = opP->odisp.size;
2412 else
2413 siz2 = SIZE_UNSPEC;
2414
2415 /* Index register stuff. */
2416 if (opP->index.reg != 0
2417 && opP->index.reg >= DATA
2418 && opP->index.reg <= ADDR7)
2419 {
2420 nextword |= (opP->index.reg - DATA) << 12;
2421
2422 if (opP->index.size == SIZE_LONG
2423 || (opP->index.size == SIZE_UNSPEC
2424 && m68k_index_width_default == SIZE_LONG))
2425 nextword |= 0x800;
2426
2427 if ((opP->index.scale != 1
2428 && cpu_of_arch (current_architecture) < m68020)
2429 || (opP->index.scale == 8
2430 && (arch_coldfire_p (current_architecture)
2431 && !arch_coldfire_fpu (current_architecture))))
2432 {
2433 opP->error =
2434 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2435 }
2436
2437 if (arch_coldfire_p (current_architecture)
2438 && opP->index.size == SIZE_WORD)
2439 opP->error = _("invalid index size for coldfire");
2440
2441 switch (opP->index.scale)
2442 {
2443 case 1:
2444 break;
2445 case 2:
2446 nextword |= 0x200;
2447 break;
2448 case 4:
2449 nextword |= 0x400;
2450 break;
2451 case 8:
2452 nextword |= 0x600;
2453 break;
2454 default:
2455 abort ();
2456 }
2457 /* IF its simple,
2458 GET US OUT OF HERE! */
2459
2460 /* Must be INDEX, with an index register. Address
2461 register cannot be ZERO-PC, and either :b was
2462 forced, or we know it will fit. For a 68000 or
2463 68010, force this mode anyways, because the
2464 larger modes aren't supported. */
2465 if (opP->mode == BASE
2466 && ((opP->reg >= ADDR0
2467 && opP->reg <= ADDR7)
2468 || opP->reg == PC))
2469 {
2470 if (siz1 == SIZE_BYTE
2471 || cpu_of_arch (current_architecture) < m68020
2472 || arch_coldfire_p (current_architecture)
2473 || (siz1 == SIZE_UNSPEC
2474 && ! isvar (&opP->disp)
2475 && issbyte (baseo)))
2476 {
2477 nextword += baseo & 0xff;
2478 addword (nextword);
2479 if (isvar (&opP->disp))
2480 {
2481 /* Do a byte relocation. If it doesn't
2482 fit (possible on m68000) let the
2483 fixup processing complain later. */
2484 if (opP->reg == PC)
2485 add_fix ('B', &opP->disp, 1, 1);
2486 else
2487 add_fix ('B', &opP->disp, 0, 0);
2488 }
2489 else if (siz1 != SIZE_BYTE)
2490 {
2491 if (siz1 != SIZE_UNSPEC)
2492 as_warn (_("Forcing byte displacement"));
2493 if (! issbyte (baseo))
2494 opP->error = _("byte displacement out of range");
2495 }
2496
2497 break;
2498 }
2499 else if (siz1 == SIZE_UNSPEC
2500 && opP->reg == PC
2501 && isvar (&opP->disp)
2502 && subs (&opP->disp) == NULL
2503 #ifdef OBJ_ELF
2504 /* If the displacement needs pic
2505 relocation it cannot be relaxed. */
2506 && opP->disp.pic_reloc == pic_none
2507 #endif
2508 )
2509 {
2510 /* The code in md_convert_frag_1 needs to be
2511 able to adjust nextword. Call frag_grow
2512 to ensure that we have enough space in
2513 the frag obstack to make all the bytes
2514 contiguous. */
2515 frag_grow (14);
2516 nextword += baseo & 0xff;
2517 addword (nextword);
2518 add_frag (adds (&opP->disp),
2519 SEXT (offs (&opP->disp)),
2520 TAB (PCINDEX, SZ_UNDEF));
2521
2522 break;
2523 }
2524 }
2525 }
2526 else
2527 {
2528 nextword |= 0x40; /* No index reg. */
2529 if (opP->index.reg >= ZDATA0
2530 && opP->index.reg <= ZDATA7)
2531 nextword |= (opP->index.reg - ZDATA0) << 12;
2532 else if (opP->index.reg >= ZADDR0
2533 || opP->index.reg <= ZADDR7)
2534 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2535 }
2536
2537 /* It isn't simple. */
2538
2539 if (cpu_of_arch (current_architecture) < m68020
2540 || arch_coldfire_p (current_architecture))
2541 opP->error =
2542 _("invalid operand mode for this architecture; needs 68020 or higher");
2543
2544 nextword |= 0x100;
2545 /* If the guy specified a width, we assume that it is
2546 wide enough. Maybe it isn't. If so, we lose. */
2547 switch (siz1)
2548 {
2549 case SIZE_UNSPEC:
2550 if (isvar (&opP->disp)
2551 ? m68k_rel32
2552 : ! issword (baseo))
2553 {
2554 siz1 = SIZE_LONG;
2555 nextword |= 0x30;
2556 }
2557 else if (! isvar (&opP->disp) && baseo == 0)
2558 nextword |= 0x10;
2559 else
2560 {
2561 nextword |= 0x20;
2562 siz1 = SIZE_WORD;
2563 }
2564 break;
2565 case SIZE_BYTE:
2566 as_warn (_(":b not permitted; defaulting to :w"));
2567 /* Fall through. */
2568 case SIZE_WORD:
2569 nextword |= 0x20;
2570 break;
2571 case SIZE_LONG:
2572 nextword |= 0x30;
2573 break;
2574 }
2575
2576 /* Figure out inner displacement stuff. */
2577 if (opP->mode == POST || opP->mode == PRE)
2578 {
2579 if (cpu_of_arch (current_architecture) & cpu32)
2580 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2581 switch (siz2)
2582 {
2583 case SIZE_UNSPEC:
2584 if (isvar (&opP->odisp)
2585 ? m68k_rel32
2586 : ! issword (outro))
2587 {
2588 siz2 = SIZE_LONG;
2589 nextword |= 0x3;
2590 }
2591 else if (! isvar (&opP->odisp) && outro == 0)
2592 nextword |= 0x1;
2593 else
2594 {
2595 nextword |= 0x2;
2596 siz2 = SIZE_WORD;
2597 }
2598 break;
2599 case 1:
2600 as_warn (_(":b not permitted; defaulting to :w"));
2601 /* Fall through. */
2602 case 2:
2603 nextword |= 0x2;
2604 break;
2605 case 3:
2606 nextword |= 0x3;
2607 break;
2608 }
2609 if (opP->mode == POST
2610 && (nextword & 0x40) == 0)
2611 nextword |= 0x04;
2612 }
2613 addword (nextword);
2614
2615 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2616 {
2617 if (opP->reg == PC || opP->reg == ZPC)
2618 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2619 else
2620 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2621 }
2622 if (siz1 == SIZE_LONG)
2623 addword (baseo >> 16);
2624 if (siz1 != SIZE_UNSPEC)
2625 addword (baseo);
2626
2627 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2628 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2629 if (siz2 == SIZE_LONG)
2630 addword (outro >> 16);
2631 if (siz2 != SIZE_UNSPEC)
2632 addword (outro);
2633
2634 break;
2635
2636 case ABSL:
2637 nextword = get_num (&opP->disp, 90);
2638 switch (opP->disp.size)
2639 {
2640 default:
2641 abort ();
2642 case SIZE_UNSPEC:
2643 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2644 {
2645 tmpreg = 0x38; /* 7.0 */
2646 addword (nextword);
2647 break;
2648 }
2649 if (isvar (&opP->disp)
2650 && !subs (&opP->disp)
2651 && adds (&opP->disp)
2652 #ifdef OBJ_ELF
2653 /* If the displacement needs pic relocation it
2654 cannot be relaxed. */
2655 && opP->disp.pic_reloc == pic_none
2656 #endif
2657 && !flag_long_jumps
2658 && !strchr ("~%&$?", s[0]))
2659 {
2660 tmpreg = 0x3A; /* 7.2 */
2661 add_frag (adds (&opP->disp),
2662 SEXT (offs (&opP->disp)),
2663 TAB (ABSTOPCREL, SZ_UNDEF));
2664 break;
2665 }
2666 /* Fall through into long. */
2667 case SIZE_LONG:
2668 if (isvar (&opP->disp))
2669 add_fix ('l', &opP->disp, 0, 0);
2670
2671 tmpreg = 0x39;/* 7.1 mode */
2672 addword (nextword >> 16);
2673 addword (nextword);
2674 break;
2675
2676 case SIZE_BYTE:
2677 as_bad (_("unsupported byte value; use a different suffix"));
2678 /* Fall through. */
2679
2680 case SIZE_WORD:
2681 if (isvar (&opP->disp))
2682 add_fix ('w', &opP->disp, 0, 0);
2683
2684 tmpreg = 0x38;/* 7.0 mode */
2685 addword (nextword);
2686 break;
2687 }
2688 break;
2689 case CONTROL:
2690 case FPREG:
2691 default:
2692 as_bad (_("unknown/incorrect operand"));
2693 /* abort (); */
2694 }
2695
2696 /* If s[0] is '4', then this is for the mac instructions
2697 that can have a trailing_ampersand set. If so, set 0x100
2698 bit on tmpreg so install_gen_operand can check for it and
2699 set the appropriate bit (word2, bit 5). */
2700 if (s[0] == '4')
2701 {
2702 if (opP->trailing_ampersand)
2703 tmpreg |= 0x100;
2704 }
2705 install_gen_operand (s[1], tmpreg);
2706 break;
2707
2708 case '#':
2709 case '^':
2710 switch (s[1])
2711 { /* JF: I hate floating point! */
2712 case 'j':
2713 tmpreg = 70;
2714 break;
2715 case '8':
2716 tmpreg = 20;
2717 break;
2718 case 'C':
2719 tmpreg = 50;
2720 break;
2721 case '3':
2722 default:
2723 tmpreg = 90;
2724 break;
2725 }
2726 tmpreg = get_num (&opP->disp, tmpreg);
2727 if (isvar (&opP->disp))
2728 add_fix (s[1], &opP->disp, 0, 0);
2729 switch (s[1])
2730 {
2731 case 'b': /* Danger: These do no check for
2732 certain types of overflow.
2733 user beware! */
2734 if (!isbyte (tmpreg))
2735 opP->error = _("out of range");
2736 insop (tmpreg, opcode);
2737 if (isvar (&opP->disp))
2738 the_ins.reloc[the_ins.nrel - 1].n =
2739 (opcode->m_codenum) * 2 + 1;
2740 break;
2741 case 'B':
2742 if (!issbyte (tmpreg))
2743 opP->error = _("out of range");
2744 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2745 if (isvar (&opP->disp))
2746 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2747 break;
2748 case 'w':
2749 if (!isword (tmpreg))
2750 opP->error = _("out of range");
2751 insop (tmpreg, opcode);
2752 if (isvar (&opP->disp))
2753 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2754 break;
2755 case 'W':
2756 if (!issword (tmpreg))
2757 opP->error = _("out of range");
2758 insop (tmpreg, opcode);
2759 if (isvar (&opP->disp))
2760 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2761 break;
2762 case 'l':
2763 /* Because of the way insop works, we put these two out
2764 backwards. */
2765 insop (tmpreg, opcode);
2766 insop (tmpreg >> 16, opcode);
2767 if (isvar (&opP->disp))
2768 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2769 break;
2770 case '3':
2771 tmpreg &= 0xFF;
2772 case '8':
2773 case 'C':
2774 case 'j':
2775 install_operand (s[1], tmpreg);
2776 break;
2777 default:
2778 abort ();
2779 }
2780 break;
2781
2782 case '+':
2783 case '-':
2784 case 'A':
2785 case 'a':
2786 install_operand (s[1], opP->reg - ADDR);
2787 break;
2788
2789 case 'B':
2790 tmpreg = get_num (&opP->disp, 90);
2791 switch (s[1])
2792 {
2793 case 'B':
2794 add_fix ('B', &opP->disp, 1, -1);
2795 break;
2796 case 'W':
2797 add_fix ('w', &opP->disp, 1, 0);
2798 addword (0);
2799 break;
2800 case 'L':
2801 long_branch:
2802 if (! HAVE_LONG_BRANCH (current_architecture))
2803 as_warn (_("Can't use long branches on 68000/68010/5200"));
2804 the_ins.opcode[0] |= 0xff;
2805 add_fix ('l', &opP->disp, 1, 0);
2806 addword (0);
2807 addword (0);
2808 break;
2809 case 'g':
2810 if (subs (&opP->disp)) /* We can't relax it. */
2811 goto long_branch;
2812
2813 #ifdef OBJ_ELF
2814 /* If the displacement needs pic relocation it cannot be
2815 relaxed. */
2816 if (opP->disp.pic_reloc != pic_none)
2817 goto long_branch;
2818 #endif
2819 /* This could either be a symbol, or an absolute
2820 address. If it's an absolute address, turn it into
2821 an absolute jump right here and keep it out of the
2822 relaxer. */
2823 if (adds (&opP->disp) == 0)
2824 {
2825 if (the_ins.opcode[0] == 0x6000) /* jbra */
2826 the_ins.opcode[0] = 0x4EF9;
2827 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2828 the_ins.opcode[0] = 0x4EB9;
2829 else /* jCC */
2830 {
2831 the_ins.opcode[0] ^= 0x0100;
2832 the_ins.opcode[0] |= 0x0006;
2833 addword (0x4EF9);
2834 }
2835 add_fix ('l', &opP->disp, 0, 0);
2836 addword (0);
2837 addword (0);
2838 break;
2839 }
2840
2841 /* Now we know it's going into the relaxer. Now figure
2842 out which mode. We try in this order of preference:
2843 long branch, absolute jump, byte/word branches only. */
2844 if (HAVE_LONG_BRANCH (current_architecture))
2845 add_frag (adds (&opP->disp),
2846 SEXT (offs (&opP->disp)),
2847 TAB (BRANCHBWL, SZ_UNDEF));
2848 else if (! flag_keep_pcrel)
2849 {
2850 if ((the_ins.opcode[0] == 0x6000)
2851 || (the_ins.opcode[0] == 0x6100))
2852 add_frag (adds (&opP->disp),
2853 SEXT (offs (&opP->disp)),
2854 TAB (BRABSJUNC, SZ_UNDEF));
2855 else
2856 add_frag (adds (&opP->disp),
2857 SEXT (offs (&opP->disp)),
2858 TAB (BRABSJCOND, SZ_UNDEF));
2859 }
2860 else
2861 add_frag (adds (&opP->disp),
2862 SEXT (offs (&opP->disp)),
2863 TAB (BRANCHBW, SZ_UNDEF));
2864 break;
2865 case 'w':
2866 if (isvar (&opP->disp))
2867 {
2868 /* Check for DBcc instructions. We can relax them,
2869 but only if we have long branches and/or absolute
2870 jumps. */
2871 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2872 && (HAVE_LONG_BRANCH (current_architecture)
2873 || (! flag_keep_pcrel)))
2874 {
2875 if (HAVE_LONG_BRANCH (current_architecture))
2876 add_frag (adds (&opP->disp),
2877 SEXT (offs (&opP->disp)),
2878 TAB (DBCCLBR, SZ_UNDEF));
2879 else
2880 add_frag (adds (&opP->disp),
2881 SEXT (offs (&opP->disp)),
2882 TAB (DBCCABSJ, SZ_UNDEF));
2883 break;
2884 }
2885 add_fix ('w', &opP->disp, 1, 0);
2886 }
2887 addword (0);
2888 break;
2889 case 'C': /* Fixed size LONG coproc branches. */
2890 add_fix ('l', &opP->disp, 1, 0);
2891 addword (0);
2892 addword (0);
2893 break;
2894 case 'c': /* Var size Coprocesssor branches. */
2895 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
2896 {
2897 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2898 add_fix ('l', &opP->disp, 1, 0);
2899 addword (0);
2900 addword (0);
2901 }
2902 else
2903 add_frag (adds (&opP->disp),
2904 SEXT (offs (&opP->disp)),
2905 TAB (FBRANCH, SZ_UNDEF));
2906 break;
2907 default:
2908 abort ();
2909 }
2910 break;
2911
2912 case 'C': /* Ignore it. */
2913 break;
2914
2915 case 'd': /* JF this is a kludge. */
2916 install_operand ('s', opP->reg - ADDR);
2917 tmpreg = get_num (&opP->disp, 90);
2918 if (!issword (tmpreg))
2919 {
2920 as_warn (_("Expression out of range, using 0"));
2921 tmpreg = 0;
2922 }
2923 addword (tmpreg);
2924 break;
2925
2926 case 'D':
2927 install_operand (s[1], opP->reg - DATA);
2928 break;
2929
2930 case 'e': /* EMAC ACCx, reg/reg. */
2931 install_operand (s[1], opP->reg - ACC);
2932 break;
2933
2934 case 'E': /* Ignore it. */
2935 break;
2936
2937 case 'F':
2938 install_operand (s[1], opP->reg - FP0);
2939 break;
2940
2941 case 'g': /* EMAC ACCEXTx. */
2942 install_operand (s[1], opP->reg - ACCEXT01);
2943 break;
2944
2945 case 'G': /* Ignore it. */
2946 case 'H':
2947 break;
2948
2949 case 'I':
2950 tmpreg = opP->reg - COP0;
2951 install_operand (s[1], tmpreg);
2952 break;
2953
2954 case 'i': /* MAC/EMAC scale factor. */
2955 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
2956 break;
2957
2958 case 'J': /* JF foo. */
2959 switch (opP->reg)
2960 {
2961 case SFC:
2962 tmpreg = 0x000;
2963 break;
2964 case DFC:
2965 tmpreg = 0x001;
2966 break;
2967 case CACR:
2968 tmpreg = 0x002;
2969 break;
2970 case TC:
2971 tmpreg = 0x003;
2972 break;
2973 case ACR0:
2974 case ITT0:
2975 tmpreg = 0x004;
2976 break;
2977 case ACR1:
2978 case ITT1:
2979 tmpreg = 0x005;
2980 break;
2981 case ACR2:
2982 case DTT0:
2983 tmpreg = 0x006;
2984 break;
2985 case ACR3:
2986 case DTT1:
2987 tmpreg = 0x007;
2988 break;
2989 case BUSCR:
2990 tmpreg = 0x008;
2991 break;
2992
2993 case USP:
2994 tmpreg = 0x800;
2995 break;
2996 case VBR:
2997 tmpreg = 0x801;
2998 break;
2999 case CAAR:
3000 tmpreg = 0x802;
3001 break;
3002 case MSP:
3003 tmpreg = 0x803;
3004 break;
3005 case ISP:
3006 tmpreg = 0x804;
3007 break;
3008 case MMUSR:
3009 tmpreg = 0x805;
3010 break;
3011 case URP:
3012 tmpreg = 0x806;
3013 break;
3014 case SRP:
3015 tmpreg = 0x807;
3016 break;
3017 case PCR:
3018 tmpreg = 0x808;
3019 break;
3020 case ROMBAR:
3021 tmpreg = 0xC00;
3022 break;
3023 case ROMBAR1:
3024 tmpreg = 0xC01;
3025 break;
3026 case FLASHBAR:
3027 case RAMBAR0:
3028 tmpreg = 0xC04;
3029 break;
3030 case RAMBAR:
3031 case RAMBAR1:
3032 tmpreg = 0xC05;
3033 break;
3034 case MPCR:
3035 tmpreg = 0xC0C;
3036 break;
3037 case EDRAMBAR:
3038 tmpreg = 0xC0D;
3039 break;
3040 case MBAR0:
3041 case MBAR2:
3042 case SECMBAR:
3043 tmpreg = 0xC0E;
3044 break;
3045 case MBAR1:
3046 case MBAR:
3047 tmpreg = 0xC0F;
3048 break;
3049 case PCR1U0:
3050 tmpreg = 0xD02;
3051 break;
3052 case PCR1L0:
3053 tmpreg = 0xD03;
3054 break;
3055 case PCR2U0:
3056 tmpreg = 0xD04;
3057 break;
3058 case PCR2L0:
3059 tmpreg = 0xD05;
3060 break;
3061 case PCR3U0:
3062 tmpreg = 0xD06;
3063 break;
3064 case PCR3L0:
3065 tmpreg = 0xD07;
3066 break;
3067 case PCR1L1:
3068 tmpreg = 0xD0A;
3069 break;
3070 case PCR1U1:
3071 tmpreg = 0xD0B;
3072 break;
3073 case PCR2L1:
3074 tmpreg = 0xD0C;
3075 break;
3076 case PCR2U1:
3077 tmpreg = 0xD0D;
3078 break;
3079 case PCR3L1:
3080 tmpreg = 0xD0E;
3081 break;
3082 case PCR3U1:
3083 tmpreg = 0xD0F;
3084 break;
3085 default:
3086 abort ();
3087 }
3088 install_operand (s[1], tmpreg);
3089 break;
3090
3091 case 'k':
3092 tmpreg = get_num (&opP->disp, 55);
3093 install_operand (s[1], tmpreg & 0x7f);
3094 break;
3095
3096 case 'l':
3097 tmpreg = opP->mask;
3098 if (s[1] == 'w')
3099 {
3100 if (tmpreg & 0x7FF0000)
3101 as_bad (_("Floating point register in register list"));
3102 insop (reverse_16_bits (tmpreg), opcode);
3103 }
3104 else
3105 {
3106 if (tmpreg & 0x700FFFF)
3107 as_bad (_("Wrong register in floating-point reglist"));
3108 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3109 }
3110 break;
3111
3112 case 'L':
3113 tmpreg = opP->mask;
3114 if (s[1] == 'w')
3115 {
3116 if (tmpreg & 0x7FF0000)
3117 as_bad (_("Floating point register in register list"));
3118 insop (tmpreg, opcode);
3119 }
3120 else if (s[1] == '8')
3121 {
3122 if (tmpreg & 0x0FFFFFF)
3123 as_bad (_("incorrect register in reglist"));
3124 install_operand (s[1], tmpreg >> 24);
3125 }
3126 else
3127 {
3128 if (tmpreg & 0x700FFFF)
3129 as_bad (_("wrong register in floating-point reglist"));
3130 else
3131 install_operand (s[1], tmpreg >> 16);
3132 }
3133 break;
3134
3135 case 'M':
3136 install_operand (s[1], get_num (&opP->disp, 60));
3137 break;
3138
3139 case 'O':
3140 tmpreg = ((opP->mode == DREG)
3141 ? 0x20 + (int) (opP->reg - DATA)
3142 : (get_num (&opP->disp, 40) & 0x1F));
3143 install_operand (s[1], tmpreg);
3144 break;
3145
3146 case 'Q':
3147 tmpreg = get_num (&opP->disp, 10);
3148 if (tmpreg == 8)
3149 tmpreg = 0;
3150 install_operand (s[1], tmpreg);
3151 break;
3152
3153 case 'R':
3154 /* This depends on the fact that ADDR registers are eight
3155 more than their corresponding DATA regs, so the result
3156 will have the ADDR_REG bit set. */
3157 install_operand (s[1], opP->reg - DATA);
3158 break;
3159
3160 case 'r':
3161 if (opP->mode == AINDR)
3162 install_operand (s[1], opP->reg - DATA);
3163 else
3164 install_operand (s[1], opP->index.reg - DATA);
3165 break;
3166
3167 case 's':
3168 if (opP->reg == FPI)
3169 tmpreg = 0x1;
3170 else if (opP->reg == FPS)
3171 tmpreg = 0x2;
3172 else if (opP->reg == FPC)
3173 tmpreg = 0x4;
3174 else
3175 abort ();
3176 install_operand (s[1], tmpreg);
3177 break;
3178
3179 case 'S': /* Ignore it. */
3180 break;
3181
3182 case 'T':
3183 install_operand (s[1], get_num (&opP->disp, 30));
3184 break;
3185
3186 case 'U': /* Ignore it. */
3187 break;
3188
3189 case 'c':
3190 switch (opP->reg)
3191 {
3192 case NC:
3193 tmpreg = 0;
3194 break;
3195 case DC:
3196 tmpreg = 1;
3197 break;
3198 case IC:
3199 tmpreg = 2;
3200 break;
3201 case BC:
3202 tmpreg = 3;
3203 break;
3204 default:
3205 as_fatal (_("failed sanity check"));
3206 } /* switch on cache token. */
3207 install_operand (s[1], tmpreg);
3208 break;
3209 #ifndef NO_68851
3210 /* JF: These are out of order, I fear. */
3211 case 'f':
3212 switch (opP->reg)
3213 {
3214 case SFC:
3215 tmpreg = 0;
3216 break;
3217 case DFC:
3218 tmpreg = 1;
3219 break;
3220 default:
3221 abort ();
3222 }
3223 install_operand (s[1], tmpreg);
3224 break;
3225
3226 case '0':
3227 case '1':
3228 case '2':
3229 switch (opP->reg)
3230 {
3231 case TC:
3232 tmpreg = 0;
3233 break;
3234 case CAL:
3235 tmpreg = 4;
3236 break;
3237 case VAL:
3238 tmpreg = 5;
3239 break;
3240 case SCC:
3241 tmpreg = 6;
3242 break;
3243 case AC:
3244 tmpreg = 7;
3245 break;
3246 default:
3247 abort ();
3248 }
3249 install_operand (s[1], tmpreg);
3250 break;
3251
3252 case 'V':
3253 if (opP->reg == VAL)
3254 break;
3255 abort ();
3256
3257 case 'W':
3258 switch (opP->reg)
3259 {
3260 case DRP:
3261 tmpreg = 1;
3262 break;
3263 case SRP:
3264 tmpreg = 2;
3265 break;
3266 case CRP:
3267 tmpreg = 3;
3268 break;
3269 default:
3270 abort ();
3271 }
3272 install_operand (s[1], tmpreg);
3273 break;
3274
3275 case 'X':
3276 switch (opP->reg)
3277 {
3278 case BAD:
3279 case BAD + 1:
3280 case BAD + 2:
3281 case BAD + 3:
3282 case BAD + 4:
3283 case BAD + 5:
3284 case BAD + 6:
3285 case BAD + 7:
3286 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3287 break;
3288
3289 case BAC:
3290 case BAC + 1:
3291 case BAC + 2:
3292 case BAC + 3:
3293 case BAC + 4:
3294 case BAC + 5:
3295 case BAC + 6:
3296 case BAC + 7:
3297 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3298 break;
3299
3300 default:
3301 abort ();
3302 }
3303 install_operand (s[1], tmpreg);
3304 break;
3305 case 'Y':
3306 know (opP->reg == PSR);
3307 break;
3308 case 'Z':
3309 know (opP->reg == PCSR);
3310 break;
3311 #endif /* m68851 */
3312 case '3':
3313 switch (opP->reg)
3314 {
3315 case TT0:
3316 tmpreg = 2;
3317 break;
3318 case TT1:
3319 tmpreg = 3;
3320 break;
3321 default:
3322 abort ();
3323 }
3324 install_operand (s[1], tmpreg);
3325 break;
3326 case 't':
3327 tmpreg = get_num (&opP->disp, 20);
3328 install_operand (s[1], tmpreg);
3329 break;
3330 case '_': /* used only for move16 absolute 32-bit address. */
3331 if (isvar (&opP->disp))
3332 add_fix ('l', &opP->disp, 0, 0);
3333 tmpreg = get_num (&opP->disp, 90);
3334 addword (tmpreg >> 16);
3335 addword (tmpreg & 0xFFFF);
3336 break;
3337 case 'u':
3338 install_operand (s[1], opP->reg - DATA0L);
3339 opP->reg -= (DATA0L);
3340 opP->reg &= 0x0F; /* remove upper/lower bit. */
3341 break;
3342 case 'x':
3343 tmpreg = get_num (&opP->disp, 80);
3344 if (tmpreg == -1)
3345 tmpreg = 0;
3346 install_operand (s[1], tmpreg);
3347 break;
3348 default:
3349 abort ();
3350 }
3351 }
3352
3353 /* By the time whe get here (FINALLY) the_ins contains the complete
3354 instruction, ready to be emitted. . . */
3355 }
3356
3357 static int
3358 reverse_16_bits (int in)
3359 {
3360 int out = 0;
3361 int n;
3362
3363 static int mask[16] =
3364 {
3365 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3366 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3367 };
3368 for (n = 0; n < 16; n++)
3369 {
3370 if (in & mask[n])
3371 out |= mask[15 - n];
3372 }
3373 return out;
3374 } /* reverse_16_bits() */
3375
3376 static int
3377 reverse_8_bits (int in)
3378 {
3379 int out = 0;
3380 int n;
3381
3382 static int mask[8] =
3383 {
3384 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3385 };
3386
3387 for (n = 0; n < 8; n++)
3388 {
3389 if (in & mask[n])
3390 out |= mask[7 - n];
3391 }
3392 return out;
3393 } /* reverse_8_bits() */
3394
3395 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3396 (that value is chosen in the frag_var call in md_assemble). TYPE
3397 is the subtype of the frag to be generated; its primary type is
3398 rs_machine_dependent.
3399
3400 The TYPE parameter is also used by md_convert_frag_1 and
3401 md_estimate_size_before_relax. The appropriate type of fixup will
3402 be emitted by md_convert_frag_1.
3403
3404 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3405 static void
3406 install_operand (int mode, int val)
3407 {
3408 switch (mode)
3409 {
3410 case 's':
3411 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3412 break;
3413 case 'd':
3414 the_ins.opcode[0] |= val << 9;
3415 break;
3416 case '1':
3417 the_ins.opcode[1] |= val << 12;
3418 break;
3419 case '2':
3420 the_ins.opcode[1] |= val << 6;
3421 break;
3422 case '3':
3423 the_ins.opcode[1] |= val;
3424 break;
3425 case '4':
3426 the_ins.opcode[2] |= val << 12;
3427 break;
3428 case '5':
3429 the_ins.opcode[2] |= val << 6;
3430 break;
3431 case '6':
3432 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3433 three words long! */
3434 the_ins.numo++;
3435 the_ins.opcode[2] |= val;
3436 break;
3437 case '7':
3438 the_ins.opcode[1] |= val << 7;
3439 break;
3440 case '8':
3441 the_ins.opcode[1] |= val << 10;
3442 break;
3443 #ifndef NO_68851
3444 case '9':
3445 the_ins.opcode[1] |= val << 5;
3446 break;
3447 #endif
3448
3449 case 't':
3450 the_ins.opcode[1] |= (val << 10) | (val << 7);
3451 break;
3452 case 'D':
3453 the_ins.opcode[1] |= (val << 12) | val;
3454 break;
3455 case 'g':
3456 the_ins.opcode[0] |= val = 0xff;
3457 break;
3458 case 'i':
3459 the_ins.opcode[0] |= val << 9;
3460 break;
3461 case 'C':
3462 the_ins.opcode[1] |= val;
3463 break;
3464 case 'j':
3465 the_ins.opcode[1] |= val;
3466 the_ins.numo++; /* What a hack. */
3467 break;
3468 case 'k':
3469 the_ins.opcode[1] |= val << 4;
3470 break;
3471 case 'b':
3472 case 'w':
3473 case 'W':
3474 case 'l':
3475 break;
3476 case 'e':
3477 the_ins.opcode[0] |= (val << 6);
3478 break;
3479 case 'L':
3480 the_ins.opcode[1] = (val >> 16);
3481 the_ins.opcode[2] = val & 0xffff;
3482 break;
3483 case 'm':
3484 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3485 the_ins.opcode[0] |= ((val & 0x7) << 9);
3486 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3487 break;
3488 case 'n': /* MAC/EMAC Rx on !load. */
3489 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3490 the_ins.opcode[0] |= ((val & 0x7) << 9);
3491 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3492 break;
3493 case 'o': /* MAC/EMAC Rx on load. */
3494 the_ins.opcode[1] |= val << 12;
3495 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3496 break;
3497 case 'M': /* MAC/EMAC Ry on !load. */
3498 the_ins.opcode[0] |= (val & 0xF);
3499 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3500 break;
3501 case 'N': /* MAC/EMAC Ry on load. */
3502 the_ins.opcode[1] |= (val & 0xF);
3503 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3504 break;
3505 case 'h':
3506 the_ins.opcode[1] |= ((val != 1) << 10);
3507 break;
3508 case 'F':
3509 the_ins.opcode[0] |= ((val & 0x3) << 9);
3510 break;
3511 case 'f':
3512 the_ins.opcode[0] |= ((val & 0x3) << 0);
3513 break;
3514 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3515 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3516 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3517 break;
3518 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3519 the_ins.opcode[0] |= ((val & 0x1) << 7);
3520 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3521 break;
3522 case 'I':
3523 the_ins.opcode[1] |= ((val & 0x3) << 9);
3524 break;
3525 case ']':
3526 the_ins.opcode[0] |= (val & 0x1) <<10;
3527 break;
3528 case 'c':
3529 default:
3530 as_fatal (_("failed sanity check."));
3531 }
3532 }
3533
3534 static void
3535 install_gen_operand (int mode, int val)
3536 {
3537 switch (mode)
3538 {
3539 case '/': /* Special for mask loads for mac/msac insns with
3540 possible mask; trailing_ampersend set in bit 8. */
3541 the_ins.opcode[0] |= (val & 0x3f);
3542 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3543 break;
3544 case 's':
3545 the_ins.opcode[0] |= val;
3546 break;
3547 case 'd':
3548 /* This is a kludge!!! */
3549 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3550 break;
3551 case 'b':
3552 case 'w':
3553 case 'l':
3554 case 'f':
3555 case 'F':
3556 case 'x':
3557 case 'p':
3558 the_ins.opcode[0] |= val;
3559 break;
3560 /* more stuff goes here. */
3561 default:
3562 as_fatal (_("failed sanity check."));
3563 }
3564 }
3565
3566 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3567 then deal with the bitfield hack. */
3568
3569 static char *
3570 crack_operand (char *str, struct m68k_op *opP)
3571 {
3572 register int parens;
3573 register int c;
3574 register char *beg_str;
3575 int inquote = 0;
3576
3577 if (!str)
3578 {
3579 return str;
3580 }
3581 beg_str = str;
3582 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3583 {
3584 if (! inquote)
3585 {
3586 if (*str == '(')
3587 parens++;
3588 else if (*str == ')')
3589 {
3590 if (!parens)
3591 { /* ERROR. */
3592 opP->error = _("Extra )");
3593 return str;
3594 }
3595 --parens;
3596 }
3597 }
3598 if (flag_mri && *str == '\'')
3599 inquote = ! inquote;
3600 }
3601 if (!*str && parens)
3602 { /* ERROR. */
3603 opP->error = _("Missing )");
3604 return str;
3605 }
3606 c = *str;
3607 *str = '\0';
3608 if (m68k_ip_op (beg_str, opP) != 0)
3609 {
3610 *str = c;
3611 return str;
3612 }
3613 *str = c;
3614 if (c == '}')
3615 c = *++str; /* JF bitfield hack. */
3616 if (c)
3617 {
3618 c = *++str;
3619 if (!c)
3620 as_bad (_("Missing operand"));
3621 }
3622
3623 /* Detect MRI REG symbols and convert them to REGLSTs. */
3624 if (opP->mode == CONTROL && (int)opP->reg < 0)
3625 {
3626 opP->mode = REGLST;
3627 opP->mask = ~(int)opP->reg;
3628 opP->reg = 0;
3629 }
3630
3631 return str;
3632 }
3633
3634 /* This is the guts of the machine-dependent assembler. STR points to a
3635 machine dependent instruction. This function is supposed to emit
3636 the frags/bytes it assembles to.
3637 */
3638
3639 static void
3640 insert_reg (const char *regname, int regnum)
3641 {
3642 char buf[100];
3643 int i;
3644
3645 #ifdef REGISTER_PREFIX
3646 if (!flag_reg_prefix_optional)
3647 {
3648 buf[0] = REGISTER_PREFIX;
3649 strcpy (buf + 1, regname);
3650 regname = buf;
3651 }
3652 #endif
3653
3654 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3655 &zero_address_frag));
3656
3657 for (i = 0; regname[i]; i++)
3658 buf[i] = TOUPPER (regname[i]);
3659 buf[i] = '\0';
3660
3661 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3662 &zero_address_frag));
3663 }
3664
3665 struct init_entry
3666 {
3667 const char *name;
3668 int number;
3669 };
3670
3671 static const struct init_entry init_table[] =
3672 {
3673 { "d0", DATA0 },
3674 { "d1", DATA1 },
3675 { "d2", DATA2 },
3676 { "d3", DATA3 },
3677 { "d4", DATA4 },
3678 { "d5", DATA5 },
3679 { "d6", DATA6 },
3680 { "d7", DATA7 },
3681 { "a0", ADDR0 },
3682 { "a1", ADDR1 },
3683 { "a2", ADDR2 },
3684 { "a3", ADDR3 },
3685 { "a4", ADDR4 },
3686 { "a5", ADDR5 },
3687 { "a6", ADDR6 },
3688 { "fp", ADDR6 },
3689 { "a7", ADDR7 },
3690 { "sp", ADDR7 },
3691 { "ssp", ADDR7 },
3692 { "fp0", FP0 },
3693 { "fp1", FP1 },
3694 { "fp2", FP2 },
3695 { "fp3", FP3 },
3696 { "fp4", FP4 },
3697 { "fp5", FP5 },
3698 { "fp6", FP6 },
3699 { "fp7", FP7 },
3700 { "fpi", FPI },
3701 { "fpiar", FPI },
3702 { "fpc", FPI },
3703 { "fps", FPS },
3704 { "fpsr", FPS },
3705 { "fpc", FPC },
3706 { "fpcr", FPC },
3707 { "control", FPC },
3708 { "status", FPS },
3709 { "iaddr", FPI },
3710
3711 { "cop0", COP0 },
3712 { "cop1", COP1 },
3713 { "cop2", COP2 },
3714 { "cop3", COP3 },
3715 { "cop4", COP4 },
3716 { "cop5", COP5 },
3717 { "cop6", COP6 },
3718 { "cop7", COP7 },
3719 { "pc", PC },
3720 { "zpc", ZPC },
3721 { "sr", SR },
3722
3723 { "ccr", CCR },
3724 { "cc", CCR },
3725
3726 { "acc", ACC },
3727 { "acc0", ACC },
3728 { "acc1", ACC1 },
3729 { "acc2", ACC2 },
3730 { "acc3", ACC3 },
3731 { "accext01", ACCEXT01 },
3732 { "accext23", ACCEXT23 },
3733 { "macsr", MACSR },
3734 { "mask", MASK },
3735
3736 /* Control registers. */
3737 { "sfc", SFC }, /* Source Function Code. */
3738 { "sfcr", SFC },
3739 { "dfc", DFC }, /* Destination Function Code. */
3740 { "dfcr", DFC },
3741 { "cacr", CACR }, /* Cache Control Register. */
3742 { "caar", CAAR }, /* Cache Address Register. */
3743
3744 { "usp", USP }, /* User Stack Pointer. */
3745 { "vbr", VBR }, /* Vector Base Register. */
3746 { "msp", MSP }, /* Master Stack Pointer. */
3747 { "isp", ISP }, /* Interrupt Stack Pointer. */
3748
3749 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3750 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3751 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3752 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
3753
3754 /* 68ec040 versions of same */
3755 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3756 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3757 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3758 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
3759
3760 /* mcf5200 versions of same. The ColdFire programmer's reference
3761 manual indicated that the order is 2,3,0,1, but Ken Rose
3762 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3763 { "acr0", ACR0 }, /* Access Control Unit 0. */
3764 { "acr1", ACR1 }, /* Access Control Unit 1. */
3765 { "acr2", ACR2 }, /* Access Control Unit 2. */
3766 { "acr3", ACR3 }, /* Access Control Unit 3. */
3767
3768 { "tc", TC }, /* MMU Translation Control Register. */
3769 { "tcr", TC },
3770
3771 { "mmusr", MMUSR }, /* MMU Status Register. */
3772 { "srp", SRP }, /* User Root Pointer. */
3773 { "urp", URP }, /* Supervisor Root Pointer. */
3774
3775 { "buscr", BUSCR },
3776 { "pcr", PCR },
3777
3778 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3779 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3780 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3781 { "mbar", MBAR }, /* Module Base Address Register. */
3782
3783 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3784 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3785 { "rombar0", ROMBAR }, /* mcfv4e registers. */
3786 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3787 { "mpcr", MPCR }, /* mcfv4e registers. */
3788 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3789 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3790 { "asid", TC }, /* mcfv4e registers. */
3791 { "mmubar", BUSCR }, /* mcfv4e registers. */
3792 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3793 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3794 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3795 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3796 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3797 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3798 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3799 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3800 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3801 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3802 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3803 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3804
3805 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3806 { "rambar", RAMBAR }, /* mcf528x registers. */
3807
3808 { "mbar2", MBAR2 }, /* mcf5249 registers. */
3809 /* End of control registers. */
3810
3811 { "ac", AC },
3812 { "bc", BC },
3813 { "cal", CAL },
3814 { "crp", CRP },
3815 { "drp", DRP },
3816 { "pcsr", PCSR },
3817 { "psr", PSR },
3818 { "scc", SCC },
3819 { "val", VAL },
3820 { "bad0", BAD0 },
3821 { "bad1", BAD1 },
3822 { "bad2", BAD2 },
3823 { "bad3", BAD3 },
3824 { "bad4", BAD4 },
3825 { "bad5", BAD5 },
3826 { "bad6", BAD6 },
3827 { "bad7", BAD7 },
3828 { "bac0", BAC0 },
3829 { "bac1", BAC1 },
3830 { "bac2", BAC2 },
3831 { "bac3", BAC3 },
3832 { "bac4", BAC4 },
3833 { "bac5", BAC5 },
3834 { "bac6", BAC6 },
3835 { "bac7", BAC7 },
3836
3837 { "ic", IC },
3838 { "dc", DC },
3839 { "nc", NC },
3840
3841 { "tt0", TT0 },
3842 { "tt1", TT1 },
3843 /* 68ec030 versions of same. */
3844 { "ac0", TT0 },
3845 { "ac1", TT1 },
3846 /* 68ec030 access control unit, identical to 030 MMU status reg. */
3847 { "acusr", PSR },
3848
3849 /* Suppressed data and address registers. */
3850 { "zd0", ZDATA0 },
3851 { "zd1", ZDATA1 },
3852 { "zd2", ZDATA2 },
3853 { "zd3", ZDATA3 },
3854 { "zd4", ZDATA4 },
3855 { "zd5", ZDATA5 },
3856 { "zd6", ZDATA6 },
3857 { "zd7", ZDATA7 },
3858 { "za0", ZADDR0 },
3859 { "za1", ZADDR1 },
3860 { "za2", ZADDR2 },
3861 { "za3", ZADDR3 },
3862 { "za4", ZADDR4 },
3863 { "za5", ZADDR5 },
3864 { "za6", ZADDR6 },
3865 { "za7", ZADDR7 },
3866
3867 /* Upper and lower data and address registers, used by macw and msacw. */
3868 { "d0l", DATA0L },
3869 { "d1l", DATA1L },
3870 { "d2l", DATA2L },
3871 { "d3l", DATA3L },
3872 { "d4l", DATA4L },
3873 { "d5l", DATA5L },
3874 { "d6l", DATA6L },
3875 { "d7l", DATA7L },
3876
3877 { "a0l", ADDR0L },
3878 { "a1l", ADDR1L },
3879 { "a2l", ADDR2L },
3880 { "a3l", ADDR3L },
3881 { "a4l", ADDR4L },
3882 { "a5l", ADDR5L },
3883 { "a6l", ADDR6L },
3884 { "a7l", ADDR7L },
3885
3886 { "d0u", DATA0U },
3887 { "d1u", DATA1U },
3888 { "d2u", DATA2U },
3889 { "d3u", DATA3U },
3890 { "d4u", DATA4U },
3891 { "d5u", DATA5U },
3892 { "d6u", DATA6U },
3893 { "d7u", DATA7U },
3894
3895 { "a0u", ADDR0U },
3896 { "a1u", ADDR1U },
3897 { "a2u", ADDR2U },
3898 { "a3u", ADDR3U },
3899 { "a4u", ADDR4U },
3900 { "a5u", ADDR5U },
3901 { "a6u", ADDR6U },
3902 { "a7u", ADDR7U },
3903
3904 { 0, 0 }
3905 };
3906
3907 static void
3908 init_regtable (void)
3909 {
3910 int i;
3911 for (i = 0; init_table[i].name; i++)
3912 insert_reg (init_table[i].name, init_table[i].number);
3913 }
3914
3915 void
3916 md_assemble (char *str)
3917 {
3918 const char *er;
3919 short *fromP;
3920 char *toP = NULL;
3921 int m, n = 0;
3922 char *to_beg_P;
3923 int shorts_this_frag;
3924 fixS *fixP;
3925
3926 if (!selected_cpu && !selected_arch)
3927 {
3928 /* We've not selected an architecture yet. Set the default
3929 now. We do this lazily so that an initial .cpu or .arch directive
3930 can specify. */
3931 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
3932 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
3933 }
3934 if (!initialized)
3935 m68k_init_arch ();
3936
3937 /* In MRI mode, the instruction and operands are separated by a
3938 space. Anything following the operands is a comment. The label
3939 has already been removed. */
3940 if (flag_mri)
3941 {
3942 char *s;
3943 int fields = 0;
3944 int infield = 0;
3945 int inquote = 0;
3946
3947 for (s = str; *s != '\0'; s++)
3948 {
3949 if ((*s == ' ' || *s == '\t') && ! inquote)
3950 {
3951 if (infield)
3952 {
3953 ++fields;
3954 if (fields >= 2)
3955 {
3956 *s = '\0';
3957 break;
3958 }
3959 infield = 0;
3960 }
3961 }
3962 else
3963 {
3964 if (! infield)
3965 infield = 1;
3966 if (*s == '\'')
3967 inquote = ! inquote;
3968 }
3969 }
3970 }
3971
3972 memset (&the_ins, '\0', sizeof (the_ins));
3973 m68k_ip (str);
3974 er = the_ins.error;
3975 if (!er)
3976 {
3977 for (n = 0; n < the_ins.numargs; n++)
3978 if (the_ins.operands[n].error)
3979 {
3980 er = the_ins.operands[n].error;
3981 break;
3982 }
3983 }
3984 if (er)
3985 {
3986 as_bad (_("%s -- statement `%s' ignored"), er, str);
3987 return;
3988 }
3989
3990 /* If there is a current label, record that it marks an instruction. */
3991 if (current_label != NULL)
3992 {
3993 current_label->text = 1;
3994 current_label = NULL;
3995 }
3996
3997 #ifdef OBJ_ELF
3998 /* Tie dwarf2 debug info to the address at the start of the insn. */
3999 dwarf2_emit_insn (0);
4000 #endif
4001
4002 if (the_ins.nfrag == 0)
4003 {
4004 /* No frag hacking involved; just put it out. */
4005 toP = frag_more (2 * the_ins.numo);
4006 fromP = &the_ins.opcode[0];
4007 for (m = the_ins.numo; m; --m)
4008 {
4009 md_number_to_chars (toP, (long) (*fromP), 2);
4010 toP += 2;
4011 fromP++;
4012 }
4013 /* Put out symbol-dependent info. */
4014 for (m = 0; m < the_ins.nrel; m++)
4015 {
4016 switch (the_ins.reloc[m].wid)
4017 {
4018 case 'B':
4019 n = 1;
4020 break;
4021 case 'b':
4022 n = 1;
4023 break;
4024 case '3':
4025 n = 1;
4026 break;
4027 case 'w':
4028 case 'W':
4029 n = 2;
4030 break;
4031 case 'l':
4032 n = 4;
4033 break;
4034 default:
4035 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4036 the_ins.reloc[m].wid);
4037 }
4038
4039 fixP = fix_new_exp (frag_now,
4040 ((toP - frag_now->fr_literal)
4041 - the_ins.numo * 2 + the_ins.reloc[m].n),
4042 n,
4043 &the_ins.reloc[m].exp,
4044 the_ins.reloc[m].pcrel,
4045 get_reloc_code (n, the_ins.reloc[m].pcrel,
4046 the_ins.reloc[m].pic_reloc));
4047 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4048 if (the_ins.reloc[m].wid == 'B')
4049 fixP->fx_signed = 1;
4050 }
4051 return;
4052 }
4053
4054 /* There's some frag hacking. */
4055 {
4056 /* Calculate the max frag size. */
4057 int wid;
4058
4059 wid = 2 * the_ins.fragb[0].fragoff;
4060 for (n = 1; n < the_ins.nfrag; n++)
4061 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4062 /* frag_var part. */
4063 wid += 10;
4064 /* Make sure the whole insn fits in one chunk, in particular that
4065 the var part is attached, as we access one byte before the
4066 variable frag for byte branches. */
4067 frag_grow (wid);
4068 }
4069
4070 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4071 {
4072 int wid;
4073
4074 if (n == 0)
4075 wid = 2 * the_ins.fragb[n].fragoff;
4076 else
4077 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4078 toP = frag_more (wid);
4079 to_beg_P = toP;
4080 shorts_this_frag = 0;
4081 for (m = wid / 2; m; --m)
4082 {
4083 md_number_to_chars (toP, (long) (*fromP), 2);
4084 toP += 2;
4085 fromP++;
4086 shorts_this_frag++;
4087 }
4088 for (m = 0; m < the_ins.nrel; m++)
4089 {
4090 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4091 {
4092 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4093 break;
4094 }
4095 wid = the_ins.reloc[m].wid;
4096 if (wid == 0)
4097 continue;
4098 the_ins.reloc[m].wid = 0;
4099 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4100
4101 fixP = fix_new_exp (frag_now,
4102 ((toP - frag_now->fr_literal)
4103 - the_ins.numo * 2 + the_ins.reloc[m].n),
4104 wid,
4105 &the_ins.reloc[m].exp,
4106 the_ins.reloc[m].pcrel,
4107 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4108 the_ins.reloc[m].pic_reloc));
4109 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4110 }
4111 (void) frag_var (rs_machine_dependent, 10, 0,
4112 (relax_substateT) (the_ins.fragb[n].fragty),
4113 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4114 }
4115 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4116 shorts_this_frag = 0;
4117 if (n)
4118 {
4119 toP = frag_more (n * 2);
4120 while (n--)
4121 {
4122 md_number_to_chars (toP, (long) (*fromP), 2);
4123 toP += 2;
4124 fromP++;
4125 shorts_this_frag++;
4126 }
4127 }
4128 for (m = 0; m < the_ins.nrel; m++)
4129 {
4130 int wid;
4131
4132 wid = the_ins.reloc[m].wid;
4133 if (wid == 0)
4134 continue;
4135 the_ins.reloc[m].wid = 0;
4136 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4137
4138 fixP = fix_new_exp (frag_now,
4139 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4140 - shorts_this_frag * 2),
4141 wid,
4142 &the_ins.reloc[m].exp,
4143 the_ins.reloc[m].pcrel,
4144 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4145 the_ins.reloc[m].pic_reloc));
4146 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4147 }
4148 }
4149
4150 /* Comparison function used by qsort to rank the opcode entries by name. */
4151
4152 static int
4153 m68k_compare_opcode (const void * v1, const void * v2)
4154 {
4155 struct m68k_opcode * op1, * op2;
4156 int ret;
4157
4158 if (v1 == v2)
4159 return 0;
4160
4161 op1 = *(struct m68k_opcode **) v1;
4162 op2 = *(struct m68k_opcode **) v2;
4163
4164 /* Compare the two names. If different, return the comparison.
4165 If the same, return the order they are in the opcode table. */
4166 ret = strcmp (op1->name, op2->name);
4167 if (ret)
4168 return ret;
4169 if (op1 < op2)
4170 return -1;
4171 return 1;
4172 }
4173
4174 void
4175 md_begin (void)
4176 {
4177 const struct m68k_opcode *ins;
4178 struct m68k_incant *hack, *slak;
4179 const char *retval = 0; /* Empty string, or error msg text. */
4180 int i;
4181
4182 /* Set up hash tables with 68000 instructions.
4183 similar to what the vax assembler does. */
4184 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4185 a copy of it at runtime, adding in the information we want but isn't
4186 there. I think it'd be better to have an awk script hack the table
4187 at compile time. Or even just xstr the table and use it as-is. But
4188 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4189 names. */
4190
4191 if (flag_mri)
4192 {
4193 flag_reg_prefix_optional = 1;
4194 m68k_abspcadd = 1;
4195 if (! m68k_rel32_from_cmdline)
4196 m68k_rel32 = 0;
4197 }
4198
4199 /* First sort the opcode table into alphabetical order to seperate
4200 the order that the assembler wants to see the opcodes from the
4201 order that the disassembler wants to see them. */
4202 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4203 if (!m68k_sorted_opcodes)
4204 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4205 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
4206
4207 for (i = m68k_numopcodes; i--;)
4208 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4209
4210 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4211 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4212
4213 op_hash = hash_new ();
4214
4215 obstack_begin (&robyn, 4000);
4216 for (i = 0; i < m68k_numopcodes; i++)
4217 {
4218 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4219 do
4220 {
4221 ins = m68k_sorted_opcodes[i];
4222
4223 /* We *could* ignore insns that don't match our
4224 arch here by just leaving them out of the hash. */
4225 slak->m_operands = ins->args;
4226 slak->m_opnum = strlen (slak->m_operands) / 2;
4227 slak->m_arch = ins->arch;
4228 slak->m_opcode = ins->opcode;
4229 /* This is kludgey. */
4230 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4231 if (i + 1 != m68k_numopcodes
4232 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4233 {
4234 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4235 i++;
4236 }
4237 else
4238 slak->m_next = 0;
4239 slak = slak->m_next;
4240 }
4241 while (slak);
4242
4243 retval = hash_insert (op_hash, ins->name, (char *) hack);
4244 if (retval)
4245 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4246 }
4247
4248 for (i = 0; i < m68k_numaliases; i++)
4249 {
4250 const char *name = m68k_opcode_aliases[i].primary;
4251 const char *alias = m68k_opcode_aliases[i].alias;
4252 PTR val = hash_find (op_hash, name);
4253
4254 if (!val)
4255 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4256 retval = hash_insert (op_hash, alias, val);
4257 if (retval)
4258 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4259 }
4260
4261 /* In MRI mode, all unsized branches are variable sized. Normally,
4262 they are word sized. */
4263 if (flag_mri)
4264 {
4265 static struct m68k_opcode_alias mri_aliases[] =
4266 {
4267 { "bhi", "jhi", },
4268 { "bls", "jls", },
4269 { "bcc", "jcc", },
4270 { "bcs", "jcs", },
4271 { "bne", "jne", },
4272 { "beq", "jeq", },
4273 { "bvc", "jvc", },
4274 { "bvs", "jvs", },
4275 { "bpl", "jpl", },
4276 { "bmi", "jmi", },
4277 { "bge", "jge", },
4278 { "blt", "jlt", },
4279 { "bgt", "jgt", },
4280 { "ble", "jle", },
4281 { "bra", "jra", },
4282 { "bsr", "jbsr", },
4283 };
4284
4285 for (i = 0;
4286 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4287 i++)
4288 {
4289 const char *name = mri_aliases[i].primary;
4290 const char *alias = mri_aliases[i].alias;
4291 PTR val = hash_find (op_hash, name);
4292
4293 if (!val)
4294 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4295 retval = hash_jam (op_hash, alias, val);
4296 if (retval)
4297 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4298 }
4299 }
4300
4301 for (i = 0; i < (int) sizeof (notend_table); i++)
4302 {
4303 notend_table[i] = 0;
4304 alt_notend_table[i] = 0;
4305 }
4306
4307 notend_table[','] = 1;
4308 notend_table['{'] = 1;
4309 notend_table['}'] = 1;
4310 alt_notend_table['a'] = 1;
4311 alt_notend_table['A'] = 1;
4312 alt_notend_table['d'] = 1;
4313 alt_notend_table['D'] = 1;
4314 alt_notend_table['#'] = 1;
4315 alt_notend_table['&'] = 1;
4316 alt_notend_table['f'] = 1;
4317 alt_notend_table['F'] = 1;
4318 #ifdef REGISTER_PREFIX
4319 alt_notend_table[REGISTER_PREFIX] = 1;
4320 #endif
4321
4322 /* We need to put '(' in alt_notend_table to handle
4323 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4324 alt_notend_table['('] = 1;
4325
4326 /* We need to put '@' in alt_notend_table to handle
4327 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4328 alt_notend_table['@'] = 1;
4329
4330 /* We need to put digits in alt_notend_table to handle
4331 bfextu %d0{24:1},%d0 */
4332 alt_notend_table['0'] = 1;
4333 alt_notend_table['1'] = 1;
4334 alt_notend_table['2'] = 1;
4335 alt_notend_table['3'] = 1;
4336 alt_notend_table['4'] = 1;
4337 alt_notend_table['5'] = 1;
4338 alt_notend_table['6'] = 1;
4339 alt_notend_table['7'] = 1;
4340 alt_notend_table['8'] = 1;
4341 alt_notend_table['9'] = 1;
4342
4343 #ifndef MIT_SYNTAX_ONLY
4344 /* Insert pseudo ops, these have to go into the opcode table since
4345 gas expects pseudo ops to start with a dot. */
4346 {
4347 int n = 0;
4348
4349 while (mote_pseudo_table[n].poc_name)
4350 {
4351 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4352 hash_insert (op_hash,
4353 mote_pseudo_table[n].poc_name, (char *) hack);
4354 hack->m_operands = 0;
4355 hack->m_opnum = n;
4356 n++;
4357 }
4358 }
4359 #endif
4360
4361 init_regtable ();
4362
4363 #ifdef OBJ_ELF
4364 record_alignment (text_section, 2);
4365 record_alignment (data_section, 2);
4366 record_alignment (bss_section, 2);
4367 #endif
4368 }
4369
4370 static void
4371 select_control_regs (void)
4372 {
4373 /* Note which set of "movec" control registers is available. */
4374 switch (current_chip)
4375 {
4376 case 0:
4377 if (verbose)
4378 as_warn (_("architecture not yet selected: defaulting to 68020"));
4379 control_regs = m68020_control_regs;
4380 break;
4381
4382 case cpu_m68000:
4383 control_regs = m68000_control_regs;
4384 break;
4385 case cpu_m68010:
4386 control_regs = m68010_control_regs;
4387 break;
4388 case cpu_m68020:
4389 case cpu_m68030:
4390 control_regs = m68020_control_regs;
4391 break;
4392 case cpu_m68040:
4393 control_regs = m68040_control_regs;
4394 break;
4395 case cpu_m68060:
4396 control_regs = m68060_control_regs;
4397 break;
4398 case cpu_cpu32:
4399 control_regs = cpu32_control_regs;
4400 break;
4401 case cpu_cf5200:
4402 case cpu_cf5206e:
4403 case cpu_cf5307:
4404 case cpu_cf5407:
4405 control_regs = mcf_control_regs;
4406 break;
4407 case cpu_cf5249:
4408 control_regs = mcf5249_control_regs;
4409 break;
4410 case cpu_cf528x:
4411 case cpu_cf521x:
4412 control_regs = mcf528x_control_regs;
4413 break;
4414 case cpu_cf547x:
4415 case cpu_cf548x:
4416 control_regs = mcfv4e_control_regs;
4417 break;
4418 case cpu_cf5208:
4419 control_regs = mcf5208_control_regs;
4420 break;
4421 case cpu_cf5213:
4422 control_regs = mcf5213_control_regs;
4423 break;
4424 case cpu_cf5329:
4425 control_regs = mcf5329_control_regs;
4426 break;
4427 default:
4428 abort ();
4429 }
4430 }
4431
4432 \f
4433 /* This is called when a label is defined. */
4434
4435 void
4436 m68k_frob_label (symbolS *sym)
4437 {
4438 struct label_line *n;
4439
4440 n = (struct label_line *) xmalloc (sizeof *n);
4441 n->next = labels;
4442 n->label = sym;
4443 as_where (&n->file, &n->line);
4444 n->text = 0;
4445 labels = n;
4446 current_label = n;
4447
4448 #ifdef OBJ_ELF
4449 dwarf2_emit_label (sym);
4450 #endif
4451 }
4452
4453 /* This is called when a value that is not an instruction is emitted. */
4454
4455 void
4456 m68k_flush_pending_output (void)
4457 {
4458 current_label = NULL;
4459 }
4460
4461 /* This is called at the end of the assembly, when the final value of
4462 the label is known. We warn if this is a text symbol aligned at an
4463 odd location. */
4464
4465 void
4466 m68k_frob_symbol (symbolS *sym)
4467 {
4468 if (S_GET_SEGMENT (sym) == reg_section
4469 && (int) S_GET_VALUE (sym) < 0)
4470 {
4471 S_SET_SEGMENT (sym, absolute_section);
4472 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4473 }
4474 else if ((S_GET_VALUE (sym) & 1) != 0)
4475 {
4476 struct label_line *l;
4477
4478 for (l = labels; l != NULL; l = l->next)
4479 {
4480 if (l->label == sym)
4481 {
4482 if (l->text)
4483 as_warn_where (l->file, l->line,
4484 _("text label `%s' aligned to odd boundary"),
4485 S_GET_NAME (sym));
4486 break;
4487 }
4488 }
4489 }
4490 }
4491 \f
4492 /* This is called if we go in or out of MRI mode because of the .mri
4493 pseudo-op. */
4494
4495 void
4496 m68k_mri_mode_change (int on)
4497 {
4498 if (on)
4499 {
4500 if (! flag_reg_prefix_optional)
4501 {
4502 flag_reg_prefix_optional = 1;
4503 #ifdef REGISTER_PREFIX
4504 init_regtable ();
4505 #endif
4506 }
4507 m68k_abspcadd = 1;
4508 if (! m68k_rel32_from_cmdline)
4509 m68k_rel32 = 0;
4510 }
4511 else
4512 {
4513 if (! reg_prefix_optional_seen)
4514 {
4515 #ifdef REGISTER_PREFIX_OPTIONAL
4516 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4517 #else
4518 flag_reg_prefix_optional = 0;
4519 #endif
4520 #ifdef REGISTER_PREFIX
4521 init_regtable ();
4522 #endif
4523 }
4524 m68k_abspcadd = 0;
4525 if (! m68k_rel32_from_cmdline)
4526 m68k_rel32 = 1;
4527 }
4528 }
4529
4530 /* Equal to MAX_PRECISION in atof-ieee.c. */
4531 #define MAX_LITTLENUMS 6
4532
4533 /* Turn a string in input_line_pointer into a floating point constant
4534 of type TYPE, and store the appropriate bytes in *LITP. The number
4535 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4536 returned, or NULL on OK. */
4537
4538 char *
4539 md_atof (int type, char *litP, int *sizeP)
4540 {
4541 int prec;
4542 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4543 LITTLENUM_TYPE *wordP;
4544 char *t;
4545
4546 switch (type)
4547 {
4548 case 'f':
4549 case 'F':
4550 case 's':
4551 case 'S':
4552 prec = 2;
4553 break;
4554
4555 case 'd':
4556 case 'D':
4557 case 'r':
4558 case 'R':
4559 prec = 4;
4560 break;
4561
4562 case 'x':
4563 case 'X':
4564 prec = 6;
4565 break;
4566
4567 case 'p':
4568 case 'P':
4569 prec = 6;
4570 break;
4571
4572 default:
4573 *sizeP = 0;
4574 return _("Bad call to MD_ATOF()");
4575 }
4576 t = atof_ieee (input_line_pointer, type, words);
4577 if (t)
4578 input_line_pointer = t;
4579
4580 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4581 for (wordP = words; prec--;)
4582 {
4583 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4584 litP += sizeof (LITTLENUM_TYPE);
4585 }
4586 return 0;
4587 }
4588
4589 void
4590 md_number_to_chars (char *buf, valueT val, int n)
4591 {
4592 number_to_chars_bigendian (buf, val, n);
4593 }
4594
4595 void
4596 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4597 {
4598 offsetT val = *valP;
4599 addressT upper_limit;
4600 offsetT lower_limit;
4601
4602 /* This is unnecessary but it convinces the native rs6000 compiler
4603 to generate the code we want. */
4604 char *buf = fixP->fx_frag->fr_literal;
4605 buf += fixP->fx_where;
4606 /* End ibm compiler workaround. */
4607
4608 val = SEXT (val);
4609
4610 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4611 fixP->fx_done = 1;
4612
4613 #ifdef OBJ_ELF
4614 if (fixP->fx_addsy)
4615 {
4616 memset (buf, 0, fixP->fx_size);
4617 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4618
4619 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4620 && !S_IS_DEFINED (fixP->fx_addsy)
4621 && !S_IS_WEAK (fixP->fx_addsy))
4622 S_SET_WEAK (fixP->fx_addsy);
4623 return;
4624 }
4625 #endif
4626
4627 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4628 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4629 return;
4630
4631 switch (fixP->fx_size)
4632 {
4633 /* The cast to offsetT below are necessary to make code
4634 correct for machines where ints are smaller than offsetT. */
4635 case 1:
4636 *buf++ = val;
4637 upper_limit = 0x7f;
4638 lower_limit = - (offsetT) 0x80;
4639 break;
4640 case 2:
4641 *buf++ = (val >> 8);
4642 *buf++ = val;
4643 upper_limit = 0x7fff;
4644 lower_limit = - (offsetT) 0x8000;
4645 break;
4646 case 4:
4647 *buf++ = (val >> 24);
4648 *buf++ = (val >> 16);
4649 *buf++ = (val >> 8);
4650 *buf++ = val;
4651 upper_limit = 0x7fffffff;
4652 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4653 break;
4654 default:
4655 BAD_CASE (fixP->fx_size);
4656 }
4657
4658 /* Fix up a negative reloc. */
4659 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4660 {
4661 fixP->fx_addsy = fixP->fx_subsy;
4662 fixP->fx_subsy = NULL;
4663 fixP->fx_tcbit = 1;
4664 }
4665
4666 /* For non-pc-relative values, it's conceivable we might get something
4667 like "0xff" for a byte field. So extend the upper part of the range
4668 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4669 so that we can do any range checking at all. */
4670 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4671 upper_limit = upper_limit * 2 + 1;
4672
4673 if ((addressT) val > upper_limit
4674 && (val > 0 || val < lower_limit))
4675 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4676
4677 /* A one byte PC-relative reloc means a short branch. We can't use
4678 a short branch with a value of 0 or -1, because those indicate
4679 different opcodes (branches with longer offsets). fixup_segment
4680 in write.c may have clobbered fx_pcrel, so we need to examine the
4681 reloc type. */
4682 if ((fixP->fx_pcrel
4683 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4684 && fixP->fx_size == 1
4685 && (fixP->fx_addsy == NULL
4686 || S_IS_DEFINED (fixP->fx_addsy))
4687 && (val == 0 || val == -1))
4688 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4689 }
4690
4691 /* *fragP has been relaxed to its final size, and now needs to have
4692 the bytes inside it modified to conform to the new size There is UGLY
4693 MAGIC here. ..
4694 */
4695 static void
4696 md_convert_frag_1 (fragS *fragP)
4697 {
4698 long disp;
4699 fixS *fixP;
4700
4701 /* Address in object code of the displacement. */
4702 register int object_address = fragP->fr_fix + fragP->fr_address;
4703
4704 /* Address in gas core of the place to store the displacement. */
4705 /* This convinces the native rs6000 compiler to generate the code we
4706 want. */
4707 register char *buffer_address = fragP->fr_literal;
4708 buffer_address += fragP->fr_fix;
4709 /* End ibm compiler workaround. */
4710
4711 /* The displacement of the address, from current location. */
4712 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4713 disp = (disp + fragP->fr_offset) - object_address;
4714
4715 switch (fragP->fr_subtype)
4716 {
4717 case TAB (BRANCHBWL, BYTE):
4718 case TAB (BRABSJUNC, BYTE):
4719 case TAB (BRABSJCOND, BYTE):
4720 case TAB (BRANCHBW, BYTE):
4721 know (issbyte (disp));
4722 if (disp == 0)
4723 as_bad_where (fragP->fr_file, fragP->fr_line,
4724 _("short branch with zero offset: use :w"));
4725 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4726 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4727 fixP->fx_pcrel_adjust = -1;
4728 break;
4729 case TAB (BRANCHBWL, SHORT):
4730 case TAB (BRABSJUNC, SHORT):
4731 case TAB (BRABSJCOND, SHORT):
4732 case TAB (BRANCHBW, SHORT):
4733 fragP->fr_opcode[1] = 0x00;
4734 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4735 1, RELAX_RELOC_PC16);
4736 fragP->fr_fix += 2;
4737 break;
4738 case TAB (BRANCHBWL, LONG):
4739 fragP->fr_opcode[1] = (char) 0xFF;
4740 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4741 1, RELAX_RELOC_PC32);
4742 fragP->fr_fix += 4;
4743 break;
4744 case TAB (BRABSJUNC, LONG):
4745 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4746 {
4747 if (flag_keep_pcrel)
4748 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
4749 fragP->fr_opcode[0] = 0x4E;
4750 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4751 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4752 0, RELAX_RELOC_ABS32);
4753 fragP->fr_fix += 4;
4754 }
4755 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4756 {
4757 if (flag_keep_pcrel)
4758 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
4759 fragP->fr_opcode[0] = 0x4E;
4760 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4761 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4762 0, RELAX_RELOC_ABS32);
4763 fragP->fr_fix += 4;
4764 }
4765 else
4766 {
4767 /* This cannot happen, because jbsr and jbra are the only two
4768 unconditional branches. */
4769 abort ();
4770 }
4771 break;
4772 case TAB (BRABSJCOND, LONG):
4773 if (flag_keep_pcrel)
4774 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4775
4776 /* Only Bcc 68000 instructions can come here
4777 Change bcc into b!cc/jmp absl long. */
4778 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4779 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
4780
4781 /* JF: these used to be fr_opcode[2,3], but they may be in a
4782 different frag, in which case referring to them is a no-no.
4783 Only fr_opcode[0,1] are guaranteed to work. */
4784 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4785 *buffer_address++ = (char) 0xf9;
4786 fragP->fr_fix += 2; /* Account for jmp instruction. */
4787 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4788 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4789 fragP->fr_fix += 4;
4790 break;
4791 case TAB (FBRANCH, SHORT):
4792 know ((fragP->fr_opcode[1] & 0x40) == 0);
4793 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4794 1, RELAX_RELOC_PC16);
4795 fragP->fr_fix += 2;
4796 break;
4797 case TAB (FBRANCH, LONG):
4798 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
4799 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4800 1, RELAX_RELOC_PC32);
4801 fragP->fr_fix += 4;
4802 break;
4803 case TAB (DBCCLBR, SHORT):
4804 case TAB (DBCCABSJ, SHORT):
4805 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4806 1, RELAX_RELOC_PC16);
4807 fragP->fr_fix += 2;
4808 break;
4809 case TAB (DBCCLBR, LONG):
4810 /* Only DBcc instructions can come here.
4811 Change dbcc into dbcc/bral.
4812 JF: these used to be fr_opcode[2-7], but that's wrong. */
4813 if (flag_keep_pcrel)
4814 as_fatal (_("Tried to convert DBcc to absolute jump"));
4815
4816 *buffer_address++ = 0x00; /* Branch offset = 4. */
4817 *buffer_address++ = 0x04;
4818 *buffer_address++ = 0x60; /* Put in bra pc+6. */
4819 *buffer_address++ = 0x06;
4820 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4821 *buffer_address++ = (char) 0xff;
4822
4823 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4824 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
4825 RELAX_RELOC_PC32);
4826 fragP->fr_fix += 4;
4827 break;
4828 case TAB (DBCCABSJ, LONG):
4829 /* Only DBcc instructions can come here.
4830 Change dbcc into dbcc/jmp.
4831 JF: these used to be fr_opcode[2-7], but that's wrong. */
4832 if (flag_keep_pcrel)
4833 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4834
4835 *buffer_address++ = 0x00; /* Branch offset = 4. */
4836 *buffer_address++ = 0x04;
4837 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
4838 *buffer_address++ = 0x06;
4839 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4840 *buffer_address++ = (char) 0xf9;
4841
4842 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4843 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
4844 RELAX_RELOC_ABS32);
4845 fragP->fr_fix += 4;
4846 break;
4847 case TAB (PCREL1632, SHORT):
4848 fragP->fr_opcode[1] &= ~0x3F;
4849 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4850 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4851 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4852 fragP->fr_fix += 2;
4853 break;
4854 case TAB (PCREL1632, LONG):
4855 /* Already set to mode 7.3; this indicates: PC indirect with
4856 suppressed index, 32-bit displacement. */
4857 *buffer_address++ = 0x01;
4858 *buffer_address++ = 0x70;
4859 fragP->fr_fix += 2;
4860 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4861 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4862 fixP->fx_pcrel_adjust = 2;
4863 fragP->fr_fix += 4;
4864 break;
4865 case TAB (PCINDEX, BYTE):
4866 assert (fragP->fr_fix >= 2);
4867 buffer_address[-2] &= ~1;
4868 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4869 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4870 fixP->fx_pcrel_adjust = 1;
4871 break;
4872 case TAB (PCINDEX, SHORT):
4873 assert (fragP->fr_fix >= 2);
4874 buffer_address[-2] |= 0x1;
4875 buffer_address[-1] = 0x20;
4876 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4877 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4878 fixP->fx_pcrel_adjust = 2;
4879 fragP->fr_fix += 2;
4880 break;
4881 case TAB (PCINDEX, LONG):
4882 assert (fragP->fr_fix >= 2);
4883 buffer_address[-2] |= 0x1;
4884 buffer_address[-1] = 0x30;
4885 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4886 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4887 fixP->fx_pcrel_adjust = 2;
4888 fragP->fr_fix += 4;
4889 break;
4890 case TAB (ABSTOPCREL, SHORT):
4891 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4892 1, RELAX_RELOC_PC16);
4893 fragP->fr_fix += 2;
4894 break;
4895 case TAB (ABSTOPCREL, LONG):
4896 if (flag_keep_pcrel)
4897 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4898 /* The thing to do here is force it to ABSOLUTE LONG, since
4899 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
4900 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4901 abort ();
4902 fragP->fr_opcode[1] &= ~0x3F;
4903 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4904 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4905 0, RELAX_RELOC_ABS32);
4906 fragP->fr_fix += 4;
4907 break;
4908 }
4909 }
4910
4911 void
4912 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
4913 segT sec ATTRIBUTE_UNUSED,
4914 fragS *fragP)
4915 {
4916 md_convert_frag_1 (fragP);
4917 }
4918
4919 /* Force truly undefined symbols to their maximum size, and generally set up
4920 the frag list to be relaxed
4921 */
4922 int
4923 md_estimate_size_before_relax (fragS *fragP, segT segment)
4924 {
4925 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4926 switch (fragP->fr_subtype)
4927 {
4928 case TAB (BRANCHBWL, SZ_UNDEF):
4929 case TAB (BRABSJUNC, SZ_UNDEF):
4930 case TAB (BRABSJCOND, SZ_UNDEF):
4931 {
4932 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4933 && relaxable_symbol (fragP->fr_symbol))
4934 {
4935 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4936 }
4937 else if (flag_short_refs)
4938 {
4939 /* Symbol is undefined and we want short ref. */
4940 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4941 }
4942 else
4943 {
4944 /* Symbol is still undefined. Make it LONG. */
4945 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4946 }
4947 break;
4948 }
4949
4950 case TAB (BRANCHBW, SZ_UNDEF):
4951 {
4952 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4953 && relaxable_symbol (fragP->fr_symbol))
4954 {
4955 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4956 }
4957 else
4958 {
4959 /* Symbol is undefined and we don't have long branches. */
4960 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4961 }
4962 break;
4963 }
4964
4965 case TAB (FBRANCH, SZ_UNDEF):
4966 case TAB (DBCCLBR, SZ_UNDEF):
4967 case TAB (DBCCABSJ, SZ_UNDEF):
4968 case TAB (PCREL1632, SZ_UNDEF):
4969 {
4970 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4971 && relaxable_symbol (fragP->fr_symbol))
4972 || flag_short_refs)
4973 {
4974 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4975 }
4976 else
4977 {
4978 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4979 }
4980 break;
4981 }
4982
4983 case TAB (PCINDEX, SZ_UNDEF):
4984 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4985 && relaxable_symbol (fragP->fr_symbol)))
4986 {
4987 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4988 }
4989 else
4990 {
4991 fragP->fr_subtype = TAB (PCINDEX, LONG);
4992 }
4993 break;
4994
4995 case TAB (ABSTOPCREL, SZ_UNDEF):
4996 {
4997 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4998 && relaxable_symbol (fragP->fr_symbol)))
4999 {
5000 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5001 }
5002 else
5003 {
5004 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5005 }
5006 break;
5007 }
5008
5009 default:
5010 break;
5011 }
5012
5013 /* Now that SZ_UNDEF are taken care of, check others. */
5014 switch (fragP->fr_subtype)
5015 {
5016 case TAB (BRANCHBWL, BYTE):
5017 case TAB (BRABSJUNC, BYTE):
5018 case TAB (BRABSJCOND, BYTE):
5019 case TAB (BRANCHBW, BYTE):
5020 /* We can't do a short jump to the next instruction, so in that
5021 case we force word mode. If the symbol is at the start of a
5022 frag, and it is the next frag with any data in it (usually
5023 this is just the next frag, but assembler listings may
5024 introduce empty frags), we must use word mode. */
5025 if (fragP->fr_symbol)
5026 {
5027 fragS *sym_frag;
5028
5029 sym_frag = symbol_get_frag (fragP->fr_symbol);
5030 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5031 {
5032 fragS *l;
5033
5034 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5035 if (l->fr_fix != 0)
5036 break;
5037 if (l == sym_frag)
5038 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5039 }
5040 }
5041 break;
5042 default:
5043 break;
5044 }
5045 return md_relax_table[fragP->fr_subtype].rlx_length;
5046 }
5047
5048 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5049 /* the bit-field entries in the relocation_info struct plays hell
5050 with the byte-order problems of cross-assembly. So as a hack,
5051 I added this mach. dependent ri twiddler. Ugly, but it gets
5052 you there. -KWK */
5053 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5054 are symbolnum, most sig. byte first. Last byte is broken up with
5055 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5056 nibble as nuthin. (on Sun 3 at least) */
5057 /* Translate the internal relocation information into target-specific
5058 format. */
5059 #ifdef comment
5060 void
5061 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
5062 {
5063 /* This is easy. */
5064 md_number_to_chars (the_bytes, ri->r_address, 4);
5065 /* Now the fun stuff. */
5066 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5067 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5068 the_bytes[6] = ri->r_symbolnum & 0x0ff;
5069 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5070 | ((ri->r_length << 5) & 0x60)
5071 | ((ri->r_extern << 4) & 0x10));
5072 }
5073
5074 #endif
5075
5076 #endif /* OBJ_AOUT or OBJ_BOUT */
5077
5078 #ifndef WORKING_DOT_WORD
5079 int md_short_jump_size = 4;
5080 int md_long_jump_size = 6;
5081
5082 void
5083 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5084 fragS *frag ATTRIBUTE_UNUSED,
5085 symbolS *to_symbol ATTRIBUTE_UNUSED)
5086 {
5087 valueT offset;
5088
5089 offset = to_addr - (from_addr + 2);
5090
5091 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5092 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5093 }
5094
5095 void
5096 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5097 fragS *frag, symbolS *to_symbol)
5098 {
5099 valueT offset;
5100
5101 if (!HAVE_LONG_BRANCH (current_architecture))
5102 {
5103 if (flag_keep_pcrel)
5104 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5105 offset = to_addr - S_GET_VALUE (to_symbol);
5106 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5107 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5108 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5109 0, NO_RELOC);
5110 }
5111 else
5112 {
5113 offset = to_addr - (from_addr + 2);
5114 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5115 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5116 }
5117 }
5118
5119 #endif
5120
5121 /* Different values of OK tell what its OK to return. Things that
5122 aren't OK are an error (what a shock, no?)
5123
5124 0: Everything is OK
5125 10: Absolute 1:8 only
5126 20: Absolute 0:7 only
5127 30: absolute 0:15 only
5128 40: Absolute 0:31 only
5129 50: absolute 0:127 only
5130 55: absolute -64:63 only
5131 60: absolute -128:127 only
5132 70: absolute 0:4095 only
5133 80: absolute -1, 1:7 only
5134 90: No bignums. */
5135
5136 static int
5137 get_num (struct m68k_exp *exp, int ok)
5138 {
5139 if (exp->exp.X_op == O_absent)
5140 {
5141 /* Do the same thing the VAX asm does. */
5142 op (exp) = O_constant;
5143 adds (exp) = 0;
5144 subs (exp) = 0;
5145 offs (exp) = 0;
5146 if (ok == 10)
5147 {
5148 as_warn (_("expression out of range: defaulting to 1"));
5149 offs (exp) = 1;
5150 }
5151 }
5152 else if (exp->exp.X_op == O_constant)
5153 {
5154 switch (ok)
5155 {
5156 case 10:
5157 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5158 {
5159 as_warn (_("expression out of range: defaulting to 1"));
5160 offs (exp) = 1;
5161 }
5162 break;
5163 case 20:
5164 if ((valueT) TRUNC (offs (exp)) > 7)
5165 goto outrange;
5166 break;
5167 case 30:
5168 if ((valueT) TRUNC (offs (exp)) > 15)
5169 goto outrange;
5170 break;
5171 case 40:
5172 if ((valueT) TRUNC (offs (exp)) > 32)
5173 goto outrange;
5174 break;
5175 case 50:
5176 if ((valueT) TRUNC (offs (exp)) > 127)
5177 goto outrange;
5178 break;
5179 case 55:
5180 if ((valueT) SEXT (offs (exp)) + 64 > 127)
5181 goto outrange;
5182 break;
5183 case 60:
5184 if ((valueT) SEXT (offs (exp)) + 128 > 255)
5185 goto outrange;
5186 break;
5187 case 70:
5188 if ((valueT) TRUNC (offs (exp)) > 4095)
5189 {
5190 outrange:
5191 as_warn (_("expression out of range: defaulting to 0"));
5192 offs (exp) = 0;
5193 }
5194 break;
5195 case 80:
5196 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5197 && (valueT) TRUNC (offs (exp)) - 1 > 6)
5198 {
5199 as_warn (_("expression out of range: defaulting to 1"));
5200 offs (exp) = 1;
5201 }
5202 break;
5203 default:
5204 break;
5205 }
5206 }
5207 else if (exp->exp.X_op == O_big)
5208 {
5209 if (offs (exp) <= 0 /* flonum. */
5210 && (ok == 90 /* no bignums */
5211 || (ok > 10 /* Small-int ranges including 0 ok. */
5212 /* If we have a flonum zero, a zero integer should
5213 do as well (e.g., in moveq). */
5214 && generic_floating_point_number.exponent == 0
5215 && generic_floating_point_number.low[0] == 0)))
5216 {
5217 /* HACK! Turn it into a long. */
5218 LITTLENUM_TYPE words[6];
5219
5220 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5221 op (exp) = O_constant;
5222 adds (exp) = 0;
5223 subs (exp) = 0;
5224 offs (exp) = words[1] | (words[0] << 16);
5225 }
5226 else if (ok != 0)
5227 {
5228 op (exp) = O_constant;
5229 adds (exp) = 0;
5230 subs (exp) = 0;
5231 offs (exp) = (ok == 10) ? 1 : 0;
5232 as_warn (_("Can't deal with expression; defaulting to %ld"),
5233 (long) offs (exp));
5234 }
5235 }
5236 else
5237 {
5238 if (ok >= 10 && ok <= 80)
5239 {
5240 op (exp) = O_constant;
5241 adds (exp) = 0;
5242 subs (exp) = 0;
5243 offs (exp) = (ok == 10) ? 1 : 0;
5244 as_warn (_("Can't deal with expression; defaulting to %ld"),
5245 (long) offs (exp));
5246 }
5247 }
5248
5249 if (exp->size != SIZE_UNSPEC)
5250 {
5251 switch (exp->size)
5252 {
5253 case SIZE_UNSPEC:
5254 case SIZE_LONG:
5255 break;
5256 case SIZE_BYTE:
5257 if (!isbyte (offs (exp)))
5258 as_warn (_("expression doesn't fit in BYTE"));
5259 break;
5260 case SIZE_WORD:
5261 if (!isword (offs (exp)))
5262 as_warn (_("expression doesn't fit in WORD"));
5263 break;
5264 }
5265 }
5266
5267 return offs (exp);
5268 }
5269
5270 /* These are the back-ends for the various machine dependent pseudo-ops. */
5271
5272 static void
5273 s_data1 (int ignore ATTRIBUTE_UNUSED)
5274 {
5275 subseg_set (data_section, 1);
5276 demand_empty_rest_of_line ();
5277 }
5278
5279 static void
5280 s_data2 (int ignore ATTRIBUTE_UNUSED)
5281 {
5282 subseg_set (data_section, 2);
5283 demand_empty_rest_of_line ();
5284 }
5285
5286 static void
5287 s_bss (int ignore ATTRIBUTE_UNUSED)
5288 {
5289 /* We don't support putting frags in the BSS segment, we fake it
5290 by marking in_bss, then looking at s_skip for clues. */
5291
5292 subseg_set (bss_section, 0);
5293 demand_empty_rest_of_line ();
5294 }
5295
5296 static void
5297 s_even (int ignore ATTRIBUTE_UNUSED)
5298 {
5299 register int temp;
5300 register long temp_fill;
5301
5302 temp = 1; /* JF should be 2? */
5303 temp_fill = get_absolute_expression ();
5304 if (!need_pass_2) /* Never make frag if expect extra pass. */
5305 frag_align (temp, (int) temp_fill, 0);
5306 demand_empty_rest_of_line ();
5307 record_alignment (now_seg, temp);
5308 }
5309
5310 static void
5311 s_proc (int ignore ATTRIBUTE_UNUSED)
5312 {
5313 demand_empty_rest_of_line ();
5314 }
5315 \f
5316 /* Pseudo-ops handled for MRI compatibility. */
5317
5318 /* This function returns non-zero if the argument is a conditional
5319 pseudo-op. This is called when checking whether a pending
5320 alignment is needed. */
5321
5322 int
5323 m68k_conditional_pseudoop (pseudo_typeS *pop)
5324 {
5325 return (pop->poc_handler == s_mri_if
5326 || pop->poc_handler == s_mri_else);
5327 }
5328
5329 /* Handle an MRI style chip specification. */
5330
5331 static void
5332 mri_chip (void)
5333 {
5334 char *s;
5335 char c;
5336 int i;
5337
5338 s = input_line_pointer;
5339 /* We can't use get_symbol_end since the processor names are not proper
5340 symbols. */
5341 while (is_part_of_name (c = *input_line_pointer++))
5342 ;
5343 *--input_line_pointer = 0;
5344 for (i = 0; m68k_cpus[i].name; i++)
5345 if (strcasecmp (s, m68k_cpus[i].name) == 0)
5346 break;
5347 if (!m68k_cpus[i].name)
5348 {
5349 as_bad (_("%s: unrecognized processor name"), s);
5350 *input_line_pointer = c;
5351 ignore_rest_of_line ();
5352 return;
5353 }
5354 *input_line_pointer = c;
5355
5356 if (*input_line_pointer == '/')
5357 current_architecture = 0;
5358 else
5359 current_architecture &= m68881 | m68851;
5360 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5361 current_chip = m68k_cpus[i].chip;
5362
5363 while (*input_line_pointer == '/')
5364 {
5365 ++input_line_pointer;
5366 s = input_line_pointer;
5367 /* We can't use get_symbol_end since the processor names are not
5368 proper symbols. */
5369 while (is_part_of_name (c = *input_line_pointer++))
5370 ;
5371 *--input_line_pointer = 0;
5372 if (strcmp (s, "68881") == 0)
5373 current_architecture |= m68881;
5374 else if (strcmp (s, "68851") == 0)
5375 current_architecture |= m68851;
5376 *input_line_pointer = c;
5377 }
5378
5379 /* Update info about available control registers. */
5380 select_control_regs ();
5381 }
5382
5383 /* The MRI CHIP pseudo-op. */
5384
5385 static void
5386 s_chip (int ignore ATTRIBUTE_UNUSED)
5387 {
5388 char *stop = NULL;
5389 char stopc;
5390
5391 if (flag_mri)
5392 stop = mri_comment_field (&stopc);
5393 mri_chip ();
5394 if (flag_mri)
5395 mri_comment_end (stop, stopc);
5396 demand_empty_rest_of_line ();
5397 }
5398
5399 /* The MRI FOPT pseudo-op. */
5400
5401 static void
5402 s_fopt (int ignore ATTRIBUTE_UNUSED)
5403 {
5404 SKIP_WHITESPACE ();
5405
5406 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5407 {
5408 int temp;
5409
5410 input_line_pointer += 3;
5411 temp = get_absolute_expression ();
5412 if (temp < 0 || temp > 7)
5413 as_bad (_("bad coprocessor id"));
5414 else
5415 m68k_float_copnum = COP0 + temp;
5416 }
5417 else
5418 {
5419 as_bad (_("unrecognized fopt option"));
5420 ignore_rest_of_line ();
5421 return;
5422 }
5423
5424 demand_empty_rest_of_line ();
5425 }
5426
5427 /* The structure used to handle the MRI OPT pseudo-op. */
5428
5429 struct opt_action
5430 {
5431 /* The name of the option. */
5432 const char *name;
5433
5434 /* If this is not NULL, just call this function. The first argument
5435 is the ARG field of this structure, the second argument is
5436 whether the option was negated. */
5437 void (*pfn) (int arg, int on);
5438
5439 /* If this is not NULL, and the PFN field is NULL, set the variable
5440 this points to. Set it to the ARG field if the option was not
5441 negated, and the NOTARG field otherwise. */
5442 int *pvar;
5443
5444 /* The value to pass to PFN or to assign to *PVAR. */
5445 int arg;
5446
5447 /* The value to assign to *PVAR if the option is negated. If PFN is
5448 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5449 the option may not be negated. */
5450 int notarg;
5451 };
5452
5453 /* The table used to handle the MRI OPT pseudo-op. */
5454
5455 static void skip_to_comma (int, int);
5456 static void opt_nest (int, int);
5457 static void opt_chip (int, int);
5458 static void opt_list (int, int);
5459 static void opt_list_symbols (int, int);
5460
5461 static const struct opt_action opt_table[] =
5462 {
5463 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5464
5465 /* We do relaxing, so there is little use for these options. */
5466 { "b", 0, 0, 0, 0 },
5467 { "brs", 0, 0, 0, 0 },
5468 { "brb", 0, 0, 0, 0 },
5469 { "brl", 0, 0, 0, 0 },
5470 { "brw", 0, 0, 0, 0 },
5471
5472 { "c", 0, 0, 0, 0 },
5473 { "cex", 0, 0, 0, 0 },
5474 { "case", 0, &symbols_case_sensitive, 1, 0 },
5475 { "cl", 0, 0, 0, 0 },
5476 { "cre", 0, 0, 0, 0 },
5477 { "d", 0, &flag_keep_locals, 1, 0 },
5478 { "e", 0, 0, 0, 0 },
5479 { "f", 0, &flag_short_refs, 1, 0 },
5480 { "frs", 0, &flag_short_refs, 1, 0 },
5481 { "frl", 0, &flag_short_refs, 0, 1 },
5482 { "g", 0, 0, 0, 0 },
5483 { "i", 0, 0, 0, 0 },
5484 { "m", 0, 0, 0, 0 },
5485 { "mex", 0, 0, 0, 0 },
5486 { "mc", 0, 0, 0, 0 },
5487 { "md", 0, 0, 0, 0 },
5488 { "nest", opt_nest, 0, 0, 0 },
5489 { "next", skip_to_comma, 0, 0, 0 },
5490 { "o", 0, 0, 0, 0 },
5491 { "old", 0, 0, 0, 0 },
5492 { "op", skip_to_comma, 0, 0, 0 },
5493 { "pco", 0, 0, 0, 0 },
5494 { "p", opt_chip, 0, 0, 0 },
5495 { "pcr", 0, 0, 0, 0 },
5496 { "pcs", 0, 0, 0, 0 },
5497 { "r", 0, 0, 0, 0 },
5498 { "quick", 0, &m68k_quick, 1, 0 },
5499 { "rel32", 0, &m68k_rel32, 1, 0 },
5500 { "s", opt_list, 0, 0, 0 },
5501 { "t", opt_list_symbols, 0, 0, 0 },
5502 { "w", 0, &flag_no_warnings, 0, 1 },
5503 { "x", 0, 0, 0, 0 }
5504 };
5505
5506 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5507
5508 /* The MRI OPT pseudo-op. */
5509
5510 static void
5511 s_opt (int ignore ATTRIBUTE_UNUSED)
5512 {
5513 do
5514 {
5515 int t;
5516 char *s;
5517 char c;
5518 int i;
5519 const struct opt_action *o;
5520
5521 SKIP_WHITESPACE ();
5522
5523 t = 1;
5524 if (*input_line_pointer == '-')
5525 {
5526 ++input_line_pointer;
5527 t = 0;
5528 }
5529 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5530 {
5531 input_line_pointer += 2;
5532 t = 0;
5533 }
5534
5535 s = input_line_pointer;
5536 c = get_symbol_end ();
5537
5538 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5539 {
5540 if (strcasecmp (s, o->name) == 0)
5541 {
5542 if (o->pfn)
5543 {
5544 /* Restore input_line_pointer now in case the option
5545 takes arguments. */
5546 *input_line_pointer = c;
5547 (*o->pfn) (o->arg, t);
5548 }
5549 else if (o->pvar != NULL)
5550 {
5551 if (! t && o->arg == o->notarg)
5552 as_bad (_("option `%s' may not be negated"), s);
5553 *input_line_pointer = c;
5554 *o->pvar = t ? o->arg : o->notarg;
5555 }
5556 else
5557 *input_line_pointer = c;
5558 break;
5559 }
5560 }
5561 if (i >= OPTCOUNT)
5562 {
5563 as_bad (_("option `%s' not recognized"), s);
5564 *input_line_pointer = c;
5565 }
5566 }
5567 while (*input_line_pointer++ == ',');
5568
5569 /* Move back to terminating character. */
5570 --input_line_pointer;
5571 demand_empty_rest_of_line ();
5572 }
5573
5574 /* Skip ahead to a comma. This is used for OPT options which we do
5575 not support and which take arguments. */
5576
5577 static void
5578 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5579 {
5580 while (*input_line_pointer != ','
5581 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5582 ++input_line_pointer;
5583 }
5584
5585 /* Handle the OPT NEST=depth option. */
5586
5587 static void
5588 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5589 {
5590 if (*input_line_pointer != '=')
5591 {
5592 as_bad (_("bad format of OPT NEST=depth"));
5593 return;
5594 }
5595
5596 ++input_line_pointer;
5597 max_macro_nest = get_absolute_expression ();
5598 }
5599
5600 /* Handle the OPT P=chip option. */
5601
5602 static void
5603 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5604 {
5605 if (*input_line_pointer != '=')
5606 {
5607 /* This is just OPT P, which we do not support. */
5608 return;
5609 }
5610
5611 ++input_line_pointer;
5612 mri_chip ();
5613 }
5614
5615 /* Handle the OPT S option. */
5616
5617 static void
5618 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5619 {
5620 listing_list (on);
5621 }
5622
5623 /* Handle the OPT T option. */
5624
5625 static void
5626 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5627 {
5628 if (on)
5629 listing |= LISTING_SYMBOLS;
5630 else
5631 listing &= ~LISTING_SYMBOLS;
5632 }
5633
5634 /* Handle the MRI REG pseudo-op. */
5635
5636 static void
5637 s_reg (int ignore ATTRIBUTE_UNUSED)
5638 {
5639 char *s;
5640 int c;
5641 struct m68k_op rop;
5642 int mask;
5643 char *stop = NULL;
5644 char stopc;
5645
5646 if (line_label == NULL)
5647 {
5648 as_bad (_("missing label"));
5649 ignore_rest_of_line ();
5650 return;
5651 }
5652
5653 if (flag_mri)
5654 stop = mri_comment_field (&stopc);
5655
5656 SKIP_WHITESPACE ();
5657
5658 s = input_line_pointer;
5659 while (ISALNUM (*input_line_pointer)
5660 #ifdef REGISTER_PREFIX
5661 || *input_line_pointer == REGISTER_PREFIX
5662 #endif
5663 || *input_line_pointer == '/'
5664 || *input_line_pointer == '-')
5665 ++input_line_pointer;
5666 c = *input_line_pointer;
5667 *input_line_pointer = '\0';
5668
5669 if (m68k_ip_op (s, &rop) != 0)
5670 {
5671 if (rop.error == NULL)
5672 as_bad (_("bad register list"));
5673 else
5674 as_bad (_("bad register list: %s"), rop.error);
5675 *input_line_pointer = c;
5676 ignore_rest_of_line ();
5677 return;
5678 }
5679
5680 *input_line_pointer = c;
5681
5682 if (rop.mode == REGLST)
5683 mask = rop.mask;
5684 else if (rop.mode == DREG)
5685 mask = 1 << (rop.reg - DATA0);
5686 else if (rop.mode == AREG)
5687 mask = 1 << (rop.reg - ADDR0 + 8);
5688 else if (rop.mode == FPREG)
5689 mask = 1 << (rop.reg - FP0 + 16);
5690 else if (rop.mode == CONTROL
5691 && rop.reg == FPI)
5692 mask = 1 << 24;
5693 else if (rop.mode == CONTROL
5694 && rop.reg == FPS)
5695 mask = 1 << 25;
5696 else if (rop.mode == CONTROL
5697 && rop.reg == FPC)
5698 mask = 1 << 26;
5699 else
5700 {
5701 as_bad (_("bad register list"));
5702 ignore_rest_of_line ();
5703 return;
5704 }
5705
5706 S_SET_SEGMENT (line_label, reg_section);
5707 S_SET_VALUE (line_label, ~mask);
5708 symbol_set_frag (line_label, &zero_address_frag);
5709
5710 if (flag_mri)
5711 mri_comment_end (stop, stopc);
5712
5713 demand_empty_rest_of_line ();
5714 }
5715
5716 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5717
5718 struct save_opts
5719 {
5720 struct save_opts *next;
5721 int abspcadd;
5722 int symbols_case_sensitive;
5723 int keep_locals;
5724 int short_refs;
5725 int architecture;
5726 int chip;
5727 int quick;
5728 int rel32;
5729 int listing;
5730 int no_warnings;
5731 /* FIXME: We don't save OPT S. */
5732 };
5733
5734 /* This variable holds the stack of saved options. */
5735
5736 static struct save_opts *save_stack;
5737
5738 /* The MRI SAVE pseudo-op. */
5739
5740 static void
5741 s_save (int ignore ATTRIBUTE_UNUSED)
5742 {
5743 struct save_opts *s;
5744
5745 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5746 s->abspcadd = m68k_abspcadd;
5747 s->symbols_case_sensitive = symbols_case_sensitive;
5748 s->keep_locals = flag_keep_locals;
5749 s->short_refs = flag_short_refs;
5750 s->architecture = current_architecture;
5751 s->chip = current_chip;
5752 s->quick = m68k_quick;
5753 s->rel32 = m68k_rel32;
5754 s->listing = listing;
5755 s->no_warnings = flag_no_warnings;
5756
5757 s->next = save_stack;
5758 save_stack = s;
5759
5760 demand_empty_rest_of_line ();
5761 }
5762
5763 /* The MRI RESTORE pseudo-op. */
5764
5765 static void
5766 s_restore (int ignore ATTRIBUTE_UNUSED)
5767 {
5768 struct save_opts *s;
5769
5770 if (save_stack == NULL)
5771 {
5772 as_bad (_("restore without save"));
5773 ignore_rest_of_line ();
5774 return;
5775 }
5776
5777 s = save_stack;
5778 save_stack = s->next;
5779
5780 m68k_abspcadd = s->abspcadd;
5781 symbols_case_sensitive = s->symbols_case_sensitive;
5782 flag_keep_locals = s->keep_locals;
5783 flag_short_refs = s->short_refs;
5784 current_architecture = s->architecture;
5785 current_chip = s->chip;
5786 m68k_quick = s->quick;
5787 m68k_rel32 = s->rel32;
5788 listing = s->listing;
5789 flag_no_warnings = s->no_warnings;
5790
5791 free (s);
5792
5793 demand_empty_rest_of_line ();
5794 }
5795
5796 /* Types of MRI structured control directives. */
5797
5798 enum mri_control_type
5799 {
5800 mri_for,
5801 mri_if,
5802 mri_repeat,
5803 mri_while
5804 };
5805
5806 /* This structure is used to stack the MRI structured control
5807 directives. */
5808
5809 struct mri_control_info
5810 {
5811 /* The directive within which this one is enclosed. */
5812 struct mri_control_info *outer;
5813
5814 /* The type of directive. */
5815 enum mri_control_type type;
5816
5817 /* Whether an ELSE has been in an IF. */
5818 int else_seen;
5819
5820 /* The add or sub statement at the end of a FOR. */
5821 char *incr;
5822
5823 /* The label of the top of a FOR or REPEAT loop. */
5824 char *top;
5825
5826 /* The label to jump to for the next iteration, or the else
5827 expression of a conditional. */
5828 char *next;
5829
5830 /* The label to jump to to break out of the loop, or the label past
5831 the end of a conditional. */
5832 char *bottom;
5833 };
5834
5835 /* The stack of MRI structured control directives. */
5836
5837 static struct mri_control_info *mri_control_stack;
5838
5839 /* The current MRI structured control directive index number, used to
5840 generate label names. */
5841
5842 static int mri_control_index;
5843
5844 /* Assemble an instruction for an MRI structured control directive. */
5845
5846 static void
5847 mri_assemble (char *str)
5848 {
5849 char *s;
5850
5851 /* md_assemble expects the opcode to be in lower case. */
5852 for (s = str; *s != ' ' && *s != '\0'; s++)
5853 *s = TOLOWER (*s);
5854
5855 md_assemble (str);
5856 }
5857
5858 /* Generate a new MRI label structured control directive label name. */
5859
5860 static char *
5861 mri_control_label (void)
5862 {
5863 char *n;
5864
5865 n = (char *) xmalloc (20);
5866 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5867 ++mri_control_index;
5868 return n;
5869 }
5870
5871 /* Create a new MRI structured control directive. */
5872
5873 static struct mri_control_info *
5874 push_mri_control (enum mri_control_type type)
5875 {
5876 struct mri_control_info *n;
5877
5878 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5879
5880 n->type = type;
5881 n->else_seen = 0;
5882 if (type == mri_if || type == mri_while)
5883 n->top = NULL;
5884 else
5885 n->top = mri_control_label ();
5886 n->next = mri_control_label ();
5887 n->bottom = mri_control_label ();
5888
5889 n->outer = mri_control_stack;
5890 mri_control_stack = n;
5891
5892 return n;
5893 }
5894
5895 /* Pop off the stack of MRI structured control directives. */
5896
5897 static void
5898 pop_mri_control (void)
5899 {
5900 struct mri_control_info *n;
5901
5902 n = mri_control_stack;
5903 mri_control_stack = n->outer;
5904 if (n->top != NULL)
5905 free (n->top);
5906 free (n->next);
5907 free (n->bottom);
5908 free (n);
5909 }
5910
5911 /* Recognize a condition code in an MRI structured control expression. */
5912
5913 static int
5914 parse_mri_condition (int *pcc)
5915 {
5916 char c1, c2;
5917
5918 know (*input_line_pointer == '<');
5919
5920 ++input_line_pointer;
5921 c1 = *input_line_pointer++;
5922 c2 = *input_line_pointer++;
5923
5924 if (*input_line_pointer != '>')
5925 {
5926 as_bad (_("syntax error in structured control directive"));
5927 return 0;
5928 }
5929
5930 ++input_line_pointer;
5931 SKIP_WHITESPACE ();
5932
5933 c1 = TOLOWER (c1);
5934 c2 = TOLOWER (c2);
5935
5936 *pcc = (c1 << 8) | c2;
5937
5938 return 1;
5939 }
5940
5941 /* Parse a single operand in an MRI structured control expression. */
5942
5943 static int
5944 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
5945 char **rightstart, char **rightstop)
5946 {
5947 char *s;
5948
5949 SKIP_WHITESPACE ();
5950
5951 *pcc = -1;
5952 *leftstart = NULL;
5953 *leftstop = NULL;
5954 *rightstart = NULL;
5955 *rightstop = NULL;
5956
5957 if (*input_line_pointer == '<')
5958 {
5959 /* It's just a condition code. */
5960 return parse_mri_condition (pcc);
5961 }
5962
5963 /* Look ahead for the condition code. */
5964 for (s = input_line_pointer; *s != '\0'; ++s)
5965 {
5966 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5967 break;
5968 }
5969 if (*s == '\0')
5970 {
5971 as_bad (_("missing condition code in structured control directive"));
5972 return 0;
5973 }
5974
5975 *leftstart = input_line_pointer;
5976 *leftstop = s;
5977 if (*leftstop > *leftstart
5978 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5979 --*leftstop;
5980
5981 input_line_pointer = s;
5982 if (! parse_mri_condition (pcc))
5983 return 0;
5984
5985 /* Look ahead for AND or OR or end of line. */
5986 for (s = input_line_pointer; *s != '\0'; ++s)
5987 {
5988 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5989 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5990 ^^^ ^^ */
5991 if ((s == input_line_pointer
5992 || *(s-1) == ' '
5993 || *(s-1) == '\t')
5994 && ((strncasecmp (s, "AND", 3) == 0
5995 && (s[3] == '.' || ! is_part_of_name (s[3])))
5996 || (strncasecmp (s, "OR", 2) == 0
5997 && (s[2] == '.' || ! is_part_of_name (s[2])))))
5998 break;
5999 }
6000
6001 *rightstart = input_line_pointer;
6002 *rightstop = s;
6003 if (*rightstop > *rightstart
6004 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6005 --*rightstop;
6006
6007 input_line_pointer = s;
6008
6009 return 1;
6010 }
6011
6012 #define MCC(b1, b2) (((b1) << 8) | (b2))
6013
6014 /* Swap the sense of a condition. This changes the condition so that
6015 it generates the same result when the operands are swapped. */
6016
6017 static int
6018 swap_mri_condition (int cc)
6019 {
6020 switch (cc)
6021 {
6022 case MCC ('h', 'i'): return MCC ('c', 's');
6023 case MCC ('l', 's'): return MCC ('c', 'c');
6024 /* <HS> is an alias for <CC>. */
6025 case MCC ('h', 's'):
6026 case MCC ('c', 'c'): return MCC ('l', 's');
6027 /* <LO> is an alias for <CS>. */
6028 case MCC ('l', 'o'):
6029 case MCC ('c', 's'): return MCC ('h', 'i');
6030 case MCC ('p', 'l'): return MCC ('m', 'i');
6031 case MCC ('m', 'i'): return MCC ('p', 'l');
6032 case MCC ('g', 'e'): return MCC ('l', 'e');
6033 case MCC ('l', 't'): return MCC ('g', 't');
6034 case MCC ('g', 't'): return MCC ('l', 't');
6035 case MCC ('l', 'e'): return MCC ('g', 'e');
6036 /* Issue a warning for conditions we can not swap. */
6037 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6038 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6039 case MCC ('v', 'c'):
6040 case MCC ('v', 's'):
6041 default :
6042 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6043 (char) (cc >> 8), (char) (cc));
6044 break;
6045 }
6046 return cc;
6047 }
6048
6049 /* Reverse the sense of a condition. */
6050
6051 static int
6052 reverse_mri_condition (int cc)
6053 {
6054 switch (cc)
6055 {
6056 case MCC ('h', 'i'): return MCC ('l', 's');
6057 case MCC ('l', 's'): return MCC ('h', 'i');
6058 /* <HS> is an alias for <CC> */
6059 case MCC ('h', 's'): return MCC ('l', 'o');
6060 case MCC ('c', 'c'): return MCC ('c', 's');
6061 /* <LO> is an alias for <CS> */
6062 case MCC ('l', 'o'): return MCC ('h', 's');
6063 case MCC ('c', 's'): return MCC ('c', 'c');
6064 case MCC ('n', 'e'): return MCC ('e', 'q');
6065 case MCC ('e', 'q'): return MCC ('n', 'e');
6066 case MCC ('v', 'c'): return MCC ('v', 's');
6067 case MCC ('v', 's'): return MCC ('v', 'c');
6068 case MCC ('p', 'l'): return MCC ('m', 'i');
6069 case MCC ('m', 'i'): return MCC ('p', 'l');
6070 case MCC ('g', 'e'): return MCC ('l', 't');
6071 case MCC ('l', 't'): return MCC ('g', 'e');
6072 case MCC ('g', 't'): return MCC ('l', 'e');
6073 case MCC ('l', 'e'): return MCC ('g', 't');
6074 }
6075 return cc;
6076 }
6077
6078 /* Build an MRI structured control expression. This generates test
6079 and branch instructions. It goes to TRUELAB if the condition is
6080 true, and to FALSELAB if the condition is false. Exactly one of
6081 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6082 is the size qualifier for the expression. EXTENT is the size to
6083 use for the branch. */
6084
6085 static void
6086 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6087 char *rightstart, char *rightstop,
6088 const char *truelab, const char *falselab,
6089 int extent)
6090 {
6091 char *buf;
6092 char *s;
6093
6094 if (leftstart != NULL)
6095 {
6096 struct m68k_op leftop, rightop;
6097 char c;
6098
6099 /* Swap the compare operands, if necessary, to produce a legal
6100 m68k compare instruction. Comparing a register operand with
6101 a non-register operand requires the register to be on the
6102 right (cmp, cmpa). Comparing an immediate value with
6103 anything requires the immediate value to be on the left
6104 (cmpi). */
6105
6106 c = *leftstop;
6107 *leftstop = '\0';
6108 (void) m68k_ip_op (leftstart, &leftop);
6109 *leftstop = c;
6110
6111 c = *rightstop;
6112 *rightstop = '\0';
6113 (void) m68k_ip_op (rightstart, &rightop);
6114 *rightstop = c;
6115
6116 if (rightop.mode == IMMED
6117 || ((leftop.mode == DREG || leftop.mode == AREG)
6118 && (rightop.mode != DREG && rightop.mode != AREG)))
6119 {
6120 char *temp;
6121
6122 /* Correct conditional handling:
6123 if #1 <lt> d0 then ;means if (1 < d0)
6124 ...
6125 endi
6126
6127 should assemble to:
6128
6129 cmp #1,d0 if we do *not* swap the operands
6130 bgt true we need the swapped condition!
6131 ble false
6132 true:
6133 ...
6134 false:
6135 */
6136 temp = leftstart;
6137 leftstart = rightstart;
6138 rightstart = temp;
6139 temp = leftstop;
6140 leftstop = rightstop;
6141 rightstop = temp;
6142 }
6143 else
6144 {
6145 cc = swap_mri_condition (cc);
6146 }
6147 }
6148
6149 if (truelab == NULL)
6150 {
6151 cc = reverse_mri_condition (cc);
6152 truelab = falselab;
6153 }
6154
6155 if (leftstart != NULL)
6156 {
6157 buf = (char *) xmalloc (20
6158 + (leftstop - leftstart)
6159 + (rightstop - rightstart));
6160 s = buf;
6161 *s++ = 'c';
6162 *s++ = 'm';
6163 *s++ = 'p';
6164 if (qual != '\0')
6165 *s++ = TOLOWER (qual);
6166 *s++ = ' ';
6167 memcpy (s, leftstart, leftstop - leftstart);
6168 s += leftstop - leftstart;
6169 *s++ = ',';
6170 memcpy (s, rightstart, rightstop - rightstart);
6171 s += rightstop - rightstart;
6172 *s = '\0';
6173 mri_assemble (buf);
6174 free (buf);
6175 }
6176
6177 buf = (char *) xmalloc (20 + strlen (truelab));
6178 s = buf;
6179 *s++ = 'b';
6180 *s++ = cc >> 8;
6181 *s++ = cc & 0xff;
6182 if (extent != '\0')
6183 *s++ = TOLOWER (extent);
6184 *s++ = ' ';
6185 strcpy (s, truelab);
6186 mri_assemble (buf);
6187 free (buf);
6188 }
6189
6190 /* Parse an MRI structured control expression. This generates test
6191 and branch instructions. STOP is where the expression ends. It
6192 goes to TRUELAB if the condition is true, and to FALSELAB if the
6193 condition is false. Exactly one of TRUELAB and FALSELAB will be
6194 NULL, meaning to fall through. QUAL is the size qualifier for the
6195 expression. EXTENT is the size to use for the branch. */
6196
6197 static void
6198 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6199 const char *falselab, int extent)
6200 {
6201 int c;
6202 int cc;
6203 char *leftstart;
6204 char *leftstop;
6205 char *rightstart;
6206 char *rightstop;
6207
6208 c = *stop;
6209 *stop = '\0';
6210
6211 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6212 &rightstart, &rightstop))
6213 {
6214 *stop = c;
6215 return;
6216 }
6217
6218 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6219 {
6220 const char *flab;
6221
6222 if (falselab != NULL)
6223 flab = falselab;
6224 else
6225 flab = mri_control_label ();
6226
6227 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6228 rightstop, (const char *) NULL, flab, extent);
6229
6230 input_line_pointer += 3;
6231 if (*input_line_pointer != '.'
6232 || input_line_pointer[1] == '\0')
6233 qual = '\0';
6234 else
6235 {
6236 qual = input_line_pointer[1];
6237 input_line_pointer += 2;
6238 }
6239
6240 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6241 &rightstart, &rightstop))
6242 {
6243 *stop = c;
6244 return;
6245 }
6246
6247 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6248 rightstop, truelab, falselab, extent);
6249
6250 if (falselab == NULL)
6251 colon (flab);
6252 }
6253 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6254 {
6255 const char *tlab;
6256
6257 if (truelab != NULL)
6258 tlab = truelab;
6259 else
6260 tlab = mri_control_label ();
6261
6262 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6263 rightstop, tlab, (const char *) NULL, extent);
6264
6265 input_line_pointer += 2;
6266 if (*input_line_pointer != '.'
6267 || input_line_pointer[1] == '\0')
6268 qual = '\0';
6269 else
6270 {
6271 qual = input_line_pointer[1];
6272 input_line_pointer += 2;
6273 }
6274
6275 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6276 &rightstart, &rightstop))
6277 {
6278 *stop = c;
6279 return;
6280 }
6281
6282 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6283 rightstop, truelab, falselab, extent);
6284
6285 if (truelab == NULL)
6286 colon (tlab);
6287 }
6288 else
6289 {
6290 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6291 rightstop, truelab, falselab, extent);
6292 }
6293
6294 *stop = c;
6295 if (input_line_pointer != stop)
6296 as_bad (_("syntax error in structured control directive"));
6297 }
6298
6299 /* Handle the MRI IF pseudo-op. This may be a structured control
6300 directive, or it may be a regular assembler conditional, depending
6301 on its operands. */
6302
6303 static void
6304 s_mri_if (int qual)
6305 {
6306 char *s;
6307 int c;
6308 struct mri_control_info *n;
6309
6310 /* A structured control directive must end with THEN with an
6311 optional qualifier. */
6312 s = input_line_pointer;
6313 /* We only accept '*' as introduction of comments if preceded by white space
6314 or at first column of a line (I think this can't actually happen here?)
6315 This is important when assembling:
6316 if d0 <ne> 12(a0,d0*2) then
6317 if d0 <ne> #CONST*20 then. */
6318 while (! (is_end_of_line[(unsigned char) *s]
6319 || (flag_mri
6320 && *s == '*'
6321 && (s == input_line_pointer
6322 || *(s-1) == ' '
6323 || *(s-1) == '\t'))))
6324 ++s;
6325 --s;
6326 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6327 --s;
6328
6329 if (s - input_line_pointer > 1
6330 && s[-1] == '.')
6331 s -= 2;
6332
6333 if (s - input_line_pointer < 3
6334 || strncasecmp (s - 3, "THEN", 4) != 0)
6335 {
6336 if (qual != '\0')
6337 {
6338 as_bad (_("missing then"));
6339 ignore_rest_of_line ();
6340 return;
6341 }
6342
6343 /* It's a conditional. */
6344 s_if (O_ne);
6345 return;
6346 }
6347
6348 /* Since this might be a conditional if, this pseudo-op will be
6349 called even if we are supported to be ignoring input. Double
6350 check now. Clobber *input_line_pointer so that ignore_input
6351 thinks that this is not a special pseudo-op. */
6352 c = *input_line_pointer;
6353 *input_line_pointer = 0;
6354 if (ignore_input ())
6355 {
6356 *input_line_pointer = c;
6357 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6358 ++input_line_pointer;
6359 demand_empty_rest_of_line ();
6360 return;
6361 }
6362 *input_line_pointer = c;
6363
6364 n = push_mri_control (mri_if);
6365
6366 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6367 n->next, s[1] == '.' ? s[2] : '\0');
6368
6369 if (s[1] == '.')
6370 input_line_pointer = s + 3;
6371 else
6372 input_line_pointer = s + 1;
6373
6374 if (flag_mri)
6375 {
6376 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6377 ++input_line_pointer;
6378 }
6379
6380 demand_empty_rest_of_line ();
6381 }
6382
6383 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6384 structured IF, associate the ELSE with the IF. Otherwise, assume
6385 it is a conditional else. */
6386
6387 static void
6388 s_mri_else (int qual)
6389 {
6390 int c;
6391 char *buf;
6392 char q[2];
6393
6394 if (qual == '\0'
6395 && (mri_control_stack == NULL
6396 || mri_control_stack->type != mri_if
6397 || mri_control_stack->else_seen))
6398 {
6399 s_else (0);
6400 return;
6401 }
6402
6403 c = *input_line_pointer;
6404 *input_line_pointer = 0;
6405 if (ignore_input ())
6406 {
6407 *input_line_pointer = c;
6408 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6409 ++input_line_pointer;
6410 demand_empty_rest_of_line ();
6411 return;
6412 }
6413 *input_line_pointer = c;
6414
6415 if (mri_control_stack == NULL
6416 || mri_control_stack->type != mri_if
6417 || mri_control_stack->else_seen)
6418 {
6419 as_bad (_("else without matching if"));
6420 ignore_rest_of_line ();
6421 return;
6422 }
6423
6424 mri_control_stack->else_seen = 1;
6425
6426 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6427 q[0] = TOLOWER (qual);
6428 q[1] = '\0';
6429 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6430 mri_assemble (buf);
6431 free (buf);
6432
6433 colon (mri_control_stack->next);
6434
6435 if (flag_mri)
6436 {
6437 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6438 ++input_line_pointer;
6439 }
6440
6441 demand_empty_rest_of_line ();
6442 }
6443
6444 /* Handle the MRI ENDI pseudo-op. */
6445
6446 static void
6447 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6448 {
6449 if (mri_control_stack == NULL
6450 || mri_control_stack->type != mri_if)
6451 {
6452 as_bad (_("endi without matching if"));
6453 ignore_rest_of_line ();
6454 return;
6455 }
6456
6457 /* ignore_input will not return true for ENDI, so we don't need to
6458 worry about checking it again here. */
6459
6460 if (! mri_control_stack->else_seen)
6461 colon (mri_control_stack->next);
6462 colon (mri_control_stack->bottom);
6463
6464 pop_mri_control ();
6465
6466 if (flag_mri)
6467 {
6468 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6469 ++input_line_pointer;
6470 }
6471
6472 demand_empty_rest_of_line ();
6473 }
6474
6475 /* Handle the MRI BREAK pseudo-op. */
6476
6477 static void
6478 s_mri_break (int extent)
6479 {
6480 struct mri_control_info *n;
6481 char *buf;
6482 char ex[2];
6483
6484 n = mri_control_stack;
6485 while (n != NULL
6486 && n->type != mri_for
6487 && n->type != mri_repeat
6488 && n->type != mri_while)
6489 n = n->outer;
6490 if (n == NULL)
6491 {
6492 as_bad (_("break outside of structured loop"));
6493 ignore_rest_of_line ();
6494 return;
6495 }
6496
6497 buf = (char *) xmalloc (20 + strlen (n->bottom));
6498 ex[0] = TOLOWER (extent);
6499 ex[1] = '\0';
6500 sprintf (buf, "bra%s %s", ex, n->bottom);
6501 mri_assemble (buf);
6502 free (buf);
6503
6504 if (flag_mri)
6505 {
6506 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6507 ++input_line_pointer;
6508 }
6509
6510 demand_empty_rest_of_line ();
6511 }
6512
6513 /* Handle the MRI NEXT pseudo-op. */
6514
6515 static void
6516 s_mri_next (int extent)
6517 {
6518 struct mri_control_info *n;
6519 char *buf;
6520 char ex[2];
6521
6522 n = mri_control_stack;
6523 while (n != NULL
6524 && n->type != mri_for
6525 && n->type != mri_repeat
6526 && n->type != mri_while)
6527 n = n->outer;
6528 if (n == NULL)
6529 {
6530 as_bad (_("next outside of structured loop"));
6531 ignore_rest_of_line ();
6532 return;
6533 }
6534
6535 buf = (char *) xmalloc (20 + strlen (n->next));
6536 ex[0] = TOLOWER (extent);
6537 ex[1] = '\0';
6538 sprintf (buf, "bra%s %s", ex, n->next);
6539 mri_assemble (buf);
6540 free (buf);
6541
6542 if (flag_mri)
6543 {
6544 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6545 ++input_line_pointer;
6546 }
6547
6548 demand_empty_rest_of_line ();
6549 }
6550
6551 /* Handle the MRI FOR pseudo-op. */
6552
6553 static void
6554 s_mri_for (int qual)
6555 {
6556 const char *varstart, *varstop;
6557 const char *initstart, *initstop;
6558 const char *endstart, *endstop;
6559 const char *bystart, *bystop;
6560 int up;
6561 int by;
6562 int extent;
6563 struct mri_control_info *n;
6564 char *buf;
6565 char *s;
6566 char ex[2];
6567
6568 /* The syntax is
6569 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6570 */
6571
6572 SKIP_WHITESPACE ();
6573 varstart = input_line_pointer;
6574
6575 /* Look for the '='. */
6576 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6577 && *input_line_pointer != '=')
6578 ++input_line_pointer;
6579 if (*input_line_pointer != '=')
6580 {
6581 as_bad (_("missing ="));
6582 ignore_rest_of_line ();
6583 return;
6584 }
6585
6586 varstop = input_line_pointer;
6587 if (varstop > varstart
6588 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6589 --varstop;
6590
6591 ++input_line_pointer;
6592
6593 initstart = input_line_pointer;
6594
6595 /* Look for TO or DOWNTO. */
6596 up = 1;
6597 initstop = NULL;
6598 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6599 {
6600 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6601 && ! is_part_of_name (input_line_pointer[2]))
6602 {
6603 initstop = input_line_pointer;
6604 input_line_pointer += 2;
6605 break;
6606 }
6607 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6608 && ! is_part_of_name (input_line_pointer[6]))
6609 {
6610 initstop = input_line_pointer;
6611 up = 0;
6612 input_line_pointer += 6;
6613 break;
6614 }
6615 ++input_line_pointer;
6616 }
6617 if (initstop == NULL)
6618 {
6619 as_bad (_("missing to or downto"));
6620 ignore_rest_of_line ();
6621 return;
6622 }
6623 if (initstop > initstart
6624 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6625 --initstop;
6626
6627 SKIP_WHITESPACE ();
6628 endstart = input_line_pointer;
6629
6630 /* Look for BY or DO. */
6631 by = 0;
6632 endstop = NULL;
6633 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6634 {
6635 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6636 && ! is_part_of_name (input_line_pointer[2]))
6637 {
6638 endstop = input_line_pointer;
6639 by = 1;
6640 input_line_pointer += 2;
6641 break;
6642 }
6643 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6644 && (input_line_pointer[2] == '.'
6645 || ! is_part_of_name (input_line_pointer[2])))
6646 {
6647 endstop = input_line_pointer;
6648 input_line_pointer += 2;
6649 break;
6650 }
6651 ++input_line_pointer;
6652 }
6653 if (endstop == NULL)
6654 {
6655 as_bad (_("missing do"));
6656 ignore_rest_of_line ();
6657 return;
6658 }
6659 if (endstop > endstart
6660 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6661 --endstop;
6662
6663 if (! by)
6664 {
6665 bystart = "#1";
6666 bystop = bystart + 2;
6667 }
6668 else
6669 {
6670 SKIP_WHITESPACE ();
6671 bystart = input_line_pointer;
6672
6673 /* Look for DO. */
6674 bystop = NULL;
6675 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6676 {
6677 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6678 && (input_line_pointer[2] == '.'
6679 || ! is_part_of_name (input_line_pointer[2])))
6680 {
6681 bystop = input_line_pointer;
6682 input_line_pointer += 2;
6683 break;
6684 }
6685 ++input_line_pointer;
6686 }
6687 if (bystop == NULL)
6688 {
6689 as_bad (_("missing do"));
6690 ignore_rest_of_line ();
6691 return;
6692 }
6693 if (bystop > bystart
6694 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6695 --bystop;
6696 }
6697
6698 if (*input_line_pointer != '.')
6699 extent = '\0';
6700 else
6701 {
6702 extent = input_line_pointer[1];
6703 input_line_pointer += 2;
6704 }
6705
6706 /* We have fully parsed the FOR operands. Now build the loop. */
6707 n = push_mri_control (mri_for);
6708
6709 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6710
6711 /* Move init,var. */
6712 s = buf;
6713 *s++ = 'm';
6714 *s++ = 'o';
6715 *s++ = 'v';
6716 *s++ = 'e';
6717 if (qual != '\0')
6718 *s++ = TOLOWER (qual);
6719 *s++ = ' ';
6720 memcpy (s, initstart, initstop - initstart);
6721 s += initstop - initstart;
6722 *s++ = ',';
6723 memcpy (s, varstart, varstop - varstart);
6724 s += varstop - varstart;
6725 *s = '\0';
6726 mri_assemble (buf);
6727
6728 colon (n->top);
6729
6730 /* cmp end,var. */
6731 s = buf;
6732 *s++ = 'c';
6733 *s++ = 'm';
6734 *s++ = 'p';
6735 if (qual != '\0')
6736 *s++ = TOLOWER (qual);
6737 *s++ = ' ';
6738 memcpy (s, endstart, endstop - endstart);
6739 s += endstop - endstart;
6740 *s++ = ',';
6741 memcpy (s, varstart, varstop - varstart);
6742 s += varstop - varstart;
6743 *s = '\0';
6744 mri_assemble (buf);
6745
6746 /* bcc bottom. */
6747 ex[0] = TOLOWER (extent);
6748 ex[1] = '\0';
6749 if (up)
6750 sprintf (buf, "blt%s %s", ex, n->bottom);
6751 else
6752 sprintf (buf, "bgt%s %s", ex, n->bottom);
6753 mri_assemble (buf);
6754
6755 /* Put together the add or sub instruction used by ENDF. */
6756 s = buf;
6757 if (up)
6758 strcpy (s, "add");
6759 else
6760 strcpy (s, "sub");
6761 s += 3;
6762 if (qual != '\0')
6763 *s++ = TOLOWER (qual);
6764 *s++ = ' ';
6765 memcpy (s, bystart, bystop - bystart);
6766 s += bystop - bystart;
6767 *s++ = ',';
6768 memcpy (s, varstart, varstop - varstart);
6769 s += varstop - varstart;
6770 *s = '\0';
6771 n->incr = buf;
6772
6773 if (flag_mri)
6774 {
6775 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6776 ++input_line_pointer;
6777 }
6778
6779 demand_empty_rest_of_line ();
6780 }
6781
6782 /* Handle the MRI ENDF pseudo-op. */
6783
6784 static void
6785 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
6786 {
6787 if (mri_control_stack == NULL
6788 || mri_control_stack->type != mri_for)
6789 {
6790 as_bad (_("endf without for"));
6791 ignore_rest_of_line ();
6792 return;
6793 }
6794
6795 colon (mri_control_stack->next);
6796
6797 mri_assemble (mri_control_stack->incr);
6798
6799 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6800 mri_assemble (mri_control_stack->incr);
6801
6802 free (mri_control_stack->incr);
6803
6804 colon (mri_control_stack->bottom);
6805
6806 pop_mri_control ();
6807
6808 if (flag_mri)
6809 {
6810 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6811 ++input_line_pointer;
6812 }
6813
6814 demand_empty_rest_of_line ();
6815 }
6816
6817 /* Handle the MRI REPEAT pseudo-op. */
6818
6819 static void
6820 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
6821 {
6822 struct mri_control_info *n;
6823
6824 n = push_mri_control (mri_repeat);
6825 colon (n->top);
6826 if (flag_mri)
6827 {
6828 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6829 ++input_line_pointer;
6830 }
6831 demand_empty_rest_of_line ();
6832 }
6833
6834 /* Handle the MRI UNTIL pseudo-op. */
6835
6836 static void
6837 s_mri_until (int qual)
6838 {
6839 char *s;
6840
6841 if (mri_control_stack == NULL
6842 || mri_control_stack->type != mri_repeat)
6843 {
6844 as_bad (_("until without repeat"));
6845 ignore_rest_of_line ();
6846 return;
6847 }
6848
6849 colon (mri_control_stack->next);
6850
6851 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6852 ;
6853
6854 parse_mri_control_expression (s, qual, (const char *) NULL,
6855 mri_control_stack->top, '\0');
6856
6857 colon (mri_control_stack->bottom);
6858
6859 input_line_pointer = s;
6860
6861 pop_mri_control ();
6862
6863 if (flag_mri)
6864 {
6865 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6866 ++input_line_pointer;
6867 }
6868
6869 demand_empty_rest_of_line ();
6870 }
6871
6872 /* Handle the MRI WHILE pseudo-op. */
6873
6874 static void
6875 s_mri_while (int qual)
6876 {
6877 char *s;
6878
6879 struct mri_control_info *n;
6880
6881 s = input_line_pointer;
6882 /* We only accept '*' as introduction of comments if preceded by white space
6883 or at first column of a line (I think this can't actually happen here?)
6884 This is important when assembling:
6885 while d0 <ne> 12(a0,d0*2) do
6886 while d0 <ne> #CONST*20 do. */
6887 while (! (is_end_of_line[(unsigned char) *s]
6888 || (flag_mri
6889 && *s == '*'
6890 && (s == input_line_pointer
6891 || *(s-1) == ' '
6892 || *(s-1) == '\t'))))
6893 s++;
6894 --s;
6895 while (*s == ' ' || *s == '\t')
6896 --s;
6897 if (s - input_line_pointer > 1
6898 && s[-1] == '.')
6899 s -= 2;
6900 if (s - input_line_pointer < 2
6901 || strncasecmp (s - 1, "DO", 2) != 0)
6902 {
6903 as_bad (_("missing do"));
6904 ignore_rest_of_line ();
6905 return;
6906 }
6907
6908 n = push_mri_control (mri_while);
6909
6910 colon (n->next);
6911
6912 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6913 s[1] == '.' ? s[2] : '\0');
6914
6915 input_line_pointer = s + 1;
6916 if (*input_line_pointer == '.')
6917 input_line_pointer += 2;
6918
6919 if (flag_mri)
6920 {
6921 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6922 ++input_line_pointer;
6923 }
6924
6925 demand_empty_rest_of_line ();
6926 }
6927
6928 /* Handle the MRI ENDW pseudo-op. */
6929
6930 static void
6931 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
6932 {
6933 char *buf;
6934
6935 if (mri_control_stack == NULL
6936 || mri_control_stack->type != mri_while)
6937 {
6938 as_bad (_("endw without while"));
6939 ignore_rest_of_line ();
6940 return;
6941 }
6942
6943 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6944 sprintf (buf, "bra %s", mri_control_stack->next);
6945 mri_assemble (buf);
6946 free (buf);
6947
6948 colon (mri_control_stack->bottom);
6949
6950 pop_mri_control ();
6951
6952 if (flag_mri)
6953 {
6954 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6955 ++input_line_pointer;
6956 }
6957
6958 demand_empty_rest_of_line ();
6959 }
6960 \f
6961 /* Parse a .cpu directive. */
6962
6963 static void
6964 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
6965 {
6966 char saved_char;
6967 char *name;
6968
6969 if (initialized)
6970 {
6971 as_bad (_("already assembled instructions"));
6972 ignore_rest_of_line ();
6973 return;
6974 }
6975
6976 name = input_line_pointer;
6977 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
6978 input_line_pointer++;
6979 saved_char = *input_line_pointer;
6980 *input_line_pointer = 0;
6981
6982 m68k_set_cpu (name, 1, 0);
6983
6984 *input_line_pointer = saved_char;
6985 demand_empty_rest_of_line ();
6986 return;
6987 }
6988
6989 /* Parse a .arch directive. */
6990
6991 static void
6992 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
6993 {
6994 char saved_char;
6995 char *name;
6996
6997 if (initialized)
6998 {
6999 as_bad (_("already assembled instructions"));
7000 ignore_rest_of_line ();
7001 return;
7002 }
7003
7004 name = input_line_pointer;
7005 while (*input_line_pointer && *input_line_pointer != ','
7006 && !ISSPACE (*input_line_pointer))
7007 input_line_pointer++;
7008 saved_char = *input_line_pointer;
7009 *input_line_pointer = 0;
7010
7011 if (m68k_set_arch (name, 1, 0))
7012 {
7013 /* Scan extensions. */
7014 do
7015 {
7016 *input_line_pointer++ = saved_char;
7017 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7018 break;
7019 name = input_line_pointer;
7020 while (*input_line_pointer && *input_line_pointer != ','
7021 && !ISSPACE (*input_line_pointer))
7022 input_line_pointer++;
7023 saved_char = *input_line_pointer;
7024 *input_line_pointer = 0;
7025 }
7026 while (m68k_set_extension (name, 1, 0));
7027 }
7028
7029 *input_line_pointer = saved_char;
7030 demand_empty_rest_of_line ();
7031 return;
7032 }
7033 \f
7034 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7035 if none is found, the caller is responsible for emitting an error
7036 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7037 cpu name, if it begins with a '6' (possibly skipping an intervening
7038 'c'. We also allow a 'c' in the same place. if NEGATED is
7039 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7040 the option is indeed negated. */
7041
7042 static const struct m68k_cpu *
7043 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7044 int allow_m, int *negated)
7045 {
7046 /* allow negated value? */
7047 if (negated)
7048 {
7049 *negated = 0;
7050
7051 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7052 {
7053 arg += 3;
7054 *negated = 1;
7055 }
7056 }
7057
7058 /* Remove 'm' or 'mc' prefix from 68k variants. */
7059 if (allow_m)
7060 {
7061 if (arg[0] == 'm')
7062 {
7063 if (arg[1] == '6')
7064 arg += 1;
7065 else if (arg[1] == 'c' && arg[2] == '6')
7066 arg += 2;
7067 }
7068 }
7069 else if (arg[0] == 'c' && arg[1] == '6')
7070 arg += 1;
7071
7072 for (; table->name; table++)
7073 if (!strcmp (arg, table->name))
7074 return table;
7075 return 0;
7076 }
7077
7078 /* Set the cpu, issuing errors if it is unrecognized, or invalid */
7079
7080 static int
7081 m68k_set_cpu (char const *name, int allow_m, int silent)
7082 {
7083 const struct m68k_cpu *cpu;
7084
7085 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7086
7087 if (!cpu)
7088 {
7089 if (!silent)
7090 as_bad (_("cpu `%s' unrecognized"), name);
7091 return 0;
7092 }
7093
7094 if (selected_cpu && selected_cpu != cpu)
7095 {
7096 as_bad (_("already selected `%s' processor"),
7097 selected_cpu->name);
7098 return 0;
7099 }
7100 selected_cpu = cpu;
7101 return 1;
7102 }
7103
7104 /* Set the architecture, issuing errors if it is unrecognized, or invalid */
7105
7106 static int
7107 m68k_set_arch (char const *name, int allow_m, int silent)
7108 {
7109 const struct m68k_cpu *arch;
7110
7111 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7112
7113 if (!arch)
7114 {
7115 if (!silent)
7116 as_bad (_("architecture `%s' unrecognized"), name);
7117 return 0;
7118 }
7119
7120 if (selected_arch && selected_arch != arch)
7121 {
7122 as_bad (_("already selected `%s' architecture"),
7123 selected_arch->name);
7124 return 0;
7125 }
7126
7127 selected_arch = arch;
7128 return 1;
7129 }
7130
7131 /* Set the architecture extension, issuing errors if it is
7132 unrecognized, or invalid */
7133
7134 static int
7135 m68k_set_extension (char const *name, int allow_m, int silent)
7136 {
7137 int negated;
7138 const struct m68k_cpu *ext;
7139
7140 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7141
7142 if (!ext)
7143 {
7144 if (!silent)
7145 as_bad (_("extension `%s' unrecognized"), name);
7146 return 0;
7147 }
7148
7149 if (negated)
7150 not_current_architecture |= ext->arch;
7151 else
7152 current_architecture |= ext->arch;
7153 return 1;
7154 }
7155
7156 /* md_parse_option
7157 Invocation line includes a switch not recognized by the base assembler.
7158 */
7159
7160 #ifdef OBJ_ELF
7161 const char *md_shortopts = "lSA:m:kQ:V";
7162 #else
7163 const char *md_shortopts = "lSA:m:k";
7164 #endif
7165
7166 struct option md_longopts[] = {
7167 #define OPTION_PIC (OPTION_MD_BASE)
7168 {"pic", no_argument, NULL, OPTION_PIC},
7169 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7170 {"register-prefix-optional", no_argument, NULL,
7171 OPTION_REGISTER_PREFIX_OPTIONAL},
7172 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7173 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7174 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7175 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7176 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7177 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7178 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7179 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7180 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7181 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7182 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7183 {"pcrel", no_argument, NULL, OPTION_PCREL},
7184 {NULL, no_argument, NULL, 0}
7185 };
7186 size_t md_longopts_size = sizeof (md_longopts);
7187
7188 int
7189 md_parse_option (int c, char *arg)
7190 {
7191 switch (c)
7192 {
7193 case 'l': /* -l means keep external to 2 bit offset
7194 rather than 16 bit one. */
7195 flag_short_refs = 1;
7196 break;
7197
7198 case 'S': /* -S means that jbsr's always turn into
7199 jsr's. */
7200 flag_long_jumps = 1;
7201 break;
7202
7203 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7204 branches into absolute jumps. */
7205 flag_keep_pcrel = 1;
7206 break;
7207
7208 case OPTION_PIC:
7209 case 'k':
7210 flag_want_pic = 1;
7211 break; /* -pic, Position Independent Code. */
7212
7213 case OPTION_REGISTER_PREFIX_OPTIONAL:
7214 flag_reg_prefix_optional = 1;
7215 reg_prefix_optional_seen = 1;
7216 break;
7217
7218 /* -V: SVR4 argument to print version ID. */
7219 case 'V':
7220 print_version_id ();
7221 break;
7222
7223 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7224 should be emitted or not. FIXME: Not implemented. */
7225 case 'Q':
7226 break;
7227
7228 case OPTION_BITWISE_OR:
7229 {
7230 char *n, *t;
7231 const char *s;
7232
7233 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7234 t = n;
7235 for (s = m68k_comment_chars; *s != '\0'; s++)
7236 if (*s != '|')
7237 *t++ = *s;
7238 *t = '\0';
7239 m68k_comment_chars = n;
7240 }
7241 break;
7242
7243 case OPTION_BASE_SIZE_DEFAULT_16:
7244 m68k_index_width_default = SIZE_WORD;
7245 break;
7246
7247 case OPTION_BASE_SIZE_DEFAULT_32:
7248 m68k_index_width_default = SIZE_LONG;
7249 break;
7250
7251 case OPTION_DISP_SIZE_DEFAULT_16:
7252 m68k_rel32 = 0;
7253 m68k_rel32_from_cmdline = 1;
7254 break;
7255
7256 case OPTION_DISP_SIZE_DEFAULT_32:
7257 m68k_rel32 = 1;
7258 m68k_rel32_from_cmdline = 1;
7259 break;
7260
7261 case 'A':
7262 #if WARN_DEPRECATED
7263 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7264 arg, arg));
7265 #endif
7266 /* Intentional fall-through. */
7267 case 'm':
7268 if (!strncmp (arg, "arch=", 5))
7269 m68k_set_arch (arg + 5, 1, 0);
7270 else if (!strncmp (arg, "cpu=", 4))
7271 m68k_set_cpu (arg + 4, 1, 0);
7272 else if (m68k_set_extension (arg, 0, 1))
7273 ;
7274 else if (m68k_set_cpu (arg, 0, 1))
7275 ;
7276 else
7277 return 0;
7278 break;
7279
7280 default:
7281 return 0;
7282 }
7283
7284 return 1;
7285 }
7286
7287 /* Setup tables from the selected arch and/or cpu */
7288
7289 static void
7290 m68k_init_arch (void)
7291 {
7292 unsigned arch_of_chip = 0;
7293
7294 if (not_current_architecture & current_architecture)
7295 {
7296 as_bad (_("architecture features both enabled and disabled"));
7297 not_current_architecture &= ~current_architecture;
7298 }
7299 if (selected_arch)
7300 {
7301 arch_of_chip = selected_arch->arch;
7302 current_chip = selected_arch->chip;
7303 if (selected_cpu && (arch_of_chip & ~selected_cpu->arch))
7304 {
7305 as_bad (_("selected processor is not from selected architecture"));
7306 arch_of_chip = selected_cpu->arch;
7307 }
7308 }
7309 else
7310 arch_of_chip = selected_cpu->arch;
7311 if (selected_cpu)
7312 current_chip = selected_cpu->chip;
7313
7314 current_architecture |= arch_of_chip;
7315 current_architecture &= ~not_current_architecture;
7316 if ((current_architecture & m68k_mask)
7317 && (current_architecture & ~m68k_mask))
7318 {
7319 as_bad (_ ("m68k and cf features both selected"));
7320 if (arch_of_chip & m68k_mask)
7321 current_architecture &= m68k_mask;
7322 else
7323 current_architecture &= ~m68k_mask;
7324 }
7325
7326 /* Permit m68881 specification with all cpus; those that can't work
7327 with a coprocessor could be doing emulation. */
7328 if (current_architecture & m68851)
7329 {
7330 if (current_architecture & m68040)
7331 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7332 }
7333 /* What other incompatibilities could we check for? */
7334
7335 /* Note which set of "movec" control registers is available. */
7336 select_control_regs ();
7337
7338 if (cpu_of_arch (current_architecture) < m68020
7339 || arch_coldfire_p (current_architecture))
7340 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7341
7342 initialized = 1;
7343 }
7344
7345 void
7346 md_show_usage (FILE *stream)
7347 {
7348 const char *default_cpu = TARGET_CPU;
7349 int i;
7350 unsigned int default_arch;
7351
7352 /* Get the canonical name for the default target CPU. */
7353 if (*default_cpu == 'm')
7354 default_cpu++;
7355 for (i = 0; m68k_cpus[i].name; i++)
7356 {
7357 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7358 {
7359 default_arch = m68k_cpus[i].arch;
7360 for (i = 0; m68k_cpus[i].name; i++)
7361 {
7362 if (m68k_cpus[i].arch == default_arch
7363 && !m68k_cpus[i].alias)
7364 {
7365 default_cpu = m68k_cpus[i].name;
7366 break;
7367 }
7368 }
7369 }
7370 }
7371
7372 fprintf (stream, _("\
7373 -march=<arch> set architecture\n\
7374 -mcpu=<cpu> set cpu [default %s]\n\
7375 "), default_cpu);
7376 for (i = 0; m68k_extensions[i].name; i++)
7377 fprintf (stream, _("\
7378 -m[no-]%-16s enable/disable %s architecture extension\n\
7379 "), m68k_extensions[i].name, m68k_extensions[i].alias ? "ColdFire" : "m68k");
7380
7381 fprintf (stream, _("\
7382 -l use 1 word for refs to undefined symbols [default 2]\n\
7383 -pic, -k generate position independent code\n\
7384 -S turn jbsr into jsr\n\
7385 --pcrel never turn PC-relative branches into absolute jumps\n\
7386 --register-prefix-optional\n\
7387 recognize register names without prefix character\n\
7388 --bitwise-or do not treat `|' as a comment character\n\
7389 --base-size-default-16 base reg without size is 16 bits\n\
7390 --base-size-default-32 base reg without size is 32 bits (default)\n\
7391 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7392 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7393 "));
7394
7395 fprintf (stream, _("Architecture variants are: "));
7396 for (i = 0; m68k_archs[i].name; i++)
7397 {
7398 if (i)
7399 fprintf (stream, " | ");
7400 fprintf (stream, m68k_archs[i].name);
7401 }
7402 fprintf (stream, "\n");
7403
7404 fprintf (stream, _("Processor variants are: "));
7405 for (i = 0; m68k_cpus[i].name; i++)
7406 {
7407 if (i)
7408 fprintf (stream, " | ");
7409 fprintf (stream, m68k_cpus[i].name);
7410 }
7411 fprintf (stream, _("\n"));
7412 }
7413 \f
7414 #ifdef TEST2
7415
7416 /* TEST2: Test md_assemble() */
7417 /* Warning, this routine probably doesn't work anymore. */
7418 int
7419 main (void)
7420 {
7421 struct m68k_it the_ins;
7422 char buf[120];
7423 char *cp;
7424 int n;
7425
7426 m68k_ip_begin ();
7427 for (;;)
7428 {
7429 if (!gets (buf) || !*buf)
7430 break;
7431 if (buf[0] == '|' || buf[1] == '.')
7432 continue;
7433 for (cp = buf; *cp; cp++)
7434 if (*cp == '\t')
7435 *cp = ' ';
7436 if (is_label (buf))
7437 continue;
7438 memset (&the_ins, '\0', sizeof (the_ins));
7439 m68k_ip (&the_ins, buf);
7440 if (the_ins.error)
7441 {
7442 printf (_("Error %s in %s\n"), the_ins.error, buf);
7443 }
7444 else
7445 {
7446 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7447 for (n = 0; n < the_ins.numo; n++)
7448 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7449 printf (" ");
7450 print_the_insn (&the_ins.opcode[0], stdout);
7451 (void) putchar ('\n');
7452 }
7453 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7454 {
7455 if (the_ins.operands[n].error)
7456 {
7457 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7458 continue;
7459 }
7460 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7461 the_ins.operands[n].reg);
7462 if (the_ins.operands[n].b_const)
7463 printf ("Constant: '%.*s', ",
7464 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7465 the_ins.operands[n].b_const);
7466 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7467 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7468 if (the_ins.operands[n].b_iadd)
7469 printf ("Iadd: '%.*s',",
7470 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7471 the_ins.operands[n].b_iadd);
7472 putchar ('\n');
7473 }
7474 }
7475 m68k_ip_end ();
7476 return 0;
7477 }
7478
7479 int
7480 is_label (char *str)
7481 {
7482 while (*str == ' ')
7483 str++;
7484 while (*str && *str != ' ')
7485 str++;
7486 if (str[-1] == ':' || str[1] == '=')
7487 return 1;
7488 return 0;
7489 }
7490
7491 #endif
7492
7493 /* Possible states for relaxation:
7494
7495 0 0 branch offset byte (bra, etc)
7496 0 1 word
7497 0 2 long
7498
7499 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7500 1 1 word
7501 1 2 long
7502
7503 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7504 2 1 word-long
7505 2 2 long-word
7506 2 3 long-long
7507
7508 */
7509
7510 /* We have no need to default values of symbols. */
7511
7512 symbolS *
7513 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7514 {
7515 return 0;
7516 }
7517
7518 /* Round up a section size to the appropriate boundary. */
7519 valueT
7520 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7521 {
7522 #ifdef OBJ_AOUT
7523 /* For a.out, force the section size to be aligned. If we don't do
7524 this, BFD will align it for us, but it will not write out the
7525 final bytes of the section. This may be a bug in BFD, but it is
7526 easier to fix it here since that is how the other a.out targets
7527 work. */
7528 int align;
7529
7530 align = bfd_get_section_alignment (stdoutput, segment);
7531 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7532 #endif
7533
7534 return size;
7535 }
7536
7537 /* Exactly what point is a PC-relative offset relative TO?
7538 On the 68k, it is relative to the address of the first extension
7539 word. The difference between the addresses of the offset and the
7540 first extension word is stored in fx_pcrel_adjust. */
7541 long
7542 md_pcrel_from (fixS *fixP)
7543 {
7544 int adjust;
7545
7546 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7547 sign extend the value here. */
7548 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7549 if (adjust == 64)
7550 adjust = -1;
7551 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7552 }
7553
7554 #ifdef OBJ_ELF
7555 void
7556 m68k_elf_final_processing (void)
7557 {
7558 unsigned flags = 0;
7559
7560 if (arch_coldfire_fpu (current_architecture))
7561 flags |= EF_M68K_CFV4E;
7562 /* Set file-specific flags if this is a cpu32 processor. */
7563 if (cpu_of_arch (current_architecture) & cpu32)
7564 flags |= EF_M68K_CPU32;
7565 else if ((cpu_of_arch (current_architecture) & m68000up)
7566 && !(cpu_of_arch (current_architecture) & m68020up))
7567 flags |= EF_M68K_M68000;
7568
7569 if (current_architecture & mcfisa_a)
7570 {
7571 /* Set coldfire specific elf flags */
7572 if (current_architecture & mcfisa_b)
7573 flags |= EF_M68K_ISA_B;
7574 else if (current_architecture & mcfisa_aa)
7575 flags |= EF_M68K_ISA_A_PLUS;
7576 else
7577 flags |= EF_M68K_ISA_A;
7578
7579 if (current_architecture & mcfhwdiv)
7580 flags |= EF_M68K_HW_DIV;
7581
7582 if (current_architecture & mcfusp)
7583 flags |= EF_M68K_USP;
7584
7585 if (current_architecture & cfloat)
7586 flags |= EF_M68K_FLOAT;
7587
7588 if (current_architecture & mcfmac)
7589 flags |= EF_M68K_MAC;
7590 else if (current_architecture & mcfemac)
7591 flags |= EF_M68K_EMAC;
7592 }
7593 elf_elfheader (stdoutput)->e_flags |= flags;
7594 }
7595 #endif
7596
7597 int
7598 tc_m68k_regname_to_dw2regnum (const char *regname)
7599 {
7600 unsigned int regnum;
7601 static const char *const regnames[] =
7602 {
7603 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7604 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7605 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7606 "pc"
7607 };
7608
7609 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7610 if (strcmp (regname, regnames[regnum]) == 0)
7611 return regnum;
7612
7613 return -1;
7614 }
7615
7616 void
7617 tc_m68k_frame_initial_instructions (void)
7618 {
7619 static int sp_regno = -1;
7620
7621 if (sp_regno < 0)
7622 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7623
7624 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7625 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7626 }
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