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1 @c Copyright 1996, 2000, 2002 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
4 @ifset GENERIC
5 @page
6 @node D10V-Dependent
7 @chapter D10V Dependent Features
8 @end ifset
9 @ifclear GENERIC
10 @node Machine Dependencies
11 @chapter D10V Dependent Features
12 @end ifclear
14 @cindex D10V support
15 @menu
16 * D10V-Opts:: D10V Options
17 * D10V-Syntax:: Syntax
18 * D10V-Float:: Floating Point
19 * D10V-Opcodes:: Opcodes
20 @end menu
22 @node D10V-Opts
23 @section D10V Options
24 @cindex options, D10V
25 @cindex D10V options
26 The Mitsubishi D10V version of @code{@value{AS}} has a few machine
27 dependent options.
29 @table @samp
30 @item -O
31 The D10V can often execute two sub-instructions in parallel. When this option
32 is used, @code{@value{AS}} will attempt to optimize its output by detecting when
33 instructions can be executed in parallel.
34 @item --nowarnswap
35 To optimize execution performance, @code{@value{AS}} will sometimes swap the
36 order of instructions. Normally this generates a warning. When this option
37 is used, no warning will be generated when instructions are swapped.
38 @item --gstabs-packing
39 @item --no-gstabs-packing
40 @code{@value{AS}} packs adjacent short instructions into a single packed
41 instruction. @samp{--no-gstabs-packing} turns instruction packing off if
42 @samp{--gstabs} is specified as well; @samp{--gstabs-packing} (the
43 default) turns instruction packing on even when @samp{--gstabs} is
44 specified.
45 @end table
47 @node D10V-Syntax
48 @section Syntax
49 @cindex D10V syntax
50 @cindex syntax, D10V
52 The D10V syntax is based on the syntax in Mitsubishi's D10V architecture manual.
53 The differences are detailed below.
55 @menu
56 * D10V-Size:: Size Modifiers
57 * D10V-Subs:: Sub-Instructions
58 * D10V-Chars:: Special Characters
59 * D10V-Regs:: Register Names
60 * D10V-Addressing:: Addressing Modes
61 * D10V-Word:: @@WORD Modifier
62 @end menu
65 @node D10V-Size
66 @subsection Size Modifiers
67 @cindex D10V size modifiers
68 @cindex size modifiers, D10V
69 The D10V version of @code{@value{AS}} uses the instruction names in the D10V
70 Architecture Manual. However, the names in the manual are sometimes ambiguous.
71 There are instruction names that can assemble to a short or long form opcode.
72 How does the assembler pick the correct form? @code{@value{AS}} will always pick the
73 smallest form if it can. When dealing with a symbol that is not defined yet when a
74 line is being assembled, it will always use the long form. If you need to force the
75 assembler to use either the short or long form of the instruction, you can append
76 either @samp{.s} (short) or @samp{.l} (long) to it. For example, if you are writing
77 an assembly program and you want to do a branch to a symbol that is defined later
78 in your program, you can write @samp{bra.s foo}.
79 Objdump and GDB will always append @samp{.s} or @samp{.l} to instructions which
80 have both short and long forms.
82 @node D10V-Subs
83 @subsection Sub-Instructions
84 @cindex D10V sub-instructions
85 @cindex sub-instructions, D10V
86 The D10V assembler takes as input a series of instructions, either one-per-line,
87 or in the special two-per-line format described in the next section. Some of these
88 instructions will be short-form or sub-instructions. These sub-instructions can be packed
89 into a single instruction. The assembler will do this automatically. It will also detect
90 when it should not pack instructions. For example, when a label is defined, the next
91 instruction will never be packaged with the previous one. Whenever a branch and link
92 instruction is called, it will not be packaged with the next instruction so the return
93 address will be valid. Nops are automatically inserted when necessary.
95 If you do not want the assembler automatically making these decisions, you can control
96 the packaging and execution type (parallel or sequential) with the special execution
97 symbols described in the next section.
99 @node D10V-Chars
100 @subsection Special Characters
101 @cindex line comment character, D10V
102 @cindex D10V line comment character
103 @samp{;} and @samp{#} are the line comment characters.
104 @cindex sub-instruction ordering, D10V
105 @cindex D10V sub-instruction ordering
106 Sub-instructions may be executed in order, in reverse-order, or in parallel.
107 Instructions listed in the standard one-per-line format will be executed sequentially.
108 To specify the executing order, use the following symbols:
109 @table @samp
110 @item ->
111 Sequential with instruction on the left first.
112 @item <-
113 Sequential with instruction on the right first.
114 @item ||
115 Parallel
116 @end table
117 The D10V syntax allows either one instruction per line, one instruction per line with
118 the execution symbol, or two instructions per line. For example
119 @table @code
120 @item abs a1 -> abs r0
121 Execute these sequentially. The instruction on the right is in the right
122 container and is executed second.
123 @item abs r0 <- abs a1
124 Execute these reverse-sequentially. The instruction on the right is in the right
125 container, and is executed first.
126 @item ld2w r2,@@r8+ || mac a0,r0,r7
127 Execute these in parallel.
128 @item ld2w r2,@@r8+ ||
129 @itemx mac a0,r0,r7
130 Two-line format. Execute these in parallel.
131 @item ld2w r2,@@r8+
132 @itemx mac a0,r0,r7
133 Two-line format. Execute these sequentially. Assembler will
134 put them in the proper containers.
135 @item ld2w r2,@@r8+ ->
136 @itemx mac a0,r0,r7
137 Two-line format. Execute these sequentially. Same as above but
138 second instruction will always go into right container.
139 @end table
140 @cindex symbol names, @samp{$} in
141 @cindex @code{$} in symbol names
142 Since @samp{$} has no special meaning, you may use it in symbol names.
144 @node D10V-Regs
145 @subsection Register Names
146 @cindex D10V registers
147 @cindex registers, D10V
148 You can use the predefined symbols @samp{r0} through @samp{r15} to refer to the D10V
149 registers. You can also use @samp{sp} as an alias for @samp{r15}. The accumulators
150 are @samp{a0} and @samp{a1}. There are special register-pair names that may
151 optionally be used in opcodes that require even-numbered registers. Register names are
152 not case sensitive.
154 Register Pairs
155 @table @code
156 @item r0-r1
157 @item r2-r3
158 @item r4-r5
159 @item r6-r7
160 @item r8-r9
161 @item r10-r11
162 @item r12-r13
163 @item r14-r15
164 @end table
166 The D10V also has predefined symbols for these control registers and status bits:
167 @table @code
168 @item psw
169 Processor Status Word
170 @item bpsw
171 Backup Processor Status Word
172 @item pc
173 Program Counter
174 @item bpc
175 Backup Program Counter
176 @item rpt_c
177 Repeat Count
178 @item rpt_s
179 Repeat Start address
180 @item rpt_e
181 Repeat End address
182 @item mod_s
183 Modulo Start address
184 @item mod_e
185 Modulo End address
186 @item iba
187 Instruction Break Address
188 @item f0
189 Flag 0
190 @item f1
191 Flag 1
192 @item c
193 Carry flag
194 @end table
196 @node D10V-Addressing
197 @subsection Addressing Modes
198 @cindex addressing modes, D10V
199 @cindex D10V addressing modes
200 @code{@value{AS}} understands the following addressing modes for the D10V.
201 @code{R@var{n}} in the following refers to any of the numbered
202 registers, but @emph{not} the control registers.
203 @table @code
204 @item R@var{n}
205 Register direct
206 @item @@R@var{n}
207 Register indirect
208 @item @@R@var{n}+
209 Register indirect with post-increment
210 @item @@R@var{n}-
211 Register indirect with post-decrement
212 @item @@-SP
213 Register indirect with pre-decrement
214 @item @@(@var{disp}, R@var{n})
215 Register indirect with displacement
216 @item @var{addr}
217 PC relative address (for branch or rep).
218 @item #@var{imm}
219 Immediate data (the @samp{#} is optional and ignored)
220 @end table
222 @node D10V-Word
223 @subsection @@WORD Modifier
224 @cindex D10V @@word modifier
225 @cindex @@word modifier, D10V
226 Any symbol followed by @code{@@word} will be replaced by the symbol's value
227 shifted right by 2. This is used in situations such as loading a register
228 with the address of a function (or any other code fragment). For example, if
229 you want to load a register with the location of the function @code{main} then
230 jump to that function, you could do it as follows:
231 @smallexample
232 @group
233 ldi r2, main@@word
234 jmp r2
235 @end group
236 @end smallexample
238 @node D10V-Float
239 @section Floating Point
240 @cindex floating point, D10V
241 @cindex D10V floating point
242 The D10V has no hardware floating point, but the @code{.float} and @code{.double}
243 directives generates @sc{ieee} floating-point numbers for compatibility
244 with other development tools.
246 @node D10V-Opcodes
247 @section Opcodes
248 @cindex D10V opcode summary
249 @cindex opcode summary, D10V
250 @cindex mnemonics, D10V
251 @cindex instruction summary, D10V
252 For detailed information on the D10V machine instruction set, see
253 @cite{D10V Architecture: A VLIW Microprocessor for Multimedia Applications}
254 (Mitsubishi Electric Corp.).
255 @code{@value{AS}} implements all the standard D10V opcodes. The only changes are those
256 described in the section on size modifiers