opcodes/frv-desc.c

   1 /* CPU data for frv.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #include "sysdep.h"
  26 #include <stdio.h>
  27 #include <stdarg.h>
  28 #include "ansidecl.h"
  29 #include "bfd.h"
  30 #include "symcat.h"
  31 #include "frv-desc.h"
  32 #include "frv-opc.h"
  33 #include "opintl.h"
  34 #include "libiberty.h"
  35
  36 /* Attributes.  */
  37
  38 static const CGEN_ATTR_ENTRY bool_attr[] =
  39 {
  40   { "#f", 0 },
  41   { "#t", 1 },
  42   { 0, 0 }
  43 };
  44
  45 static const CGEN_ATTR_ENTRY MACH_attr[] =
  46 {
  47   { "base", MACH_BASE },
  48   { "frv", MACH_FRV },
  49   { "fr500", MACH_FR500 },
  50   { "fr400", MACH_FR400 },
  51   { "tomcat", MACH_TOMCAT },
  52   { "simple", MACH_SIMPLE },
  53   { "max", MACH_MAX },
  54   { 0, 0 }
  55 };
  56
  57 static const CGEN_ATTR_ENTRY ISA_attr[] =
  58 {
  59   { "frv", ISA_FRV },
  60   { "max", ISA_MAX },
  61   { 0, 0 }
  62 };
  63
  64 static const CGEN_ATTR_ENTRY UNIT_attr[] =
  65 {
  66   { "NIL", UNIT_NIL },
  67   { "I0", UNIT_I0 },
  68   { "I1", UNIT_I1 },
  69   { "I01", UNIT_I01 },
  70   { "FM0", UNIT_FM0 },
  71   { "FM1", UNIT_FM1 },
  72   { "FM01", UNIT_FM01 },
  73   { "B0", UNIT_B0 },
  74   { "B1", UNIT_B1 },
  75   { "B01", UNIT_B01 },
  76   { "C", UNIT_C },
  77   { "MULT_DIV", UNIT_MULT_DIV },
  78   { "LOAD", UNIT_LOAD },
  79   { "NUM_UNITS", UNIT_NUM_UNITS },
  80   { 0, 0 }
  81 };
  82
  83 static const CGEN_ATTR_ENTRY FR400_MAJOR_attr[] =
  84 {
  85   { "NONE", FR400_MAJOR_NONE },
  86   { "I_1", FR400_MAJOR_I_1 },
  87   { "I_2", FR400_MAJOR_I_2 },
  88   { "I_3", FR400_MAJOR_I_3 },
  89   { "I_4", FR400_MAJOR_I_4 },
  90   { "I_5", FR400_MAJOR_I_5 },
  91   { "B_1", FR400_MAJOR_B_1 },
  92   { "B_2", FR400_MAJOR_B_2 },
  93   { "B_3", FR400_MAJOR_B_3 },
  94   { "B_4", FR400_MAJOR_B_4 },
  95   { "B_5", FR400_MAJOR_B_5 },
  96   { "B_6", FR400_MAJOR_B_6 },
  97   { "C_1", FR400_MAJOR_C_1 },
  98   { "C_2", FR400_MAJOR_C_2 },
  99   { "M_1", FR400_MAJOR_M_1 },
 100   { "M_2", FR400_MAJOR_M_2 },
 101   { 0, 0 }
 102 };
 103
 104 static const CGEN_ATTR_ENTRY FR500_MAJOR_attr[] =
 105 {
 106   { "NONE", FR500_MAJOR_NONE },
 107   { "I_1", FR500_MAJOR_I_1 },
 108   { "I_2", FR500_MAJOR_I_2 },
 109   { "I_3", FR500_MAJOR_I_3 },
 110   { "I_4", FR500_MAJOR_I_4 },
 111   { "I_5", FR500_MAJOR_I_5 },
 112   { "I_6", FR500_MAJOR_I_6 },
 113   { "B_1", FR500_MAJOR_B_1 },
 114   { "B_2", FR500_MAJOR_B_2 },
 115   { "B_3", FR500_MAJOR_B_3 },
 116   { "B_4", FR500_MAJOR_B_4 },
 117   { "B_5", FR500_MAJOR_B_5 },
 118   { "B_6", FR500_MAJOR_B_6 },
 119   { "C_1", FR500_MAJOR_C_1 },
 120   { "C_2", FR500_MAJOR_C_2 },
 121   { "F_1", FR500_MAJOR_F_1 },
 122   { "F_2", FR500_MAJOR_F_2 },
 123   { "F_3", FR500_MAJOR_F_3 },
 124   { "F_4", FR500_MAJOR_F_4 },
 125   { "F_5", FR500_MAJOR_F_5 },
 126   { "F_6", FR500_MAJOR_F_6 },
 127   { "F_7", FR500_MAJOR_F_7 },
 128   { "F_8", FR500_MAJOR_F_8 },
 129   { "M_1", FR500_MAJOR_M_1 },
 130   { "M_2", FR500_MAJOR_M_2 },
 131   { "M_3", FR500_MAJOR_M_3 },
 132   { "M_4", FR500_MAJOR_M_4 },
 133   { "M_5", FR500_MAJOR_M_5 },
 134   { "M_6", FR500_MAJOR_M_6 },
 135   { "M_7", FR500_MAJOR_M_7 },
 136   { "M_8", FR500_MAJOR_M_8 },
 137   { 0, 0 }
 138 };
 139
 140 const CGEN_ATTR_TABLE frv_cgen_ifield_attr_table[] =
 141 {
 142   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 143   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 144   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
 145   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
 146   { "RESERVED", &bool_attr[0], &bool_attr[0] },
 147   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
 148   { "SIGNED", &bool_attr[0], &bool_attr[0] },
 149   { 0, 0, 0 }
 150 };
 151
 152 const CGEN_ATTR_TABLE frv_cgen_hardware_attr_table[] =
 153 {
 154   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 155   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 156   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
 157   { "PC", &bool_attr[0], &bool_attr[0] },
 158   { "PROFILE", &bool_attr[0], &bool_attr[0] },
 159   { 0, 0, 0 }
 160 };
 161
 162 const CGEN_ATTR_TABLE frv_cgen_operand_attr_table[] =
 163 {
 164   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 165   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 166   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
 167   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
 168   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
 169   { "SIGNED", &bool_attr[0], &bool_attr[0] },
 170   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
 171   { "RELAX", &bool_attr[0], &bool_attr[0] },
 172   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
 173   { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
 174   { 0, 0, 0 }
 175 };
 176
 177 const CGEN_ATTR_TABLE frv_cgen_insn_attr_table[] =
 178 {
 179   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 180   { "UNIT", & UNIT_attr[0], & UNIT_attr[0] },
 181   { "FR400-MAJOR", & FR400_MAJOR_attr[0], & FR400_MAJOR_attr[0] },
 182   { "FR500-MAJOR", & FR500_MAJOR_attr[0], & FR500_MAJOR_attr[0] },
 183   { "ALIAS", &bool_attr[0], &bool_attr[0] },
 184   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 185   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
 186   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
 187   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
 188   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 189   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
 190   { "RELAX", &bool_attr[0], &bool_attr[0] },
 191   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
 192   { "PBB", &bool_attr[0], &bool_attr[0] },
 193   { "PRIVILEGED", &bool_attr[0], &bool_attr[0] },
 194   { "NON-EXCEPTING", &bool_attr[0], &bool_attr[0] },
 195   { "CONDITIONAL", &bool_attr[0], &bool_attr[0] },
 196   { "FR-ACCESS", &bool_attr[0], &bool_attr[0] },
 197   { "PRESERVE-OVF", &bool_attr[0], &bool_attr[0] },
 198   { 0, 0, 0 }
 199 };
 200
 201 /* Instruction set variants.  */
 202
 203 static const CGEN_ISA frv_cgen_isa_table[] = {
 204   { "frv", 32, 32, 32, 32 },
 205   { 0, 0, 0, 0, 0 }
 206 };
 207
 208 /* Machine variants.  */
 209
 210 static const CGEN_MACH frv_cgen_mach_table[] = {
 211   { "frv", "frv", MACH_FRV, 0 },
 212   { "fr500", "fr500", MACH_FR500, 0 },
 213   { "tomcat", "tomcat", MACH_TOMCAT, 0 },
 214   { "fr400", "fr400", MACH_FR400, 0 },
 215   { "simple", "simple", MACH_SIMPLE, 0 },
 216   { 0, 0, 0, 0 }
 217 };
 218
 219 static CGEN_KEYWORD_ENTRY frv_cgen_opval_gr_names_entries[] =
 220 {
 221   { "sp", 1, {0, {0}}, 0, 0 },
 222   { "fp", 2, {0, {0}}, 0, 0 },
 223   { "gr0", 0, {0, {0}}, 0, 0 },
 224   { "gr1", 1, {0, {0}}, 0, 0 },
 225   { "gr2", 2, {0, {0}}, 0, 0 },
 226   { "gr3", 3, {0, {0}}, 0, 0 },
 227   { "gr4", 4, {0, {0}}, 0, 0 },
 228   { "gr5", 5, {0, {0}}, 0, 0 },
 229   { "gr6", 6, {0, {0}}, 0, 0 },
 230   { "gr7", 7, {0, {0}}, 0, 0 },
 231   { "gr8", 8, {0, {0}}, 0, 0 },
 232   { "gr9", 9, {0, {0}}, 0, 0 },
 233   { "gr10", 10, {0, {0}}, 0, 0 },
 234   { "gr11", 11, {0, {0}}, 0, 0 },
 235   { "gr12", 12, {0, {0}}, 0, 0 },
 236   { "gr13", 13, {0, {0}}, 0, 0 },
 237   { "gr14", 14, {0, {0}}, 0, 0 },
 238   { "gr15", 15, {0, {0}}, 0, 0 },
 239   { "gr16", 16, {0, {0}}, 0, 0 },
 240   { "gr17", 17, {0, {0}}, 0, 0 },
 241   { "gr18", 18, {0, {0}}, 0, 0 },
 242   { "gr19", 19, {0, {0}}, 0, 0 },
 243   { "gr20", 20, {0, {0}}, 0, 0 },
 244   { "gr21", 21, {0, {0}}, 0, 0 },
 245   { "gr22", 22, {0, {0}}, 0, 0 },
 246   { "gr23", 23, {0, {0}}, 0, 0 },
 247   { "gr24", 24, {0, {0}}, 0, 0 },
 248   { "gr25", 25, {0, {0}}, 0, 0 },
 249   { "gr26", 26, {0, {0}}, 0, 0 },
 250   { "gr27", 27, {0, {0}}, 0, 0 },
 251   { "gr28", 28, {0, {0}}, 0, 0 },
 252   { "gr29", 29, {0, {0}}, 0, 0 },
 253   { "gr30", 30, {0, {0}}, 0, 0 },
 254   { "gr31", 31, {0, {0}}, 0, 0 },
 255   { "gr32", 32, {0, {0}}, 0, 0 },
 256   { "gr33", 33, {0, {0}}, 0, 0 },
 257   { "gr34", 34, {0, {0}}, 0, 0 },
 258   { "gr35", 35, {0, {0}}, 0, 0 },
 259   { "gr36", 36, {0, {0}}, 0, 0 },
 260   { "gr37", 37, {0, {0}}, 0, 0 },
 261   { "gr38", 38, {0, {0}}, 0, 0 },
 262   { "gr39", 39, {0, {0}}, 0, 0 },
 263   { "gr40", 40, {0, {0}}, 0, 0 },
 264   { "gr41", 41, {0, {0}}, 0, 0 },
 265   { "gr42", 42, {0, {0}}, 0, 0 },
 266   { "gr43", 43, {0, {0}}, 0, 0 },
 267   { "gr44", 44, {0, {0}}, 0, 0 },
 268   { "gr45", 45, {0, {0}}, 0, 0 },
 269   { "gr46", 46, {0, {0}}, 0, 0 },
 270   { "gr47", 47, {0, {0}}, 0, 0 },
 271   { "gr48", 48, {0, {0}}, 0, 0 },
 272   { "gr49", 49, {0, {0}}, 0, 0 },
 273   { "gr50", 50, {0, {0}}, 0, 0 },
 274   { "gr51", 51, {0, {0}}, 0, 0 },
 275   { "gr52", 52, {0, {0}}, 0, 0 },
 276   { "gr53", 53, {0, {0}}, 0, 0 },
 277   { "gr54", 54, {0, {0}}, 0, 0 },
 278   { "gr55", 55, {0, {0}}, 0, 0 },
 279   { "gr56", 56, {0, {0}}, 0, 0 },
 280   { "gr57", 57, {0, {0}}, 0, 0 },
 281   { "gr58", 58, {0, {0}}, 0, 0 },
 282   { "gr59", 59, {0, {0}}, 0, 0 },
 283   { "gr60", 60, {0, {0}}, 0, 0 },
 284   { "gr61", 61, {0, {0}}, 0, 0 },
 285   { "gr62", 62, {0, {0}}, 0, 0 },
 286   { "gr63", 63, {0, {0}}, 0, 0 }
 287 };
 288
 289 CGEN_KEYWORD frv_cgen_opval_gr_names =
 290 {
 291   & frv_cgen_opval_gr_names_entries[0],
 292   66,
 293   0, 0, 0, 0, ""
 294 };
 295
 296 static CGEN_KEYWORD_ENTRY frv_cgen_opval_fr_names_entries[] =
 297 {
 298   { "fr0", 0, {0, {0}}, 0, 0 },
 299   { "fr1", 1, {0, {0}}, 0, 0 },
 300   { "fr2", 2, {0, {0}}, 0, 0 },
 301   { "fr3", 3, {0, {0}}, 0, 0 },
 302   { "fr4", 4, {0, {0}}, 0, 0 },
 303   { "fr5", 5, {0, {0}}, 0, 0 },
 304   { "fr6", 6, {0, {0}}, 0, 0 },
 305   { "fr7", 7, {0, {0}}, 0, 0 },
 306   { "fr8", 8, {0, {0}}, 0, 0 },
 307   { "fr9", 9, {0, {0}}, 0, 0 },
 308   { "fr10", 10, {0, {0}}, 0, 0 },
 309   { "fr11", 11, {0, {0}}, 0, 0 },
 310   { "fr12", 12, {0, {0}}, 0, 0 },
 311   { "fr13", 13, {0, {0}}, 0, 0 },
 312   { "fr14", 14, {0, {0}}, 0, 0 },
 313   { "fr15", 15, {0, {0}}, 0, 0 },
 314   { "fr16", 16, {0, {0}}, 0, 0 },
 315   { "fr17", 17, {0, {0}}, 0, 0 },
 316   { "fr18", 18, {0, {0}}, 0, 0 },
 317   { "fr19", 19, {0, {0}}, 0, 0 },
 318   { "fr20", 20, {0, {0}}, 0, 0 },
 319   { "fr21", 21, {0, {0}}, 0, 0 },
 320   { "fr22", 22, {0, {0}}, 0, 0 },
 321   { "fr23", 23, {0, {0}}, 0, 0 },
 322   { "fr24", 24, {0, {0}}, 0, 0 },
 323   { "fr25", 25, {0, {0}}, 0, 0 },
 324   { "fr26", 26, {0, {0}}, 0, 0 },
 325   { "fr27", 27, {0, {0}}, 0, 0 },
 326   { "fr28", 28, {0, {0}}, 0, 0 },
 327   { "fr29", 29, {0, {0}}, 0, 0 },
 328   { "fr30", 30, {0, {0}}, 0, 0 },
 329   { "fr31", 31, {0, {0}}, 0, 0 },
 330   { "fr32", 32, {0, {0}}, 0, 0 },
 331   { "fr33", 33, {0, {0}}, 0, 0 },
 332   { "fr34", 34, {0, {0}}, 0, 0 },
 333   { "fr35", 35, {0, {0}}, 0, 0 },
 334   { "fr36", 36, {0, {0}}, 0, 0 },
 335   { "fr37", 37, {0, {0}}, 0, 0 },
 336   { "fr38", 38, {0, {0}}, 0, 0 },
 337   { "fr39", 39, {0, {0}}, 0, 0 },
 338   { "fr40", 40, {0, {0}}, 0, 0 },
 339   { "fr41", 41, {0, {0}}, 0, 0 },
 340   { "fr42", 42, {0, {0}}, 0, 0 },
 341   { "fr43", 43, {0, {0}}, 0, 0 },
 342   { "fr44", 44, {0, {0}}, 0, 0 },
 343   { "fr45", 45, {0, {0}}, 0, 0 },
 344   { "fr46", 46, {0, {0}}, 0, 0 },
 345   { "fr47", 47, {0, {0}}, 0, 0 },
 346   { "fr48", 48, {0, {0}}, 0, 0 },
 347   { "fr49", 49, {0, {0}}, 0, 0 },
 348   { "fr50", 50, {0, {0}}, 0, 0 },
 349   { "fr51", 51, {0, {0}}, 0, 0 },
 350   { "fr52", 52, {0, {0}}, 0, 0 },
 351   { "fr53", 53, {0, {0}}, 0, 0 },
 352   { "fr54", 54, {0, {0}}, 0, 0 },
 353   { "fr55", 55, {0, {0}}, 0, 0 },
 354   { "fr56", 56, {0, {0}}, 0, 0 },
 355   { "fr57", 57, {0, {0}}, 0, 0 },
 356   { "fr58", 58, {0, {0}}, 0, 0 },
 357   { "fr59", 59, {0, {0}}, 0, 0 },
 358   { "fr60", 60, {0, {0}}, 0, 0 },
 359   { "fr61", 61, {0, {0}}, 0, 0 },
 360   { "fr62", 62, {0, {0}}, 0, 0 },
 361   { "fr63", 63, {0, {0}}, 0, 0 }
 362 };
 363
 364 CGEN_KEYWORD frv_cgen_opval_fr_names =
 365 {
 366   & frv_cgen_opval_fr_names_entries[0],
 367   64,
 368   0, 0, 0, 0, ""
 369 };
 370
 371 static CGEN_KEYWORD_ENTRY frv_cgen_opval_cpr_names_entries[] =
 372 {
 373   { "cpr0", 0, {0, {0}}, 0, 0 },
 374   { "cpr1", 1, {0, {0}}, 0, 0 },
 375   { "cpr2", 2, {0, {0}}, 0, 0 },
 376   { "cpr3", 3, {0, {0}}, 0, 0 },
 377   { "cpr4", 4, {0, {0}}, 0, 0 },
 378   { "cpr5", 5, {0, {0}}, 0, 0 },
 379   { "cpr6", 6, {0, {0}}, 0, 0 },
 380   { "cpr7", 7, {0, {0}}, 0, 0 },
 381   { "cpr8", 8, {0, {0}}, 0, 0 },
 382   { "cpr9", 9, {0, {0}}, 0, 0 },
 383   { "cpr10", 10, {0, {0}}, 0, 0 },
 384   { "cpr11", 11, {0, {0}}, 0, 0 },
 385   { "cpr12", 12, {0, {0}}, 0, 0 },
 386   { "cpr13", 13, {0, {0}}, 0, 0 },
 387   { "cpr14", 14, {0, {0}}, 0, 0 },
 388   { "cpr15", 15, {0, {0}}, 0, 0 },
 389   { "cpr16", 16, {0, {0}}, 0, 0 },
 390   { "cpr17", 17, {0, {0}}, 0, 0 },
 391   { "cpr18", 18, {0, {0}}, 0, 0 },
 392   { "cpr19", 19, {0, {0}}, 0, 0 },
 393   { "cpr20", 20, {0, {0}}, 0, 0 },
 394   { "cpr21", 21, {0, {0}}, 0, 0 },
 395   { "cpr22", 22, {0, {0}}, 0, 0 },
 396   { "cpr23", 23, {0, {0}}, 0, 0 },
 397   { "cpr24", 24, {0, {0}}, 0, 0 },
 398   { "cpr25", 25, {0, {0}}, 0, 0 },
 399   { "cpr26", 26, {0, {0}}, 0, 0 },
 400   { "cpr27", 27, {0, {0}}, 0, 0 },
 401   { "cpr28", 28, {0, {0}}, 0, 0 },
 402   { "cpr29", 29, {0, {0}}, 0, 0 },
 403   { "cpr30", 30, {0, {0}}, 0, 0 },
 404   { "cpr31", 31, {0, {0}}, 0, 0 },
 405   { "cpr32", 32, {0, {0}}, 0, 0 },
 406   { "cpr33", 33, {0, {0}}, 0, 0 },
 407   { "cpr34", 34, {0, {0}}, 0, 0 },
 408   { "cpr35", 35, {0, {0}}, 0, 0 },
 409   { "cpr36", 36, {0, {0}}, 0, 0 },
 410   { "cpr37", 37, {0, {0}}, 0, 0 },
 411   { "cpr38", 38, {0, {0}}, 0, 0 },
 412   { "cpr39", 39, {0, {0}}, 0, 0 },
 413   { "cpr40", 40, {0, {0}}, 0, 0 },
 414   { "cpr41", 41, {0, {0}}, 0, 0 },
 415   { "cpr42", 42, {0, {0}}, 0, 0 },
 416   { "cpr43", 43, {0, {0}}, 0, 0 },
 417   { "cpr44", 44, {0, {0}}, 0, 0 },
 418   { "cpr45", 45, {0, {0}}, 0, 0 },
 419   { "cpr46", 46, {0, {0}}, 0, 0 },
 420   { "cpr47", 47, {0, {0}}, 0, 0 },
 421   { "cpr48", 48, {0, {0}}, 0, 0 },
 422   { "cpr49", 49, {0, {0}}, 0, 0 },
 423   { "cpr50", 50, {0, {0}}, 0, 0 },
 424   { "cpr51", 51, {0, {0}}, 0, 0 },
 425   { "cpr52", 52, {0, {0}}, 0, 0 },
 426   { "cpr53", 53, {0, {0}}, 0, 0 },
 427   { "cpr54", 54, {0, {0}}, 0, 0 },
 428   { "cpr55", 55, {0, {0}}, 0, 0 },
 429   { "cpr56", 56, {0, {0}}, 0, 0 },
 430   { "cpr57", 57, {0, {0}}, 0, 0 },
 431   { "cpr58", 58, {0, {0}}, 0, 0 },
 432   { "cpr59", 59, {0, {0}}, 0, 0 },
 433   { "cpr60", 60, {0, {0}}, 0, 0 },
 434   { "cpr61", 61, {0, {0}}, 0, 0 },
 435   { "cpr62", 62, {0, {0}}, 0, 0 },
 436   { "cpr63", 63, {0, {0}}, 0, 0 }
 437 };
 438
 439 CGEN_KEYWORD frv_cgen_opval_cpr_names =
 440 {
 441   & frv_cgen_opval_cpr_names_entries[0],
 442   64,
 443   0, 0, 0, 0, ""
 444 };
 445
 446 static CGEN_KEYWORD_ENTRY frv_cgen_opval_spr_names_entries[] =
 447 {
 448   { "psr", 0, {0, {0}}, 0, 0 },
 449   { "pcsr", 1, {0, {0}}, 0, 0 },
 450   { "bpcsr", 2, {0, {0}}, 0, 0 },
 451   { "tbr", 3, {0, {0}}, 0, 0 },
 452   { "bpsr", 4, {0, {0}}, 0, 0 },
 453   { "hsr0", 16, {0, {0}}, 0, 0 },
 454   { "hsr1", 17, {0, {0}}, 0, 0 },
 455   { "hsr2", 18, {0, {0}}, 0, 0 },
 456   { "hsr3", 19, {0, {0}}, 0, 0 },
 457   { "hsr4", 20, {0, {0}}, 0, 0 },
 458   { "hsr5", 21, {0, {0}}, 0, 0 },
 459   { "hsr6", 22, {0, {0}}, 0, 0 },
 460   { "hsr7", 23, {0, {0}}, 0, 0 },
 461   { "hsr8", 24, {0, {0}}, 0, 0 },
 462   { "hsr9", 25, {0, {0}}, 0, 0 },
 463   { "hsr10", 26, {0, {0}}, 0, 0 },
 464   { "hsr11", 27, {0, {0}}, 0, 0 },
 465   { "hsr12", 28, {0, {0}}, 0, 0 },
 466   { "hsr13", 29, {0, {0}}, 0, 0 },
 467   { "hsr14", 30, {0, {0}}, 0, 0 },
 468   { "hsr15", 31, {0, {0}}, 0, 0 },
 469   { "hsr16", 32, {0, {0}}, 0, 0 },
 470   { "hsr17", 33, {0, {0}}, 0, 0 },
 471   { "hsr18", 34, {0, {0}}, 0, 0 },
 472   { "hsr19", 35, {0, {0}}, 0, 0 },
 473   { "hsr20", 36, {0, {0}}, 0, 0 },
 474   { "hsr21", 37, {0, {0}}, 0, 0 },
 475   { "hsr22", 38, {0, {0}}, 0, 0 },
 476   { "hsr23", 39, {0, {0}}, 0, 0 },
 477   { "hsr24", 40, {0, {0}}, 0, 0 },
 478   { "hsr25", 41, {0, {0}}, 0, 0 },
 479   { "hsr26", 42, {0, {0}}, 0, 0 },
 480   { "hsr27", 43, {0, {0}}, 0, 0 },
 481   { "hsr28", 44, {0, {0}}, 0, 0 },
 482   { "hsr29", 45, {0, {0}}, 0, 0 },
 483   { "hsr30", 46, {0, {0}}, 0, 0 },
 484   { "hsr31", 47, {0, {0}}, 0, 0 },
 485   { "hsr32", 48, {0, {0}}, 0, 0 },
 486   { "hsr33", 49, {0, {0}}, 0, 0 },
 487   { "hsr34", 50, {0, {0}}, 0, 0 },
 488   { "hsr35", 51, {0, {0}}, 0, 0 },
 489   { "hsr36", 52, {0, {0}}, 0, 0 },
 490   { "hsr37", 53, {0, {0}}, 0, 0 },
 491   { "hsr38", 54, {0, {0}}, 0, 0 },
 492   { "hsr39", 55, {0, {0}}, 0, 0 },
 493   { "hsr40", 56, {0, {0}}, 0, 0 },
 494   { "hsr41", 57, {0, {0}}, 0, 0 },
 495   { "hsr42", 58, {0, {0}}, 0, 0 },
 496   { "hsr43", 59, {0, {0}}, 0, 0 },
 497   { "hsr44", 60, {0, {0}}, 0, 0 },
 498   { "hsr45", 61, {0, {0}}, 0, 0 },
 499   { "hsr46", 62, {0, {0}}, 0, 0 },
 500   { "hsr47", 63, {0, {0}}, 0, 0 },
 501   { "hsr48", 64, {0, {0}}, 0, 0 },
 502   { "hsr49", 65, {0, {0}}, 0, 0 },
 503   { "hsr50", 66, {0, {0}}, 0, 0 },
 504   { "hsr51", 67, {0, {0}}, 0, 0 },
 505   { "hsr52", 68, {0, {0}}, 0, 0 },
 506   { "hsr53", 69, {0, {0}}, 0, 0 },
 507   { "hsr54", 70, {0, {0}}, 0, 0 },
 508   { "hsr55", 71, {0, {0}}, 0, 0 },
 509   { "hsr56", 72, {0, {0}}, 0, 0 },
 510   { "hsr57", 73, {0, {0}}, 0, 0 },
 511   { "hsr58", 74, {0, {0}}, 0, 0 },
 512   { "hsr59", 75, {0, {0}}, 0, 0 },
 513   { "hsr60", 76, {0, {0}}, 0, 0 },
 514   { "hsr61", 77, {0, {0}}, 0, 0 },
 515   { "hsr62", 78, {0, {0}}, 0, 0 },
 516   { "hsr63", 79, {0, {0}}, 0, 0 },
 517   { "ccr", 256, {0, {0}}, 0, 0 },
 518   { "cccr", 263, {0, {0}}, 0, 0 },
 519   { "lr", 272, {0, {0}}, 0, 0 },
 520   { "lcr", 273, {0, {0}}, 0, 0 },
 521   { "isr", 288, {0, {0}}, 0, 0 },
 522   { "neear0", 352, {0, {0}}, 0, 0 },
 523   { "neear1", 353, {0, {0}}, 0, 0 },
 524   { "neear2", 354, {0, {0}}, 0, 0 },
 525   { "neear3", 355, {0, {0}}, 0, 0 },
 526   { "neear4", 356, {0, {0}}, 0, 0 },
 527   { "neear5", 357, {0, {0}}, 0, 0 },
 528   { "neear6", 358, {0, {0}}, 0, 0 },
 529   { "neear7", 359, {0, {0}}, 0, 0 },
 530   { "neear8", 360, {0, {0}}, 0, 0 },
 531   { "neear9", 361, {0, {0}}, 0, 0 },
 532   { "neear10", 362, {0, {0}}, 0, 0 },
 533   { "neear11", 363, {0, {0}}, 0, 0 },
 534   { "neear12", 364, {0, {0}}, 0, 0 },
 535   { "neear13", 365, {0, {0}}, 0, 0 },
 536   { "neear14", 366, {0, {0}}, 0, 0 },
 537   { "neear15", 367, {0, {0}}, 0, 0 },
 538   { "neear16", 368, {0, {0}}, 0, 0 },
 539   { "neear17", 369, {0, {0}}, 0, 0 },
 540   { "neear18", 370, {0, {0}}, 0, 0 },
 541   { "neear19", 371, {0, {0}}, 0, 0 },
 542   { "neear20", 372, {0, {0}}, 0, 0 },
 543   { "neear21", 373, {0, {0}}, 0, 0 },
 544   { "neear22", 374, {0, {0}}, 0, 0 },
 545   { "neear23", 375, {0, {0}}, 0, 0 },
 546   { "neear24", 376, {0, {0}}, 0, 0 },
 547   { "neear25", 377, {0, {0}}, 0, 0 },
 548   { "neear26", 378, {0, {0}}, 0, 0 },
 549   { "neear27", 379, {0, {0}}, 0, 0 },
 550   { "neear28", 380, {0, {0}}, 0, 0 },
 551   { "neear29", 381, {0, {0}}, 0, 0 },
 552   { "neear30", 382, {0, {0}}, 0, 0 },
 553   { "neear31", 383, {0, {0}}, 0, 0 },
 554   { "nesr0", 384, {0, {0}}, 0, 0 },
 555   { "nesr1", 385, {0, {0}}, 0, 0 },
 556   { "nesr2", 386, {0, {0}}, 0, 0 },
 557   { "nesr3", 387, {0, {0}}, 0, 0 },
 558   { "nesr4", 388, {0, {0}}, 0, 0 },
 559   { "nesr5", 389, {0, {0}}, 0, 0 },
 560   { "nesr6", 390, {0, {0}}, 0, 0 },
 561   { "nesr7", 391, {0, {0}}, 0, 0 },
 562   { "nesr8", 392, {0, {0}}, 0, 0 },
 563   { "nesr9", 393, {0, {0}}, 0, 0 },
 564   { "nesr10", 394, {0, {0}}, 0, 0 },
 565   { "nesr11", 395, {0, {0}}, 0, 0 },
 566   { "nesr12", 396, {0, {0}}, 0, 0 },
 567   { "nesr13", 397, {0, {0}}, 0, 0 },
 568   { "nesr14", 398, {0, {0}}, 0, 0 },
 569   { "nesr15", 399, {0, {0}}, 0, 0 },
 570   { "nesr16", 400, {0, {0}}, 0, 0 },
 571   { "nesr17", 401, {0, {0}}, 0, 0 },
 572   { "nesr18", 402, {0, {0}}, 0, 0 },
 573   { "nesr19", 403, {0, {0}}, 0, 0 },
 574   { "nesr20", 404, {0, {0}}, 0, 0 },
 575   { "nesr21", 405, {0, {0}}, 0, 0 },
 576   { "nesr22", 406, {0, {0}}, 0, 0 },
 577   { "nesr23", 407, {0, {0}}, 0, 0 },
 578   { "nesr24", 408, {0, {0}}, 0, 0 },
 579   { "nesr25", 409, {0, {0}}, 0, 0 },
 580   { "nesr26", 410, {0, {0}}, 0, 0 },
 581   { "nesr27", 411, {0, {0}}, 0, 0 },
 582   { "nesr28", 412, {0, {0}}, 0, 0 },
 583   { "nesr29", 413, {0, {0}}, 0, 0 },
 584   { "nesr30", 414, {0, {0}}, 0, 0 },
 585   { "nesr31", 415, {0, {0}}, 0, 0 },
 586   { "necr", 416, {0, {0}}, 0, 0 },
 587   { "gner0", 432, {0, {0}}, 0, 0 },
 588   { "gner1", 433, {0, {0}}, 0, 0 },
 589   { "fner0", 434, {0, {0}}, 0, 0 },
 590   { "fner1", 435, {0, {0}}, 0, 0 },
 591   { "epcr0", 512, {0, {0}}, 0, 0 },
 592   { "epcr1", 513, {0, {0}}, 0, 0 },
 593   { "epcr2", 514, {0, {0}}, 0, 0 },
 594   { "epcr3", 515, {0, {0}}, 0, 0 },
 595   { "epcr4", 516, {0, {0}}, 0, 0 },
 596   { "epcr5", 517, {0, {0}}, 0, 0 },
 597   { "epcr6", 518, {0, {0}}, 0, 0 },
 598   { "epcr7", 519, {0, {0}}, 0, 0 },
 599   { "epcr8", 520, {0, {0}}, 0, 0 },
 600   { "epcr9", 521, {0, {0}}, 0, 0 },
 601   { "epcr10", 522, {0, {0}}, 0, 0 },
 602   { "epcr11", 523, {0, {0}}, 0, 0 },
 603   { "epcr12", 524, {0, {0}}, 0, 0 },
 604   { "epcr13", 525, {0, {0}}, 0, 0 },
 605   { "epcr14", 526, {0, {0}}, 0, 0 },
 606   { "epcr15", 527, {0, {0}}, 0, 0 },
 607   { "epcr16", 528, {0, {0}}, 0, 0 },
 608   { "epcr17", 529, {0, {0}}, 0, 0 },
 609   { "epcr18", 530, {0, {0}}, 0, 0 },
 610   { "epcr19", 531, {0, {0}}, 0, 0 },
 611   { "epcr20", 532, {0, {0}}, 0, 0 },
 612   { "epcr21", 533, {0, {0}}, 0, 0 },
 613   { "epcr22", 534, {0, {0}}, 0, 0 },
 614   { "epcr23", 535, {0, {0}}, 0, 0 },
 615   { "epcr24", 536, {0, {0}}, 0, 0 },
 616   { "epcr25", 537, {0, {0}}, 0, 0 },
 617   { "epcr26", 538, {0, {0}}, 0, 0 },
 618   { "epcr27", 539, {0, {0}}, 0, 0 },
 619   { "epcr28", 540, {0, {0}}, 0, 0 },
 620   { "epcr29", 541, {0, {0}}, 0, 0 },
 621   { "epcr30", 542, {0, {0}}, 0, 0 },
 622   { "epcr31", 543, {0, {0}}, 0, 0 },
 623   { "epcr32", 544, {0, {0}}, 0, 0 },
 624   { "epcr33", 545, {0, {0}}, 0, 0 },
 625   { "epcr34", 546, {0, {0}}, 0, 0 },
 626   { "epcr35", 547, {0, {0}}, 0, 0 },
 627   { "epcr36", 548, {0, {0}}, 0, 0 },
 628   { "epcr37", 549, {0, {0}}, 0, 0 },
 629   { "epcr38", 550, {0, {0}}, 0, 0 },
 630   { "epcr39", 551, {0, {0}}, 0, 0 },
 631   { "epcr40", 552, {0, {0}}, 0, 0 },
 632   { "epcr41", 553, {0, {0}}, 0, 0 },
 633   { "epcr42", 554, {0, {0}}, 0, 0 },
 634   { "epcr43", 555, {0, {0}}, 0, 0 },
 635   { "epcr44", 556, {0, {0}}, 0, 0 },
 636   { "epcr45", 557, {0, {0}}, 0, 0 },
 637   { "epcr46", 558, {0, {0}}, 0, 0 },
 638   { "epcr47", 559, {0, {0}}, 0, 0 },
 639   { "epcr48", 560, {0, {0}}, 0, 0 },
 640   { "epcr49", 561, {0, {0}}, 0, 0 },
 641   { "epcr50", 562, {0, {0}}, 0, 0 },
 642   { "epcr51", 563, {0, {0}}, 0, 0 },
 643   { "epcr52", 564, {0, {0}}, 0, 0 },
 644   { "epcr53", 565, {0, {0}}, 0, 0 },
 645   { "epcr54", 566, {0, {0}}, 0, 0 },
 646   { "epcr55", 567, {0, {0}}, 0, 0 },
 647   { "epcr56", 568, {0, {0}}, 0, 0 },
 648   { "epcr57", 569, {0, {0}}, 0, 0 },
 649   { "epcr58", 570, {0, {0}}, 0, 0 },
 650   { "epcr59", 571, {0, {0}}, 0, 0 },
 651   { "epcr60", 572, {0, {0}}, 0, 0 },
 652   { "epcr61", 573, {0, {0}}, 0, 0 },
 653   { "epcr62", 574, {0, {0}}, 0, 0 },
 654   { "epcr63", 575, {0, {0}}, 0, 0 },
 655   { "esr0", 576, {0, {0}}, 0, 0 },
 656   { "esr1", 577, {0, {0}}, 0, 0 },
 657   { "esr2", 578, {0, {0}}, 0, 0 },
 658   { "esr3", 579, {0, {0}}, 0, 0 },
 659   { "esr4", 580, {0, {0}}, 0, 0 },
 660   { "esr5", 581, {0, {0}}, 0, 0 },
 661   { "esr6", 582, {0, {0}}, 0, 0 },
 662   { "esr7", 583, {0, {0}}, 0, 0 },
 663   { "esr8", 584, {0, {0}}, 0, 0 },
 664   { "esr9", 585, {0, {0}}, 0, 0 },
 665   { "esr10", 586, {0, {0}}, 0, 0 },
 666   { "esr11", 587, {0, {0}}, 0, 0 },
 667   { "esr12", 588, {0, {0}}, 0, 0 },
 668   { "esr13", 589, {0, {0}}, 0, 0 },
 669   { "esr14", 590, {0, {0}}, 0, 0 },
 670   { "esr15", 591, {0, {0}}, 0, 0 },
 671   { "esr16", 592, {0, {0}}, 0, 0 },
 672   { "esr17", 593, {0, {0}}, 0, 0 },
 673   { "esr18", 594, {0, {0}}, 0, 0 },
 674   { "esr19", 595, {0, {0}}, 0, 0 },
 675   { "esr20", 596, {0, {0}}, 0, 0 },
 676   { "esr21", 597, {0, {0}}, 0, 0 },
 677   { "esr22", 598, {0, {0}}, 0, 0 },
 678   { "esr23", 599, {0, {0}}, 0, 0 },
 679   { "esr24", 600, {0, {0}}, 0, 0 },
 680   { "esr25", 601, {0, {0}}, 0, 0 },
 681   { "esr26", 602, {0, {0}}, 0, 0 },
 682   { "esr27", 603, {0, {0}}, 0, 0 },
 683   { "esr28", 604, {0, {0}}, 0, 0 },
 684   { "esr29", 605, {0, {0}}, 0, 0 },
 685   { "esr30", 606, {0, {0}}, 0, 0 },
 686   { "esr31", 607, {0, {0}}, 0, 0 },
 687   { "esr32", 608, {0, {0}}, 0, 0 },
 688   { "esr33", 609, {0, {0}}, 0, 0 },
 689   { "esr34", 610, {0, {0}}, 0, 0 },
 690   { "esr35", 611, {0, {0}}, 0, 0 },
 691   { "esr36", 612, {0, {0}}, 0, 0 },
 692   { "esr37", 613, {0, {0}}, 0, 0 },
 693   { "esr38", 614, {0, {0}}, 0, 0 },
 694   { "esr39", 615, {0, {0}}, 0, 0 },
 695   { "esr40", 616, {0, {0}}, 0, 0 },
 696   { "esr41", 617, {0, {0}}, 0, 0 },
 697   { "esr42", 618, {0, {0}}, 0, 0 },
 698   { "esr43", 619, {0, {0}}, 0, 0 },
 699   { "esr44", 620, {0, {0}}, 0, 0 },
 700   { "esr45", 621, {0, {0}}, 0, 0 },
 701   { "esr46", 622, {0, {0}}, 0, 0 },
 702   { "esr47", 623, {0, {0}}, 0, 0 },
 703   { "esr48", 624, {0, {0}}, 0, 0 },
 704   { "esr49", 625, {0, {0}}, 0, 0 },
 705   { "esr50", 626, {0, {0}}, 0, 0 },
 706   { "esr51", 627, {0, {0}}, 0, 0 },
 707   { "esr52", 628, {0, {0}}, 0, 0 },
 708   { "esr53", 629, {0, {0}}, 0, 0 },
 709   { "esr54", 630, {0, {0}}, 0, 0 },
 710   { "esr55", 631, {0, {0}}, 0, 0 },
 711   { "esr56", 632, {0, {0}}, 0, 0 },
 712   { "esr57", 633, {0, {0}}, 0, 0 },
 713   { "esr58", 634, {0, {0}}, 0, 0 },
 714   { "esr59", 635, {0, {0}}, 0, 0 },
 715   { "esr60", 636, {0, {0}}, 0, 0 },
 716   { "esr61", 637, {0, {0}}, 0, 0 },
 717   { "esr62", 638, {0, {0}}, 0, 0 },
 718   { "esr63", 639, {0, {0}}, 0, 0 },
 719   { "eir0", 640, {0, {0}}, 0, 0 },
 720   { "eir1", 641, {0, {0}}, 0, 0 },
 721   { "eir2", 642, {0, {0}}, 0, 0 },
 722   { "eir3", 643, {0, {0}}, 0, 0 },
 723   { "eir4", 644, {0, {0}}, 0, 0 },
 724   { "eir5", 645, {0, {0}}, 0, 0 },
 725   { "eir6", 646, {0, {0}}, 0, 0 },
 726   { "eir7", 647, {0, {0}}, 0, 0 },
 727   { "eir8", 648, {0, {0}}, 0, 0 },
 728   { "eir9", 649, {0, {0}}, 0, 0 },
 729   { "eir10", 650, {0, {0}}, 0, 0 },
 730   { "eir11", 651, {0, {0}}, 0, 0 },
 731   { "eir12", 652, {0, {0}}, 0, 0 },
 732   { "eir13", 653, {0, {0}}, 0, 0 },
 733   { "eir14", 654, {0, {0}}, 0, 0 },
 734   { "eir15", 655, {0, {0}}, 0, 0 },
 735   { "eir16", 656, {0, {0}}, 0, 0 },
 736   { "eir17", 657, {0, {0}}, 0, 0 },
 737   { "eir18", 658, {0, {0}}, 0, 0 },
 738   { "eir19", 659, {0, {0}}, 0, 0 },
 739   { "eir20", 660, {0, {0}}, 0, 0 },
 740   { "eir21", 661, {0, {0}}, 0, 0 },
 741   { "eir22", 662, {0, {0}}, 0, 0 },
 742   { "eir23", 663, {0, {0}}, 0, 0 },
 743   { "eir24", 664, {0, {0}}, 0, 0 },
 744   { "eir25", 665, {0, {0}}, 0, 0 },
 745   { "eir26", 666, {0, {0}}, 0, 0 },
 746   { "eir27", 667, {0, {0}}, 0, 0 },
 747   { "eir28", 668, {0, {0}}, 0, 0 },
 748   { "eir29", 669, {0, {0}}, 0, 0 },
 749   { "eir30", 670, {0, {0}}, 0, 0 },
 750   { "eir31", 671, {0, {0}}, 0, 0 },
 751   { "esfr0", 672, {0, {0}}, 0, 0 },
 752   { "esfr1", 673, {0, {0}}, 0, 0 },
 753   { "sr0", 768, {0, {0}}, 0, 0 },
 754   { "sr1", 769, {0, {0}}, 0, 0 },
 755   { "sr2", 770, {0, {0}}, 0, 0 },
 756   { "sr3", 771, {0, {0}}, 0, 0 },
 757   { "fsr0", 1024, {0, {0}}, 0, 0 },
 758   { "fsr1", 1025, {0, {0}}, 0, 0 },
 759   { "fsr2", 1026, {0, {0}}, 0, 0 },
 760   { "fsr3", 1027, {0, {0}}, 0, 0 },
 761   { "fsr4", 1028, {0, {0}}, 0, 0 },
 762   { "fsr5", 1029, {0, {0}}, 0, 0 },
 763   { "fsr6", 1030, {0, {0}}, 0, 0 },
 764   { "fsr7", 1031, {0, {0}}, 0, 0 },
 765   { "fsr8", 1032, {0, {0}}, 0, 0 },
 766   { "fsr9", 1033, {0, {0}}, 0, 0 },
 767   { "fsr10", 1034, {0, {0}}, 0, 0 },
 768   { "fsr11", 1035, {0, {0}}, 0, 0 },
 769   { "fsr12", 1036, {0, {0}}, 0, 0 },
 770   { "fsr13", 1037, {0, {0}}, 0, 0 },
 771   { "fsr14", 1038, {0, {0}}, 0, 0 },
 772   { "fsr15", 1039, {0, {0}}, 0, 0 },
 773   { "fsr16", 1040, {0, {0}}, 0, 0 },
 774   { "fsr17", 1041, {0, {0}}, 0, 0 },
 775   { "fsr18", 1042, {0, {0}}, 0, 0 },
 776   { "fsr19", 1043, {0, {0}}, 0, 0 },
 777   { "fsr20", 1044, {0, {0}}, 0, 0 },
 778   { "fsr21", 1045, {0, {0}}, 0, 0 },
 779   { "fsr22", 1046, {0, {0}}, 0, 0 },
 780   { "fsr23", 1047, {0, {0}}, 0, 0 },
 781   { "fsr24", 1048, {0, {0}}, 0, 0 },
 782   { "fsr25", 1049, {0, {0}}, 0, 0 },
 783   { "fsr26", 1050, {0, {0}}, 0, 0 },
 784   { "fsr27", 1051, {0, {0}}, 0, 0 },
 785   { "fsr28", 1052, {0, {0}}, 0, 0 },
 786   { "fsr29", 1053, {0, {0}}, 0, 0 },
 787   { "fsr30", 1054, {0, {0}}, 0, 0 },
 788   { "fsr31", 1055, {0, {0}}, 0, 0 },
 789   { "fsr32", 1056, {0, {0}}, 0, 0 },
 790   { "fsr33", 1057, {0, {0}}, 0, 0 },
 791   { "fsr34", 1058, {0, {0}}, 0, 0 },
 792   { "fsr35", 1059, {0, {0}}, 0, 0 },
 793   { "fsr36", 1060, {0, {0}}, 0, 0 },
 794   { "fsr37", 1061, {0, {0}}, 0, 0 },
 795   { "fsr38", 1062, {0, {0}}, 0, 0 },
 796   { "fsr39", 1063, {0, {0}}, 0, 0 },
 797   { "fsr40", 1064, {0, {0}}, 0, 0 },
 798   { "fsr41", 1065, {0, {0}}, 0, 0 },
 799   { "fsr42", 1066, {0, {0}}, 0, 0 },
 800   { "fsr43", 1067, {0, {0}}, 0, 0 },
 801   { "fsr44", 1068, {0, {0}}, 0, 0 },
 802   { "fsr45", 1069, {0, {0}}, 0, 0 },
 803   { "fsr46", 1070, {0, {0}}, 0, 0 },
 804   { "fsr47", 1071, {0, {0}}, 0, 0 },
 805   { "fsr48", 1072, {0, {0}}, 0, 0 },
 806   { "fsr49", 1073, {0, {0}}, 0, 0 },
 807   { "fsr50", 1074, {0, {0}}, 0, 0 },
 808   { "fsr51", 1075, {0, {0}}, 0, 0 },
 809   { "fsr52", 1076, {0, {0}}, 0, 0 },
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 820   { "fsr63", 1087, {0, {0}}, 0, 0 },
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 911   { "msr24", 1304, {0, {0}}, 0, 0 },
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 922   { "msr35", 1315, {0, {0}}, 0, 0 },
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 924   { "msr37", 1317, {0, {0}}, 0, 0 },
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 945   { "msr58", 1338, {0, {0}}, 0, 0 },
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 950   { "msr63", 1343, {0, {0}}, 0, 0 },
 951   { "mqop0", 1344, {0, {0}}, 0, 0 },
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 978   { "mqop27", 1398, {0, {0}}, 0, 0 },
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 996   { "mqst13", 1371, {0, {0}}, 0, 0 },
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 998   { "mqst15", 1375, {0, {0}}, 0, 0 },
 999   { "mqst16", 1377, {0, {0}}, 0, 0 },
1000   { "mqst17", 1379, {0, {0}}, 0, 0 },
1001   { "mqst18", 1381, {0, {0}}, 0, 0 },
1002   { "mqst19", 1383, {0, {0}}, 0, 0 },
1003   { "mqst20", 1385, {0, {0}}, 0, 0 },
1004   { "mqst21", 1387, {0, {0}}, 0, 0 },
1005   { "mqst22", 1389, {0, {0}}, 0, 0 },
1006   { "mqst23", 1391, {0, {0}}, 0, 0 },
1007   { "mqst24", 1393, {0, {0}}, 0, 0 },
1008   { "mqst25", 1395, {0, {0}}, 0, 0 },
1009   { "mqst26", 1397, {0, {0}}, 0, 0 },
1010   { "mqst27", 1399, {0, {0}}, 0, 0 },
1011   { "mqst28", 1401, {0, {0}}, 0, 0 },
1012   { "mqst29", 1403, {0, {0}}, 0, 0 },
1013   { "mqst30", 1405, {0, {0}}, 0, 0 },
1014   { "mqst31", 1407, {0, {0}}, 0, 0 },
1015   { "ear0", 1536, {0, {0}}, 0, 0 },
1016   { "ear1", 1537, {0, {0}}, 0, 0 },
1017   { "ear2", 1538, {0, {0}}, 0, 0 },
1018   { "ear3", 1539, {0, {0}}, 0, 0 },
1019   { "ear4", 1540, {0, {0}}, 0, 0 },
1020   { "ear5", 1541, {0, {0}}, 0, 0 },
1021   { "ear6", 1542, {0, {0}}, 0, 0 },
1022   { "ear7", 1543, {0, {0}}, 0, 0 },
1023   { "ear8", 1544, {0, {0}}, 0, 0 },
1024   { "ear9", 1545, {0, {0}}, 0, 0 },
1025   { "ear10", 1546, {0, {0}}, 0, 0 },
1026   { "ear11", 1547, {0, {0}}, 0, 0 },
1027   { "ear12", 1548, {0, {0}}, 0, 0 },
1028   { "ear13", 1549, {0, {0}}, 0, 0 },
1029   { "ear14", 1550, {0, {0}}, 0, 0 },
1030   { "ear15", 1551, {0, {0}}, 0, 0 },
1031   { "ear16", 1552, {0, {0}}, 0, 0 },
1032   { "ear17", 1553, {0, {0}}, 0, 0 },
1033   { "ear18", 1554, {0, {0}}, 0, 0 },
1034   { "ear19", 1555, {0, {0}}, 0, 0 },
1035   { "ear20", 1556, {0, {0}}, 0, 0 },
1036   { "ear21", 1557, {0, {0}}, 0, 0 },
1037   { "ear22", 1558, {0, {0}}, 0, 0 },
1038   { "ear23", 1559, {0, {0}}, 0, 0 },
1039   { "ear24", 1560, {0, {0}}, 0, 0 },
1040   { "ear25", 1561, {0, {0}}, 0, 0 },
1041   { "ear26", 1562, {0, {0}}, 0, 0 },
1042   { "ear27", 1563, {0, {0}}, 0, 0 },
1043   { "ear28", 1564, {0, {0}}, 0, 0 },
1044   { "ear29", 1565, {0, {0}}, 0, 0 },
1045   { "ear30", 1566, {0, {0}}, 0, 0 },
1046   { "ear31", 1567, {0, {0}}, 0, 0 },
1047   { "ear32", 1568, {0, {0}}, 0, 0 },
1048   { "ear33", 1569, {0, {0}}, 0, 0 },
1049   { "ear34", 1570, {0, {0}}, 0, 0 },
1050   { "ear35", 1571, {0, {0}}, 0, 0 },
1051   { "ear36", 1572, {0, {0}}, 0, 0 },
1052   { "ear37", 1573, {0, {0}}, 0, 0 },
1053   { "ear38", 1574, {0, {0}}, 0, 0 },
1054   { "ear39", 1575, {0, {0}}, 0, 0 },
1055   { "ear40", 1576, {0, {0}}, 0, 0 },
1056   { "ear41", 1577, {0, {0}}, 0, 0 },
1057   { "ear42", 1578, {0, {0}}, 0, 0 },
1058   { "ear43", 1579, {0, {0}}, 0, 0 },
1059   { "ear44", 1580, {0, {0}}, 0, 0 },
1060   { "ear45", 1581, {0, {0}}, 0, 0 },
1061   { "ear46", 1582, {0, {0}}, 0, 0 },
1062   { "ear47", 1583, {0, {0}}, 0, 0 },
1063   { "ear48", 1584, {0, {0}}, 0, 0 },
1064   { "ear49", 1585, {0, {0}}, 0, 0 },
1065   { "ear50", 1586, {0, {0}}, 0, 0 },
1066   { "ear51", 1587, {0, {0}}, 0, 0 },
1067   { "ear52", 1588, {0, {0}}, 0, 0 },
1068   { "ear53", 1589, {0, {0}}, 0, 0 },
1069   { "ear54", 1590, {0, {0}}, 0, 0 },
1070   { "ear55", 1591, {0, {0}}, 0, 0 },
1071   { "ear56", 1592, {0, {0}}, 0, 0 },
1072   { "ear57", 1593, {0, {0}}, 0, 0 },
1073   { "ear58", 1594, {0, {0}}, 0, 0 },
1074   { "ear59", 1595, {0, {0}}, 0, 0 },
1075   { "ear60", 1596, {0, {0}}, 0, 0 },
1076   { "ear61", 1597, {0, {0}}, 0, 0 },
1077   { "ear62", 1598, {0, {0}}, 0, 0 },
1078   { "ear63", 1599, {0, {0}}, 0, 0 },
1079   { "edr0", 1600, {0, {0}}, 0, 0 },
1080   { "edr1", 1601, {0, {0}}, 0, 0 },
1081   { "edr2", 1602, {0, {0}}, 0, 0 },
1082   { "edr3", 1603, {0, {0}}, 0, 0 },
1083   { "edr4", 1604, {0, {0}}, 0, 0 },
1084   { "edr5", 1605, {0, {0}}, 0, 0 },
1085   { "edr6", 1606, {0, {0}}, 0, 0 },
1086   { "edr7", 1607, {0, {0}}, 0, 0 },
1087   { "edr8", 1608, {0, {0}}, 0, 0 },
1088   { "edr9", 1609, {0, {0}}, 0, 0 },
1089   { "edr10", 1610, {0, {0}}, 0, 0 },
1090   { "edr11", 1611, {0, {0}}, 0, 0 },
1091   { "edr12", 1612, {0, {0}}, 0, 0 },
1092   { "edr13", 1613, {0, {0}}, 0, 0 },
1093   { "edr14", 1614, {0, {0}}, 0, 0 },
1094   { "edr15", 1615, {0, {0}}, 0, 0 },
1095   { "edr16", 1616, {0, {0}}, 0, 0 },
1096   { "edr17", 1617, {0, {0}}, 0, 0 },
1097   { "edr18", 1618, {0, {0}}, 0, 0 },
1098   { "edr19", 1619, {0, {0}}, 0, 0 },
1099   { "edr20", 1620, {0, {0}}, 0, 0 },
1100   { "edr21", 1621, {0, {0}}, 0, 0 },
1101   { "edr22", 1622, {0, {0}}, 0, 0 },
1102   { "edr23", 1623, {0, {0}}, 0, 0 },
1103   { "edr24", 1624, {0, {0}}, 0, 0 },
1104   { "edr25", 1625, {0, {0}}, 0, 0 },
1105   { "edr26", 1626, {0, {0}}, 0, 0 },
1106   { "edr27", 1627, {0, {0}}, 0, 0 },
1107   { "edr28", 1628, {0, {0}}, 0, 0 },
1108   { "edr29", 1629, {0, {0}}, 0, 0 },
1109   { "edr30", 1630, {0, {0}}, 0, 0 },
1110   { "edr31", 1631, {0, {0}}, 0, 0 },
1111   { "edr32", 1632, {0, {0}}, 0, 0 },
1112   { "edr33", 1636, {0, {0}}, 0, 0 },
1113   { "edr34", 1634, {0, {0}}, 0, 0 },
1114   { "edr35", 1635, {0, {0}}, 0, 0 },
1115   { "edr36", 1636, {0, {0}}, 0, 0 },
1116   { "edr37", 1637, {0, {0}}, 0, 0 },
1117   { "edr38", 1638, {0, {0}}, 0, 0 },
1118   { "edr39", 1639, {0, {0}}, 0, 0 },
1119   { "edr40", 1640, {0, {0}}, 0, 0 },
1120   { "edr41", 1641, {0, {0}}, 0, 0 },
1121   { "edr42", 1642, {0, {0}}, 0, 0 },
1122   { "edr43", 1643, {0, {0}}, 0, 0 },
1123   { "edr44", 1644, {0, {0}}, 0, 0 },
1124   { "edr45", 1645, {0, {0}}, 0, 0 },
1125   { "edr46", 1646, {0, {0}}, 0, 0 },
1126   { "edr47", 1647, {0, {0}}, 0, 0 },
1127   { "edr48", 1648, {0, {0}}, 0, 0 },
1128   { "edr49", 1649, {0, {0}}, 0, 0 },
1129   { "edr50", 1650, {0, {0}}, 0, 0 },
1130   { "edr51", 1651, {0, {0}}, 0, 0 },
1131   { "edr52", 1652, {0, {0}}, 0, 0 },
1132   { "edr53", 1653, {0, {0}}, 0, 0 },
1133   { "edr54", 1654, {0, {0}}, 0, 0 },
1134   { "edr55", 1655, {0, {0}}, 0, 0 },
1135   { "edr56", 1656, {0, {0}}, 0, 0 },
1136   { "edr57", 1657, {0, {0}}, 0, 0 },
1137   { "edr58", 1658, {0, {0}}, 0, 0 },
1138   { "edr59", 1659, {0, {0}}, 0, 0 },
1139   { "edr60", 1660, {0, {0}}, 0, 0 },
1140   { "edr61", 1661, {0, {0}}, 0, 0 },
1141   { "edr62", 1662, {0, {0}}, 0, 0 },
1142   { "edr63", 1663, {0, {0}}, 0, 0 },
1143   { "iamlr0", 1664, {0, {0}}, 0, 0 },
1144   { "iamlr1", 1665, {0, {0}}, 0, 0 },
1145   { "iamlr2", 1666, {0, {0}}, 0, 0 },
1146   { "iamlr3", 1667, {0, {0}}, 0, 0 },
1147   { "iamlr4", 1668, {0, {0}}, 0, 0 },
1148   { "iamlr5", 1669, {0, {0}}, 0, 0 },
1149   { "iamlr6", 1670, {0, {0}}, 0, 0 },
1150   { "iamlr7", 1671, {0, {0}}, 0, 0 },
1151   { "iamlr8", 1672, {0, {0}}, 0, 0 },
1152   { "iamlr9", 1673, {0, {0}}, 0, 0 },
1153   { "iamlr10", 1674, {0, {0}}, 0, 0 },
1154   { "iamlr11", 1675, {0, {0}}, 0, 0 },
1155   { "iamlr12", 1676, {0, {0}}, 0, 0 },
1156   { "iamlr13", 1677, {0, {0}}, 0, 0 },
1157   { "iamlr14", 1678, {0, {0}}, 0, 0 },
1158   { "iamlr15", 1679, {0, {0}}, 0, 0 },
1159   { "iamlr16", 1680, {0, {0}}, 0, 0 },
1160   { "iamlr17", 1681, {0, {0}}, 0, 0 },
1161   { "iamlr18", 1682, {0, {0}}, 0, 0 },
1162   { "iamlr19", 1683, {0, {0}}, 0, 0 },
1163   { "iamlr20", 1684, {0, {0}}, 0, 0 },
1164   { "iamlr21", 1685, {0, {0}}, 0, 0 },
1165   { "iamlr22", 1686, {0, {0}}, 0, 0 },
1166   { "iamlr23", 1687, {0, {0}}, 0, 0 },
1167   { "iamlr24", 1688, {0, {0}}, 0, 0 },
1168   { "iamlr25", 1689, {0, {0}}, 0, 0 },
1169   { "iamlr26", 1690, {0, {0}}, 0, 0 },
1170   { "iamlr27", 1691, {0, {0}}, 0, 0 },
1171   { "iamlr28", 1692, {0, {0}}, 0, 0 },
1172   { "iamlr29", 1693, {0, {0}}, 0, 0 },
1173   { "iamlr30", 1694, {0, {0}}, 0, 0 },
1174   { "iamlr31", 1695, {0, {0}}, 0, 0 },
1175   { "iamlr32", 1696, {0, {0}}, 0, 0 },
1176   { "iamlr33", 1697, {0, {0}}, 0, 0 },
1177   { "iamlr34", 1698, {0, {0}}, 0, 0 },
1178   { "iamlr35", 1699, {0, {0}}, 0, 0 },
1179   { "iamlr36", 1700, {0, {0}}, 0, 0 },
1180   { "iamlr37", 1701, {0, {0}}, 0, 0 },
1181   { "iamlr38", 1702, {0, {0}}, 0, 0 },
1182   { "iamlr39", 1703, {0, {0}}, 0, 0 },
1183   { "iamlr40", 1704, {0, {0}}, 0, 0 },
1184   { "iamlr41", 1705, {0, {0}}, 0, 0 },
1185   { "iamlr42", 1706, {0, {0}}, 0, 0 },
1186   { "iamlr43", 1707, {0, {0}}, 0, 0 },
1187   { "iamlr44", 1708, {0, {0}}, 0, 0 },
1188   { "iamlr45", 1709, {0, {0}}, 0, 0 },
1189   { "iamlr46", 1710, {0, {0}}, 0, 0 },
1190   { "iamlr47", 1711, {0, {0}}, 0, 0 },
1191   { "iamlr48", 1712, {0, {0}}, 0, 0 },
1192   { "iamlr49", 1713, {0, {0}}, 0, 0 },
1193   { "iamlr50", 1714, {0, {0}}, 0, 0 },
1194   { "iamlr51", 1715, {0, {0}}, 0, 0 },
1195   { "iamlr52", 1716, {0, {0}}, 0, 0 },
1196   { "iamlr53", 1717, {0, {0}}, 0, 0 },
1197   { "iamlr54", 1718, {0, {0}}, 0, 0 },
1198   { "iamlr55", 1719, {0, {0}}, 0, 0 },
1199   { "iamlr56", 1720, {0, {0}}, 0, 0 },
1200   { "iamlr57", 1721, {0, {0}}, 0, 0 },
1201   { "iamlr58", 1722, {0, {0}}, 0, 0 },
1202   { "iamlr59", 1723, {0, {0}}, 0, 0 },
1203   { "iamlr60", 1724, {0, {0}}, 0, 0 },
1204   { "iamlr61", 1725, {0, {0}}, 0, 0 },
1205   { "iamlr62", 1726, {0, {0}}, 0, 0 },
1206   { "iamlr63", 1727, {0, {0}}, 0, 0 },
1207   { "iampr0", 1728, {0, {0}}, 0, 0 },
1208   { "iampr1", 1729, {0, {0}}, 0, 0 },
1209   { "iampr2", 1730, {0, {0}}, 0, 0 },
1210   { "iampr3", 1731, {0, {0}}, 0, 0 },
1211   { "iampr4", 1732, {0, {0}}, 0, 0 },
1212   { "iampr5", 1733, {0, {0}}, 0, 0 },
1213   { "iampr6", 1734, {0, {0}}, 0, 0 },
1214   { "iampr7", 1735, {0, {0}}, 0, 0 },
1215   { "iampr8", 1736, {0, {0}}, 0, 0 },
1216   { "iampr9", 1737, {0, {0}}, 0, 0 },
1217   { "iampr10", 1738, {0, {0}}, 0, 0 },
1218   { "iampr11", 1739, {0, {0}}, 0, 0 },
1219   { "iampr12", 1740, {0, {0}}, 0, 0 },
1220   { "iampr13", 1741, {0, {0}}, 0, 0 },
1221   { "iampr14", 1742, {0, {0}}, 0, 0 },
1222   { "iampr15", 1743, {0, {0}}, 0, 0 },
1223   { "iampr16", 1744, {0, {0}}, 0, 0 },
1224   { "iampr17", 1745, {0, {0}}, 0, 0 },
1225   { "iampr18", 1746, {0, {0}}, 0, 0 },
1226   { "iampr19", 1747, {0, {0}}, 0, 0 },
1227   { "iampr20", 1748, {0, {0}}, 0, 0 },
1228   { "iampr21", 1749, {0, {0}}, 0, 0 },
1229   { "iampr22", 1750, {0, {0}}, 0, 0 },
1230   { "iampr23", 1751, {0, {0}}, 0, 0 },
1231   { "iampr24", 1752, {0, {0}}, 0, 0 },
1232   { "iampr25", 1753, {0, {0}}, 0, 0 },
1233   { "iampr26", 1754, {0, {0}}, 0, 0 },
1234   { "iampr27", 1755, {0, {0}}, 0, 0 },
1235   { "iampr28", 1756, {0, {0}}, 0, 0 },
1236   { "iampr29", 1757, {0, {0}}, 0, 0 },
1237   { "iampr30", 1758, {0, {0}}, 0, 0 },
1238   { "iampr31", 1759, {0, {0}}, 0, 0 },
1239   { "iampr32", 1760, {0, {0}}, 0, 0 },
1240   { "iampr33", 1761, {0, {0}}, 0, 0 },
1241   { "iampr34", 1762, {0, {0}}, 0, 0 },
1242   { "iampr35", 1763, {0, {0}}, 0, 0 },
1243   { "iampr36", 1764, {0, {0}}, 0, 0 },
1244   { "iampr37", 1765, {0, {0}}, 0, 0 },
1245   { "iampr38", 1766, {0, {0}}, 0, 0 },
1246   { "iampr39", 1767, {0, {0}}, 0, 0 },
1247   { "iampr40", 1768, {0, {0}}, 0, 0 },
1248   { "iampr41", 1769, {0, {0}}, 0, 0 },
1249   { "iampr42", 1770, {0, {0}}, 0, 0 },
1250   { "iampr43", 1771, {0, {0}}, 0, 0 },
1251   { "iampr44", 1772, {0, {0}}, 0, 0 },
1252   { "iampr45", 1773, {0, {0}}, 0, 0 },
1253   { "iampr46", 1774, {0, {0}}, 0, 0 },
1254   { "iampr47", 1775, {0, {0}}, 0, 0 },
1255   { "iampr48", 1776, {0, {0}}, 0, 0 },
1256   { "iampr49", 1777, {0, {0}}, 0, 0 },
1257   { "iampr50", 1778, {0, {0}}, 0, 0 },
1258   { "iampr51", 1779, {0, {0}}, 0, 0 },
1259   { "iampr52", 1780, {0, {0}}, 0, 0 },
1260   { "iampr53", 1781, {0, {0}}, 0, 0 },
1261   { "iampr54", 1782, {0, {0}}, 0, 0 },
1262   { "iampr55", 1783, {0, {0}}, 0, 0 },
1263   { "iampr56", 1784, {0, {0}}, 0, 0 },
1264   { "iampr57", 1785, {0, {0}}, 0, 0 },
1265   { "iampr58", 1786, {0, {0}}, 0, 0 },
1266   { "iampr59", 1787, {0, {0}}, 0, 0 },
1267   { "iampr60", 1788, {0, {0}}, 0, 0 },
1268   { "iampr61", 1789, {0, {0}}, 0, 0 },
1269   { "iampr62", 1790, {0, {0}}, 0, 0 },
1270   { "iampr63", 1791, {0, {0}}, 0, 0 },
1271   { "damlr0", 1792, {0, {0}}, 0, 0 },
1272   { "damlr1", 1793, {0, {0}}, 0, 0 },
1273   { "damlr2", 1794, {0, {0}}, 0, 0 },
1274   { "damlr3", 1795, {0, {0}}, 0, 0 },
1275   { "damlr4", 1796, {0, {0}}, 0, 0 },
1276   { "damlr5", 1797, {0, {0}}, 0, 0 },
1277   { "damlr6", 1798, {0, {0}}, 0, 0 },
1278   { "damlr7", 1799, {0, {0}}, 0, 0 },
1279   { "damlr8", 1800, {0, {0}}, 0, 0 },
1280   { "damlr9", 1801, {0, {0}}, 0, 0 },
1281   { "damlr10", 1802, {0, {0}}, 0, 0 },
1282   { "damlr11", 1803, {0, {0}}, 0, 0 },
1283   { "damlr12", 1804, {0, {0}}, 0, 0 },
1284   { "damlr13", 1805, {0, {0}}, 0, 0 },
1285   { "damlr14", 1806, {0, {0}}, 0, 0 },
1286   { "damlr15", 1807, {0, {0}}, 0, 0 },
1287   { "damlr16", 1808, {0, {0}}, 0, 0 },
1288   { "damlr17", 1809, {0, {0}}, 0, 0 },
1289   { "damlr18", 1810, {0, {0}}, 0, 0 },
1290   { "damlr19", 1811, {0, {0}}, 0, 0 },
1291   { "damlr20", 1812, {0, {0}}, 0, 0 },
1292   { "damlr21", 1813, {0, {0}}, 0, 0 },
1293   { "damlr22", 1814, {0, {0}}, 0, 0 },
1294   { "damlr23", 1815, {0, {0}}, 0, 0 },
1295   { "damlr24", 1816, {0, {0}}, 0, 0 },
1296   { "damlr25", 1817, {0, {0}}, 0, 0 },
1297   { "damlr26", 1818, {0, {0}}, 0, 0 },
1298   { "damlr27", 1819, {0, {0}}, 0, 0 },
1299   { "damlr28", 1820, {0, {0}}, 0, 0 },
1300   { "damlr29", 1821, {0, {0}}, 0, 0 },
1301   { "damlr30", 1822, {0, {0}}, 0, 0 },
1302   { "damlr31", 1823, {0, {0}}, 0, 0 },
1303   { "damlr32", 1824, {0, {0}}, 0, 0 },
1304   { "damlr33", 1825, {0, {0}}, 0, 0 },
1305   { "damlr34", 1826, {0, {0}}, 0, 0 },
1306   { "damlr35", 1827, {0, {0}}, 0, 0 },
1307   { "damlr36", 1828, {0, {0}}, 0, 0 },
1308   { "damlr37", 1829, {0, {0}}, 0, 0 },
1309   { "damlr38", 1830, {0, {0}}, 0, 0 },
1310   { "damlr39", 1831, {0, {0}}, 0, 0 },
1311   { "damlr40", 1832, {0, {0}}, 0, 0 },
1312   { "damlr41", 1833, {0, {0}}, 0, 0 },
1313   { "damlr42", 1834, {0, {0}}, 0, 0 },
1314   { "damlr43", 1835, {0, {0}}, 0, 0 },
1315   { "damlr44", 1836, {0, {0}}, 0, 0 },
1316   { "damlr45", 1837, {0, {0}}, 0, 0 },
1317   { "damlr46", 1838, {0, {0}}, 0, 0 },
1318   { "damlr47", 1839, {0, {0}}, 0, 0 },
1319   { "damlr48", 1840, {0, {0}}, 0, 0 },
1320   { "damlr49", 1841, {0, {0}}, 0, 0 },
1321   { "damlr50", 1842, {0, {0}}, 0, 0 },
1322   { "damlr51", 1843, {0, {0}}, 0, 0 },
1323   { "damlr52", 1844, {0, {0}}, 0, 0 },
1324   { "damlr53", 1845, {0, {0}}, 0, 0 },
1325   { "damlr54", 1846, {0, {0}}, 0, 0 },
1326   { "damlr55", 1847, {0, {0}}, 0, 0 },
1327   { "damlr56", 1848, {0, {0}}, 0, 0 },
1328   { "damlr57", 1849, {0, {0}}, 0, 0 },
1329   { "damlr58", 1850, {0, {0}}, 0, 0 },
1330   { "damlr59", 1851, {0, {0}}, 0, 0 },
1331   { "damlr60", 1852, {0, {0}}, 0, 0 },
1332   { "damlr61", 1853, {0, {0}}, 0, 0 },
1333   { "damlr62", 1854, {0, {0}}, 0, 0 },
1334   { "damlr63", 1855, {0, {0}}, 0, 0 },
1335   { "dampr0", 1856, {0, {0}}, 0, 0 },
1336   { "dampr1", 1857, {0, {0}}, 0, 0 },
1337   { "dampr2", 1858, {0, {0}}, 0, 0 },
1338   { "dampr3", 1859, {0, {0}}, 0, 0 },
1339   { "dampr4", 1860, {0, {0}}, 0, 0 },
1340   { "dampr5", 1861, {0, {0}}, 0, 0 },
1341   { "dampr6", 1862, {0, {0}}, 0, 0 },
1342   { "dampr7", 1863, {0, {0}}, 0, 0 },
1343   { "dampr8", 1864, {0, {0}}, 0, 0 },
1344   { "dampr9", 1865, {0, {0}}, 0, 0 },
1345   { "dampr10", 1866, {0, {0}}, 0, 0 },
1346   { "dampr11", 1867, {0, {0}}, 0, 0 },
1347   { "dampr12", 1868, {0, {0}}, 0, 0 },
1348   { "dampr13", 1869, {0, {0}}, 0, 0 },
1349   { "dampr14", 1870, {0, {0}}, 0, 0 },
1350   { "dampr15", 1871, {0, {0}}, 0, 0 },
1351   { "dampr16", 1872, {0, {0}}, 0, 0 },
1352   { "dampr17", 1873, {0, {0}}, 0, 0 },
1353   { "dampr18", 1874, {0, {0}}, 0, 0 },
1354   { "dampr19", 1875, {0, {0}}, 0, 0 },
1355   { "dampr20", 1876, {0, {0}}, 0, 0 },
1356   { "dampr21", 1877, {0, {0}}, 0, 0 },
1357   { "dampr22", 1878, {0, {0}}, 0, 0 },
1358   { "dampr23", 1879, {0, {0}}, 0, 0 },
1359   { "dampr24", 1880, {0, {0}}, 0, 0 },
1360   { "dampr25", 1881, {0, {0}}, 0, 0 },
1361   { "dampr26", 1882, {0, {0}}, 0, 0 },
1362   { "dampr27", 1883, {0, {0}}, 0, 0 },
1363   { "dampr28", 1884, {0, {0}}, 0, 0 },
1364   { "dampr29", 1885, {0, {0}}, 0, 0 },
1365   { "dampr30", 1886, {0, {0}}, 0, 0 },
1366   { "dampr31", 1887, {0, {0}}, 0, 0 },
1367   { "dampr32", 1888, {0, {0}}, 0, 0 },
1368   { "dampr33", 1889, {0, {0}}, 0, 0 },
1369   { "dampr34", 1890, {0, {0}}, 0, 0 },
1370   { "dampr35", 1891, {0, {0}}, 0, 0 },
1371   { "dampr36", 1892, {0, {0}}, 0, 0 },
1372   { "dampr37", 1893, {0, {0}}, 0, 0 },
1373   { "dampr38", 1894, {0, {0}}, 0, 0 },
1374   { "dampr39", 1895, {0, {0}}, 0, 0 },
1375   { "dampr40", 1896, {0, {0}}, 0, 0 },
1376   { "dampr41", 1897, {0, {0}}, 0, 0 },
1377   { "dampr42", 1898, {0, {0}}, 0, 0 },
1378   { "dampr43", 1899, {0, {0}}, 0, 0 },
1379   { "dampr44", 1900, {0, {0}}, 0, 0 },
1380   { "dampr45", 1901, {0, {0}}, 0, 0 },
1381   { "dampr46", 1902, {0, {0}}, 0, 0 },
1382   { "dampr47", 1903, {0, {0}}, 0, 0 },
1383   { "dampr48", 1904, {0, {0}}, 0, 0 },
1384   { "dampr49", 1905, {0, {0}}, 0, 0 },
1385   { "dampr50", 1906, {0, {0}}, 0, 0 },
1386   { "dampr51", 1907, {0, {0}}, 0, 0 },
1387   { "dampr52", 1908, {0, {0}}, 0, 0 },
1388   { "dampr53", 1909, {0, {0}}, 0, 0 },
1389   { "dampr54", 1910, {0, {0}}, 0, 0 },
1390   { "dampr55", 1911, {0, {0}}, 0, 0 },
1391   { "dampr56", 1912, {0, {0}}, 0, 0 },
1392   { "dampr57", 1913, {0, {0}}, 0, 0 },
1393   { "dampr58", 1914, {0, {0}}, 0, 0 },
1394   { "dampr59", 1915, {0, {0}}, 0, 0 },
1395   { "dampr60", 1916, {0, {0}}, 0, 0 },
1396   { "dampr61", 1917, {0, {0}}, 0, 0 },
1397   { "dampr62", 1918, {0, {0}}, 0, 0 },
1398   { "dampr63", 1919, {0, {0}}, 0, 0 },
1399   { "amcr", 1920, {0, {0}}, 0, 0 },
1400   { "stbar", 1921, {0, {0}}, 0, 0 },
1401   { "mmcr", 1922, {0, {0}}, 0, 0 },
1402   { "dcr", 2048, {0, {0}}, 0, 0 },
1403   { "brr", 2049, {0, {0}}, 0, 0 },
1404   { "nmar", 2050, {0, {0}}, 0, 0 },
1405   { "ibar0", 2052, {0, {0}}, 0, 0 },
1406   { "ibar1", 2053, {0, {0}}, 0, 0 },
1407   { "ibar2", 2054, {0, {0}}, 0, 0 },
1408   { "ibar3", 2055, {0, {0}}, 0, 0 },
1409   { "dbar0", 2056, {0, {0}}, 0, 0 },
1410   { "dbar1", 2057, {0, {0}}, 0, 0 },
1411   { "dbar2", 2058, {0, {0}}, 0, 0 },
1412   { "dbar3", 2059, {0, {0}}, 0, 0 },
1413   { "dbdr00", 2060, {0, {0}}, 0, 0 },
1414   { "dbdr01", 2061, {0, {0}}, 0, 0 },
1415   { "dbdr02", 2062, {0, {0}}, 0, 0 },
1416   { "dbdr03", 2063, {0, {0}}, 0, 0 },
1417   { "dbdr10", 2064, {0, {0}}, 0, 0 },
1418   { "dbdr11", 2065, {0, {0}}, 0, 0 },
1419   { "dbdr12", 2066, {0, {0}}, 0, 0 },
1420   { "dbdr13", 2067, {0, {0}}, 0, 0 },
1421   { "dbdr20", 2068, {0, {0}}, 0, 0 },
1422   { "dbdr21", 2069, {0, {0}}, 0, 0 },
1423   { "dbdr22", 2070, {0, {0}}, 0, 0 },
1424   { "dbdr23", 2071, {0, {0}}, 0, 0 },
1425   { "dbdr30", 2072, {0, {0}}, 0, 0 },
1426   { "dbdr31", 2073, {0, {0}}, 0, 0 },
1427   { "dbdr32", 2074, {0, {0}}, 0, 0 },
1428   { "dbdr33", 2075, {0, {0}}, 0, 0 },
1429   { "dbmr00", 2076, {0, {0}}, 0, 0 },
1430   { "dbmr01", 2077, {0, {0}}, 0, 0 },
1431   { "dbmr02", 2078, {0, {0}}, 0, 0 },
1432   { "dbmr03", 2079, {0, {0}}, 0, 0 },
1433   { "dbmr10", 2080, {0, {0}}, 0, 0 },
1434   { "dbmr11", 2081, {0, {0}}, 0, 0 },
1435   { "dbmr12", 2082, {0, {0}}, 0, 0 },
1436   { "dbmr13", 2083, {0, {0}}, 0, 0 },
1437   { "dbmr20", 2084, {0, {0}}, 0, 0 },
1438   { "dbmr21", 2085, {0, {0}}, 0, 0 },
1439   { "dbmr22", 2086, {0, {0}}, 0, 0 },
1440   { "dbmr23", 2087, {0, {0}}, 0, 0 },
1441   { "dbmr30", 2088, {0, {0}}, 0, 0 },
1442   { "dbmr31", 2089, {0, {0}}, 0, 0 },
1443   { "dbmr32", 2090, {0, {0}}, 0, 0 },
1444   { "dbmr33", 2091, {0, {0}}, 0, 0 },
1445   { "cpcfr", 2092, {0, {0}}, 0, 0 },
1446   { "cpcr", 2093, {0, {0}}, 0, 0 },
1447   { "cpsr", 2094, {0, {0}}, 0, 0 },
1448   { "cpesr0", 2096, {0, {0}}, 0, 0 },
1449   { "cpesr1", 2097, {0, {0}}, 0, 0 },
1450   { "cpemr0", 2098, {0, {0}}, 0, 0 },
1451   { "cpemr1", 2099, {0, {0}}, 0, 0 },
1452   { "ihsr8", 3848, {0, {0}}, 0, 0 }
1453 };
1454
1455 CGEN_KEYWORD frv_cgen_opval_spr_names =
1456 {
1457   & frv_cgen_opval_spr_names_entries[0],
1458   1005,
1459   0, 0, 0, 0, ""
1460 };
1461
1462 static CGEN_KEYWORD_ENTRY frv_cgen_opval_accg_names_entries[] =
1463 {
1464   { "accg0", 0, {0, {0}}, 0, 0 },
1465   { "accg1", 1, {0, {0}}, 0, 0 },
1466   { "accg2", 2, {0, {0}}, 0, 0 },
1467   { "accg3", 3, {0, {0}}, 0, 0 },
1468   { "accg4", 4, {0, {0}}, 0, 0 },
1469   { "accg5", 5, {0, {0}}, 0, 0 },
1470   { "accg6", 6, {0, {0}}, 0, 0 },
1471   { "accg7", 7, {0, {0}}, 0, 0 },
1472   { "accg8", 8, {0, {0}}, 0, 0 },
1473   { "accg9", 9, {0, {0}}, 0, 0 },
1474   { "accg10", 10, {0, {0}}, 0, 0 },
1475   { "accg11", 11, {0, {0}}, 0, 0 },
1476   { "accg12", 12, {0, {0}}, 0, 0 },
1477   { "accg13", 13, {0, {0}}, 0, 0 },
1478   { "accg14", 14, {0, {0}}, 0, 0 },
1479   { "accg15", 15, {0, {0}}, 0, 0 },
1480   { "accg16", 16, {0, {0}}, 0, 0 },
1481   { "accg17", 17, {0, {0}}, 0, 0 },
1482   { "accg18", 18, {0, {0}}, 0, 0 },
1483   { "accg19", 19, {0, {0}}, 0, 0 },
1484   { "accg20", 20, {0, {0}}, 0, 0 },
1485   { "accg21", 21, {0, {0}}, 0, 0 },
1486   { "accg22", 22, {0, {0}}, 0, 0 },
1487   { "accg23", 23, {0, {0}}, 0, 0 },
1488   { "accg24", 24, {0, {0}}, 0, 0 },
1489   { "accg25", 25, {0, {0}}, 0, 0 },
1490   { "accg26", 26, {0, {0}}, 0, 0 },
1491   { "accg27", 27, {0, {0}}, 0, 0 },
1492   { "accg28", 28, {0, {0}}, 0, 0 },
1493   { "accg29", 29, {0, {0}}, 0, 0 },
1494   { "accg30", 30, {0, {0}}, 0, 0 },
1495   { "accg31", 31, {0, {0}}, 0, 0 },
1496   { "accg32", 32, {0, {0}}, 0, 0 },
1497   { "accg33", 33, {0, {0}}, 0, 0 },
1498   { "accg34", 34, {0, {0}}, 0, 0 },
1499   { "accg35", 35, {0, {0}}, 0, 0 },
1500   { "accg36", 36, {0, {0}}, 0, 0 },
1501   { "accg37", 37, {0, {0}}, 0, 0 },
1502   { "accg38", 38, {0, {0}}, 0, 0 },
1503   { "accg39", 39, {0, {0}}, 0, 0 },
1504   { "accg40", 40, {0, {0}}, 0, 0 },
1505   { "accg41", 41, {0, {0}}, 0, 0 },
1506   { "accg42", 42, {0, {0}}, 0, 0 },
1507   { "accg43", 43, {0, {0}}, 0, 0 },
1508   { "accg44", 44, {0, {0}}, 0, 0 },
1509   { "accg45", 45, {0, {0}}, 0, 0 },
1510   { "accg46", 46, {0, {0}}, 0, 0 },
1511   { "accg47", 47, {0, {0}}, 0, 0 },
1512   { "accg48", 48, {0, {0}}, 0, 0 },
1513   { "accg49", 49, {0, {0}}, 0, 0 },
1514   { "accg50", 50, {0, {0}}, 0, 0 },
1515   { "accg51", 51, {0, {0}}, 0, 0 },
1516   { "accg52", 52, {0, {0}}, 0, 0 },
1517   { "accg53", 53, {0, {0}}, 0, 0 },
1518   { "accg54", 54, {0, {0}}, 0, 0 },
1519   { "accg55", 55, {0, {0}}, 0, 0 },
1520   { "accg56", 56, {0, {0}}, 0, 0 },
1521   { "accg57", 57, {0, {0}}, 0, 0 },
1522   { "accg58", 58, {0, {0}}, 0, 0 },
1523   { "accg59", 59, {0, {0}}, 0, 0 },
1524   { "accg60", 60, {0, {0}}, 0, 0 },
1525   { "accg61", 61, {0, {0}}, 0, 0 },
1526   { "accg62", 62, {0, {0}}, 0, 0 },
1527   { "accg63", 63, {0, {0}}, 0, 0 }
1528 };
1529
1530 CGEN_KEYWORD frv_cgen_opval_accg_names =
1531 {
1532   & frv_cgen_opval_accg_names_entries[0],
1533   64,
1534   0, 0, 0, 0, ""
1535 };
1536
1537 static CGEN_KEYWORD_ENTRY frv_cgen_opval_acc_names_entries[] =
1538 {
1539   { "acc0", 0, {0, {0}}, 0, 0 },
1540   { "acc1", 1, {0, {0}}, 0, 0 },
1541   { "acc2", 2, {0, {0}}, 0, 0 },
1542   { "acc3", 3, {0, {0}}, 0, 0 },
1543   { "acc4", 4, {0, {0}}, 0, 0 },
1544   { "acc5", 5, {0, {0}}, 0, 0 },
1545   { "acc6", 6, {0, {0}}, 0, 0 },
1546   { "acc7", 7, {0, {0}}, 0, 0 },
1547   { "acc8", 8, {0, {0}}, 0, 0 },
1548   { "acc9", 9, {0, {0}}, 0, 0 },
1549   { "acc10", 10, {0, {0}}, 0, 0 },
1550   { "acc11", 11, {0, {0}}, 0, 0 },
1551   { "acc12", 12, {0, {0}}, 0, 0 },
1552   { "acc13", 13, {0, {0}}, 0, 0 },
1553   { "acc14", 14, {0, {0}}, 0, 0 },
1554   { "acc15", 15, {0, {0}}, 0, 0 },
1555   { "acc16", 16, {0, {0}}, 0, 0 },
1556   { "acc17", 17, {0, {0}}, 0, 0 },
1557   { "acc18", 18, {0, {0}}, 0, 0 },
1558   { "acc19", 19, {0, {0}}, 0, 0 },
1559   { "acc20", 20, {0, {0}}, 0, 0 },
1560   { "acc21", 21, {0, {0}}, 0, 0 },
1561   { "acc22", 22, {0, {0}}, 0, 0 },
1562   { "acc23", 23, {0, {0}}, 0, 0 },
1563   { "acc24", 24, {0, {0}}, 0, 0 },
1564   { "acc25", 25, {0, {0}}, 0, 0 },
1565   { "acc26", 26, {0, {0}}, 0, 0 },
1566   { "acc27", 27, {0, {0}}, 0, 0 },
1567   { "acc28", 28, {0, {0}}, 0, 0 },
1568   { "acc29", 29, {0, {0}}, 0, 0 },
1569   { "acc30", 30, {0, {0}}, 0, 0 },
1570   { "acc31", 31, {0, {0}}, 0, 0 },
1571   { "acc32", 32, {0, {0}}, 0, 0 },
1572   { "acc33", 33, {0, {0}}, 0, 0 },
1573   { "acc34", 34, {0, {0}}, 0, 0 },
1574   { "acc35", 35, {0, {0}}, 0, 0 },
1575   { "acc36", 36, {0, {0}}, 0, 0 },
1576   { "acc37", 37, {0, {0}}, 0, 0 },
1577   { "acc38", 38, {0, {0}}, 0, 0 },
1578   { "acc39", 39, {0, {0}}, 0, 0 },
1579   { "acc40", 40, {0, {0}}, 0, 0 },
1580   { "acc41", 41, {0, {0}}, 0, 0 },
1581   { "acc42", 42, {0, {0}}, 0, 0 },
1582   { "acc43", 43, {0, {0}}, 0, 0 },
1583   { "acc44", 44, {0, {0}}, 0, 0 },
1584   { "acc45", 45, {0, {0}}, 0, 0 },
1585   { "acc46", 46, {0, {0}}, 0, 0 },
1586   { "acc47", 47, {0, {0}}, 0, 0 },
1587   { "acc48", 48, {0, {0}}, 0, 0 },
1588   { "acc49", 49, {0, {0}}, 0, 0 },
1589   { "acc50", 50, {0, {0}}, 0, 0 },
1590   { "acc51", 51, {0, {0}}, 0, 0 },
1591   { "acc52", 52, {0, {0}}, 0, 0 },
1592   { "acc53", 53, {0, {0}}, 0, 0 },
1593   { "acc54", 54, {0, {0}}, 0, 0 },
1594   { "acc55", 55, {0, {0}}, 0, 0 },
1595   { "acc56", 56, {0, {0}}, 0, 0 },
1596   { "acc57", 57, {0, {0}}, 0, 0 },
1597   { "acc58", 58, {0, {0}}, 0, 0 },
1598   { "acc59", 59, {0, {0}}, 0, 0 },
1599   { "acc60", 60, {0, {0}}, 0, 0 },
1600   { "acc61", 61, {0, {0}}, 0, 0 },
1601   { "acc62", 62, {0, {0}}, 0, 0 },
1602   { "acc63", 63, {0, {0}}, 0, 0 }
1603 };
1604
1605 CGEN_KEYWORD frv_cgen_opval_acc_names =
1606 {
1607   & frv_cgen_opval_acc_names_entries[0],
1608   64,
1609   0, 0, 0, 0, ""
1610 };
1611
1612 static CGEN_KEYWORD_ENTRY frv_cgen_opval_iccr_names_entries[] =
1613 {
1614   { "icc0", 0, {0, {0}}, 0, 0 },
1615   { "icc1", 1, {0, {0}}, 0, 0 },
1616   { "icc2", 2, {0, {0}}, 0, 0 },
1617   { "icc3", 3, {0, {0}}, 0, 0 }
1618 };
1619
1620 CGEN_KEYWORD frv_cgen_opval_iccr_names =
1621 {
1622   & frv_cgen_opval_iccr_names_entries[0],
1623   4,
1624   0, 0, 0, 0, ""
1625 };
1626
1627 static CGEN_KEYWORD_ENTRY frv_cgen_opval_fccr_names_entries[] =
1628 {
1629   { "fcc0", 0, {0, {0}}, 0, 0 },
1630   { "fcc1", 1, {0, {0}}, 0, 0 },
1631   { "fcc2", 2, {0, {0}}, 0, 0 },
1632   { "fcc3", 3, {0, {0}}, 0, 0 }
1633 };
1634
1635 CGEN_KEYWORD frv_cgen_opval_fccr_names =
1636 {
1637   & frv_cgen_opval_fccr_names_entries[0],
1638   4,
1639   0, 0, 0, 0, ""
1640 };
1641
1642 static CGEN_KEYWORD_ENTRY frv_cgen_opval_cccr_names_entries[] =
1643 {
1644   { "cc0", 0, {0, {0}}, 0, 0 },
1645   { "cc1", 1, {0, {0}}, 0, 0 },
1646   { "cc2", 2, {0, {0}}, 0, 0 },
1647   { "cc3", 3, {0, {0}}, 0, 0 },
1648   { "cc4", 4, {0, {0}}, 0, 0 },
1649   { "cc5", 5, {0, {0}}, 0, 0 },
1650   { "cc6", 6, {0, {0}}, 0, 0 },
1651   { "cc7", 7, {0, {0}}, 0, 0 }
1652 };
1653
1654 CGEN_KEYWORD frv_cgen_opval_cccr_names =
1655 {
1656   & frv_cgen_opval_cccr_names_entries[0],
1657   8,
1658   0, 0, 0, 0, ""
1659 };
1660
1661 static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_pack_entries[] =
1662 {
1663   { "", 1, {0, {0}}, 0, 0 },
1664   { ".p", 0, {0, {0}}, 0, 0 },
1665   { ".P", 0, {0, {0}}, 0, 0 }
1666 };
1667
1668 CGEN_KEYWORD frv_cgen_opval_h_pack =
1669 {
1670   & frv_cgen_opval_h_pack_entries[0],
1671   3,
1672   0, 0, 0, 0, ""
1673 };
1674
1675 static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_hint_taken_entries[] =
1676 {
1677   { "", 2, {0, {0}}, 0, 0 },
1678   { "", 0, {0, {0}}, 0, 0 },
1679   { "", 1, {0, {0}}, 0, 0 },
1680   { "", 3, {0, {0}}, 0, 0 }
1681 };
1682
1683 CGEN_KEYWORD frv_cgen_opval_h_hint_taken =
1684 {
1685   & frv_cgen_opval_h_hint_taken_entries[0],
1686   4,
1687   0, 0, 0, 0, ""
1688 };
1689
1690 static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_hint_not_taken_entries[] =
1691 {
1692   { "", 0, {0, {0}}, 0, 0 },
1693   { "", 1, {0, {0}}, 0, 0 },
1694   { "", 2, {0, {0}}, 0, 0 },
1695   { "", 3, {0, {0}}, 0, 0 }
1696 };
1697
1698 CGEN_KEYWORD frv_cgen_opval_h_hint_not_taken =
1699 {
1700   & frv_cgen_opval_h_hint_not_taken_entries[0],
1701   4,
1702   0, 0, 0, 0, ""
1703 };
1704
1705
1706 /* The hardware table.  */
1707
1708 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1709 #define A(a) (1 << CGEN_HW_##a)
1710 #else
1711 #define A(a) (1 << CGEN_HW_/**/a)
1712 #endif
1713
1714 const CGEN_HW_ENTRY frv_cgen_hw_table[] =
1715 {
1716   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1717   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1718   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1719   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1720   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1721   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
1722   { "h-psr_imple", HW_H_PSR_IMPLE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1723   { "h-psr_ver", HW_H_PSR_VER, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1724   { "h-psr_ice", HW_H_PSR_ICE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1725   { "h-psr_nem", HW_H_PSR_NEM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1726   { "h-psr_cm", HW_H_PSR_CM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1727   { "h-psr_be", HW_H_PSR_BE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1728   { "h-psr_esr", HW_H_PSR_ESR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1729   { "h-psr_ef", HW_H_PSR_EF, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1730   { "h-psr_em", HW_H_PSR_EM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1731   { "h-psr_pil", HW_H_PSR_PIL, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1732   { "h-psr_ps", HW_H_PSR_PS, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1733   { "h-psr_et", HW_H_PSR_ET, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1734   { "h-psr_s", HW_H_PSR_S, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1735   { "h-tbr_tba", HW_H_TBR_TBA, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1736   { "h-tbr_tt", HW_H_TBR_TT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1737   { "h-bpsr_bs", HW_H_BPSR_BS, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1738   { "h-bpsr_bet", HW_H_BPSR_BET, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1739   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1740   { "h-gr_double", HW_H_GR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1741   { "h-gr_hi", HW_H_GR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1742   { "h-gr_lo", HW_H_GR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1743   { "h-fr", HW_H_FR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1744   { "h-fr_double", HW_H_FR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1745   { "h-fr_int", HW_H_FR_INT, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1746   { "h-fr_hi", HW_H_FR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1747   { "h-fr_lo", HW_H_FR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1748   { "h-fr_0", HW_H_FR_0, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1749   { "h-fr_1", HW_H_FR_1, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1750   { "h-fr_2", HW_H_FR_2, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1751   { "h-fr_3", HW_H_FR_3, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1752   { "h-cpr", HW_H_CPR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cpr_names, { 0|A(PROFILE), { (1<<MACH_FRV) } } },
1753   { "h-cpr_double", HW_H_CPR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cpr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_FRV) } } },
1754   { "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_spr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1755   { "h-accg", HW_H_ACCG, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_accg_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1756   { "h-acc40S", HW_H_ACC40S, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1757   { "h-acc40U", HW_H_ACC40U, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1758   { "h-iccr", HW_H_ICCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1759   { "h-fccr", HW_H_FCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1760   { "h-cccr", HW_H_CCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1761   { "h-pack", HW_H_PACK, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_pack, { 0, { (1<<MACH_BASE) } } },
1762   { "h-hint-taken", HW_H_HINT_TAKEN, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_hint_taken, { 0, { (1<<MACH_BASE) } } },
1763   { "h-hint-not-taken", HW_H_HINT_NOT_TAKEN, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_hint_not_taken, { 0, { (1<<MACH_BASE) } } },
1764   { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
1765 };
1766
1767 #undef A
1768
1769
1770 /* The instruction field table.  */
1771
1772 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1773 #define A(a) (1 << CGEN_IFLD_##a)
1774 #else
1775 #define A(a) (1 << CGEN_IFLD_/**/a)
1776 #endif
1777
1778 const CGEN_IFLD frv_cgen_ifld_table[] =
1779 {
1780   { FRV_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
1781   { FRV_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
1782   { FRV_F_PACK, "f-pack", 0, 32, 31, 1, { 0, { (1<<MACH_BASE) } }  },
1783   { FRV_F_OP, "f-op", 0, 32, 24, 7, { 0, { (1<<MACH_BASE) } }  },
1784   { FRV_F_OPE1, "f-ope1", 0, 32, 11, 6, { 0, { (1<<MACH_BASE) } }  },
1785   { FRV_F_OPE2, "f-ope2", 0, 32, 9, 4, { 0, { (1<<MACH_BASE) } }  },
1786   { FRV_F_OPE3, "f-ope3", 0, 32, 15, 3, { 0, { (1<<MACH_BASE) } }  },
1787   { FRV_F_OPE4, "f-ope4", 0, 32, 7, 2, { 0, { (1<<MACH_BASE) } }  },
1788   { FRV_F_GRI, "f-GRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1789   { FRV_F_GRJ, "f-GRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
1790   { FRV_F_GRK, "f-GRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1791   { FRV_F_FRI, "f-FRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1792   { FRV_F_FRJ, "f-FRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
1793   { FRV_F_FRK, "f-FRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1794   { FRV_F_CPRI, "f-CPRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1795   { FRV_F_CPRJ, "f-CPRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
1796   { FRV_F_CPRK, "f-CPRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1797   { FRV_F_ACCGI, "f-ACCGi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1798   { FRV_F_ACCGK, "f-ACCGk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1799   { FRV_F_ACC40SI, "f-ACC40Si", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1800   { FRV_F_ACC40UI, "f-ACC40Ui", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1801   { FRV_F_ACC40SK, "f-ACC40Sk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1802   { FRV_F_ACC40UK, "f-ACC40Uk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1803   { FRV_F_CRI, "f-CRi", 0, 32, 14, 3, { 0, { (1<<MACH_BASE) } }  },
1804   { FRV_F_CRJ, "f-CRj", 0, 32, 2, 3, { 0, { (1<<MACH_BASE) } }  },
1805   { FRV_F_CRK, "f-CRk", 0, 32, 27, 3, { 0, { (1<<MACH_BASE) } }  },
1806   { FRV_F_CCI, "f-CCi", 0, 32, 11, 3, { 0, { (1<<MACH_BASE) } }  },
1807   { FRV_F_CRJ_INT, "f-CRj_int", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
1808   { FRV_F_CRJ_FLOAT, "f-CRj_float", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
1809   { FRV_F_ICCI_1, "f-ICCi_1", 0, 32, 11, 2, { 0, { (1<<MACH_BASE) } }  },
1810   { FRV_F_ICCI_2, "f-ICCi_2", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
1811   { FRV_F_ICCI_3, "f-ICCi_3", 0, 32, 1, 2, { 0, { (1<<MACH_BASE) } }  },
1812   { FRV_F_FCCI_1, "f-FCCi_1", 0, 32, 11, 2, { 0, { (1<<MACH_BASE) } }  },
1813   { FRV_F_FCCI_2, "f-FCCi_2", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
1814   { FRV_F_FCCI_3, "f-FCCi_3", 0, 32, 1, 2, { 0, { (1<<MACH_BASE) } }  },
1815   { FRV_F_FCCK, "f-FCCk", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
1816   { FRV_F_EIR, "f-eir", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1817   { FRV_F_S10, "f-s10", 0, 32, 9, 10, { 0, { (1<<MACH_BASE) } }  },
1818   { FRV_F_S12, "f-s12", 0, 32, 11, 12, { 0, { (1<<MACH_BASE) } }  },
1819   { FRV_F_D12, "f-d12", 0, 32, 11, 12, { 0, { (1<<MACH_BASE) } }  },
1820   { FRV_F_U16, "f-u16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
1821   { FRV_F_S16, "f-s16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
1822   { FRV_F_S6, "f-s6", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
1823   { FRV_F_S6_1, "f-s6_1", 0, 32, 11, 6, { 0, { (1<<MACH_BASE) } }  },
1824   { FRV_F_U6, "f-u6", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
1825   { FRV_F_S5, "f-s5", 0, 32, 4, 5, { 0, { (1<<MACH_BASE) } }  },
1826   { FRV_F_U12_H, "f-u12-h", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1827   { FRV_F_U12_L, "f-u12-l", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
1828   { FRV_F_INT_CC, "f-int-cc", 0, 32, 30, 4, { 0, { (1<<MACH_BASE) } }  },
1829   { FRV_F_FLT_CC, "f-flt-cc", 0, 32, 30, 4, { 0, { (1<<MACH_BASE) } }  },
1830   { FRV_F_COND, "f-cond", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } }  },
1831   { FRV_F_CCOND, "f-ccond", 0, 32, 12, 1, { 0, { (1<<MACH_BASE) } }  },
1832   { FRV_F_HINT, "f-hint", 0, 32, 17, 2, { 0, { (1<<MACH_BASE) } }  },
1833   { FRV_F_LI, "f-LI", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
1834   { FRV_F_LOCK, "f-lock", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
1835   { FRV_F_DEBUG, "f-debug", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
1836   { FRV_F_A, "f-A", 0, 32, 17, 1, { 0, { (1<<MACH_BASE) } }  },
1837   { FRV_F_AE, "f-ae", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
1838   { FRV_F_SPR_H, "f-spr-h", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1839   { FRV_F_SPR_L, "f-spr-l", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1840   { FRV_F_LABEL16, "f-label16", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
1841   { FRV_F_LABELH6, "f-labelH6", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1842   { FRV_F_LABELL18, "f-labelL18", 0, 32, 17, 18, { 0, { (1<<MACH_BASE) } }  },
1843   { FRV_F_ICCI_1_NULL, "f-ICCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1844   { FRV_F_ICCI_2_NULL, "f-ICCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1845   { FRV_F_ICCI_3_NULL, "f-ICCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1846   { FRV_F_FCCI_1_NULL, "f-FCCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1847   { FRV_F_FCCI_2_NULL, "f-FCCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1848   { FRV_F_FCCI_3_NULL, "f-FCCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1849   { FRV_F_RS_NULL, "f-rs-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1850   { FRV_F_GRI_NULL, "f-GRi-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1851   { FRV_F_GRJ_NULL, "f-GRj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1852   { FRV_F_GRK_NULL, "f-GRk-null", 0, 32, 30, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1853   { FRV_F_FRI_NULL, "f-FRi-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1854   { FRV_F_FRJ_NULL, "f-FRj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1855   { FRV_F_ACCJ_NULL, "f-ACCj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1856   { FRV_F_RD_NULL, "f-rd-null", 0, 32, 30, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1857   { FRV_F_COND_NULL, "f-cond-null", 0, 32, 30, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1858   { FRV_F_CCOND_NULL, "f-ccond-null", 0, 32, 12, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1859   { FRV_F_S12_NULL, "f-s12-null", 0, 32, 11, 12, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1860   { FRV_F_LABEL16_NULL, "f-label16-null", 0, 32, 15, 16, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1861   { FRV_F_MISC_NULL_1, "f-misc-null-1", 0, 32, 30, 5, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1862   { FRV_F_MISC_NULL_2, "f-misc-null-2", 0, 32, 11, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1863   { FRV_F_MISC_NULL_3, "f-misc-null-3", 0, 32, 11, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1864   { FRV_F_MISC_NULL_4, "f-misc-null-4", 0, 32, 17, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1865   { FRV_F_MISC_NULL_5, "f-misc-null-5", 0, 32, 17, 16, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1866   { FRV_F_MISC_NULL_6, "f-misc-null-6", 0, 32, 30, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1867   { FRV_F_MISC_NULL_7, "f-misc-null-7", 0, 32, 17, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1868   { FRV_F_MISC_NULL_8, "f-misc-null-8", 0, 32, 5, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1869   { FRV_F_MISC_NULL_9, "f-misc-null-9", 0, 32, 5, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1870   { FRV_F_MISC_NULL_10, "f-misc-null-10", 0, 32, 16, 5, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1871   { FRV_F_MISC_NULL_11, "f-misc-null-11", 0, 32, 5, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1872   { FRV_F_LI_OFF, "f-LI-off", 0, 32, 25, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1873   { FRV_F_LI_ON, "f-LI-on", 0, 32, 25, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1874   { 0, 0, 0, 0, 0, 0, {0, {0}} }
1875 };
1876
1877 #undef A
1878
1879
1880
1881 /* multi ifield declarations */
1882
1883 const CGEN_MAYBE_MULTI_IFLD FRV_F_U12_MULTI_IFIELD [];
1884 const CGEN_MAYBE_MULTI_IFLD FRV_F_SPR_MULTI_IFIELD [];
1885 const CGEN_MAYBE_MULTI_IFLD FRV_F_LABEL24_MULTI_IFIELD [];
1886
1887
1888 /* multi ifield definitions */
1889
1890 const CGEN_MAYBE_MULTI_IFLD FRV_F_U12_MULTI_IFIELD [] =
1891 {
1892     { 0, &(frv_cgen_ifld_table[46]) },
1893     { 0, &(frv_cgen_ifld_table[47]) },
1894     {0,0}
1895 };
1896 const CGEN_MAYBE_MULTI_IFLD FRV_F_SPR_MULTI_IFIELD [] =
1897 {
1898     { 0, &(frv_cgen_ifld_table[58]) },
1899     { 0, &(frv_cgen_ifld_table[59]) },
1900     {0,0}
1901 };
1902 const CGEN_MAYBE_MULTI_IFLD FRV_F_LABEL24_MULTI_IFIELD [] =
1903 {
1904     { 0, &(frv_cgen_ifld_table[61]) },
1905     { 0, &(frv_cgen_ifld_table[62]) },
1906     {0,0}
1907 };
1908
1909 /* The operand table.  */
1910
1911 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1912 #define A(a) (1 << CGEN_OPERAND_##a)
1913 #else
1914 #define A(a) (1 << CGEN_OPERAND_/**/a)
1915 #endif
1916 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1917 #define OPERAND(op) FRV_OPERAND_##op
1918 #else
1919 #define OPERAND(op) FRV_OPERAND_/**/op
1920 #endif
1921
1922 const CGEN_OPERAND frv_cgen_operand_table[] =
1923 {
1924 /* pc: program counter */
1925   { "pc", FRV_OPERAND_PC, HW_H_PC, 0, 0,
1926     { 0, &(frv_cgen_ifld_table[0]) },
1927     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
1928 /* pack: packing bit */
1929   { "pack", FRV_OPERAND_PACK, HW_H_PACK, 31, 1,
1930     { 0, &(frv_cgen_ifld_table[2]) },
1931     { 0, { (1<<MACH_BASE) } }  },
1932 /* GRi: source register 1 */
1933   { "GRi", FRV_OPERAND_GRI, HW_H_GR, 17, 6,
1934     { 0, &(frv_cgen_ifld_table[8]) },
1935     { 0, { (1<<MACH_BASE) } }  },
1936 /* GRj: source register 2 */
1937   { "GRj", FRV_OPERAND_GRJ, HW_H_GR, 5, 6,
1938     { 0, &(frv_cgen_ifld_table[9]) },
1939     { 0, { (1<<MACH_BASE) } }  },
1940 /* GRk: destination register */
1941   { "GRk", FRV_OPERAND_GRK, HW_H_GR, 30, 6,
1942     { 0, &(frv_cgen_ifld_table[10]) },
1943     { 0, { (1<<MACH_BASE) } }  },
1944 /* GRkhi: destination register */
1945   { "GRkhi", FRV_OPERAND_GRKHI, HW_H_GR_HI, 30, 6,
1946     { 0, &(frv_cgen_ifld_table[10]) },
1947     { 0, { (1<<MACH_BASE) } }  },
1948 /* GRklo: destination register */
1949   { "GRklo", FRV_OPERAND_GRKLO, HW_H_GR_LO, 30, 6,
1950     { 0, &(frv_cgen_ifld_table[10]) },
1951     { 0, { (1<<MACH_BASE) } }  },
1952 /* GRdoublek: destination register */
1953   { "GRdoublek", FRV_OPERAND_GRDOUBLEK, HW_H_GR_DOUBLE, 30, 6,
1954     { 0, &(frv_cgen_ifld_table[10]) },
1955     { 0, { (1<<MACH_BASE) } }  },
1956 /* ACC40Si: signed accumulator */
1957   { "ACC40Si", FRV_OPERAND_ACC40SI, HW_H_ACC40S, 17, 6,
1958     { 0, &(frv_cgen_ifld_table[19]) },
1959     { 0, { (1<<MACH_BASE) } }  },
1960 /* ACC40Ui: unsigned accumulator */
1961   { "ACC40Ui", FRV_OPERAND_ACC40UI, HW_H_ACC40U, 17, 6,
1962     { 0, &(frv_cgen_ifld_table[20]) },
1963     { 0, { (1<<MACH_BASE) } }  },
1964 /* ACC40Sk: target accumulator */
1965   { "ACC40Sk", FRV_OPERAND_ACC40SK, HW_H_ACC40S, 30, 6,
1966     { 0, &(frv_cgen_ifld_table[21]) },
1967     { 0, { (1<<MACH_BASE) } }  },
1968 /* ACC40Uk: target accumulator */
1969   { "ACC40Uk", FRV_OPERAND_ACC40UK, HW_H_ACC40U, 30, 6,
1970     { 0, &(frv_cgen_ifld_table[22]) },
1971     { 0, { (1<<MACH_BASE) } }  },
1972 /* ACCGi: source register */
1973   { "ACCGi", FRV_OPERAND_ACCGI, HW_H_ACCG, 17, 6,
1974     { 0, &(frv_cgen_ifld_table[17]) },
1975     { 0, { (1<<MACH_BASE) } }  },
1976 /* ACCGk: target register */
1977   { "ACCGk", FRV_OPERAND_ACCGK, HW_H_ACCG, 30, 6,
1978     { 0, &(frv_cgen_ifld_table[18]) },
1979     { 0, { (1<<MACH_BASE) } }  },
1980 /* CPRi: source register */
1981   { "CPRi", FRV_OPERAND_CPRI, HW_H_CPR, 17, 6,
1982     { 0, &(frv_cgen_ifld_table[14]) },
1983     { 0, { (1<<MACH_FRV) } }  },
1984 /* CPRj: source register */
1985   { "CPRj", FRV_OPERAND_CPRJ, HW_H_CPR, 5, 6,
1986     { 0, &(frv_cgen_ifld_table[15]) },
1987     { 0, { (1<<MACH_FRV) } }  },
1988 /* CPRk: destination register */
1989   { "CPRk", FRV_OPERAND_CPRK, HW_H_CPR, 30, 6,
1990     { 0, &(frv_cgen_ifld_table[16]) },
1991     { 0, { (1<<MACH_FRV) } }  },
1992 /* CPRdoublek: destination register */
1993   { "CPRdoublek", FRV_OPERAND_CPRDOUBLEK, HW_H_CPR_DOUBLE, 30, 6,
1994     { 0, &(frv_cgen_ifld_table[16]) },
1995     { 0, { (1<<MACH_FRV) } }  },
1996 /* FRinti: source register 1 */
1997   { "FRinti", FRV_OPERAND_FRINTI, HW_H_FR_INT, 17, 6,
1998     { 0, &(frv_cgen_ifld_table[11]) },
1999     { 0, { (1<<MACH_BASE) } }  },
2000 /* FRintj: source register 2 */
2001   { "FRintj", FRV_OPERAND_FRINTJ, HW_H_FR_INT, 5, 6,
2002     { 0, &(frv_cgen_ifld_table[12]) },
2003     { 0, { (1<<MACH_BASE) } }  },
2004 /* FRintk: target register */
2005   { "FRintk", FRV_OPERAND_FRINTK, HW_H_FR_INT, 30, 6,
2006     { 0, &(frv_cgen_ifld_table[13]) },
2007     { 0, { (1<<MACH_BASE) } }  },
2008 /* FRi: source register 1 */
2009   { "FRi", FRV_OPERAND_FRI, HW_H_FR, 17, 6,
2010     { 0, &(frv_cgen_ifld_table[11]) },
2011     { 0, { (1<<MACH_BASE) } }  },
2012 /* FRj: source register 2 */
2013   { "FRj", FRV_OPERAND_FRJ, HW_H_FR, 5, 6,
2014     { 0, &(frv_cgen_ifld_table[12]) },
2015     { 0, { (1<<MACH_BASE) } }  },
2016 /* FRk: destination register */
2017   { "FRk", FRV_OPERAND_FRK, HW_H_FR, 30, 6,
2018     { 0, &(frv_cgen_ifld_table[13]) },
2019     { 0, { (1<<MACH_BASE) } }  },
2020 /* FRkhi: destination register */
2021   { "FRkhi", FRV_OPERAND_FRKHI, HW_H_FR_HI, 30, 6,
2022     { 0, &(frv_cgen_ifld_table[13]) },
2023     { 0, { (1<<MACH_BASE) } }  },
2024 /* FRklo: destination register */
2025   { "FRklo", FRV_OPERAND_FRKLO, HW_H_FR_LO, 30, 6,
2026     { 0, &(frv_cgen_ifld_table[13]) },
2027     { 0, { (1<<MACH_BASE) } }  },
2028 /* FRdoublei: source register 1 */
2029   { "FRdoublei", FRV_OPERAND_FRDOUBLEI, HW_H_FR_DOUBLE, 17, 6,
2030     { 0, &(frv_cgen_ifld_table[11]) },
2031     { 0, { (1<<MACH_BASE) } }  },
2032 /* FRdoublej: source register 2 */
2033   { "FRdoublej", FRV_OPERAND_FRDOUBLEJ, HW_H_FR_DOUBLE, 5, 6,
2034     { 0, &(frv_cgen_ifld_table[12]) },
2035     { 0, { (1<<MACH_BASE) } }  },
2036 /* FRdoublek: target register */
2037   { "FRdoublek", FRV_OPERAND_FRDOUBLEK, HW_H_FR_DOUBLE, 30, 6,
2038     { 0, &(frv_cgen_ifld_table[13]) },
2039     { 0, { (1<<MACH_BASE) } }  },
2040 /* CRi: source register 1 */
2041   { "CRi", FRV_OPERAND_CRI, HW_H_CCCR, 14, 3,
2042     { 0, &(frv_cgen_ifld_table[23]) },
2043     { 0, { (1<<MACH_BASE) } }  },
2044 /* CRj: source register 2 */
2045   { "CRj", FRV_OPERAND_CRJ, HW_H_CCCR, 2, 3,
2046     { 0, &(frv_cgen_ifld_table[24]) },
2047     { 0, { (1<<MACH_BASE) } }  },
2048 /* CRj_int: destination register */
2049   { "CRj_int", FRV_OPERAND_CRJ_INT, HW_H_CCCR, 26, 2,
2050     { 0, &(frv_cgen_ifld_table[27]) },
2051     { 0, { (1<<MACH_BASE) } }  },
2052 /* CRj_float: destination register */
2053   { "CRj_float", FRV_OPERAND_CRJ_FLOAT, HW_H_CCCR, 26, 2,
2054     { 0, &(frv_cgen_ifld_table[28]) },
2055     { 0, { (1<<MACH_BASE) } }  },
2056 /* CRk: destination register */
2057   { "CRk", FRV_OPERAND_CRK, HW_H_CCCR, 27, 3,
2058     { 0, &(frv_cgen_ifld_table[25]) },
2059     { 0, { (1<<MACH_BASE) } }  },
2060 /* CCi: condition   register */
2061   { "CCi", FRV_OPERAND_CCI, HW_H_CCCR, 11, 3,
2062     { 0, &(frv_cgen_ifld_table[26]) },
2063     { 0, { (1<<MACH_BASE) } }  },
2064 /* ICCi_1: condition   register */
2065   { "ICCi_1", FRV_OPERAND_ICCI_1, HW_H_ICCR, 11, 2,
2066     { 0, &(frv_cgen_ifld_table[29]) },
2067     { 0, { (1<<MACH_BASE) } }  },
2068 /* ICCi_2: condition   register */
2069   { "ICCi_2", FRV_OPERAND_ICCI_2, HW_H_ICCR, 26, 2,
2070     { 0, &(frv_cgen_ifld_table[30]) },
2071     { 0, { (1<<MACH_BASE) } }  },
2072 /* ICCi_3: condition   register */
2073   { "ICCi_3", FRV_OPERAND_ICCI_3, HW_H_ICCR, 1, 2,
2074     { 0, &(frv_cgen_ifld_table[31]) },
2075     { 0, { (1<<MACH_BASE) } }  },
2076 /* FCCi_1: condition   register */
2077   { "FCCi_1", FRV_OPERAND_FCCI_1, HW_H_FCCR, 11, 2,
2078     { 0, &(frv_cgen_ifld_table[32]) },
2079     { 0, { (1<<MACH_BASE) } }  },
2080 /* FCCi_2: condition   register */
2081   { "FCCi_2", FRV_OPERAND_FCCI_2, HW_H_FCCR, 26, 2,
2082     { 0, &(frv_cgen_ifld_table[33]) },
2083     { 0, { (1<<MACH_BASE) } }  },
2084 /* FCCi_3: condition   register */
2085   { "FCCi_3", FRV_OPERAND_FCCI_3, HW_H_FCCR, 1, 2,
2086     { 0, &(frv_cgen_ifld_table[34]) },
2087     { 0, { (1<<MACH_BASE) } }  },
2088 /* FCCk: condition   register */
2089   { "FCCk", FRV_OPERAND_FCCK, HW_H_FCCR, 26, 2,
2090     { 0, &(frv_cgen_ifld_table[35]) },
2091     { 0, { (1<<MACH_BASE) } }  },
2092 /* eir: exception insn reg */
2093   { "eir", FRV_OPERAND_EIR, HW_H_UINT, 17, 6,
2094     { 0, &(frv_cgen_ifld_table[36]) },
2095     { 0, { (1<<MACH_BASE) } }  },
2096 /* s10: 10 bit signed immediate */
2097   { "s10", FRV_OPERAND_S10, HW_H_SINT, 9, 10,
2098     { 0, &(frv_cgen_ifld_table[37]) },
2099     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2100 /* u16: 16 bit unsigned immediate */
2101   { "u16", FRV_OPERAND_U16, HW_H_UINT, 15, 16,
2102     { 0, &(frv_cgen_ifld_table[40]) },
2103     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2104 /* s16: 16 bit signed   immediate */
2105   { "s16", FRV_OPERAND_S16, HW_H_SINT, 15, 16,
2106     { 0, &(frv_cgen_ifld_table[41]) },
2107     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2108 /* s6: 6  bit signed   immediate */
2109   { "s6", FRV_OPERAND_S6, HW_H_SINT, 5, 6,
2110     { 0, &(frv_cgen_ifld_table[42]) },
2111     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2112 /* s6_1: 6  bit signed   immediate */
2113   { "s6_1", FRV_OPERAND_S6_1, HW_H_SINT, 11, 6,
2114     { 0, &(frv_cgen_ifld_table[43]) },
2115     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2116 /* u6: 6  bit unsigned immediate */
2117   { "u6", FRV_OPERAND_U6, HW_H_UINT, 5, 6,
2118     { 0, &(frv_cgen_ifld_table[44]) },
2119     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2120 /* s5: 5  bit signed   immediate */
2121   { "s5", FRV_OPERAND_S5, HW_H_SINT, 4, 5,
2122     { 0, &(frv_cgen_ifld_table[45]) },
2123     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2124 /* cond: conditional arithmetic */
2125   { "cond", FRV_OPERAND_COND, HW_H_UINT, 8, 1,
2126     { 0, &(frv_cgen_ifld_table[50]) },
2127     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2128 /* ccond: lr branch condition */
2129   { "ccond", FRV_OPERAND_CCOND, HW_H_UINT, 12, 1,
2130     { 0, &(frv_cgen_ifld_table[51]) },
2131     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2132 /* hint: 2 bit branch predictor */
2133   { "hint", FRV_OPERAND_HINT, HW_H_UINT, 17, 2,
2134     { 0, &(frv_cgen_ifld_table[52]) },
2135     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2136 /* hint_taken: 2 bit branch predictor */
2137   { "hint_taken", FRV_OPERAND_HINT_TAKEN, HW_H_HINT_TAKEN, 17, 2,
2138     { 0, &(frv_cgen_ifld_table[52]) },
2139     { 0, { (1<<MACH_BASE) } }  },
2140 /* hint_not_taken: 2 bit branch predictor */
2141   { "hint_not_taken", FRV_OPERAND_HINT_NOT_TAKEN, HW_H_HINT_NOT_TAKEN, 17, 2,
2142     { 0, &(frv_cgen_ifld_table[52]) },
2143     { 0, { (1<<MACH_BASE) } }  },
2144 /* LI: link indicator */
2145   { "LI", FRV_OPERAND_LI, HW_H_UINT, 25, 1,
2146     { 0, &(frv_cgen_ifld_table[53]) },
2147     { 0, { (1<<MACH_BASE) } }  },
2148 /* lock: cache lock indicator */
2149   { "lock", FRV_OPERAND_LOCK, HW_H_UINT, 25, 1,
2150     { 0, &(frv_cgen_ifld_table[54]) },
2151     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2152 /* debug: debug mode indicator */
2153   { "debug", FRV_OPERAND_DEBUG, HW_H_UINT, 25, 1,
2154     { 0, &(frv_cgen_ifld_table[55]) },
2155     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2156 /* A: all accumulator indicator */
2157   { "A", FRV_OPERAND_A, HW_H_UINT, 17, 1,
2158     { 0, &(frv_cgen_ifld_table[56]) },
2159     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2160 /* ae: all entries indicator */
2161   { "ae", FRV_OPERAND_AE, HW_H_UINT, 25, 1,
2162     { 0, &(frv_cgen_ifld_table[57]) },
2163     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2164 /* label16: 18 bit pc relative address */
2165   { "label16", FRV_OPERAND_LABEL16, HW_H_IADDR, 15, 16,
2166     { 0, &(frv_cgen_ifld_table[60]) },
2167     { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
2168 /* label24: 26 bit pc relative address */
2169   { "label24", FRV_OPERAND_LABEL24, HW_H_IADDR, 17, 24,
2170     { 2, &(FRV_F_LABEL24_MULTI_IFIELD[0]) },
2171     { 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
2172 /* d12: 12 bit signed immediate */
2173   { "d12", FRV_OPERAND_D12, HW_H_SINT, 11, 12,
2174     { 0, &(frv_cgen_ifld_table[39]) },
2175     { 0, { (1<<MACH_BASE) } }  },
2176 /* s12: 12 bit signed immediate */
2177   { "s12", FRV_OPERAND_S12, HW_H_SINT, 11, 12,
2178     { 0, &(frv_cgen_ifld_table[39]) },
2179     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2180 /* u12: 12 bit signed immediate */
2181   { "u12", FRV_OPERAND_U12, HW_H_SINT, 5, 12,
2182     { 2, &(FRV_F_U12_MULTI_IFIELD[0]) },
2183     { 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
2184 /* spr: special purpose register */
2185   { "spr", FRV_OPERAND_SPR, HW_H_SPR, 17, 12,
2186     { 2, &(FRV_F_SPR_MULTI_IFIELD[0]) },
2187     { 0|A(VIRTUAL), { (1<<MACH_BASE) } }  },
2188 /* ulo16: 16 bit unsigned immediate, for #lo() */
2189   { "ulo16", FRV_OPERAND_ULO16, HW_H_UINT, 15, 16,
2190     { 0, &(frv_cgen_ifld_table[40]) },
2191     { 0, { (1<<MACH_BASE) } }  },
2192 /* slo16: 16 bit unsigned immediate, for #lo() */
2193   { "slo16", FRV_OPERAND_SLO16, HW_H_SINT, 15, 16,
2194     { 0, &(frv_cgen_ifld_table[41]) },
2195     { 0, { (1<<MACH_BASE) } }  },
2196 /* uhi16: 16 bit unsigned immediate, for #hi() */
2197   { "uhi16", FRV_OPERAND_UHI16, HW_H_UINT, 15, 16,
2198     { 0, &(frv_cgen_ifld_table[40]) },
2199     { 0, { (1<<MACH_BASE) } }  },
2200 /* psr_esr: PSR.ESR bit */
2201   { "psr_esr", FRV_OPERAND_PSR_ESR, HW_H_PSR_ESR, 0, 0,
2202     { 0, 0 },
2203     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2204 /* psr_s: PSR.S   bit */
2205   { "psr_s", FRV_OPERAND_PSR_S, HW_H_PSR_S, 0, 0,
2206     { 0, 0 },
2207     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2208 /* psr_ps: PSR.PS  bit */
2209   { "psr_ps", FRV_OPERAND_PSR_PS, HW_H_PSR_PS, 0, 0,
2210     { 0, 0 },
2211     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2212 /* psr_et: PSR.ET  bit */
2213   { "psr_et", FRV_OPERAND_PSR_ET, HW_H_PSR_ET, 0, 0,
2214     { 0, 0 },
2215     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2216 /* bpsr_bs: BPSR.BS  bit */
2217   { "bpsr_bs", FRV_OPERAND_BPSR_BS, HW_H_BPSR_BS, 0, 0,
2218     { 0, 0 },
2219     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2220 /* bpsr_bet: BPSR.BET bit */
2221   { "bpsr_bet", FRV_OPERAND_BPSR_BET, HW_H_BPSR_BET, 0, 0,
2222     { 0, 0 },
2223     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2224 /* tbr_tba: TBR.TBA */
2225   { "tbr_tba", FRV_OPERAND_TBR_TBA, HW_H_TBR_TBA, 0, 0,
2226     { 0, 0 },
2227     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2228 /* tbr_tt: TBR.TT */
2229   { "tbr_tt", FRV_OPERAND_TBR_TT, HW_H_TBR_TT, 0, 0,
2230     { 0, 0 },
2231     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2232   { 0, 0, 0, 0, 0, {0, {0}} }
2233 };
2234
2235 #undef A
2236
2237
2238 /* The instruction table.  */
2239
2240 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2241 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
2242 #define A(a) (1 << CGEN_INSN_##a)
2243 #else
2244 #define A(a) (1 << CGEN_INSN_/**/a)
2245 #endif
2246
2247 static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
2248 {
2249   /* Special null first entry.
2250      A `num' value of zero is thus invalid.
2251      Also, the special `invalid' insn resides here.  */
2252   { 0, 0, 0, 0, {0, {0}} },
2253 /* add$pack $GRi,$GRj,$GRk */
2254   {
2255     FRV_INSN_ADD, "add", "add", 32,
2256     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2257   },
2258 /* sub$pack $GRi,$GRj,$GRk */
2259   {
2260     FRV_INSN_SUB, "sub", "sub", 32,
2261     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2262   },
2263 /* and$pack $GRi,$GRj,$GRk */
2264   {
2265     FRV_INSN_AND, "and", "and", 32,
2266     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2267   },
2268 /* or$pack $GRi,$GRj,$GRk */
2269   {
2270     FRV_INSN_OR, "or", "or", 32,
2271     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2272   },
2273 /* xor$pack $GRi,$GRj,$GRk */
2274   {
2275     FRV_INSN_XOR, "xor", "xor", 32,
2276     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2277   },
2278 /* not$pack $GRj,$GRk */
2279   {
2280     FRV_INSN_NOT, "not", "not", 32,
2281     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2282   },
2283 /* sdiv$pack $GRi,$GRj,$GRk */
2284   {
2285     FRV_INSN_SDIV, "sdiv", "sdiv", 32,
2286     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2287   },
2288 /* nsdiv$pack $GRi,$GRj,$GRk */
2289   {
2290     FRV_INSN_NSDIV, "nsdiv", "nsdiv", 32,
2291     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } }
2292   },
2293 /* udiv$pack $GRi,$GRj,$GRk */
2294   {
2295     FRV_INSN_UDIV, "udiv", "udiv", 32,
2296     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2297   },
2298 /* nudiv$pack $GRi,$GRj,$GRk */
2299   {
2300     FRV_INSN_NUDIV, "nudiv", "nudiv", 32,
2301     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } }
2302   },
2303 /* smul$pack $GRi,$GRj,$GRdoublek */
2304   {
2305     FRV_INSN_SMUL, "smul", "smul", 32,
2306     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2307   },
2308 /* umul$pack $GRi,$GRj,$GRdoublek */
2309   {
2310     FRV_INSN_UMUL, "umul", "umul", 32,
2311     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2312   },
2313 /* sll$pack $GRi,$GRj,$GRk */
2314   {
2315     FRV_INSN_SLL, "sll", "sll", 32,
2316     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2317   },
2318 /* srl$pack $GRi,$GRj,$GRk */
2319   {
2320     FRV_INSN_SRL, "srl", "srl", 32,
2321     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2322   },
2323 /* sra$pack $GRi,$GRj,$GRk */
2324   {
2325     FRV_INSN_SRA, "sra", "sra", 32,
2326     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2327   },
2328 /* scan$pack $GRi,$GRj,$GRk */
2329   {
2330     FRV_INSN_SCAN, "scan", "scan", 32,
2331     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2332   },
2333 /* cadd$pack $GRi,$GRj,$GRk,$CCi,$cond */
2334   {
2335     FRV_INSN_CADD, "cadd", "cadd", 32,
2336     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2337   },
2338 /* csub$pack $GRi,$GRj,$GRk,$CCi,$cond */
2339   {
2340     FRV_INSN_CSUB, "csub", "csub", 32,
2341     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2342   },
2343 /* cand$pack $GRi,$GRj,$GRk,$CCi,$cond */
2344   {
2345     FRV_INSN_CAND, "cand", "cand", 32,
2346     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2347   },
2348 /* cor$pack $GRi,$GRj,$GRk,$CCi,$cond */
2349   {
2350     FRV_INSN_COR, "cor", "cor", 32,
2351     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2352   },
2353 /* cxor$pack $GRi,$GRj,$GRk,$CCi,$cond */
2354   {
2355     FRV_INSN_CXOR, "cxor", "cxor", 32,
2356     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2357   },
2358 /* cnot$pack $GRj,$GRk,$CCi,$cond */
2359   {
2360     FRV_INSN_CNOT, "cnot", "cnot", 32,
2361     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2362   },
2363 /* csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */
2364   {
2365     FRV_INSN_CSMUL, "csmul", "csmul", 32,
2366     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2367   },
2368 /* csdiv$pack $GRi,$GRj,$GRk,$CCi,$cond */
2369   {
2370     FRV_INSN_CSDIV, "csdiv", "csdiv", 32,
2371     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2372   },
2373 /* cudiv$pack $GRi,$GRj,$GRk,$CCi,$cond */
2374   {
2375     FRV_INSN_CUDIV, "cudiv", "cudiv", 32,
2376     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2377   },
2378 /* csll$pack $GRi,$GRj,$GRk,$CCi,$cond */
2379   {
2380     FRV_INSN_CSLL, "csll", "csll", 32,
2381     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2382   },
2383 /* csrl$pack $GRi,$GRj,$GRk,$CCi,$cond */
2384   {
2385     FRV_INSN_CSRL, "csrl", "csrl", 32,
2386     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2387   },
2388 /* csra$pack $GRi,$GRj,$GRk,$CCi,$cond */
2389   {
2390     FRV_INSN_CSRA, "csra", "csra", 32,
2391     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2392   },
2393 /* cscan$pack $GRi,$GRj,$GRk,$CCi,$cond */
2394   {
2395     FRV_INSN_CSCAN, "cscan", "cscan", 32,
2396     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2397   },
2398 /* addcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2399   {
2400     FRV_INSN_ADDCC, "addcc", "addcc", 32,
2401     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2402   },
2403 /* subcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2404   {
2405     FRV_INSN_SUBCC, "subcc", "subcc", 32,
2406     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2407   },
2408 /* andcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2409   {
2410     FRV_INSN_ANDCC, "andcc", "andcc", 32,
2411     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2412   },
2413 /* orcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2414   {
2415     FRV_INSN_ORCC, "orcc", "orcc", 32,
2416     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2417   },
2418 /* xorcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2419   {
2420     FRV_INSN_XORCC, "xorcc", "xorcc", 32,
2421     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2422   },
2423 /* sllcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2424   {
2425     FRV_INSN_SLLCC, "sllcc", "sllcc", 32,
2426     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2427   },
2428 /* srlcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2429   {
2430     FRV_INSN_SRLCC, "srlcc", "srlcc", 32,
2431     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2432   },
2433 /* sracc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2434   {
2435     FRV_INSN_SRACC, "sracc", "sracc", 32,
2436     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2437   },
2438 /* smulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */
2439   {
2440     FRV_INSN_SMULCC, "smulcc", "smulcc", 32,
2441     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2442   },
2443 /* umulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */
2444   {
2445     FRV_INSN_UMULCC, "umulcc", "umulcc", 32,
2446     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2447   },
2448 /* caddcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2449   {
2450     FRV_INSN_CADDCC, "caddcc", "caddcc", 32,
2451     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2452   },
2453 /* csubcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2454   {
2455     FRV_INSN_CSUBCC, "csubcc", "csubcc", 32,
2456     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2457   },
2458 /* csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */
2459   {
2460     FRV_INSN_CSMULCC, "csmulcc", "csmulcc", 32,
2461     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2462   },
2463 /* candcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2464   {
2465     FRV_INSN_CANDCC, "candcc", "candcc", 32,
2466     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2467   },
2468 /* corcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2469   {
2470     FRV_INSN_CORCC, "corcc", "corcc", 32,
2471     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2472   },
2473 /* cxorcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2474   {
2475     FRV_INSN_CXORCC, "cxorcc", "cxorcc", 32,
2476     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2477   },
2478 /* csllcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2479   {
2480     FRV_INSN_CSLLCC, "csllcc", "csllcc", 32,
2481     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2482   },
2483 /* csrlcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2484   {
2485     FRV_INSN_CSRLCC, "csrlcc", "csrlcc", 32,
2486     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2487   },
2488 /* csracc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2489   {
2490     FRV_INSN_CSRACC, "csracc", "csracc", 32,
2491     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2492   },
2493 /* addx$pack $GRi,$GRj,$GRk,$ICCi_1 */
2494   {
2495     FRV_INSN_ADDX, "addx", "addx", 32,
2496     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2497   },
2498 /* subx$pack $GRi,$GRj,$GRk,$ICCi_1 */
2499   {
2500     FRV_INSN_SUBX, "subx", "subx", 32,
2501     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2502   },
2503 /* addxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2504   {
2505     FRV_INSN_ADDXCC, "addxcc", "addxcc", 32,
2506     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2507   },
2508 /* subxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2509   {
2510     FRV_INSN_SUBXCC, "subxcc", "subxcc", 32,
2511     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2512   },
2513 /* addi$pack $GRi,$s12,$GRk */
2514   {
2515     FRV_INSN_ADDI, "addi", "addi", 32,
2516     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2517   },
2518 /* subi$pack $GRi,$s12,$GRk */
2519   {
2520     FRV_INSN_SUBI, "subi", "subi", 32,
2521     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2522   },
2523 /* andi$pack $GRi,$s12,$GRk */
2524   {
2525     FRV_INSN_ANDI, "andi", "andi", 32,
2526     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2527   },
2528 /* ori$pack $GRi,$s12,$GRk */
2529   {
2530     FRV_INSN_ORI, "ori", "ori", 32,
2531     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2532   },
2533 /* xori$pack $GRi,$s12,$GRk */
2534   {
2535     FRV_INSN_XORI, "xori", "xori", 32,
2536     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2537   },
2538 /* sdivi$pack $GRi,$s12,$GRk */
2539   {
2540     FRV_INSN_SDIVI, "sdivi", "sdivi", 32,
2541     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2542   },
2543 /* nsdivi$pack $GRi,$s12,$GRk */
2544   {
2545     FRV_INSN_NSDIVI, "nsdivi", "nsdivi", 32,
2546     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } }
2547   },
2548 /* udivi$pack $GRi,$s12,$GRk */
2549   {
2550     FRV_INSN_UDIVI, "udivi", "udivi", 32,
2551     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2552   },
2553 /* nudivi$pack $GRi,$s12,$GRk */
2554   {
2555     FRV_INSN_NUDIVI, "nudivi", "nudivi", 32,
2556     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } }
2557   },
2558 /* smuli$pack $GRi,$s12,$GRdoublek */
2559   {
2560     FRV_INSN_SMULI, "smuli", "smuli", 32,
2561     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2562   },
2563 /* umuli$pack $GRi,$s12,$GRdoublek */
2564   {
2565     FRV_INSN_UMULI, "umuli", "umuli", 32,
2566     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2567   },
2568 /* slli$pack $GRi,$s12,$GRk */
2569   {
2570     FRV_INSN_SLLI, "slli", "slli", 32,
2571     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2572   },
2573 /* srli$pack $GRi,$s12,$GRk */
2574   {
2575     FRV_INSN_SRLI, "srli", "srli", 32,
2576     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2577   },
2578 /* srai$pack $GRi,$s12,$GRk */
2579   {
2580     FRV_INSN_SRAI, "srai", "srai", 32,
2581     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2582   },
2583 /* scani$pack $GRi,$s12,$GRk */
2584   {
2585     FRV_INSN_SCANI, "scani", "scani", 32,
2586     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2587   },
2588 /* addicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2589   {
2590     FRV_INSN_ADDICC, "addicc", "addicc", 32,
2591     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2592   },
2593 /* subicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2594   {
2595     FRV_INSN_SUBICC, "subicc", "subicc", 32,
2596     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2597   },
2598 /* andicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2599   {
2600     FRV_INSN_ANDICC, "andicc", "andicc", 32,
2601     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2602   },
2603 /* oricc$pack $GRi,$s10,$GRk,$ICCi_1 */
2604   {
2605     FRV_INSN_ORICC, "oricc", "oricc", 32,
2606     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2607   },
2608 /* xoricc$pack $GRi,$s10,$GRk,$ICCi_1 */
2609   {
2610     FRV_INSN_XORICC, "xoricc", "xoricc", 32,
2611     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2612   },
2613 /* smulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */
2614   {
2615     FRV_INSN_SMULICC, "smulicc", "smulicc", 32,
2616     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2617   },
2618 /* umulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */
2619   {
2620     FRV_INSN_UMULICC, "umulicc", "umulicc", 32,
2621     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2622   },
2623 /* sllicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2624   {
2625     FRV_INSN_SLLICC, "sllicc", "sllicc", 32,
2626     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2627   },
2628 /* srlicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2629   {
2630     FRV_INSN_SRLICC, "srlicc", "srlicc", 32,
2631     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2632   },
2633 /* sraicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2634   {
2635     FRV_INSN_SRAICC, "sraicc", "sraicc", 32,
2636     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2637   },
2638 /* addxi$pack $GRi,$s10,$GRk,$ICCi_1 */
2639   {
2640     FRV_INSN_ADDXI, "addxi", "addxi", 32,
2641     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2642   },
2643 /* subxi$pack $GRi,$s10,$GRk,$ICCi_1 */
2644   {
2645     FRV_INSN_SUBXI, "subxi", "subxi", 32,
2646     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2647   },
2648 /* addxicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2649   {
2650     FRV_INSN_ADDXICC, "addxicc", "addxicc", 32,
2651     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2652   },
2653 /* subxicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2654   {
2655     FRV_INSN_SUBXICC, "subxicc", "subxicc", 32,
2656     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2657   },
2658 /* cmpb$pack $GRi,$GRj,$ICCi_1 */
2659   {
2660     FRV_INSN_CMPB, "cmpb", "cmpb", 32,
2661     { 0, { (1<<MACH_FR400), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_NONE } }
2662   },
2663 /* cmpba$pack $GRi,$GRj,$ICCi_1 */
2664   {
2665     FRV_INSN_CMPBA, "cmpba", "cmpba", 32,
2666     { 0, { (1<<MACH_FR400), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_NONE } }
2667   },
2668 /* setlo$pack $ulo16,$GRklo */
2669   {
2670     FRV_INSN_SETLO, "setlo", "setlo", 32,
2671     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2672   },
2673 /* sethi$pack $uhi16,$GRkhi */
2674   {
2675     FRV_INSN_SETHI, "sethi", "sethi", 32,
2676     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2677   },
2678 /* setlos$pack $slo16,$GRk */
2679   {
2680     FRV_INSN_SETLOS, "setlos", "setlos", 32,
2681     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2682   },
2683 /* ldsb$pack @($GRi,$GRj),$GRk */
2684   {
2685     FRV_INSN_LDSB, "ldsb", "ldsb", 32,
2686     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2687   },
2688 /* ldub$pack @($GRi,$GRj),$GRk */
2689   {
2690     FRV_INSN_LDUB, "ldub", "ldub", 32,
2691     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2692   },
2693 /* ldsh$pack @($GRi,$GRj),$GRk */
2694   {
2695     FRV_INSN_LDSH, "ldsh", "ldsh", 32,
2696     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2697   },
2698 /* lduh$pack @($GRi,$GRj),$GRk */
2699   {
2700     FRV_INSN_LDUH, "lduh", "lduh", 32,
2701     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2702   },
2703 /* ld$pack @($GRi,$GRj),$GRk */
2704   {
2705     FRV_INSN_LD, "ld", "ld", 32,
2706     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2707   },
2708 /* ldbf$pack @($GRi,$GRj),$FRintk */
2709   {
2710     FRV_INSN_LDBF, "ldbf", "ldbf", 32,
2711     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2712   },
2713 /* ldhf$pack @($GRi,$GRj),$FRintk */
2714   {
2715     FRV_INSN_LDHF, "ldhf", "ldhf", 32,
2716     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2717   },
2718 /* ldf$pack @($GRi,$GRj),$FRintk */
2719   {
2720     FRV_INSN_LDF, "ldf", "ldf", 32,
2721     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2722   },
2723 /* ldc$pack @($GRi,$GRj),$CPRk */
2724   {
2725     FRV_INSN_LDC, "ldc", "ldc", 32,
2726     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2727   },
2728 /* nldsb$pack @($GRi,$GRj),$GRk */
2729   {
2730     FRV_INSN_NLDSB, "nldsb", "nldsb", 32,
2731     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2732   },
2733 /* nldub$pack @($GRi,$GRj),$GRk */
2734   {
2735     FRV_INSN_NLDUB, "nldub", "nldub", 32,
2736     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2737   },
2738 /* nldsh$pack @($GRi,$GRj),$GRk */
2739   {
2740     FRV_INSN_NLDSH, "nldsh", "nldsh", 32,
2741     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2742   },
2743 /* nlduh$pack @($GRi,$GRj),$GRk */
2744   {
2745     FRV_INSN_NLDUH, "nlduh", "nlduh", 32,
2746     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2747   },
2748 /* nld$pack @($GRi,$GRj),$GRk */
2749   {
2750     FRV_INSN_NLD, "nld", "nld", 32,
2751     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2752   },
2753 /* nldbf$pack @($GRi,$GRj),$FRintk */
2754   {
2755     FRV_INSN_NLDBF, "nldbf", "nldbf", 32,
2756     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2757   },
2758 /* nldhf$pack @($GRi,$GRj),$FRintk */
2759   {
2760     FRV_INSN_NLDHF, "nldhf", "nldhf", 32,
2761     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2762   },
2763 /* nldf$pack @($GRi,$GRj),$FRintk */
2764   {
2765     FRV_INSN_NLDF, "nldf", "nldf", 32,
2766     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2767   },
2768 /* ldd$pack @($GRi,$GRj),$GRdoublek */
2769   {
2770     FRV_INSN_LDD, "ldd", "ldd", 32,
2771     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2772   },
2773 /* lddf$pack @($GRi,$GRj),$FRdoublek */
2774   {
2775     FRV_INSN_LDDF, "lddf", "lddf", 32,
2776     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2777   },
2778 /* lddc$pack @($GRi,$GRj),$CPRdoublek */
2779   {
2780     FRV_INSN_LDDC, "lddc", "lddc", 32,
2781     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2782   },
2783 /* nldd$pack @($GRi,$GRj),$GRdoublek */
2784   {
2785     FRV_INSN_NLDD, "nldd", "nldd", 32,
2786     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2787   },
2788 /* nlddf$pack @($GRi,$GRj),$FRdoublek */
2789   {
2790     FRV_INSN_NLDDF, "nlddf", "nlddf", 32,
2791     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2792   },
2793 /* ldq$pack @($GRi,$GRj),$GRk */
2794   {
2795     FRV_INSN_LDQ, "ldq", "ldq", 32,
2796     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2797   },
2798 /* ldqf$pack @($GRi,$GRj),$FRintk */
2799   {
2800     FRV_INSN_LDQF, "ldqf", "ldqf", 32,
2801     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2802   },
2803 /* ldqc$pack @($GRi,$GRj),$CPRk */
2804   {
2805     FRV_INSN_LDQC, "ldqc", "ldqc", 32,
2806     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2807   },
2808 /* nldq$pack @($GRi,$GRj),$GRk */
2809   {
2810     FRV_INSN_NLDQ, "nldq", "nldq", 32,
2811     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2812   },
2813 /* nldqf$pack @($GRi,$GRj),$FRintk */
2814   {
2815     FRV_INSN_NLDQF, "nldqf", "nldqf", 32,
2816     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2817   },
2818 /* ldsbu$pack @($GRi,$GRj),$GRk */
2819   {
2820     FRV_INSN_LDSBU, "ldsbu", "ldsbu", 32,
2821     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2822   },
2823 /* ldubu$pack @($GRi,$GRj),$GRk */
2824   {
2825     FRV_INSN_LDUBU, "ldubu", "ldubu", 32,
2826     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2827   },
2828 /* ldshu$pack @($GRi,$GRj),$GRk */
2829   {
2830     FRV_INSN_LDSHU, "ldshu", "ldshu", 32,
2831     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2832   },
2833 /* lduhu$pack @($GRi,$GRj),$GRk */
2834   {
2835     FRV_INSN_LDUHU, "lduhu", "lduhu", 32,
2836     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2837   },
2838 /* ldu$pack @($GRi,$GRj),$GRk */
2839   {
2840     FRV_INSN_LDU, "ldu", "ldu", 32,
2841     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2842   },
2843 /* nldsbu$pack @($GRi,$GRj),$GRk */
2844   {
2845     FRV_INSN_NLDSBU, "nldsbu", "nldsbu", 32,
2846     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2847   },
2848 /* nldubu$pack @($GRi,$GRj),$GRk */
2849   {
2850     FRV_INSN_NLDUBU, "nldubu", "nldubu", 32,
2851     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2852   },
2853 /* nldshu$pack @($GRi,$GRj),$GRk */
2854   {
2855     FRV_INSN_NLDSHU, "nldshu", "nldshu", 32,
2856     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2857   },
2858 /* nlduhu$pack @($GRi,$GRj),$GRk */
2859   {
2860     FRV_INSN_NLDUHU, "nlduhu", "nlduhu", 32,
2861     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2862   },
2863 /* nldu$pack @($GRi,$GRj),$GRk */
2864   {
2865     FRV_INSN_NLDU, "nldu", "nldu", 32,
2866     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2867   },
2868 /* ldbfu$pack @($GRi,$GRj),$FRintk */
2869   {
2870     FRV_INSN_LDBFU, "ldbfu", "ldbfu", 32,
2871     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2872   },
2873 /* ldhfu$pack @($GRi,$GRj),$FRintk */
2874   {
2875     FRV_INSN_LDHFU, "ldhfu", "ldhfu", 32,
2876     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2877   },
2878 /* ldfu$pack @($GRi,$GRj),$FRintk */
2879   {
2880     FRV_INSN_LDFU, "ldfu", "ldfu", 32,
2881     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2882   },
2883 /* ldcu$pack @($GRi,$GRj),$CPRk */
2884   {
2885     FRV_INSN_LDCU, "ldcu", "ldcu", 32,
2886     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2887   },
2888 /* nldbfu$pack @($GRi,$GRj),$FRintk */
2889   {
2890     FRV_INSN_NLDBFU, "nldbfu", "nldbfu", 32,
2891     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2892   },
2893 /* nldhfu$pack @($GRi,$GRj),$FRintk */
2894   {
2895     FRV_INSN_NLDHFU, "nldhfu", "nldhfu", 32,
2896     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2897   },
2898 /* nldfu$pack @($GRi,$GRj),$FRintk */
2899   {
2900     FRV_INSN_NLDFU, "nldfu", "nldfu", 32,
2901     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2902   },
2903 /* lddu$pack @($GRi,$GRj),$GRdoublek */
2904   {
2905     FRV_INSN_LDDU, "lddu", "lddu", 32,
2906     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2907   },
2908 /* nlddu$pack @($GRi,$GRj),$GRdoublek */
2909   {
2910     FRV_INSN_NLDDU, "nlddu", "nlddu", 32,
2911     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2912   },
2913 /* lddfu$pack @($GRi,$GRj),$FRdoublek */
2914   {
2915     FRV_INSN_LDDFU, "lddfu", "lddfu", 32,
2916     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2917   },
2918 /* lddcu$pack @($GRi,$GRj),$CPRdoublek */
2919   {
2920     FRV_INSN_LDDCU, "lddcu", "lddcu", 32,
2921     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2922   },
2923 /* nlddfu$pack @($GRi,$GRj),$FRdoublek */
2924   {
2925     FRV_INSN_NLDDFU, "nlddfu", "nlddfu", 32,
2926     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2927   },
2928 /* ldqu$pack @($GRi,$GRj),$GRk */
2929   {
2930     FRV_INSN_LDQU, "ldqu", "ldqu", 32,
2931     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2932   },
2933 /* nldqu$pack @($GRi,$GRj),$GRk */
2934   {
2935     FRV_INSN_NLDQU, "nldqu", "nldqu", 32,
2936     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2937   },
2938 /* ldqfu$pack @($GRi,$GRj),$FRintk */
2939   {
2940     FRV_INSN_LDQFU, "ldqfu", "ldqfu", 32,
2941     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2942   },
2943 /* ldqcu$pack @($GRi,$GRj),$CPRk */
2944   {
2945     FRV_INSN_LDQCU, "ldqcu", "ldqcu", 32,
2946     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2947   },
2948 /* nldqfu$pack @($GRi,$GRj),$FRintk */
2949   {
2950     FRV_INSN_NLDQFU, "nldqfu", "nldqfu", 32,
2951     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2952   },
2953 /* ldsbi$pack @($GRi,$d12),$GRk */
2954   {
2955     FRV_INSN_LDSBI, "ldsbi", "ldsbi", 32,
2956     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2957   },
2958 /* ldshi$pack @($GRi,$d12),$GRk */
2959   {
2960     FRV_INSN_LDSHI, "ldshi", "ldshi", 32,
2961     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2962   },
2963 /* ldi$pack @($GRi,$d12),$GRk */
2964   {
2965     FRV_INSN_LDI, "ldi", "ldi", 32,
2966     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2967   },
2968 /* ldubi$pack @($GRi,$d12),$GRk */
2969   {
2970     FRV_INSN_LDUBI, "ldubi", "ldubi", 32,
2971     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2972   },
2973 /* lduhi$pack @($GRi,$d12),$GRk */
2974   {
2975     FRV_INSN_LDUHI, "lduhi", "lduhi", 32,
2976     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2977   },
2978 /* ldbfi$pack @($GRi,$d12),$FRintk */
2979   {
2980     FRV_INSN_LDBFI, "ldbfi", "ldbfi", 32,
2981     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2982   },
2983 /* ldhfi$pack @($GRi,$d12),$FRintk */
2984   {
2985     FRV_INSN_LDHFI, "ldhfi", "ldhfi", 32,
2986     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2987   },
2988 /* ldfi$pack @($GRi,$d12),$FRintk */
2989   {
2990     FRV_INSN_LDFI, "ldfi", "ldfi", 32,
2991     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2992   },
2993 /* nldsbi$pack @($GRi,$d12),$GRk */
2994   {
2995     FRV_INSN_NLDSBI, "nldsbi", "nldsbi", 32,
2996     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2997   },
2998 /* nldubi$pack @($GRi,$d12),$GRk */
2999   {
3000     FRV_INSN_NLDUBI, "nldubi", "nldubi", 32,
3001     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3002   },
3003 /* nldshi$pack @($GRi,$d12),$GRk */
3004   {
3005     FRV_INSN_NLDSHI, "nldshi", "nldshi", 32,
3006     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3007   },
3008 /* nlduhi$pack @($GRi,$d12),$GRk */
3009   {
3010     FRV_INSN_NLDUHI, "nlduhi", "nlduhi", 32,
3011     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3012   },
3013 /* nldi$pack @($GRi,$d12),$GRk */
3014   {
3015     FRV_INSN_NLDI, "nldi", "nldi", 32,
3016     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3017   },
3018 /* nldbfi$pack @($GRi,$d12),$FRintk */
3019   {
3020     FRV_INSN_NLDBFI, "nldbfi", "nldbfi", 32,
3021     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3022   },
3023 /* nldhfi$pack @($GRi,$d12),$FRintk */
3024   {
3025     FRV_INSN_NLDHFI, "nldhfi", "nldhfi", 32,
3026     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3027   },
3028 /* nldfi$pack @($GRi,$d12),$FRintk */
3029   {
3030     FRV_INSN_NLDFI, "nldfi", "nldfi", 32,
3031     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3032   },
3033 /* lddi$pack @($GRi,$d12),$GRdoublek */
3034   {
3035     FRV_INSN_LDDI, "lddi", "lddi", 32,
3036     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3037   },
3038 /* lddfi$pack @($GRi,$d12),$FRdoublek */
3039   {
3040     FRV_INSN_LDDFI, "lddfi", "lddfi", 32,
3041     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3042   },
3043 /* nlddi$pack @($GRi,$d12),$GRdoublek */
3044   {
3045     FRV_INSN_NLDDI, "nlddi", "nlddi", 32,
3046     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3047   },
3048 /* nlddfi$pack @($GRi,$d12),$FRdoublek */
3049   {
3050     FRV_INSN_NLDDFI, "nlddfi", "nlddfi", 32,
3051     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3052   },
3053 /* ldqi$pack @($GRi,$d12),$GRk */
3054   {
3055     FRV_INSN_LDQI, "ldqi", "ldqi", 32,
3056     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3057   },
3058 /* ldqfi$pack @($GRi,$d12),$FRintk */
3059   {
3060     FRV_INSN_LDQFI, "ldqfi", "ldqfi", 32,
3061     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3062   },
3063 /* nldqi$pack @($GRi,$d12),$GRk */
3064   {
3065     FRV_INSN_NLDQI, "nldqi", "nldqi", 32,
3066     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3067   },
3068 /* nldqfi$pack @($GRi,$d12),$FRintk */
3069   {
3070     FRV_INSN_NLDQFI, "nldqfi", "nldqfi", 32,
3071     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3072   },
3073 /* stb$pack $GRk,@($GRi,$GRj) */
3074   {
3075     FRV_INSN_STB, "stb", "stb", 32,
3076     { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3077   },
3078 /* sth$pack $GRk,@($GRi,$GRj) */
3079   {
3080     FRV_INSN_STH, "sth", "sth", 32,
3081     { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3082   },
3083 /* st$pack $GRk,@($GRi,$GRj) */
3084   {
3085     FRV_INSN_ST, "st", "st", 32,
3086     { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3087   },
3088 /* stbf$pack $FRintk,@($GRi,$GRj) */
3089   {
3090     FRV_INSN_STBF, "stbf", "stbf", 32,
3091     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3092   },
3093 /* sthf$pack $FRintk,@($GRi,$GRj) */
3094   {
3095     FRV_INSN_STHF, "sthf", "sthf", 32,
3096     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3097   },
3098 /* stf$pack $FRintk,@($GRi,$GRj) */
3099   {
3100     FRV_INSN_STF, "stf", "stf", 32,
3101     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3102   },
3103 /* stc$pack $CPRk,@($GRi,$GRj) */
3104   {
3105     FRV_INSN_STC, "stc", "stc", 32,
3106     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3107   },
3108 /* rstb$pack $GRk,@($GRi,$GRj) */
3109   {
3110     FRV_INSN_RSTB, "rstb", "rstb", 32,
3111     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3112   },
3113 /* rsth$pack $GRk,@($GRi,$GRj) */
3114   {
3115     FRV_INSN_RSTH, "rsth", "rsth", 32,
3116     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3117   },
3118 /* rst$pack $GRk,@($GRi,$GRj) */
3119   {
3120     FRV_INSN_RST, "rst", "rst", 32,
3121     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3122   },
3123 /* rstbf$pack $FRintk,@($GRi,$GRj) */
3124   {
3125     FRV_INSN_RSTBF, "rstbf", "rstbf", 32,
3126     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3127   },
3128 /* rsthf$pack $FRintk,@($GRi,$GRj) */
3129   {
3130     FRV_INSN_RSTHF, "rsthf", "rsthf", 32,
3131     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3132   },
3133 /* rstf$pack $FRintk,@($GRi,$GRj) */
3134   {
3135     FRV_INSN_RSTF, "rstf", "rstf", 32,
3136     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3137   },
3138 /* std$pack $GRk,@($GRi,$GRj) */
3139   {
3140     FRV_INSN_STD, "std", "std", 32,
3141     { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3142   },
3143 /* stdf$pack $FRk,@($GRi,$GRj) */
3144   {
3145     FRV_INSN_STDF, "stdf", "stdf", 32,
3146     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3147   },
3148 /* stdc$pack $CPRk,@($GRi,$GRj) */
3149   {
3150     FRV_INSN_STDC, "stdc", "stdc", 32,
3151     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3152   },
3153 /* rstd$pack $GRk,@($GRi,$GRj) */
3154   {
3155     FRV_INSN_RSTD, "rstd", "rstd", 32,
3156     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3157   },
3158 /* rstdf$pack $FRk,@($GRi,$GRj) */
3159   {
3160     FRV_INSN_RSTDF, "rstdf", "rstdf", 32,
3161     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3162   },
3163 /* stq$pack $GRk,@($GRi,$GRj) */
3164   {
3165     FRV_INSN_STQ, "stq", "stq", 32,
3166     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3167   },
3168 /* stqf$pack $FRintk,@($GRi,$GRj) */
3169   {
3170     FRV_INSN_STQF, "stqf", "stqf", 32,
3171     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3172   },
3173 /* stqc$pack $CPRk,@($GRi,$GRj) */
3174   {
3175     FRV_INSN_STQC, "stqc", "stqc", 32,
3176     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3177   },
3178 /* rstq$pack $GRk,@($GRi,$GRj) */
3179   {
3180     FRV_INSN_RSTQ, "rstq", "rstq", 32,
3181     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3182   },
3183 /* rstqf$pack $FRintk,@($GRi,$GRj) */
3184   {
3185     FRV_INSN_RSTQF, "rstqf", "rstqf", 32,
3186     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3187   },
3188 /* stbu$pack $GRk,@($GRi,$GRj) */
3189   {
3190     FRV_INSN_STBU, "stbu", "stbu", 32,
3191     { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3192   },
3193 /* sthu$pack $GRk,@($GRi,$GRj) */
3194   {
3195     FRV_INSN_STHU, "sthu", "sthu", 32,
3196     { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3197   },
3198 /* stu$pack $GRk,@($GRi,$GRj) */
3199   {
3200     FRV_INSN_STU, "stu", "stu", 32,
3201     { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3202   },
3203 /* stbfu$pack $FRintk,@($GRi,$GRj) */
3204   {
3205     FRV_INSN_STBFU, "stbfu", "stbfu", 32,
3206     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3207   },
3208 /* sthfu$pack $FRintk,@($GRi,$GRj) */
3209   {
3210     FRV_INSN_STHFU, "sthfu", "sthfu", 32,
3211     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3212   },
3213 /* stfu$pack $FRintk,@($GRi,$GRj) */
3214   {
3215     FRV_INSN_STFU, "stfu", "stfu", 32,
3216     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3217   },
3218 /* stcu$pack $CPRk,@($GRi,$GRj) */
3219   {
3220     FRV_INSN_STCU, "stcu", "stcu", 32,
3221     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3222   },
3223 /* stdu$pack $GRk,@($GRi,$GRj) */
3224   {
3225     FRV_INSN_STDU, "stdu", "stdu", 32,
3226     { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3227   },
3228 /* stdfu$pack $FRk,@($GRi,$GRj) */
3229   {
3230     FRV_INSN_STDFU, "stdfu", "stdfu", 32,
3231     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3232   },
3233 /* stdcu$pack $CPRk,@($GRi,$GRj) */
3234   {
3235     FRV_INSN_STDCU, "stdcu", "stdcu", 32,
3236     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3237   },
3238 /* stqu$pack $GRk,@($GRi,$GRj) */
3239   {
3240     FRV_INSN_STQU, "stqu", "stqu", 32,
3241     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3242   },
3243 /* stqfu$pack $FRintk,@($GRi,$GRj) */
3244   {
3245     FRV_INSN_STQFU, "stqfu", "stqfu", 32,
3246     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3247   },
3248 /* stqcu$pack $CPRk,@($GRi,$GRj) */
3249   {
3250     FRV_INSN_STQCU, "stqcu", "stqcu", 32,
3251     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3252   },
3253 /* cldsb$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3254   {
3255     FRV_INSN_CLDSB, "cldsb", "cldsb", 32,
3256     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3257   },
3258 /* cldub$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3259   {
3260     FRV_INSN_CLDUB, "cldub", "cldub", 32,
3261     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3262   },
3263 /* cldsh$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3264   {
3265     FRV_INSN_CLDSH, "cldsh", "cldsh", 32,
3266     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3267   },
3268 /* clduh$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3269   {
3270     FRV_INSN_CLDUH, "clduh", "clduh", 32,
3271     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3272   },
3273 /* cld$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3274   {
3275     FRV_INSN_CLD, "cld", "cld", 32,
3276     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3277   },
3278 /* cldbf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3279   {
3280     FRV_INSN_CLDBF, "cldbf", "cldbf", 32,
3281     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3282   },
3283 /* cldhf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3284   {
3285     FRV_INSN_CLDHF, "cldhf", "cldhf", 32,
3286     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3287   },
3288 /* cldf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3289   {
3290     FRV_INSN_CLDF, "cldf", "cldf", 32,
3291     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3292   },
3293 /* cldd$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */
3294   {
3295     FRV_INSN_CLDD, "cldd", "cldd", 32,
3296     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3297   },
3298 /* clddf$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */
3299   {
3300     FRV_INSN_CLDDF, "clddf", "clddf", 32,
3301     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3302   },
3303 /* cldq$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3304   {
3305     FRV_INSN_CLDQ, "cldq", "cldq", 32,
3306     { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3307   },
3308 /* cldsbu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3309   {
3310     FRV_INSN_CLDSBU, "cldsbu", "cldsbu", 32,
3311     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3312   },
3313 /* cldubu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3314   {
3315     FRV_INSN_CLDUBU, "cldubu", "cldubu", 32,
3316     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3317   },
3318 /* cldshu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3319   {
3320     FRV_INSN_CLDSHU, "cldshu", "cldshu", 32,
3321     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3322   },
3323 /* clduhu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3324   {
3325     FRV_INSN_CLDUHU, "clduhu", "clduhu", 32,
3326     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3327   },
3328 /* cldu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3329   {
3330     FRV_INSN_CLDU, "cldu", "cldu", 32,
3331     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3332   },
3333 /* cldbfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3334   {
3335     FRV_INSN_CLDBFU, "cldbfu", "cldbfu", 32,
3336     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3337   },
3338 /* cldhfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3339   {
3340     FRV_INSN_CLDHFU, "cldhfu", "cldhfu", 32,
3341     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3342   },
3343 /* cldfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3344   {
3345     FRV_INSN_CLDFU, "cldfu", "cldfu", 32,
3346     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3347   },
3348 /* clddu$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */
3349   {
3350     FRV_INSN_CLDDU, "clddu", "clddu", 32,
3351     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3352   },
3353 /* clddfu$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */
3354   {
3355     FRV_INSN_CLDDFU, "clddfu", "clddfu", 32,
3356     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3357   },
3358 /* cldqu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3359   {
3360     FRV_INSN_CLDQU, "cldqu", "cldqu", 32,
3361     { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3362   },
3363 /* cstb$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3364   {
3365     FRV_INSN_CSTB, "cstb", "cstb", 32,
3366     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3367   },
3368 /* csth$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3369   {
3370     FRV_INSN_CSTH, "csth", "csth", 32,
3371     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3372   },
3373 /* cst$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3374   {
3375     FRV_INSN_CST, "cst", "cst", 32,
3376     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3377   },
3378 /* cstbf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3379   {
3380     FRV_INSN_CSTBF, "cstbf", "cstbf", 32,
3381     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3382   },
3383 /* csthf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3384   {
3385     FRV_INSN_CSTHF, "csthf", "csthf", 32,
3386     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3387   },
3388 /* cstf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3389   {
3390     FRV_INSN_CSTF, "cstf", "cstf", 32,
3391     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3392   },
3393 /* cstd$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3394   {
3395     FRV_INSN_CSTD, "cstd", "cstd", 32,
3396     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3397   },
3398 /* cstdf$pack $FRk,@($GRi,$GRj),$CCi,$cond */
3399   {
3400     FRV_INSN_CSTDF, "cstdf", "cstdf", 32,
3401     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3402   },
3403 /* cstq$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3404   {
3405     FRV_INSN_CSTQ, "cstq", "cstq", 32,
3406     { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3407   },
3408 /* cstbu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3409   {
3410     FRV_INSN_CSTBU, "cstbu", "cstbu", 32,
3411     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3412   },
3413 /* csthu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3414   {
3415     FRV_INSN_CSTHU, "csthu", "csthu", 32,
3416     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3417   },
3418 /* cstu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3419   {
3420     FRV_INSN_CSTU, "cstu", "cstu", 32,
3421     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3422   },
3423 /* cstbfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3424   {
3425     FRV_INSN_CSTBFU, "cstbfu", "cstbfu", 32,
3426     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3427   },
3428 /* csthfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3429   {
3430     FRV_INSN_CSTHFU, "csthfu", "csthfu", 32,
3431     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3432   },
3433 /* cstfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3434   {
3435     FRV_INSN_CSTFU, "cstfu", "cstfu", 32,
3436     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3437   },
3438 /* cstdu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3439   {
3440     FRV_INSN_CSTDU, "cstdu", "cstdu", 32,
3441     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3442   },
3443 /* cstdfu$pack $FRk,@($GRi,$GRj),$CCi,$cond */
3444   {
3445     FRV_INSN_CSTDFU, "cstdfu", "cstdfu", 32,
3446     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3447   },
3448 /* stbi$pack $GRk,@($GRi,$d12) */
3449   {
3450     FRV_INSN_STBI, "stbi", "stbi", 32,
3451     { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3452   },
3453 /* sthi$pack $GRk,@($GRi,$d12) */
3454   {
3455     FRV_INSN_STHI, "sthi", "sthi", 32,
3456     { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3457   },
3458 /* sti$pack $GRk,@($GRi,$d12) */
3459   {
3460     FRV_INSN_STI, "sti", "sti", 32,
3461     { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3462   },
3463 /* stbfi$pack $FRintk,@($GRi,$d12) */
3464   {
3465     FRV_INSN_STBFI, "stbfi", "stbfi", 32,
3466     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3467   },
3468 /* sthfi$pack $FRintk,@($GRi,$d12) */
3469   {
3470     FRV_INSN_STHFI, "sthfi", "sthfi", 32,
3471     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3472   },
3473 /* stfi$pack $FRintk,@($GRi,$d12) */
3474   {
3475     FRV_INSN_STFI, "stfi", "stfi", 32,
3476     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3477   },
3478 /* stdi$pack $GRk,@($GRi,$d12) */
3479   {
3480     FRV_INSN_STDI, "stdi", "stdi", 32,
3481     { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3482   },
3483 /* stdfi$pack $FRk,@($GRi,$d12) */
3484   {
3485     FRV_INSN_STDFI, "stdfi", "stdfi", 32,
3486     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3487   },
3488 /* stqi$pack $GRk,@($GRi,$d12) */
3489   {
3490     FRV_INSN_STQI, "stqi", "stqi", 32,
3491     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3492   },
3493 /* stqfi$pack $FRintk,@($GRi,$d12) */
3494   {
3495     FRV_INSN_STQFI, "stqfi", "stqfi", 32,
3496     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3497   },
3498 /* swap$pack @($GRi,$GRj),$GRk */
3499   {
3500     FRV_INSN_SWAP, "swap", "swap", 32,
3501     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
3502   },
3503 /* swapi$pack @($GRi,$d12),$GRk */
3504   {
3505     FRV_INSN_SWAPI, "swapi", "swapi", 32,
3506     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
3507   },
3508 /* cswap$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3509   {
3510     FRV_INSN_CSWAP, "cswap", "cswap", 32,
3511     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
3512   },
3513 /* movgf$pack $GRj,$FRintk */
3514   {
3515     FRV_INSN_MOVGF, "movgf", "movgf", 32,
3516     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3517   },
3518 /* movfg$pack $FRintk,$GRj */
3519   {
3520     FRV_INSN_MOVFG, "movfg", "movfg", 32,
3521     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3522   },
3523 /* movgfd$pack $GRj,$FRintk */
3524   {
3525     FRV_INSN_MOVGFD, "movgfd", "movgfd", 32,
3526     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3527   },
3528 /* movfgd$pack $FRintk,$GRj */
3529   {
3530     FRV_INSN_MOVFGD, "movfgd", "movfgd", 32,
3531     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3532   },
3533 /* movgfq$pack $GRj,$FRintk */
3534   {
3535     FRV_INSN_MOVGFQ, "movgfq", "movgfq", 32,
3536     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_4 } }
3537   },
3538 /* movfgq$pack $FRintk,$GRj */
3539   {
3540     FRV_INSN_MOVFGQ, "movfgq", "movfgq", 32,
3541     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_4 } }
3542   },
3543 /* cmovgf$pack $GRj,$FRintk,$CCi,$cond */
3544   {
3545     FRV_INSN_CMOVGF, "cmovgf", "cmovgf", 32,
3546     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3547   },
3548 /* cmovfg$pack $FRintk,$GRj,$CCi,$cond */
3549   {
3550     FRV_INSN_CMOVFG, "cmovfg", "cmovfg", 32,
3551     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3552   },
3553 /* cmovgfd$pack $GRj,$FRintk,$CCi,$cond */
3554   {
3555     FRV_INSN_CMOVGFD, "cmovgfd", "cmovgfd", 32,
3556     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3557   },
3558 /* cmovfgd$pack $FRintk,$GRj,$CCi,$cond */
3559   {
3560     FRV_INSN_CMOVFGD, "cmovfgd", "cmovfgd", 32,
3561     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3562   },
3563 /* movgs$pack $GRj,$spr */
3564   {
3565     FRV_INSN_MOVGS, "movgs", "movgs", 32,
3566     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
3567   },
3568 /* movsg$pack $spr,$GRj */
3569   {
3570     FRV_INSN_MOVSG, "movsg", "movsg", 32,
3571     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
3572   },
3573 /* bra$pack $hint_taken$label16 */
3574   {
3575     FRV_INSN_BRA, "bra", "bra", 32,
3576     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3577   },
3578 /* bno$pack$hint_not_taken */
3579   {
3580     FRV_INSN_BNO, "bno", "bno", 32,
3581     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3582   },
3583 /* beq$pack $ICCi_2,$hint,$label16 */
3584   {
3585     FRV_INSN_BEQ, "beq", "beq", 32,
3586     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3587   },
3588 /* bne$pack $ICCi_2,$hint,$label16 */
3589   {
3590     FRV_INSN_BNE, "bne", "bne", 32,
3591     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3592   },
3593 /* ble$pack $ICCi_2,$hint,$label16 */
3594   {
3595     FRV_INSN_BLE, "ble", "ble", 32,
3596     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3597   },
3598 /* bgt$pack $ICCi_2,$hint,$label16 */
3599   {
3600     FRV_INSN_BGT, "bgt", "bgt", 32,
3601     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3602   },
3603 /* blt$pack $ICCi_2,$hint,$label16 */
3604   {
3605     FRV_INSN_BLT, "blt", "blt", 32,
3606     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3607   },
3608 /* bge$pack $ICCi_2,$hint,$label16 */
3609   {
3610     FRV_INSN_BGE, "bge", "bge", 32,
3611     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3612   },
3613 /* bls$pack $ICCi_2,$hint,$label16 */
3614   {
3615     FRV_INSN_BLS, "bls", "bls", 32,
3616     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3617   },
3618 /* bhi$pack $ICCi_2,$hint,$label16 */
3619   {
3620     FRV_INSN_BHI, "bhi", "bhi", 32,
3621     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3622   },
3623 /* bc$pack $ICCi_2,$hint,$label16 */
3624   {
3625     FRV_INSN_BC, "bc", "bc", 32,
3626     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3627   },
3628 /* bnc$pack $ICCi_2,$hint,$label16 */
3629   {
3630     FRV_INSN_BNC, "bnc", "bnc", 32,
3631     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3632   },
3633 /* bn$pack $ICCi_2,$hint,$label16 */
3634   {
3635     FRV_INSN_BN, "bn", "bn", 32,
3636     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3637   },
3638 /* bp$pack $ICCi_2,$hint,$label16 */
3639   {
3640     FRV_INSN_BP, "bp", "bp", 32,
3641     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3642   },
3643 /* bv$pack $ICCi_2,$hint,$label16 */
3644   {
3645     FRV_INSN_BV, "bv", "bv", 32,
3646     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3647   },
3648 /* bnv$pack $ICCi_2,$hint,$label16 */
3649   {
3650     FRV_INSN_BNV, "bnv", "bnv", 32,
3651     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3652   },
3653 /* fbra$pack $hint_taken$label16 */
3654   {
3655     FRV_INSN_FBRA, "fbra", "fbra", 32,
3656     { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3657   },
3658 /* fbno$pack$hint_not_taken */
3659   {
3660     FRV_INSN_FBNO, "fbno", "fbno", 32,
3661     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3662   },
3663 /* fbne$pack $FCCi_2,$hint,$label16 */
3664   {
3665     FRV_INSN_FBNE, "fbne", "fbne", 32,
3666     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3667   },
3668 /* fbeq$pack $FCCi_2,$hint,$label16 */
3669   {
3670     FRV_INSN_FBEQ, "fbeq", "fbeq", 32,
3671     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3672   },
3673 /* fblg$pack $FCCi_2,$hint,$label16 */
3674   {
3675     FRV_INSN_FBLG, "fblg", "fblg", 32,
3676     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3677   },
3678 /* fbue$pack $FCCi_2,$hint,$label16 */
3679   {
3680     FRV_INSN_FBUE, "fbue", "fbue", 32,
3681     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3682   },
3683 /* fbul$pack $FCCi_2,$hint,$label16 */
3684   {
3685     FRV_INSN_FBUL, "fbul", "fbul", 32,
3686     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3687   },
3688 /* fbge$pack $FCCi_2,$hint,$label16 */
3689   {
3690     FRV_INSN_FBGE, "fbge", "fbge", 32,
3691     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3692   },
3693 /* fblt$pack $FCCi_2,$hint,$label16 */
3694   {
3695     FRV_INSN_FBLT, "fblt", "fblt", 32,
3696     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3697   },
3698 /* fbuge$pack $FCCi_2,$hint,$label16 */
3699   {
3700     FRV_INSN_FBUGE, "fbuge", "fbuge", 32,
3701     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3702   },
3703 /* fbug$pack $FCCi_2,$hint,$label16 */
3704   {
3705     FRV_INSN_FBUG, "fbug", "fbug", 32,
3706     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3707   },
3708 /* fble$pack $FCCi_2,$hint,$label16 */
3709   {
3710     FRV_INSN_FBLE, "fble", "fble", 32,
3711     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3712   },
3713 /* fbgt$pack $FCCi_2,$hint,$label16 */
3714   {
3715     FRV_INSN_FBGT, "fbgt", "fbgt", 32,
3716     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3717   },
3718 /* fbule$pack $FCCi_2,$hint,$label16 */
3719   {
3720     FRV_INSN_FBULE, "fbule", "fbule", 32,
3721     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3722   },
3723 /* fbu$pack $FCCi_2,$hint,$label16 */
3724   {
3725     FRV_INSN_FBU, "fbu", "fbu", 32,
3726     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3727   },
3728 /* fbo$pack $FCCi_2,$hint,$label16 */
3729   {
3730     FRV_INSN_FBO, "fbo", "fbo", 32,
3731     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3732   },
3733 /* bctrlr$pack $ccond,$hint */
3734   {
3735     FRV_INSN_BCTRLR, "bctrlr", "bctrlr", 32,
3736     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3737   },
3738 /* bralr$pack$hint_taken */
3739   {
3740     FRV_INSN_BRALR, "bralr", "bralr", 32,
3741     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3742   },
3743 /* bnolr$pack$hint_not_taken */
3744   {
3745     FRV_INSN_BNOLR, "bnolr", "bnolr", 32,
3746     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3747   },
3748 /* beqlr$pack $ICCi_2,$hint */
3749   {
3750     FRV_INSN_BEQLR, "beqlr", "beqlr", 32,
3751     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3752   },
3753 /* bnelr$pack $ICCi_2,$hint */
3754   {
3755     FRV_INSN_BNELR, "bnelr", "bnelr", 32,
3756     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3757   },
3758 /* blelr$pack $ICCi_2,$hint */
3759   {
3760     FRV_INSN_BLELR, "blelr", "blelr", 32,
3761     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3762   },
3763 /* bgtlr$pack $ICCi_2,$hint */
3764   {
3765     FRV_INSN_BGTLR, "bgtlr", "bgtlr", 32,
3766     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3767   },
3768 /* bltlr$pack $ICCi_2,$hint */
3769   {
3770     FRV_INSN_BLTLR, "bltlr", "bltlr", 32,
3771     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3772   },
3773 /* bgelr$pack $ICCi_2,$hint */
3774   {
3775     FRV_INSN_BGELR, "bgelr", "bgelr", 32,
3776     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3777   },
3778 /* blslr$pack $ICCi_2,$hint */
3779   {
3780     FRV_INSN_BLSLR, "blslr", "blslr", 32,
3781     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3782   },
3783 /* bhilr$pack $ICCi_2,$hint */
3784   {
3785     FRV_INSN_BHILR, "bhilr", "bhilr", 32,
3786     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3787   },
3788 /* bclr$pack $ICCi_2,$hint */
3789   {
3790     FRV_INSN_BCLR, "bclr", "bclr", 32,
3791     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3792   },
3793 /* bnclr$pack $ICCi_2,$hint */
3794   {
3795     FRV_INSN_BNCLR, "bnclr", "bnclr", 32,
3796     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3797   },
3798 /* bnlr$pack $ICCi_2,$hint */
3799   {
3800     FRV_INSN_BNLR, "bnlr", "bnlr", 32,
3801     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3802   },
3803 /* bplr$pack $ICCi_2,$hint */
3804   {
3805     FRV_INSN_BPLR, "bplr", "bplr", 32,
3806     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3807   },
3808 /* bvlr$pack $ICCi_2,$hint */
3809   {
3810     FRV_INSN_BVLR, "bvlr", "bvlr", 32,
3811     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3812   },
3813 /* bnvlr$pack $ICCi_2,$hint */
3814   {
3815     FRV_INSN_BNVLR, "bnvlr", "bnvlr", 32,
3816     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3817   },
3818 /* fbralr$pack$hint_taken */
3819   {
3820     FRV_INSN_FBRALR, "fbralr", "fbralr", 32,
3821     { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3822   },
3823 /* fbnolr$pack$hint_not_taken */
3824   {
3825     FRV_INSN_FBNOLR, "fbnolr", "fbnolr", 32,
3826     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3827   },
3828 /* fbeqlr$pack $FCCi_2,$hint */
3829   {
3830     FRV_INSN_FBEQLR, "fbeqlr", "fbeqlr", 32,
3831     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3832   },
3833 /* fbnelr$pack $FCCi_2,$hint */
3834   {
3835     FRV_INSN_FBNELR, "fbnelr", "fbnelr", 32,
3836     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3837   },
3838 /* fblglr$pack $FCCi_2,$hint */
3839   {
3840     FRV_INSN_FBLGLR, "fblglr", "fblglr", 32,
3841     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3842   },
3843 /* fbuelr$pack $FCCi_2,$hint */
3844   {
3845     FRV_INSN_FBUELR, "fbuelr", "fbuelr", 32,
3846     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3847   },
3848 /* fbullr$pack $FCCi_2,$hint */
3849   {
3850     FRV_INSN_FBULLR, "fbullr", "fbullr", 32,
3851     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3852   },
3853 /* fbgelr$pack $FCCi_2,$hint */
3854   {
3855     FRV_INSN_FBGELR, "fbgelr", "fbgelr", 32,
3856     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3857   },
3858 /* fbltlr$pack $FCCi_2,$hint */
3859   {
3860     FRV_INSN_FBLTLR, "fbltlr", "fbltlr", 32,
3861     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3862   },
3863 /* fbugelr$pack $FCCi_2,$hint */
3864   {
3865     FRV_INSN_FBUGELR, "fbugelr", "fbugelr", 32,
3866     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3867   },
3868 /* fbuglr$pack $FCCi_2,$hint */
3869   {
3870     FRV_INSN_FBUGLR, "fbuglr", "fbuglr", 32,
3871     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3872   },
3873 /* fblelr$pack $FCCi_2,$hint */
3874   {
3875     FRV_INSN_FBLELR, "fblelr", "fblelr", 32,
3876     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3877   },
3878 /* fbgtlr$pack $FCCi_2,$hint */
3879   {
3880     FRV_INSN_FBGTLR, "fbgtlr", "fbgtlr", 32,
3881     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3882   },
3883 /* fbulelr$pack $FCCi_2,$hint */
3884   {
3885     FRV_INSN_FBULELR, "fbulelr", "fbulelr", 32,
3886     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3887   },
3888 /* fbulr$pack $FCCi_2,$hint */
3889   {
3890     FRV_INSN_FBULR, "fbulr", "fbulr", 32,
3891     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3892   },
3893 /* fbolr$pack $FCCi_2,$hint */
3894   {
3895     FRV_INSN_FBOLR, "fbolr", "fbolr", 32,
3896     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3897   },
3898 /* bcralr$pack $ccond$hint_taken */
3899   {
3900     FRV_INSN_BCRALR, "bcralr", "bcralr", 32,
3901     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3902   },
3903 /* bcnolr$pack$hint_not_taken */
3904   {
3905     FRV_INSN_BCNOLR, "bcnolr", "bcnolr", 32,
3906     { 0, { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3907   },
3908 /* bceqlr$pack $ICCi_2,$ccond,$hint */
3909   {
3910     FRV_INSN_BCEQLR, "bceqlr", "bceqlr", 32,
3911     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3912   },
3913 /* bcnelr$pack $ICCi_2,$ccond,$hint */
3914   {
3915     FRV_INSN_BCNELR, "bcnelr", "bcnelr", 32,
3916     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3917   },
3918 /* bclelr$pack $ICCi_2,$ccond,$hint */
3919   {
3920     FRV_INSN_BCLELR, "bclelr", "bclelr", 32,
3921     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3922   },
3923 /* bcgtlr$pack $ICCi_2,$ccond,$hint */
3924   {
3925     FRV_INSN_BCGTLR, "bcgtlr", "bcgtlr", 32,
3926     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3927   },
3928 /* bcltlr$pack $ICCi_2,$ccond,$hint */
3929   {
3930     FRV_INSN_BCLTLR, "bcltlr", "bcltlr", 32,
3931     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3932   },
3933 /* bcgelr$pack $ICCi_2,$ccond,$hint */
3934   {
3935     FRV_INSN_BCGELR, "bcgelr", "bcgelr", 32,
3936     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3937   },
3938 /* bclslr$pack $ICCi_2,$ccond,$hint */
3939   {
3940     FRV_INSN_BCLSLR, "bclslr", "bclslr", 32,
3941     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3942   },
3943 /* bchilr$pack $ICCi_2,$ccond,$hint */
3944   {
3945     FRV_INSN_BCHILR, "bchilr", "bchilr", 32,
3946     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3947   },
3948 /* bcclr$pack $ICCi_2,$ccond,$hint */
3949   {
3950     FRV_INSN_BCCLR, "bcclr", "bcclr", 32,
3951     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3952   },
3953 /* bcnclr$pack $ICCi_2,$ccond,$hint */
3954   {
3955     FRV_INSN_BCNCLR, "bcnclr", "bcnclr", 32,
3956     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3957   },
3958 /* bcnlr$pack $ICCi_2,$ccond,$hint */
3959   {
3960     FRV_INSN_BCNLR, "bcnlr", "bcnlr", 32,
3961     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3962   },
3963 /* bcplr$pack $ICCi_2,$ccond,$hint */
3964   {
3965     FRV_INSN_BCPLR, "bcplr", "bcplr", 32,
3966     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3967   },
3968 /* bcvlr$pack $ICCi_2,$ccond,$hint */
3969   {
3970     FRV_INSN_BCVLR, "bcvlr", "bcvlr", 32,
3971     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3972   },
3973 /* bcnvlr$pack $ICCi_2,$ccond,$hint */
3974   {
3975     FRV_INSN_BCNVLR, "bcnvlr", "bcnvlr", 32,
3976     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3977   },
3978 /* fcbralr$pack $ccond$hint_taken */
3979   {
3980     FRV_INSN_FCBRALR, "fcbralr", "fcbralr", 32,
3981     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3982   },
3983 /* fcbnolr$pack$hint_not_taken */
3984   {
3985     FRV_INSN_FCBNOLR, "fcbnolr", "fcbnolr", 32,
3986     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3987   },
3988 /* fcbeqlr$pack $FCCi_2,$ccond,$hint */
3989   {
3990     FRV_INSN_FCBEQLR, "fcbeqlr", "fcbeqlr", 32,
3991     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3992   },
3993 /* fcbnelr$pack $FCCi_2,$ccond,$hint */
3994   {
3995     FRV_INSN_FCBNELR, "fcbnelr", "fcbnelr", 32,
3996     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3997   },
3998 /* fcblglr$pack $FCCi_2,$ccond,$hint */
3999   {
4000     FRV_INSN_FCBLGLR, "fcblglr", "fcblglr", 32,
4001     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4002   },
4003 /* fcbuelr$pack $FCCi_2,$ccond,$hint */
4004   {
4005     FRV_INSN_FCBUELR, "fcbuelr", "fcbuelr", 32,
4006     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4007   },
4008 /* fcbullr$pack $FCCi_2,$ccond,$hint */
4009   {
4010     FRV_INSN_FCBULLR, "fcbullr", "fcbullr", 32,
4011     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4012   },
4013 /* fcbgelr$pack $FCCi_2,$ccond,$hint */
4014   {
4015     FRV_INSN_FCBGELR, "fcbgelr", "fcbgelr", 32,
4016     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4017   },
4018 /* fcbltlr$pack $FCCi_2,$ccond,$hint */
4019   {
4020     FRV_INSN_FCBLTLR, "fcbltlr", "fcbltlr", 32,
4021     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4022   },
4023 /* fcbugelr$pack $FCCi_2,$ccond,$hint */
4024   {
4025     FRV_INSN_FCBUGELR, "fcbugelr", "fcbugelr", 32,
4026     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4027   },
4028 /* fcbuglr$pack $FCCi_2,$ccond,$hint */
4029   {
4030     FRV_INSN_FCBUGLR, "fcbuglr", "fcbuglr", 32,
4031     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4032   },
4033 /* fcblelr$pack $FCCi_2,$ccond,$hint */
4034   {
4035     FRV_INSN_FCBLELR, "fcblelr", "fcblelr", 32,
4036     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4037   },
4038 /* fcbgtlr$pack $FCCi_2,$ccond,$hint */
4039   {
4040     FRV_INSN_FCBGTLR, "fcbgtlr", "fcbgtlr", 32,
4041     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4042   },
4043 /* fcbulelr$pack $FCCi_2,$ccond,$hint */
4044   {
4045     FRV_INSN_FCBULELR, "fcbulelr", "fcbulelr", 32,
4046     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4047   },
4048 /* fcbulr$pack $FCCi_2,$ccond,$hint */
4049   {
4050     FRV_INSN_FCBULR, "fcbulr", "fcbulr", 32,
4051     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4052   },
4053 /* fcbolr$pack $FCCi_2,$ccond,$hint */
4054   {
4055     FRV_INSN_FCBOLR, "fcbolr", "fcbolr", 32,
4056     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4057   },
4058 /* jmpl$pack @($GRi,$GRj) */
4059   {
4060     FRV_INSN_JMPL, "jmpl", "jmpl", 32,
4061     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
4062   },
4063 /* calll$pack @($GRi,$GRj) */
4064   {
4065     FRV_INSN_CALLL, "calll", "calll", 32,
4066     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
4067   },
4068 /* jmpil$pack @($GRi,$s12) */
4069   {
4070     FRV_INSN_JMPIL, "jmpil", "jmpil", 32,
4071     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
4072   },
4073 /* callil$pack @($GRi,$s12) */
4074   {
4075     FRV_INSN_CALLIL, "callil", "callil", 32,
4076     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
4077   },
4078 /* call$pack $label24 */
4079   {
4080     FRV_INSN_CALL, "call", "call", 32,
4081     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_4, FR500_MAJOR_B_4 } }
4082   },
4083 /* rett$pack $debug */
4084   {
4085     FRV_INSN_RETT, "rett", "rett", 32,
4086     { 0|A(PRIVILEGED)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4087   },
4088 /* rei$pack $eir */
4089   {
4090     FRV_INSN_REI, "rei", "rei", 32,
4091     { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_1 } }
4092   },
4093 /* tra$pack $GRi,$GRj */
4094   {
4095     FRV_INSN_TRA, "tra", "tra", 32,
4096     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4097   },
4098 /* tno$pack */
4099   {
4100     FRV_INSN_TNO, "tno", "tno", 32,
4101     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4102   },
4103 /* teq$pack $ICCi_2,$GRi,$GRj */
4104   {
4105     FRV_INSN_TEQ, "teq", "teq", 32,
4106     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4107   },
4108 /* tne$pack $ICCi_2,$GRi,$GRj */
4109   {
4110     FRV_INSN_TNE, "tne", "tne", 32,
4111     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4112   },
4113 /* tle$pack $ICCi_2,$GRi,$GRj */
4114   {
4115     FRV_INSN_TLE, "tle", "tle", 32,
4116     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4117   },
4118 /* tgt$pack $ICCi_2,$GRi,$GRj */
4119   {
4120     FRV_INSN_TGT, "tgt", "tgt", 32,
4121     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4122   },
4123 /* tlt$pack $ICCi_2,$GRi,$GRj */
4124   {
4125     FRV_INSN_TLT, "tlt", "tlt", 32,
4126     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4127   },
4128 /* tge$pack $ICCi_2,$GRi,$GRj */
4129   {
4130     FRV_INSN_TGE, "tge", "tge", 32,
4131     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4132   },
4133 /* tls$pack $ICCi_2,$GRi,$GRj */
4134   {
4135     FRV_INSN_TLS, "tls", "tls", 32,
4136     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4137   },
4138 /* thi$pack $ICCi_2,$GRi,$GRj */
4139   {
4140     FRV_INSN_THI, "thi", "thi", 32,
4141     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4142   },
4143 /* tc$pack $ICCi_2,$GRi,$GRj */
4144   {
4145     FRV_INSN_TC, "tc", "tc", 32,
4146     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4147   },
4148 /* tnc$pack $ICCi_2,$GRi,$GRj */
4149   {
4150     FRV_INSN_TNC, "tnc", "tnc", 32,
4151     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4152   },
4153 /* tn$pack $ICCi_2,$GRi,$GRj */
4154   {
4155     FRV_INSN_TN, "tn", "tn", 32,
4156     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4157   },
4158 /* tp$pack $ICCi_2,$GRi,$GRj */
4159   {
4160     FRV_INSN_TP, "tp", "tp", 32,
4161     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4162   },
4163 /* tv$pack $ICCi_2,$GRi,$GRj */
4164   {
4165     FRV_INSN_TV, "tv", "tv", 32,
4166     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4167   },
4168 /* tnv$pack $ICCi_2,$GRi,$GRj */
4169   {
4170     FRV_INSN_TNV, "tnv", "tnv", 32,
4171     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4172   },
4173 /* ftra$pack $GRi,$GRj */
4174   {
4175     FRV_INSN_FTRA, "ftra", "ftra", 32,
4176     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4177   },
4178 /* ftno$pack */
4179   {
4180     FRV_INSN_FTNO, "ftno", "ftno", 32,
4181     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4182   },
4183 /* ftne$pack $FCCi_2,$GRi,$GRj */
4184   {
4185     FRV_INSN_FTNE, "ftne", "ftne", 32,
4186     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4187   },
4188 /* fteq$pack $FCCi_2,$GRi,$GRj */
4189   {
4190     FRV_INSN_FTEQ, "fteq", "fteq", 32,
4191     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4192   },
4193 /* ftlg$pack $FCCi_2,$GRi,$GRj */
4194   {
4195     FRV_INSN_FTLG, "ftlg", "ftlg", 32,
4196     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4197   },
4198 /* ftue$pack $FCCi_2,$GRi,$GRj */
4199   {
4200     FRV_INSN_FTUE, "ftue", "ftue", 32,
4201     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4202   },
4203 /* ftul$pack $FCCi_2,$GRi,$GRj */
4204   {
4205     FRV_INSN_FTUL, "ftul", "ftul", 32,
4206     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4207   },
4208 /* ftge$pack $FCCi_2,$GRi,$GRj */
4209   {
4210     FRV_INSN_FTGE, "ftge", "ftge", 32,
4211     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4212   },
4213 /* ftlt$pack $FCCi_2,$GRi,$GRj */
4214   {
4215     FRV_INSN_FTLT, "ftlt", "ftlt", 32,
4216     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4217   },
4218 /* ftuge$pack $FCCi_2,$GRi,$GRj */
4219   {
4220     FRV_INSN_FTUGE, "ftuge", "ftuge", 32,
4221     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4222   },
4223 /* ftug$pack $FCCi_2,$GRi,$GRj */
4224   {
4225     FRV_INSN_FTUG, "ftug", "ftug", 32,
4226     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4227   },
4228 /* ftle$pack $FCCi_2,$GRi,$GRj */
4229   {
4230     FRV_INSN_FTLE, "ftle", "ftle", 32,
4231     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4232   },
4233 /* ftgt$pack $FCCi_2,$GRi,$GRj */
4234   {
4235     FRV_INSN_FTGT, "ftgt", "ftgt", 32,
4236     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4237   },
4238 /* ftule$pack $FCCi_2,$GRi,$GRj */
4239   {
4240     FRV_INSN_FTULE, "ftule", "ftule", 32,
4241     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4242   },
4243 /* ftu$pack $FCCi_2,$GRi,$GRj */
4244   {
4245     FRV_INSN_FTU, "ftu", "ftu", 32,
4246     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4247   },
4248 /* fto$pack $FCCi_2,$GRi,$GRj */
4249   {
4250     FRV_INSN_FTO, "fto", "fto", 32,
4251     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4252   },
4253 /* tira$pack $GRi,$s12 */
4254   {
4255     FRV_INSN_TIRA, "tira", "tira", 32,
4256     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4257   },
4258 /* tino$pack */
4259   {
4260     FRV_INSN_TINO, "tino", "tino", 32,
4261     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4262   },
4263 /* tieq$pack $ICCi_2,$GRi,$s12 */
4264   {
4265     FRV_INSN_TIEQ, "tieq", "tieq", 32,
4266     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4267   },
4268 /* tine$pack $ICCi_2,$GRi,$s12 */
4269   {
4270     FRV_INSN_TINE, "tine", "tine", 32,
4271     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4272   },
4273 /* tile$pack $ICCi_2,$GRi,$s12 */
4274   {
4275     FRV_INSN_TILE, "tile", "tile", 32,
4276     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4277   },
4278 /* tigt$pack $ICCi_2,$GRi,$s12 */
4279   {
4280     FRV_INSN_TIGT, "tigt", "tigt", 32,
4281     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4282   },
4283 /* tilt$pack $ICCi_2,$GRi,$s12 */
4284   {
4285     FRV_INSN_TILT, "tilt", "tilt", 32,
4286     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4287   },
4288 /* tige$pack $ICCi_2,$GRi,$s12 */
4289   {
4290     FRV_INSN_TIGE, "tige", "tige", 32,
4291     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4292   },
4293 /* tils$pack $ICCi_2,$GRi,$s12 */
4294   {
4295     FRV_INSN_TILS, "tils", "tils", 32,
4296     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4297   },
4298 /* tihi$pack $ICCi_2,$GRi,$s12 */
4299   {
4300     FRV_INSN_TIHI, "tihi", "tihi", 32,
4301     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4302   },
4303 /* tic$pack $ICCi_2,$GRi,$s12 */
4304   {
4305     FRV_INSN_TIC, "tic", "tic", 32,
4306     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4307   },
4308 /* tinc$pack $ICCi_2,$GRi,$s12 */
4309   {
4310     FRV_INSN_TINC, "tinc", "tinc", 32,
4311     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4312   },
4313 /* tin$pack $ICCi_2,$GRi,$s12 */
4314   {
4315     FRV_INSN_TIN, "tin", "tin", 32,
4316     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4317   },
4318 /* tip$pack $ICCi_2,$GRi,$s12 */
4319   {
4320     FRV_INSN_TIP, "tip", "tip", 32,
4321     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4322   },
4323 /* tiv$pack $ICCi_2,$GRi,$s12 */
4324   {
4325     FRV_INSN_TIV, "tiv", "tiv", 32,
4326     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4327   },
4328 /* tinv$pack $ICCi_2,$GRi,$s12 */
4329   {
4330     FRV_INSN_TINV, "tinv", "tinv", 32,
4331     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4332   },
4333 /* ftira$pack $GRi,$s12 */
4334   {
4335     FRV_INSN_FTIRA, "ftira", "ftira", 32,
4336     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4337   },
4338 /* ftino$pack */
4339   {
4340     FRV_INSN_FTINO, "ftino", "ftino", 32,
4341     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4342   },
4343 /* ftine$pack $FCCi_2,$GRi,$s12 */
4344   {
4345     FRV_INSN_FTINE, "ftine", "ftine", 32,
4346     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4347   },
4348 /* ftieq$pack $FCCi_2,$GRi,$s12 */
4349   {
4350     FRV_INSN_FTIEQ, "ftieq", "ftieq", 32,
4351     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4352   },
4353 /* ftilg$pack $FCCi_2,$GRi,$s12 */
4354   {
4355     FRV_INSN_FTILG, "ftilg", "ftilg", 32,
4356     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4357   },
4358 /* ftiue$pack $FCCi_2,$GRi,$s12 */
4359   {
4360     FRV_INSN_FTIUE, "ftiue", "ftiue", 32,
4361     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4362   },
4363 /* ftiul$pack $FCCi_2,$GRi,$s12 */
4364   {
4365     FRV_INSN_FTIUL, "ftiul", "ftiul", 32,
4366     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4367   },
4368 /* ftige$pack $FCCi_2,$GRi,$s12 */
4369   {
4370     FRV_INSN_FTIGE, "ftige", "ftige", 32,
4371     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4372   },
4373 /* ftilt$pack $FCCi_2,$GRi,$s12 */
4374   {
4375     FRV_INSN_FTILT, "ftilt", "ftilt", 32,
4376     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4377   },
4378 /* ftiuge$pack $FCCi_2,$GRi,$s12 */
4379   {
4380     FRV_INSN_FTIUGE, "ftiuge", "ftiuge", 32,
4381     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4382   },
4383 /* ftiug$pack $FCCi_2,$GRi,$s12 */
4384   {
4385     FRV_INSN_FTIUG, "ftiug", "ftiug", 32,
4386     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4387   },
4388 /* ftile$pack $FCCi_2,$GRi,$s12 */
4389   {
4390     FRV_INSN_FTILE, "ftile", "ftile", 32,
4391     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4392   },
4393 /* ftigt$pack $FCCi_2,$GRi,$s12 */
4394   {
4395     FRV_INSN_FTIGT, "ftigt", "ftigt", 32,
4396     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4397   },
4398 /* ftiule$pack $FCCi_2,$GRi,$s12 */
4399   {
4400     FRV_INSN_FTIULE, "ftiule", "ftiule", 32,
4401     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4402   },
4403 /* ftiu$pack $FCCi_2,$GRi,$s12 */
4404   {
4405     FRV_INSN_FTIU, "ftiu", "ftiu", 32,
4406     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4407   },
4408 /* ftio$pack $FCCi_2,$GRi,$s12 */
4409   {
4410     FRV_INSN_FTIO, "ftio", "ftio", 32,
4411     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4412   },
4413 /* break$pack */
4414   {
4415     FRV_INSN_BREAK, "break", "break", 32,
4416     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4417   },
4418 /* mtrap$pack */
4419   {
4420     FRV_INSN_MTRAP, "mtrap", "mtrap", 32,
4421     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4422   },
4423 /* andcr$pack $CRi,$CRj,$CRk */
4424   {
4425     FRV_INSN_ANDCR, "andcr", "andcr", 32,
4426     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4427   },
4428 /* orcr$pack $CRi,$CRj,$CRk */
4429   {
4430     FRV_INSN_ORCR, "orcr", "orcr", 32,
4431     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4432   },
4433 /* xorcr$pack $CRi,$CRj,$CRk */
4434   {
4435     FRV_INSN_XORCR, "xorcr", "xorcr", 32,
4436     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4437   },
4438 /* nandcr$pack $CRi,$CRj,$CRk */
4439   {
4440     FRV_INSN_NANDCR, "nandcr", "nandcr", 32,
4441     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4442   },
4443 /* norcr$pack $CRi,$CRj,$CRk */
4444   {
4445     FRV_INSN_NORCR, "norcr", "norcr", 32,
4446     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4447   },
4448 /* andncr$pack $CRi,$CRj,$CRk */
4449   {
4450     FRV_INSN_ANDNCR, "andncr", "andncr", 32,
4451     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4452   },
4453 /* orncr$pack $CRi,$CRj,$CRk */
4454   {
4455     FRV_INSN_ORNCR, "orncr", "orncr", 32,
4456     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4457   },
4458 /* nandncr$pack $CRi,$CRj,$CRk */
4459   {
4460     FRV_INSN_NANDNCR, "nandncr", "nandncr", 32,
4461     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4462   },
4463 /* norncr$pack $CRi,$CRj,$CRk */
4464   {
4465     FRV_INSN_NORNCR, "norncr", "norncr", 32,
4466     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4467   },
4468 /* notcr$pack $CRj,$CRk */
4469   {
4470     FRV_INSN_NOTCR, "notcr", "notcr", 32,
4471     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4472   },
4473 /* ckra$pack $CRj_int */
4474   {
4475     FRV_INSN_CKRA, "ckra", "ckra", 32,
4476     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4477   },
4478 /* ckno$pack $CRj_int */
4479   {
4480     FRV_INSN_CKNO, "ckno", "ckno", 32,
4481     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4482   },
4483 /* ckeq$pack $ICCi_3,$CRj_int */
4484   {
4485     FRV_INSN_CKEQ, "ckeq", "ckeq", 32,
4486     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4487   },
4488 /* ckne$pack $ICCi_3,$CRj_int */
4489   {
4490     FRV_INSN_CKNE, "ckne", "ckne", 32,
4491     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4492   },
4493 /* ckle$pack $ICCi_3,$CRj_int */
4494   {
4495     FRV_INSN_CKLE, "ckle", "ckle", 32,
4496     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4497   },
4498 /* ckgt$pack $ICCi_3,$CRj_int */
4499   {
4500     FRV_INSN_CKGT, "ckgt", "ckgt", 32,
4501     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4502   },
4503 /* cklt$pack $ICCi_3,$CRj_int */
4504   {
4505     FRV_INSN_CKLT, "cklt", "cklt", 32,
4506     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4507   },
4508 /* ckge$pack $ICCi_3,$CRj_int */
4509   {
4510     FRV_INSN_CKGE, "ckge", "ckge", 32,
4511     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4512   },
4513 /* ckls$pack $ICCi_3,$CRj_int */
4514   {
4515     FRV_INSN_CKLS, "ckls", "ckls", 32,
4516     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4517   },
4518 /* ckhi$pack $ICCi_3,$CRj_int */
4519   {
4520     FRV_INSN_CKHI, "ckhi", "ckhi", 32,
4521     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4522   },
4523 /* ckc$pack $ICCi_3,$CRj_int */
4524   {
4525     FRV_INSN_CKC, "ckc", "ckc", 32,
4526     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4527   },
4528 /* cknc$pack $ICCi_3,$CRj_int */
4529   {
4530     FRV_INSN_CKNC, "cknc", "cknc", 32,
4531     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4532   },
4533 /* ckn$pack $ICCi_3,$CRj_int */
4534   {
4535     FRV_INSN_CKN, "ckn", "ckn", 32,
4536     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4537   },
4538 /* ckp$pack $ICCi_3,$CRj_int */
4539   {
4540     FRV_INSN_CKP, "ckp", "ckp", 32,
4541     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4542   },
4543 /* ckv$pack $ICCi_3,$CRj_int */
4544   {
4545     FRV_INSN_CKV, "ckv", "ckv", 32,
4546     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4547   },
4548 /* cknv$pack $ICCi_3,$CRj_int */
4549   {
4550     FRV_INSN_CKNV, "cknv", "cknv", 32,
4551     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4552   },
4553 /* fckra$pack $CRj_float */
4554   {
4555     FRV_INSN_FCKRA, "fckra", "fckra", 32,
4556     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4557   },
4558 /* fckno$pack $CRj_float */
4559   {
4560     FRV_INSN_FCKNO, "fckno", "fckno", 32,
4561     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4562   },
4563 /* fckne$pack $FCCi_3,$CRj_float */
4564   {
4565     FRV_INSN_FCKNE, "fckne", "fckne", 32,
4566     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4567   },
4568 /* fckeq$pack $FCCi_3,$CRj_float */
4569   {
4570     FRV_INSN_FCKEQ, "fckeq", "fckeq", 32,
4571     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4572   },
4573 /* fcklg$pack $FCCi_3,$CRj_float */
4574   {
4575     FRV_INSN_FCKLG, "fcklg", "fcklg", 32,
4576     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4577   },
4578 /* fckue$pack $FCCi_3,$CRj_float */
4579   {
4580     FRV_INSN_FCKUE, "fckue", "fckue", 32,
4581     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4582   },
4583 /* fckul$pack $FCCi_3,$CRj_float */
4584   {
4585     FRV_INSN_FCKUL, "fckul", "fckul", 32,
4586     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4587   },
4588 /* fckge$pack $FCCi_3,$CRj_float */
4589   {
4590     FRV_INSN_FCKGE, "fckge", "fckge", 32,
4591     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4592   },
4593 /* fcklt$pack $FCCi_3,$CRj_float */
4594   {
4595     FRV_INSN_FCKLT, "fcklt", "fcklt", 32,
4596     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4597   },
4598 /* fckuge$pack $FCCi_3,$CRj_float */
4599   {
4600     FRV_INSN_FCKUGE, "fckuge", "fckuge", 32,
4601     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4602   },
4603 /* fckug$pack $FCCi_3,$CRj_float */
4604   {
4605     FRV_INSN_FCKUG, "fckug", "fckug", 32,
4606     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4607   },
4608 /* fckle$pack $FCCi_3,$CRj_float */
4609   {
4610     FRV_INSN_FCKLE, "fckle", "fckle", 32,
4611     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4612   },
4613 /* fckgt$pack $FCCi_3,$CRj_float */
4614   {
4615     FRV_INSN_FCKGT, "fckgt", "fckgt", 32,
4616     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4617   },
4618 /* fckule$pack $FCCi_3,$CRj_float */
4619   {
4620     FRV_INSN_FCKULE, "fckule", "fckule", 32,
4621     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4622   },
4623 /* fcku$pack $FCCi_3,$CRj_float */
4624   {
4625     FRV_INSN_FCKU, "fcku", "fcku", 32,
4626     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4627   },
4628 /* fcko$pack $FCCi_3,$CRj_float */
4629   {
4630     FRV_INSN_FCKO, "fcko", "fcko", 32,
4631     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4632   },
4633 /* cckra$pack $CRj_int,$CCi,$cond */
4634   {
4635     FRV_INSN_CCKRA, "cckra", "cckra", 32,
4636     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4637   },
4638 /* cckno$pack $CRj_int,$CCi,$cond */
4639   {
4640     FRV_INSN_CCKNO, "cckno", "cckno", 32,
4641     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4642   },
4643 /* cckeq$pack $ICCi_3,$CRj_int,$CCi,$cond */
4644   {
4645     FRV_INSN_CCKEQ, "cckeq", "cckeq", 32,
4646     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4647   },
4648 /* cckne$pack $ICCi_3,$CRj_int,$CCi,$cond */
4649   {
4650     FRV_INSN_CCKNE, "cckne", "cckne", 32,
4651     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4652   },
4653 /* cckle$pack $ICCi_3,$CRj_int,$CCi,$cond */
4654   {
4655     FRV_INSN_CCKLE, "cckle", "cckle", 32,
4656     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4657   },
4658 /* cckgt$pack $ICCi_3,$CRj_int,$CCi,$cond */
4659   {
4660     FRV_INSN_CCKGT, "cckgt", "cckgt", 32,
4661     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4662   },
4663 /* ccklt$pack $ICCi_3,$CRj_int,$CCi,$cond */
4664   {
4665     FRV_INSN_CCKLT, "ccklt", "ccklt", 32,
4666     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4667   },
4668 /* cckge$pack $ICCi_3,$CRj_int,$CCi,$cond */
4669   {
4670     FRV_INSN_CCKGE, "cckge", "cckge", 32,
4671     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4672   },
4673 /* cckls$pack $ICCi_3,$CRj_int,$CCi,$cond */
4674   {
4675     FRV_INSN_CCKLS, "cckls", "cckls", 32,
4676     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4677   },
4678 /* cckhi$pack $ICCi_3,$CRj_int,$CCi,$cond */
4679   {
4680     FRV_INSN_CCKHI, "cckhi", "cckhi", 32,
4681     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4682   },
4683 /* cckc$pack $ICCi_3,$CRj_int,$CCi,$cond */
4684   {
4685     FRV_INSN_CCKC, "cckc", "cckc", 32,
4686     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4687   },
4688 /* ccknc$pack $ICCi_3,$CRj_int,$CCi,$cond */
4689   {
4690     FRV_INSN_CCKNC, "ccknc", "ccknc", 32,
4691     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4692   },
4693 /* cckn$pack $ICCi_3,$CRj_int,$CCi,$cond */
4694   {
4695     FRV_INSN_CCKN, "cckn", "cckn", 32,
4696     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4697   },
4698 /* cckp$pack $ICCi_3,$CRj_int,$CCi,$cond */
4699   {
4700     FRV_INSN_CCKP, "cckp", "cckp", 32,
4701     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4702   },
4703 /* cckv$pack $ICCi_3,$CRj_int,$CCi,$cond */
4704   {
4705     FRV_INSN_CCKV, "cckv", "cckv", 32,
4706     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4707   },
4708 /* ccknv$pack $ICCi_3,$CRj_int,$CCi,$cond */
4709   {
4710     FRV_INSN_CCKNV, "ccknv", "ccknv", 32,
4711     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4712   },
4713 /* cfckra$pack $CRj_float,$CCi,$cond */
4714   {
4715     FRV_INSN_CFCKRA, "cfckra", "cfckra", 32,
4716     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4717   },
4718 /* cfckno$pack $CRj_float,$CCi,$cond */
4719   {
4720     FRV_INSN_CFCKNO, "cfckno", "cfckno", 32,
4721     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4722   },
4723 /* cfckne$pack $FCCi_3,$CRj_float,$CCi,$cond */
4724   {
4725     FRV_INSN_CFCKNE, "cfckne", "cfckne", 32,
4726     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4727   },
4728 /* cfckeq$pack $FCCi_3,$CRj_float,$CCi,$cond */
4729   {
4730     FRV_INSN_CFCKEQ, "cfckeq", "cfckeq", 32,
4731     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4732   },
4733 /* cfcklg$pack $FCCi_3,$CRj_float,$CCi,$cond */
4734   {
4735     FRV_INSN_CFCKLG, "cfcklg", "cfcklg", 32,
4736     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4737   },
4738 /* cfckue$pack $FCCi_3,$CRj_float,$CCi,$cond */
4739   {
4740     FRV_INSN_CFCKUE, "cfckue", "cfckue", 32,
4741     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4742   },
4743 /* cfckul$pack $FCCi_3,$CRj_float,$CCi,$cond */
4744   {
4745     FRV_INSN_CFCKUL, "cfckul", "cfckul", 32,
4746     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4747   },
4748 /* cfckge$pack $FCCi_3,$CRj_float,$CCi,$cond */
4749   {
4750     FRV_INSN_CFCKGE, "cfckge", "cfckge", 32,
4751     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4752   },
4753 /* cfcklt$pack $FCCi_3,$CRj_float,$CCi,$cond */
4754   {
4755     FRV_INSN_CFCKLT, "cfcklt", "cfcklt", 32,
4756     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4757   },
4758 /* cfckuge$pack $FCCi_3,$CRj_float,$CCi,$cond */
4759   {
4760     FRV_INSN_CFCKUGE, "cfckuge", "cfckuge", 32,
4761     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4762   },
4763 /* cfckug$pack $FCCi_3,$CRj_float,$CCi,$cond */
4764   {
4765     FRV_INSN_CFCKUG, "cfckug", "cfckug", 32,
4766     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4767   },
4768 /* cfckle$pack $FCCi_3,$CRj_float,$CCi,$cond */
4769   {
4770     FRV_INSN_CFCKLE, "cfckle", "cfckle", 32,
4771     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4772   },
4773 /* cfckgt$pack $FCCi_3,$CRj_float,$CCi,$cond */
4774   {
4775     FRV_INSN_CFCKGT, "cfckgt", "cfckgt", 32,
4776     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4777   },
4778 /* cfckule$pack $FCCi_3,$CRj_float,$CCi,$cond */
4779   {
4780     FRV_INSN_CFCKULE, "cfckule", "cfckule", 32,
4781     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4782   },
4783 /* cfcku$pack $FCCi_3,$CRj_float,$CCi,$cond */
4784   {
4785     FRV_INSN_CFCKU, "cfcku", "cfcku", 32,
4786     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4787   },
4788 /* cfcko$pack $FCCi_3,$CRj_float,$CCi,$cond */
4789   {
4790     FRV_INSN_CFCKO, "cfcko", "cfcko", 32,
4791     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4792   },
4793 /* cjmpl$pack @($GRi,$GRj),$CCi,$cond */
4794   {
4795     FRV_INSN_CJMPL, "cjmpl", "cjmpl", 32,
4796     { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
4797   },
4798 /* ccalll$pack @($GRi,$GRj),$CCi,$cond */
4799   {
4800     FRV_INSN_CCALLL, "ccalll", "ccalll", 32,
4801     { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
4802   },
4803 /* ici$pack @($GRi,$GRj) */
4804   {
4805     FRV_INSN_ICI, "ici", "ici", 32,
4806     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4807   },
4808 /* dci$pack @($GRi,$GRj) */
4809   {
4810     FRV_INSN_DCI, "dci", "dci", 32,
4811     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4812   },
4813 /* icei$pack @($GRi,$GRj),$ae */
4814   {
4815     FRV_INSN_ICEI, "icei", "icei", 32,
4816     { 0, { (1<<MACH_FR400), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE } }
4817   },
4818 /* dcei$pack @($GRi,$GRj),$ae */
4819   {
4820     FRV_INSN_DCEI, "dcei", "dcei", 32,
4821     { 0, { (1<<MACH_FR400), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE } }
4822   },
4823 /* dcf$pack @($GRi,$GRj) */
4824   {
4825     FRV_INSN_DCF, "dcf", "dcf", 32,
4826     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4827   },
4828 /* dcef$pack @($GRi,$GRj),$ae */
4829   {
4830     FRV_INSN_DCEF, "dcef", "dcef", 32,
4831     { 0, { (1<<MACH_FR400), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE } }
4832   },
4833 /* witlb$pack $GRk,@($GRi,$GRj) */
4834   {
4835     FRV_INSN_WITLB, "witlb", "witlb", 32,
4836     { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
4837   },
4838 /* wdtlb$pack $GRk,@($GRi,$GRj) */
4839   {
4840     FRV_INSN_WDTLB, "wdtlb", "wdtlb", 32,
4841     { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
4842   },
4843 /* itlbi$pack @($GRi,$GRj) */
4844   {
4845     FRV_INSN_ITLBI, "itlbi", "itlbi", 32,
4846     { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
4847   },
4848 /* dtlbi$pack @($GRi,$GRj) */
4849   {
4850     FRV_INSN_DTLBI, "dtlbi", "dtlbi", 32,
4851     { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
4852   },
4853 /* icpl$pack $GRi,$GRj,$lock */
4854   {
4855     FRV_INSN_ICPL, "icpl", "icpl", 32,
4856     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4857   },
4858 /* dcpl$pack $GRi,$GRj,$lock */
4859   {
4860     FRV_INSN_DCPL, "dcpl", "dcpl", 32,
4861     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4862   },
4863 /* icul$pack $GRi */
4864   {
4865     FRV_INSN_ICUL, "icul", "icul", 32,
4866     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4867   },
4868 /* dcul$pack $GRi */
4869   {
4870     FRV_INSN_DCUL, "dcul", "dcul", 32,
4871     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4872   },
4873 /* bar$pack */
4874   {
4875     FRV_INSN_BAR, "bar", "bar", 32,
4876     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4877   },
4878 /* membar$pack */
4879   {
4880     FRV_INSN_MEMBAR, "membar", "membar", 32,
4881     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4882   },
4883 /* cop1$pack $s6_1,$CPRi,$CPRj,$CPRk */
4884   {
4885     FRV_INSN_COP1, "cop1", "cop1", 32,
4886     { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
4887   },
4888 /* cop2$pack $s6_1,$CPRi,$CPRj,$CPRk */
4889   {
4890     FRV_INSN_COP2, "cop2", "cop2", 32,
4891     { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
4892   },
4893 /* clrgr$pack $GRk */
4894   {
4895     FRV_INSN_CLRGR, "clrgr", "clrgr", 32,
4896     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4897   },
4898 /* clrfr$pack $FRk */
4899   {
4900     FRV_INSN_CLRFR, "clrfr", "clrfr", 32,
4901     { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4902   },
4903 /* clrga$pack */
4904   {
4905     FRV_INSN_CLRGA, "clrga", "clrga", 32,
4906     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4907   },
4908 /* clrfa$pack */
4909   {
4910     FRV_INSN_CLRFA, "clrfa", "clrfa", 32,
4911     { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4912   },
4913 /* commitgr$pack $GRk */
4914   {
4915     FRV_INSN_COMMITGR, "commitgr", "commitgr", 32,
4916     { 0, { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4917   },
4918 /* commitfr$pack $FRk */
4919   {
4920     FRV_INSN_COMMITFR, "commitfr", "commitfr", 32,
4921     { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4922   },
4923 /* commitga$pack */
4924   {
4925     FRV_INSN_COMMITGA, "commitga", "commitga", 32,
4926     { 0, { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4927   },
4928 /* commitfa$pack */
4929   {
4930     FRV_INSN_COMMITFA, "commitfa", "commitfa", 32,
4931     { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4932   },
4933 /* fitos$pack $FRintj,$FRk */
4934   {
4935     FRV_INSN_FITOS, "fitos", "fitos", 32,
4936     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4937   },
4938 /* fstoi$pack $FRj,$FRintk */
4939   {
4940     FRV_INSN_FSTOI, "fstoi", "fstoi", 32,
4941     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4942   },
4943 /* fitod$pack $FRintj,$FRdoublek */
4944   {
4945     FRV_INSN_FITOD, "fitod", "fitod", 32,
4946     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4947   },
4948 /* fdtoi$pack $FRdoublej,$FRintk */
4949   {
4950     FRV_INSN_FDTOI, "fdtoi", "fdtoi", 32,
4951     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4952   },
4953 /* fditos$pack $FRintj,$FRk */
4954   {
4955     FRV_INSN_FDITOS, "fditos", "fditos", 32,
4956     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4957   },
4958 /* fdstoi$pack $FRj,$FRintk */
4959   {
4960     FRV_INSN_FDSTOI, "fdstoi", "fdstoi", 32,
4961     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4962   },
4963 /* nfditos$pack $FRintj,$FRk */
4964   {
4965     FRV_INSN_NFDITOS, "nfditos", "nfditos", 32,
4966     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4967   },
4968 /* nfdstoi$pack $FRj,$FRintk */
4969   {
4970     FRV_INSN_NFDSTOI, "nfdstoi", "nfdstoi", 32,
4971     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4972   },
4973 /* cfitos$pack $FRintj,$FRk,$CCi,$cond */
4974   {
4975     FRV_INSN_CFITOS, "cfitos", "cfitos", 32,
4976     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4977   },
4978 /* cfstoi$pack $FRj,$FRintk,$CCi,$cond */
4979   {
4980     FRV_INSN_CFSTOI, "cfstoi", "cfstoi", 32,
4981     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4982   },
4983 /* nfitos$pack $FRintj,$FRk */
4984   {
4985     FRV_INSN_NFITOS, "nfitos", "nfitos", 32,
4986     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4987   },
4988 /* nfstoi$pack $FRj,$FRintk */
4989   {
4990     FRV_INSN_NFSTOI, "nfstoi", "nfstoi", 32,
4991     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4992   },
4993 /* fmovs$pack $FRj,$FRk */
4994   {
4995     FRV_INSN_FMOVS, "fmovs", "fmovs", 32,
4996     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4997   },
4998 /* fmovd$pack $FRdoublej,$FRdoublek */
4999   {
5000     FRV_INSN_FMOVD, "fmovd", "fmovd", 32,
5001     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5002   },
5003 /* fdmovs$pack $FRj,$FRk */
5004   {
5005     FRV_INSN_FDMOVS, "fdmovs", "fdmovs", 32,
5006     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5007   },
5008 /* cfmovs$pack $FRj,$FRk,$CCi,$cond */
5009   {
5010     FRV_INSN_CFMOVS, "cfmovs", "cfmovs", 32,
5011     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5012   },
5013 /* fnegs$pack $FRj,$FRk */
5014   {
5015     FRV_INSN_FNEGS, "fnegs", "fnegs", 32,
5016     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5017   },
5018 /* fnegd$pack $FRdoublej,$FRdoublek */
5019   {
5020     FRV_INSN_FNEGD, "fnegd", "fnegd", 32,
5021     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5022   },
5023 /* fdnegs$pack $FRj,$FRk */
5024   {
5025     FRV_INSN_FDNEGS, "fdnegs", "fdnegs", 32,
5026     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5027   },
5028 /* cfnegs$pack $FRj,$FRk,$CCi,$cond */
5029   {
5030     FRV_INSN_CFNEGS, "cfnegs", "cfnegs", 32,
5031     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5032   },
5033 /* fabss$pack $FRj,$FRk */
5034   {
5035     FRV_INSN_FABSS, "fabss", "fabss", 32,
5036     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5037   },
5038 /* fabsd$pack $FRdoublej,$FRdoublek */
5039   {
5040     FRV_INSN_FABSD, "fabsd", "fabsd", 32,
5041     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5042   },
5043 /* fdabss$pack $FRj,$FRk */
5044   {
5045     FRV_INSN_FDABSS, "fdabss", "fdabss", 32,
5046     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5047   },
5048 /* cfabss$pack $FRj,$FRk,$CCi,$cond */
5049   {
5050     FRV_INSN_CFABSS, "cfabss", "cfabss", 32,
5051     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5052   },
5053 /* fsqrts$pack $FRj,$FRk */
5054   {
5055     FRV_INSN_FSQRTS, "fsqrts", "fsqrts", 32,
5056     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5057   },
5058 /* fdsqrts$pack $FRj,$FRk */
5059   {
5060     FRV_INSN_FDSQRTS, "fdsqrts", "fdsqrts", 32,
5061     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5062   },
5063 /* nfdsqrts$pack $FRj,$FRk */
5064   {
5065     FRV_INSN_NFDSQRTS, "nfdsqrts", "nfdsqrts", 32,
5066     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5067   },
5068 /* fsqrtd$pack $FRdoublej,$FRdoublek */
5069   {
5070     FRV_INSN_FSQRTD, "fsqrtd", "fsqrtd", 32,
5071     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5072   },
5073 /* cfsqrts$pack $FRj,$FRk,$CCi,$cond */
5074   {
5075     FRV_INSN_CFSQRTS, "cfsqrts", "cfsqrts", 32,
5076     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5077   },
5078 /* nfsqrts$pack $FRj,$FRk */
5079   {
5080     FRV_INSN_NFSQRTS, "nfsqrts", "nfsqrts", 32,
5081     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5082   },
5083 /* fadds$pack $FRi,$FRj,$FRk */
5084   {
5085     FRV_INSN_FADDS, "fadds", "fadds", 32,
5086     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5087   },
5088 /* fsubs$pack $FRi,$FRj,$FRk */
5089   {
5090     FRV_INSN_FSUBS, "fsubs", "fsubs", 32,
5091     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5092   },
5093 /* fmuls$pack $FRi,$FRj,$FRk */
5094   {
5095     FRV_INSN_FMULS, "fmuls", "fmuls", 32,
5096     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } }
5097   },
5098 /* fdivs$pack $FRi,$FRj,$FRk */
5099   {
5100     FRV_INSN_FDIVS, "fdivs", "fdivs", 32,
5101     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5102   },
5103 /* faddd$pack $FRdoublei,$FRdoublej,$FRdoublek */
5104   {
5105     FRV_INSN_FADDD, "faddd", "faddd", 32,
5106     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5107   },
5108 /* fsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */
5109   {
5110     FRV_INSN_FSUBD, "fsubd", "fsubd", 32,
5111     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5112   },
5113 /* fmuld$pack $FRdoublei,$FRdoublej,$FRdoublek */
5114   {
5115     FRV_INSN_FMULD, "fmuld", "fmuld", 32,
5116     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } }
5117   },
5118 /* fdivd$pack $FRdoublei,$FRdoublej,$FRdoublek */
5119   {
5120     FRV_INSN_FDIVD, "fdivd", "fdivd", 32,
5121     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5122   },
5123 /* cfadds$pack $FRi,$FRj,$FRk,$CCi,$cond */
5124   {
5125     FRV_INSN_CFADDS, "cfadds", "cfadds", 32,
5126     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5127   },
5128 /* cfsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */
5129   {
5130     FRV_INSN_CFSUBS, "cfsubs", "cfsubs", 32,
5131     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5132   },
5133 /* cfmuls$pack $FRi,$FRj,$FRk,$CCi,$cond */
5134   {
5135     FRV_INSN_CFMULS, "cfmuls", "cfmuls", 32,
5136     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } }
5137   },
5138 /* cfdivs$pack $FRi,$FRj,$FRk,$CCi,$cond */
5139   {
5140     FRV_INSN_CFDIVS, "cfdivs", "cfdivs", 32,
5141     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5142   },
5143 /* nfadds$pack $FRi,$FRj,$FRk */
5144   {
5145     FRV_INSN_NFADDS, "nfadds", "nfadds", 32,
5146     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5147   },
5148 /* nfsubs$pack $FRi,$FRj,$FRk */
5149   {
5150     FRV_INSN_NFSUBS, "nfsubs", "nfsubs", 32,
5151     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5152   },
5153 /* nfmuls$pack $FRi,$FRj,$FRk */
5154   {
5155     FRV_INSN_NFMULS, "nfmuls", "nfmuls", 32,
5156     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } }
5157   },
5158 /* nfdivs$pack $FRi,$FRj,$FRk */
5159   {
5160     FRV_INSN_NFDIVS, "nfdivs", "nfdivs", 32,
5161     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5162   },
5163 /* fcmps$pack $FRi,$FRj,$FCCi_2 */
5164   {
5165     FRV_INSN_FCMPS, "fcmps", "fcmps", 32,
5166     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5167   },
5168 /* fcmpd$pack $FRdoublei,$FRdoublej,$FCCi_2 */
5169   {
5170     FRV_INSN_FCMPD, "fcmpd", "fcmpd", 32,
5171     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5172   },
5173 /* cfcmps$pack $FRi,$FRj,$FCCi_2,$CCi,$cond */
5174   {
5175     FRV_INSN_CFCMPS, "cfcmps", "cfcmps", 32,
5176     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5177   },
5178 /* fdcmps$pack $FRi,$FRj,$FCCi_2 */
5179   {
5180     FRV_INSN_FDCMPS, "fdcmps", "fdcmps", 32,
5181     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5182   },
5183 /* fmadds$pack $FRi,$FRj,$FRk */
5184   {
5185     FRV_INSN_FMADDS, "fmadds", "fmadds", 32,
5186     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5187   },
5188 /* fmsubs$pack $FRi,$FRj,$FRk */
5189   {
5190     FRV_INSN_FMSUBS, "fmsubs", "fmsubs", 32,
5191     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5192   },
5193 /* fmaddd$pack $FRdoublei,$FRdoublej,$FRdoublek */
5194   {
5195     FRV_INSN_FMADDD, "fmaddd", "fmaddd", 32,
5196     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5197   },
5198 /* fmsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */
5199   {
5200     FRV_INSN_FMSUBD, "fmsubd", "fmsubd", 32,
5201     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5202   },
5203 /* fdmadds$pack $FRi,$FRj,$FRk */
5204   {
5205     FRV_INSN_FDMADDS, "fdmadds", "fdmadds", 32,
5206     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5207   },
5208 /* nfdmadds$pack $FRi,$FRj,$FRk */
5209   {
5210     FRV_INSN_NFDMADDS, "nfdmadds", "nfdmadds", 32,
5211     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5212   },
5213 /* cfmadds$pack $FRi,$FRj,$FRk,$CCi,$cond */
5214   {
5215     FRV_INSN_CFMADDS, "cfmadds", "cfmadds", 32,
5216     { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5217   },
5218 /* cfmsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */
5219   {
5220     FRV_INSN_CFMSUBS, "cfmsubs", "cfmsubs", 32,
5221     { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5222   },
5223 /* nfmadds$pack $FRi,$FRj,$FRk */
5224   {
5225     FRV_INSN_NFMADDS, "nfmadds", "nfmadds", 32,
5226     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5227   },
5228 /* nfmsubs$pack $FRi,$FRj,$FRk */
5229   {
5230     FRV_INSN_NFMSUBS, "nfmsubs", "nfmsubs", 32,
5231     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5232   },
5233 /* fmas$pack $FRi,$FRj,$FRk */
5234   {
5235     FRV_INSN_FMAS, "fmas", "fmas", 32,
5236     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5237   },
5238 /* fmss$pack $FRi,$FRj,$FRk */
5239   {
5240     FRV_INSN_FMSS, "fmss", "fmss", 32,
5241     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5242   },
5243 /* fdmas$pack $FRi,$FRj,$FRk */
5244   {
5245     FRV_INSN_FDMAS, "fdmas", "fdmas", 32,
5246     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5247   },
5248 /* fdmss$pack $FRi,$FRj,$FRk */
5249   {
5250     FRV_INSN_FDMSS, "fdmss", "fdmss", 32,
5251     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5252   },
5253 /* nfdmas$pack $FRi,$FRj,$FRk */
5254   {
5255     FRV_INSN_NFDMAS, "nfdmas", "nfdmas", 32,
5256     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5257   },
5258 /* nfdmss$pack $FRi,$FRj,$FRk */
5259   {
5260     FRV_INSN_NFDMSS, "nfdmss", "nfdmss", 32,
5261     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5262   },
5263 /* cfmas$pack $FRi,$FRj,$FRk,$CCi,$cond */
5264   {
5265     FRV_INSN_CFMAS, "cfmas", "cfmas", 32,
5266     { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5267   },
5268 /* cfmss$pack $FRi,$FRj,$FRk,$CCi,$cond */
5269   {
5270     FRV_INSN_CFMSS, "cfmss", "cfmss", 32,
5271     { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5272   },
5273 /* fmad$pack $FRi,$FRj,$FRk */
5274   {
5275     FRV_INSN_FMAD, "fmad", "fmad", 32,
5276     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5277   },
5278 /* fmsd$pack $FRi,$FRj,$FRk */
5279   {
5280     FRV_INSN_FMSD, "fmsd", "fmsd", 32,
5281     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5282   },
5283 /* nfmas$pack $FRi,$FRj,$FRk */
5284   {
5285     FRV_INSN_NFMAS, "nfmas", "nfmas", 32,
5286     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5287   },
5288 /* nfmss$pack $FRi,$FRj,$FRk */
5289   {
5290     FRV_INSN_NFMSS, "nfmss", "nfmss", 32,
5291     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5292   },
5293 /* fdadds$pack $FRi,$FRj,$FRk */
5294   {
5295     FRV_INSN_FDADDS, "fdadds", "fdadds", 32,
5296     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5297   },
5298 /* fdsubs$pack $FRi,$FRj,$FRk */
5299   {
5300     FRV_INSN_FDSUBS, "fdsubs", "fdsubs", 32,
5301     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5302   },
5303 /* fdmuls$pack $FRi,$FRj,$FRk */
5304   {
5305     FRV_INSN_FDMULS, "fdmuls", "fdmuls", 32,
5306     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
5307   },
5308 /* fddivs$pack $FRi,$FRj,$FRk */
5309   {
5310     FRV_INSN_FDDIVS, "fddivs", "fddivs", 32,
5311     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
5312   },
5313 /* fdsads$pack $FRi,$FRj,$FRk */
5314   {
5315     FRV_INSN_FDSADS, "fdsads", "fdsads", 32,
5316     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5317   },
5318 /* fdmulcs$pack $FRi,$FRj,$FRk */
5319   {
5320     FRV_INSN_FDMULCS, "fdmulcs", "fdmulcs", 32,
5321     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
5322   },
5323 /* nfdmulcs$pack $FRi,$FRj,$FRk */
5324   {
5325     FRV_INSN_NFDMULCS, "nfdmulcs", "nfdmulcs", 32,
5326     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
5327   },
5328 /* nfdadds$pack $FRi,$FRj,$FRk */
5329   {
5330     FRV_INSN_NFDADDS, "nfdadds", "nfdadds", 32,
5331     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5332   },
5333 /* nfdsubs$pack $FRi,$FRj,$FRk */
5334   {
5335     FRV_INSN_NFDSUBS, "nfdsubs", "nfdsubs", 32,
5336     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5337   },
5338 /* nfdmuls$pack $FRi,$FRj,$FRk */
5339   {
5340     FRV_INSN_NFDMULS, "nfdmuls", "nfdmuls", 32,
5341     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
5342   },
5343 /* nfddivs$pack $FRi,$FRj,$FRk */
5344   {
5345     FRV_INSN_NFDDIVS, "nfddivs", "nfddivs", 32,
5346     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
5347   },
5348 /* nfdsads$pack $FRi,$FRj,$FRk */
5349   {
5350     FRV_INSN_NFDSADS, "nfdsads", "nfdsads", 32,
5351     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5352   },
5353 /* nfdcmps$pack $FRi,$FRj,$FCCi_2 */
5354   {
5355     FRV_INSN_NFDCMPS, "nfdcmps", "nfdcmps", 32,
5356     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5357   },
5358 /* mhsetlos$pack $u12,$FRklo */
5359   {
5360     FRV_INSN_MHSETLOS, "mhsetlos", "mhsetlos", 32,
5361     { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5362   },
5363 /* mhsethis$pack $u12,$FRkhi */
5364   {
5365     FRV_INSN_MHSETHIS, "mhsethis", "mhsethis", 32,
5366     { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5367   },
5368 /* mhdsets$pack $u12,$FRintk */
5369   {
5370     FRV_INSN_MHDSETS, "mhdsets", "mhdsets", 32,
5371     { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5372   },
5373 /* mhsetloh$pack $s5,$FRklo */
5374   {
5375     FRV_INSN_MHSETLOH, "mhsetloh", "mhsetloh", 32,
5376     { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5377   },
5378 /* mhsethih$pack $s5,$FRkhi */
5379   {
5380     FRV_INSN_MHSETHIH, "mhsethih", "mhsethih", 32,
5381     { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5382   },
5383 /* mhdseth$pack $s5,$FRintk */
5384   {
5385     FRV_INSN_MHDSETH, "mhdseth", "mhdseth", 32,
5386     { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5387   },
5388 /* mand$pack $FRinti,$FRintj,$FRintk */
5389   {
5390     FRV_INSN_MAND, "mand", "mand", 32,
5391     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5392   },
5393 /* mor$pack $FRinti,$FRintj,$FRintk */
5394   {
5395     FRV_INSN_MOR, "mor", "mor", 32,
5396     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5397   },
5398 /* mxor$pack $FRinti,$FRintj,$FRintk */
5399   {
5400     FRV_INSN_MXOR, "mxor", "mxor", 32,
5401     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5402   },
5403 /* cmand$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5404   {
5405     FRV_INSN_CMAND, "cmand", "cmand", 32,
5406     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5407   },
5408 /* cmor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5409   {
5410     FRV_INSN_CMOR, "cmor", "cmor", 32,
5411     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5412   },
5413 /* cmxor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5414   {
5415     FRV_INSN_CMXOR, "cmxor", "cmxor", 32,
5416     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5417   },
5418 /* mnot$pack $FRintj,$FRintk */
5419   {
5420     FRV_INSN_MNOT, "mnot", "mnot", 32,
5421     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5422   },
5423 /* cmnot$pack $FRintj,$FRintk,$CCi,$cond */
5424   {
5425     FRV_INSN_CMNOT, "cmnot", "cmnot", 32,
5426     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5427   },
5428 /* mrotli$pack $FRinti,$u6,$FRintk */
5429   {
5430     FRV_INSN_MROTLI, "mrotli", "mrotli", 32,
5431     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5432   },
5433 /* mrotri$pack $FRinti,$u6,$FRintk */
5434   {
5435     FRV_INSN_MROTRI, "mrotri", "mrotri", 32,
5436     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5437   },
5438 /* mwcut$pack $FRinti,$FRintj,$FRintk */
5439   {
5440     FRV_INSN_MWCUT, "mwcut", "mwcut", 32,
5441     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5442   },
5443 /* mwcuti$pack $FRinti,$u6,$FRintk */
5444   {
5445     FRV_INSN_MWCUTI, "mwcuti", "mwcuti", 32,
5446     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5447   },
5448 /* mcut$pack $ACC40Si,$FRintj,$FRintk */
5449   {
5450     FRV_INSN_MCUT, "mcut", "mcut", 32,
5451     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5452   },
5453 /* mcuti$pack $ACC40Si,$s6,$FRintk */
5454   {
5455     FRV_INSN_MCUTI, "mcuti", "mcuti", 32,
5456     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5457   },
5458 /* mcutss$pack $ACC40Si,$FRintj,$FRintk */
5459   {
5460     FRV_INSN_MCUTSS, "mcutss", "mcutss", 32,
5461     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5462   },
5463 /* mcutssi$pack $ACC40Si,$s6,$FRintk */
5464   {
5465     FRV_INSN_MCUTSSI, "mcutssi", "mcutssi", 32,
5466     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5467   },
5468 /* mdcutssi$pack $ACC40Si,$s6,$FRintk */
5469   {
5470     FRV_INSN_MDCUTSSI, "mdcutssi", "mdcutssi", 32,
5471     { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5472   },
5473 /* maveh$pack $FRinti,$FRintj,$FRintk */
5474   {
5475     FRV_INSN_MAVEH, "maveh", "maveh", 32,
5476     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5477   },
5478 /* msllhi$pack $FRinti,$u6,$FRintk */
5479   {
5480     FRV_INSN_MSLLHI, "msllhi", "msllhi", 32,
5481     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5482   },
5483 /* msrlhi$pack $FRinti,$u6,$FRintk */
5484   {
5485     FRV_INSN_MSRLHI, "msrlhi", "msrlhi", 32,
5486     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5487   },
5488 /* msrahi$pack $FRinti,$u6,$FRintk */
5489   {
5490     FRV_INSN_MSRAHI, "msrahi", "msrahi", 32,
5491     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5492   },
5493 /* mdrotli$pack $FRinti,$u6,$FRintk */
5494   {
5495     FRV_INSN_MDROTLI, "mdrotli", "mdrotli", 32,
5496     { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5497   },
5498 /* mcplhi$pack $FRinti,$u6,$FRintk */
5499   {
5500     FRV_INSN_MCPLHI, "mcplhi", "mcplhi", 32,
5501     { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5502   },
5503 /* mcpli$pack $FRinti,$u6,$FRintk */
5504   {
5505     FRV_INSN_MCPLI, "mcpli", "mcpli", 32,
5506     { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5507   },
5508 /* msaths$pack $FRinti,$FRintj,$FRintk */
5509   {
5510     FRV_INSN_MSATHS, "msaths", "msaths", 32,
5511     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5512   },
5513 /* mqsaths$pack $FRinti,$FRintj,$FRintk */
5514   {
5515     FRV_INSN_MQSATHS, "mqsaths", "mqsaths", 32,
5516     { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5517   },
5518 /* msathu$pack $FRinti,$FRintj,$FRintk */
5519   {
5520     FRV_INSN_MSATHU, "msathu", "msathu", 32,
5521     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5522   },
5523 /* mcmpsh$pack $FRinti,$FRintj,$FCCk */
5524   {
5525     FRV_INSN_MCMPSH, "mcmpsh", "mcmpsh", 32,
5526     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5527   },
5528 /* mcmpuh$pack $FRinti,$FRintj,$FCCk */
5529   {
5530     FRV_INSN_MCMPUH, "mcmpuh", "mcmpuh", 32,
5531     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5532   },
5533 /* mabshs$pack $FRintj,$FRintk */
5534   {
5535     FRV_INSN_MABSHS, "mabshs", "mabshs", 32,
5536     { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5537   },
5538 /* maddhss$pack $FRinti,$FRintj,$FRintk */
5539   {
5540     FRV_INSN_MADDHSS, "maddhss", "maddhss", 32,
5541     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5542   },
5543 /* maddhus$pack $FRinti,$FRintj,$FRintk */
5544   {
5545     FRV_INSN_MADDHUS, "maddhus", "maddhus", 32,
5546     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5547   },
5548 /* msubhss$pack $FRinti,$FRintj,$FRintk */
5549   {
5550     FRV_INSN_MSUBHSS, "msubhss", "msubhss", 32,
5551     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5552   },
5553 /* msubhus$pack $FRinti,$FRintj,$FRintk */
5554   {
5555     FRV_INSN_MSUBHUS, "msubhus", "msubhus", 32,
5556     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5557   },
5558 /* cmaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5559   {
5560     FRV_INSN_CMADDHSS, "cmaddhss", "cmaddhss", 32,
5561     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5562   },
5563 /* cmaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5564   {
5565     FRV_INSN_CMADDHUS, "cmaddhus", "cmaddhus", 32,
5566     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5567   },
5568 /* cmsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5569   {
5570     FRV_INSN_CMSUBHSS, "cmsubhss", "cmsubhss", 32,
5571     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5572   },
5573 /* cmsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5574   {
5575     FRV_INSN_CMSUBHUS, "cmsubhus", "cmsubhus", 32,
5576     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5577   },
5578 /* mqaddhss$pack $FRinti,$FRintj,$FRintk */
5579   {
5580     FRV_INSN_MQADDHSS, "mqaddhss", "mqaddhss", 32,
5581     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5582   },
5583 /* mqaddhus$pack $FRinti,$FRintj,$FRintk */
5584   {
5585     FRV_INSN_MQADDHUS, "mqaddhus", "mqaddhus", 32,
5586     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5587   },
5588 /* mqsubhss$pack $FRinti,$FRintj,$FRintk */
5589   {
5590     FRV_INSN_MQSUBHSS, "mqsubhss", "mqsubhss", 32,
5591     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5592   },
5593 /* mqsubhus$pack $FRinti,$FRintj,$FRintk */
5594   {
5595     FRV_INSN_MQSUBHUS, "mqsubhus", "mqsubhus", 32,
5596     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5597   },
5598 /* cmqaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5599   {
5600     FRV_INSN_CMQADDHSS, "cmqaddhss", "cmqaddhss", 32,
5601     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5602   },
5603 /* cmqaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5604   {
5605     FRV_INSN_CMQADDHUS, "cmqaddhus", "cmqaddhus", 32,
5606     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5607   },
5608 /* cmqsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5609   {
5610     FRV_INSN_CMQSUBHSS, "cmqsubhss", "cmqsubhss", 32,
5611     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5612   },
5613 /* cmqsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5614   {
5615     FRV_INSN_CMQSUBHUS, "cmqsubhus", "cmqsubhus", 32,
5616     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5617   },
5618 /* maddaccs$pack $ACC40Si,$ACC40Sk */
5619   {
5620     FRV_INSN_MADDACCS, "maddaccs", "maddaccs", 32,
5621     { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5622   },
5623 /* msubaccs$pack $ACC40Si,$ACC40Sk */
5624   {
5625     FRV_INSN_MSUBACCS, "msubaccs", "msubaccs", 32,
5626     { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5627   },
5628 /* mdaddaccs$pack $ACC40Si,$ACC40Sk */
5629   {
5630     FRV_INSN_MDADDACCS, "mdaddaccs", "mdaddaccs", 32,
5631     { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5632   },
5633 /* mdsubaccs$pack $ACC40Si,$ACC40Sk */
5634   {
5635     FRV_INSN_MDSUBACCS, "mdsubaccs", "mdsubaccs", 32,
5636     { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5637   },
5638 /* masaccs$pack $ACC40Si,$ACC40Sk */
5639   {
5640     FRV_INSN_MASACCS, "masaccs", "masaccs", 32,
5641     { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5642   },
5643 /* mdasaccs$pack $ACC40Si,$ACC40Sk */
5644   {
5645     FRV_INSN_MDASACCS, "mdasaccs", "mdasaccs", 32,
5646     { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5647   },
5648 /* mmulhs$pack $FRinti,$FRintj,$ACC40Sk */
5649   {
5650     FRV_INSN_MMULHS, "mmulhs", "mmulhs", 32,
5651     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5652   },
5653 /* mmulhu$pack $FRinti,$FRintj,$ACC40Sk */
5654   {
5655     FRV_INSN_MMULHU, "mmulhu", "mmulhu", 32,
5656     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5657   },
5658 /* mmulxhs$pack $FRinti,$FRintj,$ACC40Sk */
5659   {
5660     FRV_INSN_MMULXHS, "mmulxhs", "mmulxhs", 32,
5661     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5662   },
5663 /* mmulxhu$pack $FRinti,$FRintj,$ACC40Sk */
5664   {
5665     FRV_INSN_MMULXHU, "mmulxhu", "mmulxhu", 32,
5666     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5667   },
5668 /* cmmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5669   {
5670     FRV_INSN_CMMULHS, "cmmulhs", "cmmulhs", 32,
5671     { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5672   },
5673 /* cmmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5674   {
5675     FRV_INSN_CMMULHU, "cmmulhu", "cmmulhu", 32,
5676     { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5677   },
5678 /* mqmulhs$pack $FRinti,$FRintj,$ACC40Sk */
5679   {
5680     FRV_INSN_MQMULHS, "mqmulhs", "mqmulhs", 32,
5681     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5682   },
5683 /* mqmulhu$pack $FRinti,$FRintj,$ACC40Sk */
5684   {
5685     FRV_INSN_MQMULHU, "mqmulhu", "mqmulhu", 32,
5686     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5687   },
5688 /* mqmulxhs$pack $FRinti,$FRintj,$ACC40Sk */
5689   {
5690     FRV_INSN_MQMULXHS, "mqmulxhs", "mqmulxhs", 32,
5691     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5692   },
5693 /* mqmulxhu$pack $FRinti,$FRintj,$ACC40Sk */
5694   {
5695     FRV_INSN_MQMULXHU, "mqmulxhu", "mqmulxhu", 32,
5696     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5697   },
5698 /* cmqmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5699   {
5700     FRV_INSN_CMQMULHS, "cmqmulhs", "cmqmulhs", 32,
5701     { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5702   },
5703 /* cmqmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5704   {
5705     FRV_INSN_CMQMULHU, "cmqmulhu", "cmqmulhu", 32,
5706     { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5707   },
5708 /* mmachs$pack $FRinti,$FRintj,$ACC40Sk */
5709   {
5710     FRV_INSN_MMACHS, "mmachs", "mmachs", 32,
5711     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5712   },
5713 /* mmachu$pack $FRinti,$FRintj,$ACC40Uk */
5714   {
5715     FRV_INSN_MMACHU, "mmachu", "mmachu", 32,
5716     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5717   },
5718 /* mmrdhs$pack $FRinti,$FRintj,$ACC40Sk */
5719   {
5720     FRV_INSN_MMRDHS, "mmrdhs", "mmrdhs", 32,
5721     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5722   },
5723 /* mmrdhu$pack $FRinti,$FRintj,$ACC40Uk */
5724   {
5725     FRV_INSN_MMRDHU, "mmrdhu", "mmrdhu", 32,
5726     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5727   },
5728 /* cmmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5729   {
5730     FRV_INSN_CMMACHS, "cmmachs", "cmmachs", 32,
5731     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5732   },
5733 /* cmmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */
5734   {
5735     FRV_INSN_CMMACHU, "cmmachu", "cmmachu", 32,
5736     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5737   },
5738 /* mqmachs$pack $FRinti,$FRintj,$ACC40Sk */
5739   {
5740     FRV_INSN_MQMACHS, "mqmachs", "mqmachs", 32,
5741     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5742   },
5743 /* mqmachu$pack $FRinti,$FRintj,$ACC40Uk */
5744   {
5745     FRV_INSN_MQMACHU, "mqmachu", "mqmachu", 32,
5746     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5747   },
5748 /* cmqmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5749   {
5750     FRV_INSN_CMQMACHS, "cmqmachs", "cmqmachs", 32,
5751     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5752   },
5753 /* cmqmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */
5754   {
5755     FRV_INSN_CMQMACHU, "cmqmachu", "cmqmachu", 32,
5756     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5757   },
5758 /* mqxmachs$pack $FRinti,$FRintj,$ACC40Sk */
5759   {
5760     FRV_INSN_MQXMACHS, "mqxmachs", "mqxmachs", 32,
5761     { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5762   },
5763 /* mqxmacxhs$pack $FRinti,$FRintj,$ACC40Sk */
5764   {
5765     FRV_INSN_MQXMACXHS, "mqxmacxhs", "mqxmacxhs", 32,
5766     { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5767   },
5768 /* mqmacxhs$pack $FRinti,$FRintj,$ACC40Sk */
5769   {
5770     FRV_INSN_MQMACXHS, "mqmacxhs", "mqmacxhs", 32,
5771     { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5772   },
5773 /* mcpxrs$pack $FRinti,$FRintj,$ACC40Sk */
5774   {
5775     FRV_INSN_MCPXRS, "mcpxrs", "mcpxrs", 32,
5776     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5777   },
5778 /* mcpxru$pack $FRinti,$FRintj,$ACC40Sk */
5779   {
5780     FRV_INSN_MCPXRU, "mcpxru", "mcpxru", 32,
5781     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5782   },
5783 /* mcpxis$pack $FRinti,$FRintj,$ACC40Sk */
5784   {
5785     FRV_INSN_MCPXIS, "mcpxis", "mcpxis", 32,
5786     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5787   },
5788 /* mcpxiu$pack $FRinti,$FRintj,$ACC40Sk */
5789   {
5790     FRV_INSN_MCPXIU, "mcpxiu", "mcpxiu", 32,
5791     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5792   },
5793 /* cmcpxrs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5794   {
5795     FRV_INSN_CMCPXRS, "cmcpxrs", "cmcpxrs", 32,
5796     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5797   },
5798 /* cmcpxru$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5799   {
5800     FRV_INSN_CMCPXRU, "cmcpxru", "cmcpxru", 32,
5801     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5802   },
5803 /* cmcpxis$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5804   {
5805     FRV_INSN_CMCPXIS, "cmcpxis", "cmcpxis", 32,
5806     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5807   },
5808 /* cmcpxiu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5809   {
5810     FRV_INSN_CMCPXIU, "cmcpxiu", "cmcpxiu", 32,
5811     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5812   },
5813 /* mqcpxrs$pack $FRinti,$FRintj,$ACC40Sk */
5814   {
5815     FRV_INSN_MQCPXRS, "mqcpxrs", "mqcpxrs", 32,
5816     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5817   },
5818 /* mqcpxru$pack $FRinti,$FRintj,$ACC40Sk */
5819   {
5820     FRV_INSN_MQCPXRU, "mqcpxru", "mqcpxru", 32,
5821     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5822   },
5823 /* mqcpxis$pack $FRinti,$FRintj,$ACC40Sk */
5824   {
5825     FRV_INSN_MQCPXIS, "mqcpxis", "mqcpxis", 32,
5826     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5827   },
5828 /* mqcpxiu$pack $FRinti,$FRintj,$ACC40Sk */
5829   {
5830     FRV_INSN_MQCPXIU, "mqcpxiu", "mqcpxiu", 32,
5831     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5832   },
5833 /* mexpdhw$pack $FRinti,$u6,$FRintk */
5834   {
5835     FRV_INSN_MEXPDHW, "mexpdhw", "mexpdhw", 32,
5836     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5837   },
5838 /* cmexpdhw$pack $FRinti,$u6,$FRintk,$CCi,$cond */
5839   {
5840     FRV_INSN_CMEXPDHW, "cmexpdhw", "cmexpdhw", 32,
5841     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5842   },
5843 /* mexpdhd$pack $FRinti,$u6,$FRintk */
5844   {
5845     FRV_INSN_MEXPDHD, "mexpdhd", "mexpdhd", 32,
5846     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5847   },
5848 /* cmexpdhd$pack $FRinti,$u6,$FRintk,$CCi,$cond */
5849   {
5850     FRV_INSN_CMEXPDHD, "cmexpdhd", "cmexpdhd", 32,
5851     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5852   },
5853 /* mpackh$pack $FRinti,$FRintj,$FRintk */
5854   {
5855     FRV_INSN_MPACKH, "mpackh", "mpackh", 32,
5856     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5857   },
5858 /* mdpackh$pack $FRinti,$FRintj,$FRintk */
5859   {
5860     FRV_INSN_MDPACKH, "mdpackh", "mdpackh", 32,
5861     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_5 } }
5862   },
5863 /* munpackh$pack $FRinti,$FRintk */
5864   {
5865     FRV_INSN_MUNPACKH, "munpackh", "munpackh", 32,
5866     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5867   },
5868 /* mdunpackh$pack $FRinti,$FRintk */
5869   {
5870     FRV_INSN_MDUNPACKH, "mdunpackh", "mdunpackh", 32,
5871     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7 } }
5872   },
5873 /* mbtoh$pack $FRintj,$FRintk */
5874   {
5875     FRV_INSN_MBTOH, "mbtoh", "mbtoh", 32,
5876     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5877   },
5878 /* cmbtoh$pack $FRintj,$FRintk,$CCi,$cond */
5879   {
5880     FRV_INSN_CMBTOH, "cmbtoh", "cmbtoh", 32,
5881     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5882   },
5883 /* mhtob$pack $FRintj,$FRintk */
5884   {
5885     FRV_INSN_MHTOB, "mhtob", "mhtob", 32,
5886     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5887   },
5888 /* cmhtob$pack $FRintj,$FRintk,$CCi,$cond */
5889   {
5890     FRV_INSN_CMHTOB, "cmhtob", "cmhtob", 32,
5891     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5892   },
5893 /* mbtohe$pack $FRintj,$FRintk */
5894   {
5895     FRV_INSN_MBTOHE, "mbtohe", "mbtohe", 32,
5896     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7 } }
5897   },
5898 /* cmbtohe$pack $FRintj,$FRintk,$CCi,$cond */
5899   {
5900     FRV_INSN_CMBTOHE, "cmbtohe", "cmbtohe", 32,
5901     { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7 } }
5902   },
5903 /* mclracc$pack $ACC40Sk,$A */
5904   {
5905     FRV_INSN_MCLRACC, "mclracc", "mclracc", 32,
5906     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_3 } }
5907   },
5908 /* mrdacc$pack $ACC40Si,$FRintk */
5909   {
5910     FRV_INSN_MRDACC, "mrdacc", "mrdacc", 32,
5911     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5912   },
5913 /* mrdaccg$pack $ACCGi,$FRintk */
5914   {
5915     FRV_INSN_MRDACCG, "mrdaccg", "mrdaccg", 32,
5916     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5917   },
5918 /* mwtacc$pack $FRinti,$ACC40Sk */
5919   {
5920     FRV_INSN_MWTACC, "mwtacc", "mwtacc", 32,
5921     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_3 } }
5922   },
5923 /* mwtaccg$pack $FRinti,$ACCGk */
5924   {
5925     FRV_INSN_MWTACCG, "mwtaccg", "mwtaccg", 32,
5926     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_3 } }
5927   },
5928 /* mcop1$pack $FRi,$FRj,$FRk */
5929   {
5930     FRV_INSN_MCOP1, "mcop1", "mcop1", 32,
5931     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_1 } }
5932   },
5933 /* mcop2$pack $FRi,$FRj,$FRk */
5934   {
5935     FRV_INSN_MCOP2, "mcop2", "mcop2", 32,
5936     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_1 } }
5937   },
5938 /* fnop$pack */
5939   {
5940     FRV_INSN_FNOP, "fnop", "fnop", 32,
5941     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_8 } }
5942   },
5943 };
5944
5945 #undef OP
5946 #undef A
5947
5948 /* Initialize anything needed to be done once, before any cpu_open call.  */
5949 static void init_tables PARAMS ((void));
5950
5951 static void
5952 init_tables ()
5953 {
5954 }
5955
5956 static const CGEN_MACH * lookup_mach_via_bfd_name
5957   PARAMS ((const CGEN_MACH *, const char *));
5958 static void build_hw_table  PARAMS ((CGEN_CPU_TABLE *));
5959 static void build_ifield_table  PARAMS ((CGEN_CPU_TABLE *));
5960 static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
5961 static void build_insn_table    PARAMS ((CGEN_CPU_TABLE *));
5962 static void frv_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
5963
5964 /* Subroutine of frv_cgen_cpu_open to look up a mach via its bfd name.  */
5965
5966 static const CGEN_MACH *
5967 lookup_mach_via_bfd_name (table, name)
5968      const CGEN_MACH *table;
5969      const char *name;
5970 {
5971   while (table->name)
5972     {
5973       if (strcmp (name, table->bfd_name) == 0)
5974         return table;
5975       ++table;
5976     }
5977   abort ();
5978 }
5979
5980 /* Subroutine of frv_cgen_cpu_open to build the hardware table.  */
5981
5982 static void
5983 build_hw_table (cd)
5984      CGEN_CPU_TABLE *cd;
5985 {
5986   int i;
5987   int machs = cd->machs;
5988   const CGEN_HW_ENTRY *init = & frv_cgen_hw_table[0];
5989   /* MAX_HW is only an upper bound on the number of selected entries.
5990      However each entry is indexed by it's enum so there can be holes in
5991      the table.  */
5992   const CGEN_HW_ENTRY **selected =
5993     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
5994
5995   cd->hw_table.init_entries = init;
5996   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
5997   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
5998   /* ??? For now we just use machs to determine which ones we want.  */
5999   for (i = 0; init[i].name != NULL; ++i)
6000     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
6001         & machs)
6002       selected[init[i].type] = &init[i];
6003   cd->hw_table.entries = selected;
6004   cd->hw_table.num_entries = MAX_HW;
6005 }
6006
6007 /* Subroutine of frv_cgen_cpu_open to build the hardware table.  */
6008
6009 static void
6010 build_ifield_table (cd)
6011      CGEN_CPU_TABLE *cd;
6012 {
6013   cd->ifld_table = & frv_cgen_ifld_table[0];
6014 }
6015
6016 /* Subroutine of frv_cgen_cpu_open to build the hardware table.  */
6017
6018 static void
6019 build_operand_table (cd)
6020      CGEN_CPU_TABLE *cd;
6021 {
6022   int i;
6023   int machs = cd->machs;
6024   const CGEN_OPERAND *init = & frv_cgen_operand_table[0];
6025   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
6026      However each entry is indexed by it's enum so there can be holes in
6027      the table.  */
6028   const CGEN_OPERAND **selected =
6029     (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
6030
6031   cd->operand_table.init_entries = init;
6032   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
6033   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
6034   /* ??? For now we just use mach to determine which ones we want.  */
6035   for (i = 0; init[i].name != NULL; ++i)
6036     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
6037         & machs)
6038       selected[init[i].type] = &init[i];
6039   cd->operand_table.entries = selected;
6040   cd->operand_table.num_entries = MAX_OPERANDS;
6041 }
6042
6043 /* Subroutine of frv_cgen_cpu_open to build the hardware table.
6044    ??? This could leave out insns not supported by the specified mach/isa,
6045    but that would cause errors like "foo only supported by bar" to become
6046    "unknown insn", so for now we include all insns and require the app to
6047    do the checking later.
6048    ??? On the other hand, parsing of such insns may require their hardware or
6049    operand elements to be in the table [which they mightn't be].  */
6050
6051 static void
6052 build_insn_table (cd)
6053      CGEN_CPU_TABLE *cd;
6054 {
6055   int i;
6056   const CGEN_IBASE *ib = & frv_cgen_insn_table[0];
6057   CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
6058
6059   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
6060   for (i = 0; i < MAX_INSNS; ++i)
6061     insns[i].base = &ib[i];
6062   cd->insn_table.init_entries = insns;
6063   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
6064   cd->insn_table.num_init_entries = MAX_INSNS;
6065 }
6066
6067 /* Subroutine of frv_cgen_cpu_open to rebuild the tables.  */
6068
6069 static void
6070 frv_cgen_rebuild_tables (cd)
6071      CGEN_CPU_TABLE *cd;
6072 {
6073   int i;
6074   unsigned int isas = cd->isas;
6075   unsigned int machs = cd->machs;
6076
6077   cd->int_insn_p = CGEN_INT_INSN_P;
6078
6079   /* Data derived from the isa spec.  */
6080 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
6081   cd->default_insn_bitsize = UNSET;
6082   cd->base_insn_bitsize = UNSET;
6083   cd->min_insn_bitsize = 65535; /* some ridiculously big number */
6084   cd->max_insn_bitsize = 0;
6085   for (i = 0; i < MAX_ISAS; ++i)
6086     if (((1 << i) & isas) != 0)
6087       {
6088         const CGEN_ISA *isa = & frv_cgen_isa_table[i];
6089
6090         /* Default insn sizes of all selected isas must be
6091            equal or we set the result to 0, meaning "unknown".  */
6092         if (cd->default_insn_bitsize == UNSET)
6093           cd->default_insn_bitsize = isa->default_insn_bitsize;
6094         else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
6095           ; /* this is ok */
6096         else
6097           cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
6098
6099         /* Base insn sizes of all selected isas must be equal
6100            or we set the result to 0, meaning "unknown".  */
6101         if (cd->base_insn_bitsize == UNSET)
6102           cd->base_insn_bitsize = isa->base_insn_bitsize;
6103         else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
6104           ; /* this is ok */
6105         else
6106           cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
6107
6108         /* Set min,max insn sizes.  */
6109         if (isa->min_insn_bitsize < cd->min_insn_bitsize)
6110           cd->min_insn_bitsize = isa->min_insn_bitsize;
6111         if (isa->max_insn_bitsize > cd->max_insn_bitsize)
6112           cd->max_insn_bitsize = isa->max_insn_bitsize;
6113       }
6114
6115   /* Data derived from the mach spec.  */
6116   for (i = 0; i < MAX_MACHS; ++i)
6117     if (((1 << i) & machs) != 0)
6118       {
6119         const CGEN_MACH *mach = & frv_cgen_mach_table[i];
6120
6121         if (mach->insn_chunk_bitsize != 0)
6122         {
6123           if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
6124             {
6125               fprintf (stderr, "frv_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
6126                        cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
6127               abort ();
6128             }
6129
6130           cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
6131         }
6132       }
6133
6134   /* Determine which hw elements are used by MACH.  */
6135   build_hw_table (cd);
6136
6137   /* Build the ifield table.  */
6138   build_ifield_table (cd);
6139
6140   /* Determine which operands are used by MACH/ISA.  */
6141   build_operand_table (cd);
6142
6143   /* Build the instruction table.  */
6144   build_insn_table (cd);
6145 }
6146
6147 /* Initialize a cpu table and return a descriptor.
6148    It's much like opening a file, and must be the first function called.
6149    The arguments are a set of (type/value) pairs, terminated with
6150    CGEN_CPU_OPEN_END.
6151
6152    Currently supported values:
6153    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
6154    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
6155    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
6156    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
6157    CGEN_CPU_OPEN_END:     terminates arguments
6158
6159    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
6160    precluded.
6161
6162    ??? We only support ISO C stdargs here, not K&R.
6163    Laziness, plus experiment to see if anything requires K&R - eventually
6164    K&R will no longer be supported - e.g. GDB is currently trying this.  */
6165
6166 CGEN_CPU_DESC
6167 frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
6168 {
6169   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
6170   static int init_p;
6171   unsigned int isas = 0;  /* 0 = "unspecified" */
6172   unsigned int machs = 0; /* 0 = "unspecified" */
6173   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
6174   va_list ap;
6175
6176   if (! init_p)
6177     {
6178       init_tables ();
6179       init_p = 1;
6180     }
6181
6182   memset (cd, 0, sizeof (*cd));
6183
6184   va_start (ap, arg_type);
6185   while (arg_type != CGEN_CPU_OPEN_END)
6186     {
6187       switch (arg_type)
6188         {
6189         case CGEN_CPU_OPEN_ISAS :
6190           isas = va_arg (ap, unsigned int);
6191           break;
6192         case CGEN_CPU_OPEN_MACHS :
6193           machs = va_arg (ap, unsigned int);
6194           break;
6195         case CGEN_CPU_OPEN_BFDMACH :
6196           {
6197             const char *name = va_arg (ap, const char *);
6198             const CGEN_MACH *mach =
6199               lookup_mach_via_bfd_name (frv_cgen_mach_table, name);
6200
6201             machs |= 1 << mach->num;
6202             break;
6203           }
6204         case CGEN_CPU_OPEN_ENDIAN :
6205           endian = va_arg (ap, enum cgen_endian);
6206           break;
6207         default :
6208           fprintf (stderr, "frv_cgen_cpu_open: unsupported argument `%d'\n",
6209                    arg_type);
6210           abort (); /* ??? return NULL? */
6211         }
6212       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
6213     }
6214   va_end (ap);
6215
6216   /* mach unspecified means "all" */
6217   if (machs == 0)
6218     machs = (1 << MAX_MACHS) - 1;
6219   /* base mach is always selected */
6220   machs |= 1;
6221   /* isa unspecified means "all" */
6222   if (isas == 0)
6223     isas = (1 << MAX_ISAS) - 1;
6224   if (endian == CGEN_ENDIAN_UNKNOWN)
6225     {
6226       /* ??? If target has only one, could have a default.  */
6227       fprintf (stderr, "frv_cgen_cpu_open: no endianness specified\n");
6228       abort ();
6229     }
6230
6231   cd->isas = isas;
6232   cd->machs = machs;
6233   cd->endian = endian;
6234   /* FIXME: for the sparc case we can determine insn-endianness statically.
6235      The worry here is where both data and insn endian can be independently
6236      chosen, in which case this function will need another argument.
6237      Actually, will want to allow for more arguments in the future anyway.  */
6238   cd->insn_endian = endian;
6239
6240   /* Table (re)builder.  */
6241   cd->rebuild_tables = frv_cgen_rebuild_tables;
6242   frv_cgen_rebuild_tables (cd);
6243
6244   /* Default to not allowing signed overflow.  */
6245   cd->signed_overflow_ok_p = 0;
6246
6247   return (CGEN_CPU_DESC) cd;
6248 }
6249
6250 /* Cover fn to frv_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
6251    MACH_NAME is the bfd name of the mach.  */
6252
6253 CGEN_CPU_DESC
6254 frv_cgen_cpu_open_1 (mach_name, endian)
6255      const char *mach_name;
6256      enum cgen_endian endian;
6257 {
6258   return frv_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
6259                                CGEN_CPU_OPEN_ENDIAN, endian,
6260                                CGEN_CPU_OPEN_END);
6261 }
6262
6263 /* Close a cpu table.
6264    ??? This can live in a machine independent file, but there's currently
6265    no place to put this file (there's no libcgen).  libopcodes is the wrong
6266    place as some simulator ports use this but they don't use libopcodes.  */
6267
6268 void
6269 frv_cgen_cpu_close (cd)
6270      CGEN_CPU_DESC cd;
6271 {
6272   unsigned int i;
6273   CGEN_INSN *insns;
6274
6275   if (cd->macro_insn_table.init_entries)
6276     {
6277       insns = cd->macro_insn_table.init_entries;
6278       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
6279         {
6280           if (CGEN_INSN_RX ((insns)))
6281             regfree(CGEN_INSN_RX (insns));
6282         }
6283     }
6284
6285   if (cd->insn_table.init_entries)
6286     {
6287       insns = cd->insn_table.init_entries;
6288       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
6289         {
6290           if (CGEN_INSN_RX (insns))
6291             regfree(CGEN_INSN_RX (insns));
6292         }
6293     }
6294
6295
6296
6297   if (cd->macro_insn_table.init_entries)
6298     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
6299
6300   if (cd->insn_table.init_entries)
6301     free ((CGEN_INSN *) cd->insn_table.init_entries);
6302
6303   if (cd->hw_table.entries)
6304     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
6305
6306   if (cd->operand_table.entries)
6307     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
6308
6309   free (cd);
6310 }
6311