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merge from gcc
[binutils.git] / include / opcode / hppa.h
blob8114c6714d8f33537ec6f598efa2e4e2ad1d52da
1 /* Table of opcodes for the PA-RISC.
2 Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005
4 Free Software Foundation, Inc.
5
6 Contributed by the Center for Software Science at the
7 University of Utah (pa-gdb-bugs@cs.utah.edu).
8
9 This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
10
11 GAS/GDB is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 1, or (at your option)
14 any later version.
15
16 GAS/GDB is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GAS or GDB; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
24
25 #if !defined(__STDC__) && !defined(const)
26 #define const
27 #endif
28
29 /*
30 * Structure of an opcode table entry.
31 */
32
33 /* There are two kinds of delay slot nullification: normal which is
34 * controled by the nullification bit, and conditional, which depends
35 * on the direction of the branch and its success or failure.
36 *
37 * NONE is unfortunately #defined in the hiux system include files.
38 * #undef it away.
39 */
40 #undef NONE
41 struct pa_opcode
42 {
43 const char *name;
44 unsigned long int match; /* Bits that must be set... */
45 unsigned long int mask; /* ... in these bits. */
46 char *args;
47 enum pa_arch arch;
48 char flags;
49 };
50
51 /* Enable/disable strict syntax checking. When strict syntax checking
52 is not used, out-of-range immediate fields can result in an error,
53 depending on the specific immediate range being matched. An immediate
54 value of zero is also accepted as equivalent to index register 0.
55 As a result, non-strict opcode entries must be ordered from largest
56 to smallest immediate range. */
57 #define FLAG_STRICT 0x1
58
59 /*
60 All hppa opcodes are 32 bits.
61
62 The match component is a mask saying which bits must match a
63 particular opcode in order for an instruction to be an instance
64 of that opcode.
65
66 The args component is a string containing one character for each operand of
67 the instruction. Characters used as a prefix allow any second character to
68 be used without conflicting with the main operand characters.
69
70 Bit positions in this description follow HP usage of lsb = 31,
71 "at" is lsb of field.
72
73 In the args field, the following characters must match exactly:
74
75 '+,() '
76
77 In the args field, the following characters are unused:
78
79 ' " - / 34 6789:; '
80 '@ C M [\] '
81 '` e g } '
82
83 Here are all the characters:
84
85 ' !"#$%&'()*+-,./0123456789:;<=>?'
86 '@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_'
87 '`abcdefghijklmnopqrstuvwxyz{|}~ '
88
89 Kinds of operands:
90 x integer register field at 15.
91 b integer register field at 10.
92 t integer register field at 31.
93 a integer register field at 10 and 15 (for PERMH)
94 5 5 bit immediate at 15.
95 s 2 bit space specifier at 17.
96 S 3 bit space specifier at 18.
97 V 5 bit immediate value at 31
98 i 11 bit immediate value at 31
99 j 14 bit immediate value at 31
100 k 21 bit immediate value at 31
101 l 16 bit immediate value at 31 (wide mode only, unusual encoding).
102 n nullification for branch instructions
103 N nullification for spop and copr instructions
104 w 12 bit branch displacement
105 W 17 bit branch displacement (PC relative)
106 X 22 bit branch displacement (PC relative)
107 z 17 bit branch displacement (just a number, not an address)
108
109 Also these:
110
111 . 2 bit shift amount at 25
112 * 4 bit shift amount at 25
113 p 5 bit shift count at 26 (to support the SHD instruction) encoded as
114 31-p
115 ~ 6 bit shift count at 20,22:26 encoded as 63-~.
116 P 5 bit bit position at 26
117 q 6 bit bit position at 20,22:26
118 T 5 bit field length at 31 (encoded as 32-T)
119 % 6 bit field length at 23,27:31 (variable extract/deposit)
120 | 6 bit field length at 19,27:31 (fixed extract/deposit)
121 A 13 bit immediate at 18 (to support the BREAK instruction)
122 ^ like b, but describes a control register
123 ! sar (cr11) register
124 D 26 bit immediate at 31 (to support the DIAG instruction)
125 $ 9 bit immediate at 28 (to support POPBTS)
126
127 v 3 bit Special Function Unit identifier at 25
128 O 20 bit Special Function Unit operation split between 15 bits at 20
129 and 5 bits at 31
130 o 15 bit Special Function Unit operation at 20
131 2 22 bit Special Function Unit operation split between 17 bits at 20
132 and 5 bits at 31
133 1 15 bit Special Function Unit operation split between 10 bits at 20
134 and 5 bits at 31
135 0 10 bit Special Function Unit operation split between 5 bits at 20
136 and 5 bits at 31
137 u 3 bit coprocessor unit identifier at 25
138 F Source Floating Point Operand Format Completer encoded 2 bits at 20
139 I Source Floating Point Operand Format Completer encoded 1 bits at 20
140 (for 0xe format FP instructions)
141 G Destination Floating Point Operand Format Completer encoded 2 bits at 18
142 H Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub'
143 (very similar to 'F')
144
145 r 5 bit immediate value at 31 (for the break instruction)
146 (very similar to V above, except the value is unsigned instead of
147 low_sign_ext)
148 R 5 bit immediate value at 15 (for the ssm, rsm, probei instructions)
149 (same as r above, except the value is in a different location)
150 U 10 bit immediate value at 15 (for SSM, RSM on pa2.0)
151 Q 5 bit immediate value at 10 (a bit position specified in
152 the bb instruction. It's the same as r above, except the
153 value is in a different location)
154 B 5 bit immediate value at 10 (a bit position specified in
155 the bb instruction. Similar to Q, but 64 bit handling is
156 different.
157 Z %r1 -- implicit target of addil instruction.
158 L ,%r2 completer for new syntax branch
159 { Source format completer for fcnv
160 _ Destination format completer for fcnv
161 h cbit for fcmp
162 = gfx tests for ftest
163 d 14 bit offset for single precision FP long load/store.
164 # 14 bit offset for double precision FP load long/store.
165 J Yet another 14 bit offset for load/store with ma,mb completers.
166 K Yet another 14 bit offset for load/store with ma,mb completers.
167 y 16 bit offset for word aligned load/store (PA2.0 wide).
168 & 16 bit offset for dword aligned load/store (PA2.0 wide).
169 < 16 bit offset for load/store with ma,mb completers (PA2.0 wide).
170 > 16 bit offset for load/store with ma,mb completers (PA2.0 wide).
171 Y %sr0,%r31 -- implicit target of be,l instruction.
172 @ implicit immediate value of 0
173
174 Completer operands all have 'c' as the prefix:
175
176 cx indexed load completer.
177 cX indexed load completer. Like cx, but emits a space after
178 in disassembler.
179 cm short load and store completer.
180 cM short load and store completer. Like cm, but emits a space
181 after in disassembler.
182 cq long load and store completer (like cm, but inserted into a
183 different location in the target instruction).
184 cs store bytes short completer.
185 cA store bytes short completer. Like cs, but emits a space
186 after in disassembler.
187 ce long load/store completer for LDW/STW with a different encoding
188 than the others
189 cc load cache control hint
190 cd load and clear cache control hint
191 cC store cache control hint
192 co ordered access
193
194 cp branch link and push completer
195 cP branch pop completer
196 cl branch link completer
197 cg branch gate completer
198
199 cw read/write completer for PROBE
200 cW wide completer for MFCTL
201 cL local processor completer for cache control
202 cZ System Control Completer (to support LPA, LHA, etc.)
203
204 ci correction completer for DCOR
205 ca add completer
206 cy 32 bit add carry completer
207 cY 64 bit add carry completer
208 cv signed overflow trap completer
209 ct trap on condition completer for ADDI, SUB
210 cT trap on condition completer for UADDCM
211 cb 32 bit borrow completer for SUB
212 cB 64 bit borrow completer for SUB
213
214 ch left/right half completer
215 cH signed/unsigned saturation completer
216 cS signed/unsigned completer at 21
217 cz zero/sign extension completer.
218 c* permutation completer
219
220 Condition operands all have '?' as the prefix:
221
222 ?f Floating point compare conditions (encoded as 5 bits at 31)
223
224 ?a add conditions
225 ?A 64 bit add conditions
226 ?@ add branch conditions followed by nullify
227 ?d non-negated add branch conditions
228 ?D negated add branch conditions
229 ?w wide mode non-negated add branch conditions
230 ?W wide mode negated add branch conditions
231
232 ?s compare/subtract conditions
233 ?S 64 bit compare/subtract conditions
234 ?t non-negated compare and branch conditions
235 ?n 32 bit compare and branch conditions followed by nullify
236 ?N 64 bit compare and branch conditions followed by nullify
237 ?Q 64 bit compare and branch conditions for CMPIB instruction
238
239 ?l logical conditions
240 ?L 64 bit logical conditions
241
242 ?b branch on bit conditions
243 ?B 64 bit branch on bit conditions
244
245 ?x shift/extract/deposit conditions
246 ?X 64 bit shift/extract/deposit conditions
247 ?y shift/extract/deposit conditions followed by nullify for conditional
248 branches
249
250 ?u unit conditions
251 ?U 64 bit unit conditions
252
253 Floating point registers all have 'f' as a prefix:
254
255 ft target register at 31
256 fT target register with L/R halves at 31
257 fa operand 1 register at 10
258 fA operand 1 register with L/R halves at 10
259 fX Same as fA, except prints a space before register during disasm
260 fb operand 2 register at 15
261 fB operand 2 register with L/R halves at 15
262 fC operand 3 register with L/R halves at 16:18,21:23
263 fe Like fT, but encoding is different.
264 fE Same as fe, except prints a space before register during disasm.
265 fx target register at 15 (only for PA 2.0 long format FLDD/FSTD).
266
267 Float registers for fmpyadd and fmpysub:
268
269 fi mult operand 1 register at 10
270 fj mult operand 2 register at 15
271 fk mult target register at 20
272 fl add/sub operand register at 25
273 fm add/sub target register at 31
274
275 */
276
277
278 #if 0
279 /* List of characters not to put a space after. Note that
280 "," is included, as the "spopN" operations use literal
281 commas in their completer sections. */
282 static const char *const completer_chars = ",CcY<>?!@+&U~FfGHINnOoZMadu|/=0123%e$m}";
283 #endif
284
285 /* The order of the opcodes in this table is significant:
286
287 * The assembler requires that all instances of the same mnemonic be
288 consecutive. If they aren't, the assembler will bomb at runtime.
289
290 * The disassembler does not care about the order of the opcodes
291 except in cases where implicit addressing is used.
292
293 Strict syntax (FLAG_STRICT) should be used for pa11 opcodes
294 and later.
295
296 Here are the rules for ordering the opcodes of a mnemonic:
297
298 1) Opcodes with FLAG_STRICT precede opcodes without FLAG_STRICT,
299
300 2) Opcodes with FLAG_STRICT should be ordered as follows:
301 register index opcodes, short immediate opcodes, and finally
302 long immediate opcodes. Where there are opcodes for more
303 than one architecture in any of these groups, the opcodes
304 for the higher architecture should come first,
305
306 3) Where implicit addressing is available for an opcode, the
307 implicit opcode should precede the explicit opcode, and
308
309 4) Opcodes without FLAG_STRICT should be order as follows: long
310 immediate opcodes, short immediate opcodes and finally register
311 index opcodes. */
312
313 static const struct pa_opcode pa_opcodes[] =
314 {
315
316 /* Pseudo-instructions. */
317
318 { "ldi", 0x34000000, 0xffe00000, "l,x", pa20w, 0},/* ldo val(r0),r */
319 { "ldi", 0x34000000, 0xffe0c000, "j,x", pa10, 0},/* ldo val(r0),r */
320
321 { "cmpib", 0xec000000, 0xfc000000, "?Qn5,b,w", pa20, FLAG_STRICT},
322 { "cmpib", 0x84000000, 0xf4000000, "?nn5,b,w", pa10, FLAG_STRICT},
323 { "comib", 0x84000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/
324 /* This entry is for the disassembler only. It will never be used by
325 assembler. */
326 { "comib", 0x8c000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/
327 { "cmpb", 0x9c000000, 0xdc000000, "?Nnx,b,w", pa20, FLAG_STRICT},
328 { "cmpb", 0x80000000, 0xf4000000, "?nnx,b,w", pa10, FLAG_STRICT},
329 { "comb", 0x80000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */
330 /* This entry is for the disassembler only. It will never be used by
331 assembler. */
332 { "comb", 0x88000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */
333 { "addb", 0xa0000000, 0xf4000000, "?Wnx,b,w", pa20w, FLAG_STRICT},
334 { "addb", 0xa0000000, 0xfc000000, "?@nx,b,w", pa10, 0}, /* addb{tf} */
335 /* This entry is for the disassembler only. It will never be used by
336 assembler. */
337 { "addb", 0xa8000000, 0xfc000000, "?@nx,b,w", pa10, 0},
338 { "addib", 0xa4000000, 0xf4000000, "?Wn5,b,w", pa20w, FLAG_STRICT},
339 { "addib", 0xa4000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/
340 /* This entry is for the disassembler only. It will never be used by
341 assembler. */
342 { "addib", 0xac000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/
343 { "nop", 0x08000240, 0xffffffff, "", pa10, 0}, /* or 0,0,0 */
344 { "copy", 0x08000240, 0xffe0ffe0, "x,t", pa10, 0}, /* or r,0,t */
345 { "mtsar", 0x01601840, 0xffe0ffff, "x", pa10, 0}, /* mtctl r,cr11 */
346
347 /* Loads and Stores for integer registers. */
348
349 { "ldd", 0x0c0000c0, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT},
350 { "ldd", 0x0c0000c0, 0xfc0013c0, "cxccx(s,b),t", pa20, FLAG_STRICT},
351 { "ldd", 0x0c0010e0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
352 { "ldd", 0x0c0010e0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},
353 { "ldd", 0x0c0010c0, 0xfc00d3c0, "cmcc5(b),t", pa20, FLAG_STRICT},
354 { "ldd", 0x0c0010c0, 0xfc0013c0, "cmcc5(s,b),t", pa20, FLAG_STRICT},
355 { "ldd", 0x50000000, 0xfc000002, "cq&(b),x", pa20w, FLAG_STRICT},
356 { "ldd", 0x50000000, 0xfc00c002, "cq#(b),x", pa20, FLAG_STRICT},
357 { "ldd", 0x50000000, 0xfc000002, "cq#(s,b),x", pa20, FLAG_STRICT},
358 { "ldw", 0x0c000080, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
359 { "ldw", 0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
360 { "ldw", 0x0c0010a0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
361 { "ldw", 0x0c0010a0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},
362 { "ldw", 0x0c001080, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
363 { "ldw", 0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
364 { "ldw", 0x4c000000, 0xfc000000, "ce<(b),x", pa20w, FLAG_STRICT},
365 { "ldw", 0x5c000004, 0xfc000006, "ce>(b),x", pa20w, FLAG_STRICT},
366 { "ldw", 0x48000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT},
367 { "ldw", 0x5c000004, 0xfc00c006, "ceK(b),x", pa20, FLAG_STRICT},
368 { "ldw", 0x5c000004, 0xfc000006, "ceK(s,b),x", pa20, FLAG_STRICT},
369 { "ldw", 0x4c000000, 0xfc00c000, "ceJ(b),x", pa10, 0},
370 { "ldw", 0x4c000000, 0xfc000000, "ceJ(s,b),x", pa10, 0},
371 { "ldw", 0x48000000, 0xfc00c000, "j(b),x", pa10, 0},
372 { "ldw", 0x48000000, 0xfc000000, "j(s,b),x", pa10, 0},
373 { "ldw", 0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, 0},
374 { "ldw", 0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, 0},
375 { "ldw", 0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, 0},
376 { "ldw", 0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, 0},
377 { "ldh", 0x0c000040, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
378 { "ldh", 0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
379 { "ldh", 0x0c001060, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
380 { "ldh", 0x0c001060, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},
381 { "ldh", 0x0c001040, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
382 { "ldh", 0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
383 { "ldh", 0x44000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT},
384 { "ldh", 0x44000000, 0xfc00c000, "j(b),x", pa10, 0},
385 { "ldh", 0x44000000, 0xfc000000, "j(s,b),x", pa10, 0},
386 { "ldh", 0x0c001040, 0xfc00dfc0, "cM5(b),t", pa10, 0},
387 { "ldh", 0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, 0},
388 { "ldh", 0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, 0},
389 { "ldh", 0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, 0},
390 { "ldb", 0x0c000000, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
391 { "ldb", 0x0c000000, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
392 { "ldb", 0x0c001020, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
393 { "ldb", 0x0c001020, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},
394 { "ldb", 0x0c001000, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
395 { "ldb", 0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
396 { "ldb", 0x40000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT},
397 { "ldb", 0x40000000, 0xfc00c000, "j(b),x", pa10, 0},
398 { "ldb", 0x40000000, 0xfc000000, "j(s,b),x", pa10, 0},
399 { "ldb", 0x0c001000, 0xfc00dfc0, "cM5(b),t", pa10, 0},
400 { "ldb", 0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, 0},
401 { "ldb", 0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, 0},
402 { "ldb", 0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, 0},
403 { "std", 0x0c0012e0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
404 { "std", 0x0c0012e0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},
405 { "std", 0x0c0012c0, 0xfc00d3c0, "cmcCx,V(b)", pa20, FLAG_STRICT},
406 { "std", 0x0c0012c0, 0xfc0013c0, "cmcCx,V(s,b)", pa20, FLAG_STRICT},
407 { "std", 0x70000000, 0xfc000002, "cqx,&(b)", pa20w, FLAG_STRICT},
408 { "std", 0x70000000, 0xfc00c002, "cqx,#(b)", pa20, FLAG_STRICT},
409 { "std", 0x70000000, 0xfc000002, "cqx,#(s,b)", pa20, FLAG_STRICT},
410 { "stw", 0x0c0012a0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
411 { "stw", 0x0c0012a0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},
412 { "stw", 0x0c001280, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
413 { "stw", 0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
414 { "stw", 0x6c000000, 0xfc000000, "cex,<(b)", pa20w, FLAG_STRICT},
415 { "stw", 0x7c000004, 0xfc000006, "cex,>(b)", pa20w, FLAG_STRICT},
416 { "stw", 0x68000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT},
417 { "stw", 0x7c000004, 0xfc00c006, "cex,K(b)", pa20, FLAG_STRICT},
418 { "stw", 0x7c000004, 0xfc000006, "cex,K(s,b)", pa20, FLAG_STRICT},
419 { "stw", 0x6c000000, 0xfc00c000, "cex,J(b)", pa10, 0},
420 { "stw", 0x6c000000, 0xfc000000, "cex,J(s,b)", pa10, 0},
421 { "stw", 0x68000000, 0xfc00c000, "x,j(b)", pa10, 0},
422 { "stw", 0x68000000, 0xfc000000, "x,j(s,b)", pa10, 0},
423 { "stw", 0x0c001280, 0xfc00dfc0, "cMx,V(b)", pa10, 0},
424 { "stw", 0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, 0},
425 { "sth", 0x0c001260, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
426 { "sth", 0x0c001260, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},
427 { "sth", 0x0c001240, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
428 { "sth", 0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
429 { "sth", 0x64000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT},
430 { "sth", 0x64000000, 0xfc00c000, "x,j(b)", pa10, 0},
431 { "sth", 0x64000000, 0xfc000000, "x,j(s,b)", pa10, 0},
432 { "sth", 0x0c001240, 0xfc00dfc0, "cMx,V(b)", pa10, 0},
433 { "sth", 0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, 0},
434 { "stb", 0x0c001220, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
435 { "stb", 0x0c001220, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},
436 { "stb", 0x0c001200, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
437 { "stb", 0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
438 { "stb", 0x60000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT},
439 { "stb", 0x60000000, 0xfc00c000, "x,j(b)", pa10, 0},
440 { "stb", 0x60000000, 0xfc000000, "x,j(s,b)", pa10, 0},
441 { "stb", 0x0c001200, 0xfc00dfc0, "cMx,V(b)", pa10, 0},
442 { "stb", 0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, 0},
443 { "ldwm", 0x4c000000, 0xfc00c000, "j(b),x", pa10, 0},
444 { "ldwm", 0x4c000000, 0xfc000000, "j(s,b),x", pa10, 0},
445 { "stwm", 0x6c000000, 0xfc00c000, "x,j(b)", pa10, 0},
446 { "stwm", 0x6c000000, 0xfc000000, "x,j(s,b)", pa10, 0},
447 { "ldwx", 0x0c000080, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
448 { "ldwx", 0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
449 { "ldwx", 0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, 0},
450 { "ldwx", 0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, 0},
451 { "ldhx", 0x0c000040, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
452 { "ldhx", 0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
453 { "ldhx", 0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, 0},
454 { "ldhx", 0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, 0},
455 { "ldbx", 0x0c000000, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
456 { "ldbx", 0x0c000000, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
457 { "ldbx", 0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, 0},
458 { "ldbx", 0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, 0},
459 { "ldwa", 0x0c000180, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
460 { "ldwa", 0x0c0011a0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
461 { "ldwa", 0x0c001180, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
462 { "ldwa", 0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, 0},
463 { "ldwa", 0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, 0},
464 { "ldcw", 0x0c0001c0, 0xfc00d3c0, "cxcdx(b),t", pa11, FLAG_STRICT},
465 { "ldcw", 0x0c0001c0, 0xfc0013c0, "cxcdx(s,b),t", pa11, FLAG_STRICT},
466 { "ldcw", 0x0c0011c0, 0xfc00d3c0, "cmcd5(b),t", pa11, FLAG_STRICT},
467 { "ldcw", 0x0c0011c0, 0xfc0013c0, "cmcd5(s,b),t", pa11, FLAG_STRICT},
468 { "ldcw", 0x0c0011c0, 0xfc00dfc0, "cM5(b),t", pa10, 0},
469 { "ldcw", 0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, 0},
470 { "ldcw", 0x0c0001c0, 0xfc00dfc0, "cXx(b),t", pa10, 0},
471 { "ldcw", 0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, 0},
472 { "stwa", 0x0c0013a0, 0xfc00d3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
473 { "stwa", 0x0c001380, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
474 { "stwa", 0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, 0},
475 { "stby", 0x0c001300, 0xfc00d3c0, "cscCx,V(b)", pa11, FLAG_STRICT},
476 { "stby", 0x0c001300, 0xfc0013c0, "cscCx,V(s,b)", pa11, FLAG_STRICT},
477 { "stby", 0x0c001300, 0xfc00dfc0, "cAx,V(b)", pa10, 0},
478 { "stby", 0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, 0},
479 { "ldda", 0x0c000100, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT},
480 { "ldda", 0x0c001120, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
481 { "ldda", 0x0c001100, 0xfc00d3c0, "cmcc5(b),t", pa20, FLAG_STRICT},
482 { "ldcd", 0x0c000140, 0xfc00d3c0, "cxcdx(b),t", pa20, FLAG_STRICT},
483 { "ldcd", 0x0c000140, 0xfc0013c0, "cxcdx(s,b),t", pa20, FLAG_STRICT},
484 { "ldcd", 0x0c001140, 0xfc00d3c0, "cmcd5(b),t", pa20, FLAG_STRICT},
485 { "ldcd", 0x0c001140, 0xfc0013c0, "cmcd5(s,b),t", pa20, FLAG_STRICT},
486 { "stda", 0x0c0013e0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
487 { "stda", 0x0c0013c0, 0xfc00d3c0, "cmcCx,V(b)", pa20, FLAG_STRICT},
488 { "ldwax", 0x0c000180, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
489 { "ldwax", 0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, 0},
490 { "ldcwx", 0x0c0001c0, 0xfc00d3c0, "cxcdx(b),t", pa11, FLAG_STRICT},
491 { "ldcwx", 0x0c0001c0, 0xfc0013c0, "cxcdx(s,b),t", pa11, FLAG_STRICT},
492 { "ldcwx", 0x0c0001c0, 0xfc00dfc0, "cXx(b),t", pa10, 0},
493 { "ldcwx", 0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, 0},
494 { "ldws", 0x0c001080, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
495 { "ldws", 0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
496 { "ldws", 0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, 0},
497 { "ldws", 0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, 0},
498 { "ldhs", 0x0c001040, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
499 { "ldhs", 0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
500 { "ldhs", 0x0c001040, 0xfc00dfc0, "cM5(b),t", pa10, 0},
501 { "ldhs", 0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, 0},
502 { "ldbs", 0x0c001000, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
503 { "ldbs", 0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
504 { "ldbs", 0x0c001000, 0xfc00dfc0, "cM5(b),t", pa10, 0},
505 { "ldbs", 0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, 0},
506 { "ldwas", 0x0c001180, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
507 { "ldwas", 0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, 0},
508 { "ldcws", 0x0c0011c0, 0xfc00d3c0, "cmcd5(b),t", pa11, FLAG_STRICT},
509 { "ldcws", 0x0c0011c0, 0xfc0013c0, "cmcd5(s,b),t", pa11, FLAG_STRICT},
510 { "ldcws", 0x0c0011c0, 0xfc00dfc0, "cM5(b),t", pa10, 0},
511 { "ldcws", 0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, 0},
512 { "stws", 0x0c001280, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
513 { "stws", 0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
514 { "stws", 0x0c001280, 0xfc00dfc0, "cMx,V(b)", pa10, 0},
515 { "stws", 0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, 0},
516 { "sths", 0x0c001240, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
517 { "sths", 0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
518 { "sths", 0x0c001240, 0xfc00dfc0, "cMx,V(b)", pa10, 0},
519 { "sths", 0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, 0},
520 { "stbs", 0x0c001200, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
521 { "stbs", 0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
522 { "stbs", 0x0c001200, 0xfc00dfc0, "cMx,V(b)", pa10, 0},
523 { "stbs", 0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, 0},
524 { "stwas", 0x0c001380, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
525 { "stwas", 0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, 0},
526 { "stdby", 0x0c001340, 0xfc00d3c0, "cscCx,V(b)", pa20, FLAG_STRICT},
527 { "stdby", 0x0c001340, 0xfc0013c0, "cscCx,V(s,b)", pa20, FLAG_STRICT},
528 { "stbys", 0x0c001300, 0xfc00d3c0, "cscCx,V(b)", pa11, FLAG_STRICT},
529 { "stbys", 0x0c001300, 0xfc0013c0, "cscCx,V(s,b)", pa11, FLAG_STRICT},
530 { "stbys", 0x0c001300, 0xfc00dfc0, "cAx,V(b)", pa10, 0},
531 { "stbys", 0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, 0},
532
533 /* Immediate instructions. */
534 { "ldo", 0x34000000, 0xfc000000, "l(b),x", pa20w, 0},
535 { "ldo", 0x34000000, 0xfc00c000, "j(b),x", pa10, 0},
536 { "ldil", 0x20000000, 0xfc000000, "k,b", pa10, 0},
537 { "addil", 0x28000000, 0xfc000000, "k,b,Z", pa10, 0},
538 { "addil", 0x28000000, 0xfc000000, "k,b", pa10, 0},
539
540 /* Branching instructions. */
541 { "b", 0xe8008000, 0xfc00e000, "cpnXL", pa20, FLAG_STRICT},
542 { "b", 0xe800a000, 0xfc00e000, "clnXL", pa20, FLAG_STRICT},
543 { "b", 0xe8000000, 0xfc00e000, "clnW,b", pa10, FLAG_STRICT},
544 { "b", 0xe8002000, 0xfc00e000, "cgnW,b", pa10, FLAG_STRICT},
545 { "b", 0xe8000000, 0xffe0e000, "nW", pa10, 0}, /* b,l foo,r0 */
546 { "bl", 0xe8000000, 0xfc00e000, "nW,b", pa10, 0},
547 { "gate", 0xe8002000, 0xfc00e000, "nW,b", pa10, 0},
548 { "blr", 0xe8004000, 0xfc00e001, "nx,b", pa10, 0},
549 { "bv", 0xe800c000, 0xfc00fffd, "nx(b)", pa10, 0},
550 { "bv", 0xe800c000, 0xfc00fffd, "n(b)", pa10, 0},
551 { "bve", 0xe800f001, 0xfc1ffffd, "cpn(b)L", pa20, FLAG_STRICT},
552 { "bve", 0xe800f000, 0xfc1ffffd, "cln(b)L", pa20, FLAG_STRICT},
553 { "bve", 0xe800d001, 0xfc1ffffd, "cPn(b)", pa20, FLAG_STRICT},
554 { "bve", 0xe800d000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT},
555 { "be", 0xe4000000, 0xfc000000, "clnz(S,b),Y", pa10, FLAG_STRICT},
556 { "be", 0xe4000000, 0xfc000000, "clnz(b),Y", pa10, FLAG_STRICT},
557 { "be", 0xe0000000, 0xfc000000, "nz(S,b)", pa10, 0},
558 { "be", 0xe0000000, 0xfc000000, "nz(b)", pa10, 0},
559 { "ble", 0xe4000000, 0xfc000000, "nz(S,b)", pa10, 0},
560 { "movb", 0xc8000000, 0xfc000000, "?ynx,b,w", pa10, 0},
561 { "movib", 0xcc000000, 0xfc000000, "?yn5,b,w", pa10, 0},
562 { "combt", 0x80000000, 0xfc000000, "?tnx,b,w", pa10, 0},
563 { "combf", 0x88000000, 0xfc000000, "?tnx,b,w", pa10, 0},
564 { "comibt", 0x84000000, 0xfc000000, "?tn5,b,w", pa10, 0},
565 { "comibf", 0x8c000000, 0xfc000000, "?tn5,b,w", pa10, 0},
566 { "addbt", 0xa0000000, 0xfc000000, "?dnx,b,w", pa10, 0},
567 { "addbf", 0xa8000000, 0xfc000000, "?dnx,b,w", pa10, 0},
568 { "addibt", 0xa4000000, 0xfc000000, "?dn5,b,w", pa10, 0},
569 { "addibf", 0xac000000, 0xfc000000, "?dn5,b,w", pa10, 0},
570 { "bb", 0xc0006000, 0xffe06000, "?Bnx,!,w", pa20, FLAG_STRICT},
571 { "bb", 0xc4004000, 0xfc004000, "?Bnx,B,w", pa20, FLAG_STRICT},
572 { "bb", 0xc0004000, 0xffe06000, "?bnx,!,w", pa10, FLAG_STRICT},
573 { "bb", 0xc4004000, 0xfc004000, "?bnx,Q,w", pa10, 0},
574 { "bvb", 0xc0004000, 0xffe04000, "?bnx,w", pa10, 0},
575 { "clrbts", 0xe8004005, 0xffffffff, "", pa20, FLAG_STRICT},
576 { "popbts", 0xe8004005, 0xfffff007, "$", pa20, FLAG_STRICT},
577 { "pushnom", 0xe8004001, 0xffffffff, "", pa20, FLAG_STRICT},
578 { "pushbts", 0xe8004001, 0xffe0ffff, "x", pa20, FLAG_STRICT},
579
580 /* Computation Instructions. */
581
582 { "cmpclr", 0x080008a0, 0xfc000fe0, "?Sx,b,t", pa20, FLAG_STRICT},
583 { "cmpclr", 0x08000880, 0xfc000fe0, "?sx,b,t", pa10, FLAG_STRICT},
584 { "comclr", 0x08000880, 0xfc000fe0, "?sx,b,t", pa10, 0},
585 { "or", 0x08000260, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
586 { "or", 0x08000240, 0xfc000fe0, "?lx,b,t", pa10, 0},
587 { "xor", 0x080002a0, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
588 { "xor", 0x08000280, 0xfc000fe0, "?lx,b,t", pa10, 0},
589 { "and", 0x08000220, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
590 { "and", 0x08000200, 0xfc000fe0, "?lx,b,t", pa10, 0},
591 { "andcm", 0x08000020, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
592 { "andcm", 0x08000000, 0xfc000fe0, "?lx,b,t", pa10, 0},
593 { "uxor", 0x080003a0, 0xfc000fe0, "?Ux,b,t", pa20, FLAG_STRICT},
594 { "uxor", 0x08000380, 0xfc000fe0, "?ux,b,t", pa10, 0},
595 { "uaddcm", 0x080009a0, 0xfc000fa0, "cT?Ux,b,t", pa20, FLAG_STRICT},
596 { "uaddcm", 0x08000980, 0xfc000fa0, "cT?ux,b,t", pa10, FLAG_STRICT},
597 { "uaddcm", 0x08000980, 0xfc000fe0, "?ux,b,t", pa10, 0},
598 { "uaddcmt", 0x080009c0, 0xfc000fe0, "?ux,b,t", pa10, 0},
599 { "dcor", 0x08000ba0, 0xfc1f0fa0, "ci?Ub,t", pa20, FLAG_STRICT},
600 { "dcor", 0x08000b80, 0xfc1f0fa0, "ci?ub,t", pa10, FLAG_STRICT},
601 { "dcor", 0x08000b80, 0xfc1f0fe0, "?ub,t", pa10, 0},
602 { "idcor", 0x08000bc0, 0xfc1f0fe0, "?ub,t", pa10, 0},
603 { "addi", 0xb0000000, 0xfc000000, "ct?ai,b,x", pa10, FLAG_STRICT},
604 { "addi", 0xb4000000, 0xfc000000, "cv?ai,b,x", pa10, FLAG_STRICT},
605 { "addi", 0xb4000000, 0xfc000800, "?ai,b,x", pa10, 0},
606 { "addio", 0xb4000800, 0xfc000800, "?ai,b,x", pa10, 0},
607 { "addit", 0xb0000000, 0xfc000800, "?ai,b,x", pa10, 0},
608 { "addito", 0xb0000800, 0xfc000800, "?ai,b,x", pa10, 0},
609 { "add", 0x08000720, 0xfc0007e0, "cY?Ax,b,t", pa20, FLAG_STRICT},
610 { "add", 0x08000700, 0xfc0007e0, "cy?ax,b,t", pa10, FLAG_STRICT},
611 { "add", 0x08000220, 0xfc0003e0, "ca?Ax,b,t", pa20, FLAG_STRICT},
612 { "add", 0x08000200, 0xfc0003e0, "ca?ax,b,t", pa10, FLAG_STRICT},
613 { "add", 0x08000600, 0xfc000fe0, "?ax,b,t", pa10, 0},
614 { "addl", 0x08000a00, 0xfc000fe0, "?ax,b,t", pa10, 0},
615 { "addo", 0x08000e00, 0xfc000fe0, "?ax,b,t", pa10, 0},
616 { "addc", 0x08000700, 0xfc000fe0, "?ax,b,t", pa10, 0},
617 { "addco", 0x08000f00, 0xfc000fe0, "?ax,b,t", pa10, 0},
618 { "sub", 0x080004e0, 0xfc0007e0, "ct?Sx,b,t", pa20, FLAG_STRICT},
619 { "sub", 0x080004c0, 0xfc0007e0, "ct?sx,b,t", pa10, FLAG_STRICT},
620 { "sub", 0x08000520, 0xfc0007e0, "cB?Sx,b,t", pa20, FLAG_STRICT},
621 { "sub", 0x08000500, 0xfc0007e0, "cb?sx,b,t", pa10, FLAG_STRICT},
622 { "sub", 0x08000420, 0xfc0007e0, "cv?Sx,b,t", pa20, FLAG_STRICT},
623 { "sub", 0x08000400, 0xfc0007e0, "cv?sx,b,t", pa10, FLAG_STRICT},
624 { "sub", 0x08000400, 0xfc000fe0, "?sx,b,t", pa10, 0},
625 { "subo", 0x08000c00, 0xfc000fe0, "?sx,b,t", pa10, 0},
626 { "subb", 0x08000500, 0xfc000fe0, "?sx,b,t", pa10, 0},
627 { "subbo", 0x08000d00, 0xfc000fe0, "?sx,b,t", pa10, 0},
628 { "subt", 0x080004c0, 0xfc000fe0, "?sx,b,t", pa10, 0},
629 { "subto", 0x08000cc0, 0xfc000fe0, "?sx,b,t", pa10, 0},
630 { "ds", 0x08000440, 0xfc000fe0, "?sx,b,t", pa10, 0},
631 { "subi", 0x94000000, 0xfc000000, "cv?si,b,x", pa10, FLAG_STRICT},
632 { "subi", 0x94000000, 0xfc000800, "?si,b,x", pa10, 0},
633 { "subio", 0x94000800, 0xfc000800, "?si,b,x", pa10, 0},
634 { "cmpiclr", 0x90000800, 0xfc000800, "?Si,b,x", pa20, FLAG_STRICT},
635 { "cmpiclr", 0x90000000, 0xfc000800, "?si,b,x", pa10, FLAG_STRICT},
636 { "comiclr", 0x90000000, 0xfc000800, "?si,b,x", pa10, 0},
637 { "shladd", 0x08000220, 0xfc000320, "ca?Ax,.,b,t", pa20, FLAG_STRICT},
638 { "shladd", 0x08000200, 0xfc000320, "ca?ax,.,b,t", pa10, FLAG_STRICT},
639 { "sh1add", 0x08000640, 0xfc000fe0, "?ax,b,t", pa10, 0},
640 { "sh1addl", 0x08000a40, 0xfc000fe0, "?ax,b,t", pa10, 0},
641 { "sh1addo", 0x08000e40, 0xfc000fe0, "?ax,b,t", pa10, 0},
642 { "sh2add", 0x08000680, 0xfc000fe0, "?ax,b,t", pa10, 0},
643 { "sh2addl", 0x08000a80, 0xfc000fe0, "?ax,b,t", pa10, 0},
644 { "sh2addo", 0x08000e80, 0xfc000fe0, "?ax,b,t", pa10, 0},
645 { "sh3add", 0x080006c0, 0xfc000fe0, "?ax,b,t", pa10, 0},
646 { "sh3addl", 0x08000ac0, 0xfc000fe0, "?ax,b,t", pa10, 0},
647 { "sh3addo", 0x08000ec0, 0xfc000fe0, "?ax,b,t", pa10, 0},
648
649 /* Subword Operation Instructions. */
650
651 { "hadd", 0x08000300, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT},
652 { "havg", 0x080002c0, 0xfc00ffe0, "x,b,t", pa20, FLAG_STRICT},
653 { "hshl", 0xf8008800, 0xffe0fc20, "x,*,t", pa20, FLAG_STRICT},
654 { "hshladd", 0x08000700, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT},
655 { "hshr", 0xf800c800, 0xfc1ff820, "cSb,*,t", pa20, FLAG_STRICT},
656 { "hshradd", 0x08000500, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT},
657 { "hsub", 0x08000100, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT},
658 { "mixh", 0xf8008400, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT},
659 { "mixw", 0xf8008000, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT},
660 { "permh", 0xf8000000, 0xfc009020, "c*a,t", pa20, FLAG_STRICT},
661
662
663 /* Extract and Deposit Instructions. */
664
665 { "shrpd", 0xd0000200, 0xfc001fe0, "?Xx,b,!,t", pa20, FLAG_STRICT},
666 { "shrpd", 0xd0000400, 0xfc001400, "?Xx,b,~,t", pa20, FLAG_STRICT},
667 { "shrpw", 0xd0000000, 0xfc001fe0, "?xx,b,!,t", pa10, FLAG_STRICT},
668 { "shrpw", 0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, FLAG_STRICT},
669 { "vshd", 0xd0000000, 0xfc001fe0, "?xx,b,t", pa10, 0},
670 { "shd", 0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, 0},
671 { "extrd", 0xd0001200, 0xfc001ae0, "cS?Xb,!,%,x", pa20, FLAG_STRICT},
672 { "extrd", 0xd8000000, 0xfc000000, "cS?Xb,q,|,x", pa20, FLAG_STRICT},
673 { "extrw", 0xd0001000, 0xfc001be0, "cS?xb,!,T,x", pa10, FLAG_STRICT},
674 { "extrw", 0xd0001800, 0xfc001800, "cS?xb,P,T,x", pa10, FLAG_STRICT},
675 { "vextru", 0xd0001000, 0xfc001fe0, "?xb,T,x", pa10, 0},
676 { "vextrs", 0xd0001400, 0xfc001fe0, "?xb,T,x", pa10, 0},
677 { "extru", 0xd0001800, 0xfc001c00, "?xb,P,T,x", pa10, 0},
678 { "extrs", 0xd0001c00, 0xfc001c00, "?xb,P,T,x", pa10, 0},
679 { "depd", 0xd4000200, 0xfc001ae0, "cz?Xx,!,%,b", pa20, FLAG_STRICT},
680 { "depd", 0xf0000000, 0xfc000000, "cz?Xx,~,|,b", pa20, FLAG_STRICT},
681 { "depdi", 0xd4001200, 0xfc001ae0, "cz?X5,!,%,b", pa20, FLAG_STRICT},
682 { "depdi", 0xf4000000, 0xfc000000, "cz?X5,~,|,b", pa20, FLAG_STRICT},
683 { "depw", 0xd4000000, 0xfc001be0, "cz?xx,!,T,b", pa10, FLAG_STRICT},
684 { "depw", 0xd4000800, 0xfc001800, "cz?xx,p,T,b", pa10, FLAG_STRICT},
685 { "depwi", 0xd4001000, 0xfc001be0, "cz?x5,!,T,b", pa10, FLAG_STRICT},
686 { "depwi", 0xd4001800, 0xfc001800, "cz?x5,p,T,b", pa10, FLAG_STRICT},
687 { "zvdep", 0xd4000000, 0xfc001fe0, "?xx,T,b", pa10, 0},
688 { "vdep", 0xd4000400, 0xfc001fe0, "?xx,T,b", pa10, 0},
689 { "zdep", 0xd4000800, 0xfc001c00, "?xx,p,T,b", pa10, 0},
690 { "dep", 0xd4000c00, 0xfc001c00, "?xx,p,T,b", pa10, 0},
691 { "zvdepi", 0xd4001000, 0xfc001fe0, "?x5,T,b", pa10, 0},
692 { "vdepi", 0xd4001400, 0xfc001fe0, "?x5,T,b", pa10, 0},
693 { "zdepi", 0xd4001800, 0xfc001c00, "?x5,p,T,b", pa10, 0},
694 { "depi", 0xd4001c00, 0xfc001c00, "?x5,p,T,b", pa10, 0},
695
696 /* System Control Instructions. */
697
698 { "break", 0x00000000, 0xfc001fe0, "r,A", pa10, 0},
699 { "rfi", 0x00000c00, 0xffffff1f, "cr", pa10, FLAG_STRICT},
700 { "rfi", 0x00000c00, 0xffffffff, "", pa10, 0},
701 { "rfir", 0x00000ca0, 0xffffffff, "", pa11, 0},
702 { "ssm", 0x00000d60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT},
703 { "ssm", 0x00000d60, 0xffe0ffe0, "R,t", pa10, 0},
704 { "rsm", 0x00000e60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT},
705 { "rsm", 0x00000e60, 0xffe0ffe0, "R,t", pa10, 0},
706 { "mtsm", 0x00001860, 0xffe0ffff, "x", pa10, 0},
707 { "ldsid", 0x000010a0, 0xfc1fffe0, "(b),t", pa10, 0},
708 { "ldsid", 0x000010a0, 0xfc1f3fe0, "(s,b),t", pa10, 0},
709 { "mtsp", 0x00001820, 0xffe01fff, "x,S", pa10, 0},
710 { "mtctl", 0x00001840, 0xfc00ffff, "x,^", pa10, 0},
711 { "mtsarcm", 0x016018C0, 0xffe0ffff, "x", pa20, FLAG_STRICT},
712 { "mfia", 0x000014A0, 0xffffffe0, "t", pa20, FLAG_STRICT},
713 { "mfsp", 0x000004a0, 0xffff1fe0, "S,t", pa10, 0},
714 { "mfctl", 0x016048a0, 0xffffffe0, "cW!,t", pa20, FLAG_STRICT},
715 { "mfctl", 0x000008a0, 0xfc1fffe0, "^,t", pa10, 0},
716 { "sync", 0x00000400, 0xffffffff, "", pa10, 0},
717 { "syncdma", 0x00100400, 0xffffffff, "", pa10, 0},
718 { "probe", 0x04001180, 0xfc00ffa0, "cw(b),x,t", pa10, FLAG_STRICT},
719 { "probe", 0x04001180, 0xfc003fa0, "cw(s,b),x,t", pa10, FLAG_STRICT},
720 { "probei", 0x04003180, 0xfc00ffa0, "cw(b),R,t", pa10, FLAG_STRICT},
721 { "probei", 0x04003180, 0xfc003fa0, "cw(s,b),R,t", pa10, FLAG_STRICT},
722 { "prober", 0x04001180, 0xfc00ffe0, "(b),x,t", pa10, 0},
723 { "prober", 0x04001180, 0xfc003fe0, "(s,b),x,t", pa10, 0},
724 { "proberi", 0x04003180, 0xfc00ffe0, "(b),R,t", pa10, 0},
725 { "proberi", 0x04003180, 0xfc003fe0, "(s,b),R,t", pa10, 0},
726 { "probew", 0x040011c0, 0xfc00ffe0, "(b),x,t", pa10, 0},
727 { "probew", 0x040011c0, 0xfc003fe0, "(s,b),x,t", pa10, 0},
728 { "probewi", 0x040031c0, 0xfc00ffe0, "(b),R,t", pa10, 0},
729 { "probewi", 0x040031c0, 0xfc003fe0, "(s,b),R,t", pa10, 0},
730 { "lpa", 0x04001340, 0xfc00ffc0, "cZx(b),t", pa10, 0},
731 { "lpa", 0x04001340, 0xfc003fc0, "cZx(s,b),t", pa10, 0},
732 { "lha", 0x04001300, 0xfc00ffc0, "cZx(b),t", pa10, 0},
733 { "lha", 0x04001300, 0xfc003fc0, "cZx(s,b),t", pa10, 0},
734 { "lci", 0x04001300, 0xfc00ffe0, "x(b),t", pa10, 0},
735 { "lci", 0x04001300, 0xfc003fe0, "x(s,b),t", pa10, 0},
736 { "pdtlb", 0x04001600, 0xfc00ffdf, "cLcZx(b)", pa20, FLAG_STRICT},
737 { "pdtlb", 0x04001600, 0xfc003fdf, "cLcZx(s,b)", pa20, FLAG_STRICT},
738 { "pdtlb", 0x04001600, 0xfc1fffdf, "cLcZ@(b)", pa20, FLAG_STRICT},
739 { "pdtlb", 0x04001600, 0xfc1f3fdf, "cLcZ@(s,b)", pa20, FLAG_STRICT},
740 { "pdtlb", 0x04001200, 0xfc00ffdf, "cZx(b)", pa10, 0},
741 { "pdtlb", 0x04001200, 0xfc003fdf, "cZx(s,b)", pa10, 0},
742 { "pitlb", 0x04000600, 0xfc001fdf, "cLcZx(S,b)", pa20, FLAG_STRICT},
743 { "pitlb", 0x04000600, 0xfc1f1fdf, "cLcZ@(S,b)", pa20, FLAG_STRICT},
744 { "pitlb", 0x04000200, 0xfc001fdf, "cZx(S,b)", pa10, 0},
745 { "pdtlbe", 0x04001240, 0xfc00ffdf, "cZx(b)", pa10, 0},
746 { "pdtlbe", 0x04001240, 0xfc003fdf, "cZx(s,b)", pa10, 0},
747 { "pitlbe", 0x04000240, 0xfc001fdf, "cZx(S,b)", pa10, 0},
748 { "idtlba", 0x04001040, 0xfc00ffff, "x,(b)", pa10, 0},
749 { "idtlba", 0x04001040, 0xfc003fff, "x,(s,b)", pa10, 0},
750 { "iitlba", 0x04000040, 0xfc001fff, "x,(S,b)", pa10, 0},
751 { "idtlbp", 0x04001000, 0xfc00ffff, "x,(b)", pa10, 0},
752 { "idtlbp", 0x04001000, 0xfc003fff, "x,(s,b)", pa10, 0},
753 { "iitlbp", 0x04000000, 0xfc001fff, "x,(S,b)", pa10, 0},
754 { "pdc", 0x04001380, 0xfc00ffdf, "cZx(b)", pa10, 0},
755 { "pdc", 0x04001380, 0xfc003fdf, "cZx(s,b)", pa10, 0},
756 { "fdc", 0x04001280, 0xfc00ffdf, "cZx(b)", pa10, 0},
757 { "fdc", 0x04001280, 0xfc003fdf, "cZx(s,b)", pa10, 0},
758 { "fic", 0x04000280, 0xfc001fdf, "cZx(S,b)", pa10, 0},
759 { "fdce", 0x040012c0, 0xfc00ffdf, "cZx(b)", pa10, 0},
760 { "fdce", 0x040012c0, 0xfc003fdf, "cZx(s,b)", pa10, 0},
761 { "fice", 0x040002c0, 0xfc001fdf, "cZx(S,b)", pa10, 0},
762 { "diag", 0x14000000, 0xfc000000, "D", pa10, 0},
763 { "idtlbt", 0x04001800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT},
764 { "iitlbt", 0x04000800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT},
765
766 /* These may be specific to certain versions of the PA. Joel claimed
767 they were 72000 (7200?) specific. However, I'm almost certain the
768 mtcpu/mfcpu were undocumented, but available in the older 700 machines. */
769 { "mtcpu", 0x14001600, 0xfc00ffff, "x,^", pa10, 0},
770 { "mfcpu", 0x14001A00, 0xfc00ffff, "^,x", pa10, 0},
771 { "tocen", 0x14403600, 0xffffffff, "", pa10, 0},
772 { "tocdis", 0x14401620, 0xffffffff, "", pa10, 0},
773 { "shdwgr", 0x14402600, 0xffffffff, "", pa10, 0},
774 { "grshdw", 0x14400620, 0xffffffff, "", pa10, 0},
775
776 /* gfw and gfr are not in the HP PA 1.1 manual, but they are in either
777 the Timex FPU or the Mustang ERS (not sure which) manual. */
778 { "gfw", 0x04001680, 0xfc00ffdf, "cZx(b)", pa11, 0},
779 { "gfw", 0x04001680, 0xfc003fdf, "cZx(s,b)", pa11, 0},
780 { "gfr", 0x04001a80, 0xfc00ffdf, "cZx(b)", pa11, 0},
781 { "gfr", 0x04001a80, 0xfc003fdf, "cZx(s,b)", pa11, 0},
782
783 /* Floating Point Coprocessor Instructions. */
784
785 { "fldw", 0x24000000, 0xfc00d380, "cxccx(b),fT", pa11, FLAG_STRICT},
786 { "fldw", 0x24000000, 0xfc001380, "cxccx(s,b),fT", pa11, FLAG_STRICT},
787 { "fldw", 0x24001020, 0xfc1ff3a0, "cocc@(b),fT", pa20, FLAG_STRICT},
788 { "fldw", 0x24001020, 0xfc1f33a0, "cocc@(s,b),fT", pa20, FLAG_STRICT},
789 { "fldw", 0x24001000, 0xfc00d380, "cmcc5(b),fT", pa11, FLAG_STRICT},
790 { "fldw", 0x24001000, 0xfc001380, "cmcc5(s,b),fT", pa11, FLAG_STRICT},
791 { "fldw", 0x5c000000, 0xfc000004, "y(b),fe", pa20w, FLAG_STRICT},
792 { "fldw", 0x58000000, 0xfc000000, "cJy(b),fe", pa20w, FLAG_STRICT},
793 { "fldw", 0x5c000000, 0xfc00c004, "d(b),fe", pa20, FLAG_STRICT},
794 { "fldw", 0x5c000000, 0xfc000004, "d(s,b),fe", pa20, FLAG_STRICT},
795 { "fldw", 0x58000000, 0xfc00c000, "cJd(b),fe", pa20, FLAG_STRICT},
796 { "fldw", 0x58000000, 0xfc000000, "cJd(s,b),fe", pa20, FLAG_STRICT},
797 { "fldw", 0x24001000, 0xfc00df80, "cM5(b),fT", pa10, 0},
798 { "fldw", 0x24001000, 0xfc001f80, "cM5(s,b),fT", pa10, 0},
799 { "fldw", 0x24000000, 0xfc00df80, "cXx(b),fT", pa10, 0},
800 { "fldw", 0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, 0},
801 { "fldd", 0x2c000000, 0xfc00d3c0, "cxccx(b),ft", pa11, FLAG_STRICT},
802 { "fldd", 0x2c000000, 0xfc0013c0, "cxccx(s,b),ft", pa11, FLAG_STRICT},
803 { "fldd", 0x2c001020, 0xfc1ff3e0, "cocc@(b),ft", pa20, FLAG_STRICT},
804 { "fldd", 0x2c001020, 0xfc1f33e0, "cocc@(s,b),ft", pa20, FLAG_STRICT},
805 { "fldd", 0x2c001000, 0xfc00d3c0, "cmcc5(b),ft", pa11, FLAG_STRICT},
806 { "fldd", 0x2c001000, 0xfc0013c0, "cmcc5(s,b),ft", pa11, FLAG_STRICT},
807 { "fldd", 0x50000002, 0xfc000002, "cq&(b),fx", pa20w, FLAG_STRICT},
808 { "fldd", 0x50000002, 0xfc00c002, "cq#(b),fx", pa20, FLAG_STRICT},
809 { "fldd", 0x50000002, 0xfc000002, "cq#(s,b),fx", pa20, FLAG_STRICT},
810 { "fldd", 0x2c001000, 0xfc00dfc0, "cM5(b),ft", pa10, 0},
811 { "fldd", 0x2c001000, 0xfc001fc0, "cM5(s,b),ft", pa10, 0},
812 { "fldd", 0x2c000000, 0xfc00dfc0, "cXx(b),ft", pa10, 0},
813 { "fldd", 0x2c000000, 0xfc001fc0, "cXx(s,b),ft", pa10, 0},
814 { "fstw", 0x24000200, 0xfc00d380, "cxcCfT,x(b)", pa11, FLAG_STRICT},
815 { "fstw", 0x24000200, 0xfc001380, "cxcCfT,x(s,b)", pa11, FLAG_STRICT},
816 { "fstw", 0x24001220, 0xfc1ff3a0, "cocCfT,@(b)", pa20, FLAG_STRICT},
817 { "fstw", 0x24001220, 0xfc1f33a0, "cocCfT,@(s,b)", pa20, FLAG_STRICT},
818 { "fstw", 0x24001200, 0xfc00df80, "cMfT,5(b)", pa10, FLAG_STRICT},
819 { "fstw", 0x24001200, 0xfc001f80, "cMfT,5(s,b)", pa10, FLAG_STRICT},
820 { "fstw", 0x7c000000, 0xfc000004, "fE,y(b)", pa20w, FLAG_STRICT},
821 { "fstw", 0x78000000, 0xfc000000, "cJfE,y(b)", pa20w, FLAG_STRICT},
822 { "fstw", 0x7c000000, 0xfc00c004, "fE,d(b)", pa20, FLAG_STRICT},
823 { "fstw", 0x7c000000, 0xfc000004, "fE,d(s,b)", pa20, FLAG_STRICT},
824 { "fstw", 0x78000000, 0xfc00c000, "cJfE,d(b)", pa20, FLAG_STRICT},
825 { "fstw", 0x78000000, 0xfc000000, "cJfE,d(s,b)", pa20, FLAG_STRICT},
826 { "fstw", 0x24001200, 0xfc00df80, "cMfT,5(b)", pa10, 0},
827 { "fstw", 0x24001200, 0xfc001f80, "cMfT,5(s,b)", pa10, 0},
828 { "fstw", 0x24000200, 0xfc00df80, "cXfT,x(b)", pa10, 0},
829 { "fstw", 0x24000200, 0xfc001f80, "cXfT,x(s,b)", pa10, 0},
830 { "fstd", 0x2c000200, 0xfc00d3c0, "cxcCft,x(b)", pa11, FLAG_STRICT},
831 { "fstd", 0x2c000200, 0xfc0013c0, "cxcCft,x(s,b)", pa11, FLAG_STRICT},
832 { "fstd", 0x2c001220, 0xfc1ff3e0, "cocCft,@(b)", pa20, FLAG_STRICT},
833 { "fstd", 0x2c001220, 0xfc1f33e0, "cocCft,@(s,b)", pa20, FLAG_STRICT},
834 { "fstd", 0x2c001200, 0xfc00d3c0, "cmcCft,5(b)", pa11, FLAG_STRICT},
835 { "fstd", 0x2c001200, 0xfc0013c0, "cmcCft,5(s,b)", pa11, FLAG_STRICT},
836 { "fstd", 0x70000002, 0xfc000002, "cqfx,&(b)", pa20w, FLAG_STRICT},
837 { "fstd", 0x70000002, 0xfc00c002, "cqfx,#(b)", pa20, FLAG_STRICT},
838 { "fstd", 0x70000002, 0xfc000002, "cqfx,#(s,b)", pa20, FLAG_STRICT},
839 { "fstd", 0x2c001200, 0xfc00dfc0, "cMft,5(b)", pa10, 0},
840 { "fstd", 0x2c001200, 0xfc001fc0, "cMft,5(s,b)", pa10, 0},
841 { "fstd", 0x2c000200, 0xfc00dfc0, "cXft,x(b)", pa10, 0},
842 { "fstd", 0x2c000200, 0xfc001fc0, "cXft,x(s,b)", pa10, 0},
843 { "fldwx", 0x24000000, 0xfc00d380, "cxccx(b),fT", pa11, FLAG_STRICT},
844 { "fldwx", 0x24000000, 0xfc001380, "cxccx(s,b),fT", pa11, FLAG_STRICT},
845 { "fldwx", 0x24000000, 0xfc00df80, "cXx(b),fT", pa10, 0},
846 { "fldwx", 0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, 0},
847 { "flddx", 0x2c000000, 0xfc00d3c0, "cxccx(b),ft", pa11, FLAG_STRICT},
848 { "flddx", 0x2c000000, 0xfc0013c0, "cxccx(s,b),ft", pa11, FLAG_STRICT},
849 { "flddx", 0x2c000000, 0xfc00dfc0, "cXx(b),ft", pa10, 0},
850 { "flddx", 0x2c000000, 0xfc001fc0, "cXx(s,b),ft", pa10, 0},
851 { "fstwx", 0x24000200, 0xfc00d380, "cxcCfT,x(b)", pa11, FLAG_STRICT},
852 { "fstwx", 0x24000200, 0xfc001380, "cxcCfT,x(s,b)", pa11, FLAG_STRICT},
853 { "fstwx", 0x24000200, 0xfc00df80, "cxfT,x(b)", pa10, 0},
854 { "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10, 0},
855 { "fstdx", 0x2c000200, 0xfc00d3c0, "cxcCft,x(b)", pa11, FLAG_STRICT},
856 { "fstdx", 0x2c000200, 0xfc0013c0, "cxcCft,x(s,b)", pa11, FLAG_STRICT},
857 { "fstdx", 0x2c000200, 0xfc00dfc0, "cxft,x(b)", pa10, 0},
858 { "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0},
859 { "fstqx", 0x3c000200, 0xfc00dfc0, "cxft,x(b)", pa10, 0},
860 { "fstqx", 0x3c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0},
861 { "fldws", 0x24001000, 0xfc00d380, "cmcc5(b),fT", pa11, FLAG_STRICT},
862 { "fldws", 0x24001000, 0xfc001380, "cmcc5(s,b),fT", pa11, FLAG_STRICT},
863 { "fldws", 0x24001000, 0xfc00df80, "cm5(b),fT", pa10, 0},
864 { "fldws", 0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10, 0},
865 { "fldds", 0x2c001000, 0xfc00d3c0, "cmcc5(b),ft", pa11, FLAG_STRICT},
866 { "fldds", 0x2c001000, 0xfc0013c0, "cmcc5(s,b),ft", pa11, FLAG_STRICT},
867 { "fldds", 0x2c001000, 0xfc00dfc0, "cm5(b),ft", pa10, 0},
868 { "fldds", 0x2c001000, 0xfc001fc0, "cm5(s,b),ft", pa10, 0},
869 { "fstws", 0x24001200, 0xfc00d380, "cmcCfT,5(b)", pa11, FLAG_STRICT},
870 { "fstws", 0x24001200, 0xfc001380, "cmcCfT,5(s,b)", pa11, FLAG_STRICT},
871 { "fstws", 0x24001200, 0xfc00df80, "cmfT,5(b)", pa10, 0},
872 { "fstws", 0x24001200, 0xfc001f80, "cmfT,5(s,b)", pa10, 0},
873 { "fstds", 0x2c001200, 0xfc00d3c0, "cmcCft,5(b)", pa11, FLAG_STRICT},
874 { "fstds", 0x2c001200, 0xfc0013c0, "cmcCft,5(s,b)", pa11, FLAG_STRICT},
875 { "fstds", 0x2c001200, 0xfc00dfc0, "cmft,5(b)", pa10, 0},
876 { "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0},
877 { "fstqs", 0x3c001200, 0xfc00dfc0, "cmft,5(b)", pa10, 0},
878 { "fstqs", 0x3c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0},
879 { "fadd", 0x30000600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
880 { "fadd", 0x38000600, 0xfc00e720, "IfA,fB,fT", pa10, 0},
881 { "fsub", 0x30002600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
882 { "fsub", 0x38002600, 0xfc00e720, "IfA,fB,fT", pa10, 0},
883 { "fmpy", 0x30004600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
884 { "fmpy", 0x38004600, 0xfc00e720, "IfA,fB,fT", pa10, 0},
885 { "fdiv", 0x30006600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
886 { "fdiv", 0x38006600, 0xfc00e720, "IfA,fB,fT", pa10, 0},
887 { "fsqrt", 0x30008000, 0xfc1fe7e0, "Ffa,fT", pa10, 0},
888 { "fsqrt", 0x38008000, 0xfc1fe720, "FfA,fT", pa10, 0},
889 { "fabs", 0x30006000, 0xfc1fe7e0, "Ffa,fT", pa10, 0},
890 { "fabs", 0x38006000, 0xfc1fe720, "FfA,fT", pa10, 0},
891 { "frem", 0x30008600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
892 { "frem", 0x38008600, 0xfc00e720, "FfA,fB,fT", pa10, 0},
893 { "frnd", 0x3000a000, 0xfc1fe7e0, "Ffa,fT", pa10, 0},
894 { "frnd", 0x3800a000, 0xfc1fe720, "FfA,fT", pa10, 0},
895 { "fcpy", 0x30004000, 0xfc1fe7e0, "Ffa,fT", pa10, 0},
896 { "fcpy", 0x38004000, 0xfc1fe720, "FfA,fT", pa10, 0},
897 { "fcnvff", 0x30000200, 0xfc1f87e0, "FGfa,fT", pa10, 0},
898 { "fcnvff", 0x38000200, 0xfc1f8720, "FGfA,fT", pa10, 0},
899 { "fcnvxf", 0x30008200, 0xfc1f87e0, "FGfa,fT", pa10, 0},
900 { "fcnvxf", 0x38008200, 0xfc1f8720, "FGfA,fT", pa10, 0},
901 { "fcnvfx", 0x30010200, 0xfc1f87e0, "FGfa,fT", pa10, 0},
902 { "fcnvfx", 0x38010200, 0xfc1f8720, "FGfA,fT", pa10, 0},
903 { "fcnvfxt", 0x30018200, 0xfc1f87e0, "FGfa,fT", pa10, 0},
904 { "fcnvfxt", 0x38018200, 0xfc1f8720, "FGfA,fT", pa10, 0},
905 { "fmpyfadd", 0xb8000000, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT},
906 { "fmpynfadd", 0xb8000020, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT},
907 { "fneg", 0x3000c000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT},
908 { "fneg", 0x3800c000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT},
909 { "fnegabs", 0x3000e000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT},
910 { "fnegabs", 0x3800e000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT},
911 { "fcnv", 0x30000200, 0xfc1c0720, "{_fa,fT", pa20, FLAG_STRICT},
912 { "fcnv", 0x38000200, 0xfc1c0720, "FGfA,fT", pa20, FLAG_STRICT},
913 { "fcmp", 0x30000400, 0xfc0007e0, "F?ffa,fb,h", pa20, FLAG_STRICT},
914 { "fcmp", 0x38000400, 0xfc000720, "I?ffA,fB,h", pa20, FLAG_STRICT},
915 { "fcmp", 0x30000400, 0xfc00e7e0, "F?ffa,fb", pa10, 0},
916 { "fcmp", 0x38000400, 0xfc00e720, "I?ffA,fB", pa10, 0},
917 { "xmpyu", 0x38004700, 0xfc00e720, "fX,fB,fT", pa11, 0},
918 { "fmpyadd", 0x18000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11, 0},
919 { "fmpysub", 0x98000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11, 0},
920 { "ftest", 0x30002420, 0xffffffe0, ",=", pa20, FLAG_STRICT},
921 { "ftest", 0x30000420, 0xffff1fff, "m", pa20, FLAG_STRICT},
922 { "ftest", 0x30002420, 0xffffffff, "", pa10, 0},
923 { "fid", 0x30000000, 0xffffffff, "", pa11, 0},
924
925 /* Performance Monitor Instructions. */
926
927 { "pmdis", 0x30000280, 0xffffffdf, "N", pa20, FLAG_STRICT},
928 { "pmenb", 0x30000680, 0xffffffff, "", pa20, FLAG_STRICT},
929
930 /* Assist Instructions. */
931
932 { "spop0", 0x10000000, 0xfc000600, "v,ON", pa10, 0},
933 { "spop1", 0x10000200, 0xfc000600, "v,oNt", pa10, 0},
934 { "spop2", 0x10000400, 0xfc000600, "v,1Nb", pa10, 0},
935 { "spop3", 0x10000600, 0xfc000600, "v,0Nx,b", pa10, 0},
936 { "copr", 0x30000000, 0xfc000000, "u,2N", pa10, 0},
937 { "cldw", 0x24000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT},
938 { "cldw", 0x24000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT},
939 { "cldw", 0x24001000, 0xfc00d200, "ucocc@(b),t", pa20, FLAG_STRICT},
940 { "cldw", 0x24001000, 0xfc001200, "ucocc@(s,b),t", pa20, FLAG_STRICT},
941 { "cldw", 0x24001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT},
942 { "cldw", 0x24001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT},
943 { "cldw", 0x24001000, 0xfc00de00, "ucM5(b),t", pa10, 0},
944 { "cldw", 0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0},
945 { "cldw", 0x24000000, 0xfc00de00, "ucXx(b),t", pa10, 0},
946 { "cldw", 0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0},
947 { "cldd", 0x2c000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT},
948 { "cldd", 0x2c000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT},
949 { "cldd", 0x2c001000, 0xfc00d200, "ucocc@(b),t", pa20, FLAG_STRICT},
950 { "cldd", 0x2c001000, 0xfc001200, "ucocc@(s,b),t", pa20, FLAG_STRICT},
951 { "cldd", 0x2c001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT},
952 { "cldd", 0x2c001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT},
953 { "cldd", 0x2c001000, 0xfc00de00, "ucM5(b),t", pa10, 0},
954 { "cldd", 0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0},
955 { "cldd", 0x2c000000, 0xfc00de00, "ucXx(b),t", pa10, 0},
956 { "cldd", 0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0},
957 { "cstw", 0x24000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT},
958 { "cstw", 0x24000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT},
959 { "cstw", 0x24001200, 0xfc00d200, "ucocCt,@(b)", pa20, FLAG_STRICT},
960 { "cstw", 0x24001200, 0xfc001200, "ucocCt,@(s,b)", pa20, FLAG_STRICT},
961 { "cstw", 0x24001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT},
962 { "cstw", 0x24001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT},
963 { "cstw", 0x24001200, 0xfc00de00, "ucMt,5(b)", pa10, 0},
964 { "cstw", 0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0},
965 { "cstw", 0x24000200, 0xfc00de00, "ucXt,x(b)", pa10, 0},
966 { "cstw", 0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0},
967 { "cstd", 0x2c000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT},
968 { "cstd", 0x2c000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT},
969 { "cstd", 0x2c001200, 0xfc00d200, "ucocCt,@(b)", pa20, FLAG_STRICT},
970 { "cstd", 0x2c001200, 0xfc001200, "ucocCt,@(s,b)", pa20, FLAG_STRICT},
971 { "cstd", 0x2c001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT},
972 { "cstd", 0x2c001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT},
973 { "cstd", 0x2c001200, 0xfc00de00, "ucMt,5(b)", pa10, 0},
974 { "cstd", 0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0},
975 { "cstd", 0x2c000200, 0xfc00de00, "ucXt,x(b)", pa10, 0},
976 { "cstd", 0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0},
977 { "cldwx", 0x24000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT},
978 { "cldwx", 0x24000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT},
979 { "cldwx", 0x24000000, 0xfc00de00, "ucXx(b),t", pa10, 0},
980 { "cldwx", 0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0},
981 { "clddx", 0x2c000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT},
982 { "clddx", 0x2c000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT},
983 { "clddx", 0x2c000000, 0xfc00de00, "ucXx(b),t", pa10, 0},
984 { "clddx", 0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0},
985 { "cstwx", 0x24000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT},
986 { "cstwx", 0x24000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT},
987 { "cstwx", 0x24000200, 0xfc00de00, "ucXt,x(b)", pa10, 0},
988 { "cstwx", 0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0},
989 { "cstdx", 0x2c000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT},
990 { "cstdx", 0x2c000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT},
991 { "cstdx", 0x2c000200, 0xfc00de00, "ucXt,x(b)", pa10, 0},
992 { "cstdx", 0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0},
993 { "cldws", 0x24001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT},
994 { "cldws", 0x24001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT},
995 { "cldws", 0x24001000, 0xfc00de00, "ucM5(b),t", pa10, 0},
996 { "cldws", 0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0},
997 { "cldds", 0x2c001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT},
998 { "cldds", 0x2c001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT},
999 { "cldds", 0x2c001000, 0xfc00de00, "ucM5(b),t", pa10, 0},
1000 { "cldds", 0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0},
1001 { "cstws", 0x24001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT},
1002 { "cstws", 0x24001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT},
1003 { "cstws", 0x24001200, 0xfc00de00, "ucMt,5(b)", pa10, 0},
1004 { "cstws", 0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0},
1005 { "cstds", 0x2c001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT},
1006 { "cstds", 0x2c001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT},
1007 { "cstds", 0x2c001200, 0xfc00de00, "ucMt,5(b)", pa10, 0},
1008 { "cstds", 0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0},
1009
1010 /* More pseudo instructions which must follow the main table. */
1011 { "call", 0xe800f000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT},
1012 { "call", 0xe800a000, 0xffe0e000, "nW", pa10, FLAG_STRICT},
1013 { "ret", 0xe840d000, 0xfffffffd, "n", pa20, FLAG_STRICT},
1014
1015 };
1016
1017 #define NUMOPCODES ((sizeof pa_opcodes)/(sizeof pa_opcodes[0]))
1018
1019 /* SKV 12/18/92. Added some denotations for various operands. */
1020
1021 #define PA_IMM11_AT_31 'i'
1022 #define PA_IMM14_AT_31 'j'
1023 #define PA_IMM21_AT_31 'k'
1024 #define PA_DISP12 'w'
1025 #define PA_DISP17 'W'
1026
1027 #define N_HPPA_OPERAND_FORMATS 5
git-cvsimport of binutils cvsroot