opcodes/m32r-dis.c

   1 /* Disassembler interface for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 THIS FILE IS MACHINE GENERATED WITH CGEN.
   5 - the resultant file is machine generated, cgen-dis.in isn't
   6
   7 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
   8
   9 This file is part of the GNU Binutils and GDB, the GNU debugger.
  10
  11 This program is free software; you can redistribute it and/or modify
  12 it under the terms of the GNU General Public License as published by
  13 the Free Software Foundation; either version 2, or (at your option)
  14 any later version.
  15
  16 This program is distributed in the hope that it will be useful,
  17 but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 GNU General Public License for more details.
  20
  21 You should have received a copy of the GNU General Public License
  22 along with this program; if not, write to the Free Software Foundation, Inc.,
  23 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  24
  25 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
  26    Keep that in mind.  */
  27
  28 #include "sysdep.h"
  29 #include <stdio.h>
  30 #include "ansidecl.h"
  31 #include "dis-asm.h"
  32 #include "bfd.h"
  33 #include "symcat.h"
  34 #include "m32r-desc.h"
  35 #include "m32r-opc.h"
  36 #include "opintl.h"
  37
  38 /* Default text to print if an instruction isn't recognized.  */
  39 #define UNKNOWN_INSN_MSG _("*unknown*")
  40
  41 static void print_normal
  42      PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
  43 static void print_address
  44      PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
  45 static void print_keyword
  46      PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
  47 static void print_insn_normal
  48      PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
  49               bfd_vma, int));
  50 static int print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma,
  51                                disassemble_info *, char *, int));
  52 static int default_print_insn
  53      PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
  54 \f
  55 /* -- disassembler routines inserted here */
  56
  57 /* -- dis.c */
  58
  59 /* Immediate values are prefixed with '#'.  */
  60
  61 #define CGEN_PRINT_NORMAL(cd, info, value, attrs, pc, length) \
  62 do { \
  63   if (CGEN_BOOL_ATTR ((attrs), CGEN_OPERAND_HASH_PREFIX)) \
  64     (*info->fprintf_func) (info->stream, "#"); \
  65 } while (0)
  66
  67 /* Handle '#' prefixes as operands.  */
  68
  69 static void
  70 print_hash (cd, dis_info, value, attrs, pc, length)
  71      CGEN_CPU_DESC cd;
  72      PTR dis_info;
  73      long value;
  74      unsigned int attrs;
  75      bfd_vma pc;
  76      int length;
  77 {
  78   disassemble_info *info = (disassemble_info *) dis_info;
  79   (*info->fprintf_func) (info->stream, "#");
  80 }
  81
  82 #undef CGEN_PRINT_INSN
  83 #define CGEN_PRINT_INSN my_print_insn
  84
  85 static int
  86 my_print_insn (cd, pc, info)
  87      CGEN_CPU_DESC cd;
  88      bfd_vma pc;
  89      disassemble_info *info;
  90 {
  91   char buffer[CGEN_MAX_INSN_SIZE];
  92   char *buf = buffer;
  93   int status;
  94   int buflen = (pc & 3) == 0 ? 4 : 2;
  95
  96   /* Read the base part of the insn.  */
  97
  98   status = (*info->read_memory_func) (pc, buf, buflen, info);
  99   if (status != 0)
 100     {
 101       (*info->memory_error_func) (status, pc, info);
 102       return -1;
 103     }
 104
 105   /* 32 bit insn?  */
 106   if ((pc & 3) == 0 && (buf[0] & 0x80) != 0)
 107     return print_insn (cd, pc, info, buf, buflen);
 108
 109   /* Print the first insn.  */
 110   if ((pc & 3) == 0)
 111     {
 112       if (print_insn (cd, pc, info, buf, 2) == 0)
 113         (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 114       buf += 2;
 115     }
 116
 117   if (buf[0] & 0x80)
 118     {
 119       /* Parallel.  */
 120       (*info->fprintf_func) (info->stream, " || ");
 121       buf[0] &= 0x7f;
 122     }
 123   else
 124     (*info->fprintf_func) (info->stream, " -> ");
 125
 126   /* The "& 3" is to pass a consistent address.
 127      Parallel insns arguably both begin on the word boundary.
 128      Also, branch insns are calculated relative to the word boundary.  */
 129   if (print_insn (cd, pc & ~ (bfd_vma) 3, info, buf, 2) == 0)
 130     (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 131
 132   return (pc & 3) ? 2 : 4;
 133 }
 134
 135 /* -- */
 136
 137 /* Main entry point for printing operands.
 138    XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
 139    of dis-asm.h on cgen.h.
 140
 141    This function is basically just a big switch statement.  Earlier versions
 142    used tables to look up the function to use, but
 143    - if the table contains both assembler and disassembler functions then
 144      the disassembler contains much of the assembler and vice-versa,
 145    - there's a lot of inlining possibilities as things grow,
 146    - using a switch statement avoids the function call overhead.
 147
 148    This function could be moved into `print_insn_normal', but keeping it
 149    separate makes clear the interface between `print_insn_normal' and each of
 150    the handlers.
 151 */
 152
 153 void
 154 m32r_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
 155      CGEN_CPU_DESC cd;
 156      int opindex;
 157      PTR xinfo;
 158      CGEN_FIELDS *fields;
 159      void const *attrs;
 160      bfd_vma pc;
 161      int length;
 162 {
 163  disassemble_info *info = (disassemble_info *) xinfo;
 164
 165   switch (opindex)
 166     {
 167     case M32R_OPERAND_ACC :
 168       print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_acc, 0);
 169       break;
 170     case M32R_OPERAND_ACCD :
 171       print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accd, 0);
 172       break;
 173     case M32R_OPERAND_ACCS :
 174       print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accs, 0);
 175       break;
 176     case M32R_OPERAND_DCR :
 177       print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r1, 0);
 178       break;
 179     case M32R_OPERAND_DISP16 :
 180       print_address (cd, info, fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
 181       break;
 182     case M32R_OPERAND_DISP24 :
 183       print_address (cd, info, fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
 184       break;
 185     case M32R_OPERAND_DISP8 :
 186       print_address (cd, info, fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
 187       break;
 188     case M32R_OPERAND_DR :
 189       print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0);
 190       break;
 191     case M32R_OPERAND_HASH :
 192       print_hash (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
 193       break;
 194     case M32R_OPERAND_HI16 :
 195       print_normal (cd, info, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
 196       break;
 197     case M32R_OPERAND_IMM1 :
 198       print_normal (cd, info, fields->f_imm1, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 199       break;
 200     case M32R_OPERAND_SCR :
 201       print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r2, 0);
 202       break;
 203     case M32R_OPERAND_SIMM16 :
 204       print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 205       break;
 206     case M32R_OPERAND_SIMM8 :
 207       print_normal (cd, info, fields->f_simm8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 208       break;
 209     case M32R_OPERAND_SLO16 :
 210       print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
 211       break;
 212     case M32R_OPERAND_SR :
 213       print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r2, 0);
 214       break;
 215     case M32R_OPERAND_SRC1 :
 216       print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0);
 217       break;
 218     case M32R_OPERAND_SRC2 :
 219       print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r2, 0);
 220       break;
 221     case M32R_OPERAND_UIMM16 :
 222       print_normal (cd, info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 223       break;
 224     case M32R_OPERAND_UIMM24 :
 225       print_address (cd, info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
 226       break;
 227     case M32R_OPERAND_UIMM4 :
 228       print_normal (cd, info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 229       break;
 230     case M32R_OPERAND_UIMM5 :
 231       print_normal (cd, info, fields->f_uimm5, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 232       break;
 233     case M32R_OPERAND_ULO16 :
 234       print_normal (cd, info, fields->f_uimm16, 0, pc, length);
 235       break;
 236
 237     default :
 238       /* xgettext:c-format */
 239       fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
 240                opindex);
 241     abort ();
 242   }
 243 }
 244
 245 cgen_print_fn * const m32r_cgen_print_handlers[] =
 246 {
 247   print_insn_normal,
 248 };
 249
 250
 251 void
 252 m32r_cgen_init_dis (cd)
 253      CGEN_CPU_DESC cd;
 254 {
 255   m32r_cgen_init_opcode_table (cd);
 256   m32r_cgen_init_ibld_table (cd);
 257   cd->print_handlers = & m32r_cgen_print_handlers[0];
 258   cd->print_operand = m32r_cgen_print_operand;
 259 }
 260
 261 \f
 262 /* Default print handler.  */
 263
 264 static void
 265 print_normal (cd, dis_info, value, attrs, pc, length)
 266      CGEN_CPU_DESC cd;
 267      PTR dis_info;
 268      long value;
 269      unsigned int attrs;
 270      bfd_vma pc;
 271      int length;
 272 {
 273   disassemble_info *info = (disassemble_info *) dis_info;
 274
 275 #ifdef CGEN_PRINT_NORMAL
 276   CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
 277 #endif
 278
 279   /* Print the operand as directed by the attributes.  */
 280   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
 281     ; /* nothing to do */
 282   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
 283     (*info->fprintf_func) (info->stream, "%ld", value);
 284   else
 285     (*info->fprintf_func) (info->stream, "0x%lx", value);
 286 }
 287
 288 /* Default address handler.  */
 289
 290 static void
 291 print_address (cd, dis_info, value, attrs, pc, length)
 292      CGEN_CPU_DESC cd;
 293      PTR dis_info;
 294      bfd_vma value;
 295      unsigned int attrs;
 296      bfd_vma pc;
 297      int length;
 298 {
 299   disassemble_info *info = (disassemble_info *) dis_info;
 300
 301 #ifdef CGEN_PRINT_ADDRESS
 302   CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
 303 #endif
 304
 305   /* Print the operand as directed by the attributes.  */
 306   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
 307     ; /* nothing to do */
 308   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
 309     (*info->print_address_func) (value, info);
 310   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
 311     (*info->print_address_func) (value, info);
 312   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
 313     (*info->fprintf_func) (info->stream, "%ld", (long) value);
 314   else
 315     (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
 316 }
 317
 318 /* Keyword print handler.  */
 319
 320 static void
 321 print_keyword (cd, dis_info, keyword_table, value, attrs)
 322      CGEN_CPU_DESC cd;
 323      PTR dis_info;
 324      CGEN_KEYWORD *keyword_table;
 325      long value;
 326      unsigned int attrs;
 327 {
 328   disassemble_info *info = (disassemble_info *) dis_info;
 329   const CGEN_KEYWORD_ENTRY *ke;
 330
 331   ke = cgen_keyword_lookup_value (keyword_table, value);
 332   if (ke != NULL)
 333     (*info->fprintf_func) (info->stream, "%s", ke->name);
 334   else
 335     (*info->fprintf_func) (info->stream, "???");
 336 }
 337 \f
 338 /* Default insn printer.
 339
 340    DIS_INFO is defined as `PTR' so the disassembler needn't know anything
 341    about disassemble_info.  */
 342
 343 static void
 344 print_insn_normal (cd, dis_info, insn, fields, pc, length)
 345      CGEN_CPU_DESC cd;
 346      PTR dis_info;
 347      const CGEN_INSN *insn;
 348      CGEN_FIELDS *fields;
 349      bfd_vma pc;
 350      int length;
 351 {
 352   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
 353   disassemble_info *info = (disassemble_info *) dis_info;
 354   const unsigned char *syn;
 355
 356   CGEN_INIT_PRINT (cd);
 357
 358   for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
 359     {
 360       if (CGEN_SYNTAX_MNEMONIC_P (*syn))
 361         {
 362           (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
 363           continue;
 364         }
 365       if (CGEN_SYNTAX_CHAR_P (*syn))
 366         {
 367           (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
 368           continue;
 369         }
 370
 371       /* We have an operand.  */
 372       m32r_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
 373                                  fields, CGEN_INSN_ATTRS (insn), pc, length);
 374     }
 375 }
 376 \f
 377 /* Utility to print an insn.
 378    BUF is the base part of the insn, target byte order, BUFLEN bytes long.
 379    The result is the size of the insn in bytes or zero for an unknown insn
 380    or -1 if an error occurs fetching data (memory_error_func will have
 381    been called).  */
 382
 383 static int
 384 print_insn (cd, pc, info, buf, buflen)
 385      CGEN_CPU_DESC cd;
 386      bfd_vma pc;
 387      disassemble_info *info;
 388      char *buf;
 389      int buflen;
 390 {
 391   unsigned long insn_value;
 392   const CGEN_INSN_LIST *insn_list;
 393   CGEN_EXTRACT_INFO ex_info;
 394
 395   ex_info.dis_info = info;
 396   ex_info.valid = (1 << (cd->base_insn_bitsize / 8)) - 1;
 397   ex_info.insn_bytes = buf;
 398
 399   switch (buflen)
 400     {
 401     case 1:
 402       insn_value = buf[0];
 403       break;
 404     case 2:
 405       insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb16 (buf) : bfd_getl16 (buf);
 406       break;
 407     case 4:
 408       insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb32 (buf) : bfd_getl32 (buf);
 409       break;
 410     default:
 411       abort ();
 412     }
 413
 414   /* The instructions are stored in hash lists.
 415      Pick the first one and keep trying until we find the right one.  */
 416
 417   insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
 418   while (insn_list != NULL)
 419     {
 420       const CGEN_INSN *insn = insn_list->insn;
 421       CGEN_FIELDS fields;
 422       int length;
 423
 424 #ifdef CGEN_VALIDATE_INSN_SUPPORTED
 425       /* not needed as insn shouldn't be in hash lists if not supported */
 426       /* Supported by this cpu?  */
 427       if (! m32r_cgen_insn_supported (cd, insn))
 428         {
 429           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 430           continue;
 431         }
 432 #endif
 433
 434       /* Basic bit mask must be correct.  */
 435       /* ??? May wish to allow target to defer this check until the extract
 436          handler.  */
 437       if ((insn_value & CGEN_INSN_BASE_MASK (insn))
 438           == CGEN_INSN_BASE_VALUE (insn))
 439         {
 440           /* Printing is handled in two passes.  The first pass parses the
 441              machine insn and extracts the fields.  The second pass prints
 442              them.  */
 443
 444           length = CGEN_EXTRACT_FN (cd, insn)
 445             (cd, insn, &ex_info, insn_value, &fields, pc);
 446           /* length < 0 -> error */
 447           if (length < 0)
 448             return length;
 449           if (length > 0)
 450             {
 451               CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
 452               /* length is in bits, result is in bytes */
 453               return length / 8;
 454             }
 455         }
 456
 457       insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 458     }
 459
 460   return 0;
 461 }
 462
 463 /* Default value for CGEN_PRINT_INSN.
 464    The result is the size of the insn in bytes or zero for an unknown insn
 465    or -1 if an error occured fetching bytes.  */
 466
 467 #ifndef CGEN_PRINT_INSN
 468 #define CGEN_PRINT_INSN default_print_insn
 469 #endif
 470
 471 static int
 472 default_print_insn (cd, pc, info)
 473      CGEN_CPU_DESC cd;
 474      bfd_vma pc;
 475      disassemble_info *info;
 476 {
 477   char buf[CGEN_MAX_INSN_SIZE];
 478   int status;
 479
 480   /* Read the base part of the insn.  */
 481
 482   status = (*info->read_memory_func) (pc, buf, cd->base_insn_bitsize / 8, info);
 483   if (status != 0)
 484     {
 485       (*info->memory_error_func) (status, pc, info);
 486       return -1;
 487     }
 488
 489   return print_insn (cd, pc, info, buf, cd->base_insn_bitsize / 8);
 490 }
 491
 492 /* Main entry point.
 493    Print one instruction from PC on INFO->STREAM.
 494    Return the size of the instruction (in bytes).  */
 495
 496 int
 497 print_insn_m32r (pc, info)
 498      bfd_vma pc;
 499      disassemble_info *info;
 500 {
 501   static CGEN_CPU_DESC cd = 0;
 502   static prev_isa,prev_mach,prev_endian;
 503   int length;
 504   int isa,mach;
 505   int endian = (info->endian == BFD_ENDIAN_BIG
 506                 ? CGEN_ENDIAN_BIG
 507                 : CGEN_ENDIAN_LITTLE);
 508   enum bfd_architecture arch;
 509
 510   /* ??? gdb will set mach but leave the architecture as "unknown" */
 511 #ifndef CGEN_BFD_ARCH
 512 #define CGEN_BFD_ARCH bfd_arch_m32r
 513 #endif
 514   arch = info->arch;
 515   if (arch == bfd_arch_unknown)
 516     arch = CGEN_BFD_ARCH;
 517
 518   /* There's no standard way to compute the isa number (e.g. for arm thumb)
 519      so we leave it to the target.  */
 520 #ifdef CGEN_COMPUTE_ISA
 521   isa = CGEN_COMPUTE_ISA (info);
 522 #else
 523   isa = 0;
 524 #endif
 525
 526   mach = info->mach;
 527
 528   /* If we've switched cpu's, close the current table and open a new one.  */
 529   if (cd
 530       && (isa != prev_isa
 531           || mach != prev_mach
 532           || endian != prev_endian))
 533     {
 534       m32r_cgen_cpu_close (cd);
 535       cd = 0;
 536     }
 537
 538   /* If we haven't initialized yet, initialize the opcode table.  */
 539   if (! cd)
 540     {
 541       const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
 542       const char *mach_name;
 543
 544       if (!arch_type)
 545         abort ();
 546       mach_name = arch_type->printable_name;
 547
 548       prev_isa = isa;
 549       prev_mach = mach;
 550       prev_endian = endian;
 551       cd = m32r_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
 552                                  CGEN_CPU_OPEN_BFDMACH, mach_name,
 553                                  CGEN_CPU_OPEN_ENDIAN, prev_endian,
 554                                  CGEN_CPU_OPEN_END);
 555       if (!cd)
 556         abort ();
 557       m32r_cgen_init_dis (cd);
 558     }
 559
 560   /* We try to have as much common code as possible.
 561      But at this point some targets need to take over.  */
 562   /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
 563      but if not possible try to move this hook elsewhere rather than
 564      have two hooks.  */
 565   length = CGEN_PRINT_INSN (cd, pc, info);
 566   if (length > 0)
 567     return length;
 568   if (length < 0)
 569     return -1;
 570
 571   (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 572   return cd->default_insn_bitsize / 8;
 573 }