opcodes/ppc-opc.c

   1 /* ppc-opc.c -- PowerPC opcode list
   2    Copyright (c) 1994, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc.
   3    Written by Ian Lance Taylor, Cygnus Support
   4
   5 This file is part of GDB, GAS, and the GNU binutils.
   6
   7 GDB, GAS, and the GNU binutils are free software; you can redistribute
   8 them and/or modify them under the terms of the GNU General Public
   9 License as published by the Free Software Foundation; either version
  10 2, or (at your option) any later version.
  11
  12 GDB, GAS, and the GNU binutils are distributed in the hope that they
  13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15 the GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this file; see the file COPYING.  If not, write to the Free
  19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  20 02111-1307, USA.  */
  21
  22 #include <stdio.h>
  23 #include "sysdep.h"
  24 #include "opcode/ppc.h"
  25 #include "opintl.h"
  26
  27 /* This file holds the PowerPC opcode table.  The opcode table
  28    includes almost all of the extended instruction mnemonics.  This
  29    permits the disassembler to use them, and simplifies the assembler
  30    logic, at the cost of increasing the table size.  The table is
  31    strictly constant data, so the compiler should be able to put it in
  32    the .text section.
  33
  34    This file also holds the operand table.  All knowledge about
  35    inserting operands into instructions and vice-versa is kept in this
  36    file.  */
  37 \f
  38 /* Local insertion and extraction functions.  */
  39
  40 static unsigned long insert_bat PARAMS ((unsigned long, long, const char **));
  41 static long extract_bat PARAMS ((unsigned long, int *));
  42 static unsigned long insert_bba PARAMS ((unsigned long, long, const char **));
  43 static long extract_bba PARAMS ((unsigned long, int *));
  44 static unsigned long insert_bd PARAMS ((unsigned long, long, const char **));
  45 static long extract_bd PARAMS ((unsigned long, int *));
  46 static unsigned long insert_bdm PARAMS ((unsigned long, long, const char **));
  47 static long extract_bdm PARAMS ((unsigned long, int *));
  48 static unsigned long insert_bdp PARAMS ((unsigned long, long, const char **));
  49 static long extract_bdp PARAMS ((unsigned long, int *));
  50 static int valid_bo PARAMS ((long));
  51 static unsigned long insert_bo PARAMS ((unsigned long, long, const char **));
  52 static long extract_bo PARAMS ((unsigned long, int *));
  53 static unsigned long insert_boe PARAMS ((unsigned long, long, const char **));
  54 static long extract_boe PARAMS ((unsigned long, int *));
  55 static unsigned long insert_ds PARAMS ((unsigned long, long, const char **));
  56 static long extract_ds PARAMS ((unsigned long, int *));
  57 static unsigned long insert_li PARAMS ((unsigned long, long, const char **));
  58 static long extract_li PARAMS ((unsigned long, int *));
  59 static unsigned long insert_mbe PARAMS ((unsigned long, long, const char **));
  60 static long extract_mbe PARAMS ((unsigned long, int *));
  61 static unsigned long insert_mb6 PARAMS ((unsigned long, long, const char **));
  62 static long extract_mb6 PARAMS ((unsigned long, int *));
  63 static unsigned long insert_nb PARAMS ((unsigned long, long, const char **));
  64 static long extract_nb PARAMS ((unsigned long, int *));
  65 static unsigned long insert_nsi PARAMS ((unsigned long, long, const char **));
  66 static long extract_nsi PARAMS ((unsigned long, int *));
  67 static unsigned long insert_ral PARAMS ((unsigned long, long, const char **));
  68 static unsigned long insert_ram PARAMS ((unsigned long, long, const char **));
  69 static unsigned long insert_ras PARAMS ((unsigned long, long, const char **));
  70 static unsigned long insert_rbs PARAMS ((unsigned long, long, const char **));
  71 static long extract_rbs PARAMS ((unsigned long, int *));
  72 static unsigned long insert_sh6 PARAMS ((unsigned long, long, const char **));
  73 static long extract_sh6 PARAMS ((unsigned long, int *));
  74 static unsigned long insert_spr PARAMS ((unsigned long, long, const char **));
  75 static long extract_spr PARAMS ((unsigned long, int *));
  76 static unsigned long insert_tbr PARAMS ((unsigned long, long, const char **));
  77 static long extract_tbr PARAMS ((unsigned long, int *));
  78 \f
  79 /* The operands table.
  80
  81    The fields are bits, shift, insert, extract, flags.
  82
  83    We used to put parens around the various additions, like the one
  84    for BA just below.  However, that caused trouble with feeble
  85    compilers with a limit on depth of a parenthesized expression, like
  86    (reportedly) the compiler in Microsoft Developer Studio 5.  So we
  87    omit the parens, since the macros are never used in a context where
  88    the addition will be ambiguous.  */
  89
  90 const struct powerpc_operand powerpc_operands[] =
  91 {
  92   /* The zero index is used to indicate the end of the list of
  93      operands.  */
  94 #define UNUSED 0
  95   { 0, 0, 0, 0, 0 },
  96
  97   /* The BA field in an XL form instruction.  */
  98 #define BA UNUSED + 1
  99 #define BA_MASK (0x1f << 16)
 100   { 5, 16, 0, 0, PPC_OPERAND_CR },
 101
 102   /* The BA field in an XL form instruction when it must be the same
 103      as the BT field in the same instruction.  */
 104 #define BAT BA + 1
 105   { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
 106
 107   /* The BB field in an XL form instruction.  */
 108 #define BB BAT + 1
 109 #define BB_MASK (0x1f << 11)
 110   { 5, 11, 0, 0, PPC_OPERAND_CR },
 111
 112   /* The BB field in an XL form instruction when it must be the same
 113      as the BA field in the same instruction.  */
 114 #define BBA BB + 1
 115   { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
 116
 117   /* The BD field in a B form instruction.  The lower two bits are
 118      forced to zero.  */
 119 #define BD BBA + 1
 120   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 121
 122   /* The BD field in a B form instruction when absolute addressing is
 123      used.  */
 124 #define BDA BD + 1
 125   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 126
 127   /* The BD field in a B form instruction when the - modifier is used.
 128      This sets the y bit of the BO field appropriately.  */
 129 #define BDM BDA + 1
 130   { 16, 0, insert_bdm, extract_bdm,
 131       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 132
 133   /* The BD field in a B form instruction when the - modifier is used
 134      and absolute address is used.  */
 135 #define BDMA BDM + 1
 136   { 16, 0, insert_bdm, extract_bdm,
 137       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 138
 139   /* The BD field in a B form instruction when the + modifier is used.
 140      This sets the y bit of the BO field appropriately.  */
 141 #define BDP BDMA + 1
 142   { 16, 0, insert_bdp, extract_bdp,
 143       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 144
 145   /* The BD field in a B form instruction when the + modifier is used
 146      and absolute addressing is used.  */
 147 #define BDPA BDP + 1
 148   { 16, 0, insert_bdp, extract_bdp,
 149       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 150
 151   /* The BF field in an X or XL form instruction.  */
 152 #define BF BDPA + 1
 153   { 3, 23, 0, 0, PPC_OPERAND_CR },
 154
 155   /* An optional BF field.  This is used for comparison instructions,
 156      in which an omitted BF field is taken as zero.  */
 157 #define OBF BF + 1
 158   { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 159
 160   /* The BFA field in an X or XL form instruction.  */
 161 #define BFA OBF + 1
 162   { 3, 18, 0, 0, PPC_OPERAND_CR },
 163
 164   /* The BI field in a B form or XL form instruction.  */
 165 #define BI BFA + 1
 166 #define BI_MASK (0x1f << 16)
 167   { 5, 16, 0, 0, PPC_OPERAND_CR },
 168
 169   /* The BO field in a B form instruction.  Certain values are
 170      illegal.  */
 171 #define BO BI + 1
 172 #define BO_MASK (0x1f << 21)
 173   { 5, 21, insert_bo, extract_bo, 0 },
 174
 175   /* The BO field in a B form instruction when the + or - modifier is
 176      used.  This is like the BO field, but it must be even.  */
 177 #define BOE BO + 1
 178   { 5, 21, insert_boe, extract_boe, 0 },
 179
 180   /* The BT field in an X or XL form instruction.  */
 181 #define BT BOE + 1
 182   { 5, 21, 0, 0, PPC_OPERAND_CR },
 183
 184   /* The condition register number portion of the BI field in a B form
 185      or XL form instruction.  This is used for the extended
 186      conditional branch mnemonics, which set the lower two bits of the
 187      BI field.  This field is optional.  */
 188 #define CR BT + 1
 189   { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 190
 191   /* The D field in a D form instruction.  This is a displacement off
 192      a register, and implies that the next operand is a register in
 193      parentheses.  */
 194 #define D CR + 1
 195   { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 196
 197   /* The DS field in a DS form instruction.  This is like D, but the
 198      lower two bits are forced to zero.  */
 199 #define DS D + 1
 200   { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 201
 202   /* The E field in a wrteei instruction.  */
 203 #define E DS + 1
 204   { 1, 15, 0, 0, 0 },
 205
 206   /* The FL1 field in a POWER SC form instruction.  */
 207 #define FL1 E + 1
 208   { 4, 12, 0, 0, 0 },
 209
 210   /* The FL2 field in a POWER SC form instruction.  */
 211 #define FL2 FL1 + 1
 212   { 3, 2, 0, 0, 0 },
 213
 214   /* The FLM field in an XFL form instruction.  */
 215 #define FLM FL2 + 1
 216   { 8, 17, 0, 0, 0 },
 217
 218   /* The FRA field in an X or A form instruction.  */
 219 #define FRA FLM + 1
 220 #define FRA_MASK (0x1f << 16)
 221   { 5, 16, 0, 0, PPC_OPERAND_FPR },
 222
 223   /* The FRB field in an X or A form instruction.  */
 224 #define FRB FRA + 1
 225 #define FRB_MASK (0x1f << 11)
 226   { 5, 11, 0, 0, PPC_OPERAND_FPR },
 227
 228   /* The FRC field in an A form instruction.  */
 229 #define FRC FRB + 1
 230 #define FRC_MASK (0x1f << 6)
 231   { 5, 6, 0, 0, PPC_OPERAND_FPR },
 232
 233   /* The FRS field in an X form instruction or the FRT field in a D, X
 234      or A form instruction.  */
 235 #define FRS FRC + 1
 236 #define FRT FRS
 237   { 5, 21, 0, 0, PPC_OPERAND_FPR },
 238
 239   /* The FXM field in an XFX instruction.  */
 240 #define FXM FRS + 1
 241 #define FXM_MASK (0xff << 12)
 242   { 8, 12, 0, 0, 0 },
 243
 244   /* The L field in a D or X form instruction.  */
 245 #define L FXM + 1
 246   { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 247
 248   /* The LEV field in a POWER SC form instruction.  */
 249 #define LEV L + 1
 250   { 7, 5, 0, 0, 0 },
 251
 252   /* The LI field in an I form instruction.  The lower two bits are
 253      forced to zero.  */
 254 #define LI LEV + 1
 255   { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 256
 257   /* The LI field in an I form instruction when used as an absolute
 258      address.  */
 259 #define LIA LI + 1
 260   { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 261
 262   /* The MB field in an M form instruction.  */
 263 #define MB LIA + 1
 264 #define MB_MASK (0x1f << 6)
 265   { 5, 6, 0, 0, 0 },
 266
 267   /* The ME field in an M form instruction.  */
 268 #define ME MB + 1
 269 #define ME_MASK (0x1f << 1)
 270   { 5, 1, 0, 0, 0 },
 271
 272   /* The MB and ME fields in an M form instruction expressed a single
 273      operand which is a bitmask indicating which bits to select.  This
 274      is a two operand form using PPC_OPERAND_NEXT.  See the
 275      description in opcode/ppc.h for what this means.  */
 276 #define MBE ME + 1
 277   { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
 278   { 32, 0, insert_mbe, extract_mbe, 0 },
 279
 280   /* The MB or ME field in an MD or MDS form instruction.  The high
 281      bit is wrapped to the low end.  */
 282 #define MB6 MBE + 2
 283 #define ME6 MB6
 284 #define MB6_MASK (0x3f << 5)
 285   { 6, 5, insert_mb6, extract_mb6, 0 },
 286
 287   /* The NB field in an X form instruction.  The value 32 is stored as
 288      0.  */
 289 #define NB MB6 + 1
 290   { 6, 11, insert_nb, extract_nb, 0 },
 291
 292   /* The NSI field in a D form instruction.  This is the same as the
 293      SI field, only negated.  */
 294 #define NSI NB + 1
 295   { 16, 0, insert_nsi, extract_nsi,
 296       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 297
 298   /* The RA field in an D, DS, X, XO, M, or MDS form instruction.  */
 299 #define RA NSI + 1
 300 #define RA_MASK (0x1f << 16)
 301   { 5, 16, 0, 0, PPC_OPERAND_GPR },
 302
 303   /* The RA field in a D or X form instruction which is an updating
 304      load, which means that the RA field may not be zero and may not
 305      equal the RT field.  */
 306 #define RAL RA + 1
 307   { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
 308
 309   /* The RA field in an lmw instruction, which has special value
 310      restrictions.  */
 311 #define RAM RAL + 1
 312   { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
 313
 314   /* The RA field in a D or X form instruction which is an updating
 315      store or an updating floating point load, which means that the RA
 316      field may not be zero.  */
 317 #define RAS RAM + 1
 318   { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
 319
 320   /* The RB field in an X, XO, M, or MDS form instruction.  */
 321 #define RB RAS + 1
 322 #define RB_MASK (0x1f << 11)
 323   { 5, 11, 0, 0, PPC_OPERAND_GPR },
 324
 325   /* The RB field in an X form instruction when it must be the same as
 326      the RS field in the instruction.  This is used for extended
 327      mnemonics like mr.  */
 328 #define RBS RB + 1
 329   { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
 330
 331   /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
 332      instruction or the RT field in a D, DS, X, XFX or XO form
 333      instruction.  */
 334 #define RS RBS + 1
 335 #define RT RS
 336 #define RT_MASK (0x1f << 21)
 337   { 5, 21, 0, 0, PPC_OPERAND_GPR },
 338
 339   /* The SH field in an X or M form instruction.  */
 340 #define SH RS + 1
 341 #define SH_MASK (0x1f << 11)
 342   { 5, 11, 0, 0, 0 },
 343
 344   /* The SH field in an MD form instruction.  This is split.  */
 345 #define SH6 SH + 1
 346 #define SH6_MASK ((0x1f << 11) | (1 << 1))
 347   { 6, 1, insert_sh6, extract_sh6, 0 },
 348
 349   /* The SI field in a D form instruction.  */
 350 #define SI SH6 + 1
 351   { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
 352
 353   /* The SI field in a D form instruction when we accept a wide range
 354      of positive values.  */
 355 #define SISIGNOPT SI + 1
 356   { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 357
 358   /* The SPR field in an XFX form instruction.  This is flipped--the
 359      lower 5 bits are stored in the upper 5 and vice- versa.  */
 360 #define SPR SISIGNOPT + 1
 361 #define SPR_MASK (0x3ff << 11)
 362   { 10, 11, insert_spr, extract_spr, 0 },
 363
 364   /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
 365 #define SPRBAT SPR + 1
 366 #define SPRBAT_MASK (0x3 << 17)
 367   { 2, 17, 0, 0, 0 },
 368
 369   /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
 370 #define SPRG SPRBAT + 1
 371 #define SPRG_MASK (0x3 << 16)
 372   { 2, 16, 0, 0, 0 },
 373
 374   /* The SR field in an X form instruction.  */
 375 #define SR SPRG + 1
 376   { 4, 16, 0, 0, 0 },
 377
 378   /* The SV field in a POWER SC form instruction.  */
 379 #define SV SR + 1
 380   { 14, 2, 0, 0, 0 },
 381
 382   /* The TBR field in an XFX form instruction.  This is like the SPR
 383      field, but it is optional.  */
 384 #define TBR SV + 1
 385   { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
 386
 387   /* The TO field in a D or X form instruction.  */
 388 #define TO TBR + 1
 389 #define TO_MASK (0x1f << 21)
 390   { 5, 21, 0, 0, 0 },
 391
 392   /* The U field in an X form instruction.  */
 393 #define U TO + 1
 394   { 4, 12, 0, 0, 0 },
 395
 396   /* The UI field in a D form instruction.  */
 397 #define UI U + 1
 398   { 16, 0, 0, 0, 0 },
 399
 400   /* The VA field in a VA, VX or VXR form instruction. */
 401 #define VA UI + 1
 402 #define VA_MASK (0x1f << 16)
 403   {5, 16, 0, 0, PPC_OPERAND_VR},
 404
 405   /* The VB field in a VA, VX or VXR form instruction. */
 406 #define VB VA + 1
 407 #define VB_MASK (0x1f << 11)
 408   {5, 11, 0, 0, PPC_OPERAND_VR},
 409
 410   /* The VC field in a VA form instruction. */
 411 #define VC VB + 1
 412 #define VC_MASK (0x1f << 6)
 413   {5, 6, 0, 0, PPC_OPERAND_VR},
 414
 415   /* The VD or VS field in a VA, VX, VXR or X form instruction. */
 416 #define VD VC + 1
 417 #define VS VD
 418 #define VD_MASK (0x1f << 21)
 419   {5, 21, 0, 0, PPC_OPERAND_VR},
 420
 421   /* The SIMM field in a VX form instruction. */
 422 #define SIMM VD + 1
 423   { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
 424
 425   /* The UIMM field in a VX form instruction. */
 426 #define UIMM SIMM + 1
 427   { 5, 16, 0, 0, 0 },
 428
 429   /* The SHB field in a VA form instruction. */
 430 #define SHB UIMM + 1
 431   { 4, 6, 0, 0, 0 },
 432 };
 433
 434 /* The functions used to insert and extract complicated operands.  */
 435
 436 /* The BA field in an XL form instruction when it must be the same as
 437    the BT field in the same instruction.  This operand is marked FAKE.
 438    The insertion function just copies the BT field into the BA field,
 439    and the extraction function just checks that the fields are the
 440    same.  */
 441
 442 /*ARGSUSED*/
 443 static unsigned long
 444 insert_bat (insn, value, errmsg)
 445      unsigned long insn;
 446      long value ATTRIBUTE_UNUSED;
 447      const char **errmsg ATTRIBUTE_UNUSED;
 448 {
 449   return insn | (((insn >> 21) & 0x1f) << 16);
 450 }
 451
 452 static long
 453 extract_bat (insn, invalid)
 454      unsigned long insn;
 455      int *invalid;
 456 {
 457   if (invalid != (int *) NULL
 458       && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
 459     *invalid = 1;
 460   return 0;
 461 }
 462
 463 /* The BB field in an XL form instruction when it must be the same as
 464    the BA field in the same instruction.  This operand is marked FAKE.
 465    The insertion function just copies the BA field into the BB field,
 466    and the extraction function just checks that the fields are the
 467    same.  */
 468
 469 /*ARGSUSED*/
 470 static unsigned long
 471 insert_bba (insn, value, errmsg)
 472      unsigned long insn;
 473      long value ATTRIBUTE_UNUSED;
 474      const char **errmsg ATTRIBUTE_UNUSED;
 475 {
 476   return insn | (((insn >> 16) & 0x1f) << 11);
 477 }
 478
 479 static long
 480 extract_bba (insn, invalid)
 481      unsigned long insn;
 482      int *invalid;
 483 {
 484   if (invalid != (int *) NULL
 485       && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
 486     *invalid = 1;
 487   return 0;
 488 }
 489
 490 /* The BD field in a B form instruction.  The lower two bits are
 491    forced to zero.  */
 492
 493 /*ARGSUSED*/
 494 static unsigned long
 495 insert_bd (insn, value, errmsg)
 496      unsigned long insn;
 497      long value;
 498      const char **errmsg ATTRIBUTE_UNUSED;
 499 {
 500   return insn | (value & 0xfffc);
 501 }
 502
 503 /*ARGSUSED*/
 504 static long
 505 extract_bd (insn, invalid)
 506      unsigned long insn;
 507      int *invalid ATTRIBUTE_UNUSED;
 508 {
 509   if ((insn & 0x8000) != 0)
 510     return (insn & 0xfffc) - 0x10000;
 511   else
 512     return insn & 0xfffc;
 513 }
 514
 515 /* The BD field in a B form instruction when the - modifier is used.
 516    This modifier means that the branch is not expected to be taken.
 517    We must set the y bit of the BO field to 1 if the offset is
 518    negative.  When extracting, we require that the y bit be 1 and that
 519    the offset be positive, since if the y bit is 0 we just want to
 520    print the normal form of the instruction.  */
 521
 522 /*ARGSUSED*/
 523 static unsigned long
 524 insert_bdm (insn, value, errmsg)
 525      unsigned long insn;
 526      long value;
 527      const char **errmsg ATTRIBUTE_UNUSED;
 528 {
 529   if ((value & 0x8000) != 0)
 530     insn |= 1 << 21;
 531   return insn | (value & 0xfffc);
 532 }
 533
 534 static long
 535 extract_bdm (insn, invalid)
 536      unsigned long insn;
 537      int *invalid;
 538 {
 539   if (invalid != (int *) NULL
 540       && ((insn & (1 << 21)) == 0
 541           || (insn & (1 << 15)) == 0))
 542     *invalid = 1;
 543   if ((insn & 0x8000) != 0)
 544     return (insn & 0xfffc) - 0x10000;
 545   else
 546     return insn & 0xfffc;
 547 }
 548
 549 /* The BD field in a B form instruction when the + modifier is used.
 550    This is like BDM, above, except that the branch is expected to be
 551    taken.  */
 552
 553 /*ARGSUSED*/
 554 static unsigned long
 555 insert_bdp (insn, value, errmsg)
 556      unsigned long insn;
 557      long value;
 558      const char **errmsg ATTRIBUTE_UNUSED;
 559 {
 560   if ((value & 0x8000) == 0)
 561     insn |= 1 << 21;
 562   return insn | (value & 0xfffc);
 563 }
 564
 565 static long
 566 extract_bdp (insn, invalid)
 567      unsigned long insn;
 568      int *invalid;
 569 {
 570   if (invalid != (int *) NULL
 571       && ((insn & (1 << 21)) == 0
 572           || (insn & (1 << 15)) != 0))
 573     *invalid = 1;
 574   if ((insn & 0x8000) != 0)
 575     return (insn & 0xfffc) - 0x10000;
 576   else
 577     return insn & 0xfffc;
 578 }
 579
 580 /* Check for legal values of a BO field.  */
 581
 582 static int
 583 valid_bo (value)
 584      long value;
 585 {
 586   /* Certain encodings have bits that are required to be zero.  These
 587      are (z must be zero, y may be anything):
 588          001zy
 589          011zy
 590          1z00y
 591          1z01y
 592          1z1zz
 593      */
 594   switch (value & 0x14)
 595     {
 596     default:
 597     case 0:
 598       return 1;
 599     case 0x4:
 600       return (value & 0x2) == 0;
 601     case 0x10:
 602       return (value & 0x8) == 0;
 603     case 0x14:
 604       return value == 0x14;
 605     }
 606 }
 607
 608 /* The BO field in a B form instruction.  Warn about attempts to set
 609    the field to an illegal value.  */
 610
 611 static unsigned long
 612 insert_bo (insn, value, errmsg)
 613      unsigned long insn;
 614      long value;
 615      const char **errmsg;
 616 {
 617   if (errmsg != (const char **) NULL
 618       && ! valid_bo (value))
 619     *errmsg = _("invalid conditional option");
 620   return insn | ((value & 0x1f) << 21);
 621 }
 622
 623 static long
 624 extract_bo (insn, invalid)
 625      unsigned long insn;
 626      int *invalid;
 627 {
 628   long value;
 629
 630   value = (insn >> 21) & 0x1f;
 631   if (invalid != (int *) NULL
 632       && ! valid_bo (value))
 633     *invalid = 1;
 634   return value;
 635 }
 636
 637 /* The BO field in a B form instruction when the + or - modifier is
 638    used.  This is like the BO field, but it must be even.  When
 639    extracting it, we force it to be even.  */
 640
 641 static unsigned long
 642 insert_boe (insn, value, errmsg)
 643      unsigned long insn;
 644      long value;
 645      const char **errmsg;
 646 {
 647   if (errmsg != (const char **) NULL)
 648     {
 649       if (! valid_bo (value))
 650         *errmsg = _("invalid conditional option");
 651       else if ((value & 1) != 0)
 652         *errmsg = _("attempt to set y bit when using + or - modifier");
 653     }
 654   return insn | ((value & 0x1f) << 21);
 655 }
 656
 657 static long
 658 extract_boe (insn, invalid)
 659      unsigned long insn;
 660      int *invalid;
 661 {
 662   long value;
 663
 664   value = (insn >> 21) & 0x1f;
 665   if (invalid != (int *) NULL
 666       && ! valid_bo (value))
 667     *invalid = 1;
 668   return value & 0x1e;
 669 }
 670
 671 /* The DS field in a DS form instruction.  This is like D, but the
 672    lower two bits are forced to zero.  */
 673
 674 /*ARGSUSED*/
 675 static unsigned long
 676 insert_ds (insn, value, errmsg)
 677      unsigned long insn;
 678      long value;
 679      const char **errmsg ATTRIBUTE_UNUSED;
 680 {
 681   return insn | (value & 0xfffc);
 682 }
 683
 684 /*ARGSUSED*/
 685 static long
 686 extract_ds (insn, invalid)
 687      unsigned long insn;
 688      int *invalid ATTRIBUTE_UNUSED;
 689 {
 690   if ((insn & 0x8000) != 0)
 691     return (insn & 0xfffc) - 0x10000;
 692   else
 693     return insn & 0xfffc;
 694 }
 695
 696 /* The LI field in an I form instruction.  The lower two bits are
 697    forced to zero.  */
 698
 699 /*ARGSUSED*/
 700 static unsigned long
 701 insert_li (insn, value, errmsg)
 702      unsigned long insn;
 703      long value;
 704      const char **errmsg;
 705 {
 706   if ((value & 3) != 0 && errmsg != (const char **) NULL)
 707     *errmsg = _("ignoring least significant bits in branch offset");
 708   return insn | (value & 0x3fffffc);
 709 }
 710
 711 /*ARGSUSED*/
 712 static long
 713 extract_li (insn, invalid)
 714      unsigned long insn;
 715      int *invalid ATTRIBUTE_UNUSED;
 716 {
 717   if ((insn & 0x2000000) != 0)
 718     return (insn & 0x3fffffc) - 0x4000000;
 719   else
 720     return insn & 0x3fffffc;
 721 }
 722
 723 /* The MB and ME fields in an M form instruction expressed as a single
 724    operand which is itself a bitmask.  The extraction function always
 725    marks it as invalid, since we never want to recognize an
 726    instruction which uses a field of this type.  */
 727
 728 static unsigned long
 729 insert_mbe (insn, value, errmsg)
 730      unsigned long insn;
 731      long value;
 732      const char **errmsg;
 733 {
 734   unsigned long uval, mask;
 735   int mb, me, mx, count, last;
 736
 737   uval = value;
 738
 739   if (uval == 0)
 740     {
 741       if (errmsg != (const char **) NULL)
 742         *errmsg = _("illegal bitmask");
 743       return insn;
 744     }
 745
 746   mb = 0;
 747   me = 32;
 748   if ((uval & 1) != 0)
 749     last = 1;
 750   else
 751     last = 0;
 752   count = 0;
 753
 754   /* mb: location of last 0->1 transition */
 755   /* me: location of last 1->0 transition */
 756   /* count: # transitions */
 757
 758   for (mx = 0, mask = 1 << 31; mx < 32; ++mx, mask >>= 1)
 759     {
 760       if ((uval & mask) && !last)
 761         {
 762           ++count;
 763           mb = mx;
 764           last = 1;
 765         }
 766       else if (!(uval & mask) && last)
 767         {
 768           ++count;
 769           me = mx;
 770           last = 0;
 771         }
 772     }
 773   if (me == 0)
 774     me = 32;
 775
 776   if (count != 2 && (count != 0 || ! last))
 777     {
 778       if (errmsg != (const char **) NULL)
 779         *errmsg = _("illegal bitmask");
 780     }
 781
 782   return insn | (mb << 6) | ((me - 1) << 1);
 783 }
 784
 785 static long
 786 extract_mbe (insn, invalid)
 787      unsigned long insn;
 788      int *invalid;
 789 {
 790   long ret;
 791   int mb, me;
 792   int i;
 793
 794   if (invalid != (int *) NULL)
 795     *invalid = 1;
 796
 797   mb = (insn >> 6) & 0x1f;
 798   me = (insn >> 1) & 0x1f;
 799   if (mb < me + 1)
 800     {
 801       ret = 0;
 802       for (i = mb; i <= me; i++)
 803         ret |= (long) 1 << (31 - i);
 804     }
 805   else if (mb == me + 1)
 806     ret = ~0;
 807   else /* (mb > me + 1) */
 808     {
 809       ret = ~ (long) 0;
 810       for (i = me + 1; i < mb; i++)
 811         ret &= ~ ((long) 1 << (31 - i));
 812     }
 813   return ret;
 814 }
 815
 816 /* The MB or ME field in an MD or MDS form instruction.  The high bit
 817    is wrapped to the low end.  */
 818
 819 /*ARGSUSED*/
 820 static unsigned long
 821 insert_mb6 (insn, value, errmsg)
 822      unsigned long insn;
 823      long value;
 824      const char **errmsg ATTRIBUTE_UNUSED;
 825 {
 826   return insn | ((value & 0x1f) << 6) | (value & 0x20);
 827 }
 828
 829 /*ARGSUSED*/
 830 static long
 831 extract_mb6 (insn, invalid)
 832      unsigned long insn;
 833      int *invalid ATTRIBUTE_UNUSED;
 834 {
 835   return ((insn >> 6) & 0x1f) | (insn & 0x20);
 836 }
 837
 838 /* The NB field in an X form instruction.  The value 32 is stored as
 839    0.  */
 840
 841 static unsigned long
 842 insert_nb (insn, value, errmsg)
 843      unsigned long insn;
 844      long value;
 845      const char **errmsg;
 846 {
 847   if (value < 0 || value > 32)
 848     *errmsg = _("value out of range");
 849   if (value == 32)
 850     value = 0;
 851   return insn | ((value & 0x1f) << 11);
 852 }
 853
 854 /*ARGSUSED*/
 855 static long
 856 extract_nb (insn, invalid)
 857      unsigned long insn;
 858      int *invalid ATTRIBUTE_UNUSED;
 859 {
 860   long ret;
 861
 862   ret = (insn >> 11) & 0x1f;
 863   if (ret == 0)
 864     ret = 32;
 865   return ret;
 866 }
 867
 868 /* The NSI field in a D form instruction.  This is the same as the SI
 869    field, only negated.  The extraction function always marks it as
 870    invalid, since we never want to recognize an instruction which uses
 871    a field of this type.  */
 872
 873 /*ARGSUSED*/
 874 static unsigned long
 875 insert_nsi (insn, value, errmsg)
 876      unsigned long insn;
 877      long value;
 878      const char **errmsg ATTRIBUTE_UNUSED;
 879 {
 880   return insn | ((- value) & 0xffff);
 881 }
 882
 883 static long
 884 extract_nsi (insn, invalid)
 885      unsigned long insn;
 886      int *invalid;
 887 {
 888   if (invalid != (int *) NULL)
 889     *invalid = 1;
 890   if ((insn & 0x8000) != 0)
 891     return - ((long)(insn & 0xffff) - 0x10000);
 892   else
 893     return - (long)(insn & 0xffff);
 894 }
 895
 896 /* The RA field in a D or X form instruction which is an updating
 897    load, which means that the RA field may not be zero and may not
 898    equal the RT field.  */
 899
 900 static unsigned long
 901 insert_ral (insn, value, errmsg)
 902      unsigned long insn;
 903      long value;
 904      const char **errmsg;
 905 {
 906   if (value == 0
 907       || (unsigned long) value == ((insn >> 21) & 0x1f))
 908     *errmsg = "invalid register operand when updating";
 909   return insn | ((value & 0x1f) << 16);
 910 }
 911
 912 /* The RA field in an lmw instruction, which has special value
 913    restrictions.  */
 914
 915 static unsigned long
 916 insert_ram (insn, value, errmsg)
 917      unsigned long insn;
 918      long value;
 919      const char **errmsg;
 920 {
 921   if ((unsigned long) value >= ((insn >> 21) & 0x1f))
 922     *errmsg = _("index register in load range");
 923   return insn | ((value & 0x1f) << 16);
 924 }
 925
 926 /* The RA field in a D or X form instruction which is an updating
 927    store or an updating floating point load, which means that the RA
 928    field may not be zero.  */
 929
 930 static unsigned long
 931 insert_ras (insn, value, errmsg)
 932      unsigned long insn;
 933      long value;
 934      const char **errmsg;
 935 {
 936   if (value == 0)
 937     *errmsg = _("invalid register operand when updating");
 938   return insn | ((value & 0x1f) << 16);
 939 }
 940
 941 /* The RB field in an X form instruction when it must be the same as
 942    the RS field in the instruction.  This is used for extended
 943    mnemonics like mr.  This operand is marked FAKE.  The insertion
 944    function just copies the BT field into the BA field, and the
 945    extraction function just checks that the fields are the same.  */
 946
 947 /*ARGSUSED*/
 948 static unsigned long
 949 insert_rbs (insn, value, errmsg)
 950      unsigned long insn;
 951      long value ATTRIBUTE_UNUSED;
 952      const char **errmsg ATTRIBUTE_UNUSED;
 953 {
 954   return insn | (((insn >> 21) & 0x1f) << 11);
 955 }
 956
 957 static long
 958 extract_rbs (insn, invalid)
 959      unsigned long insn;
 960      int *invalid;
 961 {
 962   if (invalid != (int *) NULL
 963       && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
 964     *invalid = 1;
 965   return 0;
 966 }
 967
 968 /* The SH field in an MD form instruction.  This is split.  */
 969
 970 /*ARGSUSED*/
 971 static unsigned long
 972 insert_sh6 (insn, value, errmsg)
 973      unsigned long insn;
 974      long value;
 975      const char **errmsg ATTRIBUTE_UNUSED;
 976 {
 977   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
 978 }
 979
 980 /*ARGSUSED*/
 981 static long
 982 extract_sh6 (insn, invalid)
 983      unsigned long insn;
 984      int *invalid ATTRIBUTE_UNUSED;
 985 {
 986   return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
 987 }
 988
 989 /* The SPR field in an XFX form instruction.  This is flipped--the
 990    lower 5 bits are stored in the upper 5 and vice- versa.  */
 991
 992 static unsigned long
 993 insert_spr (insn, value, errmsg)
 994      unsigned long insn;
 995      long value;
 996      const char **errmsg ATTRIBUTE_UNUSED;
 997 {
 998   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
 999 }
1000
1001 static long
1002 extract_spr (insn, invalid)
1003      unsigned long insn;
1004      int *invalid ATTRIBUTE_UNUSED;
1005 {
1006   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1007 }
1008
1009 /* The TBR field in an XFX instruction.  This is just like SPR, but it
1010    is optional.  When TBR is omitted, it must be inserted as 268 (the
1011    magic number of the TB register).  These functions treat 0
1012    (indicating an omitted optional operand) as 268.  This means that
1013    ``mftb 4,0'' is not handled correctly.  This does not matter very
1014    much, since the architecture manual does not define mftb as
1015    accepting any values other than 268 or 269.  */
1016
1017 #define TB (268)
1018
1019 static unsigned long
1020 insert_tbr (insn, value, errmsg)
1021      unsigned long insn;
1022      long value;
1023      const char **errmsg ATTRIBUTE_UNUSED;
1024 {
1025   if (value == 0)
1026     value = TB;
1027   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1028 }
1029
1030 static long
1031 extract_tbr (insn, invalid)
1032      unsigned long insn;
1033      int *invalid ATTRIBUTE_UNUSED;
1034 {
1035   long ret;
1036
1037   ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1038   if (ret == TB)
1039     ret = 0;
1040   return ret;
1041 }
1042 \f
1043 /* Macros used to form opcodes.  */
1044
1045 /* The main opcode.  */
1046 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1047 #define OP_MASK OP (0x3f)
1048
1049 /* The main opcode combined with a trap code in the TO field of a D
1050    form instruction.  Used for extended mnemonics for the trap
1051    instructions.  */
1052 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1053 #define OPTO_MASK (OP_MASK | TO_MASK)
1054
1055 /* The main opcode combined with a comparison size bit in the L field
1056    of a D form or X form instruction.  Used for extended mnemonics for
1057    the comparison instructions.  */
1058 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1059 #define OPL_MASK OPL (0x3f,1)
1060
1061 /* An A form instruction.  */
1062 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1063 #define A_MASK A (0x3f, 0x1f, 1)
1064
1065 /* An A_MASK with the FRB field fixed.  */
1066 #define AFRB_MASK (A_MASK | FRB_MASK)
1067
1068 /* An A_MASK with the FRC field fixed.  */
1069 #define AFRC_MASK (A_MASK | FRC_MASK)
1070
1071 /* An A_MASK with the FRA and FRC fields fixed.  */
1072 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1073
1074 /* A B form instruction.  */
1075 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1076 #define B_MASK B (0x3f, 1, 1)
1077
1078 /* A B form instruction setting the BO field.  */
1079 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1080 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1081
1082 /* A BBO_MASK with the y bit of the BO field removed.  This permits
1083    matching a conditional branch regardless of the setting of the y
1084    bit.  */
1085 #define Y_MASK (((unsigned long)1) << 21)
1086 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
1087
1088 /* A B form instruction setting the BO field and the condition bits of
1089    the BI field.  */
1090 #define BBOCB(op, bo, cb, aa, lk) \
1091   (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1092 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1093
1094 /* A BBOCB_MASK with the y bit of the BO field removed.  */
1095 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1096
1097 /* A BBOYCB_MASK in which the BI field is fixed.  */
1098 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1099
1100 /* The main opcode mask with the RA field clear.  */
1101 #define DRA_MASK (OP_MASK | RA_MASK)
1102
1103 /* A DS form instruction.  */
1104 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1105 #define DS_MASK DSO (0x3f, 3)
1106
1107 /* An M form instruction.  */
1108 #define M(op, rc) (OP (op) | ((rc) & 1))
1109 #define M_MASK M (0x3f, 1)
1110
1111 /* An M form instruction with the ME field specified.  */
1112 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1113
1114 /* An M_MASK with the MB and ME fields fixed.  */
1115 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1116
1117 /* An M_MASK with the SH and ME fields fixed.  */
1118 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1119
1120 /* An MD form instruction.  */
1121 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1122 #define MD_MASK MD (0x3f, 0x7, 1)
1123
1124 /* An MD_MASK with the MB field fixed.  */
1125 #define MDMB_MASK (MD_MASK | MB6_MASK)
1126
1127 /* An MD_MASK with the SH field fixed.  */
1128 #define MDSH_MASK (MD_MASK | SH6_MASK)
1129
1130 /* An MDS form instruction.  */
1131 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1132 #define MDS_MASK MDS (0x3f, 0xf, 1)
1133
1134 /* An MDS_MASK with the MB field fixed.  */
1135 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1136
1137 /* An SC form instruction.  */
1138 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1139 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1140
1141 /* An VX form instruction. */
1142 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1143
1144 /* The mask for an VX form instruction. */
1145 #define VX_MASK VX(0x3f, 0x7ff)
1146
1147 /* An VA form instruction. */
1148 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x07f))
1149
1150 /* The mask for an VA form instruction. */
1151 #define VXA_MASK VXA(0x3f, 0x7f)
1152
1153 /* An VXR form instruction. */
1154 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1155
1156 /* The mask for a VXR form instruction. */
1157 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1158
1159 /* An X form instruction.  */
1160 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1161
1162 /* An X form instruction with the RC bit specified.  */
1163 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1164
1165 /* The mask for an X form instruction.  */
1166 #define X_MASK XRC (0x3f, 0x3ff, 1)
1167
1168 /* An X_MASK with the RA field fixed.  */
1169 #define XRA_MASK (X_MASK | RA_MASK)
1170
1171 /* An X_MASK with the RB field fixed.  */
1172 #define XRB_MASK (X_MASK | RB_MASK)
1173
1174 /* An X_MASK with the RT field fixed.  */
1175 #define XRT_MASK (X_MASK | RT_MASK)
1176
1177 /* An X_MASK with the RA and RB fields fixed.  */
1178 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1179
1180 /* An X_MASK with the RT and RA fields fixed.  */
1181 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1182
1183 /* An X form comparison instruction.  */
1184 #define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1185
1186 /* The mask for an X form comparison instruction.  */
1187 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1188
1189 /* The mask for an X form comparison instruction with the L field
1190    fixed.  */
1191 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1192
1193 /* An X form trap instruction with the TO field specified.  */
1194 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1195 #define XTO_MASK (X_MASK | TO_MASK)
1196
1197 /* An XFL form instruction.  */
1198 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1199 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1200
1201 /* An XL form instruction with the LK field set to 0.  */
1202 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1203
1204 /* An XL form instruction which uses the LK field.  */
1205 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1206
1207 /* The mask for an XL form instruction.  */
1208 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1209
1210 /* An XL form instruction which explicitly sets the BO field.  */
1211 #define XLO(op, bo, xop, lk) \
1212   (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1213 #define XLO_MASK (XL_MASK | BO_MASK)
1214
1215 /* An XL form instruction which explicitly sets the y bit of the BO
1216    field.  */
1217 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1218 #define XLYLK_MASK (XL_MASK | Y_MASK)
1219
1220 /* An XL form instruction which sets the BO field and the condition
1221    bits of the BI field.  */
1222 #define XLOCB(op, bo, cb, xop, lk) \
1223   (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1224 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1225
1226 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
1227 #define XLBB_MASK (XL_MASK | BB_MASK)
1228 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1229 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1230
1231 /* An XL_MASK with the BO and BB fields fixed.  */
1232 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1233
1234 /* An XL_MASK with the BO, BI and BB fields fixed.  */
1235 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1236
1237 /* An XO form instruction.  */
1238 #define XO(op, xop, oe, rc) \
1239   (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1240 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1241
1242 /* An XO_MASK with the RB field fixed.  */
1243 #define XORB_MASK (XO_MASK | RB_MASK)
1244
1245 /* An XS form instruction.  */
1246 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1247 #define XS_MASK XS (0x3f, 0x1ff, 1)
1248
1249 /* A mask for the FXM version of an XFX form instruction.  */
1250 #define XFXFXM_MASK (X_MASK | (((unsigned long)1) << 20) | (((unsigned long)1) << 11))
1251
1252 /* An XFX form instruction with the FXM field filled in.  */
1253 #define XFXM(op, xop, fxm) \
1254   (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1255
1256 /* An XFX form instruction with the SPR field filled in.  */
1257 #define XSPR(op, xop, spr) \
1258   (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1259 #define XSPR_MASK (X_MASK | SPR_MASK)
1260
1261 /* An XFX form instruction with the SPR field filled in except for the
1262    SPRBAT field.  */
1263 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1264
1265 /* An XFX form instruction with the SPR field filled in except for the
1266    SPRG field.  */
1267 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1268
1269 /* An X form instruction with everything filled in except the E field.  */
1270 #define XE_MASK (0xffff7fff)
1271
1272 /* The BO encodings used in extended conditional branch mnemonics.  */
1273 #define BODNZF  (0x0)
1274 #define BODNZFP (0x1)
1275 #define BODZF   (0x2)
1276 #define BODZFP  (0x3)
1277 #define BOF     (0x4)
1278 #define BOFP    (0x5)
1279 #define BODNZT  (0x8)
1280 #define BODNZTP (0x9)
1281 #define BODZT   (0xa)
1282 #define BODZTP  (0xb)
1283 #define BOT     (0xc)
1284 #define BOTP    (0xd)
1285 #define BODNZ   (0x10)
1286 #define BODNZP  (0x11)
1287 #define BODZ    (0x12)
1288 #define BODZP   (0x13)
1289 #define BOU     (0x14)
1290
1291 /* The BI condition bit encodings used in extended conditional branch
1292    mnemonics.  */
1293 #define CBLT    (0)
1294 #define CBGT    (1)
1295 #define CBEQ    (2)
1296 #define CBSO    (3)
1297
1298 /* The TO encodings used in extended trap mnemonics.  */
1299 #define TOLGT   (0x1)
1300 #define TOLLT   (0x2)
1301 #define TOEQ    (0x4)
1302 #define TOLGE   (0x5)
1303 #define TOLNL   (0x5)
1304 #define TOLLE   (0x6)
1305 #define TOLNG   (0x6)
1306 #define TOGT    (0x8)
1307 #define TOGE    (0xc)
1308 #define TONL    (0xc)
1309 #define TOLT    (0x10)
1310 #define TOLE    (0x14)
1311 #define TONG    (0x14)
1312 #define TONE    (0x18)
1313 #define TOU     (0x1f)
1314 \f
1315 /* Smaller names for the flags so each entry in the opcodes table will
1316    fit on a single line.  */
1317 #undef  PPC
1318 #define PPC     PPC_OPCODE_PPC | PPC_OPCODE_ANY
1319 #define PPCCOM  PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1320 #define PPC32   PPC_OPCODE_PPC | PPC_OPCODE_32 | PPC_OPCODE_ANY
1321 #define PPC64   PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_ANY
1322 #define PPCONLY PPC_OPCODE_PPC
1323 #define PPC403  PPC
1324 #define PPC750  PPC
1325 #define PPC860  PPC
1326 #define PPCVEC  PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY
1327 #define POWER   PPC_OPCODE_POWER | PPC_OPCODE_ANY
1328 #define POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1329 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1330 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32
1331 #define COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1332 #define COM32   PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32
1333 #define M601    PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
1334 #define PWRCOM  PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1335 #define MFDEC1  PPC_OPCODE_POWER
1336 #define MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601
1337 \f
1338 /* The opcode table.
1339
1340    The format of the opcode table is:
1341
1342    NAME      OPCODE     MASK            FLAGS           { OPERANDS }
1343
1344    NAME is the name of the instruction.
1345    OPCODE is the instruction opcode.
1346    MASK is the opcode mask; this is used to tell the disassembler
1347      which bits in the actual opcode must match OPCODE.
1348    FLAGS are flags indicated what processors support the instruction.
1349    OPERANDS is the list of operands.
1350
1351    The disassembler reads the table in order and prints the first
1352    instruction which matches, so this table is sorted to put more
1353    specific instructions before more general instructions.  It is also
1354    sorted by major opcode.  */
1355
1356 const struct powerpc_opcode powerpc_opcodes[] = {
1357 { "tdlgti",  OPTO(2,TOLGT), OPTO_MASK,  PPC64,          { RA, SI } },
1358 { "tdllti",  OPTO(2,TOLLT), OPTO_MASK,  PPC64,          { RA, SI } },
1359 { "tdeqi",   OPTO(2,TOEQ), OPTO_MASK,   PPC64,          { RA, SI } },
1360 { "tdlgei",  OPTO(2,TOLGE), OPTO_MASK,  PPC64,          { RA, SI } },
1361 { "tdlnli",  OPTO(2,TOLNL), OPTO_MASK,  PPC64,          { RA, SI } },
1362 { "tdllei",  OPTO(2,TOLLE), OPTO_MASK,  PPC64,          { RA, SI } },
1363 { "tdlngi",  OPTO(2,TOLNG), OPTO_MASK,  PPC64,          { RA, SI } },
1364 { "tdgti",   OPTO(2,TOGT), OPTO_MASK,   PPC64,          { RA, SI } },
1365 { "tdgei",   OPTO(2,TOGE), OPTO_MASK,   PPC64,          { RA, SI } },
1366 { "tdnli",   OPTO(2,TONL), OPTO_MASK,   PPC64,          { RA, SI } },
1367 { "tdlti",   OPTO(2,TOLT), OPTO_MASK,   PPC64,          { RA, SI } },
1368 { "tdlei",   OPTO(2,TOLE), OPTO_MASK,   PPC64,          { RA, SI } },
1369 { "tdngi",   OPTO(2,TONG), OPTO_MASK,   PPC64,          { RA, SI } },
1370 { "tdnei",   OPTO(2,TONE), OPTO_MASK,   PPC64,          { RA, SI } },
1371 { "tdi",     OP(2),     OP_MASK,        PPC64,          { TO, RA, SI } },
1372
1373 { "twlgti",  OPTO(3,TOLGT), OPTO_MASK,  PPCCOM,         { RA, SI } },
1374 { "tlgti",   OPTO(3,TOLGT), OPTO_MASK,  PWRCOM,         { RA, SI } },
1375 { "twllti",  OPTO(3,TOLLT), OPTO_MASK,  PPCCOM,         { RA, SI } },
1376 { "tllti",   OPTO(3,TOLLT), OPTO_MASK,  PWRCOM,         { RA, SI } },
1377 { "tweqi",   OPTO(3,TOEQ), OPTO_MASK,   PPCCOM,         { RA, SI } },
1378 { "teqi",    OPTO(3,TOEQ), OPTO_MASK,   PWRCOM,         { RA, SI } },
1379 { "twlgei",  OPTO(3,TOLGE), OPTO_MASK,  PPCCOM,         { RA, SI } },
1380 { "tlgei",   OPTO(3,TOLGE), OPTO_MASK,  PWRCOM,         { RA, SI } },
1381 { "twlnli",  OPTO(3,TOLNL), OPTO_MASK,  PPCCOM,         { RA, SI } },
1382 { "tlnli",   OPTO(3,TOLNL), OPTO_MASK,  PWRCOM,         { RA, SI } },
1383 { "twllei",  OPTO(3,TOLLE), OPTO_MASK,  PPCCOM,         { RA, SI } },
1384 { "tllei",   OPTO(3,TOLLE), OPTO_MASK,  PWRCOM,         { RA, SI } },
1385 { "twlngi",  OPTO(3,TOLNG), OPTO_MASK,  PPCCOM,         { RA, SI } },
1386 { "tlngi",   OPTO(3,TOLNG), OPTO_MASK,  PWRCOM,         { RA, SI } },
1387 { "twgti",   OPTO(3,TOGT), OPTO_MASK,   PPCCOM,         { RA, SI } },
1388 { "tgti",    OPTO(3,TOGT), OPTO_MASK,   PWRCOM,         { RA, SI } },
1389 { "twgei",   OPTO(3,TOGE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1390 { "tgei",    OPTO(3,TOGE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1391 { "twnli",   OPTO(3,TONL), OPTO_MASK,   PPCCOM,         { RA, SI } },
1392 { "tnli",    OPTO(3,TONL), OPTO_MASK,   PWRCOM,         { RA, SI } },
1393 { "twlti",   OPTO(3,TOLT), OPTO_MASK,   PPCCOM,         { RA, SI } },
1394 { "tlti",    OPTO(3,TOLT), OPTO_MASK,   PWRCOM,         { RA, SI } },
1395 { "twlei",   OPTO(3,TOLE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1396 { "tlei",    OPTO(3,TOLE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1397 { "twngi",   OPTO(3,TONG), OPTO_MASK,   PPCCOM,         { RA, SI } },
1398 { "tngi",    OPTO(3,TONG), OPTO_MASK,   PWRCOM,         { RA, SI } },
1399 { "twnei",   OPTO(3,TONE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1400 { "tnei",    OPTO(3,TONE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1401 { "twi",     OP(3),     OP_MASK,        PPCCOM,         { TO, RA, SI } },
1402 { "ti",      OP(3),     OP_MASK,        PWRCOM,         { TO, RA, SI } },
1403
1404 { "mfvscr",  VX(4, 1540), VX_MASK,      PPCVEC,         { VD } },
1405 { "mtvscr",  VX(4, 1604), VX_MASK,      PPCVEC,         { VD } },
1406 { "vaddcuw", VX(4,  384), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1407 { "vaddfp",  VX(4,   10), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1408 { "vaddsbs", VX(4,  768), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1409 { "vaddshs", VX(4,  832), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1410 { "vaddsws", VX(4,  896), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1411 { "vaddubm", VX(4,    0), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1412 { "vaddubs", VX(4,  512), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1413 { "vadduhm", VX(4,   64), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1414 { "vadduhs", VX(4,  576), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1415 { "vadduwm", VX(4,  128), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1416 { "vadduws", VX(4,  640), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1417 { "vand",    VX(4, 1028), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1418 { "vandc",   VX(4, 1092), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1419 { "vavgsb",  VX(4, 1282), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1420 { "vavgsh",  VX(4, 1346), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1421 { "vavgsw",  VX(4, 1410), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1422 { "vavgub",  VX(4, 1026), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1423 { "vavguh",  VX(4, 1090), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1424 { "vavguw",  VX(4, 1154), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1425 { "vcfsx",   VX(4,  842), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
1426 { "vcfux",   VX(4,  778), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
1427 { "vcmpbfp",   VXR(4, 966, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1428 { "vcmpbfp.",  VXR(4, 966, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1429 { "vcmpeqfp",  VXR(4, 198, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1430 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1431 { "vcmpequb",  VXR(4,   6, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1432 { "vcmpequb.", VXR(4,   6, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1433 { "vcmpequh",  VXR(4,  70, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1434 { "vcmpequh.", VXR(4,  70, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1435 { "vcmpequw",  VXR(4, 134, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1436 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1437 { "vcmpgefp",  VXR(4, 454, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1438 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1439 { "vcmpgtfp",  VXR(4, 710, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1440 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1441 { "vcmpgtsb",  VXR(4, 774, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1442 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1443 { "vcmpgtsh",  VXR(4, 838, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1444 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1445 { "vcmpgtsw",  VXR(4, 902, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1446 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1447 { "vcmpgtub",  VXR(4, 518, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1448 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1449 { "vcmpgtuh",  VXR(4, 582, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1450 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1451 { "vcmpgtuw",  VXR(4, 646, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1452 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1453 { "vctsxs",    VX(4,  970), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1454 { "vctuxs",    VX(4,  906), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1455 { "vexptefp",  VX(4,  394), VX_MASK,    PPCVEC,         { VD, VB } },
1456 { "vlogefp",   VX(4,  458), VX_MASK,    PPCVEC,         { VD, VB } },
1457 { "vmaddfp",   VXA(4,  46), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1458 { "vmaxfp",    VX(4, 1034), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1459 { "vmaxsb",    VX(4,  258), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1460 { "vmaxsh",    VX(4,  322), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1461 { "vmaxsw",    VX(4,  386), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1462 { "vmaxub",    VX(4,    2), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1463 { "vmaxuh",    VX(4,   66), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1464 { "vmaxuw",    VX(4,  130), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1465 { "vmhaddshs", VXA(4,  32), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1466 { "vmhraddshs", VXA(4, 33), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1467 { "vminfp",    VX(4, 1098), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1468 { "vminsb",    VX(4,  770), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1469 { "vminsh",    VX(4,  834), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1470 { "vminsw",    VX(4,  898), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1471 { "vminub",    VX(4,  514), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1472 { "vminuh",    VX(4,  578), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1473 { "vminuw",    VX(4,  642), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1474 { "vmladduhm", VXA(4,  34), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1475 { "vmrghb",    VX(4,   12), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1476 { "vmrghh",    VX(4,   76), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1477 { "vmrghw",    VX(4,  140), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1478 { "vmrglb",    VX(4,  268), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1479 { "vmrglh",    VX(4,  332), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1480 { "vmrglw",    VX(4,  396), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1481 { "vmsummbm",  VXA(4,  37), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1482 { "vmsumshm",  VXA(4,  40), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1483 { "vmsumshs",  VXA(4,  41), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1484 { "vmsumubm",  VXA(4,  36), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1485 { "vmsumuhm",  VXA(4,  38), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1486 { "vmsumuhs",  VXA(4,  39), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1487 { "vmulesb",   VX(4,  776), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1488 { "vmulesh",   VX(4,  840), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1489 { "vmuleub",   VX(4,  520), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1490 { "vmuleuh",   VX(4,  584), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1491 { "vmulosb",   VX(4,  264), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1492 { "vmulosh",   VX(4,  328), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1493 { "vmuloub",   VX(4,    8), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1494 { "vmulouh",   VX(4,   72), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1495 { "vnmsubfp",  VXA(4,  47), VXA_MASK,   PPCVEC,         { VD, VA, VC, VB } },
1496 { "vnor",      VX(4, 1284), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1497 { "vor",       VX(4, 1156), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1498 { "vperm",     VXA(4,  43), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1499 { "vpkpx",     VX(4,  782), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1500 { "vpkshss",   VX(4,  398), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1501 { "vpkshus",   VX(4,  270), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1502 { "vpkswss",   VX(4,  462), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1503 { "vpkswus",   VX(4,  334), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1504 { "vpkuhum",   VX(4,   14), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1505 { "vpkuhus",   VX(4,  142), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1506 { "vpkuwum",   VX(4,   78), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1507 { "vpkuwus",   VX(4,  206), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1508 { "vrefp",     VX(4,  266), VX_MASK,    PPCVEC,         { VD, VB } },
1509 { "vrfim",     VX(4,  714), VX_MASK,    PPCVEC,         { VD, VB } },
1510 { "vrfin",     VX(4,  522), VX_MASK,    PPCVEC,         { VD, VB } },
1511 { "vrfip",     VX(4,  650), VX_MASK,    PPCVEC,         { VD, VB } },
1512 { "vrfiz",     VX(4,  586), VX_MASK,    PPCVEC,         { VD, VB } },
1513 { "vrlb",      VX(4,    4), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1514 { "vrlh",      VX(4,   68), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1515 { "vrlw",      VX(4,  132), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1516 { "vrsqrtefp", VX(4,  330), VX_MASK,    PPCVEC,         { VD, VB } },
1517 { "vsel",      VXA(4,  42), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1518 { "vsl",       VX(4,  452), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1519 { "vslb",      VX(4,  260), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1520 { "vsldoi",    VXA(4,  44), VXA_MASK,   PPCVEC,         { VD, VA, VB, SHB } },
1521 { "vslh",      VX(4,  324), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1522 { "vslo",      VX(4, 1036), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1523 { "vslw",      VX(4,  338), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1524 { "vspltb",    VX(4,  524), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1525 { "vsplth",    VX(4,  588), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1526 { "vspltisb",  VX(4,  780), VX_MASK,    PPCVEC,         { VD, SIMM } },
1527 { "vspltish",  VX(4,  844), VX_MASK,    PPCVEC,         { VD, SIMM } },
1528 { "vspltisw",  VX(4,  908), VX_MASK,    PPCVEC,         { VD, SIMM } },
1529 { "vspltw",    VX(4,  652), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1530 { "vsr",       VX(4,  708), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1531 { "vsrab",     VX(4,  772), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1532 { "vsrah",     VX(4,  836), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1533 { "vsraw",     VX(4,  900), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1534 { "vsrb",      VX(4,  516), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1535 { "vsrh",      VX(4,  580), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1536 { "vsro",      VX(4, 1100), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1537 { "vsrw",      VX(4,  644), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1538 { "vsubcuw",   VX(4, 1408), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1539 { "vsubfp",    VX(4,   74), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1540 { "vsubsbs",   VX(4, 1792), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1541 { "vsubshs",   VX(4, 1856), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1542 { "vsubsws",   VX(4, 1920), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1543 { "vsububm",   VX(4, 1024), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1544 { "vsububs",   VX(4, 1536), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1545 { "vsubuhm",   VX(4, 1088), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1546 { "vsubuhs",   VX(4, 1600), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1547 { "vsubuwm",   VX(4, 1152), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1548 { "vsubuws",   VX(4, 1664), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1549 { "vsumsws",   VX(4, 1928), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1550 { "vsum2sws",  VX(4, 1672), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1551 { "vsum4sbs",  VX(4, 1800), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1552 { "vsum4shs",  VX(4, 1608), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1553 { "vsum4ubs",  VX(4, 1544), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1554 { "vupkhpx",   VX(4,  846), VX_MASK,    PPCVEC,         { VD, VB } },
1555 { "vupkhsb",   VX(4,  526), VX_MASK,    PPCVEC,         { VD, VB } },
1556 { "vupkhsh",   VX(4,  590), VX_MASK,    PPCVEC,         { VD, VB } },
1557 { "vupklpx",   VX(4,  974), VX_MASK,    PPCVEC,         { VD, VB } },
1558 { "vupklsb",   VX(4,  654), VX_MASK,    PPCVEC,         { VD, VB } },
1559 { "vupklsh",   VX(4,  718), VX_MASK,    PPCVEC,         { VD, VB } },
1560 { "vxor",      VX(4, 1220), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1561
1562 { "mulli",   OP(7),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
1563 { "muli",    OP(7),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
1564
1565 { "subfic",  OP(8),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
1566 { "sfi",     OP(8),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
1567
1568 { "dozi",    OP(9),     OP_MASK,        M601,           { RT, RA, SI } },
1569
1570 { "cmplwi",  OPL(10,0), OPL_MASK,       PPCCOM,         { OBF, RA, UI } },
1571 { "cmpldi",  OPL(10,1), OPL_MASK,       PPC64,          { OBF, RA, UI } },
1572 { "cmpli",   OP(10),    OP_MASK,        PPCONLY,        { BF, L, RA, UI } },
1573 { "cmpli",   OP(10),    OP_MASK,        PWRCOM,         { BF, RA, UI } },
1574
1575 { "cmpwi",   OPL(11,0), OPL_MASK,       PPCCOM,         { OBF, RA, SI } },
1576 { "cmpdi",   OPL(11,1), OPL_MASK,       PPC64,          { OBF, RA, SI } },
1577 { "cmpi",    OP(11),    OP_MASK,        PPCONLY,        { BF, L, RA, SI } },
1578 { "cmpi",    OP(11),    OP_MASK,        PWRCOM,         { BF, RA, SI } },
1579
1580 { "addic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
1581 { "ai",      OP(12),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
1582 { "subic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
1583
1584 { "addic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
1585 { "ai.",     OP(13),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
1586 { "subic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
1587
1588 { "li",      OP(14),    DRA_MASK,       PPCCOM,         { RT, SI } },
1589 { "lil",     OP(14),    DRA_MASK,       PWRCOM,         { RT, SI } },
1590 { "addi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
1591 { "cal",     OP(14),    OP_MASK,        PWRCOM,         { RT, D, RA } },
1592 { "subi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
1593 { "la",      OP(14),    OP_MASK,        PPCCOM,         { RT, D, RA } },
1594
1595 { "lis",     OP(15),    DRA_MASK,       PPCCOM,         { RT, SISIGNOPT } },
1596 { "liu",     OP(15),    DRA_MASK,       PWRCOM,         { RT, SISIGNOPT } },
1597 { "addis",   OP(15),    OP_MASK,        PPCCOM,         { RT,RA,SISIGNOPT } },
1598 { "cau",     OP(15),    OP_MASK,        PWRCOM,         { RT,RA,SISIGNOPT } },
1599 { "subis",   OP(15),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
1600
1601 { "bdnz-",   BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM,    { BDM } },
1602 { "bdnz+",   BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM,    { BDP } },
1603 { "bdnz",    BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM,    { BD } },
1604 { "bdn",     BBO(16,BODNZ,0,0), BBOYBI_MASK, PWRCOM,    { BD } },
1605 { "bdnzl-",  BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM,    { BDM } },
1606 { "bdnzl+",  BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM,    { BDP } },
1607 { "bdnzl",   BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM,    { BD } },
1608 { "bdnl",    BBO(16,BODNZ,0,1), BBOYBI_MASK, PWRCOM,    { BD } },
1609 { "bdnza-",  BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM,    { BDMA } },
1610 { "bdnza+",  BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM,    { BDPA } },
1611 { "bdnza",   BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM,    { BDA } },
1612 { "bdna",    BBO(16,BODNZ,1,0), BBOYBI_MASK, PWRCOM,    { BDA } },
1613 { "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM,    { BDMA } },
1614 { "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM,    { BDPA } },
1615 { "bdnzla",  BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM,    { BDA } },
1616 { "bdnla",   BBO(16,BODNZ,1,1), BBOYBI_MASK, PWRCOM,    { BDA } },
1617 { "bdz-",    BBO(16,BODZ,0,0),  BBOYBI_MASK, PPCCOM,    { BDM } },
1618 { "bdz+",    BBO(16,BODZ,0,0),  BBOYBI_MASK, PPCCOM,    { BDP } },
1619 { "bdz",     BBO(16,BODZ,0,0),  BBOYBI_MASK, COM,       { BD } },
1620 { "bdzl-",   BBO(16,BODZ,0,1),  BBOYBI_MASK, PPCCOM,    { BDM } },
1621 { "bdzl+",   BBO(16,BODZ,0,1),  BBOYBI_MASK, PPCCOM,    { BDP } },
1622 { "bdzl",    BBO(16,BODZ,0,1),  BBOYBI_MASK, COM,       { BD } },
1623 { "bdza-",   BBO(16,BODZ,1,0),  BBOYBI_MASK, PPCCOM,    { BDMA } },
1624 { "bdza+",   BBO(16,BODZ,1,0),  BBOYBI_MASK, PPCCOM,    { BDPA } },
1625 { "bdza",    BBO(16,BODZ,1,0),  BBOYBI_MASK, COM,       { BDA } },
1626 { "bdzla-",  BBO(16,BODZ,1,1),  BBOYBI_MASK, PPCCOM,    { BDMA } },
1627 { "bdzla+",  BBO(16,BODZ,1,1),  BBOYBI_MASK, PPCCOM,    { BDPA } },
1628 { "bdzla",   BBO(16,BODZ,1,1),  BBOYBI_MASK, COM,       { BDA } },
1629 { "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1630 { "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1631 { "blt",     BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1632 { "bltl-",   BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1633 { "bltl+",   BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1634 { "bltl",    BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1635 { "blta-",   BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1636 { "blta+",   BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1637 { "blta",    BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1638 { "bltla-",  BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1639 { "bltla+",  BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1640 { "bltla",   BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1641 { "bgt-",    BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1642 { "bgt+",    BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1643 { "bgt",     BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1644 { "bgtl-",   BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1645 { "bgtl+",   BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1646 { "bgtl",    BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1647 { "bgta-",   BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1648 { "bgta+",   BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1649 { "bgta",    BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1650 { "bgtla-",  BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1651 { "bgtla+",  BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1652 { "bgtla",   BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1653 { "beq-",    BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1654 { "beq+",    BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1655 { "beq",     BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1656 { "beql-",   BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1657 { "beql+",   BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1658 { "beql",    BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1659 { "beqa-",   BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1660 { "beqa+",   BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1661 { "beqa",    BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1662 { "beqla-",  BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1663 { "beqla+",  BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1664 { "beqla",   BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1665 { "bso-",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1666 { "bso+",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1667 { "bso",     BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1668 { "bsol-",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1669 { "bsol+",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1670 { "bsol",    BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1671 { "bsoa-",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1672 { "bsoa+",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1673 { "bsoa",    BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1674 { "bsola-",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1675 { "bsola+",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1676 { "bsola",   BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1677 { "bun-",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1678 { "bun+",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1679 { "bun",     BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BD } },
1680 { "bunl-",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1681 { "bunl+",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1682 { "bunl",    BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BD } },
1683 { "buna-",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1684 { "buna+",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1685 { "buna",    BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDA } },
1686 { "bunla-",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1687 { "bunla+",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1688 { "bunla",   BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDA } },
1689 { "bge-",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1690 { "bge+",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1691 { "bge",     BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1692 { "bgel-",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1693 { "bgel+",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1694 { "bgel",    BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1695 { "bgea-",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1696 { "bgea+",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1697 { "bgea",    BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1698 { "bgela-",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1699 { "bgela+",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1700 { "bgela",   BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1701 { "bnl-",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1702 { "bnl+",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1703 { "bnl",     BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1704 { "bnll-",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1705 { "bnll+",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1706 { "bnll",    BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1707 { "bnla-",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1708 { "bnla+",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1709 { "bnla",    BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1710 { "bnlla-",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1711 { "bnlla+",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1712 { "bnlla",   BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1713 { "ble-",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1714 { "ble+",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1715 { "ble",     BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1716 { "blel-",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1717 { "blel+",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1718 { "blel",    BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1719 { "blea-",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1720 { "blea+",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1721 { "blea",    BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1722 { "blela-",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1723 { "blela+",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1724 { "blela",   BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1725 { "bng-",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1726 { "bng+",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1727 { "bng",     BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1728 { "bngl-",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1729 { "bngl+",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1730 { "bngl",    BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1731 { "bnga-",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1732 { "bnga+",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1733 { "bnga",    BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1734 { "bngla-",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1735 { "bngla+",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1736 { "bngla",   BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1737 { "bne-",    BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1738 { "bne+",    BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1739 { "bne",     BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1740 { "bnel-",   BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1741 { "bnel+",   BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1742 { "bnel",    BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1743 { "bnea-",   BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1744 { "bnea+",   BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1745 { "bnea",    BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1746 { "bnela-",  BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1747 { "bnela+",  BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1748 { "bnela",   BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1749 { "bns-",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1750 { "bns+",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1751 { "bns",     BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1752 { "bnsl-",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1753 { "bnsl+",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1754 { "bnsl",    BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1755 { "bnsa-",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1756 { "bnsa+",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1757 { "bnsa",    BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1758 { "bnsla-",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1759 { "bnsla+",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1760 { "bnsla",   BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1761 { "bnu-",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1762 { "bnu+",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1763 { "bnu",     BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BD } },
1764 { "bnul-",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1765 { "bnul+",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1766 { "bnul",    BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BD } },
1767 { "bnua-",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1768 { "bnua+",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1769 { "bnua",    BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDA } },
1770 { "bnula-",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1771 { "bnula+",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1772 { "bnula",   BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDA } },
1773 { "bdnzt-",  BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,     { BI, BDM } },
1774 { "bdnzt+",  BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,     { BI, BDP } },
1775 { "bdnzt",   BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
1776 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,     { BI, BDM } },
1777 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,     { BI, BDP } },
1778 { "bdnztl",  BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
1779 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,     { BI, BDMA } },
1780 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,     { BI, BDPA } },
1781 { "bdnzta",  BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
1782 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,     { BI, BDMA } },
1783 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,     { BI, BDPA } },
1784 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
1785 { "bdnzf-",  BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,     { BI, BDM } },
1786 { "bdnzf+",  BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,     { BI, BDP } },
1787 { "bdnzf",   BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
1788 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,     { BI, BDM } },
1789 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,     { BI, BDP } },
1790 { "bdnzfl",  BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
1791 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,     { BI, BDMA } },
1792 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,     { BI, BDPA } },
1793 { "bdnzfa",  BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
1794 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,     { BI, BDMA } },
1795 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,     { BI, BDPA } },
1796 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
1797 { "bt-",     BBO(16,BOT,0,0), BBOY_MASK, PPCCOM,        { BI, BDM } },
1798 { "bt+",     BBO(16,BOT,0,0), BBOY_MASK, PPCCOM,        { BI, BDP } },
1799 { "bt",      BBO(16,BOT,0,0), BBOY_MASK, PPCCOM,        { BI, BD } },
1800 { "bbt",     BBO(16,BOT,0,0), BBOY_MASK, PWRCOM,        { BI, BD } },
1801 { "btl-",    BBO(16,BOT,0,1), BBOY_MASK, PPCCOM,        { BI, BDM } },
1802 { "btl+",    BBO(16,BOT,0,1), BBOY_MASK, PPCCOM,        { BI, BDP } },
1803 { "btl",     BBO(16,BOT,0,1), BBOY_MASK, PPCCOM,        { BI, BD } },
1804 { "bbtl",    BBO(16,BOT,0,1), BBOY_MASK, PWRCOM,        { BI, BD } },
1805 { "bta-",    BBO(16,BOT,1,0), BBOY_MASK, PPCCOM,        { BI, BDMA } },
1806 { "bta+",    BBO(16,BOT,1,0), BBOY_MASK, PPCCOM,        { BI, BDPA } },
1807 { "bta",     BBO(16,BOT,1,0), BBOY_MASK, PPCCOM,        { BI, BDA } },
1808 { "bbta",    BBO(16,BOT,1,0), BBOY_MASK, PWRCOM,        { BI, BDA } },
1809 { "btla-",   BBO(16,BOT,1,1), BBOY_MASK, PPCCOM,        { BI, BDMA } },
1810 { "btla+",   BBO(16,BOT,1,1), BBOY_MASK, PPCCOM,        { BI, BDPA } },
1811 { "btla",    BBO(16,BOT,1,1), BBOY_MASK, PPCCOM,        { BI, BDA } },
1812 { "bbtla",   BBO(16,BOT,1,1), BBOY_MASK, PWRCOM,        { BI, BDA } },
1813 { "bf-",     BBO(16,BOF,0,0), BBOY_MASK, PPCCOM,        { BI, BDM } },
1814 { "bf+",     BBO(16,BOF,0,0), BBOY_MASK, PPCCOM,        { BI, BDP } },
1815 { "bf",      BBO(16,BOF,0,0), BBOY_MASK, PPCCOM,        { BI, BD } },
1816 { "bbf",     BBO(16,BOF,0,0), BBOY_MASK, PWRCOM,        { BI, BD } },
1817 { "bfl-",    BBO(16,BOF,0,1), BBOY_MASK, PPCCOM,        { BI, BDM } },
1818 { "bfl+",    BBO(16,BOF,0,1), BBOY_MASK, PPCCOM,        { BI, BDP } },
1819 { "bfl",     BBO(16,BOF,0,1), BBOY_MASK, PPCCOM,        { BI, BD } },
1820 { "bbfl",    BBO(16,BOF,0,1), BBOY_MASK, PWRCOM,        { BI, BD } },
1821 { "bfa-",    BBO(16,BOF,1,0), BBOY_MASK, PPCCOM,        { BI, BDMA } },
1822 { "bfa+",    BBO(16,BOF,1,0), BBOY_MASK, PPCCOM,        { BI, BDPA } },
1823 { "bfa",     BBO(16,BOF,1,0), BBOY_MASK, PPCCOM,        { BI, BDA } },
1824 { "bbfa",    BBO(16,BOF,1,0), BBOY_MASK, PWRCOM,        { BI, BDA } },
1825 { "bfla-",   BBO(16,BOF,1,1), BBOY_MASK, PPCCOM,        { BI, BDMA } },
1826 { "bfla+",   BBO(16,BOF,1,1), BBOY_MASK, PPCCOM,        { BI, BDPA } },
1827 { "bfla",    BBO(16,BOF,1,1), BBOY_MASK, PPCCOM,        { BI, BDA } },
1828 { "bbfla",   BBO(16,BOF,1,1), BBOY_MASK, PWRCOM,        { BI, BDA } },
1829 { "bdzt-",   BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,      { BI, BDM } },
1830 { "bdzt+",   BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,      { BI, BDP } },
1831 { "bdzt",    BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
1832 { "bdztl-",  BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,      { BI, BDM } },
1833 { "bdztl+",  BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,      { BI, BDP } },
1834 { "bdztl",   BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
1835 { "bdzta-",  BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,      { BI, BDMA } },
1836 { "bdzta+",  BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,      { BI, BDPA } },
1837 { "bdzta",   BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
1838 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,      { BI, BDMA } },
1839 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,      { BI, BDPA } },
1840 { "bdztla",  BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
1841 { "bdzf-",   BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,      { BI, BDM } },
1842 { "bdzf+",   BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,      { BI, BDP } },
1843 { "bdzf",    BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
1844 { "bdzfl-",  BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,      { BI, BDM } },
1845 { "bdzfl+",  BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,      { BI, BDP } },
1846 { "bdzfl",   BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
1847 { "bdzfa-",  BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,      { BI, BDMA } },
1848 { "bdzfa+",  BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,      { BI, BDPA } },
1849 { "bdzfa",   BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
1850 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,      { BI, BDMA } },
1851 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,      { BI, BDPA } },
1852 { "bdzfla",  BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
1853 { "bc-",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
1854 { "bc+",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
1855 { "bc",      B(16,0,0), B_MASK,         COM,            { BO, BI, BD } },
1856 { "bcl-",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
1857 { "bcl+",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
1858 { "bcl",     B(16,0,1), B_MASK,         COM,            { BO, BI, BD } },
1859 { "bca-",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
1860 { "bca+",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
1861 { "bca",     B(16,1,0), B_MASK,         COM,            { BO, BI, BDA } },
1862 { "bcla-",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
1863 { "bcla+",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
1864 { "bcla",    B(16,1,1), B_MASK,         COM,            { BO, BI, BDA } },
1865
1866 { "sc",      SC(17,1,0), 0xffffffff,    PPC,            { 0 } },
1867 { "svc",     SC(17,0,0), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
1868 { "svcl",    SC(17,0,1), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
1869 { "svca",    SC(17,1,0), SC_MASK,       PWRCOM,         { SV } },
1870 { "svcla",   SC(17,1,1), SC_MASK,       POWER,          { SV } },
1871
1872 { "b",       B(18,0,0), B_MASK,         COM,    { LI } },
1873 { "bl",      B(18,0,1), B_MASK,         COM,    { LI } },
1874 { "ba",      B(18,1,0), B_MASK,         COM,    { LIA } },
1875 { "bla",     B(18,1,1), B_MASK,         COM,    { LIA } },
1876
1877 { "mcrf",    XL(19,0),  XLBB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
1878
1879 { "blr",     XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM,   { 0 } },
1880 { "br",      XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM,   { 0 } },
1881 { "blrl",    XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM,   { 0 } },
1882 { "brl",     XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM,   { 0 } },
1883 { "bdnzlr",  XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
1884 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
1885 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM,        { 0 } },
1886 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
1887 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
1888 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM,        { 0 } },
1889 { "bdzlr",   XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM,  { 0 } },
1890 { "bdzlr-",  XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM,  { 0 } },
1891 { "bdzlr+",  XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
1892 { "bdzlrl",  XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM,  { 0 } },
1893 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM,  { 0 } },
1894 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
1895 { "bltlr",   XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1896 { "bltlr-",  XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1897 { "bltlr+",  XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1898 { "bltr",    XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1899 { "bltlrl",  XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1900 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1901 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1902 { "bltrl",   XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1903 { "bgtlr",   XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1904 { "bgtlr-",  XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1905 { "bgtlr+",  XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1906 { "bgtr",    XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1907 { "bgtlrl",  XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1908 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1909 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1910 { "bgtrl",   XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1911 { "beqlr",   XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1912 { "beqlr-",  XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1913 { "beqlr+",  XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1914 { "beqr",    XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1915 { "beqlrl",  XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1916 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1917 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1918 { "beqrl",   XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1919 { "bsolr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1920 { "bsolr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1921 { "bsolr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1922 { "bsor",    XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1923 { "bsolrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1924 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1925 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1926 { "bsorl",   XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1927 { "bunlr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1928 { "bunlr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1929 { "bunlr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1930 { "bunlrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1931 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1932 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1933 { "bgelr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1934 { "bgelr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1935 { "bgelr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1936 { "bger",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1937 { "bgelrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1938 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1939 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1940 { "bgerl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1941 { "bnllr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1942 { "bnllr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1943 { "bnllr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1944 { "bnlr",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1945 { "bnllrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1946 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1947 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1948 { "bnlrl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1949 { "blelr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1950 { "blelr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1951 { "blelr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1952 { "bler",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1953 { "blelrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1954 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1955 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1956 { "blerl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1957 { "bnglr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1958 { "bnglr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1959 { "bnglr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1960 { "bngr",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1961 { "bnglrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1962 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1963 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1964 { "bngrl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1965 { "bnelr",   XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1966 { "bnelr-",  XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1967 { "bnelr+",  XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1968 { "bner",    XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1969 { "bnelrl",  XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1970 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1971 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1972 { "bnerl",   XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1973 { "bnslr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1974 { "bnslr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1975 { "bnslr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1976 { "bnsr",    XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1977 { "bnslrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1978 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1979 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1980 { "bnsrl",   XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1981 { "bnulr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1982 { "bnulr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1983 { "bnulr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1984 { "bnulrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1985 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1986 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1987 { "btlr",    XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
1988 { "btlr-",   XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
1989 { "btlr+",   XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM,    { BI } },
1990 { "bbtr",    XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
1991 { "btlrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
1992 { "btlrl-",  XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
1993 { "btlrl+",  XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM,    { BI } },
1994 { "bbtrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
1995 { "bflr",    XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
1996 { "bflr-",   XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
1997 { "bflr+",   XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM,    { BI } },
1998 { "bbfr",    XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
1999 { "bflrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2000 { "bflrl-",  XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2001 { "bflrl+",  XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM,    { BI } },
2002 { "bbfrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
2003 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2004 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2005 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2006 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2007 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2008 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM,{ BI } },
2009 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2010 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2011 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2012 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2013 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2014 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM,{ BI } },
2015 { "bdztlr",  XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2016 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2017 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2018 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2019 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2020 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2021 { "bdzflr",  XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2022 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2023 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2024 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2025 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2026 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2027 { "bclr",    XLLK(19,16,0), XLYBB_MASK, PPCCOM,         { BO, BI } },
2028 { "bclrl",   XLLK(19,16,1), XLYBB_MASK, PPCCOM,         { BO, BI } },
2029 { "bclr+",   XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2030 { "bclrl+",  XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2031 { "bclr-",   XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2032 { "bclrl-",  XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2033 { "bcr",     XLLK(19,16,0), XLBB_MASK,  PWRCOM,         { BO, BI } },
2034 { "bcrl",    XLLK(19,16,1), XLBB_MASK,  PWRCOM,         { BO, BI } },
2035
2036 { "crnot",   XL(19,33), XL_MASK,        PPCCOM,         { BT, BA, BBA } },
2037 { "crnor",   XL(19,33), XL_MASK,        COM,            { BT, BA, BB } },
2038
2039 { "rfi",     XL(19,50), 0xffffffff,     COM,            { 0 } },
2040 { "rfci",    XL(19,51), 0xffffffff,     PPC,            { 0 } },
2041
2042 { "rfsvc",   XL(19,82), 0xffffffff,     POWER,          { 0 } },
2043
2044 { "crandc",  XL(19,129), XL_MASK,       COM,            { BT, BA, BB } },
2045
2046 { "isync",   XL(19,150), 0xffffffff,    PPCCOM,         { 0 } },
2047 { "ics",     XL(19,150), 0xffffffff,    PWRCOM,         { 0 } },
2048
2049 { "crclr",   XL(19,193), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
2050 { "crxor",   XL(19,193), XL_MASK,       COM,            { BT, BA, BB } },
2051
2052 { "crnand",  XL(19,225), XL_MASK,       COM,            { BT, BA, BB } },
2053
2054 { "crand",   XL(19,257), XL_MASK,       COM,            { BT, BA, BB } },
2055
2056 { "crset",   XL(19,289), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
2057 { "creqv",   XL(19,289), XL_MASK,       COM,            { BT, BA, BB } },
2058
2059 { "crorc",   XL(19,417), XL_MASK,       COM,            { BT, BA, BB } },
2060
2061 { "crmove",  XL(19,449), XL_MASK,       PPCCOM,         { BT, BA, BBA } },
2062 { "cror",    XL(19,449), XL_MASK,       COM,            { BT, BA, BB } },
2063
2064 { "bctr",    XLO(19,BOU,528,0), XLBOBIBB_MASK, COM,     { 0 } },
2065 { "bctrl",   XLO(19,BOU,528,1), XLBOBIBB_MASK, COM,     { 0 } },
2066 { "bltctr",  XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2067 { "bltctr-", XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2068 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2069 { "bltctrl", XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2070 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2071 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2072 { "bgtctr",  XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2073 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2074 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2075 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2076 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2077 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2078 { "beqctr",  XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2079 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2080 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2081 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2082 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2083 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2084 { "bsoctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2085 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2086 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2087 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2088 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2089 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2090 { "bunctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2091 { "bunctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2092 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2093 { "bunctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2094 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2095 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2096 { "bgectr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2097 { "bgectr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2098 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2099 { "bgectrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2100 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2101 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2102 { "bnlctr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2103 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2104 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2105 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2106 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2107 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2108 { "blectr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2109 { "blectr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2110 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2111 { "blectrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2112 { "blectrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2113 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2114 { "bngctr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2115 { "bngctr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2116 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2117 { "bngctrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2118 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2119 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2120 { "bnectr",  XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2121 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2122 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2123 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2124 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2125 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2126 { "bnsctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2127 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2128 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2129 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2130 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2131 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2132 { "bnuctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2133 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2134 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2135 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2136 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2137 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2138 { "btctr",   XLO(19,BOT,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
2139 { "btctr-",  XLO(19,BOT,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
2140 { "btctr+",  XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM,   { BI } },
2141 { "btctrl",  XLO(19,BOT,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
2142 { "btctrl-", XLO(19,BOT,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
2143 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM,   { BI } },
2144 { "bfctr",   XLO(19,BOF,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
2145 { "bfctr-",  XLO(19,BOF,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
2146 { "bfctr+",  XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM,   { BI } },
2147 { "bfctrl",  XLO(19,BOF,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
2148 { "bfctrl-", XLO(19,BOF,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
2149 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM,   { BI } },
2150 { "bcctr",   XLLK(19,528,0),     XLYBB_MASK,  PPCCOM,   { BO, BI } },
2151 { "bcctr-",  XLYLK(19,528,0,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
2152 { "bcctr+",  XLYLK(19,528,1,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
2153 { "bcctrl",  XLLK(19,528,1),     XLYBB_MASK,  PPCCOM,   { BO, BI } },
2154 { "bcctrl-", XLYLK(19,528,0,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
2155 { "bcctrl+", XLYLK(19,528,1,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
2156 { "bcc",     XLLK(19,528,0),     XLBB_MASK,   PWRCOM,   { BO, BI } },
2157 { "bccl",    XLLK(19,528,1),     XLBB_MASK,   PWRCOM,   { BO, BI } },
2158
2159 { "rlwimi",  M(20,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
2160 { "rlimi",   M(20,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
2161
2162 { "rlwimi.", M(20,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
2163 { "rlimi.",  M(20,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
2164
2165 { "rotlwi",  MME(21,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, SH } },
2166 { "clrlwi",  MME(21,31,0), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
2167 { "rlwinm",  M(21,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
2168 { "rlinm",   M(21,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
2169 { "rotlwi.", MME(21,31,1), MMBME_MASK,  PPCCOM,         { RA,RS,SH } },
2170 { "clrlwi.", MME(21,31,1), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
2171 { "rlwinm.", M(21,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
2172 { "rlinm.",  M(21,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
2173
2174 { "rlmi",    M(22,0),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
2175 { "rlmi.",   M(22,1),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
2176
2177 { "rotlw",   MME(23,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
2178 { "rlwnm",   M(23,0),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
2179 { "rlnm",    M(23,0),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
2180 { "rotlw.",  MME(23,31,1), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
2181 { "rlwnm.",  M(23,1),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
2182 { "rlnm.",   M(23,1),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
2183
2184 { "nop",     OP(24),    0xffffffff,     PPCCOM,         { 0 } },
2185 { "ori",     OP(24),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2186 { "oril",    OP(24),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2187
2188 { "oris",    OP(25),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2189 { "oriu",    OP(25),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2190
2191 { "xori",    OP(26),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2192 { "xoril",   OP(26),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2193
2194 { "xoris",   OP(27),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2195 { "xoriu",   OP(27),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2196
2197 { "andi.",   OP(28),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2198 { "andil.",  OP(28),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2199
2200 { "andis.",  OP(29),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2201 { "andiu.",  OP(29),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2202
2203 { "rotldi",  MD(30,0,0), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
2204 { "clrldi",  MD(30,0,0), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
2205 { "rldicl",  MD(30,0,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2206 { "rotldi.", MD(30,0,1), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
2207 { "clrldi.", MD(30,0,1), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
2208 { "rldicl.", MD(30,0,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2209
2210 { "rldicr",  MD(30,1,0), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
2211 { "rldicr.", MD(30,1,1), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
2212
2213 { "rldic",   MD(30,2,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2214 { "rldic.",  MD(30,2,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2215
2216 { "rldimi",  MD(30,3,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2217 { "rldimi.", MD(30,3,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2218
2219 { "rotld",   MDS(30,8,0), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
2220 { "rldcl",   MDS(30,8,0), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
2221 { "rotld.",  MDS(30,8,1), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
2222 { "rldcl.",  MDS(30,8,1), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
2223
2224 { "rldcr",   MDS(30,9,0), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
2225 { "rldcr.",  MDS(30,9,1), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
2226
2227 { "cmpw",    XCMPL(31,0,0), XCMPL_MASK, PPCCOM,         { OBF, RA, RB } },
2228 { "cmpd",    XCMPL(31,0,1), XCMPL_MASK, PPC64,          { OBF, RA, RB } },
2229 { "cmp",     X(31,0),   XCMP_MASK,      PPCONLY,        { BF, L, RA, RB } },
2230 { "cmp",     X(31,0),   XCMPL_MASK,     PWRCOM,         { BF, RA, RB } },
2231
2232 { "twlgt",   XTO(31,4,TOLGT), XTO_MASK, PPCCOM,         { RA, RB } },
2233 { "tlgt",    XTO(31,4,TOLGT), XTO_MASK, PWRCOM,         { RA, RB } },
2234 { "twllt",   XTO(31,4,TOLLT), XTO_MASK, PPCCOM,         { RA, RB } },
2235 { "tllt",    XTO(31,4,TOLLT), XTO_MASK, PWRCOM,         { RA, RB } },
2236 { "tweq",    XTO(31,4,TOEQ), XTO_MASK,  PPCCOM,         { RA, RB } },
2237 { "teq",     XTO(31,4,TOEQ), XTO_MASK,  PWRCOM,         { RA, RB } },
2238 { "twlge",   XTO(31,4,TOLGE), XTO_MASK, PPCCOM,         { RA, RB } },
2239 { "tlge",    XTO(31,4,TOLGE), XTO_MASK, PWRCOM,         { RA, RB } },
2240 { "twlnl",   XTO(31,4,TOLNL), XTO_MASK, PPCCOM,         { RA, RB } },
2241 { "tlnl",    XTO(31,4,TOLNL), XTO_MASK, PWRCOM,         { RA, RB } },
2242 { "twlle",   XTO(31,4,TOLLE), XTO_MASK, PPCCOM,         { RA, RB } },
2243 { "tlle",    XTO(31,4,TOLLE), XTO_MASK, PWRCOM,         { RA, RB } },
2244 { "twlng",   XTO(31,4,TOLNG), XTO_MASK, PPCCOM,         { RA, RB } },
2245 { "tlng",    XTO(31,4,TOLNG), XTO_MASK, PWRCOM,         { RA, RB } },
2246 { "twgt",    XTO(31,4,TOGT), XTO_MASK,  PPCCOM,         { RA, RB } },
2247 { "tgt",     XTO(31,4,TOGT), XTO_MASK,  PWRCOM,         { RA, RB } },
2248 { "twge",    XTO(31,4,TOGE), XTO_MASK,  PPCCOM,         { RA, RB } },
2249 { "tge",     XTO(31,4,TOGE), XTO_MASK,  PWRCOM,         { RA, RB } },
2250 { "twnl",    XTO(31,4,TONL), XTO_MASK,  PPCCOM,         { RA, RB } },
2251 { "tnl",     XTO(31,4,TONL), XTO_MASK,  PWRCOM,         { RA, RB } },
2252 { "twlt",    XTO(31,4,TOLT), XTO_MASK,  PPCCOM,         { RA, RB } },
2253 { "tlt",     XTO(31,4,TOLT), XTO_MASK,  PWRCOM,         { RA, RB } },
2254 { "twle",    XTO(31,4,TOLE), XTO_MASK,  PPCCOM,         { RA, RB } },
2255 { "tle",     XTO(31,4,TOLE), XTO_MASK,  PWRCOM,         { RA, RB } },
2256 { "twng",    XTO(31,4,TONG), XTO_MASK,  PPCCOM,         { RA, RB } },
2257 { "tng",     XTO(31,4,TONG), XTO_MASK,  PWRCOM,         { RA, RB } },
2258 { "twne",    XTO(31,4,TONE), XTO_MASK,  PPCCOM,         { RA, RB } },
2259 { "tne",     XTO(31,4,TONE), XTO_MASK,  PWRCOM,         { RA, RB } },
2260 { "trap",    XTO(31,4,TOU), 0xffffffff, PPCCOM,         { 0 } },
2261 { "tw",      X(31,4),   X_MASK,         PPCCOM,         { TO, RA, RB } },
2262 { "t",       X(31,4),   X_MASK,         PWRCOM,         { TO, RA, RB } },
2263
2264 { "subfc",   XO(31,8,0,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
2265 { "sf",      XO(31,8,0,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
2266 { "subc",    XO(31,8,0,0), XO_MASK,     PPC,            { RT, RB, RA } },
2267 { "subfc.",  XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
2268 { "sf.",     XO(31,8,0,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
2269 { "subc.",   XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RB, RA } },
2270 { "subfco",  XO(31,8,1,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
2271 { "sfo",     XO(31,8,1,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
2272 { "subco",   XO(31,8,1,0), XO_MASK,     PPC,            { RT, RB, RA } },
2273 { "subfco.", XO(31,8,1,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
2274 { "sfo.",    XO(31,8,1,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
2275 { "subco.",  XO(31,8,1,1), XO_MASK,     PPC,            { RT, RB, RA } },
2276
2277 { "mulhdu",  XO(31,9,0,0), XO_MASK,     PPC64,          { RT, RA, RB } },
2278 { "mulhdu.", XO(31,9,0,1), XO_MASK,     PPC64,          { RT, RA, RB } },
2279
2280 { "addc",    XO(31,10,0,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
2281 { "a",       XO(31,10,0,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
2282 { "addc.",   XO(31,10,0,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
2283 { "a.",      XO(31,10,0,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
2284 { "addco",   XO(31,10,1,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
2285 { "ao",      XO(31,10,1,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
2286 { "addco.",  XO(31,10,1,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
2287 { "ao.",     XO(31,10,1,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
2288
2289 { "mulhwu",  XO(31,11,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
2290 { "mulhwu.", XO(31,11,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
2291
2292 { "mfcr",    X(31,19),  XRARB_MASK,     COM,            { RT } },
2293
2294 { "lwarx",   X(31,20),  X_MASK,         PPC,            { RT, RA, RB } },
2295
2296 { "ldx",     X(31,21),  X_MASK,         PPC64,          { RT, RA, RB } },
2297
2298 { "lwzx",    X(31,23),  X_MASK,         PPCCOM,         { RT, RA, RB } },
2299 { "lx",      X(31,23),  X_MASK,         PWRCOM,         { RT, RA, RB } },
2300
2301 { "slw",     XRC(31,24,0), X_MASK,      PPCCOM,         { RA, RS, RB } },
2302 { "sl",      XRC(31,24,0), X_MASK,      PWRCOM,         { RA, RS, RB } },
2303 { "slw.",    XRC(31,24,1), X_MASK,      PPCCOM,         { RA, RS, RB } },
2304 { "sl.",     XRC(31,24,1), X_MASK,      PWRCOM,         { RA, RS, RB } },
2305
2306 { "cntlzw",  XRC(31,26,0), XRB_MASK,    PPCCOM,         { RA, RS } },
2307 { "cntlz",   XRC(31,26,0), XRB_MASK,    PWRCOM,         { RA, RS } },
2308 { "cntlzw.", XRC(31,26,1), XRB_MASK,    PPCCOM,         { RA, RS } },
2309 { "cntlz.",  XRC(31,26,1), XRB_MASK,    PWRCOM,         { RA, RS } },
2310
2311 { "sld",     XRC(31,27,0), X_MASK,      PPC64,          { RA, RS, RB } },
2312 { "sld.",    XRC(31,27,1), X_MASK,      PPC64,          { RA, RS, RB } },
2313
2314 { "and",     XRC(31,28,0), X_MASK,      COM,            { RA, RS, RB } },
2315 { "and.",    XRC(31,28,1), X_MASK,      COM,            { RA, RS, RB } },
2316
2317 { "maskg",   XRC(31,29,0), X_MASK,      M601,           { RA, RS, RB } },
2318 { "maskg.",  XRC(31,29,1), X_MASK,      M601,           { RA, RS, RB } },
2319
2320 { "cmplw",   XCMPL(31,32,0), XCMPL_MASK, PPCCOM,        { OBF, RA, RB } },
2321 { "cmpld",   XCMPL(31,32,1), XCMPL_MASK, PPC64,         { OBF, RA, RB } },
2322 { "cmpl",    X(31,32),  XCMP_MASK,       PPCONLY,       { BF, L, RA, RB } },
2323 { "cmpl",    X(31,32),  XCMPL_MASK,      PWRCOM,        { BF, RA, RB } },
2324
2325 { "subf",    XO(31,40,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
2326 { "sub",     XO(31,40,0,0), XO_MASK,    PPC,            { RT, RB, RA } },
2327 { "subf.",   XO(31,40,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
2328 { "sub.",    XO(31,40,0,1), XO_MASK,    PPC,            { RT, RB, RA } },
2329 { "subfo",   XO(31,40,1,0), XO_MASK,    PPC,            { RT, RA, RB } },
2330 { "subo",    XO(31,40,1,0), XO_MASK,    PPC,            { RT, RB, RA } },
2331 { "subfo.",  XO(31,40,1,1), XO_MASK,    PPC,            { RT, RA, RB } },
2332 { "subo.",   XO(31,40,1,1), XO_MASK,    PPC,            { RT, RB, RA } },
2333
2334 { "ldux",    X(31,53),  X_MASK,         PPC64,          { RT, RAL, RB } },
2335
2336 { "dcbst",   X(31,54),  XRT_MASK,       PPC,            { RA, RB } },
2337
2338 { "lwzux",   X(31,55),  X_MASK,         PPCCOM,         { RT, RAL, RB } },
2339 { "lux",     X(31,55),  X_MASK,         PWRCOM,         { RT, RA, RB } },
2340
2341 { "cntlzd",  XRC(31,58,0), XRB_MASK,    PPC64,          { RA, RS } },
2342 { "cntlzd.", XRC(31,58,1), XRB_MASK,    PPC64,          { RA, RS } },
2343
2344 { "andc",    XRC(31,60,0), X_MASK,      COM,    { RA, RS, RB } },
2345 { "andc.",   XRC(31,60,1), X_MASK,      COM,    { RA, RS, RB } },
2346
2347 { "tdlgt",   XTO(31,68,TOLGT), XTO_MASK, PPC64,         { RA, RB } },
2348 { "tdllt",   XTO(31,68,TOLLT), XTO_MASK, PPC64,         { RA, RB } },
2349 { "tdeq",    XTO(31,68,TOEQ), XTO_MASK,  PPC64,         { RA, RB } },
2350 { "tdlge",   XTO(31,68,TOLGE), XTO_MASK, PPC64,         { RA, RB } },
2351 { "tdlnl",   XTO(31,68,TOLNL), XTO_MASK, PPC64,         { RA, RB } },
2352 { "tdlle",   XTO(31,68,TOLLE), XTO_MASK, PPC64,         { RA, RB } },
2353 { "tdlng",   XTO(31,68,TOLNG), XTO_MASK, PPC64,         { RA, RB } },
2354 { "tdgt",    XTO(31,68,TOGT), XTO_MASK,  PPC64,         { RA, RB } },
2355 { "tdge",    XTO(31,68,TOGE), XTO_MASK,  PPC64,         { RA, RB } },
2356 { "tdnl",    XTO(31,68,TONL), XTO_MASK,  PPC64,         { RA, RB } },
2357 { "tdlt",    XTO(31,68,TOLT), XTO_MASK,  PPC64,         { RA, RB } },
2358 { "tdle",    XTO(31,68,TOLE), XTO_MASK,  PPC64,         { RA, RB } },
2359 { "tdng",    XTO(31,68,TONG), XTO_MASK,  PPC64,         { RA, RB } },
2360 { "tdne",    XTO(31,68,TONE), XTO_MASK,  PPC64,         { RA, RB } },
2361 { "td",      X(31,68),  X_MASK,          PPC64,         { TO, RA, RB } },
2362
2363 { "mulhd",   XO(31,73,0,0), XO_MASK,     PPC64,         { RT, RA, RB } },
2364 { "mulhd.",  XO(31,73,0,1), XO_MASK,     PPC64,         { RT, RA, RB } },
2365
2366 { "mulhw",   XO(31,75,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
2367 { "mulhw.",  XO(31,75,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
2368
2369 { "mfmsr",   X(31,83),  XRARB_MASK,     COM,            { RT } },
2370
2371 { "ldarx",   X(31,84),  X_MASK,         PPC64,          { RT, RA, RB } },
2372
2373 { "dcbf",    X(31,86),  XRT_MASK,       PPC,            { RA, RB } },
2374
2375 { "lbzx",    X(31,87),  X_MASK,         COM,            { RT, RA, RB } },
2376
2377 { "neg",     XO(31,104,0,0), XORB_MASK, COM,            { RT, RA } },
2378 { "neg.",    XO(31,104,0,1), XORB_MASK, COM,            { RT, RA } },
2379 { "nego",    XO(31,104,1,0), XORB_MASK, COM,            { RT, RA } },
2380 { "nego.",   XO(31,104,1,1), XORB_MASK, COM,            { RT, RA } },
2381
2382 { "mul",     XO(31,107,0,0), XO_MASK,   M601,           { RT, RA, RB } },
2383 { "mul.",    XO(31,107,0,1), XO_MASK,   M601,           { RT, RA, RB } },
2384 { "mulo",    XO(31,107,1,0), XO_MASK,   M601,           { RT, RA, RB } },
2385 { "mulo.",   XO(31,107,1,1), XO_MASK,   M601,           { RT, RA, RB } },
2386
2387 { "clf",     X(31,118), XRB_MASK,       POWER,          { RT, RA } },
2388
2389 { "lbzux",   X(31,119), X_MASK,         COM,            { RT, RAL, RB } },
2390
2391 { "not",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RBS } },
2392 { "nor",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RB } },
2393 { "not.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RBS } },
2394 { "nor.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RB } },
2395
2396 { "wrtee",   X(31,131), XRARB_MASK,     PPC403,         { RS } },
2397
2398 { "subfe",   XO(31,136,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2399 { "sfe",     XO(31,136,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2400 { "subfe.",  XO(31,136,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2401 { "sfe.",    XO(31,136,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2402 { "subfeo",  XO(31,136,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2403 { "sfeo",    XO(31,136,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2404 { "subfeo.", XO(31,136,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2405 { "sfeo.",   XO(31,136,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2406
2407 { "adde",    XO(31,138,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2408 { "ae",      XO(31,138,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2409 { "adde.",   XO(31,138,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2410 { "ae.",     XO(31,138,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2411 { "addeo",   XO(31,138,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2412 { "aeo",     XO(31,138,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2413 { "addeo.",  XO(31,138,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2414 { "aeo.",    XO(31,138,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2415
2416 { "mtcr",    XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM,      { RS }},
2417 { "mtcrf",   X(31,144), XFXFXM_MASK,    COM,            { FXM, RS } },
2418
2419 { "mtmsr",   X(31,146), XRARB_MASK,     COM,            { RS } },
2420
2421 { "stdx",    X(31,149), X_MASK,         PPC64,          { RS, RA, RB } },
2422
2423 { "stwcx.",  XRC(31,150,1), X_MASK,     PPC,            { RS, RA, RB } },
2424
2425 { "stwx",    X(31,151), X_MASK,         PPCCOM,         { RS, RA, RB } },
2426 { "stx",     X(31,151), X_MASK,         PWRCOM,         { RS, RA, RB } },
2427
2428 { "slq",     XRC(31,152,0), X_MASK,     M601,           { RA, RS, RB } },
2429 { "slq.",    XRC(31,152,1), X_MASK,     M601,           { RA, RS, RB } },
2430
2431 { "sle",     XRC(31,153,0), X_MASK,     M601,           { RA, RS, RB } },
2432 { "sle.",    XRC(31,153,1), X_MASK,     M601,           { RA, RS, RB } },
2433
2434 { "wrteei",  X(31,163), XE_MASK,        PPC403,         { E } },
2435
2436 { "stdux",   X(31,181), X_MASK,         PPC64,          { RS, RAS, RB } },
2437
2438 { "stwux",   X(31,183), X_MASK,         PPCCOM,         { RS, RAS, RB } },
2439 { "stux",    X(31,183), X_MASK,         PWRCOM,         { RS, RA, RB } },
2440
2441 { "sliq",    XRC(31,184,0), X_MASK,     M601,           { RA, RS, SH } },
2442 { "sliq.",   XRC(31,184,1), X_MASK,     M601,           { RA, RS, SH } },
2443
2444 { "subfze",  XO(31,200,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
2445 { "sfze",    XO(31,200,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
2446 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
2447 { "sfze.",   XO(31,200,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
2448 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
2449 { "sfzeo",   XO(31,200,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
2450 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
2451 { "sfzeo.",  XO(31,200,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
2452
2453 { "addze",   XO(31,202,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
2454 { "aze",     XO(31,202,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
2455 { "addze.",  XO(31,202,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
2456 { "aze.",    XO(31,202,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
2457 { "addzeo",  XO(31,202,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
2458 { "azeo",    XO(31,202,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
2459 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
2460 { "azeo.",   XO(31,202,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
2461
2462 { "mtsr",    X(31,210), XRB_MASK|(1<<20), COM32,        { SR, RS } },
2463
2464 { "stdcx.",  XRC(31,214,1), X_MASK,     PPC64,          { RS, RA, RB } },
2465
2466 { "stbx",    X(31,215), X_MASK,         COM,    { RS, RA, RB } },
2467
2468 { "sllq",    XRC(31,216,0), X_MASK,     M601,           { RA, RS, RB } },
2469 { "sllq.",   XRC(31,216,1), X_MASK,     M601,           { RA, RS, RB } },
2470
2471 { "sleq",    XRC(31,217,0), X_MASK,     M601,           { RA, RS, RB } },
2472 { "sleq.",   XRC(31,217,1), X_MASK,     M601,           { RA, RS, RB } },
2473
2474 { "subfme",  XO(31,232,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
2475 { "sfme",    XO(31,232,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
2476 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
2477 { "sfme.",   XO(31,232,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
2478 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
2479 { "sfmeo",   XO(31,232,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
2480 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
2481 { "sfmeo.",  XO(31,232,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
2482
2483 { "mulld",   XO(31,233,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
2484 { "mulld.",  XO(31,233,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
2485 { "mulldo",  XO(31,233,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
2486 { "mulldo.", XO(31,233,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
2487
2488 { "addme",   XO(31,234,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
2489 { "ame",     XO(31,234,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
2490 { "addme.",  XO(31,234,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
2491 { "ame.",    XO(31,234,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
2492 { "addmeo",  XO(31,234,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
2493 { "ameo",    XO(31,234,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
2494 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
2495 { "ameo.",   XO(31,234,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
2496
2497 { "mullw",   XO(31,235,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2498 { "muls",    XO(31,235,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2499 { "mullw.",  XO(31,235,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2500 { "muls.",   XO(31,235,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2501 { "mullwo",  XO(31,235,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2502 { "mulso",   XO(31,235,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2503 { "mullwo.", XO(31,235,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2504 { "mulso.",  XO(31,235,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2505
2506 { "mtsrin",  X(31,242), XRA_MASK,       PPC32,          { RS, RB } },
2507 { "mtsri",   X(31,242), XRA_MASK,       POWER32,        { RS, RB } },
2508
2509 { "dcbtst",  X(31,246), XRT_MASK,       PPC,            { RA, RB } },
2510
2511 { "stbux",   X(31,247), X_MASK,         COM,            { RS, RAS, RB } },
2512
2513 { "slliq",   XRC(31,248,0), X_MASK,     M601,           { RA, RS, SH } },
2514 { "slliq.",  XRC(31,248,1), X_MASK,     M601,           { RA, RS, SH } },
2515
2516 { "doz",     XO(31,264,0,0), XO_MASK,   M601,           { RT, RA, RB } },
2517 { "doz.",    XO(31,264,0,1), XO_MASK,   M601,           { RT, RA, RB } },
2518 { "dozo",    XO(31,264,1,0), XO_MASK,   M601,           { RT, RA, RB } },
2519 { "dozo.",   XO(31,264,1,1), XO_MASK,   M601,           { RT, RA, RB } },
2520
2521 { "add",     XO(31,266,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2522 { "cax",     XO(31,266,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2523 { "add.",    XO(31,266,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2524 { "cax.",    XO(31,266,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2525 { "addo",    XO(31,266,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2526 { "caxo",    XO(31,266,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2527 { "addo.",   XO(31,266,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2528 { "caxo.",   XO(31,266,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2529
2530 { "lscbx",   XRC(31,277,0), X_MASK,     M601,           { RT, RA, RB } },
2531 { "lscbx.",  XRC(31,277,1), X_MASK,     M601,           { RT, RA, RB } },
2532
2533 { "dcbt",    X(31,278), XRT_MASK,       PPC,            { RA, RB } },
2534
2535 { "lhzx",    X(31,279), X_MASK,         COM,            { RT, RA, RB } },
2536
2537 { "icbt",    X(31,262), XRT_MASK,       PPC,            { RA, RB } },
2538
2539 { "eqv",     XRC(31,284,0), X_MASK,     COM,            { RA, RS, RB } },
2540 { "eqv.",    XRC(31,284,1), X_MASK,     COM,            { RA, RS, RB } },
2541
2542 { "tlbie",   X(31,306), XRTRA_MASK,     PPC,            { RB } },
2543 { "tlbi",    X(31,306), XRT_MASK,       POWER,          { RA, RB } },
2544
2545 { "eciwx",   X(31,310), X_MASK,         PPC,            { RT, RA, RB } },
2546
2547 { "lhzux",   X(31,311), X_MASK,         COM,            { RT, RAL, RB } },
2548
2549 { "xor",     XRC(31,316,0), X_MASK,     COM,            { RA, RS, RB } },
2550 { "xor.",    XRC(31,316,1), X_MASK,     COM,            { RA, RS, RB } },
2551
2552 { "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403,        { RT } },
2553 { "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403,        { RT } },
2554 { "mfbr0",   XSPR(31,323,128), XSPR_MASK, PPC403,       { RT } },
2555 { "mfbr1",   XSPR(31,323,129), XSPR_MASK, PPC403,       { RT } },
2556 { "mfbr2",   XSPR(31,323,130), XSPR_MASK, PPC403,       { RT } },
2557 { "mfbr3",   XSPR(31,323,131), XSPR_MASK, PPC403,       { RT } },
2558 { "mfbr4",   XSPR(31,323,132), XSPR_MASK, PPC403,       { RT } },
2559 { "mfbr5",   XSPR(31,323,133), XSPR_MASK, PPC403,       { RT } },
2560 { "mfbr6",   XSPR(31,323,134), XSPR_MASK, PPC403,       { RT } },
2561 { "mfbr7",   XSPR(31,323,135), XSPR_MASK, PPC403,       { RT } },
2562 { "mfbear",  XSPR(31,323,144), XSPR_MASK, PPC403,       { RT } },
2563 { "mfbesr",  XSPR(31,323,145), XSPR_MASK, PPC403,       { RT } },
2564 { "mfiocr",  XSPR(31,323,160), XSPR_MASK, PPC403,       { RT } },
2565 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403,      { RT } },
2566 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403,      { RT } },
2567 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403,      { RT } },
2568 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403,      { RT } },
2569 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403,      { RT } },
2570 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403,      { RT } },
2571 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403,      { RT } },
2572 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403,      { RT } },
2573 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403,      { RT } },
2574 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403,      { RT } },
2575 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403,      { RT } },
2576 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403,      { RT } },
2577 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403,      { RT } },
2578 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403,      { RT } },
2579 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403,      { RT } },
2580 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403,      { RT } },
2581 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403,      { RT } },
2582 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403,      { RT } },
2583 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403,      { RT } },
2584 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403,      { RT } },
2585 { "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403,       { RT } },
2586 { "mfdcr",   X(31,323), X_MASK,         PPC,            { RT, SPR } },
2587
2588 { "div",     XO(31,331,0,0), XO_MASK,   M601,           { RT, RA, RB } },
2589 { "div.",    XO(31,331,0,1), XO_MASK,   M601,           { RT, RA, RB } },
2590 { "divo",    XO(31,331,1,0), XO_MASK,   M601,           { RT, RA, RB } },
2591 { "divo.",   XO(31,331,1,1), XO_MASK,   M601,           { RT, RA, RB } },
2592
2593 { "mfmq",     XSPR(31,339,0),   XSPR_MASK, M601,        { RT } },
2594 { "mfxer",    XSPR(31,339,1),   XSPR_MASK, COM,         { RT } },
2595 { "mfrtcu",   XSPR(31,339,4),   XSPR_MASK, COM,         { RT } },
2596 { "mfrtcl",   XSPR(31,339,5),   XSPR_MASK, COM,         { RT } },
2597 { "mfdec",    XSPR(31,339,6),   XSPR_MASK, MFDEC1,      { RT } },
2598 { "mflr",     XSPR(31,339,8),   XSPR_MASK, COM,         { RT } },
2599 { "mfctr",    XSPR(31,339,9),   XSPR_MASK, COM,         { RT } },
2600 { "mftid",    XSPR(31,339,17),  XSPR_MASK, POWER,       { RT } },
2601 { "mfdsisr",  XSPR(31,339,18),  XSPR_MASK, COM,         { RT } },
2602 { "mfdar",    XSPR(31,339,19),  XSPR_MASK, COM,         { RT } },
2603 { "mfdec",    XSPR(31,339,22),  XSPR_MASK, MFDEC2,      { RT } },
2604 { "mfsdr0",   XSPR(31,339,24),  XSPR_MASK, POWER,       { RT } },
2605 { "mfsdr1",   XSPR(31,339,25),  XSPR_MASK, COM,         { RT } },
2606 { "mfsrr0",   XSPR(31,339,26),  XSPR_MASK, COM,         { RT } },
2607 { "mfsrr1",   XSPR(31,339,27),  XSPR_MASK, COM,         { RT } },
2608 { "mfcmpa",   XSPR(31,339,144), XSPR_MASK, PPC860,      { RT } },
2609 { "mfcmpb",   XSPR(31,339,145), XSPR_MASK, PPC860,      { RT } },
2610 { "mfcmpc",   XSPR(31,339,146), XSPR_MASK, PPC860,      { RT } },
2611 { "mfcmpd",   XSPR(31,339,147), XSPR_MASK, PPC860,      { RT } },
2612 { "mficr",    XSPR(31,339,148), XSPR_MASK, PPC860,      { RT } },
2613 { "mfder",    XSPR(31,339,149), XSPR_MASK, PPC860,      { RT } },
2614 { "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860,      { RT } },
2615 { "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860,      { RT } },
2616 { "mfcmpe",   XSPR(31,339,152), XSPR_MASK, PPC860,      { RT } },
2617 { "mfcmpf",   XSPR(31,339,153), XSPR_MASK, PPC860,      { RT } },
2618 { "mfcmpg",   XSPR(31,339,154), XSPR_MASK, PPC860,      { RT } },
2619 { "mfcmph",   XSPR(31,339,155), XSPR_MASK, PPC860,      { RT } },
2620 { "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860,      { RT } },
2621 { "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860,      { RT } },
2622 { "mfictrl",  XSPR(31,339,158), XSPR_MASK, PPC860,      { RT } },
2623 { "mfbar",    XSPR(31,339,159), XSPR_MASK, PPC860,      { RT } },
2624 { "mfsprg",   XSPR(31,339,272), XSPRG_MASK, PPC,        { RT, SPRG } },
2625 { "mfsprg0",  XSPR(31,339,272), XSPR_MASK, PPC,         { RT } },
2626 { "mfsprg1",  XSPR(31,339,273), XSPR_MASK, PPC,         { RT } },
2627 { "mfsprg2",  XSPR(31,339,274), XSPR_MASK, PPC,         { RT } },
2628 { "mfsprg3",  XSPR(31,339,275), XSPR_MASK, PPC,         { RT } },
2629 { "mfasr",    XSPR(31,339,280), XSPR_MASK, PPC64,       { RT } },
2630 { "mfear",    XSPR(31,339,282), XSPR_MASK, PPC,         { RT } },
2631 { "mfpvr",    XSPR(31,339,287), XSPR_MASK, PPC,         { RT } },
2632 { "mfibatu",  XSPR(31,339,528), XSPRBAT_MASK, PPC,      { RT, SPRBAT } },
2633 { "mfibatl",  XSPR(31,339,529), XSPRBAT_MASK, PPC,      { RT, SPRBAT } },
2634 { "mfdbatu",  XSPR(31,339,536), XSPRBAT_MASK, PPC,      { RT, SPRBAT } },
2635 { "mfdbatl",  XSPR(31,339,537), XSPRBAT_MASK, PPC,      { RT, SPRBAT } },
2636 { "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860,      { RT } },
2637 { "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860,      { RT } },
2638 { "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860,      { RT } },
2639 { "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860,      { RT } },
2640 { "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860,      { RT } },
2641 { "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860,      { RT } },
2642 { "mfdpdr",   XSPR(31,339,630), XSPR_MASK, PPC860,      { RT } },
2643 { "mfdpir",   XSPR(31,339,631), XSPR_MASK, PPC860,      { RT } },
2644 { "mfimmr",   XSPR(31,339,638), XSPR_MASK, PPC860,      { RT } },
2645 { "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860,      { RT } },
2646 { "mfmi_ap",  XSPR(31,339,786), XSPR_MASK, PPC860,      { RT } },
2647 { "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860,      { RT } },
2648 { "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860,      { RT } },
2649 { "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860,      { RT } },
2650 { "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860,      { RT } },
2651 { "mfm_casid",XSPR(31,339,793), XSPR_MASK, PPC860,      { RT } },
2652 { "mfmd_ap",  XSPR(31,339,794), XSPR_MASK, PPC860,      { RT } },
2653 { "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860,      { RT } },
2654 { "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860,      { RT } },
2655 { "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860,      { RT } },
2656 { "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860,      { RT } },
2657 { "mfm_tw",   XSPR(31,339,799), XSPR_MASK, PPC860,      { RT } },
2658 { "mfmi_dbcam",XSPR(31,339,816), XSPR_MASK, PPC860,     { RT } },
2659 { "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860,    { RT } },
2660 { "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860,    { RT } },
2661 { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860,    { RT } },
2662 { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860,    { RT } },
2663 { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860,    { RT } },
2664 { "mfzpr",   XSPR(31,339,944), XSPR_MASK, PPC403,       { RT } },
2665 { "mfpid",   XSPR(31,339,945), XSPR_MASK, PPC403,       { RT } },
2666 { "mficdbdr",XSPR(31,339,979), XSPR_MASK, PPC403,       { RT } },
2667 { "mfummcr0",   XSPR(31,339,936),  XSPR_MASK, PPC750,   { RT } },
2668 { "mfupmc1",    XSPR(31,339,937),  XSPR_MASK, PPC750,   { RT } },
2669 { "mfupmc2",    XSPR(31,339,938),  XSPR_MASK, PPC750,   { RT } },
2670 { "mfusia",     XSPR(31,339,939),  XSPR_MASK, PPC750,   { RT } },
2671 { "mfummcr1",   XSPR(31,339,940),  XSPR_MASK, PPC750,   { RT } },
2672 { "mfupmc3",    XSPR(31,339,941),  XSPR_MASK, PPC750,   { RT } },
2673 { "mfupmc4",    XSPR(31,339,942),  XSPR_MASK, PPC750,   { RT } },
2674 { "mfmmcr0",    XSPR(31,339,952),  XSPR_MASK, PPC750,   { RT } },
2675 { "mfpmc1",     XSPR(31,339,953),  XSPR_MASK, PPC750,   { RT } },
2676 { "mfpmc2",     XSPR(31,339,954),  XSPR_MASK, PPC750,   { RT } },
2677 { "mfsia",      XSPR(31,339,955),  XSPR_MASK, PPC750,   { RT } },
2678 { "mfmmcr1",    XSPR(31,339,956),  XSPR_MASK, PPC750,   { RT } },
2679 { "mfpmc3",     XSPR(31,339,957),  XSPR_MASK, PPC750,   { RT } },
2680 { "mfpmc4",     XSPR(31,339,958),  XSPR_MASK, PPC750,   { RT } },
2681 { "mfesr",   XSPR(31,339,980), XSPR_MASK, PPC403,       { RT } },
2682 { "mfdear",  XSPR(31,339,981), XSPR_MASK, PPC403,       { RT } },
2683 { "mfevpr",  XSPR(31,339,982), XSPR_MASK, PPC403,       { RT } },
2684 { "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403,       { RT } },
2685 { "mftsr",   XSPR(31,339,984), XSPR_MASK, PPC403,       { RT } },
2686 { "mftcr",   XSPR(31,339,986), XSPR_MASK, PPC403,       { RT } },
2687 { "mfpit",   XSPR(31,339,987), XSPR_MASK, PPC403,       { RT } },
2688 { "mftbhi",  XSPR(31,339,988), XSPR_MASK, PPC403,       { RT } },
2689 { "mftblo",  XSPR(31,339,989), XSPR_MASK, PPC403,       { RT } },
2690 { "mfsrr2",  XSPR(31,339,990), XSPR_MASK, PPC403,       { RT } },
2691 { "mfsrr3",  XSPR(31,339,991), XSPR_MASK, PPC403,       { RT } },
2692 { "mfdbsr",  XSPR(31,339,1008), XSPR_MASK, PPC403,      { RT } },
2693 { "mfiac1",  XSPR(31,339,1012), XSPR_MASK, PPC403,      { RT } },
2694 { "mfiac2",  XSPR(31,339,1013), XSPR_MASK, PPC403,      { RT } },
2695 { "mfdac1",  XSPR(31,339,1014), XSPR_MASK, PPC403,      { RT } },
2696 { "mfdac2",  XSPR(31,339,1015), XSPR_MASK, PPC403,      { RT } },
2697 { "mfdccr",  XSPR(31,339,1018), XSPR_MASK, PPC403,      { RT } },
2698 { "mficcr",  XSPR(31,339,1019), XSPR_MASK, PPC403,      { RT } },
2699 { "mfpbl1",  XSPR(31,339,1020), XSPR_MASK, PPC403,      { RT } },
2700 { "mfpbu1",  XSPR(31,339,1021), XSPR_MASK, PPC403,      { RT } },
2701 { "mfpbl2",  XSPR(31,339,1022), XSPR_MASK, PPC403,      { RT } },
2702 { "mfpbu2",  XSPR(31,339,1023), XSPR_MASK, PPC403,      { RT } },
2703 { "mfl2cr",     XSPR(31,339,1017), XSPR_MASK, PPC750,   { RT } },
2704 { "mfictc",     XSPR(31,339,1019), XSPR_MASK, PPC750,   { RT } },
2705 { "mfthrm1",    XSPR(31,339,1020), XSPR_MASK, PPC750,   { RT } },
2706 { "mfthrm2",    XSPR(31,339,1021), XSPR_MASK, PPC750,   { RT } },
2707 { "mfthrm3",    XSPR(31,339,1022), XSPR_MASK, PPC750,   { RT } },
2708 { "mfspr",   X(31,339), X_MASK,         COM,            { RT, SPR } },
2709
2710 { "lwax",    X(31,341), X_MASK,         PPC64,          { RT, RA, RB } },
2711
2712 { "lhax",    X(31,343), X_MASK,         COM,            { RT, RA, RB } },
2713
2714 { "dccci",   X(31,454), XRT_MASK,       PPC,            { RA, RB } },
2715
2716 { "abs",     XO(31,360,0,0), XORB_MASK, M601,           { RT, RA } },
2717 { "abs.",    XO(31,360,0,1), XORB_MASK, M601,           { RT, RA } },
2718 { "abso",    XO(31,360,1,0), XORB_MASK, M601,           { RT, RA } },
2719 { "abso.",   XO(31,360,1,1), XORB_MASK, M601,           { RT, RA } },
2720
2721 { "divs",    XO(31,363,0,0), XO_MASK,   M601,           { RT, RA, RB } },
2722 { "divs.",   XO(31,363,0,1), XO_MASK,   M601,           { RT, RA, RB } },
2723 { "divso",   XO(31,363,1,0), XO_MASK,   M601,           { RT, RA, RB } },
2724 { "divso.",  XO(31,363,1,1), XO_MASK,   M601,           { RT, RA, RB } },
2725
2726 { "tlbia",   X(31,370), 0xffffffff,     PPC,            { 0 } },
2727
2728 { "mftbu",   XSPR(31,371,269), XSPR_MASK, PPC,          { RT } },
2729 { "mftb",    X(31,371), X_MASK,         PPC,            { RT, TBR } },
2730
2731 { "lwaux",   X(31,373), X_MASK,         PPC64,          { RT, RAL, RB } },
2732
2733 { "lhaux",   X(31,375), X_MASK,         COM,            { RT, RAL, RB } },
2734
2735 { "sthx",    X(31,407), X_MASK,         COM,            { RS, RA, RB } },
2736
2737 { "lfqx",    X(31,791), X_MASK,         POWER2,         { FRT, RA, RB } },
2738
2739 { "lfqux",   X(31,823), X_MASK,         POWER2,         { FRT, RA, RB } },
2740
2741 { "stfqx",   X(31,919), X_MASK,         POWER2,         { FRS, RA, RB } },
2742
2743 { "stfqux",  X(31,951), X_MASK,         POWER2,         { FRS, RA, RB } },
2744
2745 { "orc",     XRC(31,412,0), X_MASK,     COM,            { RA, RS, RB } },
2746 { "orc.",    XRC(31,412,1), X_MASK,     COM,            { RA, RS, RB } },
2747
2748 { "sradi",   XS(31,413,0), XS_MASK,     PPC64,          { RA, RS, SH6 } },
2749 { "sradi.",  XS(31,413,1), XS_MASK,     PPC64,          { RA, RS, SH6 } },
2750
2751 { "slbie",   X(31,434), XRTRA_MASK,     PPC64,          { RB } },
2752
2753 { "ecowx",   X(31,438), X_MASK,         PPC,            { RT, RA, RB } },
2754
2755 { "sthux",   X(31,439), X_MASK,         COM,            { RS, RAS, RB } },
2756
2757 { "mr",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RBS } },
2758 { "or",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RB } },
2759 { "mr.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RBS } },
2760 { "or.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RB } },
2761
2762 { "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403,        { RT } },
2763 { "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403,        { RT } },
2764 { "mtbr0",   XSPR(31,451,128), XSPR_MASK, PPC403,       { RT } },
2765 { "mtbr1",   XSPR(31,451,129), XSPR_MASK, PPC403,       { RT } },
2766 { "mtbr2",   XSPR(31,451,130), XSPR_MASK, PPC403,       { RT } },
2767 { "mtbr3",   XSPR(31,451,131), XSPR_MASK, PPC403,       { RT } },
2768 { "mtbr4",   XSPR(31,451,132), XSPR_MASK, PPC403,       { RT } },
2769 { "mtbr5",   XSPR(31,451,133), XSPR_MASK, PPC403,       { RT } },
2770 { "mtbr6",   XSPR(31,451,134), XSPR_MASK, PPC403,       { RT } },
2771 { "mtbr7",   XSPR(31,451,135), XSPR_MASK, PPC403,       { RT } },
2772 { "mtbear",  XSPR(31,451,144), XSPR_MASK, PPC403,       { RT } },
2773 { "mtbesr",  XSPR(31,451,145), XSPR_MASK, PPC403,       { RT } },
2774 { "mtiocr",  XSPR(31,451,160), XSPR_MASK, PPC403,       { RT } },
2775 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403,      { RT } },
2776 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403,      { RT } },
2777 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403,      { RT } },
2778 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403,      { RT } },
2779 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403,      { RT } },
2780 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403,      { RT } },
2781 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403,      { RT } },
2782 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403,      { RT } },
2783 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403,      { RT } },
2784 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403,      { RT } },
2785 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403,      { RT } },
2786 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403,      { RT } },
2787 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403,      { RT } },
2788 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403,      { RT } },
2789 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403,      { RT } },
2790 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403,      { RT } },
2791 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403,      { RT } },
2792 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403,      { RT } },
2793 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403,      { RT } },
2794 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403,      { RT } },
2795 { "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403,       { RT } },
2796 { "mtummcr0",   XSPR(31,451,936),  XSPR_MASK, PPC750,   { RT } },
2797 { "mtupmc1",    XSPR(31,451,937),  XSPR_MASK, PPC750,   { RT } },
2798 { "mtupmc2",    XSPR(31,451,938),  XSPR_MASK, PPC750,   { RT } },
2799 { "mtusia",     XSPR(31,451,939),  XSPR_MASK, PPC750,   { RT } },
2800 { "mtummcr1",   XSPR(31,451,940),  XSPR_MASK, PPC750,   { RT } },
2801 { "mtupmc3",    XSPR(31,451,941),  XSPR_MASK, PPC750,   { RT } },
2802 { "mtupmc4",    XSPR(31,451,942),  XSPR_MASK, PPC750,   { RT } },
2803 { "mtmmcr0",    XSPR(31,451,952),  XSPR_MASK, PPC750,   { RT } },
2804 { "mtpmc1",     XSPR(31,451,953),  XSPR_MASK, PPC750,   { RT } },
2805 { "mtpmc2",     XSPR(31,451,954),  XSPR_MASK, PPC750,   { RT } },
2806 { "mtsia",      XSPR(31,451,955),  XSPR_MASK, PPC750,   { RT } },
2807 { "mtmmcr1",    XSPR(31,451,956),  XSPR_MASK, PPC750,   { RT } },
2808 { "mtpmc3",     XSPR(31,451,957),  XSPR_MASK, PPC750,   { RT } },
2809 { "mtpmc4",     XSPR(31,451,958),  XSPR_MASK, PPC750,   { RT } },
2810 { "mtl2cr",     XSPR(31,451,1017), XSPR_MASK, PPC750,   { RT } },
2811 { "mtictc",     XSPR(31,451,1019), XSPR_MASK, PPC750,   { RT } },
2812 { "mtthrm1",    XSPR(31,451,1020), XSPR_MASK, PPC750,   { RT } },
2813 { "mtthrm2",    XSPR(31,451,1021), XSPR_MASK, PPC750,   { RT } },
2814 { "mtthrm3",    XSPR(31,451,1022), XSPR_MASK, PPC750,   { RT } },
2815 { "mtdcr",   X(31,451), X_MASK,         PPC,            { SPR, RS } },
2816
2817 { "divdu",   XO(31,457,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
2818 { "divdu.",  XO(31,457,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
2819 { "divduo",  XO(31,457,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
2820 { "divduo.", XO(31,457,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
2821
2822 { "divwu",   XO(31,459,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
2823 { "divwu.",  XO(31,459,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
2824 { "divwuo",  XO(31,459,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
2825 { "divwuo.", XO(31,459,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
2826
2827 { "mtmq",    XSPR(31,467,0),   XSPR_MASK,    M601,      { RS } },
2828 { "mtxer",   XSPR(31,467,1),   XSPR_MASK,    COM,       { RS } },
2829 { "mtlr",    XSPR(31,467,8),   XSPR_MASK,    COM,       { RS } },
2830 { "mtctr",   XSPR(31,467,9),   XSPR_MASK,    COM,       { RS } },
2831 { "mttid",   XSPR(31,467,17),  XSPR_MASK,    POWER,     { RS } },
2832 { "mtdsisr", XSPR(31,467,18),  XSPR_MASK,    COM,       { RS } },
2833 { "mtdar",   XSPR(31,467,19),  XSPR_MASK,    COM,       { RS } },
2834 { "mtrtcu",  XSPR(31,467,20),  XSPR_MASK,    COM,       { RS } },
2835 { "mtrtcl",  XSPR(31,467,21),  XSPR_MASK,    COM,       { RS } },
2836 { "mtdec",   XSPR(31,467,22),  XSPR_MASK,    COM,       { RS } },
2837 { "mtsdr0",  XSPR(31,467,24),  XSPR_MASK,    POWER,     { RS } },
2838 { "mtsdr1",  XSPR(31,467,25),  XSPR_MASK,    COM,       { RS } },
2839 { "mtsrr0",  XSPR(31,467,26),  XSPR_MASK,    COM,       { RS } },
2840 { "mtsrr1",  XSPR(31,467,27),  XSPR_MASK,    COM,       { RS } },
2841 { "mtcmpa",   XSPR(31,467,144), XSPR_MASK, PPC860,      { RT } },
2842 { "mtcmpb",   XSPR(31,467,145), XSPR_MASK, PPC860,      { RT } },
2843 { "mtcmpc",   XSPR(31,467,146), XSPR_MASK, PPC860,      { RT } },
2844 { "mtcmpd",   XSPR(31,467,147), XSPR_MASK, PPC860,      { RT } },
2845 { "mticr",    XSPR(31,467,148), XSPR_MASK, PPC860,      { RT } },
2846 { "mtder",    XSPR(31,467,149), XSPR_MASK, PPC860,      { RT } },
2847 { "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860,      { RT } },
2848 { "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860,      { RT } },
2849 { "mtcmpe",   XSPR(31,467,152), XSPR_MASK, PPC860,      { RT } },
2850 { "mtcmpf",   XSPR(31,467,153), XSPR_MASK, PPC860,      { RT } },
2851 { "mtcmpg",   XSPR(31,467,154), XSPR_MASK, PPC860,      { RT } },
2852 { "mtcmph",   XSPR(31,467,155), XSPR_MASK, PPC860,      { RT } },
2853 { "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860,      { RT } },
2854 { "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860,      { RT } },
2855 { "mtictrl",  XSPR(31,467,158), XSPR_MASK, PPC860,      { RT } },
2856 { "mtbar",    XSPR(31,467,159), XSPR_MASK, PPC860,      { RT } },
2857 { "mtsprg",  XSPR(31,467,272), XSPRG_MASK,   PPC,       { SPRG, RS } },
2858 { "mtsprg0", XSPR(31,467,272), XSPR_MASK,    PPC,       { RT } },
2859 { "mtsprg1", XSPR(31,467,273), XSPR_MASK,    PPC,       { RT } },
2860 { "mtsprg2", XSPR(31,467,274), XSPR_MASK,    PPC,       { RT } },
2861 { "mtsprg3", XSPR(31,467,275), XSPR_MASK,    PPC,       { RT } },
2862 { "mtasr",   XSPR(31,467,280), XSPR_MASK,    PPC64,     { RS } },
2863 { "mtear",   XSPR(31,467,282), XSPR_MASK,    PPC,       { RS } },
2864 { "mttbl",   XSPR(31,467,284), XSPR_MASK,    PPC,       { RS } },
2865 { "mttbu",   XSPR(31,467,285), XSPR_MASK,    PPC,       { RS } },
2866 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC,       { SPRBAT, RS } },
2867 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC,       { SPRBAT, RS } },
2868 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC,       { SPRBAT, RS } },
2869 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC,       { SPRBAT, RS } },
2870 { "mtzpr",   XSPR(31,467,944), XSPR_MASK, PPC403,       { RT } },
2871 { "mtpid",   XSPR(31,467,945), XSPR_MASK, PPC403,       { RT } },
2872 { "mticdbdr",XSPR(31,467,979), XSPR_MASK, PPC403,       { RT } },
2873 { "mtesr",   XSPR(31,467,980), XSPR_MASK, PPC403,       { RT } },
2874 { "mtevpr",  XSPR(31,467,982), XSPR_MASK, PPC403,       { RT } },
2875 { "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403,       { RT } },
2876 { "mttsr",   XSPR(31,467,984), XSPR_MASK, PPC403,       { RT } },
2877 { "mttcr",   XSPR(31,467,986), XSPR_MASK, PPC403,       { RT } },
2878 { "mtpit",   XSPR(31,467,987), XSPR_MASK, PPC403,       { RT } },
2879 { "mttbhi",  XSPR(31,467,988), XSPR_MASK, PPC403,       { RT } },
2880 { "mttblo",  XSPR(31,467,989), XSPR_MASK, PPC403,       { RT } },
2881 { "mtsrr2",  XSPR(31,467,990), XSPR_MASK, PPC403,       { RT } },
2882 { "mtsrr3",  XSPR(31,467,991), XSPR_MASK, PPC403,       { RT } },
2883 { "mtdbsr",  XSPR(31,467,1008), XSPR_MASK, PPC403,      { RT } },
2884 { "mtiac1",  XSPR(31,467,1012), XSPR_MASK, PPC403,      { RT } },
2885 { "mtiac2",  XSPR(31,467,1013), XSPR_MASK, PPC403,      { RT } },
2886 { "mtdac1",  XSPR(31,467,1014), XSPR_MASK, PPC403,      { RT } },
2887 { "mtdac2",  XSPR(31,467,1015), XSPR_MASK, PPC403,      { RT } },
2888 { "mtdccr",  XSPR(31,467,1018), XSPR_MASK, PPC403,      { RT } },
2889 { "mticcr",  XSPR(31,467,1019), XSPR_MASK, PPC403,      { RT } },
2890 { "mtpbl1",  XSPR(31,467,1020), XSPR_MASK, PPC403,      { RT } },
2891 { "mtpbu1",  XSPR(31,467,1021), XSPR_MASK, PPC403,      { RT } },
2892 { "mtpbl2",  XSPR(31,467,1022), XSPR_MASK, PPC403,      { RT } },
2893 { "mtpbu2",  XSPR(31,467,1023), XSPR_MASK, PPC403,      { RT } },
2894 { "mtspr",   X(31,467),        X_MASK,       COM,       { SPR, RS } },
2895
2896 { "dcbi",    X(31,470), XRT_MASK,       PPC,            { RA, RB } },
2897
2898 { "nand",    XRC(31,476,0), X_MASK,     COM,            { RA, RS, RB } },
2899 { "nand.",   XRC(31,476,1), X_MASK,     COM,            { RA, RS, RB } },
2900
2901 { "dcread",  X(31,486), X_MASK,         PPC403,         { RT, RA, RB }},
2902
2903 { "nabs",    XO(31,488,0,0), XORB_MASK, M601,           { RT, RA } },
2904 { "nabs.",   XO(31,488,0,1), XORB_MASK, M601,           { RT, RA } },
2905 { "nabso",   XO(31,488,1,0), XORB_MASK, M601,           { RT, RA } },
2906 { "nabso.",  XO(31,488,1,1), XORB_MASK, M601,           { RT, RA } },
2907
2908 { "divd",    XO(31,489,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
2909 { "divd.",   XO(31,489,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
2910 { "divdo",   XO(31,489,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
2911 { "divdo.",  XO(31,489,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
2912
2913 { "divw",    XO(31,491,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
2914 { "divw.",   XO(31,491,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
2915 { "divwo",   XO(31,491,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
2916 { "divwo.",  XO(31,491,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
2917
2918 { "slbia",   X(31,498), 0xffffffff,     PPC64,          { 0 } },
2919
2920 { "cli",     X(31,502), XRB_MASK,       POWER,          { RT, RA } },
2921
2922 { "mcrxr",   X(31,512), XRARB_MASK|(3<<21), COM,        { BF } },
2923
2924 { "clcs",    X(31,531), XRB_MASK,       M601,           { RT, RA } },
2925
2926 { "lswx",    X(31,533), X_MASK,         PPCCOM,         { RT, RA, RB } },
2927 { "lsx",     X(31,533), X_MASK,         PWRCOM,         { RT, RA, RB } },
2928
2929 { "lwbrx",   X(31,534), X_MASK,         PPCCOM,         { RT, RA, RB } },
2930 { "lbrx",    X(31,534), X_MASK,         PWRCOM,         { RT, RA, RB } },
2931
2932 { "lfsx",    X(31,535), X_MASK,         COM,            { FRT, RA, RB } },
2933
2934 { "srw",     XRC(31,536,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
2935 { "sr",      XRC(31,536,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
2936 { "srw.",    XRC(31,536,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
2937 { "sr.",     XRC(31,536,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
2938
2939 { "rrib",    XRC(31,537,0), X_MASK,     M601,           { RA, RS, RB } },
2940 { "rrib.",   XRC(31,537,1), X_MASK,     M601,           { RA, RS, RB } },
2941
2942 { "srd",     XRC(31,539,0), X_MASK,     PPC64,          { RA, RS, RB } },
2943 { "srd.",    XRC(31,539,1), X_MASK,     PPC64,          { RA, RS, RB } },
2944
2945 { "maskir",  XRC(31,541,0), X_MASK,     M601,           { RA, RS, RB } },
2946 { "maskir.", XRC(31,541,1), X_MASK,     M601,           { RA, RS, RB } },
2947
2948 { "tlbsync", X(31,566), 0xffffffff,     PPC,            { 0 } },
2949
2950 { "lfsux",   X(31,567), X_MASK,         COM,            { FRT, RAS, RB } },
2951
2952 { "mfsr",    X(31,595), XRB_MASK|(1<<20), COM32,        { RT, SR } },
2953
2954 { "lswi",    X(31,597), X_MASK,         PPCCOM,         { RT, RA, NB } },
2955 { "lsi",     X(31,597), X_MASK,         PWRCOM,         { RT, RA, NB } },
2956
2957 { "sync",    X(31,598), 0xffffffff,     PPCCOM,         { 0 } },
2958 { "dcs",     X(31,598), 0xffffffff,     PWRCOM,         { 0 } },
2959
2960 { "lfdx",    X(31,599), X_MASK,         COM,            { FRT, RA, RB } },
2961
2962 { "mfsri",   X(31,627), X_MASK,         PWRCOM,         { RT, RA, RB } },
2963
2964 { "dclst",   X(31,630), XRB_MASK,       PWRCOM,         { RS, RA } },
2965
2966 { "lfdux",   X(31,631), X_MASK,         COM,            { FRT, RAS, RB } },
2967
2968 { "mfsrin",  X(31,659), XRA_MASK,       PPC32,          { RT, RB } },
2969
2970 { "stswx",   X(31,661), X_MASK,         PPCCOM,         { RS, RA, RB } },
2971 { "stsx",    X(31,661), X_MASK,         PWRCOM,         { RS, RA, RB } },
2972
2973 { "stwbrx",  X(31,662), X_MASK,         PPCCOM,         { RS, RA, RB } },
2974 { "stbrx",   X(31,662), X_MASK,         PWRCOM,         { RS, RA, RB } },
2975
2976 { "stfsx",   X(31,663), X_MASK,         COM,            { FRS, RA, RB } },
2977
2978 { "srq",     XRC(31,664,0), X_MASK,     M601,           { RA, RS, RB } },
2979 { "srq.",    XRC(31,664,1), X_MASK,     M601,           { RA, RS, RB } },
2980
2981 { "sre",     XRC(31,665,0), X_MASK,     M601,           { RA, RS, RB } },
2982 { "sre.",    XRC(31,665,1), X_MASK,     M601,           { RA, RS, RB } },
2983
2984 { "stfsux",  X(31,695), X_MASK,         COM,            { FRS, RAS, RB } },
2985
2986 { "sriq",    XRC(31,696,0), X_MASK,     M601,           { RA, RS, SH } },
2987 { "sriq.",   XRC(31,696,1), X_MASK,     M601,           { RA, RS, SH } },
2988
2989 { "stswi",   X(31,725), X_MASK,         PPCCOM,         { RS, RA, NB } },
2990 { "stsi",    X(31,725), X_MASK,         PWRCOM,         { RS, RA, NB } },
2991
2992 { "stfdx",   X(31,727), X_MASK,         COM,            { FRS, RA, RB } },
2993
2994 { "srlq",    XRC(31,728,0), X_MASK,     M601,           { RA, RS, RB } },
2995 { "srlq.",   XRC(31,728,1), X_MASK,     M601,           { RA, RS, RB } },
2996
2997 { "sreq",    XRC(31,729,0), X_MASK,     M601,           { RA, RS, RB } },
2998 { "sreq.",   XRC(31,729,1), X_MASK,     M601,           { RA, RS, RB } },
2999
3000 { "stfdux",  X(31,759), X_MASK,         COM,            { FRS, RAS, RB } },
3001
3002 { "srliq",   XRC(31,760,0), X_MASK,     M601,           { RA, RS, SH } },
3003 { "srliq.",  XRC(31,760,1), X_MASK,     M601,           { RA, RS, SH } },
3004
3005 { "lhbrx",   X(31,790), X_MASK,         COM,            { RT, RA, RB } },
3006
3007 { "sraw",    XRC(31,792,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
3008 { "sra",     XRC(31,792,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
3009 { "sraw.",   XRC(31,792,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
3010 { "sra.",    XRC(31,792,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
3011
3012 { "srad",    XRC(31,794,0), X_MASK,     PPC64,          { RA, RS, RB } },
3013 { "srad.",   XRC(31,794,1), X_MASK,     PPC64,          { RA, RS, RB } },
3014
3015 { "rac",     X(31,818), X_MASK,         PWRCOM,         { RT, RA, RB } },
3016
3017 { "srawi",   XRC(31,824,0), X_MASK,     PPCCOM,         { RA, RS, SH } },
3018 { "srai",    XRC(31,824,0), X_MASK,     PWRCOM,         { RA, RS, SH } },
3019 { "srawi.",  XRC(31,824,1), X_MASK,     PPCCOM,         { RA, RS, SH } },
3020 { "srai.",   XRC(31,824,1), X_MASK,     PWRCOM,         { RA, RS, SH } },
3021
3022 { "eieio",   X(31,854), 0xffffffff,     PPC,            { 0 } },
3023
3024 { "tlbsx",   XRC(31,914,0), X_MASK, PPC403,     { RT, RA, RB } },
3025 { "tlbsx.",  XRC(31,914,1), X_MASK, PPC403,     { RT, RA, RB } },
3026
3027 { "sthbrx",  X(31,918), X_MASK,         COM,            { RS, RA, RB } },
3028
3029 { "sraq",    XRC(31,920,0), X_MASK,     M601,           { RA, RS, RB } },
3030 { "sraq.",   XRC(31,920,1), X_MASK,     M601,           { RA, RS, RB } },
3031
3032 { "srea",    XRC(31,921,0), X_MASK,     M601,           { RA, RS, RB } },
3033 { "srea.",   XRC(31,921,1), X_MASK,     M601,           { RA, RS, RB } },
3034
3035 { "extsh",   XRC(31,922,0), XRB_MASK,   PPCCOM,         { RA, RS } },
3036 { "exts",    XRC(31,922,0), XRB_MASK,   PWRCOM,         { RA, RS } },
3037 { "extsh.",  XRC(31,922,1), XRB_MASK,   PPCCOM,         { RA, RS } },
3038 { "exts.",   XRC(31,922,1), XRB_MASK,   PWRCOM,         { RA, RS } },
3039
3040 { "tlbre",   X(31,946), X_MASK,         PPC403,         { RT, RA, SH } },
3041
3042 { "sraiq",   XRC(31,952,0), X_MASK,     M601,           { RA, RS, SH } },
3043 { "sraiq.",  XRC(31,952,1), X_MASK,     M601,           { RA, RS, SH } },
3044
3045 { "extsb",   XRC(31,954,0), XRB_MASK,   PPC,            { RA, RS} },
3046 { "extsb.",  XRC(31,954,1), XRB_MASK,   PPC,            { RA, RS} },
3047
3048 { "iccci",   X(31,966), XRT_MASK,       PPC,            { RA, RB } },
3049
3050 { "tlbld",   X(31,978), XRTRA_MASK,     PPC,            { RB } },
3051 { "tlbwe",   X(31,978), X_MASK,         PPC403,         { RS, RA, SH } },
3052
3053 { "icbi",    X(31,982), XRT_MASK,       PPC,            { RA, RB } },
3054
3055 { "stfiwx",  X(31,983), X_MASK,         PPC,            { FRS, RA, RB } },
3056
3057 { "extsw",   XRC(31,986,0), XRB_MASK,   PPC,            { RA, RS } },
3058 { "extsw.",  XRC(31,986,1), XRB_MASK,   PPC,            { RA, RS } },
3059
3060 { "icread",  X(31,998), XRT_MASK,       PPC403,         { RA, RB } },
3061
3062 { "tlbli",   X(31,1010), XRTRA_MASK,    PPC,            { RB } },
3063
3064 { "dcbz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
3065 { "dclz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
3066
3067 { "lvebx",   X(31,   7), X_MASK,        PPCVEC,         { VD, RA, RB } },
3068 { "lvehx",   X(31,  39), X_MASK,        PPCVEC,         { VD, RA, RB } },
3069 { "lvewx",   X(31,  71), X_MASK,        PPCVEC,         { VD, RA, RB } },
3070 { "lvsl",    X(31,   6), X_MASK,        PPCVEC,         { VD, RA, RB } },
3071 { "lvsr",    X(31,  38), X_MASK,        PPCVEC,         { VD, RA, RB } },
3072 { "lvx",     X(31, 103), X_MASK,        PPCVEC,         { VD, RA, RB } },
3073 { "lvxl",    X(31, 359), X_MASK,        PPCVEC,         { VD, RA, RB } },
3074 { "stvebx",  X(31, 135), X_MASK,        PPCVEC,         { VS, RA, RB } },
3075 { "stvehx",  X(31, 167), X_MASK,        PPCVEC,         { VS, RA, RB } },
3076 { "stvewx",  X(31, 199), X_MASK,        PPCVEC,         { VS, RA, RB } },
3077 { "stvx",    X(31, 231), X_MASK,        PPCVEC,         { VS, RA, RB } },
3078 { "stvxl",   X(31, 487), X_MASK,        PPCVEC,         { VS, RA, RB } },
3079
3080 { "lwz",     OP(32),    OP_MASK,        PPCCOM,         { RT, D, RA } },
3081 { "l",       OP(32),    OP_MASK,        PWRCOM,         { RT, D, RA } },
3082
3083 { "lwzu",    OP(33),    OP_MASK,        PPCCOM,         { RT, D, RAL } },
3084 { "lu",      OP(33),    OP_MASK,        PWRCOM,         { RT, D, RA } },
3085
3086 { "lbz",     OP(34),    OP_MASK,        COM,            { RT, D, RA } },
3087
3088 { "lbzu",    OP(35),    OP_MASK,        COM,            { RT, D, RAL } },
3089
3090 { "stw",     OP(36),    OP_MASK,        PPCCOM,         { RS, D, RA } },
3091 { "st",      OP(36),    OP_MASK,        PWRCOM,         { RS, D, RA } },
3092
3093 { "stwu",    OP(37),    OP_MASK,        PPCCOM,         { RS, D, RAS } },
3094 { "stu",     OP(37),    OP_MASK,        PWRCOM,         { RS, D, RA } },
3095
3096 { "stb",     OP(38),    OP_MASK,        COM,            { RS, D, RA } },
3097
3098 { "stbu",    OP(39),    OP_MASK,        COM,            { RS, D, RAS } },
3099
3100 { "lhz",     OP(40),    OP_MASK,        COM,            { RT, D, RA } },
3101
3102 { "lhzu",    OP(41),    OP_MASK,        COM,            { RT, D, RAL } },
3103
3104 { "lha",     OP(42),    OP_MASK,        COM,            { RT, D, RA } },
3105
3106 { "lhau",    OP(43),    OP_MASK,        COM,            { RT, D, RAL } },
3107
3108 { "sth",     OP(44),    OP_MASK,        COM,            { RS, D, RA } },
3109
3110 { "sthu",    OP(45),    OP_MASK,        COM,            { RS, D, RAS } },
3111
3112 { "lmw",     OP(46),    OP_MASK,        PPCCOM,         { RT, D, RAM } },
3113 { "lm",      OP(46),    OP_MASK,        PWRCOM,         { RT, D, RA } },
3114
3115 { "stmw",    OP(47),    OP_MASK,        PPCCOM,         { RS, D, RA } },
3116 { "stm",     OP(47),    OP_MASK,        PWRCOM,         { RS, D, RA } },
3117
3118 { "lfs",     OP(48),    OP_MASK,        COM,            { FRT, D, RA } },
3119
3120 { "lfsu",    OP(49),    OP_MASK,        COM,            { FRT, D, RAS } },
3121
3122 { "lfd",     OP(50),    OP_MASK,        COM,            { FRT, D, RA } },
3123
3124 { "lfdu",    OP(51),    OP_MASK,        COM,            { FRT, D, RAS } },
3125
3126 { "stfs",    OP(52),    OP_MASK,        COM,            { FRS, D, RA } },
3127
3128 { "stfsu",   OP(53),    OP_MASK,        COM,            { FRS, D, RAS } },
3129
3130 { "stfd",    OP(54),    OP_MASK,        COM,            { FRS, D, RA } },
3131
3132 { "stfdu",   OP(55),    OP_MASK,        COM,            { FRS, D, RAS } },
3133
3134 { "lfq",     OP(56),    OP_MASK,        POWER2,         { FRT, D, RA } },
3135
3136 { "lfqu",    OP(57),    OP_MASK,        POWER2,         { FRT, D, RA } },
3137
3138 { "ld",      DSO(58,0), DS_MASK,        PPC64,          { RT, DS, RA } },
3139
3140 { "ldu",     DSO(58,1), DS_MASK,        PPC64,          { RT, DS, RAL } },
3141
3142 { "lwa",     DSO(58,2), DS_MASK,        PPC64,          { RT, DS, RA } },
3143
3144 { "fdivs",   A(59,18,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3145 { "fdivs.",  A(59,18,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3146
3147 { "fsubs",   A(59,20,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3148 { "fsubs.",  A(59,20,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3149
3150 { "fadds",   A(59,21,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3151 { "fadds.",  A(59,21,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3152
3153 { "fsqrts",  A(59,22,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3154 { "fsqrts.", A(59,22,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3155
3156 { "fres",    A(59,24,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3157 { "fres.",   A(59,24,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3158
3159 { "fmuls",   A(59,25,0), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
3160 { "fmuls.",  A(59,25,1), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
3161
3162 { "fmsubs",  A(59,28,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3163 { "fmsubs.", A(59,28,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3164
3165 { "fmadds",  A(59,29,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3166 { "fmadds.", A(59,29,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3167
3168 { "fnmsubs", A(59,30,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3169 { "fnmsubs.",A(59,30,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3170
3171 { "fnmadds", A(59,31,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3172 { "fnmadds.",A(59,31,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3173
3174 { "stfq",    OP(60),    OP_MASK,        POWER2,         { FRS, D, RA } },
3175
3176 { "stfqu",   OP(61),    OP_MASK,        POWER2,         { FRS, D, RA } },
3177
3178 { "std",     DSO(62,0), DS_MASK,        PPC64,          { RS, DS, RA } },
3179
3180 { "stdu",    DSO(62,1), DS_MASK,        PPC64,          { RS, DS, RAS } },
3181
3182 { "fcmpu",   X(63,0),   X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
3183
3184 { "frsp",    XRC(63,12,0), XRA_MASK,    COM,            { FRT, FRB } },
3185 { "frsp.",   XRC(63,12,1), XRA_MASK,    COM,            { FRT, FRB } },
3186
3187 { "fctiw",   XRC(63,14,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
3188 { "fcir",    XRC(63,14,0), XRA_MASK,    POWER2,         { FRT, FRB } },
3189 { "fctiw.",  XRC(63,14,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
3190 { "fcir.",   XRC(63,14,1), XRA_MASK,    POWER2,         { FRT, FRB } },
3191
3192 { "fctiwz",  XRC(63,15,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
3193 { "fcirz",   XRC(63,15,0), XRA_MASK,    POWER2,         { FRT, FRB } },
3194 { "fctiwz.", XRC(63,15,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
3195 { "fcirz.",  XRC(63,15,1), XRA_MASK,    POWER2,         { FRT, FRB } },
3196
3197 { "fdiv",    A(63,18,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3198 { "fd",      A(63,18,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3199 { "fdiv.",   A(63,18,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3200 { "fd.",     A(63,18,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3201
3202 { "fsub",    A(63,20,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3203 { "fs",      A(63,20,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3204 { "fsub.",   A(63,20,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3205 { "fs.",     A(63,20,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3206
3207 { "fadd",    A(63,21,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3208 { "fa",      A(63,21,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3209 { "fadd.",   A(63,21,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3210 { "fa.",     A(63,21,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3211
3212 { "fsqrt",   A(63,22,0), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
3213 { "fsqrt.",  A(63,22,1), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
3214
3215 { "fsel",    A(63,23,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3216 { "fsel.",   A(63,23,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3217
3218 { "fmul",    A(63,25,0), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
3219 { "fm",      A(63,25,0), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
3220 { "fmul.",   A(63,25,1), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
3221 { "fm.",     A(63,25,1), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
3222
3223 { "frsqrte", A(63,26,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3224 { "frsqrte.",A(63,26,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3225
3226 { "fmsub",   A(63,28,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3227 { "fms",     A(63,28,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3228 { "fmsub.",  A(63,28,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3229 { "fms.",    A(63,28,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3230
3231 { "fmadd",   A(63,29,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3232 { "fma",     A(63,29,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3233 { "fmadd.",  A(63,29,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3234 { "fma.",    A(63,29,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3235
3236 { "fnmsub",  A(63,30,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3237 { "fnms",    A(63,30,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3238 { "fnmsub.", A(63,30,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3239 { "fnms.",   A(63,30,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3240
3241 { "fnmadd",  A(63,31,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3242 { "fnma",    A(63,31,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3243 { "fnmadd.", A(63,31,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3244 { "fnma.",   A(63,31,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3245
3246 { "fcmpo",   X(63,32),  X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
3247
3248 { "mtfsb1",  XRC(63,38,0), XRARB_MASK,  COM,            { BT } },
3249 { "mtfsb1.", XRC(63,38,1), XRARB_MASK,  COM,            { BT } },
3250
3251 { "fneg",    XRC(63,40,0), XRA_MASK,    COM,            { FRT, FRB } },
3252 { "fneg.",   XRC(63,40,1), XRA_MASK,    COM,            { FRT, FRB } },
3253
3254 { "mcrfs",   X(63,64),  XRB_MASK|(3<<21)|(3<<16), COM,  { BF, BFA } },
3255
3256 { "mtfsb0",  XRC(63,70,0), XRARB_MASK,  COM,            { BT } },
3257 { "mtfsb0.", XRC(63,70,1), XRARB_MASK,  COM,            { BT } },
3258
3259 { "fmr",     XRC(63,72,0), XRA_MASK,    COM,            { FRT, FRB } },
3260 { "fmr.",    XRC(63,72,1), XRA_MASK,    COM,            { FRT, FRB } },
3261
3262 { "mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
3263 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
3264
3265 { "fnabs",   XRC(63,136,0), XRA_MASK,   COM,            { FRT, FRB } },
3266 { "fnabs.",  XRC(63,136,1), XRA_MASK,   COM,            { FRT, FRB } },
3267
3268 { "fabs",    XRC(63,264,0), XRA_MASK,   COM,            { FRT, FRB } },
3269 { "fabs.",   XRC(63,264,1), XRA_MASK,   COM,            { FRT, FRB } },
3270
3271 { "mffs",    XRC(63,583,0), XRARB_MASK, COM,            { FRT } },
3272 { "mffs.",   XRC(63,583,1), XRARB_MASK, COM,            { FRT } },
3273
3274 { "mtfsf",   XFL(63,711,0), XFL_MASK,   COM,            { FLM, FRB } },
3275 { "mtfsf.",  XFL(63,711,1), XFL_MASK,   COM,            { FLM, FRB } },
3276
3277 { "fctid",   XRC(63,814,0), XRA_MASK,   PPC64,          { FRT, FRB } },
3278 { "fctid.",  XRC(63,814,1), XRA_MASK,   PPC64,          { FRT, FRB } },
3279
3280 { "fctidz",  XRC(63,815,0), XRA_MASK,   PPC64,          { FRT, FRB } },
3281 { "fctidz.", XRC(63,815,1), XRA_MASK,   PPC64,          { FRT, FRB } },
3282
3283 { "fcfid",   XRC(63,846,0), XRA_MASK,   PPC64,          { FRT, FRB } },
3284 { "fcfid.",  XRC(63,846,1), XRA_MASK,   PPC64,          { FRT, FRB } },
3285
3286 };
3287
3288 const int powerpc_num_opcodes =
3289   sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
3290 \f
3291 /* The macro table.  This is only used by the assembler.  */
3292
3293 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
3294    when x=0; 32-x when x is between 1 and 31; are negative if x is
3295    negative; and are 32 or more otherwise.  This is what you want
3296    when, for instance, you are emulating a right shift by a
3297    rotate-left-and-mask, because the underlying instructions support
3298    shifts of size 0 but not shifts of size 32.  By comparison, when
3299    extracting x bits from some word you want to use just 32-x, because
3300    the underlying instructions don't support extracting 0 bits but do
3301    support extracting the whole word (32 bits in this case).  */
3302
3303 const struct powerpc_macro powerpc_macros[] = {
3304 { "extldi",  4,   PPC64,        "rldicr %0,%1,%3,(%2)-1" },
3305 { "extldi.", 4,   PPC64,        "rldicr. %0,%1,%3,(%2)-1" },
3306 { "extrdi",  4,   PPC64,        "rldicl %0,%1,(%2)+(%3),64-(%2)" },
3307 { "extrdi.", 4,   PPC64,        "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
3308 { "insrdi",  4,   PPC64,        "rldimi %0,%1,64-((%2)+(%3)),%3" },
3309 { "insrdi.", 4,   PPC64,        "rldimi. %0,%1,64-((%2)+(%3)),%3" },
3310 { "rotrdi",  3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
3311 { "rotrdi.", 3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
3312 { "sldi",    3,   PPC64,        "rldicr %0,%1,%2,63-(%2)" },
3313 { "sldi.",   3,   PPC64,        "rldicr. %0,%1,%2,63-(%2)" },
3314 { "srdi",    3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
3315 { "srdi.",   3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
3316 { "clrrdi",  3,   PPC64,        "rldicr %0,%1,0,63-(%2)" },
3317 { "clrrdi.", 3,   PPC64,        "rldicr. %0,%1,0,63-(%2)" },
3318 { "clrlsldi",4,   PPC64,        "rldic %0,%1,%3,(%2)-(%3)" },
3319 { "clrlsldi.",4,  PPC64,        "rldic. %0,%1,%3,(%2)-(%3)" },
3320
3321 { "extlwi",  4,   PPCCOM,       "rlwinm %0,%1,%3,0,(%2)-1" },
3322 { "extlwi.", 4,   PPCCOM,       "rlwinm. %0,%1,%3,0,(%2)-1" },
3323 { "extrwi",  4,   PPCCOM,       "rlwinm %0,%1,(%2)+(%3),32-(%2),31" },
3324 { "extrwi.", 4,   PPCCOM,       "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" },
3325 { "inslwi",  4,   PPCCOM,       "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
3326 { "inslwi.", 4,   PPCCOM,       "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
3327 { "insrwi",  4,   PPCCOM,       "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
3328 { "insrwi.", 4,   PPCCOM,       "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
3329 { "rotrwi",  3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
3330 { "rotrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
3331 { "slwi",    3,   PPCCOM,       "rlwinm %0,%1,%2,0,31-(%2)" },
3332 { "sli",     3,   PWRCOM,       "rlinm %0,%1,%2,0,31-(%2)" },
3333 { "slwi.",   3,   PPCCOM,       "rlwinm. %0,%1,%2,0,31-(%2)" },
3334 { "sli.",    3,   PWRCOM,       "rlinm. %0,%1,%2,0,31-(%2)" },
3335 { "srwi",    3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3336 { "sri",     3,   PWRCOM,       "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3337 { "srwi.",   3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3338 { "sri.",    3,   PWRCOM,       "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3339 { "clrrwi",  3,   PPCCOM,       "rlwinm %0,%1,0,0,31-(%2)" },
3340 { "clrrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,0,0,31-(%2)" },
3341 { "clrlslwi",4,   PPCCOM,       "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
3342 { "clrlslwi.",4,  PPCCOM,       "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
3343
3344 };
3345
3346 const int powerpc_num_macros =
3347   sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);