opcodes/ppc-opc.c

   1 /* ppc-opc.c -- PowerPC opcode list
   2    Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
   3    2005, 2006, 2007, 2008, 2009, 2010, 2011
   4    Free Software Foundation, Inc.
   5    Written by Ian Lance Taylor, Cygnus Support
   6
   7    This file is part of the GNU opcodes library.
   8
   9    This library is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this file; see the file COPYING.  If not, write to the
  21    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  22    MA 02110-1301, USA.  */
  23
  24 #include <stdio.h>
  25 #include "sysdep.h"
  26 #include "opcode/ppc.h"
  27 #include "opintl.h"
  28
  29 /* This file holds the PowerPC opcode table.  The opcode table
  30    includes almost all of the extended instruction mnemonics.  This
  31    permits the disassembler to use them, and simplifies the assembler
  32    logic, at the cost of increasing the table size.  The table is
  33    strictly constant data, so the compiler should be able to put it in
  34    the .text section.
  35
  36    This file also holds the operand table.  All knowledge about
  37    inserting operands into instructions and vice-versa is kept in this
  38    file.  */
  39 \f
  40 /* Local insertion and extraction functions.  */
  41
  42 static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **);
  43 static long extract_bat (unsigned long, ppc_cpu_t, int *);
  44 static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **);
  45 static long extract_bba (unsigned long, ppc_cpu_t, int *);
  46 static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **);
  47 static long extract_bdm (unsigned long, ppc_cpu_t, int *);
  48 static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **);
  49 static long extract_bdp (unsigned long, ppc_cpu_t, int *);
  50 static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **);
  51 static long extract_bo (unsigned long, ppc_cpu_t, int *);
  52 static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **);
  53 static long extract_boe (unsigned long, ppc_cpu_t, int *);
  54 static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
  55 static long extract_fxm (unsigned long, ppc_cpu_t, int *);
  56 static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
  57 static long extract_mbe (unsigned long, ppc_cpu_t, int *);
  58 static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
  59 static long extract_mb6 (unsigned long, ppc_cpu_t, int *);
  60 static long extract_nb (unsigned long, ppc_cpu_t, int *);
  61 static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t, const char **);
  62 static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **);
  63 static long extract_nsi (unsigned long, ppc_cpu_t, int *);
  64 static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **);
  65 static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **);
  66 static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **);
  67 static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **);
  68 static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **);
  69 static long extract_rbs (unsigned long, ppc_cpu_t, int *);
  70 static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t, const char **);
  71 static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **);
  72 static long extract_sh6 (unsigned long, ppc_cpu_t, int *);
  73 static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **);
  74 static long extract_spr (unsigned long, ppc_cpu_t, int *);
  75 static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **);
  76 static long extract_sprg (unsigned long, ppc_cpu_t, int *);
  77 static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
  78 static long extract_tbr (unsigned long, ppc_cpu_t, int *);
  79 static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
  80 static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
  81 static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
  82 static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
  83 static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
  84 static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
  85 static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
  86 static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
  87 static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **);
  88 static long extract_xc6 (unsigned long, ppc_cpu_t, int *);
  89 static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **);
  90 static long extract_dm (unsigned long, ppc_cpu_t, int *);
  91 \f
  92 /* The operands table.
  93
  94    The fields are bitm, shift, insert, extract, flags.
  95
  96    We used to put parens around the various additions, like the one
  97    for BA just below.  However, that caused trouble with feeble
  98    compilers with a limit on depth of a parenthesized expression, like
  99    (reportedly) the compiler in Microsoft Developer Studio 5.  So we
 100    omit the parens, since the macros are never used in a context where
 101    the addition will be ambiguous.  */
 102
 103 const struct powerpc_operand powerpc_operands[] =
 104 {
 105   /* The zero index is used to indicate the end of the list of
 106      operands.  */
 107 #define UNUSED 0
 108   { 0, 0, NULL, NULL, 0 },
 109
 110   /* The BA field in an XL form instruction.  */
 111 #define BA UNUSED + 1
 112   /* The BI field in a B form or XL form instruction.  */
 113 #define BI BA
 114 #define BI_MASK (0x1f << 16)
 115   { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
 116
 117   /* The BA field in an XL form instruction when it must be the same
 118      as the BT field in the same instruction.  */
 119 #define BAT BA + 1
 120   { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
 121
 122   /* The BB field in an XL form instruction.  */
 123 #define BB BAT + 1
 124 #define BB_MASK (0x1f << 11)
 125   { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR },
 126
 127   /* The BB field in an XL form instruction when it must be the same
 128      as the BA field in the same instruction.  */
 129 #define BBA BB + 1
 130   { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
 131
 132   /* The BD field in a B form instruction.  The lower two bits are
 133      forced to zero.  */
 134 #define BD BBA + 1
 135   { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 136
 137   /* The BD field in a B form instruction when absolute addressing is
 138      used.  */
 139 #define BDA BD + 1
 140   { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 141
 142   /* The BD field in a B form instruction when the - modifier is used.
 143      This sets the y bit of the BO field appropriately.  */
 144 #define BDM BDA + 1
 145   { 0xfffc, 0, insert_bdm, extract_bdm,
 146       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 147
 148   /* The BD field in a B form instruction when the - modifier is used
 149      and absolute address is used.  */
 150 #define BDMA BDM + 1
 151   { 0xfffc, 0, insert_bdm, extract_bdm,
 152       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 153
 154   /* The BD field in a B form instruction when the + modifier is used.
 155      This sets the y bit of the BO field appropriately.  */
 156 #define BDP BDMA + 1
 157   { 0xfffc, 0, insert_bdp, extract_bdp,
 158       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 159
 160   /* The BD field in a B form instruction when the + modifier is used
 161      and absolute addressing is used.  */
 162 #define BDPA BDP + 1
 163   { 0xfffc, 0, insert_bdp, extract_bdp,
 164       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 165
 166   /* The BF field in an X or XL form instruction.  */
 167 #define BF BDPA + 1
 168   /* The CRFD field in an X form instruction.  */
 169 #define CRFD BF
 170   { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
 171
 172   /* The BF field in an X or XL form instruction.  */
 173 #define BFF BF + 1
 174   { 0x7, 23, NULL, NULL, 0 },
 175
 176   /* An optional BF field.  This is used for comparison instructions,
 177      in which an omitted BF field is taken as zero.  */
 178 #define OBF BFF + 1
 179   { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 180
 181   /* The BFA field in an X or XL form instruction.  */
 182 #define BFA OBF + 1
 183   { 0x7, 18, NULL, NULL, PPC_OPERAND_CR },
 184
 185   /* The BO field in a B form instruction.  Certain values are
 186      illegal.  */
 187 #define BO BFA + 1
 188 #define BO_MASK (0x1f << 21)
 189   { 0x1f, 21, insert_bo, extract_bo, 0 },
 190
 191   /* The BO field in a B form instruction when the + or - modifier is
 192      used.  This is like the BO field, but it must be even.  */
 193 #define BOE BO + 1
 194   { 0x1e, 21, insert_boe, extract_boe, 0 },
 195
 196 #define BH BOE + 1
 197   { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
 198
 199   /* The BT field in an X or XL form instruction.  */
 200 #define BT BH + 1
 201   { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR },
 202
 203   /* The condition register number portion of the BI field in a B form
 204      or XL form instruction.  This is used for the extended
 205      conditional branch mnemonics, which set the lower two bits of the
 206      BI field.  This field is optional.  */
 207 #define CR BT + 1
 208   { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 209
 210   /* The CRB field in an X form instruction.  */
 211 #define CRB CR + 1
 212   /* The MB field in an M form instruction.  */
 213 #define MB CRB
 214 #define MB_MASK (0x1f << 6)
 215   { 0x1f, 6, NULL, NULL, 0 },
 216
 217   /* The CRFS field in an X form instruction.  */
 218 #define CRFS CRB + 1
 219   { 0x7, 0, NULL, NULL, PPC_OPERAND_CR },
 220
 221   /* The CT field in an X form instruction.  */
 222 #define CT CRFS + 1
 223   /* The MO field in an mbar instruction.  */
 224 #define MO CT
 225   { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 226
 227   /* The D field in a D form instruction.  This is a displacement off
 228      a register, and implies that the next operand is a register in
 229      parentheses.  */
 230 #define D CT + 1
 231   { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 232
 233   /* The DQ field in a DQ form instruction.  This is like D, but the
 234      lower four bits are forced to zero. */
 235 #define DQ D + 1
 236   { 0xfff0, 0, NULL, NULL,
 237     PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
 238
 239   /* The DS field in a DS form instruction.  This is like D, but the
 240      lower two bits are forced to zero.  */
 241 #define DS DQ + 1
 242   { 0xfffc, 0, NULL, NULL,
 243     PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
 244
 245   /* The DUIS field in a XFX form instruction, 10 bits unsigned imediate */
 246 #define DUIS DS + 1
 247   { 0x3ff, 11, NULL, NULL, 0 },
 248
 249   /* The E field in a wrteei instruction.  */
 250   /* And the W bit in the pair singles instructions.  */
 251 #define E DUIS + 1
 252 #define PSW E
 253   { 0x1, 15, NULL, NULL, 0 },
 254
 255   /* The FL1 field in a POWER SC form instruction.  */
 256 #define FL1 E + 1
 257   /* The U field in an X form instruction.  */
 258 #define U FL1
 259   { 0xf, 12, NULL, NULL, 0 },
 260
 261   /* The FL2 field in a POWER SC form instruction.  */
 262 #define FL2 FL1 + 1
 263   { 0x7, 2, NULL, NULL, 0 },
 264
 265   /* The FLM field in an XFL form instruction.  */
 266 #define FLM FL2 + 1
 267   { 0xff, 17, NULL, NULL, 0 },
 268
 269   /* The FRA field in an X or A form instruction.  */
 270 #define FRA FLM + 1
 271 #define FRA_MASK (0x1f << 16)
 272   { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
 273
 274   /* The FRAp field of DFP instructions.  */
 275 #define FRAp FRA + 1
 276   { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR },
 277
 278   /* The FRB field in an X or A form instruction.  */
 279 #define FRB FRAp + 1
 280 #define FRB_MASK (0x1f << 11)
 281   { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
 282
 283   /* The FRBp field of DFP instructions.  */
 284 #define FRBp FRB + 1
 285   { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR },
 286
 287   /* The FRC field in an A form instruction.  */
 288 #define FRC FRBp + 1
 289 #define FRC_MASK (0x1f << 6)
 290   { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
 291
 292   /* The FRS field in an X form instruction or the FRT field in a D, X
 293      or A form instruction.  */
 294 #define FRS FRC + 1
 295 #define FRT FRS
 296   { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
 297
 298   /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
 299      instructions.  */
 300 #define FRSp FRS + 1
 301 #define FRTp FRSp
 302   { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR },
 303
 304   /* The FXM field in an XFX instruction.  */
 305 #define FXM FRSp + 1
 306   { 0xff, 12, insert_fxm, extract_fxm, 0 },
 307
 308   /* Power4 version for mfcr.  */
 309 #define FXM4 FXM + 1
 310   { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
 311
 312   /* The L field in a D or X form instruction.  */
 313 #define L FXM4 + 1
 314   { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 315
 316   /* The LEV field in a POWER SVC form instruction.  */
 317 #define SVC_LEV L + 1
 318   { 0x7f, 5, NULL, NULL, 0 },
 319
 320   /* The LEV field in an SC form instruction.  */
 321 #define LEV SVC_LEV + 1
 322   { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
 323
 324   /* The LI field in an I form instruction.  The lower two bits are
 325      forced to zero.  */
 326 #define LI LEV + 1
 327   { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 328
 329   /* The LI field in an I form instruction when used as an absolute
 330      address.  */
 331 #define LIA LI + 1
 332   { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 333
 334   /* The LS or WC field in an X (sync or wait) form instruction.  */
 335 #define LS LIA + 1
 336 #define WC LS
 337   { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 338
 339   /* The ME field in an M form instruction.  */
 340 #define ME LS + 1
 341 #define ME_MASK (0x1f << 1)
 342   { 0x1f, 1, NULL, NULL, 0 },
 343
 344   /* The MB and ME fields in an M form instruction expressed a single
 345      operand which is a bitmask indicating which bits to select.  This
 346      is a two operand form using PPC_OPERAND_NEXT.  See the
 347      description in opcode/ppc.h for what this means.  */
 348 #define MBE ME + 1
 349   { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
 350   { -1, 0, insert_mbe, extract_mbe, 0 },
 351
 352   /* The MB or ME field in an MD or MDS form instruction.  The high
 353      bit is wrapped to the low end.  */
 354 #define MB6 MBE + 2
 355 #define ME6 MB6
 356 #define MB6_MASK (0x3f << 5)
 357   { 0x3f, 5, insert_mb6, extract_mb6, 0 },
 358
 359   /* The NB field in an X form instruction.  The value 32 is stored as
 360      0.  */
 361 #define NB MB6 + 1
 362   { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
 363
 364   /* The NBI field in an lswi instruction, which has special value
 365      restrictions.  The value 32 is stored as 0.  */
 366 #define NBI NB + 1
 367   { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 },
 368
 369   /* The NSI field in a D form instruction.  This is the same as the
 370      SI field, only negated.  */
 371 #define NSI NBI + 1
 372   { 0xffff, 0, insert_nsi, extract_nsi,
 373       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 374
 375   /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */
 376 #define RA NSI + 1
 377 #define RA_MASK (0x1f << 16)
 378   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
 379
 380   /* As above, but 0 in the RA field means zero, not r0.  */
 381 #define RA0 RA + 1
 382   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
 383
 384   /* The RA field in the DQ form lq or an lswx instruction, which have special
 385      value restrictions.  */
 386 #define RAQ RA0 + 1
 387 #define RAX RAQ
 388   { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
 389
 390   /* The RA field in a D or X form instruction which is an updating
 391      load, which means that the RA field may not be zero and may not
 392      equal the RT field.  */
 393 #define RAL RAQ + 1
 394   { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
 395
 396   /* The RA field in an lmw instruction, which has special value
 397      restrictions.  */
 398 #define RAM RAL + 1
 399   { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
 400
 401   /* The RA field in a D or X form instruction which is an updating
 402      store or an updating floating point load, which means that the RA
 403      field may not be zero.  */
 404 #define RAS RAM + 1
 405   { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
 406
 407   /* The RA field of the tlbwe, dccci and iccci instructions,
 408      which are optional.  */
 409 #define RAOPT RAS + 1
 410   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 411
 412   /* The RB field in an X, XO, M, or MDS form instruction.  */
 413 #define RB RAOPT + 1
 414 #define RB_MASK (0x1f << 11)
 415   { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
 416
 417   /* The RB field in an X form instruction when it must be the same as
 418      the RS field in the instruction.  This is used for extended
 419      mnemonics like mr.  */
 420 #define RBS RB + 1
 421   { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
 422
 423   /* The RB field in an lswx instruction, which has special value
 424      restrictions.  */
 425 #define RBX RBS + 1
 426   { 0x1f, 11, insert_rbx, NULL, PPC_OPERAND_GPR },
 427
 428   /* The RB field of the dccci and iccci instructions, which are optional.  */
 429 #define RBOPT RBX + 1
 430   { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 431
 432   /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
 433      instruction or the RT field in a D, DS, X, XFX or XO form
 434      instruction.  */
 435 #define RS RBOPT + 1
 436 #define RT RS
 437 #define RT_MASK (0x1f << 21)
 438   { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
 439
 440   /* The RS and RT fields of the DS form stq instruction, which have
 441      special value restrictions.  */
 442 #define RSQ RS + 1
 443 #define RTQ RSQ
 444   { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
 445
 446   /* The RS field of the tlbwe instruction, which is optional.  */
 447 #define RSO RSQ + 1
 448 #define RTO RSO
 449   { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 450
 451   /* The SH field in an X or M form instruction.  */
 452 #define SH RSO + 1
 453 #define SH_MASK (0x1f << 11)
 454   /* The other UIMM field in a EVX form instruction.  */
 455 #define EVUIMM SH
 456   { 0x1f, 11, NULL, NULL, 0 },
 457
 458   /* The SH field in an MD form instruction.  This is split.  */
 459 #define SH6 SH + 1
 460 #define SH6_MASK ((0x1f << 11) | (1 << 1))
 461   { 0x3f, -1, insert_sh6, extract_sh6, 0 },
 462
 463   /* The SH field of the tlbwe instruction, which is optional.  */
 464 #define SHO SH6 + 1
 465   { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
 466
 467   /* The SI field in a D form instruction.  */
 468 #define SI SHO + 1
 469   { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
 470
 471   /* The SI field in a D form instruction when we accept a wide range
 472      of positive values.  */
 473 #define SISIGNOPT SI + 1
 474   { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 475
 476   /* The SPR field in an XFX form instruction.  This is flipped--the
 477      lower 5 bits are stored in the upper 5 and vice- versa.  */
 478 #define SPR SISIGNOPT + 1
 479 #define PMR SPR
 480 #define SPR_MASK (0x3ff << 11)
 481   { 0x3ff, 11, insert_spr, extract_spr, 0 },
 482
 483   /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
 484 #define SPRBAT SPR + 1
 485 #define SPRBAT_MASK (0x3 << 17)
 486   { 0x3, 17, NULL, NULL, 0 },
 487
 488   /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
 489 #define SPRG SPRBAT + 1
 490   { 0x1f, 16, insert_sprg, extract_sprg, 0 },
 491
 492   /* The SR field in an X form instruction.  */
 493 #define SR SPRG + 1
 494   { 0xf, 16, NULL, NULL, 0 },
 495
 496   /* The STRM field in an X AltiVec form instruction.  */
 497 #define STRM SR + 1
 498   /* The T field in a tlbilx form instruction.  */
 499 #define T STRM
 500   { 0x3, 21, NULL, NULL, 0 },
 501
 502   /* The SV field in a POWER SC form instruction.  */
 503 #define SV STRM + 1
 504   { 0x3fff, 2, NULL, NULL, 0 },
 505
 506   /* The TBR field in an XFX form instruction.  This is like the SPR
 507      field, but it is optional.  */
 508 #define TBR SV + 1
 509   { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
 510
 511   /* The TO field in a D or X form instruction.  */
 512 #define TO TBR + 1
 513 #define DUI TO
 514 #define TO_MASK (0x1f << 21)
 515   { 0x1f, 21, NULL, NULL, 0 },
 516
 517   /* The UI field in a D form instruction.  */
 518 #define UI TO + 1
 519   { 0xffff, 0, NULL, NULL, 0 },
 520
 521   /* The VA field in a VA, VX or VXR form instruction.  */
 522 #define VA UI + 1
 523   { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
 524
 525   /* The VB field in a VA, VX or VXR form instruction.  */
 526 #define VB VA + 1
 527   { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
 528
 529   /* The VC field in a VA form instruction.  */
 530 #define VC VB + 1
 531   { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
 532
 533   /* The VD or VS field in a VA, VX, VXR or X form instruction.  */
 534 #define VD VC + 1
 535 #define VS VD
 536   { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
 537
 538   /* The SIMM field in a VX form instruction, and TE in Z form.  */
 539 #define SIMM VD + 1
 540 #define TE SIMM
 541   { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
 542
 543   /* The UIMM field in a VX form instruction.  */
 544 #define UIMM SIMM + 1
 545   { 0x1f, 16, NULL, NULL, 0 },
 546
 547   /* The SHB field in a VA form instruction.  */
 548 #define SHB UIMM + 1
 549   { 0xf, 6, NULL, NULL, 0 },
 550
 551   /* The other UIMM field in a half word EVX form instruction.  */
 552 #define EVUIMM_2 SHB + 1
 553   { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
 554
 555   /* The other UIMM field in a word EVX form instruction.  */
 556 #define EVUIMM_4 EVUIMM_2 + 1
 557   { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
 558
 559   /* The other UIMM field in a double EVX form instruction.  */
 560 #define EVUIMM_8 EVUIMM_4 + 1
 561   { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
 562
 563   /* The WS field.  */
 564 #define WS EVUIMM_8 + 1
 565   { 0x7, 11, NULL, NULL, 0 },
 566
 567   /* PowerPC paired singles extensions.  */
 568   /* W bit in the pair singles instructions for x type instructions.  */
 569 #define PSWM WS + 1
 570   {  0x1, 10, 0, 0, 0 },
 571
 572   /* IDX bits for quantization in the pair singles instructions.  */
 573 #define PSQ PSWM + 1
 574   {  0x7, 12, 0, 0, 0 },
 575
 576   /* IDX bits for quantization in the pair singles x-type instructions.  */
 577 #define PSQM PSQ + 1
 578   {  0x7, 7, 0, 0, 0 },
 579
 580   /* Smaller D field for quantization in the pair singles instructions.  */
 581 #define PSD PSQM + 1
 582   {  0xfff, 0, 0, 0,  PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 583
 584 #define A_L PSD + 1
 585 #define W A_L
 586 #define MTMSRD_L W
 587   { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
 588
 589 #define RMC MTMSRD_L + 1
 590   { 0x3, 9, NULL, NULL, 0 },
 591
 592 #define R RMC + 1
 593   { 0x1, 16, NULL, NULL, 0 },
 594
 595 #define SP R + 1
 596   { 0x3, 19, NULL, NULL, 0 },
 597
 598 #define S SP + 1
 599   { 0x1, 20, NULL, NULL, 0 },
 600
 601   /* SH field starting at bit position 16.  */
 602 #define SH16 S + 1
 603   /* The DCM and DGM fields in a Z form instruction.  */
 604 #define DCM SH16
 605 #define DGM DCM
 606   { 0x3f, 10, NULL, NULL, 0 },
 607
 608   /* The EH field in larx instruction.  */
 609 #define EH SH16 + 1
 610   { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
 611
 612   /* The L field in an mtfsf or XFL form instruction.  */
 613 #define XFL_L EH + 1
 614   { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
 615
 616   /* Xilinx APU related masks and macros */
 617 #define FCRT XFL_L + 1
 618 #define FCRT_MASK (0x1f << 21)
 619   { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
 620
 621   /* Xilinx FSL related masks and macros */
 622 #define FSL FCRT + 1
 623 #define FSL_MASK (0x1f << 11)
 624   { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
 625
 626   /* Xilinx UDI related masks and macros */
 627 #define URT FSL + 1
 628   { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
 629
 630 #define URA URT + 1
 631   { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
 632
 633 #define URB URA + 1
 634   { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
 635
 636 #define URC URB + 1
 637   { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
 638
 639   /* The XT and XS fields in an XX1 or XX3 form instruction.  This is split.  */
 640 #define XS6 URC + 1
 641 #define XT6 XS6
 642   { 0x3f, -1, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
 643
 644   /* The XA field in an XX3 form instruction.  This is split.  */
 645 #define XA6 XT6 + 1
 646   { 0x3f, -1, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
 647
 648   /* The XB field in an XX2 or XX3 form instruction.  This is split.  */
 649 #define XB6 XA6 + 1
 650   { 0x3f, -1, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
 651
 652   /* The XB field in an XX3 form instruction when it must be the same as
 653      the XA field in the instruction.  This is used in extended mnemonics
 654      like xvmovdp.  This is split.  */
 655 #define XB6S XB6 + 1
 656   { 0x3f, -1, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
 657
 658   /* The XC field in an XX4 form instruction.  This is split.  */
 659 #define XC6 XB6S + 1
 660   { 0x3f, -1, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
 661
 662   /* The DM or SHW field in an XX3 form instruction.  */
 663 #define DM XC6 + 1
 664 #define SHW DM
 665   { 0x3, 8, NULL, NULL, 0 },
 666
 667   /* The DM field in an extended mnemonic XX3 form instruction.  */
 668 #define DMEX DM + 1
 669   { 0x3, 8, insert_dm, extract_dm, 0 },
 670
 671   /* The UIM field in an XX2 form instruction.  */
 672 #define UIM DMEX + 1
 673   { 0x3, 16, NULL, NULL, 0 },
 674
 675 #define ERAT_T UIM + 1
 676   { 0x7, 21, NULL, NULL, 0 },
 677 };
 678
 679 const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
 680                                            / sizeof (powerpc_operands[0]));
 681
 682 /* The functions used to insert and extract complicated operands.  */
 683
 684 /* The BA field in an XL form instruction when it must be the same as
 685    the BT field in the same instruction.  This operand is marked FAKE.
 686    The insertion function just copies the BT field into the BA field,
 687    and the extraction function just checks that the fields are the
 688    same.  */
 689
 690 static unsigned long
 691 insert_bat (unsigned long insn,
 692             long value ATTRIBUTE_UNUSED,
 693             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 694             const char **errmsg ATTRIBUTE_UNUSED)
 695 {
 696   return insn | (((insn >> 21) & 0x1f) << 16);
 697 }
 698
 699 static long
 700 extract_bat (unsigned long insn,
 701              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 702              int *invalid)
 703 {
 704   if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
 705     *invalid = 1;
 706   return 0;
 707 }
 708
 709 /* The BB field in an XL form instruction when it must be the same as
 710    the BA field in the same instruction.  This operand is marked FAKE.
 711    The insertion function just copies the BA field into the BB field,
 712    and the extraction function just checks that the fields are the
 713    same.  */
 714
 715 static unsigned long
 716 insert_bba (unsigned long insn,
 717             long value ATTRIBUTE_UNUSED,
 718             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 719             const char **errmsg ATTRIBUTE_UNUSED)
 720 {
 721   return insn | (((insn >> 16) & 0x1f) << 11);
 722 }
 723
 724 static long
 725 extract_bba (unsigned long insn,
 726              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 727              int *invalid)
 728 {
 729   if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
 730     *invalid = 1;
 731   return 0;
 732 }
 733
 734 /* The BD field in a B form instruction when the - modifier is used.
 735    This modifier means that the branch is not expected to be taken.
 736    For chips built to versions of the architecture prior to version 2
 737    (ie. not Power4 compatible), we set the y bit of the BO field to 1
 738    if the offset is negative.  When extracting, we require that the y
 739    bit be 1 and that the offset be positive, since if the y bit is 0
 740    we just want to print the normal form of the instruction.
 741    Power4 compatible targets use two bits, "a", and "t", instead of
 742    the "y" bit.  "at" == 00 => no hint, "at" == 01 => unpredictable,
 743    "at" == 10 => not taken, "at" == 11 => taken.  The "t" bit is 00001
 744    in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
 745    for branch on CTR.  We only handle the taken/not-taken hint here.
 746    Note that we don't relax the conditions tested here when
 747    disassembling with -Many because insns using extract_bdm and
 748    extract_bdp always occur in pairs.  One or the other will always
 749    be valid.  */
 750
 751 static unsigned long
 752 insert_bdm (unsigned long insn,
 753             long value,
 754             ppc_cpu_t dialect,
 755             const char **errmsg ATTRIBUTE_UNUSED)
 756 {
 757   if ((dialect & PPC_OPCODE_POWER4) == 0)
 758     {
 759       if ((value & 0x8000) != 0)
 760         insn |= 1 << 21;
 761     }
 762   else
 763     {
 764       if ((insn & (0x14 << 21)) == (0x04 << 21))
 765         insn |= 0x02 << 21;
 766       else if ((insn & (0x14 << 21)) == (0x10 << 21))
 767         insn |= 0x08 << 21;
 768     }
 769   return insn | (value & 0xfffc);
 770 }
 771
 772 static long
 773 extract_bdm (unsigned long insn,
 774              ppc_cpu_t dialect,
 775              int *invalid)
 776 {
 777   if ((dialect & PPC_OPCODE_POWER4) == 0)
 778     {
 779       if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
 780         *invalid = 1;
 781     }
 782   else
 783     {
 784       if ((insn & (0x17 << 21)) != (0x06 << 21)
 785           && (insn & (0x1d << 21)) != (0x18 << 21))
 786         *invalid = 1;
 787     }
 788
 789   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 790 }
 791
 792 /* The BD field in a B form instruction when the + modifier is used.
 793    This is like BDM, above, except that the branch is expected to be
 794    taken.  */
 795
 796 static unsigned long
 797 insert_bdp (unsigned long insn,
 798             long value,
 799             ppc_cpu_t dialect,
 800             const char **errmsg ATTRIBUTE_UNUSED)
 801 {
 802   if ((dialect & PPC_OPCODE_POWER4) == 0)
 803     {
 804       if ((value & 0x8000) == 0)
 805         insn |= 1 << 21;
 806     }
 807   else
 808     {
 809       if ((insn & (0x14 << 21)) == (0x04 << 21))
 810         insn |= 0x03 << 21;
 811       else if ((insn & (0x14 << 21)) == (0x10 << 21))
 812         insn |= 0x09 << 21;
 813     }
 814   return insn | (value & 0xfffc);
 815 }
 816
 817 static long
 818 extract_bdp (unsigned long insn,
 819              ppc_cpu_t dialect,
 820              int *invalid)
 821 {
 822   if ((dialect & PPC_OPCODE_POWER4) == 0)
 823     {
 824       if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
 825         *invalid = 1;
 826     }
 827   else
 828     {
 829       if ((insn & (0x17 << 21)) != (0x07 << 21)
 830           && (insn & (0x1d << 21)) != (0x19 << 21))
 831         *invalid = 1;
 832     }
 833
 834   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 835 }
 836
 837 /* Check for legal values of a BO field.  */
 838
 839 static int
 840 valid_bo (long value, ppc_cpu_t dialect, int extract)
 841 {
 842   if ((dialect & PPC_OPCODE_POWER4) == 0)
 843     {
 844       int valid;
 845       /* Certain encodings have bits that are required to be zero.
 846          These are (z must be zero, y may be anything):
 847              001zy
 848              011zy
 849              1z00y
 850              1z01y
 851              1z1zz
 852       */
 853       switch (value & 0x14)
 854         {
 855         default:
 856         case 0:
 857           valid = 1;
 858           break;
 859         case 0x4:
 860           valid = (value & 0x2) == 0;
 861           break;
 862         case 0x10:
 863           valid = (value & 0x8) == 0;
 864           break;
 865         case 0x14:
 866           valid = value == 0x14;
 867           break;
 868         }
 869       /* When disassembling with -Many, accept power4 encodings too.  */
 870       if (valid
 871           || (dialect & PPC_OPCODE_ANY) == 0
 872           || !extract)
 873         return valid;
 874     }
 875
 876   /* Certain encodings have bits that are required to be zero.
 877      These are (z must be zero, a & t may be anything):
 878          0000z
 879          0001z
 880          0100z
 881          0101z
 882          001at
 883          011at
 884          1a00t
 885          1a01t
 886          1z1zz
 887   */
 888   if ((value & 0x14) == 0)
 889     return (value & 0x1) == 0;
 890   else if ((value & 0x14) == 0x14)
 891     return value == 0x14;
 892   else
 893     return 1;
 894 }
 895
 896 /* The BO field in a B form instruction.  Warn about attempts to set
 897    the field to an illegal value.  */
 898
 899 static unsigned long
 900 insert_bo (unsigned long insn,
 901            long value,
 902            ppc_cpu_t dialect,
 903            const char **errmsg)
 904 {
 905   if (!valid_bo (value, dialect, 0))
 906     *errmsg = _("invalid conditional option");
 907   else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
 908     *errmsg = _("invalid counter access");
 909   return insn | ((value & 0x1f) << 21);
 910 }
 911
 912 static long
 913 extract_bo (unsigned long insn,
 914             ppc_cpu_t dialect,
 915             int *invalid)
 916 {
 917   long value;
 918
 919   value = (insn >> 21) & 0x1f;
 920   if (!valid_bo (value, dialect, 1))
 921     *invalid = 1;
 922   return value;
 923 }
 924
 925 /* The BO field in a B form instruction when the + or - modifier is
 926    used.  This is like the BO field, but it must be even.  When
 927    extracting it, we force it to be even.  */
 928
 929 static unsigned long
 930 insert_boe (unsigned long insn,
 931             long value,
 932             ppc_cpu_t dialect,
 933             const char **errmsg)
 934 {
 935   if (!valid_bo (value, dialect, 0))
 936     *errmsg = _("invalid conditional option");
 937   else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
 938     *errmsg = _("invalid counter access");
 939   else if ((value & 1) != 0)
 940     *errmsg = _("attempt to set y bit when using + or - modifier");
 941
 942   return insn | ((value & 0x1f) << 21);
 943 }
 944
 945 static long
 946 extract_boe (unsigned long insn,
 947              ppc_cpu_t dialect,
 948              int *invalid)
 949 {
 950   long value;
 951
 952   value = (insn >> 21) & 0x1f;
 953   if (!valid_bo (value, dialect, 1))
 954     *invalid = 1;
 955   return value & 0x1e;
 956 }
 957
 958 /* FXM mask in mfcr and mtcrf instructions.  */
 959
 960 static unsigned long
 961 insert_fxm (unsigned long insn,
 962             long value,
 963             ppc_cpu_t dialect,
 964             const char **errmsg)
 965 {
 966   /* If we're handling the mfocrf and mtocrf insns ensure that exactly
 967      one bit of the mask field is set.  */
 968   if ((insn & (1 << 20)) != 0)
 969     {
 970       if (value == 0 || (value & -value) != value)
 971         {
 972           *errmsg = _("invalid mask field");
 973           value = 0;
 974         }
 975     }
 976
 977   /* If the optional field on mfcr is missing that means we want to use
 978      the old form of the instruction that moves the whole cr.  In that
 979      case we'll have VALUE zero.  There doesn't seem to be a way to
 980      distinguish this from the case where someone writes mfcr %r3,0.  */
 981   else if (value == 0)
 982     ;
 983
 984   /* If only one bit of the FXM field is set, we can use the new form
 985      of the instruction, which is faster.  Unlike the Power4 branch hint
 986      encoding, this is not backward compatible.  Do not generate the
 987      new form unless -mpower4 has been given, or -many and the two
 988      operand form of mfcr was used.  */
 989   else if ((value & -value) == value
 990            && ((dialect & PPC_OPCODE_POWER4) != 0
 991                || ((dialect & PPC_OPCODE_ANY) != 0
 992                    && (insn & (0x3ff << 1)) == 19 << 1)))
 993     insn |= 1 << 20;
 994
 995   /* Any other value on mfcr is an error.  */
 996   else if ((insn & (0x3ff << 1)) == 19 << 1)
 997     {
 998       *errmsg = _("ignoring invalid mfcr mask");
 999       value = 0;
1000     }
1001
1002   return insn | ((value & 0xff) << 12);
1003 }
1004
1005 static long
1006 extract_fxm (unsigned long insn,
1007              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1008              int *invalid)
1009 {
1010   long mask = (insn >> 12) & 0xff;
1011
1012   /* Is this a Power4 insn?  */
1013   if ((insn & (1 << 20)) != 0)
1014     {
1015       /* Exactly one bit of MASK should be set.  */
1016       if (mask == 0 || (mask & -mask) != mask)
1017         *invalid = 1;
1018     }
1019
1020   /* Check that non-power4 form of mfcr has a zero MASK.  */
1021   else if ((insn & (0x3ff << 1)) == 19 << 1)
1022     {
1023       if (mask != 0)
1024         *invalid = 1;
1025     }
1026
1027   return mask;
1028 }
1029
1030 /* The MB and ME fields in an M form instruction expressed as a single
1031    operand which is itself a bitmask.  The extraction function always
1032    marks it as invalid, since we never want to recognize an
1033    instruction which uses a field of this type.  */
1034
1035 static unsigned long
1036 insert_mbe (unsigned long insn,
1037             long value,
1038             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1039             const char **errmsg)
1040 {
1041   unsigned long uval, mask;
1042   int mb, me, mx, count, last;
1043
1044   uval = value;
1045
1046   if (uval == 0)
1047     {
1048       *errmsg = _("illegal bitmask");
1049       return insn;
1050     }
1051
1052   mb = 0;
1053   me = 32;
1054   if ((uval & 1) != 0)
1055     last = 1;
1056   else
1057     last = 0;
1058   count = 0;
1059
1060   /* mb: location of last 0->1 transition */
1061   /* me: location of last 1->0 transition */
1062   /* count: # transitions */
1063
1064   for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1065     {
1066       if ((uval & mask) && !last)
1067         {
1068           ++count;
1069           mb = mx;
1070           last = 1;
1071         }
1072       else if (!(uval & mask) && last)
1073         {
1074           ++count;
1075           me = mx;
1076           last = 0;
1077         }
1078     }
1079   if (me == 0)
1080     me = 32;
1081
1082   if (count != 2 && (count != 0 || ! last))
1083     *errmsg = _("illegal bitmask");
1084
1085   return insn | (mb << 6) | ((me - 1) << 1);
1086 }
1087
1088 static long
1089 extract_mbe (unsigned long insn,
1090              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1091              int *invalid)
1092 {
1093   long ret;
1094   int mb, me;
1095   int i;
1096
1097   *invalid = 1;
1098
1099   mb = (insn >> 6) & 0x1f;
1100   me = (insn >> 1) & 0x1f;
1101   if (mb < me + 1)
1102     {
1103       ret = 0;
1104       for (i = mb; i <= me; i++)
1105         ret |= 1L << (31 - i);
1106     }
1107   else if (mb == me + 1)
1108     ret = ~0;
1109   else /* (mb > me + 1) */
1110     {
1111       ret = ~0;
1112       for (i = me + 1; i < mb; i++)
1113         ret &= ~(1L << (31 - i));
1114     }
1115   return ret;
1116 }
1117
1118 /* The MB or ME field in an MD or MDS form instruction.  The high bit
1119    is wrapped to the low end.  */
1120
1121 static unsigned long
1122 insert_mb6 (unsigned long insn,
1123             long value,
1124             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1125             const char **errmsg ATTRIBUTE_UNUSED)
1126 {
1127   return insn | ((value & 0x1f) << 6) | (value & 0x20);
1128 }
1129
1130 static long
1131 extract_mb6 (unsigned long insn,
1132              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1133              int *invalid ATTRIBUTE_UNUSED)
1134 {
1135   return ((insn >> 6) & 0x1f) | (insn & 0x20);
1136 }
1137
1138 /* The NB field in an X form instruction.  The value 32 is stored as
1139    0.  */
1140
1141 static long
1142 extract_nb (unsigned long insn,
1143             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1144             int *invalid ATTRIBUTE_UNUSED)
1145 {
1146   long ret;
1147
1148   ret = (insn >> 11) & 0x1f;
1149   if (ret == 0)
1150     ret = 32;
1151   return ret;
1152 }
1153
1154 /* The NB field in an lswi instruction, which has special value
1155    restrictions.  The value 32 is stored as 0.  */
1156
1157 static unsigned long
1158 insert_nbi (unsigned long insn,
1159             long value,
1160             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1161             const char **errmsg ATTRIBUTE_UNUSED)
1162 {
1163   long rtvalue = (insn & RT_MASK) >> 21;
1164   long ravalue = (insn & RA_MASK) >> 16;
1165
1166   if (value == 0)
1167     value = 32;
1168   if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32
1169                                                      : ravalue))
1170     *errmsg = _("address register in load range");
1171   return insn | ((value & 0x1f) << 11);
1172 }
1173
1174 /* The NSI field in a D form instruction.  This is the same as the SI
1175    field, only negated.  The extraction function always marks it as
1176    invalid, since we never want to recognize an instruction which uses
1177    a field of this type.  */
1178
1179 static unsigned long
1180 insert_nsi (unsigned long insn,
1181             long value,
1182             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1183             const char **errmsg ATTRIBUTE_UNUSED)
1184 {
1185   return insn | (-value & 0xffff);
1186 }
1187
1188 static long
1189 extract_nsi (unsigned long insn,
1190              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1191              int *invalid)
1192 {
1193   *invalid = 1;
1194   return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1195 }
1196
1197 /* The RA field in a D or X form instruction which is an updating
1198    load, which means that the RA field may not be zero and may not
1199    equal the RT field.  */
1200
1201 static unsigned long
1202 insert_ral (unsigned long insn,
1203             long value,
1204             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1205             const char **errmsg)
1206 {
1207   if (value == 0
1208       || (unsigned long) value == ((insn >> 21) & 0x1f))
1209     *errmsg = "invalid register operand when updating";
1210   return insn | ((value & 0x1f) << 16);
1211 }
1212
1213 /* The RA field in an lmw instruction, which has special value
1214    restrictions.  */
1215
1216 static unsigned long
1217 insert_ram (unsigned long insn,
1218             long value,
1219             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1220             const char **errmsg)
1221 {
1222   if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1223     *errmsg = _("index register in load range");
1224   return insn | ((value & 0x1f) << 16);
1225 }
1226
1227 /* The RA field in the DQ form lq or an lswx instruction, which have special
1228    value restrictions.  */
1229
1230 static unsigned long
1231 insert_raq (unsigned long insn,
1232             long value,
1233             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1234             const char **errmsg)
1235 {
1236   long rtvalue = (insn & RT_MASK) >> 21;
1237
1238   if (value == rtvalue)
1239     *errmsg = _("source and target register operands must be different");
1240   return insn | ((value & 0x1f) << 16);
1241 }
1242
1243 /* The RA field in a D or X form instruction which is an updating
1244    store or an updating floating point load, which means that the RA
1245    field may not be zero.  */
1246
1247 static unsigned long
1248 insert_ras (unsigned long insn,
1249             long value,
1250             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1251             const char **errmsg)
1252 {
1253   if (value == 0)
1254     *errmsg = _("invalid register operand when updating");
1255   return insn | ((value & 0x1f) << 16);
1256 }
1257
1258 /* The RB field in an X form instruction when it must be the same as
1259    the RS field in the instruction.  This is used for extended
1260    mnemonics like mr.  This operand is marked FAKE.  The insertion
1261    function just copies the BT field into the BA field, and the
1262    extraction function just checks that the fields are the same.  */
1263
1264 static unsigned long
1265 insert_rbs (unsigned long insn,
1266             long value ATTRIBUTE_UNUSED,
1267             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1268             const char **errmsg ATTRIBUTE_UNUSED)
1269 {
1270   return insn | (((insn >> 21) & 0x1f) << 11);
1271 }
1272
1273 static long
1274 extract_rbs (unsigned long insn,
1275              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1276              int *invalid)
1277 {
1278   if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1279     *invalid = 1;
1280   return 0;
1281 }
1282
1283 /* The RB field in an lswx instruction, which has special value
1284    restrictions.  */
1285
1286 static unsigned long
1287 insert_rbx (unsigned long insn,
1288             long value,
1289             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1290             const char **errmsg)
1291 {
1292   long rtvalue = (insn & RT_MASK) >> 21;
1293
1294   if (value == rtvalue)
1295     *errmsg = _("source and target register operands must be different");
1296   return insn | ((value & 0x1f) << 11);
1297 }
1298
1299 /* The SH field in an MD form instruction.  This is split.  */
1300
1301 static unsigned long
1302 insert_sh6 (unsigned long insn,
1303             long value,
1304             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1305             const char **errmsg ATTRIBUTE_UNUSED)
1306 {
1307   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1308 }
1309
1310 static long
1311 extract_sh6 (unsigned long insn,
1312              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1313              int *invalid ATTRIBUTE_UNUSED)
1314 {
1315   return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1316 }
1317
1318 /* The SPR field in an XFX form instruction.  This is flipped--the
1319    lower 5 bits are stored in the upper 5 and vice- versa.  */
1320
1321 static unsigned long
1322 insert_spr (unsigned long insn,
1323             long value,
1324             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1325             const char **errmsg ATTRIBUTE_UNUSED)
1326 {
1327   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1328 }
1329
1330 static long
1331 extract_spr (unsigned long insn,
1332              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1333              int *invalid ATTRIBUTE_UNUSED)
1334 {
1335   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1336 }
1337
1338 /* Some dialects have 8 SPRG registers instead of the standard 4.  */
1339
1340 static unsigned long
1341 insert_sprg (unsigned long insn,
1342              long value,
1343              ppc_cpu_t dialect,
1344              const char **errmsg)
1345 {
1346   if (value > 7
1347       || (value > 3
1348           && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0))
1349     *errmsg = _("invalid sprg number");
1350
1351   /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1352      user mode.  Anything else must use spr 272..279.  */
1353   if (value <= 3 || (insn & 0x100) != 0)
1354     value |= 0x10;
1355
1356   return insn | ((value & 0x17) << 16);
1357 }
1358
1359 static long
1360 extract_sprg (unsigned long insn,
1361               ppc_cpu_t dialect,
1362               int *invalid)
1363 {
1364   unsigned long val = (insn >> 16) & 0x1f;
1365
1366   /* mfsprg can use 260..263 and 272..279.  mtsprg only uses spr 272..279
1367      If not BOOKE or 405, then both use only 272..275.  */
1368   if ((val - 0x10 > 3 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0)
1369       || (val - 0x10 > 7 && (insn & 0x100) != 0)
1370       || val <= 3
1371       || (val & 8) != 0)
1372     *invalid = 1;
1373   return val & 7;
1374 }
1375
1376 /* The TBR field in an XFX instruction.  This is just like SPR, but it
1377    is optional.  When TBR is omitted, it must be inserted as 268 (the
1378    magic number of the TB register).  These functions treat 0
1379    (indicating an omitted optional operand) as 268.  This means that
1380    ``mftb 4,0'' is not handled correctly.  This does not matter very
1381    much, since the architecture manual does not define mftb as
1382    accepting any values other than 268 or 269.  */
1383
1384 #define TB (268)
1385
1386 static unsigned long
1387 insert_tbr (unsigned long insn,
1388             long value,
1389             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1390             const char **errmsg ATTRIBUTE_UNUSED)
1391 {
1392   if (value == 0)
1393     value = TB;
1394   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1395 }
1396
1397 static long
1398 extract_tbr (unsigned long insn,
1399              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1400              int *invalid ATTRIBUTE_UNUSED)
1401 {
1402   long ret;
1403
1404   ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1405   if (ret == TB)
1406     ret = 0;
1407   return ret;
1408 }
1409
1410 /* The XT and XS fields in an XX1 or XX3 form instruction.  This is split.  */
1411
1412 static unsigned long
1413 insert_xt6 (unsigned long insn,
1414             long value,
1415             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1416             const char **errmsg ATTRIBUTE_UNUSED)
1417 {
1418   return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
1419 }
1420
1421 static long
1422 extract_xt6 (unsigned long insn,
1423              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1424              int *invalid ATTRIBUTE_UNUSED)
1425 {
1426   return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
1427 }
1428
1429 /* The XA field in an XX3 form instruction.  This is split.  */
1430
1431 static unsigned long
1432 insert_xa6 (unsigned long insn,
1433             long value,
1434             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1435             const char **errmsg ATTRIBUTE_UNUSED)
1436 {
1437   return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
1438 }
1439
1440 static long
1441 extract_xa6 (unsigned long insn,
1442              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1443              int *invalid ATTRIBUTE_UNUSED)
1444 {
1445   return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
1446 }
1447
1448 /* The XB field in an XX3 form instruction.  This is split.  */
1449
1450 static unsigned long
1451 insert_xb6 (unsigned long insn,
1452             long value,
1453             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1454             const char **errmsg ATTRIBUTE_UNUSED)
1455 {
1456   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1457 }
1458
1459 static long
1460 extract_xb6 (unsigned long insn,
1461              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1462              int *invalid ATTRIBUTE_UNUSED)
1463 {
1464   return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
1465 }
1466
1467 /* The XB field in an XX3 form instruction when it must be the same as
1468    the XA field in the instruction.  This is used for extended
1469    mnemonics like xvmovdp.  This operand is marked FAKE.  The insertion
1470    function just copies the XA field into the XB field, and the
1471    extraction function just checks that the fields are the same.  */
1472
1473 static unsigned long
1474 insert_xb6s (unsigned long insn,
1475             long value ATTRIBUTE_UNUSED,
1476             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1477             const char **errmsg ATTRIBUTE_UNUSED)
1478 {
1479   return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
1480 }
1481
1482 static long
1483 extract_xb6s (unsigned long insn,
1484              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1485              int *invalid)
1486 {
1487   if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
1488       || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
1489     *invalid = 1;
1490   return 0;
1491 }
1492
1493 /* The XC field in an XX4 form instruction.  This is split.  */
1494
1495 static unsigned long
1496 insert_xc6 (unsigned long insn,
1497             long value,
1498             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1499             const char **errmsg ATTRIBUTE_UNUSED)
1500 {
1501   return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2);
1502 }
1503
1504 static long
1505 extract_xc6 (unsigned long insn,
1506              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1507              int *invalid ATTRIBUTE_UNUSED)
1508 {
1509   return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
1510 }
1511
1512 static unsigned long
1513 insert_dm (unsigned long insn,
1514            long value,
1515            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1516            const char **errmsg)
1517 {
1518   if (value != 0 && value != 1)
1519     *errmsg = _("invalid constant");
1520   return insn | (((value) ? 3 : 0) << 8);
1521 }
1522
1523 static long
1524 extract_dm (unsigned long insn,
1525             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1526             int *invalid)
1527 {
1528   long value;
1529
1530   value = (insn >> 8) & 3;
1531   if (value != 0 && value != 3)
1532     *invalid = 1;
1533   return (value) ? 1 : 0;
1534 }
1535 \f
1536 /* Macros used to form opcodes.  */
1537
1538 /* The main opcode.  */
1539 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1540 #define OP_MASK OP (0x3f)
1541
1542 /* The main opcode combined with a trap code in the TO field of a D
1543    form instruction.  Used for extended mnemonics for the trap
1544    instructions.  */
1545 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1546 #define OPTO_MASK (OP_MASK | TO_MASK)
1547
1548 /* The main opcode combined with a comparison size bit in the L field
1549    of a D form or X form instruction.  Used for extended mnemonics for
1550    the comparison instructions.  */
1551 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1552 #define OPL_MASK OPL (0x3f,1)
1553
1554 /* An A form instruction.  */
1555 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1556 #define A_MASK A (0x3f, 0x1f, 1)
1557
1558 /* An A_MASK with the FRB field fixed.  */
1559 #define AFRB_MASK (A_MASK | FRB_MASK)
1560
1561 /* An A_MASK with the FRC field fixed.  */
1562 #define AFRC_MASK (A_MASK | FRC_MASK)
1563
1564 /* An A_MASK with the FRA and FRC fields fixed.  */
1565 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1566
1567 /* An AFRAFRC_MASK, but with L bit clear.  */
1568 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
1569
1570 /* A B form instruction.  */
1571 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1572 #define B_MASK B (0x3f, 1, 1)
1573
1574 /* A B form instruction setting the BO field.  */
1575 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1576 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1577
1578 /* A BBO_MASK with the y bit of the BO field removed.  This permits
1579    matching a conditional branch regardless of the setting of the y
1580    bit.  Similarly for the 'at' bits used for power4 branch hints.  */
1581 #define Y_MASK   (((unsigned long) 1) << 21)
1582 #define AT1_MASK (((unsigned long) 3) << 21)
1583 #define AT2_MASK (((unsigned long) 9) << 21)
1584 #define BBOY_MASK  (BBO_MASK &~ Y_MASK)
1585 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1586
1587 /* A B form instruction setting the BO field and the condition bits of
1588    the BI field.  */
1589 #define BBOCB(op, bo, cb, aa, lk) \
1590   (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1591 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1592
1593 /* A BBOCB_MASK with the y bit of the BO field removed.  */
1594 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1595 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1596 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1597
1598 /* A BBOYCB_MASK in which the BI field is fixed.  */
1599 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1600 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1601
1602 /* An Context form instruction.  */
1603 #define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
1604 #define CTX_MASK CTX(0x3f, 0x7)
1605
1606 /* An User Context form instruction.  */
1607 #define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1608 #define UCTX_MASK UCTX(0x3f, 0x1f)
1609
1610 /* The main opcode mask with the RA field clear.  */
1611 #define DRA_MASK (OP_MASK | RA_MASK)
1612
1613 /* A DS form instruction.  */
1614 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1615 #define DS_MASK DSO (0x3f, 3)
1616
1617 /* An EVSEL form instruction.  */
1618 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1619 #define EVSEL_MASK EVSEL(0x3f, 0xff)
1620
1621 /* An M form instruction.  */
1622 #define M(op, rc) (OP (op) | ((rc) & 1))
1623 #define M_MASK M (0x3f, 1)
1624
1625 /* An M form instruction with the ME field specified.  */
1626 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1627
1628 /* An M_MASK with the MB and ME fields fixed.  */
1629 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1630
1631 /* An M_MASK with the SH and ME fields fixed.  */
1632 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1633
1634 /* An MD form instruction.  */
1635 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1636 #define MD_MASK MD (0x3f, 0x7, 1)
1637
1638 /* An MD_MASK with the MB field fixed.  */
1639 #define MDMB_MASK (MD_MASK | MB6_MASK)
1640
1641 /* An MD_MASK with the SH field fixed.  */
1642 #define MDSH_MASK (MD_MASK | SH6_MASK)
1643
1644 /* An MDS form instruction.  */
1645 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1646 #define MDS_MASK MDS (0x3f, 0xf, 1)
1647
1648 /* An MDS_MASK with the MB field fixed.  */
1649 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1650
1651 /* An SC form instruction.  */
1652 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1653 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1654
1655 /* An VX form instruction.  */
1656 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1657
1658 /* The mask for an VX form instruction.  */
1659 #define VX_MASK VX(0x3f, 0x7ff)
1660
1661 /* An VA form instruction.  */
1662 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1663
1664 /* The mask for an VA form instruction.  */
1665 #define VXA_MASK VXA(0x3f, 0x3f)
1666
1667 /* An VXR form instruction.  */
1668 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1669
1670 /* The mask for a VXR form instruction.  */
1671 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1672
1673 /* An X form instruction.  */
1674 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1675
1676 /* An XX2 form instruction.  */
1677 #define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
1678
1679 /* An XX3 form instruction.  */
1680 #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
1681
1682 /* An XX3 form instruction with the RC bit specified.  */
1683 #define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
1684
1685 /* An XX4 form instruction.  */
1686 #define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
1687
1688 /* A Z form instruction.  */
1689 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1690
1691 /* An X form instruction with the RC bit specified.  */
1692 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1693
1694 /* A Z form instruction with the RC bit specified.  */
1695 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1696
1697 /* The mask for an X form instruction.  */
1698 #define X_MASK XRC (0x3f, 0x3ff, 1)
1699
1700 /* An X form wait instruction with everything filled in except the WC field.  */
1701 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
1702
1703 /* The mask for an XX1 form instruction.  */
1704 #define XX1_MASK X (0x3f, 0x3ff)
1705
1706 /* The mask for an XX2 form instruction.  */
1707 #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
1708
1709 /* The mask for an XX2 form instruction with the UIM bits specified.  */
1710 #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
1711
1712 /* The mask for an XX2 form instruction with the BF bits specified.  */
1713 #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
1714
1715 /* The mask for an XX3 form instruction.  */
1716 #define XX3_MASK XX3 (0x3f, 0xff)
1717
1718 /* The mask for an XX3 form instruction with the BF bits specified.  */
1719 #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
1720
1721 /* The mask for an XX3 form instruction with the DM or SHW bits specified.  */
1722 #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
1723 #define XX3SHW_MASK XX3DM_MASK
1724
1725 /* The mask for an XX4 form instruction.  */
1726 #define XX4_MASK XX4 (0x3f, 0x3)
1727
1728 /* An X form wait instruction with everything filled in except the WC field.  */
1729 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
1730
1731 /* The mask for a Z form instruction.  */
1732 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
1733 #define Z2_MASK ZRC (0x3f, 0xff, 1)
1734
1735 /* An X_MASK with the RA field fixed.  */
1736 #define XRA_MASK (X_MASK | RA_MASK)
1737
1738 /* An XRA_MASK with the W field clear.  */
1739 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
1740
1741 /* An X_MASK with the RB field fixed.  */
1742 #define XRB_MASK (X_MASK | RB_MASK)
1743
1744 /* An X_MASK with the RT field fixed.  */
1745 #define XRT_MASK (X_MASK | RT_MASK)
1746
1747 /* An XRT_MASK mask with the L bits clear.  */
1748 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
1749
1750 /* An X_MASK with the RA and RB fields fixed.  */
1751 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1752
1753 /* An XRARB_MASK, but with the L bit clear.  */
1754 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1755
1756 /* An X_MASK with the RT and RA fields fixed.  */
1757 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1758
1759 /* An XRTRA_MASK, but with L bit clear.  */
1760 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1761
1762 /* An X form instruction with the L bit specified.  */
1763 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1764
1765 /* An X form instruction with the L bits specified.  */
1766 #define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1767
1768 /* An X form instruction with RT fields specified */
1769 #define XRT(op, xop, rt) (X ((op), (xop)) \
1770         | ((((unsigned long)(rt)) & 0x1f) << 21))
1771
1772 /* An X form instruction with RT and RA fields specified */
1773 #define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
1774         | ((((unsigned long)(rt)) & 0x1f) << 21) \
1775         | ((((unsigned long)(ra)) & 0x1f) << 16))
1776
1777 /* The mask for an X form comparison instruction.  */
1778 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1779
1780 /* The mask for an X form comparison instruction with the L field
1781    fixed.  */
1782 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1783
1784 /* An X form trap instruction with the TO field specified.  */
1785 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1786 #define XTO_MASK (X_MASK | TO_MASK)
1787
1788 /* An X form tlb instruction with the SH field specified.  */
1789 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1790 #define XTLB_MASK (X_MASK | SH_MASK)
1791
1792 /* An X form sync instruction.  */
1793 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1794
1795 /* An X form sync instruction with everything filled in except the LS field.  */
1796 #define XSYNC_MASK (0xff9fffff)
1797
1798 /* An X_MASK, but with the EH bit clear.  */
1799 #define XEH_MASK (X_MASK & ~((unsigned long )1))
1800
1801 /* An X form AltiVec dss instruction.  */
1802 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1803 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1804
1805 /* An XFL form instruction.  */
1806 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1807 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
1808
1809 /* An X form isel instruction.  */
1810 #define XISEL(op, xop)  (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1811 #define XISEL_MASK      XISEL(0x3f, 0x1f)
1812
1813 /* An XL form instruction with the LK field set to 0.  */
1814 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1815
1816 /* An XL form instruction which uses the LK field.  */
1817 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1818
1819 /* The mask for an XL form instruction.  */
1820 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1821
1822 /* An XL form instruction which explicitly sets the BO field.  */
1823 #define XLO(op, bo, xop, lk) \
1824   (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1825 #define XLO_MASK (XL_MASK | BO_MASK)
1826
1827 /* An XL form instruction which explicitly sets the y bit of the BO
1828    field.  */
1829 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1830 #define XLYLK_MASK (XL_MASK | Y_MASK)
1831
1832 /* An XL form instruction which sets the BO field and the condition
1833    bits of the BI field.  */
1834 #define XLOCB(op, bo, cb, xop, lk) \
1835   (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1836 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1837
1838 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
1839 #define XLBB_MASK (XL_MASK | BB_MASK)
1840 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1841 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1842
1843 /* A mask for branch instructions using the BH field.  */
1844 #define XLBH_MASK (XL_MASK | (0x1c << 11))
1845
1846 /* An XL_MASK with the BO and BB fields fixed.  */
1847 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1848
1849 /* An XL_MASK with the BO, BI and BB fields fixed.  */
1850 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1851
1852 /* An X form mbar instruction with MO field.  */
1853 #define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21))
1854
1855 /* An XO form instruction.  */
1856 #define XO(op, xop, oe, rc) \
1857   (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1858 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1859
1860 /* An XO_MASK with the RB field fixed.  */
1861 #define XORB_MASK (XO_MASK | RB_MASK)
1862
1863 /* An XOPS form instruction for paired singles.  */
1864 #define XOPS(op, xop, rc) \
1865   (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1866 #define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
1867
1868
1869 /* An XS form instruction.  */
1870 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1871 #define XS_MASK XS (0x3f, 0x1ff, 1)
1872
1873 /* A mask for the FXM version of an XFX form instruction.  */
1874 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
1875
1876 /* An XFX form instruction with the FXM field filled in.  */
1877 #define XFXM(op, xop, fxm, p4) \
1878   (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1879    | ((unsigned long)(p4) << 20))
1880
1881 /* An XFX form instruction with the SPR field filled in.  */
1882 #define XSPR(op, xop, spr) \
1883   (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1884 #define XSPR_MASK (X_MASK | SPR_MASK)
1885
1886 /* An XFX form instruction with the SPR field filled in except for the
1887    SPRBAT field.  */
1888 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1889
1890 /* An XFX form instruction with the SPR field filled in except for the
1891    SPRG field.  */
1892 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
1893
1894 /* An X form instruction with everything filled in except the E field.  */
1895 #define XE_MASK (0xffff7fff)
1896
1897 /* An X form user context instruction.  */
1898 #define XUC(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1899 #define XUC_MASK      XUC(0x3f, 0x1f)
1900
1901 /* An XW form instruction.  */
1902 #define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
1903 /* The mask for a G form instruction. rc not supported at present.  */
1904 #define XW_MASK XW (0x3f, 0x3f, 0)
1905
1906 /* An APU form instruction.  */
1907 #define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
1908
1909 /* The mask for an APU form instruction.  */
1910 #define APU_MASK APU (0x3f, 0x3ff, 1)
1911 #define APU_RT_MASK (APU_MASK | RT_MASK)
1912 #define APU_RA_MASK (APU_MASK | RA_MASK)
1913
1914 /* The BO encodings used in extended conditional branch mnemonics.  */
1915 #define BODNZF  (0x0)
1916 #define BODNZFP (0x1)
1917 #define BODZF   (0x2)
1918 #define BODZFP  (0x3)
1919 #define BODNZT  (0x8)
1920 #define BODNZTP (0x9)
1921 #define BODZT   (0xa)
1922 #define BODZTP  (0xb)
1923
1924 #define BOF     (0x4)
1925 #define BOFP    (0x5)
1926 #define BOFM4   (0x6)
1927 #define BOFP4   (0x7)
1928 #define BOT     (0xc)
1929 #define BOTP    (0xd)
1930 #define BOTM4   (0xe)
1931 #define BOTP4   (0xf)
1932
1933 #define BODNZ   (0x10)
1934 #define BODNZP  (0x11)
1935 #define BODZ    (0x12)
1936 #define BODZP   (0x13)
1937 #define BODNZM4 (0x18)
1938 #define BODNZP4 (0x19)
1939 #define BODZM4  (0x1a)
1940 #define BODZP4  (0x1b)
1941
1942 #define BOU     (0x14)
1943
1944 /* The BI condition bit encodings used in extended conditional branch
1945    mnemonics.  */
1946 #define CBLT    (0)
1947 #define CBGT    (1)
1948 #define CBEQ    (2)
1949 #define CBSO    (3)
1950
1951 /* The TO encodings used in extended trap mnemonics.  */
1952 #define TOLGT   (0x1)
1953 #define TOLLT   (0x2)
1954 #define TOEQ    (0x4)
1955 #define TOLGE   (0x5)
1956 #define TOLNL   (0x5)
1957 #define TOLLE   (0x6)
1958 #define TOLNG   (0x6)
1959 #define TOGT    (0x8)
1960 #define TOGE    (0xc)
1961 #define TONL    (0xc)
1962 #define TOLT    (0x10)
1963 #define TOLE    (0x14)
1964 #define TONG    (0x14)
1965 #define TONE    (0x18)
1966 #define TOU     (0x1f)
1967 \f
1968 /* Smaller names for the flags so each entry in the opcodes table will
1969    fit on a single line.  */
1970 #define PPCNONE 0
1971 #undef  PPC
1972 #define PPC     PPC_OPCODE_PPC
1973 #define PPCCOM  PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1974 #define POWER4  PPC_OPCODE_POWER4
1975 #define POWER5  PPC_OPCODE_POWER5
1976 #define POWER6  PPC_OPCODE_POWER6
1977 #define POWER7  PPC_OPCODE_POWER7
1978 #define CELL    PPC_OPCODE_CELL
1979 #define PPC64   PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
1980 #define NON32   (PPC_OPCODE_64 | PPC_OPCODE_POWER4      \
1981                  | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
1982 #define PPC403  PPC_OPCODE_403
1983 #define PPC405  PPC_OPCODE_405
1984 #define PPC440  PPC_OPCODE_440
1985 #define PPC464  PPC440
1986 #define PPC476  PPC_OPCODE_476
1987 #define PPC750  PPC
1988 #define PPC7450 PPC
1989 #define PPC860  PPC
1990 #define PPCPS   PPC_OPCODE_PPCPS
1991 #define PPCVEC  PPC_OPCODE_ALTIVEC
1992 #define PPCVSX  PPC_OPCODE_VSX
1993 #define POWER   PPC_OPCODE_POWER
1994 #define POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1995 #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
1996 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
1997 #define COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1998 #define M601    PPC_OPCODE_POWER | PPC_OPCODE_601
1999 #define PWRCOM  PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
2000 #define MFDEC1  PPC_OPCODE_POWER
2001 #define MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
2002 #define BOOKE   PPC_OPCODE_BOOKE
2003 #define NO371   PPC_OPCODE_BOOKE | PPC_OPCODE_EFS
2004 #define PPCE300 PPC_OPCODE_E300
2005 #define PPCSPE  PPC_OPCODE_SPE
2006 #define PPCISEL PPC_OPCODE_ISEL
2007 #define PPCEFS  PPC_OPCODE_EFS
2008 #define PPCBRLK PPC_OPCODE_BRLOCK
2009 #define PPCPMR  PPC_OPCODE_PMR
2010 #define PPCCHLK PPC_OPCODE_CACHELCK
2011 #define PPCRFMCI        PPC_OPCODE_RFMCI
2012 #define E500MC  PPC_OPCODE_E500MC
2013 #define PPCA2   PPC_OPCODE_A2
2014 #define TITAN   PPC_OPCODE_TITAN
2015 #define MULHW   PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN
2016 #define E500    PPC_OPCODE_E500
2017 \f
2018 /* The opcode table.
2019
2020    The format of the opcode table is:
2021
2022    NAME         OPCODE          MASK         FLAGS      {OPERANDS}
2023
2024    NAME is the name of the instruction.
2025    OPCODE is the instruction opcode.
2026    MASK is the opcode mask; this is used to tell the disassembler
2027      which bits in the actual opcode must match OPCODE.
2028    FLAGS are flags indicated what processors support the instruction.
2029    OPERANDS is the list of operands.
2030
2031    The disassembler reads the table in order and prints the first
2032    instruction which matches, so this table is sorted to put more
2033    specific instructions before more general instructions.
2034
2035    This table must be sorted by major opcode.  Please try to keep it
2036    vaguely sorted within major opcode too, except of course where
2037    constrained otherwise by disassembler operation.  */
2038
2039 const struct powerpc_opcode powerpc_opcodes[] = {
2040 {"attn",        X(0,256),       X_MASK,   POWER4|PPCA2, PPC476,         {0}},
2041 {"tdlgti",      OPTO(2,TOLGT),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2042 {"tdllti",      OPTO(2,TOLLT),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2043 {"tdeqi",       OPTO(2,TOEQ),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2044 {"tdlgei",      OPTO(2,TOLGE),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2045 {"tdlnli",      OPTO(2,TOLNL),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2046 {"tdllei",      OPTO(2,TOLLE),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2047 {"tdlngi",      OPTO(2,TOLNG),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2048 {"tdgti",       OPTO(2,TOGT),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2049 {"tdgei",       OPTO(2,TOGE),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2050 {"tdnli",       OPTO(2,TONL),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2051 {"tdlti",       OPTO(2,TOLT),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2052 {"tdlei",       OPTO(2,TOLE),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2053 {"tdngi",       OPTO(2,TONG),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2054 {"tdnei",       OPTO(2,TONE),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2055 {"tdi",         OP(2),          OP_MASK,     PPC64,     PPCNONE,        {TO, RA, SI}},
2056
2057 {"twlgti",      OPTO(3,TOLGT),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2058 {"tlgti",       OPTO(3,TOLGT),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2059 {"twllti",      OPTO(3,TOLLT),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2060 {"tllti",       OPTO(3,TOLLT),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2061 {"tweqi",       OPTO(3,TOEQ),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2062 {"teqi",        OPTO(3,TOEQ),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2063 {"twlgei",      OPTO(3,TOLGE),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2064 {"tlgei",       OPTO(3,TOLGE),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2065 {"twlnli",      OPTO(3,TOLNL),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2066 {"tlnli",       OPTO(3,TOLNL),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2067 {"twllei",      OPTO(3,TOLLE),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2068 {"tllei",       OPTO(3,TOLLE),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2069 {"twlngi",      OPTO(3,TOLNG),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2070 {"tlngi",       OPTO(3,TOLNG),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2071 {"twgti",       OPTO(3,TOGT),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2072 {"tgti",        OPTO(3,TOGT),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2073 {"twgei",       OPTO(3,TOGE),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2074 {"tgei",        OPTO(3,TOGE),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2075 {"twnli",       OPTO(3,TONL),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2076 {"tnli",        OPTO(3,TONL),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2077 {"twlti",       OPTO(3,TOLT),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2078 {"tlti",        OPTO(3,TOLT),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2079 {"twlei",       OPTO(3,TOLE),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2080 {"tlei",        OPTO(3,TOLE),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2081 {"twngi",       OPTO(3,TONG),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2082 {"tngi",        OPTO(3,TONG),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2083 {"twnei",       OPTO(3,TONE),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2084 {"tnei",        OPTO(3,TONE),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2085 {"twi",         OP(3),          OP_MASK,     PPCCOM,    PPCNONE,        {TO, RA, SI}},
2086 {"ti",          OP(3),          OP_MASK,     PWRCOM,    PPCNONE,        {TO, RA, SI}},
2087
2088 {"ps_cmpu0",    X  (4,   0), X_MASK|(3<<21), PPCPS,     PPCNONE,        {BF, FRA, FRB}},
2089 {"vaddubm",     VX (4,   0),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2090 {"vmaxub",      VX (4,   2),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2091 {"vrlb",        VX (4,   4),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2092 {"vcmpequb",    VXR(4,   6,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2093 {"vmuloub",     VX (4,   8),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2094 {"vaddfp",      VX (4,  10),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2095 {"psq_lx",      XW (4,   6,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRT,RA,RB,PSWM,PSQM}},
2096 {"vmrghb",      VX (4,  12),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2097 {"psq_stx",     XW (4,   7,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRS,RA,RB,PSWM,PSQM}},
2098 {"vpkuhum",     VX (4,  14),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2099 {"mulhhwu",     XRC(4,   8,0),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2100 {"mulhhwu.",    XRC(4,   8,1),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2101 {"ps_sum0",     A  (4,  10,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2102 {"ps_sum0.",    A  (4,  10,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2103 {"ps_sum1",     A  (4,  11,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2104 {"ps_sum1.",    A  (4,  11,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2105 {"ps_muls0",    A  (4,  12,0),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2106 {"machhwu",     XO (4,  12,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2107 {"ps_muls0.",   A  (4,  12,1),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2108 {"machhwu.",    XO (4,  12,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2109 {"ps_muls1",    A  (4,  13,0),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2110 {"ps_muls1.",   A  (4,  13,1),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2111 {"ps_madds0",   A  (4,  14,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2112 {"ps_madds0.",  A  (4,  14,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2113 {"ps_madds1",   A  (4,  15,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2114 {"ps_madds1.",  A  (4,  15,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2115 {"vmhaddshs",   VXA(4,  32),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2116 {"vmhraddshs",  VXA(4,  33),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2117 {"vmladduhm",   VXA(4,  34),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2118 {"ps_div",      A  (4,  18,0),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2119 {"vmsumubm",    VXA(4,  36),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2120 {"ps_div.",     A  (4,  18,1),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2121 {"vmsummbm",    VXA(4,  37),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2122 {"vmsumuhm",    VXA(4,  38),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2123 {"vmsumuhs",    VXA(4,  39),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2124 {"ps_sub",      A  (4,  20,0),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2125 {"vmsumshm",    VXA(4,  40),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2126 {"ps_sub.",     A  (4,  20,1),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2127 {"vmsumshs",    VXA(4,  41),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2128 {"ps_add",      A  (4,  21,0),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2129 {"vsel",        VXA(4,  42),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2130 {"ps_add.",     A  (4,  21,1),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2131 {"vperm",       VXA(4,  43),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2132 {"vsldoi",      VXA(4,  44),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, SHB}},
2133 {"ps_sel",      A  (4,  23,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2134 {"vmaddfp",     VXA(4,  46),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VC, VB}},
2135 {"ps_sel.",     A  (4,  23,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2136 {"vnmsubfp",    VXA(4,  47),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VC, VB}},
2137 {"ps_res",      A  (4,  24,0), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
2138 {"ps_res.",     A  (4,  24,1), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
2139 {"ps_mul",      A  (4,  25,0), AFRB_MASK,    PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2140 {"ps_mul.",     A  (4,  25,1),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2141 {"ps_rsqrte",   A  (4,  26,0), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
2142 {"ps_rsqrte.",  A  (4,  26,1), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
2143 {"ps_msub",     A  (4,  28,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2144 {"ps_msub.",    A  (4,  28,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2145 {"ps_madd",     A  (4,  29,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2146 {"ps_madd.",    A  (4,  29,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2147 {"ps_nmsub",    A  (4,  30,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2148 {"ps_nmsub.",   A  (4,  30,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2149 {"ps_nmadd",    A  (4,  31,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2150 {"ps_nmadd.",   A  (4,  31,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2151 {"ps_cmpo0",    X  (4,  32), X_MASK|(3<<21), PPCPS,     PPCNONE,        {BF, FRA, FRB}},
2152 {"vadduhm",     VX (4,  64),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2153 {"vmaxuh",      VX (4,  66),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2154 {"vrlh",        VX (4,  68),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2155 {"vcmpequh",    VXR(4,  70,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2156 {"vmulouh",     VX (4,  72),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2157 {"vsubfp",      VX (4,  74),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2158 {"psq_lux",     XW (4,  38,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRT,RA,RB,PSWM,PSQM}},
2159 {"vmrghh",      VX (4,  76),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2160 {"psq_stux",    XW (4,  39,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRS,RA,RB,PSWM,PSQM}},
2161 {"vpkuwum",     VX (4,  78),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2162 {"ps_neg",      XRC(4,  40,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2163 {"mulhhw",      XRC(4,  40,0),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2164 {"ps_neg.",     XRC(4,  40,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2165 {"mulhhw.",     XRC(4,  40,1),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2166 {"machhw",      XO (4,  44,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2167 {"machhw.",     XO (4,  44,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2168 {"nmachhw",     XO (4,  46,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2169 {"nmachhw.",    XO (4,  46,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2170 {"ps_cmpu1",    X  (4,  64), X_MASK|(3<<21), PPCPS,     PPCNONE,        {BF, FRA, FRB}},
2171 {"vadduwm",     VX (4,  128),   VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2172 {"vmaxuw",      VX (4,  130),   VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2173 {"vrlw",        VX (4,  132),   VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2174 {"vcmpequw",    VXR(4,  134,0), VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2175 {"vmrghw",      VX (4,  140),   VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2176 {"vpkuhus",     VX (4,  142),   VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2177 {"ps_mr",       XRC(4,  72,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2178 {"ps_mr.",      XRC(4,  72,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2179 {"machhwsu",    XO (4,  76,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2180 {"machhwsu.",   XO (4,  76,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2181 {"ps_cmpo1",    X  (4,  96), X_MASK|(3<<21), PPCPS,     PPCNONE,        {BF, FRA, FRB}},
2182 {"vcmpeqfp",    VXR(4, 198,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2183 {"vpkuwus",     VX (4, 206),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2184 {"machhws",     XO (4, 108,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2185 {"machhws.",    XO (4, 108,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2186 {"nmachhws",    XO (4, 110,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2187 {"nmachhws.",   XO (4, 110,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2188 {"vmaxsb",      VX (4, 258),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2189 {"vslb",        VX (4, 260),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2190 {"vmulosb",     VX (4, 264),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2191 {"vrefp",       VX (4, 266),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2192 {"vmrglb",      VX (4, 268),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2193 {"vpkshus",     VX (4, 270),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2194 {"ps_nabs",     XRC(4, 136,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2195 {"mulchwu",     XRC(4, 136,0),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2196 {"ps_nabs.",    XRC(4, 136,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2197 {"mulchwu.",    XRC(4, 136,1),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2198 {"macchwu",     XO (4, 140,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2199 {"macchwu.",    XO (4, 140,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2200 {"vmaxsh",      VX (4, 322),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2201 {"vslh",        VX (4, 324),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2202 {"vmulosh",     VX (4, 328),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2203 {"vrsqrtefp",   VX (4, 330),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2204 {"vmrglh",      VX (4, 332),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2205 {"vpkswus",     VX (4, 334),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2206 {"mulchw",      XRC(4, 168,0),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2207 {"mulchw.",     XRC(4, 168,1),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2208 {"macchw",      XO (4, 172,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2209 {"macchw.",     XO (4, 172,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2210 {"nmacchw",     XO (4, 174,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2211 {"nmacchw.",    XO (4, 174,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2212 {"vaddcuw",     VX (4, 384),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2213 {"vmaxsw",      VX (4, 386),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2214 {"vslw",        VX (4, 388),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2215 {"vexptefp",    VX (4, 394),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2216 {"vmrglw",      VX (4, 396),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2217 {"vpkshss",     VX (4, 398),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2218 {"macchwsu",    XO (4, 204,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2219 {"macchwsu.",   XO (4, 204,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2220 {"vsl",         VX (4, 452),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2221 {"vcmpgefp",    VXR(4, 454,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2222 {"vlogefp",     VX (4, 458),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2223 {"vpkswss",     VX (4, 462),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2224 {"macchws",     XO (4, 236,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2225 {"macchws.",    XO (4, 236,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2226 {"nmacchws",    XO (4, 238,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2227 {"nmacchws.",   XO (4, 238,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2228 {"evaddw",      VX (4, 512),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2229 {"vaddubs",     VX (4, 512),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2230 {"evaddiw",     VX (4, 514),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB, UIMM}},
2231 {"vminub",      VX (4, 514),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2232 {"evsubfw",     VX (4, 516),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2233 {"evsubw",      VX (4, 516),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB, RA}},
2234 {"vsrb",        VX (4, 516),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2235 {"evsubifw",    VX (4, 518),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, UIMM, RB}},
2236 {"evsubiw",     VX (4, 518),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB, UIMM}},
2237 {"vcmpgtub",    VXR(4, 518,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2238 {"evabs",       VX (4, 520),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2239 {"vmuleub",     VX (4, 520),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2240 {"evneg",       VX (4, 521),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2241 {"evextsb",     VX (4, 522),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2242 {"vrfin",       VX (4, 522),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2243 {"evextsh",     VX (4, 523),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2244 {"evrndw",      VX (4, 524),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2245 {"vspltb",      VX (4, 524),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB, UIMM}},
2246 {"evcntlzw",    VX (4, 525),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2247 {"evcntlsw",    VX (4, 526),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2248 {"vupkhsb",     VX (4, 526),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2249 {"brinc",       VX (4, 527),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2250 {"ps_abs",      XRC(4, 264,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2251 {"ps_abs.",     XRC(4, 264,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2252 {"evand",       VX (4, 529),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2253 {"evandc",      VX (4, 530),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2254 {"evxor",       VX (4, 534),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2255 {"evmr",        VX (4, 535),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, BBA}},
2256 {"evor",        VX (4, 535),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2257 {"evnor",       VX (4, 536),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2258 {"evnot",       VX (4, 536),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, BBA}},
2259 {"get",         APU(4, 268,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
2260 {"eveqv",       VX (4, 537),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2261 {"evorc",       VX (4, 539),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2262 {"evnand",      VX (4, 542),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2263 {"evsrwu",      VX (4, 544),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2264 {"evsrws",      VX (4, 545),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2265 {"evsrwiu",     VX (4, 546),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, EVUIMM}},
2266 {"evsrwis",     VX (4, 547),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, EVUIMM}},
2267 {"evslw",       VX (4, 548),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2268 {"evslwi",      VX (4, 550),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, EVUIMM}},
2269 {"evrlw",       VX (4, 552),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2270 {"evsplati",    VX (4, 553),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, SIMM}},
2271 {"evrlwi",      VX (4, 554),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, EVUIMM}},
2272 {"evsplatfi",   VX (4, 555),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, SIMM}},
2273 {"evmergehi",   VX (4, 556),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2274 {"evmergelo",   VX (4, 557),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2275 {"evmergehilo", VX (4, 558),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2276 {"evmergelohi", VX (4, 559),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2277 {"evcmpgtu",    VX (4, 560),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2278 {"evcmpgts",    VX (4, 561),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2279 {"evcmpltu",    VX (4, 562),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2280 {"evcmplts",    VX (4, 563),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2281 {"evcmpeq",     VX (4, 564),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2282 {"cget",        APU(4, 284,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
2283 {"vadduhs",     VX (4, 576),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2284 {"vminuh",      VX (4, 578),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2285 {"vsrh",        VX (4, 580),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2286 {"vcmpgtuh",    VXR(4, 582,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2287 {"vmuleuh",     VX (4, 584),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2288 {"vrfiz",       VX (4, 586),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2289 {"vsplth",      VX (4, 588),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB, UIMM}},
2290 {"vupkhsh",     VX (4, 590),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2291 {"nget",        APU(4, 300,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
2292 {"evsel",       EVSEL(4,79),    EVSEL_MASK,  PPCSPE,    PPCNONE,        {RS, RA, RB, CRFS}},
2293 {"ncget",       APU(4, 316,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
2294 {"evfsadd",     VX (4, 640),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2295 {"vadduws",     VX (4, 640),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2296 {"evfssub",     VX (4, 641),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2297 {"vminuw",      VX (4, 642),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2298 {"evfsabs",     VX (4, 644),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2299 {"vsrw",        VX (4, 644),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2300 {"evfsnabs",    VX (4, 645),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2301 {"evfsneg",     VX (4, 646),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2302 {"vcmpgtuw",    VXR(4, 646,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2303 {"evfsmul",     VX (4, 648),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2304 {"evfsdiv",     VX (4, 649),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2305 {"vrfip",       VX (4, 650),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2306 {"evfscmpgt",   VX (4, 652),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2307 {"vspltw",      VX (4, 652),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB, UIMM}},
2308 {"evfscmplt",   VX (4, 653),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2309 {"evfscmpeq",   VX (4, 654),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2310 {"vupklsb",     VX (4, 654),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2311 {"evfscfui",    VX (4, 656),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2312 {"evfscfsi",    VX (4, 657),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2313 {"evfscfuf",    VX (4, 658),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2314 {"evfscfsf",    VX (4, 659),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2315 {"evfsctui",    VX (4, 660),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2316 {"evfsctsi",    VX (4, 661),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2317 {"evfsctuf",    VX (4, 662),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2318 {"evfsctsf",    VX (4, 663),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2319 {"evfsctuiz",   VX (4, 664),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2320 {"put",         APU(4, 332,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
2321 {"evfsctsiz",   VX (4, 666),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2322 {"evfststgt",   VX (4, 668),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2323 {"evfststlt",   VX (4, 669),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2324 {"evfststeq",   VX (4, 670),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2325 {"cput",        APU(4, 348,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
2326 {"efsadd",      VX (4, 704),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2327 {"efssub",      VX (4, 705),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2328 {"efsabs",      VX (4, 708),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA}},
2329 {"vsr",         VX (4, 708),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2330 {"efsnabs",     VX (4, 709),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA}},
2331 {"efsneg",      VX (4, 710),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA}},
2332 {"vcmpgtfp",    VXR(4, 710,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2333 {"efsmul",      VX (4, 712),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2334 {"efsdiv",      VX (4, 713),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2335 {"vrfim",       VX (4, 714),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2336 {"efscmpgt",    VX (4, 716),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2337 {"efscmplt",    VX (4, 717),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2338 {"efscmpeq",    VX (4, 718),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2339 {"vupklsh",     VX (4, 718),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2340 {"efscfd",      VX (4, 719),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2341 {"efscfui",     VX (4, 720),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2342 {"efscfsi",     VX (4, 721),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2343 {"efscfuf",     VX (4, 722),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2344 {"efscfsf",     VX (4, 723),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2345 {"efsctui",     VX (4, 724),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2346 {"efsctsi",     VX (4, 725),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2347 {"efsctuf",     VX (4, 726),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2348 {"efsctsf",     VX (4, 727),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2349 {"efsctuiz",    VX (4, 728),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2350 {"nput",        APU(4, 364,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
2351 {"efsctsiz",    VX (4, 730),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2352 {"efststgt",    VX (4, 732),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2353 {"efststlt",    VX (4, 733),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2354 {"efststeq",    VX (4, 734),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2355 {"efdadd",      VX (4, 736),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2356 {"efdsub",      VX (4, 737),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2357 {"efdcfuid",    VX (4, 738),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2358 {"efdcfsid",    VX (4, 739),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2359 {"efdabs",      VX (4, 740),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA}},
2360 {"efdnabs",     VX (4, 741),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA}},
2361 {"efdneg",      VX (4, 742),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA}},
2362 {"efdmul",      VX (4, 744),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2363 {"efddiv",      VX (4, 745),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2364 {"efdctuidz",   VX (4, 746),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2365 {"efdctsidz",   VX (4, 747),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2366 {"efdcmpgt",    VX (4, 748),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2367 {"efdcmplt",    VX (4, 749),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2368 {"efdcmpeq",    VX (4, 750),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2369 {"efdcfs",      VX (4, 751),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2370 {"efdcfui",     VX (4, 752),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2371 {"efdcfsi",     VX (4, 753),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2372 {"efdcfuf",     VX (4, 754),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2373 {"efdcfsf",     VX (4, 755),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2374 {"efdctui",     VX (4, 756),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2375 {"efdctsi",     VX (4, 757),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2376 {"efdctuf",     VX (4, 758),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2377 {"efdctsf",     VX (4, 759),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2378 {"efdctuiz",    VX (4, 760),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2379 {"ncput",       APU(4, 380,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
2380 {"efdctsiz",    VX (4, 762),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2381 {"efdtstgt",    VX (4, 764),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2382 {"efdtstlt",    VX (4, 765),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2383 {"efdtsteq",    VX (4, 766),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2384 {"evlddx",      VX (4, 768),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2385 {"vaddsbs",     VX (4, 768),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2386 {"evldd",       VX (4, 769),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_8, RA}},
2387 {"evldwx",      VX (4, 770),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2388 {"vminsb",      VX (4, 770),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2389 {"evldw",       VX (4, 771),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_8, RA}},
2390 {"evldhx",      VX (4, 772),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2391 {"vsrab",       VX (4, 772),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2392 {"evldh",       VX (4, 773),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_8, RA}},
2393 {"vcmpgtsb",    VXR(4, 774,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2394 {"evlhhesplatx",VX (4, 776),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2395 {"vmulesb",     VX (4, 776),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2396 {"evlhhesplat", VX (4, 777),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_2, RA}},
2397 {"vcfux",       VX (4, 778),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB, UIMM}},
2398 {"evlhhousplatx",VX(4, 780),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2399 {"vspltisb",    VX (4, 780),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, SIMM}},
2400 {"evlhhousplat",VX (4, 781),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_2, RA}},
2401 {"evlhhossplatx",VX(4, 782),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2402 {"vpkpx",       VX (4, 782),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2403 {"evlhhossplat",VX (4, 783),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_2, RA}},
2404 {"mullhwu",     XRC(4, 392,0),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2405 {"evlwhex",     VX (4, 784),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2406 {"mullhwu.",    XRC(4, 392,1),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2407 {"evlwhe",      VX (4, 785),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2408 {"evlwhoux",    VX (4, 788),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2409 {"evlwhou",     VX (4, 789),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2410 {"evlwhosx",    VX (4, 790),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2411 {"evlwhos",     VX (4, 791),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2412 {"maclhwu",     XO (4, 396,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2413 {"evlwwsplatx", VX (4, 792),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2414 {"maclhwu.",    XO (4, 396,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2415 {"evlwwsplat",  VX (4, 793),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2416 {"evlwhsplatx", VX (4, 796),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2417 {"evlwhsplat",  VX (4, 797),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2418 {"evstddx",     VX (4, 800),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2419 {"evstdd",      VX (4, 801),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_8, RA}},
2420 {"evstdwx",     VX (4, 802),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2421 {"evstdw",      VX (4, 803),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_8, RA}},
2422 {"evstdhx",     VX (4, 804),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2423 {"evstdh",      VX (4, 805),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_8, RA}},
2424 {"evstwhex",    VX (4, 816),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2425 {"evstwhe",     VX (4, 817),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2426 {"evstwhox",    VX (4, 820),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2427 {"evstwho",     VX (4, 821),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2428 {"evstwwex",    VX (4, 824),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2429 {"evstwwe",     VX (4, 825),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2430 {"evstwwox",    VX (4, 828),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2431 {"evstwwo",     VX (4, 829),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2432 {"vaddshs",     VX (4, 832),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2433 {"vminsh",      VX (4, 834),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2434 {"vsrah",       VX (4, 836),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2435 {"vcmpgtsh",    VXR(4, 838,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2436 {"vmulesh",     VX (4, 840),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2437 {"vcfsx",       VX (4, 842),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB, UIMM}},
2438 {"vspltish",    VX (4, 844),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, SIMM}},
2439 {"vupkhpx",     VX (4, 846),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2440 {"mullhw",      XRC(4, 424,0),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2441 {"mullhw.",     XRC(4, 424,1),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2442 {"maclhw",      XO (4, 428,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2443 {"maclhw.",     XO (4, 428,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2444 {"nmaclhw",     XO (4, 430,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2445 {"nmaclhw.",    XO (4, 430,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2446 {"vaddsws",     VX (4, 896),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2447 {"vminsw",      VX (4, 898),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2448 {"vsraw",       VX (4, 900),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2449 {"vcmpgtsw",    VXR(4, 902,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2450 {"vctuxs",      VX (4, 906),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB, UIMM}},
2451 {"vspltisw",    VX (4, 908),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, SIMM}},
2452 {"maclhwsu",    XO (4, 460,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2453 {"maclhwsu.",   XO (4, 460,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2454 {"vcmpbfp",     VXR(4, 966,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2455 {"vctsxs",      VX (4, 970),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB, UIMM}},
2456 {"vupklpx",     VX (4, 974),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2457 {"maclhws",     XO (4, 492,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2458 {"maclhws.",    XO (4, 492,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2459 {"nmaclhws",    XO (4, 494,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2460 {"nmaclhws.",   XO (4, 494,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2461 {"vsububm",     VX (4,1024),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2462 {"vavgub",      VX (4,1026),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2463 {"evmhessf",    VX (4,1027),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2464 {"vand",        VX (4,1028),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2465 {"vcmpequb.",   VXR(4,   6,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2466 {"udi0fcm.",    APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2467 {"udi0fcm",     APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2468 {"evmhossf",    VX (4,1031),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2469 {"evmheumi",    VX (4,1032),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2470 {"evmhesmi",    VX (4,1033),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2471 {"vmaxfp",      VX (4,1034),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2472 {"evmhesmf",    VX (4,1035),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2473 {"evmhoumi",    VX (4,1036),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2474 {"vslo",        VX (4,1036),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2475 {"evmhosmi",    VX (4,1037),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2476 {"evmhosmf",    VX (4,1039),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2477 {"machhwuo",    XO (4,  12,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2478 {"machhwuo.",   XO (4,  12,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2479 {"ps_merge00",  XOPS(4,528,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2480 {"ps_merge00.", XOPS(4,528,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2481 {"evmhessfa",   VX (4,1059),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2482 {"evmhossfa",   VX (4,1063),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2483 {"evmheumia",   VX (4,1064),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2484 {"evmhesmia",   VX (4,1065),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2485 {"evmhesmfa",   VX (4,1067),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2486 {"evmhoumia",   VX (4,1068),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2487 {"evmhosmia",   VX (4,1069),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2488 {"evmhosmfa",   VX (4,1071),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2489 {"vsubuhm",     VX (4,1088),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2490 {"vavguh",      VX (4,1090),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2491 {"vandc",       VX (4,1092),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2492 {"vcmpequh.",   VXR(4,  70,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2493 {"udi1fcm.",    APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2494 {"udi1fcm",     APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2495 {"evmwhssf",    VX (4,1095),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2496 {"evmwlumi",    VX (4,1096),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2497 {"vminfp",      VX (4,1098),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2498 {"evmwhumi",    VX (4,1100),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2499 {"vsro",        VX (4,1100),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2500 {"evmwhsmi",    VX (4,1101),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2501 {"evmwhsmf",    VX (4,1103),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2502 {"evmwssf",     VX (4,1107),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2503 {"machhwo",     XO (4,  44,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2504 {"evmwumi",     VX (4,1112),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2505 {"machhwo.",    XO (4,  44,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2506 {"evmwsmi",     VX (4,1113),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2507 {"evmwsmf",     VX (4,1115),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2508 {"nmachhwo",    XO (4,  46,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2509 {"nmachhwo.",   XO (4,  46,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2510 {"ps_merge01",  XOPS(4,560,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2511 {"ps_merge01.", XOPS(4,560,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2512 {"evmwhssfa",   VX (4,1127),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2513 {"evmwlumia",   VX (4,1128),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2514 {"evmwhumia",   VX (4,1132),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2515 {"evmwhsmia",   VX (4,1133),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2516 {"evmwhsmfa",   VX (4,1135),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2517 {"evmwssfa",    VX (4,1139),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2518 {"evmwumia",    VX (4,1144),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2519 {"evmwsmia",    VX (4,1145),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2520 {"evmwsmfa",    VX (4,1147),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2521 {"vsubuwm",     VX (4,1152),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2522 {"vavguw",      VX (4,1154),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2523 {"vor",         VX (4,1156),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2524 {"vcmpequw.",   VXR(4, 134,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2525 {"udi2fcm.",    APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2526 {"udi2fcm",     APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2527 {"machhwsuo",   XO (4,  76,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2528 {"machhwsuo.",  XO (4,  76,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2529 {"ps_merge10",  XOPS(4,592,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2530 {"ps_merge10.", XOPS(4,592,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2531 {"evaddusiaaw", VX (4,1216),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2532 {"evaddssiaaw", VX (4,1217),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2533 {"evsubfusiaaw",VX (4,1218),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2534 {"evsubfssiaaw",VX (4,1219),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2535 {"evmra",       VX (4,1220),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2536 {"vxor",        VX (4,1220),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2537 {"evdivws",     VX (4,1222),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2538 {"vcmpeqfp.",   VXR(4, 198,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2539 {"udi3fcm.",    APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2540 {"udi3fcm",     APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2541 {"evdivwu",     VX (4,1223),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2542 {"evaddumiaaw", VX (4,1224),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2543 {"evaddsmiaaw", VX (4,1225),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2544 {"evsubfumiaaw",VX (4,1226),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2545 {"evsubfsmiaaw",VX (4,1227),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2546 {"machhwso",    XO (4, 108,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2547 {"machhwso.",   XO (4, 108,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2548 {"nmachhwso",   XO (4, 110,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2549 {"nmachhwso.",  XO (4, 110,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2550 {"ps_merge11",  XOPS(4,624,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2551 {"ps_merge11.", XOPS(4,624,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2552 {"evmheusiaaw", VX (4,1280),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2553 {"evmhessiaaw", VX (4,1281),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2554 {"vavgsb",      VX (4,1282),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2555 {"evmhessfaaw", VX (4,1283),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2556 {"evmhousiaaw", VX (4,1284),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2557 {"vnor",        VX (4,1284),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2558 {"evmhossiaaw", VX (4,1285),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2559 {"udi4fcm.",    APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2560 {"udi4fcm",     APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2561 {"evmhossfaaw", VX (4,1287),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2562 {"evmheumiaaw", VX (4,1288),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2563 {"evmhesmiaaw", VX (4,1289),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2564 {"evmhesmfaaw", VX (4,1291),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2565 {"evmhoumiaaw", VX (4,1292),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2566 {"evmhosmiaaw", VX (4,1293),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2567 {"evmhosmfaaw", VX (4,1295),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2568 {"macchwuo",    XO (4, 140,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2569 {"macchwuo.",   XO (4, 140,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2570 {"evmhegumiaa", VX (4,1320),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2571 {"evmhegsmiaa", VX (4,1321),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2572 {"evmhegsmfaa", VX (4,1323),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2573 {"evmhogumiaa", VX (4,1324),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2574 {"evmhogsmiaa", VX (4,1325),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2575 {"evmhogsmfaa", VX (4,1327),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2576 {"evmwlusiaaw", VX (4,1344),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2577 {"evmwlssiaaw", VX (4,1345),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2578 {"vavgsh",      VX (4,1346),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2579 {"udi5fcm.",    APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2580 {"udi5fcm",     APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2581 {"evmwlumiaaw", VX (4,1352),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2582 {"evmwlsmiaaw", VX (4,1353),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2583 {"evmwssfaa",   VX (4,1363),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2584 {"macchwo",     XO (4, 172,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2585 {"evmwumiaa",   VX (4,1368),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2586 {"macchwo.",    XO (4, 172,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2587 {"evmwsmiaa",   VX (4,1369),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2588 {"evmwsmfaa",   VX (4,1371),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2589 {"nmacchwo",    XO (4, 174,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2590 {"nmacchwo.",   XO (4, 174,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2591 {"evmheusianw", VX (4,1408),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2592 {"vsubcuw",     VX (4,1408),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2593 {"evmhessianw", VX (4,1409),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2594 {"vavgsw",      VX (4,1410),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2595 {"evmhessfanw", VX (4,1411),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2596 {"evmhousianw", VX (4,1412),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2597 {"evmhossianw", VX (4,1413),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2598 {"udi6fcm.",    APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2599 {"udi6fcm",     APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2600 {"evmhossfanw", VX (4,1415),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2601 {"evmheumianw", VX (4,1416),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2602 {"evmhesmianw", VX (4,1417),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2603 {"evmhesmfanw", VX (4,1419),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2604 {"evmhoumianw", VX (4,1420),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2605 {"evmhosmianw", VX (4,1421),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2606 {"evmhosmfanw", VX (4,1423),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2607 {"macchwsuo",   XO (4, 204,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2608 {"macchwsuo.",  XO (4, 204,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2609 {"evmhegumian", VX (4,1448),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2610 {"evmhegsmian", VX (4,1449),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2611 {"evmhegsmfan", VX (4,1451),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2612 {"evmhogumian", VX (4,1452),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2613 {"evmhogsmian", VX (4,1453),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2614 {"evmhogsmfan", VX (4,1455),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2615 {"evmwlusianw", VX (4,1472),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2616 {"evmwlssianw", VX (4,1473),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2617 {"vcmpgefp.",   VXR(4, 454,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2618 {"udi7fcm.",    APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2619 {"udi7fcm",     APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2620 {"evmwlumianw", VX (4,1480),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2621 {"evmwlsmianw", VX (4,1481),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2622 {"evmwssfan",   VX (4,1491),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2623 {"macchwso",    XO (4, 236,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2624 {"evmwumian",   VX (4,1496),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2625 {"macchwso.",   XO (4, 236,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2626 {"evmwsmian",   VX (4,1497),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2627 {"evmwsmfan",   VX (4,1499),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2628 {"nmacchwso",   XO (4, 238,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2629 {"nmacchwso.",  XO (4, 238,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2630 {"vsububs",     VX (4,1536),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2631 {"mfvscr",      VX (4,1540),    VX_MASK,     PPCVEC,    PPCNONE,        {VD}},
2632 {"vcmpgtub.",   VXR(4, 518,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2633 {"udi8fcm.",    APU(4, 771,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2634 {"udi8fcm",     APU(4, 771,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2635 {"vsum4ubs",    VX (4,1544),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2636 {"vsubuhs",     VX (4,1600),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2637 {"mtvscr",      VX (4,1604),    VX_MASK,     PPCVEC,    PPCNONE,        {VB}},
2638 {"vcmpgtuh.",   VXR(4, 582,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2639 {"vsum4shs",    VX (4,1608),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2640 {"udi9fcm.",    APU(4, 804,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2641 {"udi9fcm",     APU(4, 804,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2642 {"vsubuws",     VX (4,1664),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2643 {"vcmpgtuw.",   VXR(4, 646,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2644 {"udi10fcm.",   APU(4, 835,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2645 {"udi10fcm",    APU(4, 835,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2646 {"vsum2sws",    VX (4,1672),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2647 {"vcmpgtfp.",   VXR(4, 710,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2648 {"udi11fcm.",   APU(4, 867,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2649 {"udi11fcm",    APU(4, 867,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2650 {"vsubsbs",     VX (4,1792),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2651 {"vcmpgtsb.",   VXR(4, 774,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2652 {"udi12fcm.",   APU(4, 899,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2653 {"udi12fcm",    APU(4, 899,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2654 {"vsum4sbs",    VX (4,1800),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2655 {"maclhwuo",    XO (4, 396,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2656 {"maclhwuo.",   XO (4, 396,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2657 {"vsubshs",     VX (4,1856),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2658 {"vcmpgtsh.",   VXR(4, 838,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2659 {"udi13fcm.",   APU(4, 931,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2660 {"udi13fcm",    APU(4, 931,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2661 {"maclhwo",     XO (4, 428,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2662 {"maclhwo.",    XO (4, 428,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2663 {"nmaclhwo",    XO (4, 430,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2664 {"nmaclhwo.",   XO (4, 430,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2665 {"vsubsws",     VX (4,1920),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2666 {"vcmpgtsw.",   VXR(4, 902,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2667 {"udi14fcm.",   APU(4, 963,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2668 {"udi14fcm",    APU(4, 963,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2669 {"vsumsws",     VX (4,1928),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2670 {"maclhwsuo",   XO (4, 460,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2671 {"maclhwsuo.",  XO (4, 460,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2672 {"vcmpbfp.",    VXR(4, 966,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2673 {"udi15fcm.",   APU(4, 995,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2674 {"udi15fcm",    APU(4, 995,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2675 {"maclhwso",    XO (4, 492,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2676 {"maclhwso.",   XO (4, 492,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2677 {"nmaclhwso",   XO (4, 494,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2678 {"nmaclhwso.",  XO (4, 494,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2679 {"dcbz_l",      X  (4,1014),    XRT_MASK,    PPCPS,     PPCNONE,        {RA, RB}},
2680
2681 {"mulli",       OP(7),          OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
2682 {"muli",        OP(7),          OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
2683
2684 {"subfic",      OP(8),          OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
2685 {"sfi",         OP(8),          OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
2686
2687 {"dozi",        OP(9),          OP_MASK,     M601,      PPCNONE,        {RT, RA, SI}},
2688
2689 {"cmplwi",      OPL(10,0),      OPL_MASK,    PPCCOM,    PPCNONE,        {OBF, RA, UI}},
2690 {"cmpldi",      OPL(10,1),      OPL_MASK,    PPC64,     PPCNONE,        {OBF, RA, UI}},
2691 {"cmpli",       OP(10),         OP_MASK,     PPC,       PPCNONE,        {BF, L, RA, UI}},
2692 {"cmpli",       OP(10),         OP_MASK,     PWRCOM,    PPC,            {BF, RA, UI}},
2693
2694 {"cmpwi",       OPL(11,0),      OPL_MASK,    PPCCOM,    PPCNONE,        {OBF, RA, SI}},
2695 {"cmpdi",       OPL(11,1),      OPL_MASK,    PPC64,     PPCNONE,        {OBF, RA, SI}},
2696 {"cmpi",        OP(11),         OP_MASK,     PPC,       PPCNONE,        {BF, L, RA, SI}},
2697 {"cmpi",        OP(11),         OP_MASK,     PWRCOM,    PPC,            {BF, RA, SI}},
2698
2699 {"addic",       OP(12),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
2700 {"ai",          OP(12),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
2701 {"subic",       OP(12),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, NSI}},
2702
2703 {"addic.",      OP(13),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
2704 {"ai.",         OP(13),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
2705 {"subic.",      OP(13),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, NSI}},
2706
2707 {"li",          OP(14),         DRA_MASK,    PPCCOM,    PPCNONE,        {RT, SI}},
2708 {"lil",         OP(14),         DRA_MASK,    PWRCOM,    PPCNONE,        {RT, SI}},
2709 {"addi",        OP(14),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, SI}},
2710 {"cal",         OP(14),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
2711 {"subi",        OP(14),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, NSI}},
2712 {"la",          OP(14),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RA0}},
2713
2714 {"lis",         OP(15),         DRA_MASK,    PPCCOM,    PPCNONE,        {RT, SISIGNOPT}},
2715 {"liu",         OP(15),         DRA_MASK,    PWRCOM,    PPCNONE,        {RT, SISIGNOPT}},
2716 {"addis",       OP(15),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, SISIGNOPT}},
2717 {"cau",         OP(15),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA0, SISIGNOPT}},
2718 {"subis",       OP(15),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, NSI}},
2719
2720 {"bdnz-",    BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
2721 {"bdnz+",    BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
2722 {"bdnz",     BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BD}},
2723 {"bdn",      BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BD}},
2724 {"bdnzl-",   BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
2725 {"bdnzl+",   BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
2726 {"bdnzl",    BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BD}},
2727 {"bdnl",     BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BD}},
2728 {"bdnza-",   BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
2729 {"bdnza+",   BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
2730 {"bdnza",    BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDA}},
2731 {"bdna",     BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BDA}},
2732 {"bdnzla-",  BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
2733 {"bdnzla+",  BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
2734 {"bdnzla",   BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDA}},
2735 {"bdnla",    BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BDA}},
2736 {"bdz-",     BBO(16,BODZ,0,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
2737 {"bdz+",     BBO(16,BODZ,0,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
2738 {"bdz",      BBO(16,BODZ,0,0),          BBOATBI_MASK,  COM,      PPCNONE,       {BD}},
2739 {"bdzl-",    BBO(16,BODZ,0,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
2740 {"bdzl+",    BBO(16,BODZ,0,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
2741 {"bdzl",     BBO(16,BODZ,0,1),          BBOATBI_MASK,  COM,      PPCNONE,       {BD}},
2742 {"bdza-",    BBO(16,BODZ,1,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
2743 {"bdza+",    BBO(16,BODZ,1,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
2744 {"bdza",     BBO(16,BODZ,1,0),          BBOATBI_MASK,  COM,      PPCNONE,       {BDA}},
2745 {"bdzla-",   BBO(16,BODZ,1,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
2746 {"bdzla+",   BBO(16,BODZ,1,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
2747 {"bdzla",    BBO(16,BODZ,1,1),          BBOATBI_MASK,  COM,      PPCNONE,       {BDA}},
2748
2749 {"bge-",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2750 {"bge+",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2751 {"bge",      BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2752 {"bnl-",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2753 {"bnl+",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2754 {"bnl",      BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2755 {"bgel-",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2756 {"bgel+",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2757 {"bgel",     BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2758 {"bnll-",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2759 {"bnll+",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2760 {"bnll",     BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2761 {"bgea-",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2762 {"bgea+",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2763 {"bgea",     BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2764 {"bnla-",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2765 {"bnla+",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2766 {"bnla",     BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2767 {"bgela-",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2768 {"bgela+",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2769 {"bgela",    BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2770 {"bnlla-",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2771 {"bnlla+",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2772 {"bnlla",    BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2773 {"ble-",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2774 {"ble+",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2775 {"ble",      BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2776 {"bng-",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2777 {"bng+",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2778 {"bng",      BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2779 {"blel-",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2780 {"blel+",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2781 {"blel",     BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2782 {"bngl-",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2783 {"bngl+",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2784 {"bngl",     BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2785 {"blea-",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2786 {"blea+",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2787 {"blea",     BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2788 {"bnga-",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2789 {"bnga+",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2790 {"bnga",     BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2791 {"blela-",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2792 {"blela+",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2793 {"blela",    BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2794 {"bngla-",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2795 {"bngla+",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2796 {"bngla",    BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2797 {"bne-",     BBOCB(16,BOF,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2798 {"bne+",     BBOCB(16,BOF,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2799 {"bne",      BBOCB(16,BOF,CBEQ,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2800 {"bnel-",    BBOCB(16,BOF,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2801 {"bnel+",    BBOCB(16,BOF,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2802 {"bnel",     BBOCB(16,BOF,CBEQ,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2803 {"bnea-",    BBOCB(16,BOF,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2804 {"bnea+",    BBOCB(16,BOF,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2805 {"bnea",     BBOCB(16,BOF,CBEQ,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2806 {"bnela-",   BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2807 {"bnela+",   BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2808 {"bnela",    BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2809 {"bns-",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2810 {"bns+",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2811 {"bns",      BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2812 {"bnu-",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2813 {"bnu+",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2814 {"bnu",      BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
2815 {"bnsl-",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2816 {"bnsl+",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2817 {"bnsl",     BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2818 {"bnul-",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2819 {"bnul+",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2820 {"bnul",     BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
2821 {"bnsa-",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2822 {"bnsa+",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2823 {"bnsa",     BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2824 {"bnua-",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2825 {"bnua+",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2826 {"bnua",     BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
2827 {"bnsla-",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2828 {"bnsla+",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2829 {"bnsla",    BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2830 {"bnula-",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2831 {"bnula+",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2832 {"bnula",    BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
2833
2834 {"blt-",     BBOCB(16,BOT,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2835 {"blt+",     BBOCB(16,BOT,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2836 {"blt",      BBOCB(16,BOT,CBLT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2837 {"bltl-",    BBOCB(16,BOT,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2838 {"bltl+",    BBOCB(16,BOT,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2839 {"bltl",     BBOCB(16,BOT,CBLT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2840 {"blta-",    BBOCB(16,BOT,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2841 {"blta+",    BBOCB(16,BOT,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2842 {"blta",     BBOCB(16,BOT,CBLT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2843 {"bltla-",   BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2844 {"bltla+",   BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2845 {"bltla",    BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2846 {"bgt-",     BBOCB(16,BOT,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2847 {"bgt+",     BBOCB(16,BOT,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2848 {"bgt",      BBOCB(16,BOT,CBGT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2849 {"bgtl-",    BBOCB(16,BOT,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2850 {"bgtl+",    BBOCB(16,BOT,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2851 {"bgtl",     BBOCB(16,BOT,CBGT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2852 {"bgta-",    BBOCB(16,BOT,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2853 {"bgta+",    BBOCB(16,BOT,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2854 {"bgta",     BBOCB(16,BOT,CBGT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2855 {"bgtla-",   BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2856 {"bgtla+",   BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2857 {"bgtla",    BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2858 {"beq-",     BBOCB(16,BOT,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2859 {"beq+",     BBOCB(16,BOT,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2860 {"beq",      BBOCB(16,BOT,CBEQ,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2861 {"beql-",    BBOCB(16,BOT,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2862 {"beql+",    BBOCB(16,BOT,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2863 {"beql",     BBOCB(16,BOT,CBEQ,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2864 {"beqa-",    BBOCB(16,BOT,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2865 {"beqa+",    BBOCB(16,BOT,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2866 {"beqa",     BBOCB(16,BOT,CBEQ,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2867 {"beqla-",   BBOCB(16,BOT,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2868 {"beqla+",   BBOCB(16,BOT,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2869 {"beqla",    BBOCB(16,BOT,CBEQ,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2870 {"bso-",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2871 {"bso+",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2872 {"bso",      BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2873 {"bun-",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2874 {"bun+",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2875 {"bun",      BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
2876 {"bsol-",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2877 {"bsol+",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2878 {"bsol",     BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2879 {"bunl-",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2880 {"bunl+",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2881 {"bunl",     BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
2882 {"bsoa-",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2883 {"bsoa+",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2884 {"bsoa",     BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2885 {"buna-",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2886 {"buna+",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2887 {"buna",     BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
2888 {"bsola-",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2889 {"bsola+",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2890 {"bsola",    BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2891 {"bunla-",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2892 {"bunla+",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2893 {"bunla",    BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
2894
2895 {"bdnzf-",   BBO(16,BODNZF,0,0),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2896 {"bdnzf+",   BBO(16,BODNZF,0,0),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2897 {"bdnzf",    BBO(16,BODNZF,0,0),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2898 {"bdnzfl-",  BBO(16,BODNZF,0,1),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2899 {"bdnzfl+",  BBO(16,BODNZF,0,1),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2900 {"bdnzfl",   BBO(16,BODNZF,0,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2901 {"bdnzfa-",  BBO(16,BODNZF,1,0),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2902 {"bdnzfa+",  BBO(16,BODNZF,1,0),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2903 {"bdnzfa",   BBO(16,BODNZF,1,0),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2904 {"bdnzfla-", BBO(16,BODNZF,1,1),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2905 {"bdnzfla+", BBO(16,BODNZF,1,1),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2906 {"bdnzfla",  BBO(16,BODNZF,1,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2907 {"bdzf-",    BBO(16,BODZF,0,0),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2908 {"bdzf+",    BBO(16,BODZF,0,0),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2909 {"bdzf",     BBO(16,BODZF,0,0),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2910 {"bdzfl-",   BBO(16,BODZF,0,1),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2911 {"bdzfl+",   BBO(16,BODZF,0,1),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2912 {"bdzfl",    BBO(16,BODZF,0,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2913 {"bdzfa-",   BBO(16,BODZF,1,0),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2914 {"bdzfa+",   BBO(16,BODZF,1,0),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2915 {"bdzfa",    BBO(16,BODZF,1,0),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2916 {"bdzfla-",  BBO(16,BODZF,1,1),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2917 {"bdzfla+",  BBO(16,BODZF,1,1),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2918 {"bdzfla",   BBO(16,BODZF,1,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2919
2920 {"bf-",      BBO(16,BOF,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
2921 {"bf+",      BBO(16,BOF,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
2922 {"bf",       BBO(16,BOF,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
2923 {"bbf",      BBO(16,BOF,0,0),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
2924 {"bfl-",     BBO(16,BOF,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
2925 {"bfl+",     BBO(16,BOF,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
2926 {"bfl",      BBO(16,BOF,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
2927 {"bbfl",     BBO(16,BOF,0,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
2928 {"bfa-",     BBO(16,BOF,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
2929 {"bfa+",     BBO(16,BOF,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
2930 {"bfa",      BBO(16,BOF,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
2931 {"bbfa",     BBO(16,BOF,1,0),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
2932 {"bfla-",    BBO(16,BOF,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
2933 {"bfla+",    BBO(16,BOF,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
2934 {"bfla",     BBO(16,BOF,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
2935 {"bbfla",    BBO(16,BOF,1,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
2936
2937 {"bdnzt-",   BBO(16,BODNZT,0,0),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2938 {"bdnzt+",   BBO(16,BODNZT,0,0),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2939 {"bdnzt",    BBO(16,BODNZT,0,0),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2940 {"bdnztl-",  BBO(16,BODNZT,0,1),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2941 {"bdnztl+",  BBO(16,BODNZT,0,1),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2942 {"bdnztl",   BBO(16,BODNZT,0,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2943 {"bdnzta-",  BBO(16,BODNZT,1,0),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2944 {"bdnzta+",  BBO(16,BODNZT,1,0),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2945 {"bdnzta",   BBO(16,BODNZT,1,0),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2946 {"bdnztla-", BBO(16,BODNZT,1,1),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2947 {"bdnztla+", BBO(16,BODNZT,1,1),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2948 {"bdnztla",  BBO(16,BODNZT,1,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2949 {"bdzt-",    BBO(16,BODZT,0,0),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2950 {"bdzt+",    BBO(16,BODZT,0,0),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2951 {"bdzt",     BBO(16,BODZT,0,0),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2952 {"bdztl-",   BBO(16,BODZT,0,1),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2953 {"bdztl+",   BBO(16,BODZT,0,1),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2954 {"bdztl",    BBO(16,BODZT,0,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2955 {"bdzta-",   BBO(16,BODZT,1,0),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2956 {"bdzta+",   BBO(16,BODZT,1,0),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2957 {"bdzta",    BBO(16,BODZT,1,0),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2958 {"bdztla-",  BBO(16,BODZT,1,1),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2959 {"bdztla+",  BBO(16,BODZT,1,1),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2960 {"bdztla",   BBO(16,BODZT,1,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2961
2962 {"bt-",      BBO(16,BOT,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
2963 {"bt+",      BBO(16,BOT,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
2964 {"bt",       BBO(16,BOT,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
2965 {"bbt",      BBO(16,BOT,0,0),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
2966 {"btl-",     BBO(16,BOT,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
2967 {"btl+",     BBO(16,BOT,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
2968 {"btl",      BBO(16,BOT,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
2969 {"bbtl",     BBO(16,BOT,0,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
2970 {"bta-",     BBO(16,BOT,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
2971 {"bta+",     BBO(16,BOT,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
2972 {"bta",      BBO(16,BOT,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
2973 {"bbta",     BBO(16,BOT,1,0),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
2974 {"btla-",    BBO(16,BOT,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
2975 {"btla+",    BBO(16,BOT,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
2976 {"btla",     BBO(16,BOT,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
2977 {"bbtla",    BBO(16,BOT,1,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
2978
2979 {"bc-",         B(16,0,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDM}},
2980 {"bc+",         B(16,0,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDP}},
2981 {"bc",          B(16,0,0),      B_MASK,      COM,       PPCNONE,        {BO, BI, BD}},
2982 {"bcl-",        B(16,0,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDM}},
2983 {"bcl+",        B(16,0,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDP}},
2984 {"bcl",         B(16,0,1),      B_MASK,      COM,       PPCNONE,        {BO, BI, BD}},
2985 {"bca-",        B(16,1,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDMA}},
2986 {"bca+",        B(16,1,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDPA}},
2987 {"bca",         B(16,1,0),      B_MASK,      COM,       PPCNONE,        {BO, BI, BDA}},
2988 {"bcla-",       B(16,1,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDMA}},
2989 {"bcla+",       B(16,1,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDPA}},
2990 {"bcla",        B(16,1,1),      B_MASK,      COM,       PPCNONE,        {BO, BI, BDA}},
2991
2992 {"svc",         SC(17,0,0),     SC_MASK,     POWER,     PPCNONE,        {SVC_LEV, FL1, FL2}},
2993 {"svcl",        SC(17,0,1),     SC_MASK,     POWER,     PPCNONE,        {SVC_LEV, FL1, FL2}},
2994 {"sc",          SC(17,1,0),     SC_MASK,     PPC,       PPCNONE,        {LEV}},
2995 {"svca",        SC(17,1,0),     SC_MASK,     PWRCOM,    PPCNONE,        {SV}},
2996 {"svcla",       SC(17,1,1),     SC_MASK,     POWER,     PPCNONE,        {SV}},
2997
2998 {"b",           B(18,0,0),      B_MASK,      COM,       PPCNONE,        {LI}},
2999 {"bl",          B(18,0,1),      B_MASK,      COM,       PPCNONE,        {LI}},
3000 {"ba",          B(18,1,0),      B_MASK,      COM,       PPCNONE,        {LIA}},
3001 {"bla",         B(18,1,1),      B_MASK,      COM,       PPCNONE,        {LIA}},
3002
3003 {"mcrf",      XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCNONE,        {BF, BFA}},
3004
3005 {"bdnzlr",   XLO(19,BODNZ,16,0),        XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
3006 {"bdnzlr-",  XLO(19,BODNZ,16,0),        XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
3007 {"bdnzlrl",  XLO(19,BODNZ,16,1),        XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
3008 {"bdnzlrl-", XLO(19,BODNZ,16,1),        XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
3009 {"bdnzlr+",  XLO(19,BODNZP,16,0),       XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
3010 {"bdnzlrl+", XLO(19,BODNZP,16,1),       XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
3011 {"bdzlr",    XLO(19,BODZ,16,0),         XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
3012 {"bdzlr-",   XLO(19,BODZ,16,0),         XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
3013 {"bdzlrl",   XLO(19,BODZ,16,1),         XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
3014 {"bdzlrl-",  XLO(19,BODZ,16,1),         XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
3015 {"bdzlr+",   XLO(19,BODZP,16,0),        XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
3016 {"bdzlrl+",  XLO(19,BODZP,16,1),        XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
3017 {"blr",      XLO(19,BOU,16,0),          XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
3018 {"br",       XLO(19,BOU,16,0),          XLBOBIBB_MASK, PWRCOM,   PPCNONE,       {0}},
3019 {"blrl",     XLO(19,BOU,16,1),          XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
3020 {"brl",      XLO(19,BOU,16,1),          XLBOBIBB_MASK, PWRCOM,   PPCNONE,       {0}},
3021 {"bdnzlr-",  XLO(19,BODNZM4,16,0),      XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
3022 {"bdnzlrl-", XLO(19,BODNZM4,16,1),      XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
3023 {"bdnzlr+",  XLO(19,BODNZP4,16,0),      XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
3024 {"bdnzlrl+", XLO(19,BODNZP4,16,1),      XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
3025 {"bdzlr-",   XLO(19,BODZM4,16,0),       XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
3026 {"bdzlrl-",  XLO(19,BODZM4,16,1),       XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
3027 {"bdzlr+",   XLO(19,BODZP4,16,0),       XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
3028 {"bdzlrl+",  XLO(19,BODZP4,16,1),       XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
3029
3030 {"bgelr",    XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3031 {"bgelr-",   XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3032 {"bger",     XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3033 {"bnllr",    XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3034 {"bnllr-",   XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3035 {"bnlr",     XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3036 {"bgelrl",   XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3037 {"bgelrl-",  XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3038 {"bgerl",    XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3039 {"bnllrl",   XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3040 {"bnllrl-",  XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3041 {"bnlrl",    XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3042 {"blelr",    XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3043 {"blelr-",   XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3044 {"bler",     XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3045 {"bnglr",    XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3046 {"bnglr-",   XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3047 {"bngr",     XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3048 {"blelrl",   XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3049 {"blelrl-",  XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3050 {"blerl",    XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3051 {"bnglrl",   XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3052 {"bnglrl-",  XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3053 {"bngrl",    XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3054 {"bnelr",    XLOCB(19,BOF,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3055 {"bnelr-",   XLOCB(19,BOF,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3056 {"bner",     XLOCB(19,BOF,CBEQ,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3057 {"bnelrl",   XLOCB(19,BOF,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3058 {"bnelrl-",  XLOCB(19,BOF,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3059 {"bnerl",    XLOCB(19,BOF,CBEQ,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3060 {"bnslr",    XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3061 {"bnslr-",   XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3062 {"bnsr",     XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3063 {"bnulr",    XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3064 {"bnulr-",   XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3065 {"bnslrl",   XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3066 {"bnslrl-",  XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3067 {"bnsrl",    XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3068 {"bnulrl",   XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3069 {"bnulrl-",  XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3070 {"bgelr+",   XLOCB(19,BOFP,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3071 {"bnllr+",   XLOCB(19,BOFP,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3072 {"bgelrl+",  XLOCB(19,BOFP,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3073 {"bnllrl+",  XLOCB(19,BOFP,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3074 {"blelr+",   XLOCB(19,BOFP,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3075 {"bnglr+",   XLOCB(19,BOFP,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3076 {"blelrl+",  XLOCB(19,BOFP,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3077 {"bnglrl+",  XLOCB(19,BOFP,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3078 {"bnelr+",   XLOCB(19,BOFP,CBEQ,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3079 {"bnelrl+",  XLOCB(19,BOFP,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3080 {"bnslr+",   XLOCB(19,BOFP,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3081 {"bnulr+",   XLOCB(19,BOFP,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3082 {"bnslrl+",  XLOCB(19,BOFP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3083 {"bnulrl+",  XLOCB(19,BOFP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3084 {"bgelr-",   XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3085 {"bnllr-",   XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3086 {"bgelrl-",  XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3087 {"bnllrl-",  XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3088 {"blelr-",   XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3089 {"bnglr-",   XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3090 {"blelrl-",  XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3091 {"bnglrl-",  XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3092 {"bnelr-",   XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3093 {"bnelrl-",  XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3094 {"bnslr-",   XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3095 {"bnulr-",   XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3096 {"bnslrl-",  XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3097 {"bnulrl-",  XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3098 {"bgelr+",   XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3099 {"bnllr+",   XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3100 {"bgelrl+",  XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3101 {"bnllrl+",  XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3102 {"blelr+",   XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3103 {"bnglr+",   XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3104 {"blelrl+",  XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3105 {"bnglrl+",  XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3106 {"bnelr+",   XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3107 {"bnelrl+",  XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3108 {"bnslr+",   XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3109 {"bnulr+",   XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3110 {"bnslrl+",  XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3111 {"bnulrl+",  XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3112 {"bltlr",    XLOCB(19,BOT,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3113 {"bltlr-",   XLOCB(19,BOT,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3114 {"bltr",     XLOCB(19,BOT,CBLT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3115 {"bltlrl",   XLOCB(19,BOT,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3116 {"bltlrl-",  XLOCB(19,BOT,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3117 {"bltrl",    XLOCB(19,BOT,CBLT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3118 {"bgtlr",    XLOCB(19,BOT,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3119 {"bgtlr-",   XLOCB(19,BOT,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3120 {"bgtr",     XLOCB(19,BOT,CBGT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3121 {"bgtlrl",   XLOCB(19,BOT,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3122 {"bgtlrl-",  XLOCB(19,BOT,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3123 {"bgtrl",    XLOCB(19,BOT,CBGT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3124 {"beqlr",    XLOCB(19,BOT,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3125 {"beqlr-",   XLOCB(19,BOT,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3126 {"beqr",     XLOCB(19,BOT,CBEQ,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3127 {"beqlrl",   XLOCB(19,BOT,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3128 {"beqlrl-",  XLOCB(19,BOT,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3129 {"beqrl",    XLOCB(19,BOT,CBEQ,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3130 {"bsolr",    XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3131 {"bsolr-",   XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3132 {"bsor",     XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3133 {"bunlr",    XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3134 {"bunlr-",   XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3135 {"bsolrl",   XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3136 {"bsolrl-",  XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3137 {"bsorl",    XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3138 {"bunlrl",   XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3139 {"bunlrl-",  XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3140 {"bltlr+",   XLOCB(19,BOTP,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3141 {"bltlrl+",  XLOCB(19,BOTP,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3142 {"bgtlr+",   XLOCB(19,BOTP,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3143 {"bgtlrl+",  XLOCB(19,BOTP,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3144 {"beqlr+",   XLOCB(19,BOTP,CBEQ,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3145 {"beqlrl+",  XLOCB(19,BOTP,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3146 {"bsolr+",   XLOCB(19,BOTP,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3147 {"bunlr+",   XLOCB(19,BOTP,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3148 {"bsolrl+",  XLOCB(19,BOTP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3149 {"bunlrl+",  XLOCB(19,BOTP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3150 {"bltlr-",   XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3151 {"bltlrl-",  XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3152 {"bgtlr-",   XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3153 {"bgtlrl-",  XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3154 {"beqlr-",   XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3155 {"beqlrl-",  XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3156 {"bsolr-",   XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3157 {"bunlr-",   XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3158 {"bsolrl-",  XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3159 {"bunlrl-",  XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3160 {"bltlr+",   XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3161 {"bltlrl+",  XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3162 {"bgtlr+",   XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3163 {"bgtlrl+",  XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3164 {"beqlr+",   XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3165 {"beqlrl+",  XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3166 {"bsolr+",   XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3167 {"bunlr+",   XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3168 {"bsolrl+",  XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3169 {"bunlrl+",  XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3170
3171 {"bdnzflr",  XLO(19,BODNZF,16,0),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3172 {"bdnzflr-", XLO(19,BODNZF,16,0),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3173 {"bdnzflrl", XLO(19,BODNZF,16,1),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3174 {"bdnzflrl-",XLO(19,BODNZF,16,1),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3175 {"bdnzflr+", XLO(19,BODNZFP,16,0),      XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3176 {"bdnzflrl+",XLO(19,BODNZFP,16,1),      XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3177 {"bdzflr",   XLO(19,BODZF,16,0),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3178 {"bdzflr-",  XLO(19,BODZF,16,0),        XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3179 {"bdzflrl",  XLO(19,BODZF,16,1),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3180 {"bdzflrl-", XLO(19,BODZF,16,1),        XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3181 {"bdzflr+",  XLO(19,BODZFP,16,0),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3182 {"bdzflrl+", XLO(19,BODZFP,16,1),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3183 {"bflr",     XLO(19,BOF,16,0),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3184 {"bflr-",    XLO(19,BOF,16,0),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3185 {"bbfr",     XLO(19,BOF,16,0),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
3186 {"bflrl",    XLO(19,BOF,16,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3187 {"bflrl-",   XLO(19,BOF,16,1),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3188 {"bbfrl",    XLO(19,BOF,16,1),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
3189 {"bflr+",    XLO(19,BOFP,16,0),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3190 {"bflrl+",   XLO(19,BOFP,16,1),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3191 {"bflr-",    XLO(19,BOFM4,16,0),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3192 {"bflrl-",   XLO(19,BOFM4,16,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3193 {"bflr+",    XLO(19,BOFP4,16,0),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3194 {"bflrl+",   XLO(19,BOFP4,16,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3195 {"bdnztlr",  XLO(19,BODNZT,16,0),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3196 {"bdnztlr-", XLO(19,BODNZT,16,0),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3197 {"bdnztlrl", XLO(19,BODNZT,16,1),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3198 {"bdnztlrl-",XLO(19,BODNZT,16,1),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3199 {"bdnztlr+", XLO(19,BODNZTP,16,0),      XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3200 {"bdnztlrl+",XLO(19,BODNZTP,16,1),      XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3201 {"bdztlr",   XLO(19,BODZT,16,0),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3202 {"bdztlr-",  XLO(19,BODZT,16,0),        XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3203 {"bdztlrl",  XLO(19,BODZT,16,1),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3204 {"bdztlrl-", XLO(19,BODZT,16,1),        XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3205 {"bdztlr+",  XLO(19,BODZTP,16,0),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3206 {"bdztlrl+", XLO(19,BODZTP,16,1),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3207 {"btlr",     XLO(19,BOT,16,0),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3208 {"btlr-",    XLO(19,BOT,16,0),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3209 {"bbtr",     XLO(19,BOT,16,0),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
3210 {"btlrl",    XLO(19,BOT,16,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3211 {"btlrl-",   XLO(19,BOT,16,1),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3212 {"bbtrl",    XLO(19,BOT,16,1),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
3213 {"btlr+",    XLO(19,BOTP,16,0),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3214 {"btlrl+",   XLO(19,BOTP,16,1),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3215 {"btlr-",    XLO(19,BOTM4,16,0),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3216 {"btlrl-",   XLO(19,BOTM4,16,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3217 {"btlr+",    XLO(19,BOTP4,16,0),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3218 {"btlrl+",   XLO(19,BOTP4,16,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3219
3220 {"bclr-",    XLYLK(19,16,0,0),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3221 {"bclrl-",   XLYLK(19,16,0,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3222 {"bclr+",    XLYLK(19,16,1,0),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3223 {"bclrl+",   XLYLK(19,16,1,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3224 {"bclr",     XLLK(19,16,0),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
3225 {"bcr",      XLLK(19,16,0),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
3226 {"bclrl",    XLLK(19,16,1),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
3227 {"bcrl",     XLLK(19,16,1),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
3228
3229 {"rfid",        XL(19,18),      0xffffffff,  PPC64,     PPCNONE,        {0}},
3230
3231 {"crnot",       XL(19,33),      XL_MASK,     PPCCOM,    PPCNONE,        {BT, BA, BBA}},
3232 {"crnor",       XL(19,33),      XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3233 {"rfmci",       X(19,38),   0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCNONE, {0}},
3234
3235 {"rfdi",        XL(19,39),      0xffffffff,  E500MC,    PPCNONE,        {0}},
3236 {"rfi",         XL(19,50),      0xffffffff,  COM,       PPCNONE,        {0}},
3237 {"rfci",        XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {0}},
3238
3239 {"rfsvc",       XL(19,82),      0xffffffff,  POWER,     PPCNONE,        {0}},
3240
3241 {"rfgi",        XL(19,102),   0xffffffff, E500MC|PPCA2, PPCNONE,        {0}},
3242
3243 {"crandc",      XL(19,129),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3244
3245 {"isync",       XL(19,150),     0xffffffff,  PPCCOM,    PPCNONE,        {0}},
3246 {"ics",         XL(19,150),     0xffffffff,  PWRCOM,    PPCNONE,        {0}},
3247
3248 {"crclr",       XL(19,193),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BAT, BBA}},
3249 {"crxor",       XL(19,193),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3250
3251 {"dnh",         X(19,198),      X_MASK,      E500MC,    PPCNONE,        {DUI, DUIS}},
3252
3253 {"crnand",      XL(19,225),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3254
3255 {"crand",       XL(19,257),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3256
3257 {"hrfid",       XL(19,274),     0xffffffff, POWER5|CELL, PPC476,        {0}},
3258
3259 {"crset",       XL(19,289),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BAT, BBA}},
3260 {"creqv",       XL(19,289),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3261
3262 {"doze",        XL(19,402),     0xffffffff,  POWER6,    PPCNONE,        {0}},
3263
3264 {"crorc",       XL(19,417),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3265
3266 {"nap",         XL(19,434),     0xffffffff,  POWER6,    PPCNONE,        {0}},
3267
3268 {"crmove",      XL(19,449),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BA, BBA}},
3269 {"cror",        XL(19,449),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3270
3271 {"sleep",       XL(19,466),     0xffffffff,  POWER6,    PPCNONE,        {0}},
3272 {"rvwinkle",    XL(19,498),     0xffffffff,  POWER6,    PPCNONE,        {0}},
3273
3274 {"bctr",    XLO(19,BOU,528,0),          XLBOBIBB_MASK, COM,      PPCNONE,       {0}},
3275 {"bctrl",   XLO(19,BOU,528,1),          XLBOBIBB_MASK, COM,      PPCNONE,       {0}},
3276
3277 {"bgectr",  XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3278 {"bgectr-", XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3279 {"bnlctr",  XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3280 {"bnlctr-", XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3281 {"bgectrl", XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3282 {"bgectrl-",XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3283 {"bnlctrl", XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3284 {"bnlctrl-",XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3285 {"blectr",  XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3286 {"blectr-", XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3287 {"bngctr",  XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3288 {"bngctr-", XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3289 {"blectrl", XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3290 {"blectrl-",XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3291 {"bngctrl", XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3292 {"bngctrl-",XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3293 {"bnectr",  XLOCB(19,BOF,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3294 {"bnectr-", XLOCB(19,BOF,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3295 {"bnectrl", XLOCB(19,BOF,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3296 {"bnectrl-",XLOCB(19,BOF,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3297 {"bnsctr",  XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3298 {"bnsctr-", XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3299 {"bnuctr",  XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3300 {"bnuctr-", XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3301 {"bnsctrl", XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3302 {"bnsctrl-",XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3303 {"bnuctrl", XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3304 {"bnuctrl-",XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3305 {"bgectr+", XLOCB(19,BOFP,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3306 {"bnlctr+", XLOCB(19,BOFP,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3307 {"bgectrl+",XLOCB(19,BOFP,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3308 {"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3309 {"blectr+", XLOCB(19,BOFP,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3310 {"bngctr+", XLOCB(19,BOFP,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3311 {"blectrl+",XLOCB(19,BOFP,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3312 {"bngctrl+",XLOCB(19,BOFP,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3313 {"bnectr+", XLOCB(19,BOFP,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3314 {"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3315 {"bnsctr+", XLOCB(19,BOFP,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3316 {"bnuctr+", XLOCB(19,BOFP,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3317 {"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3318 {"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3319 {"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3320 {"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3321 {"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3322 {"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3323 {"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3324 {"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3325 {"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3326 {"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3327 {"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3328 {"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3329 {"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3330 {"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3331 {"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3332 {"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3333 {"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3334 {"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3335 {"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3336 {"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3337 {"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3338 {"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3339 {"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3340 {"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3341 {"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3342 {"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3343 {"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3344 {"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3345 {"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3346 {"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3347 {"bltctr",  XLOCB(19,BOT,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3348 {"bltctr-", XLOCB(19,BOT,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3349 {"bltctrl", XLOCB(19,BOT,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3350 {"bltctrl-",XLOCB(19,BOT,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3351 {"bgtctr",  XLOCB(19,BOT,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3352 {"bgtctr-", XLOCB(19,BOT,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3353 {"bgtctrl", XLOCB(19,BOT,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3354 {"bgtctrl-",XLOCB(19,BOT,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3355 {"beqctr",  XLOCB(19,BOT,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3356 {"beqctr-", XLOCB(19,BOT,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3357 {"beqctrl", XLOCB(19,BOT,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3358 {"beqctrl-",XLOCB(19,BOT,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3359 {"bsoctr",  XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3360 {"bsoctr-", XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3361 {"bunctr",  XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3362 {"bunctr-", XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3363 {"bsoctrl", XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3364 {"bsoctrl-",XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3365 {"bunctrl", XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3366 {"bunctrl-",XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3367 {"bltctr+", XLOCB(19,BOTP,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3368 {"bltctrl+",XLOCB(19,BOTP,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3369 {"bgtctr+", XLOCB(19,BOTP,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3370 {"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3371 {"beqctr+", XLOCB(19,BOTP,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3372 {"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3373 {"bsoctr+", XLOCB(19,BOTP,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3374 {"bunctr+", XLOCB(19,BOTP,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3375 {"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3376 {"bunctrl+",XLOCB(19,BOTP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3377 {"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3378 {"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3379 {"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3380 {"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3381 {"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3382 {"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3383 {"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3384 {"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3385 {"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3386 {"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3387 {"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3388 {"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3389 {"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3390 {"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3391 {"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3392 {"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3393 {"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3394 {"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3395 {"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3396 {"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3397
3398 {"bfctr",   XLO(19,BOF,528,0),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3399 {"bfctr-",  XLO(19,BOF,528,0),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3400 {"bfctrl",  XLO(19,BOF,528,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3401 {"bfctrl-", XLO(19,BOF,528,1),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3402 {"bfctr+",  XLO(19,BOFP,528,0),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3403 {"bfctrl+", XLO(19,BOFP,528,1),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3404 {"bfctr-",  XLO(19,BOFM4,528,0),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3405 {"bfctrl-", XLO(19,BOFM4,528,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3406 {"bfctr+",  XLO(19,BOFP4,528,0),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3407 {"bfctrl+", XLO(19,BOFP4,528,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3408 {"btctr",   XLO(19,BOT,528,0),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3409 {"btctr-",  XLO(19,BOT,528,0),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3410 {"btctrl",  XLO(19,BOT,528,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3411 {"btctrl-", XLO(19,BOT,528,1),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3412 {"btctr+",  XLO(19,BOTP,528,0),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3413 {"btctrl+", XLO(19,BOTP,528,1),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3414 {"btctr-",  XLO(19,BOTM4,528,0),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3415 {"btctrl-", XLO(19,BOTM4,528,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3416 {"btctr+",  XLO(19,BOTP4,528,0),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3417 {"btctrl+", XLO(19,BOTP4,528,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3418
3419 {"bcctr-",  XLYLK(19,528,0,0),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3420 {"bcctrl-", XLYLK(19,528,0,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3421 {"bcctr+",  XLYLK(19,528,1,0),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3422 {"bcctrl+", XLYLK(19,528,1,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3423 {"bcctr",   XLLK(19,528,0),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
3424 {"bcc",     XLLK(19,528,0),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
3425 {"bcctrl",  XLLK(19,528,1),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
3426 {"bccl",    XLLK(19,528,1),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
3427
3428 {"rlwimi",      M(20,0),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3429 {"rlimi",       M(20,0),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3430
3431 {"rlwimi.",     M(20,1),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3432 {"rlimi.",      M(20,1),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3433
3434 {"rotlwi",      MME(21,31,0),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, SH}},
3435 {"clrlwi",      MME(21,31,0),   MSHME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, MB}},
3436 {"rlwinm",      M(21,0),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3437 {"rlinm",       M(21,0),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3438 {"rotlwi.",     MME(21,31,1),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, SH}},
3439 {"clrlwi.",     MME(21,31,1),   MSHME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, MB}},
3440 {"rlwinm.",     M(21,1),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3441 {"rlinm.",      M(21,1),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3442
3443 {"rlmi",        M(22,0),        M_MASK,      M601,      PPCNONE,        {RA, RS, RB, MBE, ME}},
3444 {"rlmi.",       M(22,1),        M_MASK,      M601,      PPCNONE,        {RA, RS, RB, MBE, ME}},
3445
3446 {"rotlw",       MME(23,31,0),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, RB}},
3447 {"rlwnm",       M(23,0),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
3448 {"rlnm",        M(23,0),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
3449 {"rotlw.",      MME(23,31,1),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, RB}},
3450 {"rlwnm.",      M(23,1),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
3451 {"rlnm.",       M(23,1),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
3452
3453 {"nop",         OP(24),         0xffffffff,  PPCCOM,    PPCNONE,        {0}},
3454 {"ori",         OP(24),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
3455 {"oril",        OP(24),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
3456
3457 {"oris",        OP(25),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
3458 {"oriu",        OP(25),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
3459
3460 {"xori",        OP(26),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
3461 {"xoril",       OP(26),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
3462
3463 {"xoris",       OP(27),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
3464 {"xoriu",       OP(27),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
3465
3466 {"andi.",       OP(28),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
3467 {"andil.",      OP(28),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
3468
3469 {"andis.",      OP(29),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
3470 {"andiu.",      OP(29),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
3471
3472 {"rotldi",      MD(30,0,0),     MDMB_MASK,   PPC64,     PPCNONE,        {RA, RS, SH6}},
3473 {"clrldi",      MD(30,0,0),     MDSH_MASK,   PPC64,     PPCNONE,        {RA, RS, MB6}},
3474 {"rldicl",      MD(30,0,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
3475 {"rotldi.",     MD(30,0,1),     MDMB_MASK,   PPC64,     PPCNONE,        {RA, RS, SH6}},
3476 {"clrldi.",     MD(30,0,1),     MDSH_MASK,   PPC64,     PPCNONE,        {RA, RS, MB6}},
3477 {"rldicl.",     MD(30,0,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
3478
3479 {"rldicr",      MD(30,1,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, ME6}},
3480 {"rldicr.",     MD(30,1,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, ME6}},
3481
3482 {"rldic",       MD(30,2,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
3483 {"rldic.",      MD(30,2,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
3484
3485 {"rldimi",      MD(30,3,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
3486 {"rldimi.",     MD(30,3,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
3487
3488 {"rotld",       MDS(30,8,0),    MDSMB_MASK,  PPC64,     PPCNONE,        {RA, RS, RB}},
3489 {"rldcl",       MDS(30,8,0),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, MB6}},
3490 {"rotld.",      MDS(30,8,1),    MDSMB_MASK,  PPC64,     PPCNONE,        {RA, RS, RB}},
3491 {"rldcl.",      MDS(30,8,1),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, MB6}},
3492
3493 {"rldcr",       MDS(30,9,0),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, ME6}},
3494 {"rldcr.",      MDS(30,9,1),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, ME6}},
3495
3496 {"cmpw",        XOPL(31,0,0),   XCMPL_MASK,  PPCCOM,    PPCNONE,        {OBF, RA, RB}},
3497 {"cmpd",        XOPL(31,0,1),   XCMPL_MASK,  PPC64,     PPCNONE,        {OBF, RA, RB}},
3498 {"cmp",         X(31,0),        XCMP_MASK,   PPC,       PPCNONE,        {BF, L, RA, RB}},
3499 {"cmp",         X(31,0),        XCMPL_MASK,  PWRCOM,    PPC,            {BF, RA, RB}},
3500
3501 {"twlgt",       XTO(31,4,TOLGT), XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3502 {"tlgt",        XTO(31,4,TOLGT), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3503 {"twllt",       XTO(31,4,TOLLT), XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3504 {"tllt",        XTO(31,4,TOLLT), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3505 {"tweq",        XTO(31,4,TOEQ),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3506 {"teq",         XTO(31,4,TOEQ),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3507 {"twlge",       XTO(31,4,TOLGE), XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3508 {"tlge",        XTO(31,4,TOLGE), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3509 {"twlnl",       XTO(31,4,TOLNL), XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3510 {"tlnl",        XTO(31,4,TOLNL), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3511 {"twlle",       XTO(31,4,TOLLE), XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3512 {"tlle",        XTO(31,4,TOLLE), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3513 {"twlng",       XTO(31,4,TOLNG), XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3514 {"tlng",        XTO(31,4,TOLNG), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3515 {"twgt",        XTO(31,4,TOGT),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3516 {"tgt",         XTO(31,4,TOGT),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3517 {"twge",        XTO(31,4,TOGE),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3518 {"tge",         XTO(31,4,TOGE),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3519 {"twnl",        XTO(31,4,TONL),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3520 {"tnl",         XTO(31,4,TONL),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3521 {"twlt",        XTO(31,4,TOLT),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3522 {"tlt",         XTO(31,4,TOLT),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3523 {"twle",        XTO(31,4,TOLE),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3524 {"tle",         XTO(31,4,TOLE),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3525 {"twng",        XTO(31,4,TONG),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3526 {"tng",         XTO(31,4,TONG),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3527 {"twne",        XTO(31,4,TONE),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3528 {"tne",         XTO(31,4,TONE),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3529 {"trap",        XTO(31,4,TOU),   0xffffffff, PPCCOM,    PPCNONE,        {0}},
3530 {"tw",          X(31,4),         X_MASK,     PPCCOM,    PPCNONE,        {TO, RA, RB}},
3531 {"t",           X(31,4),         X_MASK,     PWRCOM,    PPCNONE,        {TO, RA, RB}},
3532
3533 {"lvsl",        X(31,6),        X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
3534 {"lvebx",       X(31,7),        X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
3535 {"lbfcmx",      APU(31,7,0),    APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3536
3537 {"subfc",       XO(31,8,0,0),   XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3538 {"sf",          XO(31,8,0,0),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3539 {"subc",        XO(31,8,0,0),   XO_MASK,     PPCCOM,    PPCNONE,        {RT, RB, RA}},
3540 {"subfc.",      XO(31,8,0,1),   XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3541 {"sf.",         XO(31,8,0,1),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3542 {"subc.",       XO(31,8,0,1),   XO_MASK,     PPCCOM,    PPCNONE,        {RT, RB, RA}},
3543
3544 {"mulhdu",      XO(31,9,0,0),   XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
3545 {"mulhdu.",     XO(31,9,0,1),   XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
3546
3547 {"addc",        XO(31,10,0,0),  XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3548 {"a",           XO(31,10,0,0),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3549 {"addc.",       XO(31,10,0,1),  XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3550 {"a.",          XO(31,10,0,1),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3551
3552 {"mulhwu",      XO(31,11,0,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
3553 {"mulhwu.",     XO(31,11,0,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
3554
3555 {"isellt",      X(31,15),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA, RB}},
3556
3557 {"tlbilxlpid",  XTO(31,18,0),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {0}},
3558 {"tlbilxpid",   XTO(31,18,1),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {0}},
3559 {"tlbilxva",    XTO(31,18,3),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {RA0, RB}},
3560 {"tlbilx",      X(31,18),       X_MASK,   E500MC|PPCA2, PPCNONE,        {T, RA0, RB}},
3561
3562 {"mfcr",        XFXM(31,19,0,0), XFXFXM_MASK, POWER4,   PPCNONE,        {RT, FXM4}},
3563 {"mfcr",        XFXM(31,19,0,0), XRARB_MASK, COM,       POWER4,         {RT}},
3564 {"mfocrf",      XFXM(31,19,0,1), XFXFXM_MASK, COM,      PPCNONE,        {RT, FXM}},
3565
3566 {"lwarx",       X(31,20),       XEH_MASK,    PPC,       PPCNONE,        {RT, RA0, RB, EH}},
3567
3568 {"ldx",         X(31,21),       X_MASK,      PPC64,     PPCNONE,        {RT, RA0, RB}},
3569
3570 {"icbt",        X(31,22),       X_MASK, BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {CT, RA, RB}},
3571
3572 {"lwzx",        X(31,23),       X_MASK,      PPCCOM,    PPCNONE,        {RT, RA0, RB}},
3573 {"lx",          X(31,23),       X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
3574
3575 {"slw",         XRC(31,24,0),   X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB}},
3576 {"sl",          XRC(31,24,0),   X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
3577 {"slw.",        XRC(31,24,1),   X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB}},
3578 {"sl.",         XRC(31,24,1),   X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
3579
3580 {"cntlzw",      XRC(31,26,0),   XRB_MASK,    PPCCOM,    PPCNONE,        {RA, RS}},
3581 {"cntlz",       XRC(31,26,0),   XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
3582 {"cntlzw.",     XRC(31,26,1),   XRB_MASK,    PPCCOM,    PPCNONE,        {RA, RS}},
3583 {"cntlz.",      XRC(31,26,1),   XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
3584
3585 {"sld",         XRC(31,27,0),   X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
3586 {"sld.",        XRC(31,27,1),   X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
3587
3588 {"and",         XRC(31,28,0),   X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3589 {"and.",        XRC(31,28,1),   X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3590
3591 {"maskg",       XRC(31,29,0),   X_MASK,      M601,      PPCA2,          {RA, RS, RB}},
3592 {"maskg.",      XRC(31,29,1),   X_MASK,      M601,      PPCA2,          {RA, RS, RB}},
3593
3594 {"ldepx",       X(31,29),       X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
3595 {"lwepx",       X(31,31),       X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
3596
3597 {"cmplw",       XOPL(31,32,0),  XCMPL_MASK,  PPCCOM,    PPCNONE,        {OBF, RA, RB}},
3598 {"cmpld",       XOPL(31,32,1),  XCMPL_MASK,  PPC64,     PPCNONE,        {OBF, RA, RB}},
3599 {"cmpl",        X(31,32),       XCMP_MASK,   PPC,       PPCNONE,        {BF, L, RA, RB}},
3600 {"cmpl",        X(31,32),       XCMPL_MASK,  PWRCOM,    PPC,            {BF, RA, RB}},
3601
3602 {"lvsr",        X(31,38),       X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
3603 {"lvehx",       X(31,39),       X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
3604 {"lhfcmx",      APU(31,39,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3605
3606 {"iselgt",      X(31,47),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA, RB}},
3607
3608 {"lvewx",       X(31,71),       X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
3609
3610 {"addg6s",      XO(31,74,0,0),  XO_MASK,     POWER6,    PPCNONE,        {RT, RA, RB}},
3611
3612 {"iseleq",      X(31,79),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA, RB}},
3613
3614 {"isel",        XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, PPCNONE,       {RT, RA, RB, CRB}},
3615
3616 {"subf",        XO(31,40,0,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
3617 {"sub",         XO(31,40,0,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
3618 {"subf.",       XO(31,40,0,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
3619 {"sub.",        XO(31,40,0,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
3620
3621 {"eratilx",     X(31,51),       X_MASK,      PPCA2,     PPCNONE,        {ERAT_T, RA, RB}},
3622
3623 {"lbarx",       X(31,52),       XEH_MASK,    POWER7,    PPCNONE,        {RT, RA0, RB, EH}},
3624
3625 {"ldux",        X(31,53),       X_MASK,      PPC64,     PPCNONE,        {RT, RAL, RB}},
3626
3627 {"dcbst",       X(31,54),       XRT_MASK,    PPC,       PPCNONE,        {RA, RB}},
3628
3629 {"lwzux",       X(31,55),       X_MASK,      PPCCOM,    PPCNONE,        {RT, RAL, RB}},
3630 {"lux",         X(31,55),       X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
3631
3632 {"cntlzd",      XRC(31,58,0),   XRB_MASK,    PPC64,     PPCNONE,        {RA, RS}},
3633 {"cntlzd.",     XRC(31,58,1),   XRB_MASK,    PPC64,     PPCNONE,        {RA, RS}},
3634
3635 {"andc",        XRC(31,60,0),   X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3636 {"andc.",       XRC(31,60,1),   X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3637
3638 {"waitrsv",     X(31,62)|(1<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
3639 {"waitimpl",    X(31,62)|(2<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
3640 {"wait",        X(31,62),         XWC_MASK,   POWER7|E500MC|PPCA2, PPCNONE, {WC}},
3641
3642 {"dcbstep",     XRT(31,63,0),   XRT_MASK, E500MC|PPCA2, PPCNONE,        {RA, RB}},
3643
3644 {"tdlgt",       XTO(31,68,TOLGT), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3645 {"tdllt",       XTO(31,68,TOLLT), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3646 {"tdeq",        XTO(31,68,TOEQ),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3647 {"tdlge",       XTO(31,68,TOLGE), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3648 {"tdlnl",       XTO(31,68,TOLNL), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3649 {"tdlle",       XTO(31,68,TOLLE), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3650 {"tdlng",       XTO(31,68,TOLNG), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3651 {"tdgt",        XTO(31,68,TOGT),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3652 {"tdge",        XTO(31,68,TOGE),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3653 {"tdnl",        XTO(31,68,TONL),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3654 {"tdlt",        XTO(31,68,TOLT),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3655 {"tdle",        XTO(31,68,TOLE),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3656 {"tdng",        XTO(31,68,TONG),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3657 {"tdne",        XTO(31,68,TONE),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3658 {"td",          X(31,68),       X_MASK,      PPC64,     PPCNONE,        {TO, RA, RB}},
3659
3660 {"lwfcmx",      APU(31,71,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3661 {"mulhd",       XO(31,73,0,0),  XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
3662 {"mulhd.",      XO(31,73,0,1),  XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
3663
3664 {"mulhw",       XO(31,75,0,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
3665 {"mulhw.",      XO(31,75,0,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
3666
3667 {"dlmzb",       XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, PPCNONE,     {RA, RS, RB}},
3668 {"dlmzb.",      XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, PPCNONE,     {RA, RS, RB}},
3669
3670 {"mtsrd",       X(31,82),  XRB_MASK|(1<<20), PPC64,     PPCNONE,        {SR, RS}},
3671
3672 {"mfmsr",       X(31,83),       XRARB_MASK,  COM,       PPCNONE,        {RT}},
3673
3674 {"ldarx",       X(31,84),       XEH_MASK,    PPC64,     PPCNONE,        {RT, RA0, RB, EH}},
3675
3676 {"dcbfl",       XOPL(31,86,1),  XRT_MASK,    POWER5,    PPC476,         {RA, RB}},
3677 {"dcbf",        X(31,86),       XLRT_MASK,   PPC,       PPCNONE,        {RA, RB, L}},
3678
3679 {"lbzx",        X(31,87),       X_MASK,      COM,       PPCNONE,        {RT, RA0, RB}},
3680
3681 {"lbepx",       X(31,95),       X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
3682
3683 {"lvx",         X(31,103),      X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
3684 {"lqfcmx",      APU(31,103,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3685
3686 {"neg",         XO(31,104,0,0), XORB_MASK,   COM,       PPCNONE,        {RT, RA}},
3687 {"neg.",        XO(31,104,0,1), XORB_MASK,   COM,       PPCNONE,        {RT, RA}},
3688
3689 {"mul",         XO(31,107,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
3690 {"mul.",        XO(31,107,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
3691
3692 {"mtsrdin",     X(31,114),      XRA_MASK,    PPC64,     PPCNONE,        {RS, RB}},
3693
3694 {"lharx",       X(31,116),      XEH_MASK,    POWER7,    PPCNONE,        {RT, RA0, RB, EH}},
3695
3696 {"clf",         X(31,118),      XTO_MASK,    POWER,     PPCNONE,        {RA, RB}},
3697
3698 {"lbzux",       X(31,119),      X_MASK,      COM,       PPCNONE,        {RT, RAL, RB}},
3699
3700 {"popcntb",     X(31,122),      XRB_MASK,    POWER5,    PPCNONE,        {RA, RS}},
3701
3702 {"not",         XRC(31,124,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RBS}},
3703 {"nor",         XRC(31,124,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3704 {"not.",        XRC(31,124,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RBS}},
3705 {"nor.",        XRC(31,124,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3706
3707 {"dcbfep",      XRT(31,127,0),  XRT_MASK, E500MC|PPCA2, PPCNONE,        {RA, RB}},
3708
3709 {"wrtee",       X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RS}},
3710
3711 {"dcbtstls",    X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,       {CT, RA, RB}},
3712
3713 {"stvebx",      X(31,135),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
3714 {"stbfcmx",     APU(31,135,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3715
3716 {"subfe",       XO(31,136,0,0), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3717 {"sfe",         XO(31,136,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3718 {"subfe.",      XO(31,136,0,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3719 {"sfe.",        XO(31,136,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3720
3721 {"adde",        XO(31,138,0,0), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3722 {"ae",          XO(31,138,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3723 {"adde.",       XO(31,138,0,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3724 {"ae.",         XO(31,138,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3725
3726 {"dcbtstlse",   X(31,142),      X_MASK,      PPCCHLK,   PPCNONE,        {CT, RA, RB}},
3727
3728 {"mtcr",        XFXM(31,144,0xff,0), XRARB_MASK, COM,   PPCNONE,        {RS}},
3729 {"mtcrf",       XFXM(31,144,0,0), XFXFXM_MASK, COM,     PPCNONE,        {FXM, RS}},
3730 {"mtocrf",      XFXM(31,144,0,1), XFXFXM_MASK, COM,     PPCNONE,        {FXM, RS}},
3731
3732 {"mtmsr",       X(31,146),      XRLARB_MASK, COM,       PPCNONE,        {RS, A_L}},
3733
3734 {"eratsx",      XRC(31,147,0),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
3735 {"eratsx.",     XRC(31,147,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
3736
3737 {"stdx",        X(31,149),      X_MASK,      PPC64,     PPCNONE,        {RS, RA0, RB}},
3738
3739 {"stwcx.",      XRC(31,150,1),  X_MASK,      PPC,       PPCNONE,        {RS, RA0, RB}},
3740
3741 {"stwx",        X(31,151),      X_MASK,      PPCCOM,    PPCNONE,        {RS, RA0, RB}},
3742 {"stx",         X(31,151),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA, RB}},
3743
3744 {"slq",         XRC(31,152,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3745 {"slq.",        XRC(31,152,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3746
3747 {"sle",         XRC(31,153,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3748 {"sle.",        XRC(31,153,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3749
3750 {"prtyw",       X(31,154),      XRB_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS}},
3751
3752 {"stdepx",      X(31,157),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RS, RA, RB}},
3753
3754 {"stwepx",      X(31,159),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RS, RA, RB}},
3755
3756 {"wrteei",      X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {E}},
3757
3758 {"dcbtls",      X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,       {CT, RA, RB}},
3759
3760 {"stvehx",      X(31,167),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
3761 {"sthfcmx",     APU(31,167,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3762
3763 {"dcbtlse",     X(31,174),      X_MASK,      PPCCHLK,   PPCNONE,        {CT, RA, RB}},
3764
3765 {"mtmsrd",      X(31,178),      XRLARB_MASK, PPC64,     PPCNONE,        {RS, A_L}},
3766
3767 {"eratre",      X(31,179),      X_MASK,      PPCA2,     PPCNONE,        {RT, RA, WS}},
3768
3769 {"stdux",       X(31,181),      X_MASK,      PPC64,     PPCNONE,        {RS, RAS, RB}},
3770
3771 {"wchkall",     X(31,182),      X_MASK,      PPCA2,     PPCNONE,        {OBF}},
3772
3773 {"stwux",       X(31,183),      X_MASK,      PPCCOM,    PPCNONE,        {RS, RAS, RB}},
3774 {"stux",        X(31,183),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
3775
3776 {"sliq",        XRC(31,184,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
3777 {"sliq.",       XRC(31,184,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
3778
3779 {"prtyd",       X(31,186),      XRB_MASK, POWER6|PPCA2, PPCNONE,        {RA, RS}},
3780
3781 {"stvewx",      X(31,199),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
3782 {"stwfcmx",     APU(31,199,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3783
3784 {"subfze",      XO(31,200,0,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3785 {"sfze",        XO(31,200,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3786 {"subfze.",     XO(31,200,0,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3787 {"sfze.",       XO(31,200,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3788
3789 {"addze",       XO(31,202,0,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3790 {"aze",         XO(31,202,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3791 {"addze.",      XO(31,202,0,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3792 {"aze.",        XO(31,202,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3793
3794 {"msgsnd",      XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2, PPCNONE,   {RB}},
3795
3796 {"mtsr",        X(31,210), XRB_MASK|(1<<20), COM,       NON32,          {SR, RS}},
3797
3798 {"eratwe",      X(31,211),      X_MASK,      PPCA2,     PPCNONE,        {RS, RA, WS}},
3799
3800 {"ldawx.",      XRC(31,212,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
3801
3802 {"stdcx.",      XRC(31,214,1),  X_MASK,      PPC64,     PPCNONE,        {RS, RA0, RB}},
3803
3804 {"stbx",        X(31,215),      X_MASK,      COM,       PPCNONE,        {RS, RA0, RB}},
3805
3806 {"sllq",        XRC(31,216,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3807 {"sllq.",       XRC(31,216,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3808
3809 {"sleq",        XRC(31,217,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3810 {"sleq.",       XRC(31,217,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3811
3812 {"stbepx",      X(31,223),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RS, RA, RB}},
3813
3814 {"icblc",       X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,       {CT, RA, RB}},
3815
3816 {"stvx",        X(31,231),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
3817 {"stqfcmx",     APU(31,231,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3818
3819 {"subfme",      XO(31,232,0,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3820 {"sfme",        XO(31,232,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3821 {"subfme.",     XO(31,232,0,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3822 {"sfme.",       XO(31,232,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3823
3824 {"mulld",       XO(31,233,0,0), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
3825 {"mulld.",      XO(31,233,0,1), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
3826
3827 {"addme",       XO(31,234,0,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3828 {"ame",         XO(31,234,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3829 {"addme.",      XO(31,234,0,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3830 {"ame.",        XO(31,234,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3831
3832 {"mullw",       XO(31,235,0,0), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3833 {"muls",        XO(31,235,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3834 {"mullw.",      XO(31,235,0,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3835 {"muls.",       XO(31,235,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3836
3837 {"icblce",      X(31,238),      X_MASK,      PPCCHLK,   E500MC|PPCA2,   {CT, RA, RB}},
3838 {"msgclr",      XRTRA(31,238,0,0),XRTRA_MASK,E500MC|PPCA2, PPCNONE,     {RB}},
3839 {"mtsrin",      X(31,242),      XRA_MASK,    PPC,       NON32,          {RS, RB}},
3840 {"mtsri",       X(31,242),      XRA_MASK,    POWER,     NON32,          {RS, RB}},
3841
3842 {"dcbtstt",     XRT(31,246,0x10), XRT_MASK,  POWER7,    PPCNONE,        {RA, RB}},
3843 {"dcbtst",      X(31,246),      X_MASK,      POWER4,    PPCNONE,        {RA, RB, CT}},
3844 {"dcbtst",      X(31,246),      X_MASK,      PPC,       POWER4,         {CT, RA, RB}},
3845
3846 {"stbux",       X(31,247),      X_MASK,      COM,       PPCNONE,        {RS, RAS, RB}},
3847
3848 {"slliq",       XRC(31,248,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
3849 {"slliq.",      XRC(31,248,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
3850
3851 {"bpermd",      X(31,252),      X_MASK,   POWER7|PPCA2, PPCNONE,        {RA, RS, RB}},
3852
3853 {"dcbtstep",    XRT(31,255,0),  X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
3854
3855 {"mfdcrx",      X(31,259),      X_MASK, BOOKE|PPCA2|PPC476, TITAN,      {RS, RA}},
3856 {"mfdcrx.",     XRC(31,259,1),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA}},
3857
3858 {"icbt",        X(31,262),      XRT_MASK,    PPC403,    PPCNONE,        {RA, RB}},
3859
3860 {"ldfcmx",      APU(31,263,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3861 {"doz",         XO(31,264,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
3862 {"doz.",        XO(31,264,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
3863
3864 {"add",         XO(31,266,0,0), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3865 {"cax",         XO(31,266,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3866 {"add.",        XO(31,266,0,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3867 {"cax.",        XO(31,266,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3868
3869 {"ehpriv",      X(31,270),      0xffffffff, E500MC|PPCA2, PPCNONE,      {0}},
3870
3871 {"tlbiel",      X(31,274),      XRTLRA_MASK, POWER4,    PPC476,         {RB, L}},
3872
3873 {"mfapidi",     X(31,275),      X_MASK,      BOOKE,     TITAN,          {RT, RA}},
3874
3875 {"lscbx",       XRC(31,277,0),  X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
3876 {"lscbx.",      XRC(31,277,1),  X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
3877
3878 {"dcbtt",       XRT(31,278,0x10), XRT_MASK,  POWER7,    PPCNONE,        {RA, RB}},
3879 {"dcbt",        X(31,278),      X_MASK,      POWER4,    PPCNONE,        {RA, RB, CT}},
3880 {"dcbt",        X(31,278),      X_MASK,      PPC,       POWER4,         {CT, RA, RB}},
3881
3882 {"lhzx",        X(31,279),      X_MASK,      COM,       PPCNONE,        {RT, RA0, RB}},
3883
3884 {"cdtbcd",      X(31,282),      XRB_MASK,    POWER6,    PPCNONE,        {RA, RS}},
3885
3886 {"eqv",         XRC(31,284,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3887 {"eqv.",        XRC(31,284,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3888
3889 {"lhepx",       X(31,287),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
3890
3891 {"mfdcrux",     X(31,291),      X_MASK,      PPC464,    PPCNONE,        {RS, RA}},
3892
3893 {"tlbie",       X(31,306),      XRTLRA_MASK, PPC,       TITAN,          {RB, L}},
3894 {"tlbi",        X(31,306),      XRT_MASK,    POWER,     PPCNONE,        {RA0, RB}},
3895
3896 {"eciwx",       X(31,310),      X_MASK,      PPC,       TITAN,          {RT, RA, RB}},
3897
3898 {"lhzux",       X(31,311),      X_MASK,      COM,       PPCNONE,        {RT, RAL, RB}},
3899
3900 {"cbcdtd",      X(31,314),      XRB_MASK,    POWER6,    PPCNONE,        {RA, RS}},
3901
3902 {"xor",         XRC(31,316,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3903 {"xor.",        XRC(31,316,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3904
3905 {"dcbtep",      XRT(31,319,0),  X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
3906
3907 {"mfexisr",     XSPR(31,323, 64), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3908 {"mfexier",     XSPR(31,323, 66), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3909 {"mfbr0",       XSPR(31,323,128), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3910 {"mfbr1",       XSPR(31,323,129), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3911 {"mfbr2",       XSPR(31,323,130), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3912 {"mfbr3",       XSPR(31,323,131), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3913 {"mfbr4",       XSPR(31,323,132), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3914 {"mfbr5",       XSPR(31,323,133), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3915 {"mfbr6",       XSPR(31,323,134), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3916 {"mfbr7",       XSPR(31,323,135), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3917 {"mfbear",      XSPR(31,323,144), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3918 {"mfbesr",      XSPR(31,323,145), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3919 {"mfiocr",      XSPR(31,323,160), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3920 {"mfdmacr0",    XSPR(31,323,192), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3921 {"mfdmact0",    XSPR(31,323,193), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3922 {"mfdmada0",    XSPR(31,323,194), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3923 {"mfdmasa0",    XSPR(31,323,195), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3924 {"mfdmacc0",    XSPR(31,323,196), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3925 {"mfdmacr1",    XSPR(31,323,200), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3926 {"mfdmact1",    XSPR(31,323,201), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3927 {"mfdmada1",    XSPR(31,323,202), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3928 {"mfdmasa1",    XSPR(31,323,203), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3929 {"mfdmacc1",    XSPR(31,323,204), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3930 {"mfdmacr2",    XSPR(31,323,208), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3931 {"mfdmact2",    XSPR(31,323,209), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3932 {"mfdmada2",    XSPR(31,323,210), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3933 {"mfdmasa2",    XSPR(31,323,211), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3934 {"mfdmacc2",    XSPR(31,323,212), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3935 {"mfdmacr3",    XSPR(31,323,216), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3936 {"mfdmact3",    XSPR(31,323,217), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3937 {"mfdmada3",    XSPR(31,323,218), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3938 {"mfdmasa3",    XSPR(31,323,219), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3939 {"mfdmacc3",    XSPR(31,323,220), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3940 {"mfdmasr",     XSPR(31,323,224), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3941 {"mfdcr",       X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN,    {RT, SPR}},
3942 {"mfdcr.",      XRC(31,323,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, SPR}},
3943
3944 {"dcread",      X(31,326),      X_MASK,  PPC476|TITAN,  PPCNONE,        {RT, RA, RB}},
3945
3946 {"div",         XO(31,331,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
3947 {"div.",        XO(31,331,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
3948
3949 {"lxvdsx",      X(31,332),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA, RB}},
3950
3951 {"mfpmr",       X(31,334),      X_MASK, PPCPMR|PPCE300, PPCNONE,        {RT, PMR}},
3952
3953 {"mfmq",        XSPR(31,339,  0), XSPR_MASK, M601,      PPCNONE,        {RT}},
3954 {"mfxer",       XSPR(31,339,  1), XSPR_MASK, COM,       PPCNONE,        {RT}},
3955 {"mfrtcu",      XSPR(31,339,  4), XSPR_MASK, COM,       TITAN,          {RT}},
3956 {"mfrtcl",      XSPR(31,339,  5), XSPR_MASK, COM,       TITAN,          {RT}},
3957 {"mfdec",       XSPR(31,339,  6), XSPR_MASK, MFDEC1,    PPCNONE,        {RT}},
3958 {"mflr",        XSPR(31,339,  8), XSPR_MASK, COM,       PPCNONE,        {RT}},
3959 {"mfctr",       XSPR(31,339,  9), XSPR_MASK, COM,       PPCNONE,        {RT}},
3960 {"mftid",       XSPR(31,339, 17), XSPR_MASK, POWER,     PPCNONE,        {RT}},
3961 {"mfdsisr",     XSPR(31,339, 18), XSPR_MASK, COM,       TITAN,          {RT}},
3962 {"mfdar",       XSPR(31,339, 19), XSPR_MASK, COM,       TITAN,          {RT}},
3963 {"mfdec",       XSPR(31,339, 22), XSPR_MASK, MFDEC2,    MFDEC1,         {RT}},
3964 {"mfsdr0",      XSPR(31,339, 24), XSPR_MASK, POWER,     PPCNONE,        {RT}},
3965 {"mfsdr1",      XSPR(31,339, 25), XSPR_MASK, COM,       TITAN,          {RT}},
3966 {"mfsrr0",      XSPR(31,339, 26), XSPR_MASK, COM,       PPCNONE,        {RT}},
3967 {"mfsrr1",      XSPR(31,339, 27), XSPR_MASK, COM,       PPCNONE,        {RT}},
3968 {"mfcfar",      XSPR(31,339, 28), XSPR_MASK, POWER6,    PPCNONE,        {RT}},
3969 {"mfpid",       XSPR(31,339, 48), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3970 {"mfcsrr0",     XSPR(31,339, 58), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3971 {"mfcsrr1",     XSPR(31,339, 59), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3972 {"mfdear",      XSPR(31,339, 61), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3973 {"mfesr",       XSPR(31,339, 62), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3974 {"mfivpr",      XSPR(31,339, 63), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3975 {"mfcmpa",      XSPR(31,339,144), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3976 {"mfcmpb",      XSPR(31,339,145), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3977 {"mfcmpc",      XSPR(31,339,146), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3978 {"mfcmpd",      XSPR(31,339,147), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3979 {"mficr",       XSPR(31,339,148), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3980 {"mfder",       XSPR(31,339,149), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3981 {"mfcounta",    XSPR(31,339,150), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3982 {"mfcountb",    XSPR(31,339,151), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3983 {"mfcmpe",      XSPR(31,339,152), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3984 {"mfcmpf",      XSPR(31,339,153), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3985 {"mfcmpg",      XSPR(31,339,154), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3986 {"mfcmph",      XSPR(31,339,155), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3987 {"mflctrl1",    XSPR(31,339,156), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3988 {"mflctrl2",    XSPR(31,339,157), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3989 {"mfictrl",     XSPR(31,339,158), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3990 {"mfbar",       XSPR(31,339,159), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3991 {"mfvrsave",    XSPR(31,339,256), XSPR_MASK, PPCVEC,    PPCNONE,        {RT}},
3992 {"mfusprg0",    XSPR(31,339,256), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3993 {"mfsprg",      XSPR(31,339,256), XSPRG_MASK, PPC,      PPCNONE,        {RT, SPRG}},
3994 {"mfsprg4",     XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RT}},
3995 {"mfsprg5",     XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RT}},
3996 {"mfsprg6",     XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RT}},
3997 {"mfsprg7",     XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RT}},
3998 {"mftb",        XSPR(31,339,268), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3999 {"mftbl",       XSPR(31,339,268), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4000 {"mftbu",       XSPR(31,339,269), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4001 {"mfsprg0",     XSPR(31,339,272), XSPR_MASK, PPC,       PPCNONE,        {RT}},
4002 {"mfsprg1",     XSPR(31,339,273), XSPR_MASK, PPC,       PPCNONE,        {RT}},
4003 {"mfsprg2",     XSPR(31,339,274), XSPR_MASK, PPC,       PPCNONE,        {RT}},
4004 {"mfsprg3",     XSPR(31,339,275), XSPR_MASK, PPC,       PPCNONE,        {RT}},
4005 {"mfasr",       XSPR(31,339,280), XSPR_MASK, PPC64,     PPCNONE,        {RT}},
4006 {"mfear",       XSPR(31,339,282), XSPR_MASK, PPC,       TITAN,          {RT}},
4007 {"mfpir",       XSPR(31,339,286), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4008 {"mfpvr",       XSPR(31,339,287), XSPR_MASK, PPC,       PPCNONE,        {RT}},
4009 {"mfdbsr",      XSPR(31,339,304), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4010 {"mfdbcr0",     XSPR(31,339,308), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4011 {"mfdbcr1",     XSPR(31,339,309), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4012 {"mfdbcr2",     XSPR(31,339,310), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4013 {"mfiac1",      XSPR(31,339,312), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4014 {"mfiac2",      XSPR(31,339,313), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4015 {"mfiac3",      XSPR(31,339,314), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4016 {"mfiac4",      XSPR(31,339,315), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4017 {"mfdac1",      XSPR(31,339,316), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4018 {"mfdac2",      XSPR(31,339,317), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4019 {"mfdvc1",      XSPR(31,339,318), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4020 {"mfdvc2",      XSPR(31,339,319), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4021 {"mftsr",       XSPR(31,339,336), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4022 {"mftcr",       XSPR(31,339,340), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4023 {"mfivor0",     XSPR(31,339,400), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4024 {"mfivor1",     XSPR(31,339,401), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4025 {"mfivor2",     XSPR(31,339,402), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4026 {"mfivor3",     XSPR(31,339,403), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4027 {"mfivor4",     XSPR(31,339,404), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4028 {"mfivor5",     XSPR(31,339,405), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4029 {"mfivor6",     XSPR(31,339,406), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4030 {"mfivor7",     XSPR(31,339,407), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4031 {"mfivor8",     XSPR(31,339,408), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4032 {"mfivor9",     XSPR(31,339,409), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4033 {"mfivor10",    XSPR(31,339,410), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4034 {"mfivor11",    XSPR(31,339,411), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4035 {"mfivor12",    XSPR(31,339,412), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4036 {"mfivor13",    XSPR(31,339,413), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4037 {"mfivor14",    XSPR(31,339,414), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4038 {"mfivor15",    XSPR(31,339,415), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
4039 {"mfspefscr",   XSPR(31,339,512), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
4040 {"mfbbear",     XSPR(31,339,513), XSPR_MASK, PPCBRLK,   PPCNONE,        {RT}},
4041 {"mfbbtar",     XSPR(31,339,514), XSPR_MASK, PPCBRLK,   PPCNONE,        {RT}},
4042 {"mfivor32",    XSPR(31,339,528), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
4043 {"mfibatu",     XSPR(31,339,528), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
4044 {"mfivor33",    XSPR(31,339,529), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
4045 {"mfibatl",     XSPR(31,339,529), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
4046 {"mfivor34",    XSPR(31,339,530), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
4047 {"mfivor35",    XSPR(31,339,531), XSPR_MASK, PPCPMR,    PPCNONE,        {RT}},
4048 {"mfdbatu",     XSPR(31,339,536), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
4049 {"mfdbatl",     XSPR(31,339,537), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
4050 {"mfic_cst",    XSPR(31,339,560), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4051 {"mfic_adr",    XSPR(31,339,561), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4052 {"mfic_dat",    XSPR(31,339,562), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4053 {"mfdc_cst",    XSPR(31,339,568), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4054 {"mfdc_adr",    XSPR(31,339,569), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4055 {"mfdc_dat",    XSPR(31,339,570), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4056 {"mfmcsrr0",    XSPR(31,339,570), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RT}},
4057 {"mfmcsrr1",    XSPR(31,339,571), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RT}},
4058 {"mfmcsr",      XSPR(31,339,572), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RT}},
4059 {"mfmcar",      XSPR(31,339,573), XSPR_MASK, PPCRFMCI,  TITAN,          {RT}},
4060 {"mfdpdr",      XSPR(31,339,630), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4061 {"mfdpir",      XSPR(31,339,631), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4062 {"mfimmr",      XSPR(31,339,638), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4063 {"mfmi_ctr",    XSPR(31,339,784), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4064 {"mfmi_ap",     XSPR(31,339,786), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4065 {"mfmi_epn",    XSPR(31,339,787), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4066 {"mfmi_twc",    XSPR(31,339,789), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4067 {"mfmi_rpn",    XSPR(31,339,790), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4068 {"mfmd_ctr",    XSPR(31,339,792), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4069 {"mfm_casid",   XSPR(31,339,793), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4070 {"mfmd_ap",     XSPR(31,339,794), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4071 {"mfmd_epn",    XSPR(31,339,795), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4072 {"mfmd_twb",    XSPR(31,339,796), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4073 {"mfmd_twc",    XSPR(31,339,797), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4074 {"mfmd_rpn",    XSPR(31,339,798), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4075 {"mfm_tw",      XSPR(31,339,799), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4076 {"mfmi_dbcam",  XSPR(31,339,816), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4077 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4078 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4079 {"mfmd_dbcam",  XSPR(31,339,824), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4080 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4081 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4082 {"mfivndx",     XSPR(31,339,880), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4083 {"mfdvndx",     XSPR(31,339,881), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4084 {"mfivlim",     XSPR(31,339,882), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4085 {"mfdvlim",     XSPR(31,339,883), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4086 {"mfclcsr",     XSPR(31,339,884), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4087 {"mfccr1",      XSPR(31,339,888), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4088 {"mfrstcfg",    XSPR(31,339,923), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4089 {"mfdcdbtrl",   XSPR(31,339,924), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4090 {"mfdcdbtrh",   XSPR(31,339,925), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4091 {"mficdbtr",    XSPR(31,339,927), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4092 {"mfummcr0",    XSPR(31,339,936), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4093 {"mfupmc1",     XSPR(31,339,937), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4094 {"mfupmc2",     XSPR(31,339,938), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4095 {"mfusia",      XSPR(31,339,939), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4096 {"mfummcr1",    XSPR(31,339,940), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4097 {"mfupmc3",     XSPR(31,339,941), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4098 {"mfupmc4",     XSPR(31,339,942), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4099 {"mfzpr",       XSPR(31,339,944), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4100 {"mfpid",       XSPR(31,339,945), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4101 {"mfmmucr",     XSPR(31,339,946), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4102 {"mfccr0",      XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, PPCNONE,     {RT}},
4103 {"mfiac3",      XSPR(31,339,948), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4104 {"mfiac4",      XSPR(31,339,949), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4105 {"mfdvc1",      XSPR(31,339,950), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4106 {"mfdvc2",      XSPR(31,339,951), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4107 {"mfmmcr0",     XSPR(31,339,952), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4108 {"mfpmc1",      XSPR(31,339,953), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4109 {"mfsgr",       XSPR(31,339,953), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4110 {"mfdcwr",      XSPR(31,339,954), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4111 {"mfpmc2",      XSPR(31,339,954), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4112 {"mfsia",       XSPR(31,339,955), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4113 {"mfsler",      XSPR(31,339,955), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4114 {"mfmmcr1",     XSPR(31,339,956), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4115 {"mfsu0r",      XSPR(31,339,956), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4116 {"mfdbcr1",     XSPR(31,339,957), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4117 {"mfpmc3",      XSPR(31,339,957), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4118 {"mfpmc4",      XSPR(31,339,958), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4119 {"mficdbdr",    XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, PPCNONE,     {RT}},
4120 {"mfesr",       XSPR(31,339,980), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4121 {"mfdear",      XSPR(31,339,981), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4122 {"mfevpr",      XSPR(31,339,982), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4123 {"mfcdbcr",     XSPR(31,339,983), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4124 {"mftsr",       XSPR(31,339,984), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4125 {"mftcr",       XSPR(31,339,986), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4126 {"mfpit",       XSPR(31,339,987), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4127 {"mftbhi",      XSPR(31,339,988), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4128 {"mftblo",      XSPR(31,339,989), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4129 {"mfsrr2",      XSPR(31,339,990), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4130 {"mfsrr3",      XSPR(31,339,991), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4131 {"mfdbsr",      XSPR(31,339,1008), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4132 {"mfdbcr0",     XSPR(31,339,1010), XSPR_MASK, PPC405,   PPCNONE,        {RT}},
4133 {"mfdbdr",      XSPR(31,339,1011), XSPR_MASK, TITAN,    PPCNONE,        {RS}},
4134 {"mfiac1",      XSPR(31,339,1012), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4135 {"mfiac2",      XSPR(31,339,1013), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4136 {"mfdac1",      XSPR(31,339,1014), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4137 {"mfdac2",      XSPR(31,339,1015), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4138 {"mfl2cr",      XSPR(31,339,1017), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4139 {"mfdccr",      XSPR(31,339,1018), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4140 {"mficcr",      XSPR(31,339,1019), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4141 {"mfictc",      XSPR(31,339,1019), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4142 {"mfpbl1",      XSPR(31,339,1020), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4143 {"mfthrm1",     XSPR(31,339,1020), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4144 {"mfpbu1",      XSPR(31,339,1021), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4145 {"mfthrm2",     XSPR(31,339,1021), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4146 {"mfpbl2",      XSPR(31,339,1022), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4147 {"mfthrm3",     XSPR(31,339,1022), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4148 {"mfpbu2",      XSPR(31,339,1023), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4149 {"mfspr",       X(31,339),      X_MASK,      COM,       PPCNONE,        {RT, SPR}},
4150
4151 {"lwax",        X(31,341),      X_MASK,      PPC64,     PPCNONE,        {RT, RA0, RB}},
4152
4153 {"dst",         XDSS(31,342,0), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
4154
4155 {"lhax",        X(31,343),      X_MASK,      COM,       PPCNONE,        {RT, RA0, RB}},
4156
4157 {"lvxl",        X(31,359),      X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
4158
4159 {"abs",         XO(31,360,0,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4160 {"abs.",        XO(31,360,0,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4161
4162 {"divs",        XO(31,363,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4163 {"divs.",       XO(31,363,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4164
4165 {"tlbia",       X(31,370),      0xffffffff,  PPC,       TITAN,          {0}},
4166
4167 {"mftbl",       XSPR(31,371,268), XSPR_MASK, PPC,       NO371,          {RT}},
4168 {"mftbu",       XSPR(31,371,269), XSPR_MASK, PPC,       NO371,          {RT}},
4169 {"mftb",        X(31,371),      X_MASK,      PPC|PPCA2, NO371|POWER7,   {RT, TBR}},
4170
4171 {"lwaux",       X(31,373),      X_MASK,      PPC64,     PPCNONE,        {RT, RAL, RB}},
4172
4173 {"dstst",       XDSS(31,374,0), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
4174
4175 {"lhaux",       X(31,375),      X_MASK,      COM,       PPCNONE,        {RT, RAL, RB}},
4176
4177 {"popcntw",     X(31,378),      XRB_MASK, POWER7|PPCA2, PPCNONE,        {RA, RS}},
4178
4179 {"mtdcrx",      X(31,387),      X_MASK, BOOKE|PPCA2|PPC476, TITAN,      {RA, RS}},
4180 {"mtdcrx.",     XRC(31,387,1),  X_MASK,      PPCA2,     PPCNONE,        {RA, RS}},
4181
4182 {"dcblc",       X(31,390),      X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,  {CT, RA, RB}},
4183 {"stdfcmx",     APU(31,391,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4184
4185 {"divdeu",      XO(31,393,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4186 {"divdeu.",     XO(31,393,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4187 {"divweu",      XO(31,395,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4188 {"divweu.",     XO(31,395,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4189
4190 {"dcblce",      X(31,398),      X_MASK,      PPCCHLK,   PPCNONE,        {CT, RA, RB}},
4191
4192 {"slbmte",      X(31,402),      XRA_MASK,    PPC64,     PPCNONE,        {RS, RB}},
4193
4194 {"icswx",       XRC(31,406,0),  X_MASK,   POWER7|PPCA2, PPCNONE,        {RS, RA, RB}},
4195 {"icswx.",      XRC(31,406,1),  X_MASK,   POWER7|PPCA2, PPCNONE,        {RS, RA, RB}},
4196
4197 {"sthx",        X(31,407),      X_MASK,      COM,       PPCNONE,        {RS, RA0, RB}},
4198
4199 {"orc",         XRC(31,412,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
4200 {"orc.",        XRC(31,412,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
4201
4202 {"sthepx",      X(31,415),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RS, RA, RB}},
4203
4204 {"mtdcrux",     X(31,419),      X_MASK,      PPC464,    PPCNONE,        {RA, RS}},
4205
4206 {"divde",       XO(31,425,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4207 {"divde.",      XO(31,425,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4208 {"divwe",       XO(31,427,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4209 {"divwe.",      XO(31,427,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4210
4211 {"slbie",       X(31,434),      XRTRA_MASK,  PPC64,     PPCNONE,        {RB}},
4212
4213 {"ecowx",       X(31,438),      X_MASK,      PPC,       TITAN,          {RT, RA, RB}},
4214
4215 {"sthux",       X(31,439),      X_MASK,      COM,       PPCNONE,        {RS, RAS, RB}},
4216
4217 {"mdors",       0x7f9ce378,     0xffffffff,  E500MC,    PPCNONE,        {0}},
4218
4219 {"mr",          XRC(31,444,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RBS}},
4220 {"or",          XRC(31,444,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
4221 {"mr.",         XRC(31,444,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RBS}},
4222 {"or.",         XRC(31,444,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
4223
4224 {"mtexisr",     XSPR(31,451, 64), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4225 {"mtexier",     XSPR(31,451, 66), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4226 {"mtbr0",       XSPR(31,451,128), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4227 {"mtbr1",       XSPR(31,451,129), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4228 {"mtbr2",       XSPR(31,451,130), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4229 {"mtbr3",       XSPR(31,451,131), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4230 {"mtbr4",       XSPR(31,451,132), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4231 {"mtbr5",       XSPR(31,451,133), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4232 {"mtbr6",       XSPR(31,451,134), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4233 {"mtbr7",       XSPR(31,451,135), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4234 {"mtbear",      XSPR(31,451,144), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4235 {"mtbesr",      XSPR(31,451,145), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4236 {"mtiocr",      XSPR(31,451,160), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4237 {"mtdmacr0",    XSPR(31,451,192), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4238 {"mtdmact0",    XSPR(31,451,193), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4239 {"mtdmada0",    XSPR(31,451,194), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4240 {"mtdmasa0",    XSPR(31,451,195), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4241 {"mtdmacc0",    XSPR(31,451,196), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4242 {"mtdmacr1",    XSPR(31,451,200), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4243 {"mtdmact1",    XSPR(31,451,201), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4244 {"mtdmada1",    XSPR(31,451,202), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4245 {"mtdmasa1",    XSPR(31,451,203), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4246 {"mtdmacc1",    XSPR(31,451,204), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4247 {"mtdmacr2",    XSPR(31,451,208), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4248 {"mtdmact2",    XSPR(31,451,209), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4249 {"mtdmada2",    XSPR(31,451,210), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4250 {"mtdmasa2",    XSPR(31,451,211), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4251 {"mtdmacc2",    XSPR(31,451,212), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4252 {"mtdmacr3",    XSPR(31,451,216), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4253 {"mtdmact3",    XSPR(31,451,217), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4254 {"mtdmada3",    XSPR(31,451,218), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4255 {"mtdmasa3",    XSPR(31,451,219), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4256 {"mtdmacc3",    XSPR(31,451,220), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4257 {"mtdmasr",     XSPR(31,451,224), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4258 {"mtdcr",       X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN,    {SPR, RS}},
4259 {"mtdcr.",      XRC(31,451,1), X_MASK,       PPCA2,     PPCNONE,        {SPR, RS}},
4260
4261 {"dccci",       X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
4262 {"dci",         X(31,454),      XRARB_MASK, PPCA2|PPC476, PPCNONE,      {CT}},
4263
4264 {"divdu",       XO(31,457,0,0), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4265 {"divdu.",      XO(31,457,0,1), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4266
4267 {"divwu",       XO(31,459,0,0), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4268 {"divwu.",      XO(31,459,0,1), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4269
4270 {"mtpmr",       X(31,462),      X_MASK, PPCPMR|PPCE300, PPCNONE,        {PMR, RS}},
4271
4272 {"mtmq",        XSPR(31,467,  0), XSPR_MASK, M601,      PPCNONE,        {RS}},
4273 {"mtxer",       XSPR(31,467,  1), XSPR_MASK, COM,       PPCNONE,        {RS}},
4274 {"mtlr",        XSPR(31,467,  8), XSPR_MASK, COM,       PPCNONE,        {RS}},
4275 {"mtctr",       XSPR(31,467,  9), XSPR_MASK, COM,       PPCNONE,        {RS}},
4276 {"mttid",       XSPR(31,467, 17), XSPR_MASK, POWER,     PPCNONE,        {RS}},
4277 {"mtdsisr",     XSPR(31,467, 18), XSPR_MASK, COM,       TITAN,          {RS}},
4278 {"mtdar",       XSPR(31,467, 19), XSPR_MASK, COM,       TITAN,          {RS}},
4279 {"mtrtcu",      XSPR(31,467, 20), XSPR_MASK, COM,       TITAN,          {RS}},
4280 {"mtrtcl",      XSPR(31,467, 21), XSPR_MASK, COM,       TITAN,          {RS}},
4281 {"mtdec",       XSPR(31,467, 22), XSPR_MASK, COM,       PPCNONE,        {RS}},
4282 {"mtsdr0",      XSPR(31,467, 24), XSPR_MASK, POWER,     PPCNONE,        {RS}},
4283 {"mtsdr1",      XSPR(31,467, 25), XSPR_MASK, COM,       TITAN,          {RS}},
4284 {"mtsrr0",      XSPR(31,467, 26), XSPR_MASK, COM,       PPCNONE,        {RS}},
4285 {"mtsrr1",      XSPR(31,467, 27), XSPR_MASK, COM,       PPCNONE,        {RS}},
4286 {"mtcfar",      XSPR(31,467, 28), XSPR_MASK, POWER6,    PPCNONE,        {RS}},
4287 {"mtpid",       XSPR(31,467, 48), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4288 {"mtdecar",     XSPR(31,467, 54), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4289 {"mtcsrr0",     XSPR(31,467, 58), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4290 {"mtcsrr1",     XSPR(31,467, 59), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4291 {"mtdear",      XSPR(31,467, 61), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4292 {"mtesr",       XSPR(31,467, 62), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4293 {"mtivpr",      XSPR(31,467, 63), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4294 {"mtcmpa",      XSPR(31,467,144), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4295 {"mtcmpb",      XSPR(31,467,145), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4296 {"mtcmpc",      XSPR(31,467,146), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4297 {"mtcmpd",      XSPR(31,467,147), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4298 {"mticr",       XSPR(31,467,148), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4299 {"mtder",       XSPR(31,467,149), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4300 {"mtcounta",    XSPR(31,467,150), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4301 {"mtcountb",    XSPR(31,467,151), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4302 {"mtcmpe",      XSPR(31,467,152), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4303 {"mtcmpf",      XSPR(31,467,153), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4304 {"mtcmpg",      XSPR(31,467,154), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4305 {"mtcmph",      XSPR(31,467,155), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4306 {"mtlctrl1",    XSPR(31,467,156), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4307 {"mtlctrl2",    XSPR(31,467,157), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4308 {"mtictrl",     XSPR(31,467,158), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4309 {"mtbar",       XSPR(31,467,159), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4310 {"mtvrsave",    XSPR(31,467,256), XSPR_MASK, PPCVEC,    PPCNONE,        {RS}},
4311 {"mtusprg0",    XSPR(31,467,256), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4312 {"mtsprg",      XSPR(31,467,256), XSPRG_MASK,PPC,       PPCNONE,        {SPRG, RS}},
4313 {"mtsprg0",     XSPR(31,467,272), XSPR_MASK, PPC,       PPCNONE,        {RS}},
4314 {"mtsprg1",     XSPR(31,467,273), XSPR_MASK, PPC,       PPCNONE,        {RS}},
4315 {"mtsprg2",     XSPR(31,467,274), XSPR_MASK, PPC,       PPCNONE,        {RS}},
4316 {"mtsprg3",     XSPR(31,467,275), XSPR_MASK, PPC,       PPCNONE,        {RS}},
4317 {"mtsprg4",     XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RS}},
4318 {"mtsprg5",     XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RS}},
4319 {"mtsprg6",     XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RS}},
4320 {"mtsprg7",     XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RS}},
4321 {"mtasr",       XSPR(31,467,280), XSPR_MASK, PPC64,     PPCNONE,        {RS}},
4322 {"mtear",       XSPR(31,467,282), XSPR_MASK, PPC,       TITAN,          {RS}},
4323 {"mttbl",       XSPR(31,467,284), XSPR_MASK, PPC,       PPCNONE,        {RS}},
4324 {"mttbu",       XSPR(31,467,285), XSPR_MASK, PPC,       PPCNONE,        {RS}},
4325 {"mtdbsr",      XSPR(31,467,304), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4326 {"mtdbcr0",     XSPR(31,467,308), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4327 {"mtdbcr1",     XSPR(31,467,309), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4328 {"mtdbcr2",     XSPR(31,467,310), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4329 {"mtiac1",      XSPR(31,467,312), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4330 {"mtiac2",      XSPR(31,467,313), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4331 {"mtiac3",      XSPR(31,467,314), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4332 {"mtiac4",      XSPR(31,467,315), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4333 {"mtdac1",      XSPR(31,467,316), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4334 {"mtdac2",      XSPR(31,467,317), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4335 {"mtdvc1",      XSPR(31,467,318), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4336 {"mtdvc2",      XSPR(31,467,319), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4337 {"mttsr",       XSPR(31,467,336), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4338 {"mttcr",       XSPR(31,467,340), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4339 {"mtivor0",     XSPR(31,467,400), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4340 {"mtivor1",     XSPR(31,467,401), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4341 {"mtivor2",     XSPR(31,467,402), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4342 {"mtivor3",     XSPR(31,467,403), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4343 {"mtivor4",     XSPR(31,467,404), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4344 {"mtivor5",     XSPR(31,467,405), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4345 {"mtivor6",     XSPR(31,467,406), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4346 {"mtivor7",     XSPR(31,467,407), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4347 {"mtivor8",     XSPR(31,467,408), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4348 {"mtivor9",     XSPR(31,467,409), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4349 {"mtivor10",    XSPR(31,467,410), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4350 {"mtivor11",    XSPR(31,467,411), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4351 {"mtivor12",    XSPR(31,467,412), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4352 {"mtivor13",    XSPR(31,467,413), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4353 {"mtivor14",    XSPR(31,467,414), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4354 {"mtivor15",    XSPR(31,467,415), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4355 {"mtspefscr",   XSPR(31,467,512), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
4356 {"mtbbear",     XSPR(31,467,513), XSPR_MASK, PPCBRLK,   PPCNONE,        {RS}},
4357 {"mtbbtar",     XSPR(31,467,514), XSPR_MASK, PPCBRLK,   PPCNONE,        {RS}},
4358 {"mtivor32",    XSPR(31,467,528), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
4359 {"mtibatu",     XSPR(31,467,528), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
4360 {"mtivor33",    XSPR(31,467,529), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
4361 {"mtibatl",     XSPR(31,467,529), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
4362 {"mtivor34",    XSPR(31,467,530), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
4363 {"mtivor35",    XSPR(31,467,531), XSPR_MASK, PPCPMR,    PPCNONE,        {RS}},
4364 {"mtdbatu",     XSPR(31,467,536), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
4365 {"mtdbatl",     XSPR(31,467,537), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
4366 {"mtmcsrr0",    XSPR(31,467,570), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RS}},
4367 {"mtmcsrr1",    XSPR(31,467,571), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RS}},
4368 {"mtmcsr",      XSPR(31,467,572), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RS}},
4369 {"mtivndx",     XSPR(31,467,880), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
4370 {"mtdvndx",     XSPR(31,467,881), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
4371 {"mtivlim",     XSPR(31,467,882), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
4372 {"mtdvlim",     XSPR(31,467,883), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
4373 {"mtclcsr",     XSPR(31,467,884), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
4374 {"mtccr1",      XSPR(31,467,888), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
4375 {"mtummcr0",    XSPR(31,467,936), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4376 {"mtupmc1",     XSPR(31,467,937), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4377 {"mtupmc2",     XSPR(31,467,938), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4378 {"mtusia",      XSPR(31,467,939), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4379 {"mtummcr1",    XSPR(31,467,940), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4380 {"mtupmc3",     XSPR(31,467,941), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4381 {"mtupmc4",     XSPR(31,467,942), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4382 {"mtzpr",       XSPR(31,467,944), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4383 {"mtpid",       XSPR(31,467,945), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4384 {"mtrmmucr",    XSPR(31,467,946), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
4385 {"mtccr0",      XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, PPCNONE,     {RS}},
4386 {"mtiac3",      XSPR(31,467,948), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4387 {"mtiac4",      XSPR(31,467,949), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4388 {"mtdvc1",      XSPR(31,467,950), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4389 {"mtdvc2",      XSPR(31,467,951), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4390 {"mtmmcr0",     XSPR(31,467,952), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4391 {"mtpmc1",      XSPR(31,467,953), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4392 {"mtsgr",       XSPR(31,467,953), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4393 {"mtdcwr",      XSPR(31,467,954), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4394 {"mtpmc2",      XSPR(31,467,954), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4395 {"mtsia",       XSPR(31,467,955), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4396 {"mtsler",      XSPR(31,467,955), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4397 {"mtmmcr1",     XSPR(31,467,956), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4398 {"mtsu0r",      XSPR(31,467,956), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4399 {"mtdbcr1",     XSPR(31,467,957), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4400 {"mtpmc3",      XSPR(31,467,957), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4401 {"mtpmc4",      XSPR(31,467,958), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4402 {"mticdbdr",    XSPR(31,467,979), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4403 {"mtesr",       XSPR(31,467,980), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4404 {"mtdear",      XSPR(31,467,981), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4405 {"mtevpr",      XSPR(31,467,982), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4406 {"mtcdbcr",     XSPR(31,467,983), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4407 {"mttsr",       XSPR(31,467,984), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4408 {"mttcr",       XSPR(31,467,986), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4409 {"mtpit",       XSPR(31,467,987), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4410 {"mttbhi",      XSPR(31,467,988), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4411 {"mttblo",      XSPR(31,467,989), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4412 {"mtsrr2",      XSPR(31,467,990), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4413 {"mtsrr3",      XSPR(31,467,991), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4414 {"mtdbsr",      XSPR(31,467,1008), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4415 {"mtdbdr",      XSPR(31,467,1011), XSPR_MASK, TITAN,    PPCNONE,        {RS}},
4416 {"mtdbcr0",     XSPR(31,467,1010), XSPR_MASK, PPC405,   PPCNONE,        {RS}},
4417 {"mtiac1",      XSPR(31,467,1012), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4418 {"mtiac2",      XSPR(31,467,1013), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4419 {"mtdac1",      XSPR(31,467,1014), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4420 {"mtdac2",      XSPR(31,467,1015), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4421 {"mtl2cr",      XSPR(31,467,1017), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
4422 {"mtdccr",      XSPR(31,467,1018), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4423 {"mticcr",      XSPR(31,467,1019), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4424 {"mtictc",      XSPR(31,467,1019), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
4425 {"mtpbl1",      XSPR(31,467,1020), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4426 {"mtthrm1",     XSPR(31,467,1020), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
4427 {"mtpbu1",      XSPR(31,467,1021), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4428 {"mtthrm2",     XSPR(31,467,1021), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
4429 {"mtpbl2",      XSPR(31,467,1022), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4430 {"mtthrm3",     XSPR(31,467,1022), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
4431 {"mtpbu2",      XSPR(31,467,1023), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4432 {"mtspr",       X(31,467),        X_MASK,    COM,       PPCNONE,        {SPR, RS}},
4433
4434 {"dcbi",        X(31,470),      XRT_MASK,    PPC,       PPCNONE,        {RA, RB}},
4435
4436 {"nand",        XRC(31,476,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
4437 {"nand.",       XRC(31,476,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
4438
4439 {"dsn",         X(31,483),      XRT_MASK,    E500MC,    PPCNONE,        {RA, RB}},
4440
4441 {"dcread",      X(31,486),      X_MASK,  PPC403|PPC440, PPCA2|PPC476,   {RT, RA, RB}},
4442
4443 {"icbtls",      X(31,486),      X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,  {CT, RA, RB}},
4444
4445 {"stvxl",       X(31,487),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
4446
4447 {"nabs",        XO(31,488,0,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4448 {"nabs.",       XO(31,488,0,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4449
4450 {"divd",        XO(31,489,0,0), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4451 {"divd.",       XO(31,489,0,1), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4452
4453 {"divw",        XO(31,491,0,0), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4454 {"divw.",       XO(31,491,0,1), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4455
4456 {"icbtlse",     X(31,494),      X_MASK,      PPCCHLK,   PPCNONE,        {CT, RA, RB}},
4457
4458 {"slbia",       X(31,498),      0xffffffff,  PPC64,     PPCNONE,        {0}},
4459
4460 {"cli",         X(31,502),      XRB_MASK,    POWER,     PPCNONE,        {RT, RA}},
4461
4462 {"popcntd",     X(31,506),      XRB_MASK, POWER7|PPCA2, PPCNONE,        {RA, RS}},
4463
4464 {"cmpb",        X(31,508),      X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {RA, RS, RB}},
4465
4466 {"mcrxr",       X(31,512), XRARB_MASK|(3<<21), COM,     POWER7,         {BF}},
4467
4468 {"lbdx",        X(31,515),      X_MASK,      E500MC,    PPCNONE,        {RT, RA, RB}},
4469
4470 {"bblels",      X(31,518),      X_MASK,      PPCBRLK,   PPCNONE,        {0}},
4471
4472 {"lvlx",        X(31,519),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
4473 {"lbfcmux",     APU(31,519,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4474
4475 {"subfco",      XO(31,8,1,0),   XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4476 {"sfo",         XO(31,8,1,0),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4477 {"subco",       XO(31,8,1,0),   XO_MASK,     PPCCOM,    PPCNONE,        {RT, RB, RA}},
4478 {"subfco.",     XO(31,8,1,1),   XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4479 {"sfo.",        XO(31,8,1,1),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4480 {"subco.",      XO(31,8,1,1),   XO_MASK,     PPCCOM,    PPCNONE,        {RT, RB, RA}},
4481
4482 {"addco",       XO(31,10,1,0),  XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4483 {"ao",          XO(31,10,1,0),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4484 {"addco.",      XO(31,10,1,1),  XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4485 {"ao.",         XO(31,10,1,1),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4486
4487 {"clcs",        X(31,531),      XRB_MASK,    M601,      PPCNONE,        {RT, RA}},
4488
4489 {"ldbrx",       X(31,532),      X_MASK, CELL|POWER7|PPCA2, PPCNONE,     {RT, RA0, RB}},
4490
4491 {"lswx",        X(31,533),      X_MASK,      PPCCOM,    E500|E500MC,    {RT, RAX, RBX}},
4492 {"lsx",         X(31,533),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
4493
4494 {"lwbrx",       X(31,534),      X_MASK,      PPCCOM,    PPCNONE,        {RT, RA0, RB}},
4495 {"lbrx",        X(31,534),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
4496
4497 {"lfsx",        X(31,535),      X_MASK,      COM,       PPCEFS,         {FRT, RA0, RB}},
4498
4499 {"srw",         XRC(31,536,0),  X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB}},
4500 {"sr",          XRC(31,536,0),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
4501 {"srw.",        XRC(31,536,1),  X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB}},
4502 {"sr.",         XRC(31,536,1),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
4503
4504 {"rrib",        XRC(31,537,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4505 {"rrib.",       XRC(31,537,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4506
4507 {"srd",         XRC(31,539,0),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
4508 {"srd.",        XRC(31,539,1),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
4509
4510 {"maskir",      XRC(31,541,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4511 {"maskir.",     XRC(31,541,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4512
4513 {"lhdx",        X(31,547),      X_MASK,      E500MC,    PPCNONE,        {RT, RA, RB}},
4514
4515 {"bbelr",       X(31,550),      X_MASK,      PPCBRLK,   PPCNONE,        {0}},
4516
4517 {"lvrx",        X(31,551),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
4518 {"lhfcmux",     APU(31,551,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4519
4520 {"subfo",       XO(31,40,1,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4521 {"subo",        XO(31,40,1,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
4522 {"subfo.",      XO(31,40,1,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4523 {"subo.",       XO(31,40,1,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
4524
4525 {"tlbsync",     X(31,566),      0xffffffff,  PPC,       PPCNONE,        {0}},
4526
4527 {"lfsux",       X(31,567),      X_MASK,      COM,       PPCEFS,         {FRT, RAS, RB}},
4528
4529 {"lwdx",        X(31,579),      X_MASK,      E500MC,    PPCNONE,        {RT, RA, RB}},
4530
4531 {"lwfcmux",     APU(31,583,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4532
4533 {"lxsdx",       X(31,588),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA, RB}},
4534
4535 {"mfsr",        X(31,595), XRB_MASK|(1<<20), COM,       NON32,          {RT, SR}},
4536
4537 {"lswi",        X(31,597),      X_MASK,      PPCCOM,    E500|E500MC,    {RT, RA0, NBI}},
4538 {"lsi",         X(31,597),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA0, NB}},
4539
4540 {"lwsync",      XSYNC(31,598,1), 0xffffffff, PPC,       E500,           {0}},
4541 {"ptesync",     XSYNC(31,598,2), 0xffffffff, PPC64,     PPCNONE,        {0}},
4542 {"sync",        X(31,598),      XSYNC_MASK,  PPCCOM,    BOOKE|PPC476,   {LS}},
4543 {"msync",       X(31,598),      0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}},
4544 {"sync",        X(31,598),      0xffffffff, BOOKE|PPC476, PPCNONE, {0}},
4545 {"lwsync",      X(31,598),      0xffffffff, E500,       PPCNONE,        {0}},
4546 {"dcs",         X(31,598),      0xffffffff,  PWRCOM,    PPCNONE,        {0}},
4547
4548 {"lfdx",        X(31,599),      X_MASK,      COM,       PPCEFS,         {FRT, RA0, RB}},
4549
4550 {"mffgpr",      XRC(31,607,0),  XRA_MASK,    POWER6,    POWER7,         {FRT, RB}},
4551 {"lfdepx",      X(31,607),      X_MASK,   E500MC|PPCA2, PPCNONE,        {FRT, RA, RB}},
4552
4553 {"lddx",        X(31,611),      X_MASK,      E500MC,    PPCNONE,        {RT, RA, RB}},
4554
4555 {"lqfcmux",     APU(31,615,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4556
4557 {"nego",        XO(31,104,1,0), XORB_MASK,   COM,       PPCNONE,        {RT, RA}},
4558 {"nego.",       XO(31,104,1,1), XORB_MASK,   COM,       PPCNONE,        {RT, RA}},
4559
4560 {"mulo",        XO(31,107,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4561 {"mulo.",       XO(31,107,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4562
4563 {"mfsri",       X(31,627),      X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
4564
4565 {"dclst",       X(31,630),      XRB_MASK,    M601,      PPCNONE,        {RS, RA}},
4566
4567 {"lfdux",       X(31,631),      X_MASK,      COM,       PPCEFS,         {FRT, RAS, RB}},
4568
4569 {"stbdx",       X(31,643),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
4570
4571 {"stvlx",       X(31,647),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
4572 {"stbfcmux",    APU(31,647,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4573
4574 {"subfeo",      XO(31,136,1,0), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4575 {"sfeo",        XO(31,136,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4576 {"subfeo.",     XO(31,136,1,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4577 {"sfeo.",       XO(31,136,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4578
4579 {"addeo",       XO(31,138,1,0), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4580 {"aeo",         XO(31,138,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4581 {"addeo.",      XO(31,138,1,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4582 {"aeo.",        XO(31,138,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4583
4584 {"mfsrin",      X(31,659),      XRA_MASK,    PPC,       NON32,          {RT, RB}},
4585
4586 {"stdbrx",      X(31,660),      X_MASK, CELL|POWER7|PPCA2, PPCNONE,     {RS, RA0, RB}},
4587
4588 {"stswx",       X(31,661),      X_MASK,      PPCCOM,    E500|E500MC,    {RS, RA0, RB}},
4589 {"stsx",        X(31,661),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
4590
4591 {"stwbrx",      X(31,662),      X_MASK,      PPCCOM,    PPCNONE,        {RS, RA0, RB}},
4592 {"stbrx",       X(31,662),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
4593
4594 {"stfsx",       X(31,663),      X_MASK,      COM,       PPCEFS,         {FRS, RA0, RB}},
4595
4596 {"srq",         XRC(31,664,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4597 {"srq.",        XRC(31,664,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4598
4599 {"sre",         XRC(31,665,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4600 {"sre.",        XRC(31,665,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4601
4602 {"sthdx",       X(31,675),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
4603
4604 {"stvrx",       X(31,679),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
4605 {"sthfcmux",    APU(31,679,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4606
4607 {"stbcx.",      XRC(31,694,1),  X_MASK,      POWER7,    PPCNONE,        {RS, RA0, RB}},
4608
4609 {"stfsux",      X(31,695),      X_MASK,      COM,       PPCEFS,         {FRS, RAS, RB}},
4610
4611 {"sriq",        XRC(31,696,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4612 {"sriq.",       XRC(31,696,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4613
4614 {"stwdx",       X(31,707),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
4615
4616 {"stwfcmux",    APU(31,711,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4617
4618 {"stxsdx",      X(31,716),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA, RB}},
4619
4620 {"subfzeo",     XO(31,200,1,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4621 {"sfzeo",       XO(31,200,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4622 {"subfzeo.",    XO(31,200,1,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4623 {"sfzeo.",      XO(31,200,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4624
4625 {"addzeo",      XO(31,202,1,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4626 {"azeo",        XO(31,202,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4627 {"addzeo.",     XO(31,202,1,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4628 {"azeo.",       XO(31,202,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4629
4630 {"stswi",       X(31,725),      X_MASK,      PPCCOM,    E500|E500MC,    {RS, RA0, NB}},
4631 {"stsi",        X(31,725),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, NB}},
4632
4633 {"sthcx.",      XRC(31,726,1),  X_MASK,      POWER7,    PPCNONE,        {RS, RA0, RB}},
4634
4635 {"stfdx",       X(31,727),      X_MASK,      COM,       PPCEFS,         {FRS, RA0, RB}},
4636
4637 {"srlq",        XRC(31,728,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4638 {"srlq.",       XRC(31,728,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4639
4640 {"sreq",        XRC(31,729,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4641 {"sreq.",       XRC(31,729,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4642
4643 {"mftgpr",      XRC(31,735,0),  XRA_MASK,    POWER6,    POWER7,         {RT, FRB}},
4644 {"stfdepx",     X(31,735),      X_MASK,   E500MC|PPCA2, PPCNONE,        {FRS, RA, RB}},
4645
4646 {"stddx",       X(31,739),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
4647
4648 {"stqfcmux",    APU(31,743,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4649
4650 {"subfmeo",     XO(31,232,1,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4651 {"sfmeo",       XO(31,232,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4652 {"subfmeo.",    XO(31,232,1,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4653 {"sfmeo.",      XO(31,232,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4654
4655 {"mulldo",      XO(31,233,1,0), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4656 {"mulldo.",     XO(31,233,1,1), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4657
4658 {"addmeo",      XO(31,234,1,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4659 {"ameo",        XO(31,234,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4660 {"addmeo.",     XO(31,234,1,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4661 {"ameo.",       XO(31,234,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4662
4663 {"mullwo",      XO(31,235,1,0), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4664 {"mulso",       XO(31,235,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4665 {"mullwo.",     XO(31,235,1,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4666 {"mulso.",      XO(31,235,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4667
4668 {"dcba",        X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, PPCNONE, {RA, RB}},
4669 {"dcbal",       XOPL(31,758,1), XRT_MASK,    E500MC,    PPCNONE,        {RA, RB}},
4670
4671 {"stfdux",      X(31,759),      X_MASK,      COM,       PPCEFS,         {FRS, RAS, RB}},
4672
4673 {"srliq",       XRC(31,760,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4674 {"srliq.",      XRC(31,760,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4675
4676 {"lvlxl",       X(31,775),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
4677 {"ldfcmux",     APU(31,775,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4678
4679 {"dozo",        XO(31,264,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4680 {"dozo.",       XO(31,264,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4681
4682 {"addo",        XO(31,266,1,0), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4683 {"caxo",        XO(31,266,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4684 {"addo.",       XO(31,266,1,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4685 {"caxo.",       XO(31,266,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4686
4687 {"lxvw4x",      X(31,780),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA, RB}},
4688
4689 {"tlbivax",     X(31,786),      XRT_MASK,  BOOKE|PPCA2|PPC476, PPCNONE, {RA, RB}},
4690
4691 {"lwzcix",      X(31,789),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
4692
4693 {"lhbrx",       X(31,790),      X_MASK,      COM,       PPCNONE,        {RT, RA0, RB}},
4694
4695 {"lfdpx",       X(31,791),      X_MASK,      POWER6,    POWER7,         {FRTp, RA, RB}},
4696 {"lfqx",        X(31,791),      X_MASK,      POWER2,    PPCNONE,        {FRT, RA, RB}},
4697
4698 {"sraw",        XRC(31,792,0),  X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB}},
4699 {"sra",         XRC(31,792,0),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
4700 {"sraw.",       XRC(31,792,1),  X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB}},
4701 {"sra.",        XRC(31,792,1),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
4702
4703 {"srad",        XRC(31,794,0),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
4704 {"srad.",       XRC(31,794,1),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
4705
4706 {"lfddx",       X(31,803),      X_MASK,      E500MC,    PPCNONE,        {FRT, RA, RB}},
4707
4708 {"lvrxl",       X(31,807),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
4709
4710 {"rac",         X(31,818),      X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
4711
4712 {"erativax",    X(31,819),      X_MASK,      PPCA2,     PPCNONE,        {RS, RA0, RB}},
4713
4714 {"lhzcix",      X(31,821),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
4715
4716 {"dss",         XDSS(31,822,0), XDSS_MASK,   PPCVEC,    PPCNONE,        {STRM}},
4717
4718 {"lfqux",       X(31,823),      X_MASK,      POWER2,    PPCNONE,        {FRT, RA, RB}},
4719
4720 {"srawi",       XRC(31,824,0),  X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH}},
4721 {"srai",        XRC(31,824,0),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH}},
4722 {"srawi.",      XRC(31,824,1),  X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH}},
4723 {"srai.",       XRC(31,824,1),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH}},
4724
4725 {"sradi",       XS(31,413,0),   XS_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6}},
4726 {"sradi.",      XS(31,413,1),   XS_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6}},
4727
4728 {"divo",        XO(31,331,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4729 {"divo.",       XO(31,331,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4730
4731 {"lxvd2x",      X(31,844),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA, RB}},
4732
4733 {"tlbsrx.",     XRC(31,850,1),  XRT_MASK,    PPCA2,     PPCNONE,        {RA, RB}},
4734
4735 {"slbmfev",     X(31,851),      XRA_MASK,    PPC64,     PPCNONE,        {RT, RB}},
4736
4737 {"lbzcix",      X(31,853),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
4738
4739 {"eieio",       X(31,854),      0xffffffff,  PPC,   BOOKE|PPCA2|PPC476, {0}},
4740 {"mbar",        X(31,854),      X_MASK, BOOKE|PPCA2|PPC476, PPCNONE,    {MO}},
4741 {"eieio",       XMBAR(31,854,1),0xffffffff,  E500,   PPCNONE,   {0}},
4742 {"eieio",       X(31,854),      0xffffffff, PPCA2|PPC476, PPCNONE,      {0}},
4743
4744 {"lfiwax",      X(31,855),      X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, RA0, RB}},
4745
4746 {"abso",        XO(31,360,1,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4747 {"abso.",       XO(31,360,1,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4748
4749 {"divso",       XO(31,363,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4750 {"divso.",      XO(31,363,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4751
4752 {"ldcix",       X(31,885),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
4753
4754 {"lfiwzx",      X(31,887),      X_MASK,   POWER7|PPCA2, PPCNONE,        {FRT, RA0, RB}},
4755
4756 {"stvlxl",      X(31,903),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
4757 {"stdfcmux",    APU(31,903,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4758
4759 {"divdeuo",     XO(31,393,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4760 {"divdeuo.",    XO(31,393,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4761 {"divweuo",     XO(31,395,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4762 {"divweuo.",    XO(31,395,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4763
4764 {"stxvw4x",     X(31,908),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA, RB}},
4765
4766 {"tlbsx",       XRC(31,914,0),  X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA, RB}},
4767 {"tlbsx.",      XRC(31,914,1),  X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA, RB}},
4768
4769 {"slbmfee",     X(31,915),      XRA_MASK,    PPC64,     PPCNONE,        {RT, RB}},
4770
4771 {"stwcix",      X(31,917),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
4772
4773 {"sthbrx",      X(31,918),      X_MASK,      COM,       PPCNONE,        {RS, RA0, RB}},
4774
4775 {"stfdpx",      X(31,919),      X_MASK,      POWER6,    POWER7,         {FRSp, RA, RB}},
4776 {"stfqx",       X(31,919),      X_MASK,      POWER2,    PPCNONE,        {FRS, RA, RB}},
4777
4778 {"sraq",        XRC(31,920,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4779 {"sraq.",       XRC(31,920,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4780
4781 {"srea",        XRC(31,921,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4782 {"srea.",       XRC(31,921,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4783
4784 {"extsh",       XRC(31,922,0),  XRB_MASK,    PPCCOM,    PPCNONE,        {RA, RS}},
4785 {"exts",        XRC(31,922,0),  XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
4786 {"extsh.",      XRC(31,922,1),  XRB_MASK,    PPCCOM,    PPCNONE,        {RA, RS}},
4787 {"exts.",       XRC(31,922,1),  XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
4788
4789 {"stfddx",      X(31,931),      X_MASK,      E500MC,    PPCNONE,        {FRS, RA, RB}},
4790
4791 {"wclrone",     XOPL2(31,934,2),XRT_MASK,    PPCA2,     PPCNONE,        {RA0, RB}},
4792 {"wclrall",     X(31,934),      XRARB_MASK,  PPCA2,     PPCNONE,        {L}},
4793 {"wclr",        X(31,934),      X_MASK,      PPCA2,     PPCNONE,        {L, RA0, RB}},
4794
4795 {"stvrxl",      X(31,935),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
4796
4797 {"divdeo",      XO(31,425,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4798 {"divdeo.",     XO(31,425,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4799 {"divweo",      XO(31,427,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4800 {"divweo.",     XO(31,427,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4801
4802 {"tlbrehi",     XTLB(31,946,0), XTLB_MASK,   PPC403,    PPCA2,          {RT, RA}},
4803 {"tlbrelo",     XTLB(31,946,1), XTLB_MASK,   PPC403,    PPCA2,          {RT, RA}},
4804 {"tlbre",       X(31,946),      X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
4805
4806 {"sthcix",      X(31,949),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
4807
4808 {"icswepx",     XRC(31,950,0),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA, RB}},
4809 {"icswepx.",    XRC(31,950,1),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA, RB}},
4810
4811 {"stfqux",      X(31,951),      X_MASK,      POWER2,    PPCNONE,        {FRS, RA, RB}},
4812
4813 {"sraiq",       XRC(31,952,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4814 {"sraiq.",      XRC(31,952,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4815
4816 {"extsb",       XRC(31,954,0),  XRB_MASK,    PPC,       PPCNONE,        {RA, RS}},
4817 {"extsb.",      XRC(31,954,1),  XRB_MASK,    PPC,       PPCNONE,        {RA, RS}},
4818
4819 {"iccci",       X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
4820 {"ici",         X(31,966),      XRARB_MASK,  PPCA2|PPC476, PPCNONE,     {CT}},
4821
4822 {"divduo",      XO(31,457,1,0), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4823 {"divduo.",     XO(31,457,1,1), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4824
4825 {"divwuo",      XO(31,459,1,0), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4826 {"divwuo.",     XO(31,459,1,1), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4827
4828 {"stxvd2x",     X(31,972),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA, RB}},
4829
4830 {"tlbld",       X(31,978),      XRTRA_MASK,  PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
4831 {"tlbwehi",     XTLB(31,978,0), XTLB_MASK,   PPC403,    PPCNONE,        {RT, RA}},
4832 {"tlbwelo",     XTLB(31,978,1), XTLB_MASK,   PPC403,    PPCNONE,        {RT, RA}},
4833 {"tlbwe",       X(31,978),      X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
4834
4835 {"stbcix",      X(31,981),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
4836
4837 {"icbi",        X(31,982),      XRT_MASK,    PPC,       PPCNONE,        {RA, RB}},
4838
4839 {"stfiwx",      X(31,983),      X_MASK,      PPC,       PPCEFS,         {FRS, RA0, RB}},
4840
4841 {"extsw",       XRC(31,986,0),  XRB_MASK,    PPC64,     PPCNONE,        {RA, RS}},
4842 {"extsw.",      XRC(31,986,1),  XRB_MASK,    PPC64,     PPCNONE,        {RA, RS}},
4843
4844 {"icbiep",      XRT(31,991,0),  XRT_MASK, E500MC|PPCA2, PPCNONE,        {RA, RB}},
4845
4846 {"icread",      X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, PPCNONE, {RA, RB}},
4847
4848 {"nabso",       XO(31,488,1,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4849 {"nabso.",      XO(31,488,1,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4850
4851 {"divdo",       XO(31,489,1,0), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4852 {"divdo.",      XO(31,489,1,1), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4853
4854 {"divwo",       XO(31,491,1,0), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4855 {"divwo.",      XO(31,491,1,1), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4856
4857 {"tlbli",       X(31,1010),     XRTRA_MASK,  PPC,       TITAN,          {RB}},
4858
4859 {"stdcix",      X(31,1013),     X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
4860
4861 {"dcbz",        X(31,1014),     XRT_MASK,    PPC,       PPCNONE,        {RA, RB}},
4862 {"dclz",        X(31,1014),     XRT_MASK,    PPC,       PPCNONE,        {RA, RB}},
4863
4864 {"dcbzep",      XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, PPCNONE,        {RA, RB}},
4865
4866 {"dcbzl",       XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476,       {RA, RB}},
4867
4868 {"cctpl",       0x7c210b78,     0xffffffff,  CELL,      PPCNONE,        {0}},
4869 {"cctpm",       0x7c421378,     0xffffffff,  CELL,      PPCNONE,        {0}},
4870 {"cctph",       0x7c631b78,     0xffffffff,  CELL,      PPCNONE,        {0}},
4871
4872 {"dstt",        XDSS(31,342,1), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
4873 {"dststt",      XDSS(31,374,1), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
4874 {"dssall",      XDSS(31,822,1), XDSS_MASK,   PPCVEC,    PPCNONE,        {0}},
4875
4876 {"db8cyc",      0x7f9ce378,     0xffffffff,  CELL,      PPCNONE,        {0}},
4877 {"db10cyc",     0x7fbdeb78,     0xffffffff,  CELL,      PPCNONE,        {0}},
4878 {"db12cyc",     0x7fdef378,     0xffffffff,  CELL,      PPCNONE,        {0}},
4879 {"db16cyc",     0x7ffffb78,     0xffffffff,  CELL,      PPCNONE,        {0}},
4880
4881 {"lwz",         OP(32),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RA0}},
4882 {"l",           OP(32),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
4883
4884 {"lwzu",        OP(33),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RAL}},
4885 {"lu",          OP(33),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
4886
4887 {"lbz",         OP(34),         OP_MASK,     COM,       PPCNONE,        {RT, D, RA0}},
4888
4889 {"lbzu",        OP(35),         OP_MASK,     COM,       PPCNONE,        {RT, D, RAL}},
4890
4891 {"stw",         OP(36),         OP_MASK,     PPCCOM,    PPCNONE,        {RS, D, RA0}},
4892 {"st",          OP(36),         OP_MASK,     PWRCOM,    PPCNONE,        {RS, D, RA0}},
4893
4894 {"stwu",        OP(37),         OP_MASK,     PPCCOM,    PPCNONE,        {RS, D, RAS}},
4895 {"stu",         OP(37),         OP_MASK,     PWRCOM,    PPCNONE,        {RS, D, RA0}},
4896
4897 {"stb",         OP(38),         OP_MASK,     COM,       PPCNONE,        {RS, D, RA0}},
4898
4899 {"stbu",        OP(39),         OP_MASK,     COM,       PPCNONE,        {RS, D, RAS}},
4900
4901 {"lhz",         OP(40),         OP_MASK,     COM,       PPCNONE,        {RT, D, RA0}},
4902
4903 {"lhzu",        OP(41),         OP_MASK,     COM,       PPCNONE,        {RT, D, RAL}},
4904
4905 {"lha",         OP(42),         OP_MASK,     COM,       PPCNONE,        {RT, D, RA0}},
4906
4907 {"lhau",        OP(43),         OP_MASK,     COM,       PPCNONE,        {RT, D, RAL}},
4908
4909 {"sth",         OP(44),         OP_MASK,     COM,       PPCNONE,        {RS, D, RA0}},
4910
4911 {"sthu",        OP(45),         OP_MASK,     COM,       PPCNONE,        {RS, D, RAS}},
4912
4913 {"lmw",         OP(46),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RAM}},
4914 {"lm",          OP(46),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
4915
4916 {"stmw",        OP(47),         OP_MASK,     PPCCOM,    PPCNONE,        {RS, D, RA0}},
4917 {"stm",         OP(47),         OP_MASK,     PWRCOM,    PPCNONE,        {RS, D, RA0}},
4918
4919 {"lfs",         OP(48),         OP_MASK,     COM,       PPCEFS,         {FRT, D, RA0}},
4920
4921 {"lfsu",        OP(49),         OP_MASK,     COM,       PPCEFS,         {FRT, D, RAS}},
4922
4923 {"lfd",         OP(50),         OP_MASK,     COM,       PPCEFS,         {FRT, D, RA0}},
4924
4925 {"lfdu",        OP(51),         OP_MASK,     COM,       PPCEFS,         {FRT, D, RAS}},
4926
4927 {"stfs",        OP(52),         OP_MASK,     COM,       PPCEFS,         {FRS, D, RA0}},
4928
4929 {"stfsu",       OP(53),         OP_MASK,     COM,       PPCEFS,         {FRS, D, RAS}},
4930
4931 {"stfd",        OP(54),         OP_MASK,     COM,       PPCEFS,         {FRS, D, RA0}},
4932
4933 {"stfdu",       OP(55),         OP_MASK,     COM,       PPCEFS,         {FRS, D, RAS}},
4934
4935 {"lq",          OP(56),         OP_MASK,     POWER4,    PPC476,         {RTQ, DQ, RAQ}},
4936 {"psq_l",       OP(56),         OP_MASK,     PPCPS,     PPCNONE,        {FRT,PSD,RA,PSW,PSQ}},
4937 {"lfq",         OP(56),         OP_MASK,     POWER2,    PPCNONE,        {FRT, D, RA0}},
4938
4939 {"lfdp",        OP(57),         OP_MASK,     POWER6,    POWER7,         {FRTp, D, RA0}},
4940 {"psq_lu",      OP(57),         OP_MASK,     PPCPS,     PPCNONE,        {FRT,PSD,RA,PSW,PSQ}},
4941 {"lfqu",        OP(57),         OP_MASK,     POWER2,    PPCNONE,        {FRT, D, RA0}},
4942
4943 {"ld",          DSO(58,0),      DS_MASK,     PPC64,     PPCNONE,        {RT, DS, RA0}},
4944 {"ldu",         DSO(58,1),      DS_MASK,     PPC64,     PPCNONE,        {RT, DS, RAL}},
4945 {"lwa",         DSO(58,2),      DS_MASK,     PPC64,     PPCNONE,        {RT, DS, RA0}},
4946
4947 {"dadd",        XRC(59,2,0),    X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4948 {"dadd.",       XRC(59,2,1),    X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4949
4950 {"dqua",        ZRC(59,3,0),    Z2_MASK,     POWER6,    PPCNONE,        {FRT,FRA,FRB,RMC}},
4951 {"dqua.",       ZRC(59,3,1),    Z2_MASK,     POWER6,    PPCNONE,        {FRT,FRA,FRB,RMC}},
4952
4953 {"fdivs",       A(59,18,0),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
4954 {"fdivs.",      A(59,18,1),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
4955
4956 {"fsubs",       A(59,20,0),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
4957 {"fsubs.",      A(59,20,1),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
4958
4959 {"fadds",       A(59,21,0),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
4960 {"fadds.",      A(59,21,1),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
4961
4962 {"fsqrts",      A(59,22,0),    AFRAFRC_MASK, PPC,       TITAN,          {FRT, FRB}},
4963 {"fsqrts.",     A(59,22,1),    AFRAFRC_MASK, PPC,       TITAN,          {FRT, FRB}},
4964
4965 {"fres",        A(59,24,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
4966 {"fres",        A(59,24,0),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
4967 {"fres.",       A(59,24,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
4968 {"fres.",       A(59,24,1),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
4969
4970 {"fmuls",       A(59,25,0),     AFRB_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRC}},
4971 {"fmuls.",      A(59,25,1),     AFRB_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRC}},
4972
4973 {"frsqrtes",    A(59,26,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
4974 {"frsqrtes",    A(59,26,0),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
4975 {"frsqrtes.",   A(59,26,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
4976 {"frsqrtes.",   A(59,26,1),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
4977
4978 {"fmsubs",      A(59,28,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
4979 {"fmsubs.",     A(59,28,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
4980
4981 {"fmadds",      A(59,29,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
4982 {"fmadds.",     A(59,29,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
4983
4984 {"fnmsubs",     A(59,30,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
4985 {"fnmsubs.",    A(59,30,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
4986
4987 {"fnmadds",     A(59,31,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
4988 {"fnmadds.",    A(59,31,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
4989
4990 {"dmul",        XRC(59,34,0),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4991 {"dmul.",       XRC(59,34,1),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4992
4993 {"drrnd",       ZRC(59,35,0),   Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
4994 {"drrnd.",      ZRC(59,35,1),   Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
4995
4996 {"dscli",       ZRC(59,66,0),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
4997 {"dscli.",      ZRC(59,66,1),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
4998
4999 {"dquai",       ZRC(59,67,0),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRT,FRB,RMC}},
5000 {"dquai.",      ZRC(59,67,1),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRT,FRB,RMC}},
5001
5002 {"dscri",       ZRC(59,98,0),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
5003 {"dscri.",      ZRC(59,98,1),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
5004
5005 {"drintx",      ZRC(59,99,0),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
5006 {"drintx.",     ZRC(59,99,1),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
5007
5008 {"dcmpo",       X(59,130),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
5009
5010 {"dtstex",      X(59,162),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
5011 {"dtstdc",      Z(59,194),      Z_MASK,      POWER6,    PPCNONE,        {BF,  FRA, DCM}},
5012 {"dtstdg",      Z(59,226),      Z_MASK,      POWER6,    PPCNONE,        {BF,  FRA, DGM}},
5013
5014 {"drintn",      ZRC(59,227,0),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
5015 {"drintn.",     ZRC(59,227,1),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
5016
5017 {"dctdp",       XRC(59,258,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5018 {"dctdp.",      XRC(59,258,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5019
5020 {"dctfix",      XRC(59,290,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5021 {"dctfix.",     XRC(59,290,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5022
5023 {"ddedpd",      XRC(59,322,0),  X_MASK,      POWER6,    PPCNONE,        {SP, FRT, FRB}},
5024 {"ddedpd.",     XRC(59,322,1),  X_MASK,      POWER6,    PPCNONE,        {SP, FRT, FRB}},
5025
5026 {"dxex",        XRC(59,354,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5027 {"dxex.",       XRC(59,354,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5028
5029 {"dsub",        XRC(59,514,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5030 {"dsub.",       XRC(59,514,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5031
5032 {"ddiv",        XRC(59,546,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5033 {"ddiv.",       XRC(59,546,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5034
5035 {"dcmpu",       X(59,642),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
5036
5037 {"dtstsf",      X(59,674),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
5038
5039 {"drsp",        XRC(59,770,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5040 {"drsp.",       XRC(59,770,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5041
5042 {"dcffix",      XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCNONE,        {FRT, FRB}},
5043 {"dcffix.",     XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCNONE,        {FRT, FRB}},
5044
5045 {"denbcd",      XRC(59,834,0),  X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
5046 {"denbcd.",     XRC(59,834,1),  X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
5047
5048 {"fcfids",      XRC(59,846,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5049 {"fcfids.",     XRC(59,846,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5050
5051 {"diex",        XRC(59,866,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5052 {"diex.",       XRC(59,866,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5053
5054 {"fcfidus",     XRC(59,974,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5055 {"fcfidus.",    XRC(59,974,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5056
5057 {"xxsldwi",     XX3(60,2),      XX3SHW_MASK, PPCVSX,    PPCNONE,        {XT6, XA6, XB6, SHW}},
5058 {"xxsel",       XX4(60,3),      XX4_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6, XC6}},
5059 {"xxspltd",     XX3(60,10),     XX3DM_MASK,  PPCVSX,    PPCNONE,        {XT6, XA6, XB6S, DMEX}},
5060 {"xxmrghd",     XX3(60,10),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5061 {"xxswapd",     XX3(60,10)|(2<<8), XX3_MASK, PPCVSX,    PPCNONE,        {XT6, XA6, XB6S}},
5062 {"xxmrgld",     XX3(60,10)|(3<<8), XX3_MASK, PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5063 {"xxpermdi",    XX3(60,10),     XX3DM_MASK,  PPCVSX,    PPCNONE,        {XT6, XA6, XB6, DM}},
5064 {"xxmrghw",     XX3(60,18),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5065 {"xsadddp",     XX3(60,32),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5066 {"xsmaddadp",   XX3(60,33),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5067 {"xscmpudp",    XX3(60,35),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
5068 {"xssubdp",     XX3(60,40),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5069 {"xsmaddmdp",   XX3(60,41),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5070 {"xscmpodp",    XX3(60,43),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
5071 {"xsmuldp",     XX3(60,48),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5072 {"xsmsubadp",   XX3(60,49),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5073 {"xxmrglw",     XX3(60,50),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5074 {"xsdivdp",     XX3(60,56),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5075 {"xsmsubmdp",   XX3(60,57),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5076 {"xstdivdp",    XX3(60,61),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
5077 {"xvaddsp",     XX3(60,64),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5078 {"xvmaddasp",   XX3(60,65),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5079 {"xvcmpeqsp",   XX3RC(60,67,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5080 {"xvcmpeqsp.",  XX3RC(60,67,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5081 {"xvsubsp",     XX3(60,72),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5082 {"xscvdpuxws",  XX2(60,72),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5083 {"xvmaddmsp",   XX3(60,73),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5084 {"xsrdpi",      XX2(60,73),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5085 {"xsrsqrtedp",  XX2(60,74),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5086 {"xssqrtdp",    XX2(60,75),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5087 {"xvcmpgtsp",   XX3RC(60,75,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5088 {"xvcmpgtsp.",  XX3RC(60,75,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5089 {"xvmulsp",     XX3(60,80),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5090 {"xvmsubasp",   XX3(60,81),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5091 {"xvcmpgesp",   XX3RC(60,83,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5092 {"xvcmpgesp.",  XX3RC(60,83,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5093 {"xvdivsp",     XX3(60,88),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5094 {"xscvdpsxws",  XX2(60,88),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5095 {"xvmsubmsp",   XX3(60,89),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5096 {"xsrdpiz",     XX2(60,89),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5097 {"xsredp",      XX2(60,90),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5098 {"xvtdivsp",    XX3(60,93),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
5099 {"xvadddp",     XX3(60,96),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5100 {"xvmaddadp",   XX3(60,97),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5101 {"xvcmpeqdp",   XX3RC(60,99,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5102 {"xvcmpeqdp.",  XX3RC(60,99,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5103 {"xvsubdp",     XX3(60,104),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5104 {"xvmaddmdp",   XX3(60,105),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5105 {"xsrdpip",     XX2(60,105),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5106 {"xstsqrtdp",   XX2(60,106),    XX2BF_MASK,  PPCVSX,    PPCNONE,        {BF, XB6}},
5107 {"xsrdpic",     XX2(60,107),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5108 {"xvcmpgtdp",   XX3RC(60,107,0), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5109 {"xvcmpgtdp.",  XX3RC(60,107,1), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5110 {"xvmuldp",     XX3(60,112),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5111 {"xvmsubadp",   XX3(60,113),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5112 {"xvcmpgedp",   XX3RC(60,115,0), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5113 {"xvcmpgedp.",  XX3RC(60,115,1), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5114 {"xvdivdp",     XX3(60,120),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5115 {"xvmsubmdp",   XX3(60,121),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5116 {"xsrdpim",     XX2(60,121),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5117 {"xvtdivdp",    XX3(60,125),    XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
5118 {"xxland",      XX3(60,130),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5119 {"xvcvspuxws",  XX2(60,136),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5120 {"xvrspi",      XX2(60,137),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5121 {"xxlandc",     XX3(60,138),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5122 {"xvrsqrtesp",  XX2(60,138),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5123 {"xvsqrtsp",    XX2(60,139),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5124 {"xxlor",       XX3(60,146),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5125 {"xvcvspsxws",  XX2(60,152),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5126 {"xvrspiz",     XX2(60,153),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5127 {"xxlxor",      XX3(60,154),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5128 {"xvresp",      XX2(60,154),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5129 {"xsmaxdp",     XX3(60,160),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5130 {"xsnmaddadp",  XX3(60,161),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5131 {"xxlnor",      XX3(60,162),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5132 {"xxspltw",     XX2(60,164),    XX2UIM_MASK, PPCVSX,    PPCNONE,        {XT6, XB6, UIM}},
5133 {"xsmindp",     XX3(60,168),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5134 {"xvcvuxwsp",   XX2(60,168),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5135 {"xsnmaddmdp",  XX3(60,169),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5136 {"xvrspip",     XX2(60,169),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5137 {"xvtsqrtsp",   XX2(60,170),    XX2BF_MASK,  PPCVSX,    PPCNONE,        {BF, XB6}},
5138 {"xvrspic",     XX2(60,171),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5139 {"xscpsgndp",   XX3(60,176),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5140 {"xsnmsubadp",  XX3(60,177),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5141 {"xvcvsxwsp",   XX2(60,184),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5142 {"xsnmsubmdp",  XX3(60,185),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5143 {"xvrspim",     XX2(60,185),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5144 {"xvmaxsp",     XX3(60,192),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5145 {"xvnmaddasp",  XX3(60,193),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5146 {"xvminsp",     XX3(60,200),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5147 {"xvcvdpuxws",  XX2(60,200),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5148 {"xvnmaddmsp",  XX3(60,201),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5149 {"xvrdpi",      XX2(60,201),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5150 {"xvrsqrtedp",  XX2(60,202),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5151 {"xvsqrtdp",    XX2(60,203),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5152 {"xvmovsp",     XX3(60,208),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6S}},
5153 {"xvcpsgnsp",   XX3(60,208),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5154 {"xvnmsubasp",  XX3(60,209),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5155 {"xvcvdpsxws",  XX2(60,216),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5156 {"xvnmsubmsp",  XX3(60,217),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5157 {"xvrdpiz",     XX2(60,217),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5158 {"xvredp",      XX2(60,218),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5159 {"xvmaxdp",     XX3(60,224),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5160 {"xvnmaddadp",  XX3(60,225),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5161 {"xvmindp",     XX3(60,232),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5162 {"xvnmaddmdp",  XX3(60,233),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5163 {"xvcvuxwdp",   XX2(60,232),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5164 {"xvrdpip",     XX2(60,233),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5165 {"xvtsqrtdp",   XX2(60,234),    XX2BF_MASK,  PPCVSX,    PPCNONE,        {BF, XB6}},
5166 {"xvrdpic",     XX2(60,235),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5167 {"xvmovdp",     XX3(60,240),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6S}},
5168 {"xvcpsgndp",   XX3(60,240),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5169 {"xvnmsubadp",  XX3(60,241),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5170 {"xvcvsxwdp",   XX2(60,248),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5171 {"xvnmsubmdp",  XX3(60,249),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5172 {"xvrdpim",     XX2(60,249),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5173 {"xscvdpsp",    XX2(60,265),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5174 {"xscvdpuxds",  XX2(60,328),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5175 {"xscvspdp",    XX2(60,329),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5176 {"xscvdpsxds",  XX2(60,344),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5177 {"xsabsdp",     XX2(60,345),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5178 {"xscvuxddp",   XX2(60,360),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5179 {"xsnabsdp",    XX2(60,361),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5180 {"xscvsxddp",   XX2(60,376),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5181 {"xsnegdp",     XX2(60,377),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5182 {"xvcvspuxds",  XX2(60,392),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5183 {"xvcvdpsp",    XX2(60,393),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5184 {"xvcvspsxds",  XX2(60,408),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5185 {"xvabssp",     XX2(60,409),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5186 {"xvcvuxdsp",   XX2(60,424),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5187 {"xvnabssp",    XX2(60,425),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5188 {"xvcvsxdsp",   XX2(60,440),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5189 {"xvnegsp",     XX2(60,441),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5190 {"xvcvdpuxds",  XX2(60,456),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5191 {"xvcvspdp",    XX2(60,457),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5192 {"xvcvdpsxds",  XX2(60,472),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5193 {"xvabsdp",     XX2(60,473),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5194 {"xvcvuxddp",   XX2(60,488),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5195 {"xvnabsdp",    XX2(60,489),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5196 {"xvcvsxddp",   XX2(60,504),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5197 {"xvnegdp",     XX2(60,505),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5198
5199 {"psq_st",      OP(60),         OP_MASK,     PPCPS,     PPCNONE,        {FRS,PSD,RA,PSW,PSQ}},
5200 {"stfq",        OP(60),         OP_MASK,     POWER2,    PPCNONE,        {FRS, D, RA}},
5201
5202 {"stfdp",       OP(61),         OP_MASK,     POWER6,    POWER7,         {FRSp, D, RA0}},
5203 {"psq_stu",     OP(61),         OP_MASK,     PPCPS,     PPCNONE,        {FRS,PSD,RA,PSW,PSQ}},
5204 {"stfqu",       OP(61),         OP_MASK,     POWER2,    PPCNONE,        {FRS, D, RA}},
5205
5206 {"std",         DSO(62,0),      DS_MASK,     PPC64,     PPCNONE,        {RS, DS, RA0}},
5207 {"stdu",        DSO(62,1),      DS_MASK,     PPC64,     PPCNONE,        {RS, DS, RAS}},
5208 {"stq",         DSO(62,2),      DS_MASK,     POWER4,    PPC476,         {RSQ, DS, RA0}},
5209
5210 {"fcmpu",       X(63,0),     X_MASK|(3<<21), COM,       PPCEFS,         {BF, FRA, FRB}},
5211
5212 {"daddq",       XRC(63,2,0),    X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
5213 {"daddq.",      XRC(63,2,1),    X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
5214
5215 {"dquaq",       ZRC(63,3,0),    Z2_MASK,     POWER6,    PPCNONE,        {FRTp, FRAp, FRBp, RMC}},
5216 {"dquaq.",      ZRC(63,3,1),    Z2_MASK,     POWER6,    PPCNONE,        {FRTp, FRAp, FRBp, RMC}},
5217
5218 {"fcpsgn",      XRC(63,8,0),    X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, FRA, FRB}},
5219 {"fcpsgn.",     XRC(63,8,1),    X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, FRA, FRB}},
5220
5221 {"frsp",        XRC(63,12,0),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
5222 {"frsp.",       XRC(63,12,1),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
5223
5224 {"fctiw",       XRC(63,14,0),   XRA_MASK,    PPCCOM,    PPCEFS,         {FRT, FRB}},
5225 {"fcir",        XRC(63,14,0),   XRA_MASK,    PWR2COM,   PPCNONE,        {FRT, FRB}},
5226 {"fctiw.",      XRC(63,14,1),   XRA_MASK,    PPCCOM,    PPCEFS,         {FRT, FRB}},
5227 {"fcir.",       XRC(63,14,1),   XRA_MASK,    PWR2COM,   PPCNONE,        {FRT, FRB}},
5228
5229 {"fctiwz",      XRC(63,15,0),   XRA_MASK,    PPCCOM,    PPCEFS,         {FRT, FRB}},
5230 {"fcirz",       XRC(63,15,0),   XRA_MASK,    PWR2COM,   PPCNONE,        {FRT, FRB}},
5231 {"fctiwz.",     XRC(63,15,1),   XRA_MASK,    PPCCOM,    PPCEFS,         {FRT, FRB}},
5232 {"fcirz.",      XRC(63,15,1),   XRA_MASK,    PWR2COM,   PPCNONE,        {FRT, FRB}},
5233
5234 {"fdiv",        A(63,18,0),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
5235 {"fd",          A(63,18,0),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5236 {"fdiv.",       A(63,18,1),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
5237 {"fd.",         A(63,18,1),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5238
5239 {"fsub",        A(63,20,0),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
5240 {"fs",          A(63,20,0),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5241 {"fsub.",       A(63,20,1),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
5242 {"fs.",         A(63,20,1),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5243
5244 {"fadd",        A(63,21,0),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
5245 {"fa",          A(63,21,0),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5246 {"fadd.",       A(63,21,1),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
5247 {"fa.",         A(63,21,1),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5248
5249 {"fsqrt",       A(63,22,0),    AFRAFRC_MASK, PPCPWR2,   TITAN,          {FRT, FRB}},
5250 {"fsqrt.",      A(63,22,1),    AFRAFRC_MASK, PPCPWR2,   TITAN,          {FRT, FRB}},
5251
5252 {"fsel",        A(63,23,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5253 {"fsel.",       A(63,23,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5254
5255 {"fre",         A(63,24,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
5256 {"fre",         A(63,24,0),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
5257 {"fre.",        A(63,24,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
5258 {"fre.",        A(63,24,1),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
5259
5260 {"fmul",        A(63,25,0),     AFRB_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRC}},
5261 {"fm",          A(63,25,0),     AFRB_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRC}},
5262 {"fmul.",       A(63,25,1),     AFRB_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRC}},
5263 {"fm.",         A(63,25,1),     AFRB_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRC}},
5264
5265 {"frsqrte",     A(63,26,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
5266 {"frsqrte",     A(63,26,0),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
5267 {"frsqrte.",    A(63,26,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
5268 {"frsqrte.",    A(63,26,1),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
5269
5270 {"fmsub",       A(63,28,0),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
5271 {"fms",         A(63,28,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5272 {"fmsub.",      A(63,28,1),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
5273 {"fms.",        A(63,28,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5274
5275 {"fmadd",       A(63,29,0),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
5276 {"fma",         A(63,29,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5277 {"fmadd.",      A(63,29,1),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
5278 {"fma.",        A(63,29,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5279
5280 {"fnmsub",      A(63,30,0),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
5281 {"fnms",        A(63,30,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5282 {"fnmsub.",     A(63,30,1),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
5283 {"fnms.",       A(63,30,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5284
5285 {"fnmadd",      A(63,31,0),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
5286 {"fnma",        A(63,31,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5287 {"fnmadd.",     A(63,31,1),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
5288 {"fnma.",       A(63,31,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5289
5290 {"fcmpo",       X(63,32),    X_MASK|(3<<21), COM,       PPCEFS,         {BF, FRA, FRB}},
5291
5292 {"dmulq",       XRC(63,34,0),   X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
5293 {"dmulq.",      XRC(63,34,1),   X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
5294
5295 {"drrndq",      ZRC(63,35,0),   Z2_MASK,     POWER6,    PPCNONE,        {FRTp, FRA, FRBp, RMC}},
5296 {"drrndq.",     ZRC(63,35,1),   Z2_MASK,     POWER6,    PPCNONE,        {FRTp, FRA, FRBp, RMC}},
5297
5298 {"mtfsb1",      XRC(63,38,0),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
5299 {"mtfsb1.",     XRC(63,38,1),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
5300
5301 {"fneg",        XRC(63,40,0),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
5302 {"fneg.",       XRC(63,40,1),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
5303
5304 {"mcrfs",      X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCNONE,        {BF, BFA}},
5305
5306 {"dscliq",      ZRC(63,66,0),   Z_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, SH16}},
5307 {"dscliq.",     ZRC(63,66,1),   Z_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, SH16}},
5308
5309 {"dquaiq",      ZRC(63,67,0),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRTp, FRBp, RMC}},
5310 {"dquaiq.",     ZRC(63,67,1),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRTp, FRBp, RMC}},
5311
5312 {"mtfsb0",      XRC(63,70,0),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
5313 {"mtfsb0.",     XRC(63,70,1),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
5314
5315 {"fmr",         XRC(63,72,0),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
5316 {"fmr.",        XRC(63,72,1),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
5317
5318 {"dscriq",      ZRC(63,98,0),   Z_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, SH16}},
5319 {"dscriq.",     ZRC(63,98,1),   Z_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, SH16}},
5320
5321 {"drintxq",     ZRC(63,99,0),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRTp, FRBp, RMC}},
5322 {"drintxq.",    ZRC(63,99,1),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRTp, FRBp, RMC}},
5323
5324 {"ftdiv",       X(63,128),   X_MASK|(3<<21), POWER7,    PPCNONE,        {BF, FRA, FRB}},
5325
5326 {"dcmpoq",      X(63,130),      X_MASK,      POWER6,    PPCNONE,        {BF, FRAp, FRBp}},
5327
5328 {"mtfsfi",  XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
5329 {"mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
5330 {"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
5331 {"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
5332
5333 {"fnabs",       XRC(63,136,0),  XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
5334 {"fnabs.",      XRC(63,136,1),  XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
5335
5336 {"fctiwu",      XRC(63,142,0),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
5337 {"fctiwu.",     XRC(63,142,1),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
5338 {"fctiwuz",     XRC(63,143,0),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
5339 {"fctiwuz.",    XRC(63,143,1),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
5340
5341 {"ftsqrt",      X(63,160), X_MASK|(3<<21|FRA_MASK), POWER7, PPCNONE,    {BF, FRB}},
5342
5343 {"dtstexq",     X(63,162),      X_MASK,      POWER6,    PPCNONE,        {BF, FRAp, FRBp}},
5344 {"dtstdcq",     Z(63,194),      Z_MASK,      POWER6,    PPCNONE,        {BF, FRAp, DCM}},
5345 {"dtstdgq",     Z(63,226),      Z_MASK,      POWER6,    PPCNONE,        {BF, FRAp, DGM}},
5346
5347 {"drintnq",     ZRC(63,227,0),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRTp, FRBp, RMC}},
5348 {"drintnq.",    ZRC(63,227,1),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRTp, FRBp, RMC}},
5349
5350 {"dctqpq",      XRC(63,258,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRB}},
5351 {"dctqpq.",     XRC(63,258,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRB}},
5352
5353 {"fabs",        XRC(63,264,0),  XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
5354 {"fabs.",       XRC(63,264,1),  XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
5355
5356 {"dctfixq",     XRC(63,290,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRBp}},
5357 {"dctfixq.",    XRC(63,290,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRBp}},
5358
5359 {"ddedpdq",     XRC(63,322,0),  X_MASK,      POWER6,    PPCNONE,        {SP, FRTp, FRBp}},
5360 {"ddedpdq.",    XRC(63,322,1),  X_MASK,      POWER6,    PPCNONE,        {SP, FRTp, FRBp}},
5361
5362 {"dxexq",       XRC(63,354,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRBp}},
5363 {"dxexq.",      XRC(63,354,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRBp}},
5364
5365 {"frin",        XRC(63,392,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5366 {"frin.",       XRC(63,392,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5367 {"friz",        XRC(63,424,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5368 {"friz.",       XRC(63,424,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5369 {"frip",        XRC(63,456,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5370 {"frip.",       XRC(63,456,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5371 {"frim",        XRC(63,488,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5372 {"frim.",       XRC(63,488,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5373
5374 {"dsubq",       XRC(63,514,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
5375 {"dsubq.",      XRC(63,514,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
5376
5377 {"ddivq",       XRC(63,546,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
5378 {"ddivq.",      XRC(63,546,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
5379
5380 {"mffs",        XRC(63,583,0),  XRARB_MASK,  COM,       PPCEFS,         {FRT}},
5381 {"mffs.",       XRC(63,583,1),  XRARB_MASK,  COM,       PPCEFS,         {FRT}},
5382
5383 {"dcmpuq",      X(63,642),      X_MASK,      POWER6,    PPCNONE,        {BF, FRAp, FRBp}},
5384
5385 {"dtstsfq",     X(63,674),      X_MASK,      POWER6,    PPCNONE,        {BF, FRA, FRBp}},
5386
5387 {"mtfsf",       XFL(63,711,0),  XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
5388 {"mtfsf",       XFL(63,711,0),  XFL_MASK,    COM, POWER6|PPCA2|PPC476|PPCEFS,   {FLM, FRB}},
5389 {"mtfsf.",      XFL(63,711,1),  XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
5390 {"mtfsf.",      XFL(63,711,1),  XFL_MASK,    COM, POWER6|PPCA2|PPC476|PPCEFS,   {FLM, FRB}},
5391
5392 {"drdpq",       XRC(63,770,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRBp}},
5393 {"drdpq.",      XRC(63,770,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRBp}},
5394
5395 {"dcffixq",     XRC(63,802,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRB}},
5396 {"dcffixq.",    XRC(63,802,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRB}},
5397
5398 {"fctid",       XRC(63,814,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
5399 {"fctid",       XRC(63,814,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
5400 {"fctid.",      XRC(63,814,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
5401 {"fctid.",      XRC(63,814,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
5402
5403 {"fctidz",      XRC(63,815,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
5404 {"fctidz",      XRC(63,815,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
5405 {"fctidz.",     XRC(63,815,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
5406 {"fctidz.",     XRC(63,815,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
5407
5408 {"denbcdq",     XRC(63,834,0),  X_MASK,      POWER6,    PPCNONE,        {S, FRTp, FRBp}},
5409 {"denbcdq.",    XRC(63,834,1),  X_MASK,      POWER6,    PPCNONE,        {S, FRTp, FRBp}},
5410
5411 {"fcfid",       XRC(63,846,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
5412 {"fcfid",       XRC(63,846,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
5413 {"fcfid.",      XRC(63,846,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
5414 {"fcfid.",      XRC(63,846,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
5415
5416 {"diexq",       XRC(63,866,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRA, FRBp}},
5417 {"diexq.",      XRC(63,866,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRA, FRBp}},
5418
5419 {"fctidu",      XRC(63,942,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5420 {"fctidu.",     XRC(63,942,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5421
5422 {"fctiduz",     XRC(63,943,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5423 {"fctiduz.",    XRC(63,943,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5424
5425 {"fcfidu",      XRC(63,974,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5426 {"fcfidu.",     XRC(63,974,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5427 };
5428
5429 const int powerpc_num_opcodes =
5430   sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
5431 \f
5432 /* The macro table.  This is only used by the assembler.  */
5433
5434 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
5435    when x=0; 32-x when x is between 1 and 31; are negative if x is
5436    negative; and are 32 or more otherwise.  This is what you want
5437    when, for instance, you are emulating a right shift by a
5438    rotate-left-and-mask, because the underlying instructions support
5439    shifts of size 0 but not shifts of size 32.  By comparison, when
5440    extracting x bits from some word you want to use just 32-x, because
5441    the underlying instructions don't support extracting 0 bits but do
5442    support extracting the whole word (32 bits in this case).  */
5443
5444 const struct powerpc_macro powerpc_macros[] = {
5445 {"extldi",   4, PPC64,  "rldicr %0,%1,%3,(%2)-1"},
5446 {"extldi.",  4, PPC64,  "rldicr. %0,%1,%3,(%2)-1"},
5447 {"extrdi",   4, PPC64,  "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
5448 {"extrdi.",  4, PPC64,  "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
5449 {"insrdi",   4, PPC64,  "rldimi %0,%1,64-((%2)+(%3)),%3"},
5450 {"insrdi.",  4, PPC64,  "rldimi. %0,%1,64-((%2)+(%3)),%3"},
5451 {"rotrdi",   3, PPC64,  "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
5452 {"rotrdi.",  3, PPC64,  "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
5453 {"sldi",     3, PPC64,  "rldicr %0,%1,%2,63-(%2)"},
5454 {"sldi.",    3, PPC64,  "rldicr. %0,%1,%2,63-(%2)"},
5455 {"srdi",     3, PPC64,  "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
5456 {"srdi.",    3, PPC64,  "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
5457 {"clrrdi",   3, PPC64,  "rldicr %0,%1,0,63-(%2)"},
5458 {"clrrdi.",  3, PPC64,  "rldicr. %0,%1,0,63-(%2)"},
5459 {"clrlsldi", 4, PPC64,  "rldic %0,%1,%3,(%2)-(%3)"},
5460 {"clrlsldi.",4, PPC64,  "rldic. %0,%1,%3,(%2)-(%3)"},
5461
5462 {"extlwi",   4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
5463 {"extlwi.",  4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
5464 {"extrwi",   4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
5465 {"extrwi.",  4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
5466 {"inslwi",   4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
5467 {"inslwi.",  4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
5468 {"insrwi",   4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
5469 {"insrwi.",  4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
5470 {"rotrwi",   3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
5471 {"rotrwi.",  3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
5472 {"slwi",     3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
5473 {"sli",      3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
5474 {"slwi.",    3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
5475 {"sli.",     3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
5476 {"srwi",     3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5477 {"sri",      3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5478 {"srwi.",    3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5479 {"sri.",     3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5480 {"clrrwi",   3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
5481 {"clrrwi.",  3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
5482 {"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
5483 {"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
5484 };
5485
5486 const int powerpc_num_macros =
5487   sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);