opcodes/i386-init.h

   1 /* This file is automatically generated by i386-gen.  Do not edit!  */
   2 /* Copyright 2007  Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21 #define CPU_UNKNOWN_FLAGS \
  22   { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,  \
  23       1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
  24
  25 #define CPU_GENERIC32_FLAGS \
  26   { { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
  27       0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
  28
  29 #define CPU_GENERIC64_FLAGS \
  30   { { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,  \
  31       0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
  32
  33 #define CPU_NONE_FLAGS \
  34   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
  35       0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
  36
  37 #define CPU_I186_FLAGS \
  38   { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
  39       0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
  40
  41 #define CPU_I286_FLAGS \
  42   { { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
  43       0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
  44
  45 #define CPU_I386_FLAGS \
  46   { { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
  47       0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
  48
  49 #define CPU_I486_FLAGS \
  50   { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
  51       0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
  52
  53 #define CPU_I586_FLAGS \
  54   { { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
  55       0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
  56
  57 #define CPU_I686_FLAGS \
  58   { { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
  59       0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
  60
  61 #define CPU_P2_FLAGS \
  62   { { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
  63       0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
  64
  65 #define CPU_P3_FLAGS \
  66   { { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,  \
  67       0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
  68
  69 #define CPU_P4_FLAGS \
  70   { { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,  \
  71       0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
  72
  73 #define CPU_NOCONA_FLAGS \
  74   { { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0,  \
  75       0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
  76
  77 #define CPU_CORE_FLAGS \
  78   { { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0,  \
  79       0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
  80
  81 #define CPU_CORE2_FLAGS \
  82   { { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0,  \
  83       1, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
  84
  85 #define CPU_K6_FLAGS \
  86   { { 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
  87       0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
  88
  89 #define CPU_K6_2_FLAGS \
  90   { { 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,  \
  91       0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
  92
  93 #define CPU_ATHLON_FLAGS \
  94   { { 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0,  \
  95       0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
  96
  97 #define CPU_K8_FLAGS \
  98   { { 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,  \
  99       0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
 100
 101 #define CPU_AMDFAM10_FLAGS \
 102   { { 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0,  \
 103       0, 1, 1, 0, 0, 0, 1, 0, 0, 0 } }
 104
 105 #define CPU_MMX_FLAGS \
 106   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
 107       0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 108
 109 #define CPU_SSE_FLAGS \
 110   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,  \
 111       0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 112
 113 #define CPU_SSE2_FLAGS \
 114   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,  \
 115       0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 116
 117 #define CPU_SSE3_FLAGS \
 118   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0,  \
 119       0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 120
 121 #define CPU_SSSE3_FLAGS \
 122   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0,  \
 123       1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 124
 125 #define CPU_SSE4_1_FLAGS \
 126   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0,  \
 127       1, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
 128
 129 #define CPU_SSE4_2_FLAGS \
 130   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0,  \
 131       1, 0, 0, 1, 1, 0, 0, 0, 0, 0 } }
 132
 133 #define CPU_3DNOW_FLAGS \
 134   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,  \
 135       0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 136
 137 #define CPU_3DNOWA_FLAGS \
 138   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0,  \
 139       0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 140
 141 #define CPU_PADLOCK_FLAGS \
 142   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,  \
 143       0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 144
 145 #define CPU_SVME_FLAGS \
 146   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,  \
 147       0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 148
 149 #define CPU_SSE4A_FLAGS \
 150   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0,  \
 151       0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
 152
 153 #define CPU_ABM_FLAGS \
 154   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  \
 155       0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
 156
 157 #define CPU_SSE5_FLAGS \
 158   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0,  \
 159       0, 1, 1, 0, 0, 1, 0, 0, 0, 0 } }
 160
 161
 162 #define OPERAND_TYPE_NONE \
 163   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 164       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 165
 166 #define OPERAND_TYPE_REG8 \
 167   { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 168       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 169
 170 #define OPERAND_TYPE_REG16 \
 171   { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 172       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 173
 174 #define OPERAND_TYPE_REG32 \
 175   { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 176       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 177
 178 #define OPERAND_TYPE_REG64 \
 179   { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 180       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 181
 182 #define OPERAND_TYPE_IMM1 \
 183   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 184       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 185
 186 #define OPERAND_TYPE_IMM8 \
 187   { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 188       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 189
 190 #define OPERAND_TYPE_IMM8S \
 191   { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 192       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 193
 194 #define OPERAND_TYPE_IMM16 \
 195   { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 196       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 197
 198 #define OPERAND_TYPE_IMM32 \
 199   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 200       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 201
 202 #define OPERAND_TYPE_IMM32S \
 203   { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 204       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 205
 206 #define OPERAND_TYPE_IMM64 \
 207   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 208       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 209
 210 #define OPERAND_TYPE_BASEINDEX \
 211   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
 212       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 213
 214 #define OPERAND_TYPE_DISP8 \
 215   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
 216       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 217
 218 #define OPERAND_TYPE_DISP16 \
 219   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
 220       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 221
 222 #define OPERAND_TYPE_DISP32 \
 223   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
 224       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 225
 226 #define OPERAND_TYPE_DISP32S \
 227   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
 228       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 229
 230 #define OPERAND_TYPE_DISP64 \
 231   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
 232       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 233
 234 #define OPERAND_TYPE_INOUTPORTREG \
 235   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
 236       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 237
 238 #define OPERAND_TYPE_SHIFTCOUNT \
 239   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
 240       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 241
 242 #define OPERAND_TYPE_CONTROL \
 243   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
 244       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 245
 246 #define OPERAND_TYPE_TEST \
 247   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 248       0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 249
 250 #define OPERAND_TYPE_DEBUG \
 251   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 252       0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 253
 254 #define OPERAND_TYPE_FLOATREG \
 255   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 256       0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 257
 258 #define OPERAND_TYPE_FLOATACC \
 259   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 260       0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
 261
 262 #define OPERAND_TYPE_SREG2 \
 263   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 264       0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
 265
 266 #define OPERAND_TYPE_SREG3 \
 267   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 268       0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
 269
 270 #define OPERAND_TYPE_ACC \
 271   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 272       0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
 273
 274 #define OPERAND_TYPE_JUMPABSOLUTE \
 275   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 276       0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }
 277
 278 #define OPERAND_TYPE_REGMMX \
 279   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 280       0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
 281
 282 #define OPERAND_TYPE_REGXMM \
 283   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 284       0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }
 285
 286 #define OPERAND_TYPE_ESSEG \
 287   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 288       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }
 289
 290 #define OPERAND_TYPE_ACC32 \
 291   { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 292       0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
 293
 294 #define OPERAND_TYPE_ACC64 \
 295   { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 296       0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
 297
 298 #define OPERAND_TYPE_REG16_INOUTPORTREG \
 299   { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
 300       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 301
 302 #define OPERAND_TYPE_DISP16_32 \
 303   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, \
 304       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 305
 306 #define OPERAND_TYPE_ANYDISP \
 307   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, \
 308       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 309
 310 #define OPERAND_TYPE_IMM16_32 \
 311   { { 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 312       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 313
 314 #define OPERAND_TYPE_IMM16_32S \
 315   { { 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 316       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 317
 318 #define OPERAND_TYPE_IMM16_32_32S \
 319   { { 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
 320       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 321
 322 #define OPERAND_TYPE_IMM32_32S_DISP32 \
 323   { { 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
 324       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 325
 326 #define OPERAND_TYPE_IMM64_DISP64 \
 327   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
 328       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 329
 330 #define OPERAND_TYPE_IMM32_32S_64_DISP32 \
 331   { { 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
 332       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
 333
 334 #define OPERAND_TYPE_IMM32_32S_64_DISP32_64 \
 335   { { 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, \
 336       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }