opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright 2007
   3    Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "opcode/i386.h"
  23 #ifdef HAVE_LIMITS_H
  24 #include <limits.h>
  25 #endif
  26
  27 #ifndef CHAR_BIT
  28 #define CHAR_BIT 8
  29 #endif
  30
  31 /* Position of cpu flags bitfiled.  */
  32
  33 /* i186 or better required */
  34 #define Cpu186          0
  35 /* i286 or better required */
  36 #define Cpu286          (Cpu186 + 1)
  37 /* i386 or better required */
  38 #define Cpu386          (Cpu286 + 1)
  39 /* i486 or better required */
  40 #define Cpu486          (Cpu386 + 1)
  41 /* i585 or better required */
  42 #define Cpu586          (Cpu486 + 1)
  43 /* i686 or better required */
  44 #define Cpu686          (Cpu586 + 1)
  45 /* Pentium4 or better required */
  46 #define CpuP4           (Cpu686 + 1)
  47 /* AMD K6 or better required*/
  48 #define CpuK6           (CpuP4 + 1)
  49 /* AMD K8 or better required */
  50 #define CpuK8           (CpuK6 + 1)
  51 /* MMX support required */
  52 #define CpuMMX          (CpuK8 + 1)
  53 /* extended MMX support (with SSE or 3DNow!Ext) required */
  54 #define CpuMMX2         (CpuMMX + 1)
  55 /* SSE support required */
  56 #define CpuSSE          (CpuMMX2 + 1)
  57 /* SSE2 support required */
  58 #define CpuSSE2         (CpuSSE + 1)
  59 /* 3dnow! support required */
  60 #define Cpu3dnow        (CpuSSE2 + 1)
  61 /* 3dnow! Extensions support required */
  62 #define Cpu3dnowA       (Cpu3dnow + 1)
  63 /* SSE3 support required */
  64 #define CpuSSE3         (Cpu3dnowA + 1)
  65 /* VIA PadLock required */
  66 #define CpuPadLock      (CpuSSE3 + 1)
  67 /* AMD Secure Virtual Machine Ext-s required */
  68 #define CpuSVME         (CpuPadLock + 1)
  69 /* VMX Instructions required */
  70 #define CpuVMX          (CpuSVME + 1)
  71 /* SMX Instructions required */
  72 #define CpuSMX          (CpuVMX + 1)
  73 /* SSSE3 support required */
  74 #define CpuSSSE3        (CpuSMX + 1)
  75 /* SSE4a support required */
  76 #define CpuSSE4a        (CpuSSSE3 + 1)
  77 /* ABM New Instructions required */
  78 #define CpuABM          (CpuSSE4a + 1)
  79 /* SSE4.1 support required */
  80 #define CpuSSE4_1       (CpuABM + 1)
  81 /* SSE4.2 support required */
  82 #define CpuSSE4_2       (CpuSSE4_1 + 1)
  83 /* SSE5 support required */
  84 #define CpuSSE5         (CpuSSE4_2 + 1)
  85 /* 64bit support available, used by -march= in assembler.  */
  86 #define CpuLM           (CpuSSE5 + 1)
  87 /* 64bit support required  */
  88 #define Cpu64           (CpuLM + 1)
  89 /* Not supported in the 64bit mode  */
  90 #define CpuNo64         (Cpu64 + 1)
  91 /* The last bitfield in i386_cpu_flags.  */
  92 #define CpuMax          CpuNo64
  93
  94 #define CpuNumOfUints \
  95   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
  96 #define CpuNumOfBits \
  97   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
  98
  99 /* If you get a compiler error for zero width of the unused field,
 100    comment it out.  */
 101 #define CpuUnused       (CpuMax + 1)
 102
 103 /* We can check if an instruction is available with array instead
 104    of bitfield. */
 105 typedef union i386_cpu_flags
 106 {
 107   struct
 108     {
 109       unsigned int cpui186:1;
 110       unsigned int cpui286:1;
 111       unsigned int cpui386:1;
 112       unsigned int cpui486:1;
 113       unsigned int cpui586:1;
 114       unsigned int cpui686:1;
 115       unsigned int cpup4:1;
 116       unsigned int cpuk6:1;
 117       unsigned int cpuk8:1;
 118       unsigned int cpummx:1;
 119       unsigned int cpummx2:1;
 120       unsigned int cpusse:1;
 121       unsigned int cpusse2:1;
 122       unsigned int cpua3dnow:1;
 123       unsigned int cpua3dnowa:1;
 124       unsigned int cpusse3:1;
 125       unsigned int cpupadlock:1;
 126       unsigned int cpusvme:1;
 127       unsigned int cpuvmx:1;
 128       unsigned int cpusmx:1;
 129       unsigned int cpussse3:1;
 130       unsigned int cpusse4a:1;
 131       unsigned int cpuabm:1;
 132       unsigned int cpusse4_1:1;
 133       unsigned int cpusse4_2:1;
 134       unsigned int cpusse5:1;
 135       unsigned int cpulm:1;
 136       unsigned int cpu64:1;
 137       unsigned int cpuno64:1;
 138 #ifdef CpuUnused
 139       unsigned int unused:(CpuNumOfBits - CpuUnused);
 140 #endif
 141     } bitfield;
 142   unsigned int array[CpuNumOfUints];
 143 } i386_cpu_flags;
 144
 145 /* Position of opcode_modifier bits.  */
 146
 147 /* has direction bit. */
 148 #define D                       0
 149 /* set if operands can be words or dwords encoded the canonical way */
 150 #define W                       (D + 1)
 151 /* insn has a modrm byte. */
 152 #define Modrm                   (W + 1)
 153 /* register is in low 3 bits of opcode */
 154 #define ShortForm               (Modrm + 1)
 155 /* special case for jump insns.  */
 156 #define Jump                    (ShortForm + 1)
 157 /* call and jump */
 158 #define JumpDword               (Jump + 1)
 159 /* loop and jecxz */
 160 #define JumpByte                (JumpDword + 1)
 161 /* special case for intersegment leaps/calls */
 162 #define JumpInterSegment        (JumpByte + 1)
 163 /* FP insn memory format bit, sized by 0x4 */
 164 #define FloatMF                 (JumpInterSegment + 1)
 165 /* src/dest swap for floats. */
 166 #define FloatR                  (FloatMF + 1)
 167 /* has float insn direction bit. */
 168 #define FloatD                  (FloatR + 1)
 169 /* needs size prefix if in 32-bit mode */
 170 #define Size16                  (FloatD + 1)
 171 /* needs size prefix if in 16-bit mode */
 172 #define Size32                  (Size16 + 1)
 173 /* needs size prefix if in 64-bit mode */
 174 #define Size64                  (Size32 + 1)
 175 /* instruction ignores operand size prefix */
 176 #define IgnoreSize              (Size64 + 1)
 177 /* default insn size depends on mode */
 178 #define DefaultSize             (IgnoreSize + 1)
 179 /* b suffix on instruction illegal */
 180 #define No_bSuf                 (DefaultSize + 1)
 181 /* w suffix on instruction illegal */
 182 #define No_wSuf                 (No_bSuf + 1)
 183 /* l suffix on instruction illegal */
 184 #define No_lSuf                 (No_wSuf + 1)
 185 /* s suffix on instruction illegal */
 186 #define No_sSuf                 (No_lSuf + 1)
 187 /* q suffix on instruction illegal */
 188 #define No_qSuf                 (No_sSuf + 1)
 189 /* x suffix on instruction illegal */
 190 #define No_xSuf                 (No_qSuf + 1)
 191 /* instruction needs FWAIT */
 192 #define FWait                   (No_xSuf + 1)
 193 /* quick test for string instructions */
 194 #define IsString                (FWait + 1)
 195 /* fake an extra reg operand for clr, imul and special register
 196    processing for some instructions.  */
 197 #define RegKludge               (IsString + 1)
 198 /* opcode is a prefix */
 199 #define IsPrefix                (RegKludge + 1)
 200 /* instruction has extension in 8 bit imm */
 201 #define ImmExt                  (IsPrefix + 1)
 202 /* instruction don't need Rex64 prefix.  */
 203 #define NoRex64                 (ImmExt + 1)
 204 /* instruction require Rex64 prefix.  */
 205 #define Rex64                   (NoRex64 + 1)
 206 /* deprecated fp insn, gets a warning */
 207 #define Ugh                     (Rex64 + 1)
 208 #define Drex                    (Ugh + 1)
 209 /* instruction needs DREX with multiple encodings for memory ops */
 210 #define Drexv                   (Drex + 1)
 211 /* special DREX for comparisons */
 212 #define Drexc                   (Drexv + 1)
 213 /* The last bitfield in i386_opcode_modifier.  */
 214 #define Opcode_Modifier_Max     Drexc
 215
 216 typedef struct i386_opcode_modifier
 217 {
 218   unsigned int d:1;
 219   unsigned int w:1;
 220   unsigned int modrm:1;
 221   unsigned int shortform:1;
 222   unsigned int jump:1;
 223   unsigned int jumpdword:1;
 224   unsigned int jumpbyte:1;
 225   unsigned int jumpintersegment:1;
 226   unsigned int floatmf:1;
 227   unsigned int floatr:1;
 228   unsigned int floatd:1;
 229   unsigned int size16:1;
 230   unsigned int size32:1;
 231   unsigned int size64:1;
 232   unsigned int ignoresize:1;
 233   unsigned int defaultsize:1;
 234   unsigned int no_bsuf:1;
 235   unsigned int no_wsuf:1;
 236   unsigned int no_lsuf:1;
 237   unsigned int no_ssuf:1;
 238   unsigned int no_qsuf:1;
 239   unsigned int no_xsuf:1;
 240   unsigned int fwait:1;
 241   unsigned int isstring:1;
 242   unsigned int regkludge:1;
 243   unsigned int isprefix:1;
 244   unsigned int immext:1;
 245   unsigned int norex64:1;
 246   unsigned int rex64:1;
 247   unsigned int ugh:1;
 248   unsigned int drex:1;
 249   unsigned int drexv:1;
 250   unsigned int drexc:1;
 251 } i386_opcode_modifier;
 252
 253 /* Position of operand_type bits.  */
 254
 255 /* Registers  */
 256
 257 /* 8 bit reg */
 258 #define Reg8                    0
 259 /* 16 bit reg */
 260 #define Reg16                   (Reg8 + 1)
 261 /* 32 bit reg */
 262 #define Reg32                   (Reg16 + 1)
 263 /* 64 bit reg */
 264 #define Reg64                   (Reg32 + 1)
 265
 266 /* immediate */
 267
 268 /* 8 bit immediate */
 269 #define Imm8                    (Reg64 + 1)
 270 /* 8 bit immediate sign extended */
 271 #define Imm8S                   (Imm8 + 1)
 272 /* 16 bit immediate */
 273 #define Imm16                   (Imm8S + 1)
 274 /* 32 bit immediate */
 275 #define Imm32                   (Imm16 + 1)
 276 /* 32 bit immediate sign extended */
 277 #define Imm32S                  (Imm32 + 1)
 278 /* 64 bit immediate */
 279 #define Imm64                   (Imm32S + 1)
 280 /* 1 bit immediate */
 281 #define Imm1                    (Imm64 + 1)
 282
 283 /* memory */
 284
 285 #define BaseIndex               (Imm1 + 1)
 286 /* Disp8,16,32 are used in different ways, depending on the
 287    instruction.  For jumps, they specify the size of the PC relative
 288    displacement, for baseindex type instructions, they specify the
 289    size of the offset relative to the base register, and for memory
 290    offset instructions such as `mov 1234,%al' they specify the size of
 291    the offset relative to the segment base.  */
 292 /* 8 bit displacement */
 293 #define Disp8                   (BaseIndex + 1)
 294 /* 16 bit displacement */
 295 #define Disp16                  (Disp8 + 1)
 296 /* 32 bit displacement */
 297 #define Disp32                  (Disp16 + 1)
 298 /* 32 bit signed displacement */
 299 #define Disp32S                 (Disp32 + 1)
 300 /* 64 bit displacement */
 301 #define Disp64                  (Disp32S + 1)
 302
 303 /* specials */
 304
 305 /* register to hold in/out port addr = dx */
 306 #define InOutPortReg            (Disp64 + 1)
 307 /* register to hold shift count = cl */
 308 #define ShiftCount              (InOutPortReg + 1)
 309 /* Control register */
 310 #define Control                 (ShiftCount + 1)
 311 /* Debug register */
 312 #define Debug                   (Control + 1)
 313 /* Test register */
 314 #define Test                    (Debug + 1)
 315 /* Float register */
 316 #define FloatReg                (Test + 1)
 317 /* Float stack top %st(0) */
 318 #define FloatAcc                (FloatReg + 1)
 319 /* 2 bit segment register */
 320 #define SReg2                   (FloatAcc + 1)
 321 /* 3 bit segment register */
 322 #define SReg3                   (SReg2 + 1)
 323 /* Accumulator %al or %ax or %eax */
 324 #define Acc                     (SReg3 + 1)
 325 #define JumpAbsolute            (Acc + 1)
 326 /* MMX register */
 327 #define RegMMX                  (JumpAbsolute + 1)
 328 /* XMM registers in PIII */
 329 #define RegXMM                  (RegMMX + 1)
 330 /* String insn operand with fixed es segment */
 331 #define EsSeg                   (RegXMM + 1)
 332
 333 /* RegMem is for instructions with a modrm byte where the register
 334    destination operand should be encoded in the mod and regmem fields.
 335    Normally, it will be encoded in the reg field. We add a RegMem
 336    flag to the destination register operand to indicate that it should
 337    be encoded in the regmem field.  */
 338 #define RegMem                  (EsSeg + 1)
 339
 340 /* The last bitfield in i386_operand_type.  */
 341 #define OTMax                   RegMem
 342
 343 #define OTNumOfUints \
 344   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 345 #define OTNumOfBits \
 346   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 347
 348 /* If you get a compiler error for zero width of the unused field,
 349    comment it out.  */
 350 #if 0
 351 #define OTUnused                (OTMax + 1)
 352 #endif
 353
 354 typedef union i386_operand_type
 355 {
 356   struct
 357     {
 358       unsigned int reg8:1;
 359       unsigned int reg16:1;
 360       unsigned int reg32:1;
 361       unsigned int reg64:1;
 362       unsigned int imm8:1;
 363       unsigned int imm8s:1;
 364       unsigned int imm16:1;
 365       unsigned int imm32:1;
 366       unsigned int imm32s:1;
 367       unsigned int imm64:1;
 368       unsigned int imm1:1;
 369       unsigned int baseindex:1;
 370       unsigned int disp8:1;
 371       unsigned int disp16:1;
 372       unsigned int disp32:1;
 373       unsigned int disp32s:1;
 374       unsigned int disp64:1;
 375       unsigned int inoutportreg:1;
 376       unsigned int shiftcount:1;
 377       unsigned int control:1;
 378       unsigned int debug:1;
 379       unsigned int test:1;
 380       unsigned int floatreg:1;
 381       unsigned int floatacc:1;
 382       unsigned int sreg2:1;
 383       unsigned int sreg3:1;
 384       unsigned int acc:1;
 385       unsigned int jumpabsolute:1;
 386       unsigned int regmmx:1;
 387       unsigned int regxmm:1;
 388       unsigned int esseg:1;
 389       unsigned int regmem:1;
 390 #ifdef OTUnused
 391       unsigned int unused:(OTNumOfBits - OTUnused);
 392 #endif
 393     } bitfield;
 394   unsigned int array[OTNumOfUints];
 395 } i386_operand_type;
 396
 397 typedef struct template
 398 {
 399   /* instruction name sans width suffix ("mov" for movl insns) */
 400   char *name;
 401
 402   /* how many operands */
 403   unsigned int operands;
 404
 405   /* base_opcode is the fundamental opcode byte without optional
 406      prefix(es).  */
 407   unsigned int base_opcode;
 408 #define Opcode_D        0x2 /* Direction bit:
 409                                set if Reg --> Regmem;
 410                                unset if Regmem --> Reg. */
 411 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 412 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 413
 414   /* extension_opcode is the 3 bit extension for group <n> insns.
 415      This field is also used to store the 8-bit opcode suffix for the
 416      AMD 3DNow! instructions.
 417      If this template has no extension opcode (the usual case) use None
 418      Instructions with Drex use this to specify 2 bits for OC */
 419   unsigned int extension_opcode;
 420 #define None 0xffff             /* If no extension_opcode is possible.  */
 421
 422   /* Opcode length.  */
 423   unsigned char opcode_length;
 424
 425   /* cpu feature flags */
 426   i386_cpu_flags cpu_flags;
 427
 428   /* the bits in opcode_modifier are used to generate the final opcode from
 429      the base_opcode.  These bits also are used to detect alternate forms of
 430      the same instruction */
 431   i386_opcode_modifier opcode_modifier;
 432
 433   /* operand_types[i] describes the type of operand i.  This is made
 434      by OR'ing together all of the possible type masks.  (e.g.
 435      'operand_types[i] = Reg|Imm' specifies that operand i can be
 436      either a register or an immediate operand.  */
 437   i386_operand_type operand_types[MAX_OPERANDS];
 438 }
 439 template;
 440
 441 extern const template i386_optab[];
 442
 443 /* these are for register name --> number & type hash lookup */
 444 typedef struct
 445 {
 446   char *reg_name;
 447   i386_operand_type reg_type;
 448   unsigned int reg_flags;
 449 #define RegRex      0x1  /* Extended register.  */
 450 #define RegRex64    0x2  /* Extended 8 bit register.  */
 451   unsigned int reg_num;
 452 #define RegRip  ((unsigned int ) ~0)
 453 #define RegEip  (RegRip - 1)
 454 /* EIZ and RIZ are fake index registers.  */
 455 #define RegEiz  (RegEip - 1)
 456 #define RegRiz  (RegEiz - 1)
 457 }
 458 reg_entry;
 459
 460 /* Entries in i386_regtab.  */
 461 #define REGNAM_AL 1
 462 #define REGNAM_AX 25
 463 #define REGNAM_EAX 41
 464
 465 extern const reg_entry i386_regtab[];
 466 extern const unsigned int i386_regtab_size;
 467
 468 typedef struct
 469 {
 470   char *seg_name;
 471   unsigned int seg_prefix;
 472 }
 473 seg_entry;
 474
 475 extern const seg_entry cs;
 476 extern const seg_entry ds;
 477 extern const seg_entry ss;
 478 extern const seg_entry es;
 479 extern const seg_entry fs;
 480 extern const seg_entry gs;