opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; if not, write to the Free Software
  19    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  20    MA 02110-1301, USA.  */
  21
  22
  23 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  24    July 1988
  25     modified by John Hassey (hassey@dg-rtp.dg.com)
  26     x86-64 support added by Jan Hubicka (jh@suse.cz)
  27     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  28
  29 /* The main tables describing the instructions is essentially a copy
  30    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  31    Programmers Manual.  Usually, there is a capital letter, followed
  32    by a small letter.  The capital letter tell the addressing mode,
  33    and the small letter tells about the operand size.  Refer to
  34    the Intel manual for details.  */
  35
  36 #include "sysdep.h"
  37 #include "dis-asm.h"
  38 #include "opintl.h"
  39 #include "opcode/i386.h"
  40 #include "libiberty.h"
  41
  42 #include <setjmp.h>
  43
  44 static int fetch_data (struct disassemble_info *, bfd_byte *);
  45 static void ckprefix (void);
  46 static const char *prefix_name (int, int);
  47 static int print_insn (bfd_vma, disassemble_info *);
  48 static void dofloat (int);
  49 static void OP_ST (int, int);
  50 static void OP_STi (int, int);
  51 static int putop (const char *, int);
  52 static void oappend (const char *);
  53 static void append_seg (void);
  54 static void OP_indirE (int, int);
  55 static void print_operand_value (char *, int, bfd_vma);
  56 static void OP_E_register (int, int);
  57 static void OP_E_memory (int, int, int);
  58 static void OP_E_extended (int, int, int);
  59 static void print_displacement (char *, bfd_vma);
  60 static void OP_E (int, int);
  61 static void OP_G (int, int);
  62 static bfd_vma get64 (void);
  63 static bfd_signed_vma get32 (void);
  64 static bfd_signed_vma get32s (void);
  65 static int get16 (void);
  66 static void set_op (bfd_vma, int);
  67 static void OP_Skip_MODRM (int, int);
  68 static void OP_REG (int, int);
  69 static void OP_IMREG (int, int);
  70 static void OP_I (int, int);
  71 static void OP_I64 (int, int);
  72 static void OP_sI (int, int);
  73 static void OP_J (int, int);
  74 static void OP_SEG (int, int);
  75 static void OP_DIR (int, int);
  76 static void OP_OFF (int, int);
  77 static void OP_OFF64 (int, int);
  78 static void ptr_reg (int, int);
  79 static void OP_ESreg (int, int);
  80 static void OP_DSreg (int, int);
  81 static void OP_C (int, int);
  82 static void OP_D (int, int);
  83 static void OP_T (int, int);
  84 static void OP_R (int, int);
  85 static void OP_MMX (int, int);
  86 static void OP_XMM (int, int);
  87 static void OP_EM (int, int);
  88 static void OP_EX (int, int);
  89 static void OP_EMC (int,int);
  90 static void OP_MXC (int,int);
  91 static void OP_MS (int, int);
  92 static void OP_XS (int, int);
  93 static void OP_M (int, int);
  94 static void OP_VEX (int, int);
  95 static void OP_EX_Vex (int, int);
  96 static void OP_EX_VexW (int, int);
  97 static void OP_XMM_Vex (int, int);
  98 static void OP_XMM_VexW (int, int);
  99 static void OP_REG_VexI4 (int, int);
 100 static void PCLMUL_Fixup (int, int);
 101 static void VEXI4_Fixup (int, int);
 102 static void VZERO_Fixup (int, int);
 103 static void VCMP_Fixup (int, int);
 104 static void VPERMIL2_Fixup (int, int);
 105 static void OP_0f07 (int, int);
 106 static void OP_Monitor (int, int);
 107 static void OP_Mwait (int, int);
 108 static void NOP_Fixup1 (int, int);
 109 static void NOP_Fixup2 (int, int);
 110 static void OP_3DNowSuffix (int, int);
 111 static void CMP_Fixup (int, int);
 112 static void BadOp (void);
 113 static void REP_Fixup (int, int);
 114 static void CMPXCHG8B_Fixup (int, int);
 115 static void XMM_Fixup (int, int);
 116 static void CRC32_Fixup (int, int);
 117 static void print_drex_arg (unsigned int, int, int);
 118 static void OP_DREX4 (int, int);
 119 static void OP_DREX3 (int, int);
 120 static void OP_DREX_ICMP (int, int);
 121 static void OP_DREX_FCMP (int, int);
 122
 123 struct dis_private {
 124   /* Points to first byte not fetched.  */
 125   bfd_byte *max_fetched;
 126   bfd_byte the_buffer[MAX_MNEM_SIZE];
 127   bfd_vma insn_start;
 128   int orig_sizeflag;
 129   jmp_buf bailout;
 130 };
 131
 132 enum address_mode
 133 {
 134   mode_16bit,
 135   mode_32bit,
 136   mode_64bit
 137 };
 138
 139 enum address_mode address_mode;
 140
 141 /* Flags for the prefixes for the current instruction.  See below.  */
 142 static int prefixes;
 143
 144 /* REX prefix the current instruction.  See below.  */
 145 static int rex;
 146 /* Bits of REX we've already used.  */
 147 static int rex_used;
 148 /* Original REX prefix.  */
 149 static int rex_original;
 150 /* REX bits in original REX prefix ignored.  It may not be the same
 151    as rex_original since some bits may not be ignored.  */
 152 static int rex_ignored;
 153 /* Mark parts used in the REX prefix.  When we are testing for
 154    empty prefix (for 8bit register REX extension), just mask it
 155    out.  Otherwise test for REX bit is excuse for existence of REX
 156    only in case value is nonzero.  */
 157 #define USED_REX(value)                                 \
 158   {                                                     \
 159     if (value)                                          \
 160       {                                                 \
 161         if ((rex & value))                              \
 162           rex_used |= (value) | REX_OPCODE;             \
 163       }                                                 \
 164     else                                                \
 165       rex_used |= REX_OPCODE;                           \
 166   }
 167
 168 /* Special 'registers' for DREX handling */
 169 #define DREX_REG_UNKNOWN        1000    /* not initialized */
 170 #define DREX_REG_MEMORY         1001    /* use MODRM/SIB/OFFSET memory */
 171
 172 /* The DREX byte has the following fields:
 173    Bits 7-4 -- DREX.Dest, xmm destination register
 174    Bit 3    -- DREX.OC0, operand config bit defines operand order
 175    Bit 2    -- DREX.R, equivalent to REX_R bit, to extend ModRM register
 176    Bit 1    -- DREX.X, equivalent to REX_X bit, to extend SIB index field
 177    Bit 0    -- DREX.W, equivalent to REX_B bit, to extend ModRM r/m field,
 178                SIB base field, or opcode reg field.  */
 179 #define DREX_XMM(drex) ((drex >> 4) & 0xf)
 180 #define DREX_OC0(drex) ((drex >> 3) & 0x1)
 181
 182 /* Flags for prefixes which we somehow handled when printing the
 183    current instruction.  */
 184 static int used_prefixes;
 185
 186 /* Flags stored in PREFIXES.  */
 187 #define PREFIX_REPZ 1
 188 #define PREFIX_REPNZ 2
 189 #define PREFIX_LOCK 4
 190 #define PREFIX_CS 8
 191 #define PREFIX_SS 0x10
 192 #define PREFIX_DS 0x20
 193 #define PREFIX_ES 0x40
 194 #define PREFIX_FS 0x80
 195 #define PREFIX_GS 0x100
 196 #define PREFIX_DATA 0x200
 197 #define PREFIX_ADDR 0x400
 198 #define PREFIX_FWAIT 0x800
 199
 200 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 201    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 202    on error.  */
 203 #define FETCH_DATA(info, addr) \
 204   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 205    ? 1 : fetch_data ((info), (addr)))
 206
 207 static int
 208 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 209 {
 210   int status;
 211   struct dis_private *priv = (struct dis_private *) info->private_data;
 212   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 213
 214   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 215     status = (*info->read_memory_func) (start,
 216                                         priv->max_fetched,
 217                                         addr - priv->max_fetched,
 218                                         info);
 219   else
 220     status = -1;
 221   if (status != 0)
 222     {
 223       /* If we did manage to read at least one byte, then
 224          print_insn_i386 will do something sensible.  Otherwise, print
 225          an error.  We do that here because this is where we know
 226          STATUS.  */
 227       if (priv->max_fetched == priv->the_buffer)
 228         (*info->memory_error_func) (status, start, info);
 229       longjmp (priv->bailout, 1);
 230     }
 231   else
 232     priv->max_fetched = addr;
 233   return 1;
 234 }
 235
 236 #define XX { NULL, 0 }
 237
 238 #define Eb { OP_E, b_mode }
 239 #define Ev { OP_E, v_mode }
 240 #define Ed { OP_E, d_mode }
 241 #define Edq { OP_E, dq_mode }
 242 #define Edqw { OP_E, dqw_mode }
 243 #define Edqb { OP_E, dqb_mode }
 244 #define Edqd { OP_E, dqd_mode }
 245 #define Eq { OP_E, q_mode }
 246 #define indirEv { OP_indirE, stack_v_mode }
 247 #define indirEp { OP_indirE, f_mode }
 248 #define stackEv { OP_E, stack_v_mode }
 249 #define Em { OP_E, m_mode }
 250 #define Ew { OP_E, w_mode }
 251 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 252 #define Ma { OP_M, a_mode }
 253 #define Mb { OP_M, b_mode }
 254 #define Md { OP_M, d_mode }
 255 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 256 #define Mq { OP_M, q_mode }
 257 #define Mx { OP_M, x_mode }
 258 #define Mxmm { OP_M, xmm_mode }
 259 #define Gb { OP_G, b_mode }
 260 #define Gv { OP_G, v_mode }
 261 #define Gd { OP_G, d_mode }
 262 #define Gdq { OP_G, dq_mode }
 263 #define Gm { OP_G, m_mode }
 264 #define Gw { OP_G, w_mode }
 265 #define Rd { OP_R, d_mode }
 266 #define Rm { OP_R, m_mode }
 267 #define Ib { OP_I, b_mode }
 268 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 269 #define Iv { OP_I, v_mode }
 270 #define Iq { OP_I, q_mode }
 271 #define Iv64 { OP_I64, v_mode }
 272 #define Iw { OP_I, w_mode }
 273 #define I1 { OP_I, const_1_mode }
 274 #define Jb { OP_J, b_mode }
 275 #define Jv { OP_J, v_mode }
 276 #define Cm { OP_C, m_mode }
 277 #define Dm { OP_D, m_mode }
 278 #define Td { OP_T, d_mode }
 279 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 280
 281 #define RMeAX { OP_REG, eAX_reg }
 282 #define RMeBX { OP_REG, eBX_reg }
 283 #define RMeCX { OP_REG, eCX_reg }
 284 #define RMeDX { OP_REG, eDX_reg }
 285 #define RMeSP { OP_REG, eSP_reg }
 286 #define RMeBP { OP_REG, eBP_reg }
 287 #define RMeSI { OP_REG, eSI_reg }
 288 #define RMeDI { OP_REG, eDI_reg }
 289 #define RMrAX { OP_REG, rAX_reg }
 290 #define RMrBX { OP_REG, rBX_reg }
 291 #define RMrCX { OP_REG, rCX_reg }
 292 #define RMrDX { OP_REG, rDX_reg }
 293 #define RMrSP { OP_REG, rSP_reg }
 294 #define RMrBP { OP_REG, rBP_reg }
 295 #define RMrSI { OP_REG, rSI_reg }
 296 #define RMrDI { OP_REG, rDI_reg }
 297 #define RMAL { OP_REG, al_reg }
 298 #define RMAL { OP_REG, al_reg }
 299 #define RMCL { OP_REG, cl_reg }
 300 #define RMDL { OP_REG, dl_reg }
 301 #define RMBL { OP_REG, bl_reg }
 302 #define RMAH { OP_REG, ah_reg }
 303 #define RMCH { OP_REG, ch_reg }
 304 #define RMDH { OP_REG, dh_reg }
 305 #define RMBH { OP_REG, bh_reg }
 306 #define RMAX { OP_REG, ax_reg }
 307 #define RMDX { OP_REG, dx_reg }
 308
 309 #define eAX { OP_IMREG, eAX_reg }
 310 #define eBX { OP_IMREG, eBX_reg }
 311 #define eCX { OP_IMREG, eCX_reg }
 312 #define eDX { OP_IMREG, eDX_reg }
 313 #define eSP { OP_IMREG, eSP_reg }
 314 #define eBP { OP_IMREG, eBP_reg }
 315 #define eSI { OP_IMREG, eSI_reg }
 316 #define eDI { OP_IMREG, eDI_reg }
 317 #define AL { OP_IMREG, al_reg }
 318 #define CL { OP_IMREG, cl_reg }
 319 #define DL { OP_IMREG, dl_reg }
 320 #define BL { OP_IMREG, bl_reg }
 321 #define AH { OP_IMREG, ah_reg }
 322 #define CH { OP_IMREG, ch_reg }
 323 #define DH { OP_IMREG, dh_reg }
 324 #define BH { OP_IMREG, bh_reg }
 325 #define AX { OP_IMREG, ax_reg }
 326 #define DX { OP_IMREG, dx_reg }
 327 #define zAX { OP_IMREG, z_mode_ax_reg }
 328 #define indirDX { OP_IMREG, indir_dx_reg }
 329
 330 #define Sw { OP_SEG, w_mode }
 331 #define Sv { OP_SEG, v_mode }
 332 #define Ap { OP_DIR, 0 }
 333 #define Ob { OP_OFF64, b_mode }
 334 #define Ov { OP_OFF64, v_mode }
 335 #define Xb { OP_DSreg, eSI_reg }
 336 #define Xv { OP_DSreg, eSI_reg }
 337 #define Xz { OP_DSreg, eSI_reg }
 338 #define Yb { OP_ESreg, eDI_reg }
 339 #define Yv { OP_ESreg, eDI_reg }
 340 #define DSBX { OP_DSreg, eBX_reg }
 341
 342 #define es { OP_REG, es_reg }
 343 #define ss { OP_REG, ss_reg }
 344 #define cs { OP_REG, cs_reg }
 345 #define ds { OP_REG, ds_reg }
 346 #define fs { OP_REG, fs_reg }
 347 #define gs { OP_REG, gs_reg }
 348
 349 #define MX { OP_MMX, 0 }
 350 #define XM { OP_XMM, 0 }
 351 #define XMM { OP_XMM, xmm_mode }
 352 #define EM { OP_EM, v_mode }
 353 #define EMd { OP_EM, d_mode }
 354 #define EMx { OP_EM, x_mode }
 355 #define EXw { OP_EX, w_mode }
 356 #define EXd { OP_EX, d_mode }
 357 #define EXq { OP_EX, q_mode }
 358 #define EXx { OP_EX, x_mode }
 359 #define EXxmm { OP_EX, xmm_mode }
 360 #define EXxmmq { OP_EX, xmmq_mode }
 361 #define EXymmq { OP_EX, ymmq_mode }
 362 #define MS { OP_MS, v_mode }
 363 #define XS { OP_XS, v_mode }
 364 #define EMCq { OP_EMC, q_mode }
 365 #define MXC { OP_MXC, 0 }
 366 #define OPSUF { OP_3DNowSuffix, 0 }
 367 #define CMP { CMP_Fixup, 0 }
 368 #define XMM0 { XMM_Fixup, 0 }
 369
 370 #define Vex { OP_VEX, vex_mode }
 371 #define Vex128 { OP_VEX, vex128_mode }
 372 #define Vex256 { OP_VEX, vex256_mode }
 373 #define VexI4 { VEXI4_Fixup, 0}
 374 #define EXdVex { OP_EX_Vex, d_mode }
 375 #define EXqVex { OP_EX_Vex, q_mode }
 376 #define EXVexW { OP_EX_VexW, x_mode }
 377 #define EXdVexW { OP_EX_VexW, d_mode }
 378 #define EXqVexW { OP_EX_VexW, q_mode }
 379 #define XMVex { OP_XMM_Vex, 0 }
 380 #define XMVexW { OP_XMM_VexW, 0 }
 381 #define XMVexI4 { OP_REG_VexI4, x_mode }
 382 #define PCLMUL { PCLMUL_Fixup, 0 }
 383 #define VZERO { VZERO_Fixup, 0 }
 384 #define VCMP { VCMP_Fixup, 0 }
 385 #define VPERMIL2 { VPERMIL2_Fixup, 0 }
 386
 387 /* Used handle "rep" prefix for string instructions.  */
 388 #define Xbr { REP_Fixup, eSI_reg }
 389 #define Xvr { REP_Fixup, eSI_reg }
 390 #define Ybr { REP_Fixup, eDI_reg }
 391 #define Yvr { REP_Fixup, eDI_reg }
 392 #define Yzr { REP_Fixup, eDI_reg }
 393 #define indirDXr { REP_Fixup, indir_dx_reg }
 394 #define ALr { REP_Fixup, al_reg }
 395 #define eAXr { REP_Fixup, eAX_reg }
 396
 397 #define cond_jump_flag { NULL, cond_jump_mode }
 398 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 399
 400 /* bits in sizeflag */
 401 #define SUFFIX_ALWAYS 4
 402 #define AFLAG 2
 403 #define DFLAG 1
 404
 405 /* byte operand */
 406 #define b_mode                  1
 407 /* operand size depends on prefixes */
 408 #define v_mode                  (b_mode + 1)
 409 /* word operand */
 410 #define w_mode                  (v_mode + 1)
 411 /* double word operand  */
 412 #define d_mode                  (w_mode + 1)
 413 /* quad word operand */
 414 #define q_mode                  (d_mode + 1)
 415 /* ten-byte operand */
 416 #define t_mode                  (q_mode + 1)
 417 /* 16-byte XMM or 32-byte YMM operand */
 418 #define x_mode                  (t_mode + 1)
 419 /* 16-byte XMM operand */
 420 #define xmm_mode                (x_mode + 1)
 421 /* 16-byte XMM or quad word operand */
 422 #define xmmq_mode               (xmm_mode + 1)
 423 /* 32-byte YMM or quad word operand */
 424 #define ymmq_mode               (xmmq_mode + 1)
 425 /* d_mode in 32bit, q_mode in 64bit mode.  */
 426 #define m_mode                  (ymmq_mode + 1)
 427 /* pair of v_mode operands */
 428 #define a_mode                  (m_mode + 1)
 429 #define cond_jump_mode          (a_mode + 1)
 430 #define loop_jcxz_mode          (cond_jump_mode + 1)
 431 /* operand size depends on REX prefixes.  */
 432 #define dq_mode                 (loop_jcxz_mode + 1)
 433 /* registers like dq_mode, memory like w_mode.  */
 434 #define dqw_mode                (dq_mode + 1)
 435 /* 4- or 6-byte pointer operand */
 436 #define f_mode                  (dqw_mode + 1)
 437 #define const_1_mode            (f_mode + 1)
 438 /* v_mode for stack-related opcodes.  */
 439 #define stack_v_mode            (const_1_mode + 1)
 440 /* non-quad operand size depends on prefixes */
 441 #define z_mode                  (stack_v_mode + 1)
 442 /* 16-byte operand */
 443 #define o_mode                  (z_mode + 1)
 444 /* registers like dq_mode, memory like b_mode.  */
 445 #define dqb_mode                (o_mode + 1)
 446 /* registers like dq_mode, memory like d_mode.  */
 447 #define dqd_mode                (dqb_mode + 1)
 448 /* normal vex mode */
 449 #define vex_mode                (dqd_mode + 1)
 450 /* 128bit vex mode */
 451 #define vex128_mode             (vex_mode + 1)
 452 /* 256bit vex mode */
 453 #define vex256_mode             (vex128_mode + 1)
 454
 455 #define es_reg                  (vex256_mode + 1)
 456 #define cs_reg                  (es_reg + 1)
 457 #define ss_reg                  (cs_reg + 1)
 458 #define ds_reg                  (ss_reg + 1)
 459 #define fs_reg                  (ds_reg + 1)
 460 #define gs_reg                  (fs_reg + 1)
 461
 462 #define eAX_reg                 (gs_reg + 1)
 463 #define eCX_reg                 (eAX_reg + 1)
 464 #define eDX_reg                 (eCX_reg + 1)
 465 #define eBX_reg                 (eDX_reg + 1)
 466 #define eSP_reg                 (eBX_reg + 1)
 467 #define eBP_reg                 (eSP_reg + 1)
 468 #define eSI_reg                 (eBP_reg + 1)
 469 #define eDI_reg                 (eSI_reg + 1)
 470
 471 #define al_reg                  (eDI_reg + 1)
 472 #define cl_reg                  (al_reg + 1)
 473 #define dl_reg                  (cl_reg + 1)
 474 #define bl_reg                  (dl_reg + 1)
 475 #define ah_reg                  (bl_reg + 1)
 476 #define ch_reg                  (ah_reg + 1)
 477 #define dh_reg                  (ch_reg + 1)
 478 #define bh_reg                  (dh_reg + 1)
 479
 480 #define ax_reg                  (bh_reg + 1)
 481 #define cx_reg                  (ax_reg + 1)
 482 #define dx_reg                  (cx_reg + 1)
 483 #define bx_reg                  (dx_reg + 1)
 484 #define sp_reg                  (bx_reg + 1)
 485 #define bp_reg                  (sp_reg + 1)
 486 #define si_reg                  (bp_reg + 1)
 487 #define di_reg                  (si_reg + 1)
 488
 489 #define rAX_reg                 (di_reg + 1)
 490 #define rCX_reg                 (rAX_reg + 1)
 491 #define rDX_reg                 (rCX_reg + 1)
 492 #define rBX_reg                 (rDX_reg + 1)
 493 #define rSP_reg                 (rBX_reg + 1)
 494 #define rBP_reg                 (rSP_reg + 1)
 495 #define rSI_reg                 (rBP_reg + 1)
 496 #define rDI_reg                 (rSI_reg + 1)
 497
 498 #define z_mode_ax_reg           (rDI_reg + 1)
 499 #define indir_dx_reg            (z_mode_ax_reg + 1)
 500
 501 #define MAX_BYTEMODE    indir_dx_reg
 502
 503 /* Flags that are OR'ed into the bytemode field to pass extra
 504    information.  */
 505 #define DREX_OC1                0x10000 /* OC1 bit set */
 506 #define DREX_NO_OC0             0x20000 /* OC0 bit not used */
 507 #define DREX_MASK               0x40000 /* mask to delete */
 508
 509 #if MAX_BYTEMODE >= DREX_OC1
 510 #error MAX_BYTEMODE must be less than DREX_OC1
 511 #endif
 512
 513 #define FLOATCODE               1
 514 #define USE_REG_TABLE           (FLOATCODE + 1)
 515 #define USE_MOD_TABLE           (USE_REG_TABLE + 1)
 516 #define USE_RM_TABLE            (USE_MOD_TABLE + 1)
 517 #define USE_PREFIX_TABLE        (USE_RM_TABLE + 1)
 518 #define USE_X86_64_TABLE        (USE_PREFIX_TABLE + 1)
 519 #define USE_3BYTE_TABLE         (USE_X86_64_TABLE + 1)
 520 #define USE_VEX_C4_TABLE        (USE_3BYTE_TABLE + 1)
 521 #define USE_VEX_C5_TABLE        (USE_VEX_C4_TABLE + 1)
 522 #define USE_VEX_LEN_TABLE       (USE_VEX_C5_TABLE + 1)
 523
 524 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 525
 526 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 527 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 528 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 529 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 530 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 531 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 532 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 533 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 534 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 535 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 536
 537 #define REG_80                  0
 538 #define REG_81                  (REG_80 + 1)
 539 #define REG_82                  (REG_81 + 1)
 540 #define REG_8F                  (REG_82 + 1)
 541 #define REG_C0                  (REG_8F + 1)
 542 #define REG_C1                  (REG_C0 + 1)
 543 #define REG_C6                  (REG_C1 + 1)
 544 #define REG_C7                  (REG_C6 + 1)
 545 #define REG_D0                  (REG_C7 + 1)
 546 #define REG_D1                  (REG_D0 + 1)
 547 #define REG_D2                  (REG_D1 + 1)
 548 #define REG_D3                  (REG_D2 + 1)
 549 #define REG_F6                  (REG_D3 + 1)
 550 #define REG_F7                  (REG_F6 + 1)
 551 #define REG_FE                  (REG_F7 + 1)
 552 #define REG_FF                  (REG_FE + 1)
 553 #define REG_0F00                (REG_FF + 1)
 554 #define REG_0F01                (REG_0F00 + 1)
 555 #define REG_0F0D                (REG_0F01 + 1)
 556 #define REG_0F18                (REG_0F0D + 1)
 557 #define REG_0F71                (REG_0F18 + 1)
 558 #define REG_0F72                (REG_0F71 + 1)
 559 #define REG_0F73                (REG_0F72 + 1)
 560 #define REG_0FA6                (REG_0F73 + 1)
 561 #define REG_0FA7                (REG_0FA6 + 1)
 562 #define REG_0FAE                (REG_0FA7 + 1)
 563 #define REG_0FBA                (REG_0FAE + 1)
 564 #define REG_0FC7                (REG_0FBA + 1)
 565 #define REG_VEX_71              (REG_0FC7 + 1)
 566 #define REG_VEX_72              (REG_VEX_71 + 1)
 567 #define REG_VEX_73              (REG_VEX_72 + 1)
 568 #define REG_VEX_AE              (REG_VEX_73 + 1)
 569
 570 #define MOD_8D                  0
 571 #define MOD_0F01_REG_0          (MOD_8D + 1)
 572 #define MOD_0F01_REG_1          (MOD_0F01_REG_0 + 1)
 573 #define MOD_0F01_REG_2          (MOD_0F01_REG_1 + 1)
 574 #define MOD_0F01_REG_3          (MOD_0F01_REG_2 + 1)
 575 #define MOD_0F01_REG_7          (MOD_0F01_REG_3 + 1)
 576 #define MOD_0F12_PREFIX_0       (MOD_0F01_REG_7 + 1)
 577 #define MOD_0F13                (MOD_0F12_PREFIX_0 + 1)
 578 #define MOD_0F16_PREFIX_0       (MOD_0F13 + 1)
 579 #define MOD_0F17                (MOD_0F16_PREFIX_0 + 1)
 580 #define MOD_0F18_REG_0          (MOD_0F17 + 1)
 581 #define MOD_0F18_REG_1          (MOD_0F18_REG_0 + 1)
 582 #define MOD_0F18_REG_2          (MOD_0F18_REG_1 + 1)
 583 #define MOD_0F18_REG_3          (MOD_0F18_REG_2 + 1)
 584 #define MOD_0F20                (MOD_0F18_REG_3 + 1)
 585 #define MOD_0F21                (MOD_0F20 + 1)
 586 #define MOD_0F22                (MOD_0F21 + 1)
 587 #define MOD_0F23                (MOD_0F22 + 1)
 588 #define MOD_0F24                (MOD_0F23 + 1)
 589 #define MOD_0F26                (MOD_0F24 + 1)
 590 #define MOD_0F2B_PREFIX_0       (MOD_0F26 + 1)
 591 #define MOD_0F2B_PREFIX_1       (MOD_0F2B_PREFIX_0 + 1)
 592 #define MOD_0F2B_PREFIX_2       (MOD_0F2B_PREFIX_1 + 1)
 593 #define MOD_0F2B_PREFIX_3       (MOD_0F2B_PREFIX_2 + 1)
 594 #define MOD_0F51                (MOD_0F2B_PREFIX_3 + 1)
 595 #define MOD_0F71_REG_2          (MOD_0F51 + 1)
 596 #define MOD_0F71_REG_4          (MOD_0F71_REG_2 + 1)
 597 #define MOD_0F71_REG_6          (MOD_0F71_REG_4 + 1)
 598 #define MOD_0F72_REG_2          (MOD_0F71_REG_6 + 1)
 599 #define MOD_0F72_REG_4          (MOD_0F72_REG_2 + 1)
 600 #define MOD_0F72_REG_6          (MOD_0F72_REG_4 + 1)
 601 #define MOD_0F73_REG_2          (MOD_0F72_REG_6 + 1)
 602 #define MOD_0F73_REG_3          (MOD_0F73_REG_2 + 1)
 603 #define MOD_0F73_REG_6          (MOD_0F73_REG_3 + 1)
 604 #define MOD_0F73_REG_7          (MOD_0F73_REG_6 + 1)
 605 #define MOD_0FAE_REG_0          (MOD_0F73_REG_7 + 1)
 606 #define MOD_0FAE_REG_1          (MOD_0FAE_REG_0 + 1)
 607 #define MOD_0FAE_REG_2          (MOD_0FAE_REG_1 + 1)
 608 #define MOD_0FAE_REG_3          (MOD_0FAE_REG_2 + 1)
 609 #define MOD_0FAE_REG_4          (MOD_0FAE_REG_3 + 1)
 610 #define MOD_0FAE_REG_5          (MOD_0FAE_REG_4 + 1)
 611 #define MOD_0FAE_REG_6          (MOD_0FAE_REG_5 + 1)
 612 #define MOD_0FAE_REG_7          (MOD_0FAE_REG_6 + 1)
 613 #define MOD_0FB2                (MOD_0FAE_REG_7 + 1)
 614 #define MOD_0FB4                (MOD_0FB2 + 1)
 615 #define MOD_0FB5                (MOD_0FB4 + 1)
 616 #define MOD_0FC7_REG_6          (MOD_0FB5 + 1)
 617 #define MOD_0FC7_REG_7          (MOD_0FC7_REG_6 + 1)
 618 #define MOD_0FD7                (MOD_0FC7_REG_7 + 1)
 619 #define MOD_0FE7_PREFIX_2       (MOD_0FD7 + 1)
 620 #define MOD_0FF0_PREFIX_3       (MOD_0FE7_PREFIX_2 + 1)
 621 #define MOD_0F382A_PREFIX_2     (MOD_0FF0_PREFIX_3 + 1)
 622 #define MOD_62_32BIT            (MOD_0F382A_PREFIX_2 + 1)
 623 #define MOD_C4_32BIT            (MOD_62_32BIT + 1)
 624 #define MOD_C5_32BIT            (MOD_C4_32BIT + 1)
 625 #define MOD_VEX_12_PREFIX_0     (MOD_C5_32BIT + 1)
 626 #define MOD_VEX_13              (MOD_VEX_12_PREFIX_0 + 1)
 627 #define MOD_VEX_16_PREFIX_0     (MOD_VEX_13 + 1)
 628 #define MOD_VEX_17              (MOD_VEX_16_PREFIX_0 + 1)
 629 #define MOD_VEX_2B              (MOD_VEX_17 + 1)
 630 #define MOD_VEX_51              (MOD_VEX_2B + 1)
 631 #define MOD_VEX_71_REG_2        (MOD_VEX_51 + 1)
 632 #define MOD_VEX_71_REG_4        (MOD_VEX_71_REG_2 + 1)
 633 #define MOD_VEX_71_REG_6        (MOD_VEX_71_REG_4 + 1)
 634 #define MOD_VEX_72_REG_2        (MOD_VEX_71_REG_6 + 1)
 635 #define MOD_VEX_72_REG_4        (MOD_VEX_72_REG_2 + 1)
 636 #define MOD_VEX_72_REG_6        (MOD_VEX_72_REG_4 + 1)
 637 #define MOD_VEX_73_REG_2        (MOD_VEX_72_REG_6 + 1)
 638 #define MOD_VEX_73_REG_3        (MOD_VEX_73_REG_2 + 1)
 639 #define MOD_VEX_73_REG_6        (MOD_VEX_73_REG_3 + 1)
 640 #define MOD_VEX_73_REG_7        (MOD_VEX_73_REG_6 + 1)
 641 #define MOD_VEX_AE_REG_2        (MOD_VEX_73_REG_7 + 1)
 642 #define MOD_VEX_AE_REG_3        (MOD_VEX_AE_REG_2 + 1)
 643 #define MOD_VEX_D7_PREFIX_2     (MOD_VEX_AE_REG_3 + 1)
 644 #define MOD_VEX_E7_PREFIX_2     (MOD_VEX_D7_PREFIX_2 + 1)
 645 #define MOD_VEX_F0_PREFIX_3     (MOD_VEX_E7_PREFIX_2 + 1)
 646 #define MOD_VEX_3818_PREFIX_2   (MOD_VEX_F0_PREFIX_3 + 1)
 647 #define MOD_VEX_3819_PREFIX_2   (MOD_VEX_3818_PREFIX_2 + 1)
 648 #define MOD_VEX_381A_PREFIX_2   (MOD_VEX_3819_PREFIX_2 + 1)
 649 #define MOD_VEX_382A_PREFIX_2   (MOD_VEX_381A_PREFIX_2 + 1)
 650 #define MOD_VEX_382C_PREFIX_2   (MOD_VEX_382A_PREFIX_2 + 1)
 651 #define MOD_VEX_382D_PREFIX_2   (MOD_VEX_382C_PREFIX_2 + 1)
 652 #define MOD_VEX_382E_PREFIX_2   (MOD_VEX_382D_PREFIX_2 + 1)
 653 #define MOD_VEX_382F_PREFIX_2   (MOD_VEX_382E_PREFIX_2 + 1)
 654
 655 #define RM_0F01_REG_0           0
 656 #define RM_0F01_REG_1           (RM_0F01_REG_0 + 1)
 657 #define RM_0F01_REG_2           (RM_0F01_REG_1 + 1)
 658 #define RM_0F01_REG_3           (RM_0F01_REG_2 + 1)
 659 #define RM_0F01_REG_7           (RM_0F01_REG_3 + 1)
 660 #define RM_0FAE_REG_5           (RM_0F01_REG_7 + 1)
 661 #define RM_0FAE_REG_6           (RM_0FAE_REG_5 + 1)
 662 #define RM_0FAE_REG_7           (RM_0FAE_REG_6 + 1)
 663
 664 #define PREFIX_90               0
 665 #define PREFIX_0F10             (PREFIX_90 + 1)
 666 #define PREFIX_0F11             (PREFIX_0F10 + 1)
 667 #define PREFIX_0F12             (PREFIX_0F11 + 1)
 668 #define PREFIX_0F16             (PREFIX_0F12 + 1)
 669 #define PREFIX_0F2A             (PREFIX_0F16 + 1)
 670 #define PREFIX_0F2B             (PREFIX_0F2A + 1)
 671 #define PREFIX_0F2C             (PREFIX_0F2B + 1)
 672 #define PREFIX_0F2D             (PREFIX_0F2C + 1)
 673 #define PREFIX_0F2E             (PREFIX_0F2D + 1)
 674 #define PREFIX_0F2F             (PREFIX_0F2E + 1)
 675 #define PREFIX_0F51             (PREFIX_0F2F + 1)
 676 #define PREFIX_0F52             (PREFIX_0F51 + 1)
 677 #define PREFIX_0F53             (PREFIX_0F52 + 1)
 678 #define PREFIX_0F58             (PREFIX_0F53 + 1)
 679 #define PREFIX_0F59             (PREFIX_0F58 + 1)
 680 #define PREFIX_0F5A             (PREFIX_0F59 + 1)
 681 #define PREFIX_0F5B             (PREFIX_0F5A + 1)
 682 #define PREFIX_0F5C             (PREFIX_0F5B + 1)
 683 #define PREFIX_0F5D             (PREFIX_0F5C + 1)
 684 #define PREFIX_0F5E             (PREFIX_0F5D + 1)
 685 #define PREFIX_0F5F             (PREFIX_0F5E + 1)
 686 #define PREFIX_0F60             (PREFIX_0F5F + 1)
 687 #define PREFIX_0F61             (PREFIX_0F60 + 1)
 688 #define PREFIX_0F62             (PREFIX_0F61 + 1)
 689 #define PREFIX_0F6C             (PREFIX_0F62 + 1)
 690 #define PREFIX_0F6D             (PREFIX_0F6C + 1)
 691 #define PREFIX_0F6F             (PREFIX_0F6D + 1)
 692 #define PREFIX_0F70             (PREFIX_0F6F + 1)
 693 #define PREFIX_0F73_REG_3       (PREFIX_0F70 + 1)
 694 #define PREFIX_0F73_REG_7       (PREFIX_0F73_REG_3 + 1)
 695 #define PREFIX_0F78             (PREFIX_0F73_REG_7 + 1)
 696 #define PREFIX_0F79             (PREFIX_0F78 + 1)
 697 #define PREFIX_0F7C             (PREFIX_0F79 + 1)
 698 #define PREFIX_0F7D             (PREFIX_0F7C + 1)
 699 #define PREFIX_0F7E             (PREFIX_0F7D + 1)
 700 #define PREFIX_0F7F             (PREFIX_0F7E + 1)
 701 #define PREFIX_0FB8             (PREFIX_0F7F + 1)
 702 #define PREFIX_0FBD             (PREFIX_0FB8 + 1)
 703 #define PREFIX_0FC2             (PREFIX_0FBD + 1)
 704 #define PREFIX_0FC3             (PREFIX_0FC2 + 1)
 705 #define PREFIX_0FC7_REG_6       (PREFIX_0FC3 + 1)
 706 #define PREFIX_0FD0             (PREFIX_0FC7_REG_6 + 1)
 707 #define PREFIX_0FD6             (PREFIX_0FD0 + 1)
 708 #define PREFIX_0FE6             (PREFIX_0FD6 + 1)
 709 #define PREFIX_0FE7             (PREFIX_0FE6 + 1)
 710 #define PREFIX_0FF0             (PREFIX_0FE7 + 1)
 711 #define PREFIX_0FF7             (PREFIX_0FF0 + 1)
 712 #define PREFIX_0F3810           (PREFIX_0FF7 + 1)
 713 #define PREFIX_0F3814           (PREFIX_0F3810 + 1)
 714 #define PREFIX_0F3815           (PREFIX_0F3814 + 1)
 715 #define PREFIX_0F3817           (PREFIX_0F3815 + 1)
 716 #define PREFIX_0F3820           (PREFIX_0F3817 + 1)
 717 #define PREFIX_0F3821           (PREFIX_0F3820 + 1)
 718 #define PREFIX_0F3822           (PREFIX_0F3821 + 1)
 719 #define PREFIX_0F3823           (PREFIX_0F3822 + 1)
 720 #define PREFIX_0F3824           (PREFIX_0F3823 + 1)
 721 #define PREFIX_0F3825           (PREFIX_0F3824 + 1)
 722 #define PREFIX_0F3828           (PREFIX_0F3825 + 1)
 723 #define PREFIX_0F3829           (PREFIX_0F3828 + 1)
 724 #define PREFIX_0F382A           (PREFIX_0F3829 + 1)
 725 #define PREFIX_0F382B           (PREFIX_0F382A + 1)
 726 #define PREFIX_0F3830           (PREFIX_0F382B + 1)
 727 #define PREFIX_0F3831           (PREFIX_0F3830 + 1)
 728 #define PREFIX_0F3832           (PREFIX_0F3831 + 1)
 729 #define PREFIX_0F3833           (PREFIX_0F3832 + 1)
 730 #define PREFIX_0F3834           (PREFIX_0F3833 + 1)
 731 #define PREFIX_0F3835           (PREFIX_0F3834 + 1)
 732 #define PREFIX_0F3837           (PREFIX_0F3835 + 1)
 733 #define PREFIX_0F3838           (PREFIX_0F3837 + 1)
 734 #define PREFIX_0F3839           (PREFIX_0F3838 + 1)
 735 #define PREFIX_0F383A           (PREFIX_0F3839 + 1)
 736 #define PREFIX_0F383B           (PREFIX_0F383A + 1)
 737 #define PREFIX_0F383C           (PREFIX_0F383B + 1)
 738 #define PREFIX_0F383D           (PREFIX_0F383C + 1)
 739 #define PREFIX_0F383E           (PREFIX_0F383D + 1)
 740 #define PREFIX_0F383F           (PREFIX_0F383E + 1)
 741 #define PREFIX_0F3840           (PREFIX_0F383F + 1)
 742 #define PREFIX_0F3841           (PREFIX_0F3840 + 1)
 743 #define PREFIX_0F38DB           (PREFIX_0F3841 + 1)
 744 #define PREFIX_0F38DC           (PREFIX_0F38DB + 1)
 745 #define PREFIX_0F38DD           (PREFIX_0F38DC + 1)
 746 #define PREFIX_0F38DE           (PREFIX_0F38DD + 1)
 747 #define PREFIX_0F38DF           (PREFIX_0F38DE + 1)
 748 #define PREFIX_0F38F0           (PREFIX_0F38DF + 1)
 749 #define PREFIX_0F38F1           (PREFIX_0F38F0 + 1)
 750 #define PREFIX_0F3A08           (PREFIX_0F38F1 + 1)
 751 #define PREFIX_0F3A09           (PREFIX_0F3A08 + 1)
 752 #define PREFIX_0F3A0A           (PREFIX_0F3A09 + 1)
 753 #define PREFIX_0F3A0B           (PREFIX_0F3A0A + 1)
 754 #define PREFIX_0F3A0C           (PREFIX_0F3A0B + 1)
 755 #define PREFIX_0F3A0D           (PREFIX_0F3A0C + 1)
 756 #define PREFIX_0F3A0E           (PREFIX_0F3A0D + 1)
 757 #define PREFIX_0F3A14           (PREFIX_0F3A0E + 1)
 758 #define PREFIX_0F3A15           (PREFIX_0F3A14 + 1)
 759 #define PREFIX_0F3A16           (PREFIX_0F3A15 + 1)
 760 #define PREFIX_0F3A17           (PREFIX_0F3A16 + 1)
 761 #define PREFIX_0F3A20           (PREFIX_0F3A17 + 1)
 762 #define PREFIX_0F3A21           (PREFIX_0F3A20 + 1)
 763 #define PREFIX_0F3A22           (PREFIX_0F3A21 + 1)
 764 #define PREFIX_0F3A40           (PREFIX_0F3A22 + 1)
 765 #define PREFIX_0F3A41           (PREFIX_0F3A40 + 1)
 766 #define PREFIX_0F3A42           (PREFIX_0F3A41 + 1)
 767 #define PREFIX_0F3A44           (PREFIX_0F3A42 + 1)
 768 #define PREFIX_0F3A60           (PREFIX_0F3A44 + 1)
 769 #define PREFIX_0F3A61           (PREFIX_0F3A60 + 1)
 770 #define PREFIX_0F3A62           (PREFIX_0F3A61 + 1)
 771 #define PREFIX_0F3A63           (PREFIX_0F3A62 + 1)
 772 #define PREFIX_0F3ADF           (PREFIX_0F3A63 + 1)
 773 #define PREFIX_VEX_10           (PREFIX_0F3ADF + 1)
 774 #define PREFIX_VEX_11           (PREFIX_VEX_10 + 1)
 775 #define PREFIX_VEX_12           (PREFIX_VEX_11 + 1)
 776 #define PREFIX_VEX_16           (PREFIX_VEX_12 + 1)
 777 #define PREFIX_VEX_2A           (PREFIX_VEX_16 + 1)
 778 #define PREFIX_VEX_2C           (PREFIX_VEX_2A + 1)
 779 #define PREFIX_VEX_2D           (PREFIX_VEX_2C + 1)
 780 #define PREFIX_VEX_2E           (PREFIX_VEX_2D + 1)
 781 #define PREFIX_VEX_2F           (PREFIX_VEX_2E + 1)
 782 #define PREFIX_VEX_51           (PREFIX_VEX_2F + 1)
 783 #define PREFIX_VEX_52           (PREFIX_VEX_51 + 1)
 784 #define PREFIX_VEX_53           (PREFIX_VEX_52 + 1)
 785 #define PREFIX_VEX_58           (PREFIX_VEX_53 + 1)
 786 #define PREFIX_VEX_59           (PREFIX_VEX_58 + 1)
 787 #define PREFIX_VEX_5A           (PREFIX_VEX_59 + 1)
 788 #define PREFIX_VEX_5B           (PREFIX_VEX_5A + 1)
 789 #define PREFIX_VEX_5C           (PREFIX_VEX_5B + 1)
 790 #define PREFIX_VEX_5D           (PREFIX_VEX_5C + 1)
 791 #define PREFIX_VEX_5E           (PREFIX_VEX_5D + 1)
 792 #define PREFIX_VEX_5F           (PREFIX_VEX_5E + 1)
 793 #define PREFIX_VEX_60           (PREFIX_VEX_5F + 1)
 794 #define PREFIX_VEX_61           (PREFIX_VEX_60 + 1)
 795 #define PREFIX_VEX_62           (PREFIX_VEX_61 + 1)
 796 #define PREFIX_VEX_63           (PREFIX_VEX_62 + 1)
 797 #define PREFIX_VEX_64           (PREFIX_VEX_63 + 1)
 798 #define PREFIX_VEX_65           (PREFIX_VEX_64 + 1)
 799 #define PREFIX_VEX_66           (PREFIX_VEX_65 + 1)
 800 #define PREFIX_VEX_67           (PREFIX_VEX_66 + 1)
 801 #define PREFIX_VEX_68           (PREFIX_VEX_67 + 1)
 802 #define PREFIX_VEX_69           (PREFIX_VEX_68 + 1)
 803 #define PREFIX_VEX_6A           (PREFIX_VEX_69 + 1)
 804 #define PREFIX_VEX_6B           (PREFIX_VEX_6A + 1)
 805 #define PREFIX_VEX_6C           (PREFIX_VEX_6B + 1)
 806 #define PREFIX_VEX_6D           (PREFIX_VEX_6C + 1)
 807 #define PREFIX_VEX_6E           (PREFIX_VEX_6D + 1)
 808 #define PREFIX_VEX_6F           (PREFIX_VEX_6E + 1)
 809 #define PREFIX_VEX_70           (PREFIX_VEX_6F + 1)
 810 #define PREFIX_VEX_71_REG_2     (PREFIX_VEX_70 + 1)
 811 #define PREFIX_VEX_71_REG_4     (PREFIX_VEX_71_REG_2 + 1)
 812 #define PREFIX_VEX_71_REG_6     (PREFIX_VEX_71_REG_4 + 1)
 813 #define PREFIX_VEX_72_REG_2     (PREFIX_VEX_71_REG_6 + 1)
 814 #define PREFIX_VEX_72_REG_4     (PREFIX_VEX_72_REG_2 + 1)
 815 #define PREFIX_VEX_72_REG_6     (PREFIX_VEX_72_REG_4 + 1)
 816 #define PREFIX_VEX_73_REG_2     (PREFIX_VEX_72_REG_6 + 1)
 817 #define PREFIX_VEX_73_REG_3     (PREFIX_VEX_73_REG_2 + 1)
 818 #define PREFIX_VEX_73_REG_6     (PREFIX_VEX_73_REG_3 + 1)
 819 #define PREFIX_VEX_73_REG_7     (PREFIX_VEX_73_REG_6 + 1)
 820 #define PREFIX_VEX_74           (PREFIX_VEX_73_REG_7 + 1)
 821 #define PREFIX_VEX_75           (PREFIX_VEX_74 + 1)
 822 #define PREFIX_VEX_76           (PREFIX_VEX_75 + 1)
 823 #define PREFIX_VEX_77           (PREFIX_VEX_76 + 1)
 824 #define PREFIX_VEX_7C           (PREFIX_VEX_77 + 1)
 825 #define PREFIX_VEX_7D           (PREFIX_VEX_7C + 1)
 826 #define PREFIX_VEX_7E           (PREFIX_VEX_7D + 1)
 827 #define PREFIX_VEX_7F           (PREFIX_VEX_7E + 1)
 828 #define PREFIX_VEX_C2           (PREFIX_VEX_7F + 1)
 829 #define PREFIX_VEX_C4           (PREFIX_VEX_C2 + 1)
 830 #define PREFIX_VEX_C5           (PREFIX_VEX_C4 + 1)
 831 #define PREFIX_VEX_D0           (PREFIX_VEX_C5 + 1)
 832 #define PREFIX_VEX_D1           (PREFIX_VEX_D0 + 1)
 833 #define PREFIX_VEX_D2           (PREFIX_VEX_D1 + 1)
 834 #define PREFIX_VEX_D3           (PREFIX_VEX_D2 + 1)
 835 #define PREFIX_VEX_D4           (PREFIX_VEX_D3 + 1)
 836 #define PREFIX_VEX_D5           (PREFIX_VEX_D4 + 1)
 837 #define PREFIX_VEX_D6           (PREFIX_VEX_D5 + 1)
 838 #define PREFIX_VEX_D7           (PREFIX_VEX_D6 + 1)
 839 #define PREFIX_VEX_D8           (PREFIX_VEX_D7 + 1)
 840 #define PREFIX_VEX_D9           (PREFIX_VEX_D8 + 1)
 841 #define PREFIX_VEX_DA           (PREFIX_VEX_D9 + 1)
 842 #define PREFIX_VEX_DB           (PREFIX_VEX_DA + 1)
 843 #define PREFIX_VEX_DC           (PREFIX_VEX_DB + 1)
 844 #define PREFIX_VEX_DD           (PREFIX_VEX_DC + 1)
 845 #define PREFIX_VEX_DE           (PREFIX_VEX_DD + 1)
 846 #define PREFIX_VEX_DF           (PREFIX_VEX_DE + 1)
 847 #define PREFIX_VEX_E0           (PREFIX_VEX_DF + 1)
 848 #define PREFIX_VEX_E1           (PREFIX_VEX_E0 + 1)
 849 #define PREFIX_VEX_E2           (PREFIX_VEX_E1 + 1)
 850 #define PREFIX_VEX_E3           (PREFIX_VEX_E2 + 1)
 851 #define PREFIX_VEX_E4           (PREFIX_VEX_E3 + 1)
 852 #define PREFIX_VEX_E5           (PREFIX_VEX_E4 + 1)
 853 #define PREFIX_VEX_E6           (PREFIX_VEX_E5 + 1)
 854 #define PREFIX_VEX_E7           (PREFIX_VEX_E6 + 1)
 855 #define PREFIX_VEX_E8           (PREFIX_VEX_E7 + 1)
 856 #define PREFIX_VEX_E9           (PREFIX_VEX_E8 + 1)
 857 #define PREFIX_VEX_EA           (PREFIX_VEX_E9 + 1)
 858 #define PREFIX_VEX_EB           (PREFIX_VEX_EA + 1)
 859 #define PREFIX_VEX_EC           (PREFIX_VEX_EB + 1)
 860 #define PREFIX_VEX_ED           (PREFIX_VEX_EC + 1)
 861 #define PREFIX_VEX_EE           (PREFIX_VEX_ED + 1)
 862 #define PREFIX_VEX_EF           (PREFIX_VEX_EE + 1)
 863 #define PREFIX_VEX_F0           (PREFIX_VEX_EF + 1)
 864 #define PREFIX_VEX_F1           (PREFIX_VEX_F0 + 1)
 865 #define PREFIX_VEX_F2           (PREFIX_VEX_F1 + 1)
 866 #define PREFIX_VEX_F3           (PREFIX_VEX_F2 + 1)
 867 #define PREFIX_VEX_F4           (PREFIX_VEX_F3 + 1)
 868 #define PREFIX_VEX_F5           (PREFIX_VEX_F4 + 1)
 869 #define PREFIX_VEX_F6           (PREFIX_VEX_F5 + 1)
 870 #define PREFIX_VEX_F7           (PREFIX_VEX_F6 + 1)
 871 #define PREFIX_VEX_F8           (PREFIX_VEX_F7 + 1)
 872 #define PREFIX_VEX_F9           (PREFIX_VEX_F8 + 1)
 873 #define PREFIX_VEX_FA           (PREFIX_VEX_F9 + 1)
 874 #define PREFIX_VEX_FB           (PREFIX_VEX_FA + 1)
 875 #define PREFIX_VEX_FC           (PREFIX_VEX_FB + 1)
 876 #define PREFIX_VEX_FD           (PREFIX_VEX_FC + 1)
 877 #define PREFIX_VEX_FE           (PREFIX_VEX_FD + 1)
 878 #define PREFIX_VEX_3800 (PREFIX_VEX_FE + 1)
 879 #define PREFIX_VEX_3801 (PREFIX_VEX_3800 + 1)
 880 #define PREFIX_VEX_3802 (PREFIX_VEX_3801 + 1)
 881 #define PREFIX_VEX_3803 (PREFIX_VEX_3802 + 1)
 882 #define PREFIX_VEX_3804 (PREFIX_VEX_3803 + 1)
 883 #define PREFIX_VEX_3805 (PREFIX_VEX_3804 + 1)
 884 #define PREFIX_VEX_3806 (PREFIX_VEX_3805 + 1)
 885 #define PREFIX_VEX_3807 (PREFIX_VEX_3806 + 1)
 886 #define PREFIX_VEX_3808 (PREFIX_VEX_3807 + 1)
 887 #define PREFIX_VEX_3809 (PREFIX_VEX_3808 + 1)
 888 #define PREFIX_VEX_380A (PREFIX_VEX_3809 + 1)
 889 #define PREFIX_VEX_380B (PREFIX_VEX_380A + 1)
 890 #define PREFIX_VEX_380C (PREFIX_VEX_380B + 1)
 891 #define PREFIX_VEX_380D (PREFIX_VEX_380C + 1)
 892 #define PREFIX_VEX_380E (PREFIX_VEX_380D + 1)
 893 #define PREFIX_VEX_380F (PREFIX_VEX_380E + 1)
 894 #define PREFIX_VEX_3817 (PREFIX_VEX_380F + 1)
 895 #define PREFIX_VEX_3818 (PREFIX_VEX_3817 + 1)
 896 #define PREFIX_VEX_3819 (PREFIX_VEX_3818 + 1)
 897 #define PREFIX_VEX_381A (PREFIX_VEX_3819 + 1)
 898 #define PREFIX_VEX_381C (PREFIX_VEX_381A + 1)
 899 #define PREFIX_VEX_381D (PREFIX_VEX_381C + 1)
 900 #define PREFIX_VEX_381E (PREFIX_VEX_381D + 1)
 901 #define PREFIX_VEX_3820 (PREFIX_VEX_381E + 1)
 902 #define PREFIX_VEX_3821 (PREFIX_VEX_3820 + 1)
 903 #define PREFIX_VEX_3822 (PREFIX_VEX_3821 + 1)
 904 #define PREFIX_VEX_3823 (PREFIX_VEX_3822 + 1)
 905 #define PREFIX_VEX_3824 (PREFIX_VEX_3823 + 1)
 906 #define PREFIX_VEX_3825 (PREFIX_VEX_3824 + 1)
 907 #define PREFIX_VEX_3828 (PREFIX_VEX_3825 + 1)
 908 #define PREFIX_VEX_3829 (PREFIX_VEX_3828 + 1)
 909 #define PREFIX_VEX_382A (PREFIX_VEX_3829 + 1)
 910 #define PREFIX_VEX_382B (PREFIX_VEX_382A + 1)
 911 #define PREFIX_VEX_382C (PREFIX_VEX_382B + 1)
 912 #define PREFIX_VEX_382D (PREFIX_VEX_382C + 1)
 913 #define PREFIX_VEX_382E (PREFIX_VEX_382D + 1)
 914 #define PREFIX_VEX_382F (PREFIX_VEX_382E + 1)
 915 #define PREFIX_VEX_3830 (PREFIX_VEX_382F + 1)
 916 #define PREFIX_VEX_3831 (PREFIX_VEX_3830 + 1)
 917 #define PREFIX_VEX_3832 (PREFIX_VEX_3831 + 1)
 918 #define PREFIX_VEX_3833 (PREFIX_VEX_3832 + 1)
 919 #define PREFIX_VEX_3834 (PREFIX_VEX_3833 + 1)
 920 #define PREFIX_VEX_3835 (PREFIX_VEX_3834 + 1)
 921 #define PREFIX_VEX_3837 (PREFIX_VEX_3835 + 1)
 922 #define PREFIX_VEX_3838 (PREFIX_VEX_3837 + 1)
 923 #define PREFIX_VEX_3839 (PREFIX_VEX_3838 + 1)
 924 #define PREFIX_VEX_383A (PREFIX_VEX_3839 + 1)
 925 #define PREFIX_VEX_383B (PREFIX_VEX_383A + 1)
 926 #define PREFIX_VEX_383C (PREFIX_VEX_383B + 1)
 927 #define PREFIX_VEX_383D (PREFIX_VEX_383C + 1)
 928 #define PREFIX_VEX_383E (PREFIX_VEX_383D + 1)
 929 #define PREFIX_VEX_383F (PREFIX_VEX_383E + 1)
 930 #define PREFIX_VEX_3840 (PREFIX_VEX_383F + 1)
 931 #define PREFIX_VEX_3841 (PREFIX_VEX_3840 + 1)
 932 #define PREFIX_VEX_3A04 (PREFIX_VEX_3841 + 1)
 933 #define PREFIX_VEX_3A05 (PREFIX_VEX_3A04 + 1)
 934 #define PREFIX_VEX_3A06 (PREFIX_VEX_3A05 + 1)
 935 #define PREFIX_VEX_3A08 (PREFIX_VEX_3A06 + 1)
 936 #define PREFIX_VEX_3A09 (PREFIX_VEX_3A08 + 1)
 937 #define PREFIX_VEX_3A0A (PREFIX_VEX_3A09 + 1)
 938 #define PREFIX_VEX_3A0B (PREFIX_VEX_3A0A + 1)
 939 #define PREFIX_VEX_3A0C (PREFIX_VEX_3A0B + 1)
 940 #define PREFIX_VEX_3A0D (PREFIX_VEX_3A0C + 1)
 941 #define PREFIX_VEX_3A0E (PREFIX_VEX_3A0D + 1)
 942 #define PREFIX_VEX_3A0F (PREFIX_VEX_3A0E + 1)
 943 #define PREFIX_VEX_3A14 (PREFIX_VEX_3A0F + 1)
 944 #define PREFIX_VEX_3A15 (PREFIX_VEX_3A14 + 1)
 945 #define PREFIX_VEX_3A16 (PREFIX_VEX_3A15 + 1)
 946 #define PREFIX_VEX_3A17 (PREFIX_VEX_3A16 + 1)
 947 #define PREFIX_VEX_3A18 (PREFIX_VEX_3A17 + 1)
 948 #define PREFIX_VEX_3A19 (PREFIX_VEX_3A18 + 1)
 949 #define PREFIX_VEX_3A20 (PREFIX_VEX_3A19 + 1)
 950 #define PREFIX_VEX_3A21 (PREFIX_VEX_3A20 + 1)
 951 #define PREFIX_VEX_3A22 (PREFIX_VEX_3A21 + 1)
 952 #define PREFIX_VEX_3A40 (PREFIX_VEX_3A22 + 1)
 953 #define PREFIX_VEX_3A41 (PREFIX_VEX_3A40 + 1)
 954 #define PREFIX_VEX_3A42 (PREFIX_VEX_3A41 + 1)
 955 #define PREFIX_VEX_3A48 (PREFIX_VEX_3A42 + 1)
 956 #define PREFIX_VEX_3A49 (PREFIX_VEX_3A48 + 1)
 957 #define PREFIX_VEX_3A4A (PREFIX_VEX_3A49 + 1)
 958 #define PREFIX_VEX_3A4B (PREFIX_VEX_3A4A + 1)
 959 #define PREFIX_VEX_3A4C (PREFIX_VEX_3A4B + 1)
 960 #define PREFIX_VEX_3A5C (PREFIX_VEX_3A4C + 1)
 961 #define PREFIX_VEX_3A5D (PREFIX_VEX_3A5C + 1)
 962 #define PREFIX_VEX_3A5E (PREFIX_VEX_3A5D + 1)
 963 #define PREFIX_VEX_3A5F (PREFIX_VEX_3A5E + 1)
 964 #define PREFIX_VEX_3A60 (PREFIX_VEX_3A5F + 1)
 965 #define PREFIX_VEX_3A61 (PREFIX_VEX_3A60 + 1)
 966 #define PREFIX_VEX_3A62 (PREFIX_VEX_3A61 + 1)
 967 #define PREFIX_VEX_3A63 (PREFIX_VEX_3A62 + 1)
 968 #define PREFIX_VEX_3A68 (PREFIX_VEX_3A63 + 1)
 969 #define PREFIX_VEX_3A69 (PREFIX_VEX_3A68 + 1)
 970 #define PREFIX_VEX_3A6A (PREFIX_VEX_3A69 + 1)
 971 #define PREFIX_VEX_3A6B (PREFIX_VEX_3A6A + 1)
 972 #define PREFIX_VEX_3A6C (PREFIX_VEX_3A6B + 1)
 973 #define PREFIX_VEX_3A6D (PREFIX_VEX_3A6C + 1)
 974 #define PREFIX_VEX_3A6E (PREFIX_VEX_3A6D + 1)
 975 #define PREFIX_VEX_3A6F (PREFIX_VEX_3A6E + 1)
 976 #define PREFIX_VEX_3A78 (PREFIX_VEX_3A6F + 1)
 977 #define PREFIX_VEX_3A79 (PREFIX_VEX_3A78 + 1)
 978 #define PREFIX_VEX_3A7A (PREFIX_VEX_3A79 + 1)
 979 #define PREFIX_VEX_3A7B (PREFIX_VEX_3A7A + 1)
 980 #define PREFIX_VEX_3A7C (PREFIX_VEX_3A7B + 1)
 981 #define PREFIX_VEX_3A7D (PREFIX_VEX_3A7C + 1)
 982 #define PREFIX_VEX_3A7E (PREFIX_VEX_3A7D + 1)
 983 #define PREFIX_VEX_3A7F (PREFIX_VEX_3A7E + 1)
 984
 985 #define X86_64_06               0
 986 #define X86_64_07               (X86_64_06 + 1)
 987 #define X86_64_0D               (X86_64_07 + 1)
 988 #define X86_64_16               (X86_64_0D + 1)
 989 #define X86_64_17               (X86_64_16 + 1)
 990 #define X86_64_1E               (X86_64_17 + 1)
 991 #define X86_64_1F               (X86_64_1E + 1)
 992 #define X86_64_27               (X86_64_1F + 1)
 993 #define X86_64_2F               (X86_64_27 + 1)
 994 #define X86_64_37               (X86_64_2F + 1)
 995 #define X86_64_3F               (X86_64_37 + 1)
 996 #define X86_64_60               (X86_64_3F + 1)
 997 #define X86_64_61               (X86_64_60 + 1)
 998 #define X86_64_62               (X86_64_61 + 1)
 999 #define X86_64_63               (X86_64_62 + 1)
1000 #define X86_64_6D               (X86_64_63 + 1)
1001 #define X86_64_6F               (X86_64_6D + 1)
1002 #define X86_64_9A               (X86_64_6F + 1)
1003 #define X86_64_C4               (X86_64_9A + 1)
1004 #define X86_64_C5               (X86_64_C4 + 1)
1005 #define X86_64_CE               (X86_64_C5 + 1)
1006 #define X86_64_D4               (X86_64_CE + 1)
1007 #define X86_64_D5               (X86_64_D4 + 1)
1008 #define X86_64_EA               (X86_64_D5 + 1)
1009 #define X86_64_0F01_REG_0       (X86_64_EA + 1)
1010 #define X86_64_0F01_REG_1       (X86_64_0F01_REG_0 + 1)
1011 #define X86_64_0F01_REG_2       (X86_64_0F01_REG_1 + 1)
1012 #define X86_64_0F01_REG_3       (X86_64_0F01_REG_2 + 1)
1013
1014 #define THREE_BYTE_0F24         0
1015 #define THREE_BYTE_0F25         (THREE_BYTE_0F24 + 1)
1016 #define THREE_BYTE_0F38         (THREE_BYTE_0F25 + 1)
1017 #define THREE_BYTE_0F3A         (THREE_BYTE_0F38 + 1)
1018 #define THREE_BYTE_0F7A         (THREE_BYTE_0F3A + 1)
1019 #define THREE_BYTE_0F7B         (THREE_BYTE_0F7A + 1)
1020
1021 #define VEX_0F                  0
1022 #define VEX_0F38                (VEX_0F + 1)
1023 #define VEX_0F3A                (VEX_0F38 + 1)
1024
1025 #define VEX_LEN_10_P_1  0
1026 #define VEX_LEN_10_P_3  (VEX_LEN_10_P_1 + 1)
1027 #define VEX_LEN_11_P_1  (VEX_LEN_10_P_3 + 1)
1028 #define VEX_LEN_11_P_3  (VEX_LEN_11_P_1 + 1)
1029 #define VEX_LEN_12_P_0_M_0      (VEX_LEN_11_P_3 + 1)
1030 #define VEX_LEN_12_P_0_M_1      (VEX_LEN_12_P_0_M_0 + 1)
1031 #define VEX_LEN_12_P_2  (VEX_LEN_12_P_0_M_1 + 1)
1032 #define VEX_LEN_13_M_0  (VEX_LEN_12_P_2 + 1)
1033 #define VEX_LEN_16_P_0_M_0      (VEX_LEN_13_M_0 + 1)
1034 #define VEX_LEN_16_P_0_M_1      (VEX_LEN_16_P_0_M_0 + 1)
1035 #define VEX_LEN_16_P_2  (VEX_LEN_16_P_0_M_1 + 1)
1036 #define VEX_LEN_17_M_0  (VEX_LEN_16_P_2 + 1)
1037 #define VEX_LEN_2A_P_1  (VEX_LEN_17_M_0 + 1)
1038 #define VEX_LEN_2A_P_3  (VEX_LEN_2A_P_1 + 1)
1039 #define VEX_LEN_2B_M_0  (VEX_LEN_2A_P_3 + 1)
1040 #define VEX_LEN_2C_P_1  (VEX_LEN_2B_M_0 + 1)
1041 #define VEX_LEN_2C_P_3  (VEX_LEN_2C_P_1 + 1)
1042 #define VEX_LEN_2D_P_1  (VEX_LEN_2C_P_3 + 1)
1043 #define VEX_LEN_2D_P_3  (VEX_LEN_2D_P_1 + 1)
1044 #define VEX_LEN_2E_P_0  (VEX_LEN_2D_P_3 + 1)
1045 #define VEX_LEN_2E_P_2  (VEX_LEN_2E_P_0 + 1)
1046 #define VEX_LEN_2F_P_0  (VEX_LEN_2E_P_2 + 1)
1047 #define VEX_LEN_2F_P_2  (VEX_LEN_2F_P_0 + 1)
1048 #define VEX_LEN_51_P_1  (VEX_LEN_2F_P_2 + 1)
1049 #define VEX_LEN_51_P_3  (VEX_LEN_51_P_1 + 1)
1050 #define VEX_LEN_52_P_1  (VEX_LEN_51_P_3 + 1)
1051 #define VEX_LEN_53_P_1  (VEX_LEN_52_P_1 + 1)
1052 #define VEX_LEN_58_P_1  (VEX_LEN_53_P_1 + 1)
1053 #define VEX_LEN_58_P_3  (VEX_LEN_58_P_1 + 1)
1054 #define VEX_LEN_59_P_1  (VEX_LEN_58_P_3 + 1)
1055 #define VEX_LEN_59_P_3  (VEX_LEN_59_P_1 + 1)
1056 #define VEX_LEN_5A_P_1  (VEX_LEN_59_P_3 + 1)
1057 #define VEX_LEN_5A_P_3  (VEX_LEN_5A_P_1 + 1)
1058 #define VEX_LEN_5C_P_1  (VEX_LEN_5A_P_3 + 1)
1059 #define VEX_LEN_5C_P_3  (VEX_LEN_5C_P_1 + 1)
1060 #define VEX_LEN_5D_P_1  (VEX_LEN_5C_P_3 + 1)
1061 #define VEX_LEN_5D_P_3  (VEX_LEN_5D_P_1 + 1)
1062 #define VEX_LEN_5E_P_1  (VEX_LEN_5D_P_3 + 1)
1063 #define VEX_LEN_5E_P_3  (VEX_LEN_5E_P_1 + 1)
1064 #define VEX_LEN_5F_P_1  (VEX_LEN_5E_P_3 + 1)
1065 #define VEX_LEN_5F_P_3  (VEX_LEN_5F_P_1 + 1)
1066 #define VEX_LEN_60_P_2  (VEX_LEN_5F_P_3 + 1)
1067 #define VEX_LEN_61_P_2  (VEX_LEN_60_P_2 + 1)
1068 #define VEX_LEN_62_P_2  (VEX_LEN_61_P_2 + 1)
1069 #define VEX_LEN_63_P_2  (VEX_LEN_62_P_2 + 1)
1070 #define VEX_LEN_64_P_2  (VEX_LEN_63_P_2 + 1)
1071 #define VEX_LEN_65_P_2  (VEX_LEN_64_P_2 + 1)
1072 #define VEX_LEN_66_P_2  (VEX_LEN_65_P_2 + 1)
1073 #define VEX_LEN_67_P_2  (VEX_LEN_66_P_2 + 1)
1074 #define VEX_LEN_68_P_2  (VEX_LEN_67_P_2 + 1)
1075 #define VEX_LEN_69_P_2  (VEX_LEN_68_P_2 + 1)
1076 #define VEX_LEN_6A_P_2  (VEX_LEN_69_P_2 + 1)
1077 #define VEX_LEN_6B_P_2  (VEX_LEN_6A_P_2 + 1)
1078 #define VEX_LEN_6C_P_2  (VEX_LEN_6B_P_2 + 1)
1079 #define VEX_LEN_6D_P_2  (VEX_LEN_6C_P_2 + 1)
1080 #define VEX_LEN_6E_P_2  (VEX_LEN_6D_P_2 + 1)
1081 #define VEX_LEN_70_P_1  (VEX_LEN_6E_P_2 + 1)
1082 #define VEX_LEN_70_P_2  (VEX_LEN_70_P_1 + 1)
1083 #define VEX_LEN_70_P_3  (VEX_LEN_70_P_2 + 1)
1084 #define VEX_LEN_71_R_2_P_2      (VEX_LEN_70_P_3 + 1)
1085 #define VEX_LEN_71_R_4_P_2      (VEX_LEN_71_R_2_P_2 + 1)
1086 #define VEX_LEN_71_R_6_P_2      (VEX_LEN_71_R_4_P_2 + 1)
1087 #define VEX_LEN_72_R_2_P_2      (VEX_LEN_71_R_6_P_2 + 1)
1088 #define VEX_LEN_72_R_4_P_2      (VEX_LEN_72_R_2_P_2 + 1)
1089 #define VEX_LEN_72_R_6_P_2      (VEX_LEN_72_R_4_P_2 + 1)
1090 #define VEX_LEN_73_R_2_P_2      (VEX_LEN_72_R_6_P_2 + 1)
1091 #define VEX_LEN_73_R_3_P_2      (VEX_LEN_73_R_2_P_2 + 1)
1092 #define VEX_LEN_73_R_6_P_2      (VEX_LEN_73_R_3_P_2 + 1)
1093 #define VEX_LEN_73_R_7_P_2      (VEX_LEN_73_R_6_P_2 + 1)
1094 #define VEX_LEN_74_P_2  (VEX_LEN_73_R_7_P_2 + 1)
1095 #define VEX_LEN_75_P_2  (VEX_LEN_74_P_2 + 1)
1096 #define VEX_LEN_76_P_2  (VEX_LEN_75_P_2 + 1)
1097 #define VEX_LEN_7E_P_1  (VEX_LEN_76_P_2 + 1)
1098 #define VEX_LEN_7E_P_2  (VEX_LEN_7E_P_1 + 1)
1099 #define VEX_LEN_AE_R_2_M_0      (VEX_LEN_7E_P_2 + 1)
1100 #define VEX_LEN_AE_R_3_M_0      (VEX_LEN_AE_R_2_M_0 + 1)
1101 #define VEX_LEN_C2_P_1  (VEX_LEN_AE_R_3_M_0 + 1)
1102 #define VEX_LEN_C2_P_3  (VEX_LEN_C2_P_1 + 1)
1103 #define VEX_LEN_C4_P_2  (VEX_LEN_C2_P_3 + 1)
1104 #define VEX_LEN_C5_P_2  (VEX_LEN_C4_P_2 + 1)
1105 #define VEX_LEN_D1_P_2  (VEX_LEN_C5_P_2 + 1)
1106 #define VEX_LEN_D2_P_2  (VEX_LEN_D1_P_2 + 1)
1107 #define VEX_LEN_D3_P_2  (VEX_LEN_D2_P_2 + 1)
1108 #define VEX_LEN_D4_P_2  (VEX_LEN_D3_P_2 + 1)
1109 #define VEX_LEN_D5_P_2  (VEX_LEN_D4_P_2 + 1)
1110 #define VEX_LEN_D6_P_2  (VEX_LEN_D5_P_2 + 1)
1111 #define VEX_LEN_D7_P_2_M_1      (VEX_LEN_D6_P_2 + 1)
1112 #define VEX_LEN_D8_P_2  (VEX_LEN_D7_P_2_M_1 + 1)
1113 #define VEX_LEN_D9_P_2  (VEX_LEN_D8_P_2 + 1)
1114 #define VEX_LEN_DA_P_2  (VEX_LEN_D9_P_2 + 1)
1115 #define VEX_LEN_DB_P_2  (VEX_LEN_DA_P_2 + 1)
1116 #define VEX_LEN_DC_P_2  (VEX_LEN_DB_P_2 + 1)
1117 #define VEX_LEN_DD_P_2  (VEX_LEN_DC_P_2 + 1)
1118 #define VEX_LEN_DE_P_2  (VEX_LEN_DD_P_2 + 1)
1119 #define VEX_LEN_DF_P_2  (VEX_LEN_DE_P_2 + 1)
1120 #define VEX_LEN_E0_P_2  (VEX_LEN_DF_P_2 + 1)
1121 #define VEX_LEN_E1_P_2  (VEX_LEN_E0_P_2 + 1)
1122 #define VEX_LEN_E2_P_2  (VEX_LEN_E1_P_2 + 1)
1123 #define VEX_LEN_E3_P_2  (VEX_LEN_E2_P_2 + 1)
1124 #define VEX_LEN_E4_P_2  (VEX_LEN_E3_P_2 + 1)
1125 #define VEX_LEN_E5_P_2  (VEX_LEN_E4_P_2 + 1)
1126 #define VEX_LEN_E7_P_2_M_0      (VEX_LEN_E5_P_2 + 1)
1127 #define VEX_LEN_E8_P_2  (VEX_LEN_E7_P_2_M_0 + 1)
1128 #define VEX_LEN_E9_P_2  (VEX_LEN_E8_P_2 + 1)
1129 #define VEX_LEN_EA_P_2  (VEX_LEN_E9_P_2 + 1)
1130 #define VEX_LEN_EB_P_2  (VEX_LEN_EA_P_2 + 1)
1131 #define VEX_LEN_EC_P_2  (VEX_LEN_EB_P_2 + 1)
1132 #define VEX_LEN_ED_P_2  (VEX_LEN_EC_P_2 + 1)
1133 #define VEX_LEN_EE_P_2  (VEX_LEN_ED_P_2 + 1)
1134 #define VEX_LEN_EF_P_2  (VEX_LEN_EE_P_2 + 1)
1135 #define VEX_LEN_F1_P_2  (VEX_LEN_EF_P_2 + 1)
1136 #define VEX_LEN_F2_P_2  (VEX_LEN_F1_P_2 + 1)
1137 #define VEX_LEN_F3_P_2  (VEX_LEN_F2_P_2 + 1)
1138 #define VEX_LEN_F4_P_2  (VEX_LEN_F3_P_2 + 1)
1139 #define VEX_LEN_F5_P_2  (VEX_LEN_F4_P_2 + 1)
1140 #define VEX_LEN_F6_P_2  (VEX_LEN_F5_P_2 + 1)
1141 #define VEX_LEN_F7_P_2  (VEX_LEN_F6_P_2 + 1)
1142 #define VEX_LEN_F8_P_2  (VEX_LEN_F7_P_2 + 1)
1143 #define VEX_LEN_F9_P_2  (VEX_LEN_F8_P_2 + 1)
1144 #define VEX_LEN_FA_P_2  (VEX_LEN_F9_P_2 + 1)
1145 #define VEX_LEN_FB_P_2  (VEX_LEN_FA_P_2 + 1)
1146 #define VEX_LEN_FC_P_2  (VEX_LEN_FB_P_2 + 1)
1147 #define VEX_LEN_FD_P_2  (VEX_LEN_FC_P_2 + 1)
1148 #define VEX_LEN_FE_P_2  (VEX_LEN_FD_P_2 + 1)
1149 #define VEX_LEN_3800_P_2        (VEX_LEN_FE_P_2 + 1)
1150 #define VEX_LEN_3801_P_2        (VEX_LEN_3800_P_2 + 1)
1151 #define VEX_LEN_3802_P_2        (VEX_LEN_3801_P_2 + 1)
1152 #define VEX_LEN_3803_P_2        (VEX_LEN_3802_P_2 + 1)
1153 #define VEX_LEN_3804_P_2        (VEX_LEN_3803_P_2 + 1)
1154 #define VEX_LEN_3805_P_2        (VEX_LEN_3804_P_2 + 1)
1155 #define VEX_LEN_3806_P_2        (VEX_LEN_3805_P_2 + 1)
1156 #define VEX_LEN_3807_P_2        (VEX_LEN_3806_P_2 + 1)
1157 #define VEX_LEN_3808_P_2        (VEX_LEN_3807_P_2 + 1)
1158 #define VEX_LEN_3809_P_2        (VEX_LEN_3808_P_2 + 1)
1159 #define VEX_LEN_380A_P_2        (VEX_LEN_3809_P_2 + 1)
1160 #define VEX_LEN_380B_P_2        (VEX_LEN_380A_P_2 + 1)
1161 #define VEX_LEN_3819_P_2_M_0    (VEX_LEN_380B_P_2 + 1)
1162 #define VEX_LEN_381A_P_2_M_0    (VEX_LEN_3819_P_2_M_0 + 1)
1163 #define VEX_LEN_381C_P_2        (VEX_LEN_381A_P_2_M_0 + 1)
1164 #define VEX_LEN_381D_P_2        (VEX_LEN_381C_P_2 + 1)
1165 #define VEX_LEN_381E_P_2        (VEX_LEN_381D_P_2 + 1)
1166 #define VEX_LEN_3820_P_2        (VEX_LEN_381E_P_2 + 1)
1167 #define VEX_LEN_3821_P_2        (VEX_LEN_3820_P_2 + 1)
1168 #define VEX_LEN_3822_P_2        (VEX_LEN_3821_P_2 + 1)
1169 #define VEX_LEN_3823_P_2        (VEX_LEN_3822_P_2 + 1)
1170 #define VEX_LEN_3824_P_2        (VEX_LEN_3823_P_2 + 1)
1171 #define VEX_LEN_3825_P_2        (VEX_LEN_3824_P_2 + 1)
1172 #define VEX_LEN_3828_P_2        (VEX_LEN_3825_P_2 + 1)
1173 #define VEX_LEN_3829_P_2        (VEX_LEN_3828_P_2 + 1)
1174 #define VEX_LEN_382A_P_2_M_0    (VEX_LEN_3829_P_2 + 1)
1175 #define VEX_LEN_382B_P_2        (VEX_LEN_382A_P_2_M_0 + 1)
1176 #define VEX_LEN_3830_P_2        (VEX_LEN_382B_P_2 + 1)
1177 #define VEX_LEN_3831_P_2        (VEX_LEN_3830_P_2 + 1)
1178 #define VEX_LEN_3832_P_2        (VEX_LEN_3831_P_2 + 1)
1179 #define VEX_LEN_3833_P_2        (VEX_LEN_3832_P_2 + 1)
1180 #define VEX_LEN_3834_P_2        (VEX_LEN_3833_P_2 + 1)
1181 #define VEX_LEN_3835_P_2        (VEX_LEN_3834_P_2 + 1)
1182 #define VEX_LEN_3837_P_2        (VEX_LEN_3835_P_2 + 1)
1183 #define VEX_LEN_3838_P_2        (VEX_LEN_3837_P_2 + 1)
1184 #define VEX_LEN_3839_P_2        (VEX_LEN_3838_P_2 + 1)
1185 #define VEX_LEN_383A_P_2        (VEX_LEN_3839_P_2 + 1)
1186 #define VEX_LEN_383B_P_2        (VEX_LEN_383A_P_2 + 1)
1187 #define VEX_LEN_383C_P_2        (VEX_LEN_383B_P_2 + 1)
1188 #define VEX_LEN_383D_P_2        (VEX_LEN_383C_P_2 + 1)
1189 #define VEX_LEN_383E_P_2        (VEX_LEN_383D_P_2 + 1)
1190 #define VEX_LEN_383F_P_2        (VEX_LEN_383E_P_2 + 1)
1191 #define VEX_LEN_3840_P_2        (VEX_LEN_383F_P_2 + 1)
1192 #define VEX_LEN_3841_P_2        (VEX_LEN_3840_P_2 + 1)
1193 #define VEX_LEN_3A06_P_2        (VEX_LEN_3841_P_2 + 1)
1194 #define VEX_LEN_3A0A_P_2        (VEX_LEN_3A06_P_2 + 1)
1195 #define VEX_LEN_3A0B_P_2        (VEX_LEN_3A0A_P_2 + 1)
1196 #define VEX_LEN_3A0E_P_2        (VEX_LEN_3A0B_P_2 + 1)
1197 #define VEX_LEN_3A0F_P_2        (VEX_LEN_3A0E_P_2 + 1)
1198 #define VEX_LEN_3A14_P_2        (VEX_LEN_3A0F_P_2 + 1)
1199 #define VEX_LEN_3A15_P_2        (VEX_LEN_3A14_P_2 + 1)
1200 #define VEX_LEN_3A16_P_2        (VEX_LEN_3A15_P_2 + 1)
1201 #define VEX_LEN_3A17_P_2        (VEX_LEN_3A16_P_2 + 1)
1202 #define VEX_LEN_3A18_P_2        (VEX_LEN_3A17_P_2 + 1)
1203 #define VEX_LEN_3A19_P_2        (VEX_LEN_3A18_P_2 + 1)
1204 #define VEX_LEN_3A20_P_2        (VEX_LEN_3A19_P_2 + 1)
1205 #define VEX_LEN_3A21_P_2        (VEX_LEN_3A20_P_2 + 1)
1206 #define VEX_LEN_3A22_P_2        (VEX_LEN_3A21_P_2 + 1)
1207 #define VEX_LEN_3A41_P_2        (VEX_LEN_3A22_P_2 + 1)
1208 #define VEX_LEN_3A42_P_2        (VEX_LEN_3A41_P_2 + 1)
1209 #define VEX_LEN_3A4C_P_2        (VEX_LEN_3A42_P_2 + 1)
1210 #define VEX_LEN_3A60_P_2        (VEX_LEN_3A4C_P_2 + 1)
1211 #define VEX_LEN_3A61_P_2        (VEX_LEN_3A60_P_2 + 1)
1212 #define VEX_LEN_3A62_P_2        (VEX_LEN_3A61_P_2 + 1)
1213 #define VEX_LEN_3A63_P_2        (VEX_LEN_3A62_P_2 + 1)
1214 #define VEX_LEN_3A6A_P_2        (VEX_LEN_3A63_P_2 + 1)
1215 #define VEX_LEN_3A6B_P_2        (VEX_LEN_3A6A_P_2 + 1)
1216 #define VEX_LEN_3A6E_P_2        (VEX_LEN_3A6B_P_2 + 1)
1217 #define VEX_LEN_3A6F_P_2        (VEX_LEN_3A6E_P_2 + 1)
1218 #define VEX_LEN_3A7A_P_2        (VEX_LEN_3A6F_P_2 + 1)
1219 #define VEX_LEN_3A7B_P_2        (VEX_LEN_3A7A_P_2 + 1)
1220 #define VEX_LEN_3A7E_P_2        (VEX_LEN_3A7B_P_2 + 1)
1221 #define VEX_LEN_3A7F_P_2        (VEX_LEN_3A7E_P_2 + 1)
1222
1223 typedef void (*op_rtn) (int bytemode, int sizeflag);
1224
1225 struct dis386 {
1226   const char *name;
1227   struct
1228     {
1229       op_rtn rtn;
1230       int bytemode;
1231     } op[MAX_OPERANDS];
1232 };
1233
1234 /* Upper case letters in the instruction names here are macros.
1235    'A' => print 'b' if no register operands or suffix_always is true
1236    'B' => print 'b' if suffix_always is true
1237    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1238           size prefix
1239    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1240           suffix_always is true
1241    'E' => print 'e' if 32-bit form of jcxz
1242    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1243    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1244    'H' => print ",pt" or ",pn" branch hint
1245    'I' => honor following macro letter even in Intel mode (implemented only
1246           for some of the macro letters)
1247    'J' => print 'l'
1248    'K' => print 'd' or 'q' if rex prefix is present.
1249    'L' => print 'l' if suffix_always is true
1250    'M' => print 'r' if intel_mnemonic is false.
1251    'N' => print 'n' if instruction has no wait "prefix"
1252    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1253    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1254           or suffix_always is true.  print 'q' if rex prefix is present.
1255    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1256           is true
1257    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1258    'S' => print 'w', 'l' or 'q' if suffix_always is true
1259    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1260    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1261    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1262    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1263    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1264    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1265           suffix_always is true.
1266    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1267    '!' => change condition from true to false or from false to true.
1268    '%' => add 1 upper case letter to the macro.
1269
1270    2 upper case letter macros:
1271    "XY" => print 'x' or 'y' if no register operands or suffix_always
1272            is true.
1273    'LQ' => print 'l' ('d' in Intel mode) or 'q' for memory operand
1274            or suffix_always is true
1275
1276    Many of the above letters print nothing in Intel mode.  See "putop"
1277    for the details.
1278
1279    Braces '{' and '}', and vertical bars '|', indicate alternative
1280    mnemonic strings for AT&T and Intel.  */
1281
1282 static const struct dis386 dis386[] = {
1283   /* 00 */
1284   { "addB",             { Eb, Gb } },
1285   { "addS",             { Ev, Gv } },
1286   { "addB",             { Gb, Eb } },
1287   { "addS",             { Gv, Ev } },
1288   { "addB",             { AL, Ib } },
1289   { "addS",             { eAX, Iv } },
1290   { X86_64_TABLE (X86_64_06) },
1291   { X86_64_TABLE (X86_64_07) },
1292   /* 08 */
1293   { "orB",              { Eb, Gb } },
1294   { "orS",              { Ev, Gv } },
1295   { "orB",              { Gb, Eb } },
1296   { "orS",              { Gv, Ev } },
1297   { "orB",              { AL, Ib } },
1298   { "orS",              { eAX, Iv } },
1299   { X86_64_TABLE (X86_64_0D) },
1300   { "(bad)",            { XX } },       /* 0x0f extended opcode escape */
1301   /* 10 */
1302   { "adcB",             { Eb, Gb } },
1303   { "adcS",             { Ev, Gv } },
1304   { "adcB",             { Gb, Eb } },
1305   { "adcS",             { Gv, Ev } },
1306   { "adcB",             { AL, Ib } },
1307   { "adcS",             { eAX, Iv } },
1308   { X86_64_TABLE (X86_64_16) },
1309   { X86_64_TABLE (X86_64_17) },
1310   /* 18 */
1311   { "sbbB",             { Eb, Gb } },
1312   { "sbbS",             { Ev, Gv } },
1313   { "sbbB",             { Gb, Eb } },
1314   { "sbbS",             { Gv, Ev } },
1315   { "sbbB",             { AL, Ib } },
1316   { "sbbS",             { eAX, Iv } },
1317   { X86_64_TABLE (X86_64_1E) },
1318   { X86_64_TABLE (X86_64_1F) },
1319   /* 20 */
1320   { "andB",             { Eb, Gb } },
1321   { "andS",             { Ev, Gv } },
1322   { "andB",             { Gb, Eb } },
1323   { "andS",             { Gv, Ev } },
1324   { "andB",             { AL, Ib } },
1325   { "andS",             { eAX, Iv } },
1326   { "(bad)",            { XX } },       /* SEG ES prefix */
1327   { X86_64_TABLE (X86_64_27) },
1328   /* 28 */
1329   { "subB",             { Eb, Gb } },
1330   { "subS",             { Ev, Gv } },
1331   { "subB",             { Gb, Eb } },
1332   { "subS",             { Gv, Ev } },
1333   { "subB",             { AL, Ib } },
1334   { "subS",             { eAX, Iv } },
1335   { "(bad)",            { XX } },       /* SEG CS prefix */
1336   { X86_64_TABLE (X86_64_2F) },
1337   /* 30 */
1338   { "xorB",             { Eb, Gb } },
1339   { "xorS",             { Ev, Gv } },
1340   { "xorB",             { Gb, Eb } },
1341   { "xorS",             { Gv, Ev } },
1342   { "xorB",             { AL, Ib } },
1343   { "xorS",             { eAX, Iv } },
1344   { "(bad)",            { XX } },       /* SEG SS prefix */
1345   { X86_64_TABLE (X86_64_37) },
1346   /* 38 */
1347   { "cmpB",             { Eb, Gb } },
1348   { "cmpS",             { Ev, Gv } },
1349   { "cmpB",             { Gb, Eb } },
1350   { "cmpS",             { Gv, Ev } },
1351   { "cmpB",             { AL, Ib } },
1352   { "cmpS",             { eAX, Iv } },
1353   { "(bad)",            { XX } },       /* SEG DS prefix */
1354   { X86_64_TABLE (X86_64_3F) },
1355   /* 40 */
1356   { "inc{S|}",          { RMeAX } },
1357   { "inc{S|}",          { RMeCX } },
1358   { "inc{S|}",          { RMeDX } },
1359   { "inc{S|}",          { RMeBX } },
1360   { "inc{S|}",          { RMeSP } },
1361   { "inc{S|}",          { RMeBP } },
1362   { "inc{S|}",          { RMeSI } },
1363   { "inc{S|}",          { RMeDI } },
1364   /* 48 */
1365   { "dec{S|}",          { RMeAX } },
1366   { "dec{S|}",          { RMeCX } },
1367   { "dec{S|}",          { RMeDX } },
1368   { "dec{S|}",          { RMeBX } },
1369   { "dec{S|}",          { RMeSP } },
1370   { "dec{S|}",          { RMeBP } },
1371   { "dec{S|}",          { RMeSI } },
1372   { "dec{S|}",          { RMeDI } },
1373   /* 50 */
1374   { "pushV",            { RMrAX } },
1375   { "pushV",            { RMrCX } },
1376   { "pushV",            { RMrDX } },
1377   { "pushV",            { RMrBX } },
1378   { "pushV",            { RMrSP } },
1379   { "pushV",            { RMrBP } },
1380   { "pushV",            { RMrSI } },
1381   { "pushV",            { RMrDI } },
1382   /* 58 */
1383   { "popV",             { RMrAX } },
1384   { "popV",             { RMrCX } },
1385   { "popV",             { RMrDX } },
1386   { "popV",             { RMrBX } },
1387   { "popV",             { RMrSP } },
1388   { "popV",             { RMrBP } },
1389   { "popV",             { RMrSI } },
1390   { "popV",             { RMrDI } },
1391   /* 60 */
1392   { X86_64_TABLE (X86_64_60) },
1393   { X86_64_TABLE (X86_64_61) },
1394   { X86_64_TABLE (X86_64_62) },
1395   { X86_64_TABLE (X86_64_63) },
1396   { "(bad)",            { XX } },       /* seg fs */
1397   { "(bad)",            { XX } },       /* seg gs */
1398   { "(bad)",            { XX } },       /* op size prefix */
1399   { "(bad)",            { XX } },       /* adr size prefix */
1400   /* 68 */
1401   { "pushT",            { Iq } },
1402   { "imulS",            { Gv, Ev, Iv } },
1403   { "pushT",            { sIb } },
1404   { "imulS",            { Gv, Ev, sIb } },
1405   { "ins{b|}",          { Ybr, indirDX } },
1406   { X86_64_TABLE (X86_64_6D) },
1407   { "outs{b|}",         { indirDXr, Xb } },
1408   { X86_64_TABLE (X86_64_6F) },
1409   /* 70 */
1410   { "joH",              { Jb, XX, cond_jump_flag } },
1411   { "jnoH",             { Jb, XX, cond_jump_flag } },
1412   { "jbH",              { Jb, XX, cond_jump_flag } },
1413   { "jaeH",             { Jb, XX, cond_jump_flag } },
1414   { "jeH",              { Jb, XX, cond_jump_flag } },
1415   { "jneH",             { Jb, XX, cond_jump_flag } },
1416   { "jbeH",             { Jb, XX, cond_jump_flag } },
1417   { "jaH",              { Jb, XX, cond_jump_flag } },
1418   /* 78 */
1419   { "jsH",              { Jb, XX, cond_jump_flag } },
1420   { "jnsH",             { Jb, XX, cond_jump_flag } },
1421   { "jpH",              { Jb, XX, cond_jump_flag } },
1422   { "jnpH",             { Jb, XX, cond_jump_flag } },
1423   { "jlH",              { Jb, XX, cond_jump_flag } },
1424   { "jgeH",             { Jb, XX, cond_jump_flag } },
1425   { "jleH",             { Jb, XX, cond_jump_flag } },
1426   { "jgH",              { Jb, XX, cond_jump_flag } },
1427   /* 80 */
1428   { REG_TABLE (REG_80) },
1429   { REG_TABLE (REG_81) },
1430   { "(bad)",            { XX } },
1431   { REG_TABLE (REG_82) },
1432   { "testB",            { Eb, Gb } },
1433   { "testS",            { Ev, Gv } },
1434   { "xchgB",            { Eb, Gb } },
1435   { "xchgS",            { Ev, Gv } },
1436   /* 88 */
1437   { "movB",             { Eb, Gb } },
1438   { "movS",             { Ev, Gv } },
1439   { "movB",             { Gb, Eb } },
1440   { "movS",             { Gv, Ev } },
1441   { "movD",             { Sv, Sw } },
1442   { MOD_TABLE (MOD_8D) },
1443   { "movD",             { Sw, Sv } },
1444   { REG_TABLE (REG_8F) },
1445   /* 90 */
1446   { PREFIX_TABLE (PREFIX_90) },
1447   { "xchgS",            { RMeCX, eAX } },
1448   { "xchgS",            { RMeDX, eAX } },
1449   { "xchgS",            { RMeBX, eAX } },
1450   { "xchgS",            { RMeSP, eAX } },
1451   { "xchgS",            { RMeBP, eAX } },
1452   { "xchgS",            { RMeSI, eAX } },
1453   { "xchgS",            { RMeDI, eAX } },
1454   /* 98 */
1455   { "cW{t|}R",          { XX } },
1456   { "cR{t|}O",          { XX } },
1457   { X86_64_TABLE (X86_64_9A) },
1458   { "(bad)",            { XX } },       /* fwait */
1459   { "pushfT",           { XX } },
1460   { "popfT",            { XX } },
1461   { "sahf",             { XX } },
1462   { "lahf",             { XX } },
1463   /* a0 */
1464   { "movB",             { AL, Ob } },
1465   { "movS",             { eAX, Ov } },
1466   { "movB",             { Ob, AL } },
1467   { "movS",             { Ov, eAX } },
1468   { "movs{b|}",         { Ybr, Xb } },
1469   { "movs{R|}",         { Yvr, Xv } },
1470   { "cmps{b|}",         { Xb, Yb } },
1471   { "cmps{R|}",         { Xv, Yv } },
1472   /* a8 */
1473   { "testB",            { AL, Ib } },
1474   { "testS",            { eAX, Iv } },
1475   { "stosB",            { Ybr, AL } },
1476   { "stosS",            { Yvr, eAX } },
1477   { "lodsB",            { ALr, Xb } },
1478   { "lodsS",            { eAXr, Xv } },
1479   { "scasB",            { AL, Yb } },
1480   { "scasS",            { eAX, Yv } },
1481   /* b0 */
1482   { "movB",             { RMAL, Ib } },
1483   { "movB",             { RMCL, Ib } },
1484   { "movB",             { RMDL, Ib } },
1485   { "movB",             { RMBL, Ib } },
1486   { "movB",             { RMAH, Ib } },
1487   { "movB",             { RMCH, Ib } },
1488   { "movB",             { RMDH, Ib } },
1489   { "movB",             { RMBH, Ib } },
1490   /* b8 */
1491   { "movS",             { RMeAX, Iv64 } },
1492   { "movS",             { RMeCX, Iv64 } },
1493   { "movS",             { RMeDX, Iv64 } },
1494   { "movS",             { RMeBX, Iv64 } },
1495   { "movS",             { RMeSP, Iv64 } },
1496   { "movS",             { RMeBP, Iv64 } },
1497   { "movS",             { RMeSI, Iv64 } },
1498   { "movS",             { RMeDI, Iv64 } },
1499   /* c0 */
1500   { REG_TABLE (REG_C0) },
1501   { REG_TABLE (REG_C1) },
1502   { "retT",             { Iw } },
1503   { "retT",             { XX } },
1504   { X86_64_TABLE (X86_64_C4) },
1505   { X86_64_TABLE (X86_64_C5) },
1506   { REG_TABLE (REG_C6) },
1507   { REG_TABLE (REG_C7) },
1508   /* c8 */
1509   { "enterT",           { Iw, Ib } },
1510   { "leaveT",           { XX } },
1511   { "lretP",            { Iw } },
1512   { "lretP",            { XX } },
1513   { "int3",             { XX } },
1514   { "int",              { Ib } },
1515   { X86_64_TABLE (X86_64_CE) },
1516   { "iretP",            { XX } },
1517   /* d0 */
1518   { REG_TABLE (REG_D0) },
1519   { REG_TABLE (REG_D1) },
1520   { REG_TABLE (REG_D2) },
1521   { REG_TABLE (REG_D3) },
1522   { X86_64_TABLE (X86_64_D4) },
1523   { X86_64_TABLE (X86_64_D5) },
1524   { "(bad)",            { XX } },
1525   { "xlat",             { DSBX } },
1526   /* d8 */
1527   { FLOAT },
1528   { FLOAT },
1529   { FLOAT },
1530   { FLOAT },
1531   { FLOAT },
1532   { FLOAT },
1533   { FLOAT },
1534   { FLOAT },
1535   /* e0 */
1536   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1537   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1538   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1539   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1540   { "inB",              { AL, Ib } },
1541   { "inG",              { zAX, Ib } },
1542   { "outB",             { Ib, AL } },
1543   { "outG",             { Ib, zAX } },
1544   /* e8 */
1545   { "callT",            { Jv } },
1546   { "jmpT",             { Jv } },
1547   { X86_64_TABLE (X86_64_EA) },
1548   { "jmp",              { Jb } },
1549   { "inB",              { AL, indirDX } },
1550   { "inG",              { zAX, indirDX } },
1551   { "outB",             { indirDX, AL } },
1552   { "outG",             { indirDX, zAX } },
1553   /* f0 */
1554   { "(bad)",            { XX } },       /* lock prefix */
1555   { "icebp",            { XX } },
1556   { "(bad)",            { XX } },       /* repne */
1557   { "(bad)",            { XX } },       /* repz */
1558   { "hlt",              { XX } },
1559   { "cmc",              { XX } },
1560   { REG_TABLE (REG_F6) },
1561   { REG_TABLE (REG_F7) },
1562   /* f8 */
1563   { "clc",              { XX } },
1564   { "stc",              { XX } },
1565   { "cli",              { XX } },
1566   { "sti",              { XX } },
1567   { "cld",              { XX } },
1568   { "std",              { XX } },
1569   { REG_TABLE (REG_FE) },
1570   { REG_TABLE (REG_FF) },
1571 };
1572
1573 static const struct dis386 dis386_twobyte[] = {
1574   /* 00 */
1575   { REG_TABLE (REG_0F00 ) },
1576   { REG_TABLE (REG_0F01 ) },
1577   { "larS",             { Gv, Ew } },
1578   { "lslS",             { Gv, Ew } },
1579   { "(bad)",            { XX } },
1580   { "syscall",          { XX } },
1581   { "clts",             { XX } },
1582   { "sysretP",          { XX } },
1583   /* 08 */
1584   { "invd",             { XX } },
1585   { "wbinvd",           { XX } },
1586   { "(bad)",            { XX } },
1587   { "ud2a",             { XX } },
1588   { "(bad)",            { XX } },
1589   { REG_TABLE (REG_0F0D) },
1590   { "femms",            { XX } },
1591   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1592   /* 10 */
1593   { PREFIX_TABLE (PREFIX_0F10) },
1594   { PREFIX_TABLE (PREFIX_0F11) },
1595   { PREFIX_TABLE (PREFIX_0F12) },
1596   { MOD_TABLE (MOD_0F13) },
1597   { "unpcklpX",         { XM, EXx } },
1598   { "unpckhpX",         { XM, EXx } },
1599   { PREFIX_TABLE (PREFIX_0F16) },
1600   { MOD_TABLE (MOD_0F17) },
1601   /* 18 */
1602   { REG_TABLE (REG_0F18) },
1603   { "nopQ",             { Ev } },
1604   { "nopQ",             { Ev } },
1605   { "nopQ",             { Ev } },
1606   { "nopQ",             { Ev } },
1607   { "nopQ",             { Ev } },
1608   { "nopQ",             { Ev } },
1609   { "nopQ",             { Ev } },
1610   /* 20 */
1611   { MOD_TABLE (MOD_0F20) },
1612   { MOD_TABLE (MOD_0F21) },
1613   { MOD_TABLE (MOD_0F22) },
1614   { MOD_TABLE (MOD_0F23) },
1615   { MOD_TABLE (MOD_0F24) },
1616   { THREE_BYTE_TABLE (THREE_BYTE_0F25) },
1617   { MOD_TABLE (MOD_0F26) },
1618   { "(bad)",            { XX } },
1619   /* 28 */
1620   { "movapX",           { XM, EXx } },
1621   { "movapX",           { EXx, XM } },
1622   { PREFIX_TABLE (PREFIX_0F2A) },
1623   { PREFIX_TABLE (PREFIX_0F2B) },
1624   { PREFIX_TABLE (PREFIX_0F2C) },
1625   { PREFIX_TABLE (PREFIX_0F2D) },
1626   { PREFIX_TABLE (PREFIX_0F2E) },
1627   { PREFIX_TABLE (PREFIX_0F2F) },
1628   /* 30 */
1629   { "wrmsr",            { XX } },
1630   { "rdtsc",            { XX } },
1631   { "rdmsr",            { XX } },
1632   { "rdpmc",            { XX } },
1633   { "sysenter",         { XX } },
1634   { "sysexit",          { XX } },
1635   { "(bad)",            { XX } },
1636   { "getsec",           { XX } },
1637   /* 38 */
1638   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
1639   { "(bad)",            { XX } },
1640   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
1641   { "(bad)",            { XX } },
1642   { "(bad)",            { XX } },
1643   { "(bad)",            { XX } },
1644   { "(bad)",            { XX } },
1645   { "(bad)",            { XX } },
1646   /* 40 */
1647   { "cmovo",            { Gv, Ev } },
1648   { "cmovno",           { Gv, Ev } },
1649   { "cmovb",            { Gv, Ev } },
1650   { "cmovae",           { Gv, Ev } },
1651   { "cmove",            { Gv, Ev } },
1652   { "cmovne",           { Gv, Ev } },
1653   { "cmovbe",           { Gv, Ev } },
1654   { "cmova",            { Gv, Ev } },
1655   /* 48 */
1656   { "cmovs",            { Gv, Ev } },
1657   { "cmovns",           { Gv, Ev } },
1658   { "cmovp",            { Gv, Ev } },
1659   { "cmovnp",           { Gv, Ev } },
1660   { "cmovl",            { Gv, Ev } },
1661   { "cmovge",           { Gv, Ev } },
1662   { "cmovle",           { Gv, Ev } },
1663   { "cmovg",            { Gv, Ev } },
1664   /* 50 */
1665   { MOD_TABLE (MOD_0F51) },
1666   { PREFIX_TABLE (PREFIX_0F51) },
1667   { PREFIX_TABLE (PREFIX_0F52) },
1668   { PREFIX_TABLE (PREFIX_0F53) },
1669   { "andpX",            { XM, EXx } },
1670   { "andnpX",           { XM, EXx } },
1671   { "orpX",             { XM, EXx } },
1672   { "xorpX",            { XM, EXx } },
1673   /* 58 */
1674   { PREFIX_TABLE (PREFIX_0F58) },
1675   { PREFIX_TABLE (PREFIX_0F59) },
1676   { PREFIX_TABLE (PREFIX_0F5A) },
1677   { PREFIX_TABLE (PREFIX_0F5B) },
1678   { PREFIX_TABLE (PREFIX_0F5C) },
1679   { PREFIX_TABLE (PREFIX_0F5D) },
1680   { PREFIX_TABLE (PREFIX_0F5E) },
1681   { PREFIX_TABLE (PREFIX_0F5F) },
1682   /* 60 */
1683   { PREFIX_TABLE (PREFIX_0F60) },
1684   { PREFIX_TABLE (PREFIX_0F61) },
1685   { PREFIX_TABLE (PREFIX_0F62) },
1686   { "packsswb",         { MX, EM } },
1687   { "pcmpgtb",          { MX, EM } },
1688   { "pcmpgtw",          { MX, EM } },
1689   { "pcmpgtd",          { MX, EM } },
1690   { "packuswb",         { MX, EM } },
1691   /* 68 */
1692   { "punpckhbw",        { MX, EM } },
1693   { "punpckhwd",        { MX, EM } },
1694   { "punpckhdq",        { MX, EM } },
1695   { "packssdw",         { MX, EM } },
1696   { PREFIX_TABLE (PREFIX_0F6C) },
1697   { PREFIX_TABLE (PREFIX_0F6D) },
1698   { "movK",             { MX, Edq } },
1699   { PREFIX_TABLE (PREFIX_0F6F) },
1700   /* 70 */
1701   { PREFIX_TABLE (PREFIX_0F70) },
1702   { REG_TABLE (REG_0F71) },
1703   { REG_TABLE (REG_0F72) },
1704   { REG_TABLE (REG_0F73) },
1705   { "pcmpeqb",          { MX, EM } },
1706   { "pcmpeqw",          { MX, EM } },
1707   { "pcmpeqd",          { MX, EM } },
1708   { "emms",             { XX } },
1709   /* 78 */
1710   { PREFIX_TABLE (PREFIX_0F78) },
1711   { PREFIX_TABLE (PREFIX_0F79) },
1712   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
1713   { THREE_BYTE_TABLE (THREE_BYTE_0F7B) },
1714   { PREFIX_TABLE (PREFIX_0F7C) },
1715   { PREFIX_TABLE (PREFIX_0F7D) },
1716   { PREFIX_TABLE (PREFIX_0F7E) },
1717   { PREFIX_TABLE (PREFIX_0F7F) },
1718   /* 80 */
1719   { "joH",              { Jv, XX, cond_jump_flag } },
1720   { "jnoH",             { Jv, XX, cond_jump_flag } },
1721   { "jbH",              { Jv, XX, cond_jump_flag } },
1722   { "jaeH",             { Jv, XX, cond_jump_flag } },
1723   { "jeH",              { Jv, XX, cond_jump_flag } },
1724   { "jneH",             { Jv, XX, cond_jump_flag } },
1725   { "jbeH",             { Jv, XX, cond_jump_flag } },
1726   { "jaH",              { Jv, XX, cond_jump_flag } },
1727   /* 88 */
1728   { "jsH",              { Jv, XX, cond_jump_flag } },
1729   { "jnsH",             { Jv, XX, cond_jump_flag } },
1730   { "jpH",              { Jv, XX, cond_jump_flag } },
1731   { "jnpH",             { Jv, XX, cond_jump_flag } },
1732   { "jlH",              { Jv, XX, cond_jump_flag } },
1733   { "jgeH",             { Jv, XX, cond_jump_flag } },
1734   { "jleH",             { Jv, XX, cond_jump_flag } },
1735   { "jgH",              { Jv, XX, cond_jump_flag } },
1736   /* 90 */
1737   { "seto",             { Eb } },
1738   { "setno",            { Eb } },
1739   { "setb",             { Eb } },
1740   { "setae",            { Eb } },
1741   { "sete",             { Eb } },
1742   { "setne",            { Eb } },
1743   { "setbe",            { Eb } },
1744   { "seta",             { Eb } },
1745   /* 98 */
1746   { "sets",             { Eb } },
1747   { "setns",            { Eb } },
1748   { "setp",             { Eb } },
1749   { "setnp",            { Eb } },
1750   { "setl",             { Eb } },
1751   { "setge",            { Eb } },
1752   { "setle",            { Eb } },
1753   { "setg",             { Eb } },
1754   /* a0 */
1755   { "pushT",            { fs } },
1756   { "popT",             { fs } },
1757   { "cpuid",            { XX } },
1758   { "btS",              { Ev, Gv } },
1759   { "shldS",            { Ev, Gv, Ib } },
1760   { "shldS",            { Ev, Gv, CL } },
1761   { REG_TABLE (REG_0FA6) },
1762   { REG_TABLE (REG_0FA7) },
1763   /* a8 */
1764   { "pushT",            { gs } },
1765   { "popT",             { gs } },
1766   { "rsm",              { XX } },
1767   { "btsS",             { Ev, Gv } },
1768   { "shrdS",            { Ev, Gv, Ib } },
1769   { "shrdS",            { Ev, Gv, CL } },
1770   { REG_TABLE (REG_0FAE) },
1771   { "imulS",            { Gv, Ev } },
1772   /* b0 */
1773   { "cmpxchgB",         { Eb, Gb } },
1774   { "cmpxchgS",         { Ev, Gv } },
1775   { MOD_TABLE (MOD_0FB2) },
1776   { "btrS",             { Ev, Gv } },
1777   { MOD_TABLE (MOD_0FB4) },
1778   { MOD_TABLE (MOD_0FB5) },
1779   { "movz{bR|x}",       { Gv, Eb } },
1780   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
1781   /* b8 */
1782   { PREFIX_TABLE (PREFIX_0FB8) },
1783   { "ud2b",             { XX } },
1784   { REG_TABLE (REG_0FBA) },
1785   { "btcS",             { Ev, Gv } },
1786   { "bsfS",             { Gv, Ev } },
1787   { PREFIX_TABLE (PREFIX_0FBD) },
1788   { "movs{bR|x}",       { Gv, Eb } },
1789   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
1790   /* c0 */
1791   { "xaddB",            { Eb, Gb } },
1792   { "xaddS",            { Ev, Gv } },
1793   { PREFIX_TABLE (PREFIX_0FC2) },
1794   { PREFIX_TABLE (PREFIX_0FC3) },
1795   { "pinsrw",           { MX, Edqw, Ib } },
1796   { "pextrw",           { Gdq, MS, Ib } },
1797   { "shufpX",           { XM, EXx, Ib } },
1798   { REG_TABLE (REG_0FC7) },
1799   /* c8 */
1800   { "bswap",            { RMeAX } },
1801   { "bswap",            { RMeCX } },
1802   { "bswap",            { RMeDX } },
1803   { "bswap",            { RMeBX } },
1804   { "bswap",            { RMeSP } },
1805   { "bswap",            { RMeBP } },
1806   { "bswap",            { RMeSI } },
1807   { "bswap",            { RMeDI } },
1808   /* d0 */
1809   { PREFIX_TABLE (PREFIX_0FD0) },
1810   { "psrlw",            { MX, EM } },
1811   { "psrld",            { MX, EM } },
1812   { "psrlq",            { MX, EM } },
1813   { "paddq",            { MX, EM } },
1814   { "pmullw",           { MX, EM } },
1815   { PREFIX_TABLE (PREFIX_0FD6) },
1816   { MOD_TABLE (MOD_0FD7) },
1817   /* d8 */
1818   { "psubusb",          { MX, EM } },
1819   { "psubusw",          { MX, EM } },
1820   { "pminub",           { MX, EM } },
1821   { "pand",             { MX, EM } },
1822   { "paddusb",          { MX, EM } },
1823   { "paddusw",          { MX, EM } },
1824   { "pmaxub",           { MX, EM } },
1825   { "pandn",            { MX, EM } },
1826   /* e0 */
1827   { "pavgb",            { MX, EM } },
1828   { "psraw",            { MX, EM } },
1829   { "psrad",            { MX, EM } },
1830   { "pavgw",            { MX, EM } },
1831   { "pmulhuw",          { MX, EM } },
1832   { "pmulhw",           { MX, EM } },
1833   { PREFIX_TABLE (PREFIX_0FE6) },
1834   { PREFIX_TABLE (PREFIX_0FE7) },
1835   /* e8 */
1836   { "psubsb",           { MX, EM } },
1837   { "psubsw",           { MX, EM } },
1838   { "pminsw",           { MX, EM } },
1839   { "por",              { MX, EM } },
1840   { "paddsb",           { MX, EM } },
1841   { "paddsw",           { MX, EM } },
1842   { "pmaxsw",           { MX, EM } },
1843   { "pxor",             { MX, EM } },
1844   /* f0 */
1845   { PREFIX_TABLE (PREFIX_0FF0) },
1846   { "psllw",            { MX, EM } },
1847   { "pslld",            { MX, EM } },
1848   { "psllq",            { MX, EM } },
1849   { "pmuludq",          { MX, EM } },
1850   { "pmaddwd",          { MX, EM } },
1851   { "psadbw",           { MX, EM } },
1852   { PREFIX_TABLE (PREFIX_0FF7) },
1853   /* f8 */
1854   { "psubb",            { MX, EM } },
1855   { "psubw",            { MX, EM } },
1856   { "psubd",            { MX, EM } },
1857   { "psubq",            { MX, EM } },
1858   { "paddb",            { MX, EM } },
1859   { "paddw",            { MX, EM } },
1860   { "paddd",            { MX, EM } },
1861   { "(bad)",            { XX } },
1862 };
1863
1864 static const unsigned char onebyte_has_modrm[256] = {
1865   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1866   /*       -------------------------------        */
1867   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1868   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1869   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1870   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1871   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1872   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1873   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1874   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1875   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1876   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1877   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1878   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1879   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1880   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1881   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1882   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
1883   /*       -------------------------------        */
1884   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1885 };
1886
1887 static const unsigned char twobyte_has_modrm[256] = {
1888   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1889   /*       -------------------------------        */
1890   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1891   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1892   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1893   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1894   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1895   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1896   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1897   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1898   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1899   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1900   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1901   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1902   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1903   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1904   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1905   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
1906   /*       -------------------------------        */
1907   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1908 };
1909
1910 static char obuf[100];
1911 static char *obufp;
1912 static char scratchbuf[100];
1913 static unsigned char *start_codep;
1914 static unsigned char *insn_codep;
1915 static unsigned char *codep;
1916 static const char *lock_prefix;
1917 static const char *data_prefix;
1918 static const char *addr_prefix;
1919 static const char *repz_prefix;
1920 static const char *repnz_prefix;
1921 static disassemble_info *the_info;
1922 static struct
1923   {
1924     int mod;
1925     int reg;
1926     int rm;
1927   }
1928 modrm;
1929 static unsigned char need_modrm;
1930 static struct
1931   {
1932     int register_specifier;
1933     int length;
1934     int prefix;
1935     int w;
1936   }
1937 vex;
1938 static unsigned char need_vex;
1939 static unsigned char need_vex_reg;
1940 static unsigned char vex_i4_done;
1941
1942 /* If we are accessing mod/rm/reg without need_modrm set, then the
1943    values are stale.  Hitting this abort likely indicates that you
1944    need to update onebyte_has_modrm or twobyte_has_modrm.  */
1945 #define MODRM_CHECK  if (!need_modrm) abort ()
1946
1947 static const char **names64;
1948 static const char **names32;
1949 static const char **names16;
1950 static const char **names8;
1951 static const char **names8rex;
1952 static const char **names_seg;
1953 static const char *index64;
1954 static const char *index32;
1955 static const char **index16;
1956
1957 static const char *intel_names64[] = {
1958   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
1959   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
1960 };
1961 static const char *intel_names32[] = {
1962   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
1963   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
1964 };
1965 static const char *intel_names16[] = {
1966   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
1967   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
1968 };
1969 static const char *intel_names8[] = {
1970   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
1971 };
1972 static const char *intel_names8rex[] = {
1973   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
1974   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
1975 };
1976 static const char *intel_names_seg[] = {
1977   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
1978 };
1979 static const char *intel_index64 = "riz";
1980 static const char *intel_index32 = "eiz";
1981 static const char *intel_index16[] = {
1982   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
1983 };
1984
1985 static const char *att_names64[] = {
1986   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
1987   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
1988 };
1989 static const char *att_names32[] = {
1990   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
1991   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
1992 };
1993 static const char *att_names16[] = {
1994   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
1995   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
1996 };
1997 static const char *att_names8[] = {
1998   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
1999 };
2000 static const char *att_names8rex[] = {
2001   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2002   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2003 };
2004 static const char *att_names_seg[] = {
2005   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2006 };
2007 static const char *att_index64 = "%riz";
2008 static const char *att_index32 = "%eiz";
2009 static const char *att_index16[] = {
2010   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2011 };
2012
2013 static const struct dis386 reg_table[][8] = {
2014   /* REG_80 */
2015   {
2016     { "addA",   { Eb, Ib } },
2017     { "orA",    { Eb, Ib } },
2018     { "adcA",   { Eb, Ib } },
2019     { "sbbA",   { Eb, Ib } },
2020     { "andA",   { Eb, Ib } },
2021     { "subA",   { Eb, Ib } },
2022     { "xorA",   { Eb, Ib } },
2023     { "cmpA",   { Eb, Ib } },
2024   },
2025   /* REG_81 */
2026   {
2027     { "addQ",   { Ev, Iv } },
2028     { "orQ",    { Ev, Iv } },
2029     { "adcQ",   { Ev, Iv } },
2030     { "sbbQ",   { Ev, Iv } },
2031     { "andQ",   { Ev, Iv } },
2032     { "subQ",   { Ev, Iv } },
2033     { "xorQ",   { Ev, Iv } },
2034     { "cmpQ",   { Ev, Iv } },
2035   },
2036   /* REG_82 */
2037   {
2038     { "addQ",   { Ev, sIb } },
2039     { "orQ",    { Ev, sIb } },
2040     { "adcQ",   { Ev, sIb } },
2041     { "sbbQ",   { Ev, sIb } },
2042     { "andQ",   { Ev, sIb } },
2043     { "subQ",   { Ev, sIb } },
2044     { "xorQ",   { Ev, sIb } },
2045     { "cmpQ",   { Ev, sIb } },
2046   },
2047   /* REG_8F */
2048   {
2049     { "popU",   { stackEv } },
2050     { "(bad)",  { XX } },
2051     { "(bad)",  { XX } },
2052     { "(bad)",  { XX } },
2053     { "(bad)",  { XX } },
2054     { "(bad)",  { XX } },
2055     { "(bad)",  { XX } },
2056     { "(bad)",  { XX } },
2057   },
2058   /* REG_C0 */
2059   {
2060     { "rolA",   { Eb, Ib } },
2061     { "rorA",   { Eb, Ib } },
2062     { "rclA",   { Eb, Ib } },
2063     { "rcrA",   { Eb, Ib } },
2064     { "shlA",   { Eb, Ib } },
2065     { "shrA",   { Eb, Ib } },
2066     { "(bad)",  { XX } },
2067     { "sarA",   { Eb, Ib } },
2068   },
2069   /* REG_C1 */
2070   {
2071     { "rolQ",   { Ev, Ib } },
2072     { "rorQ",   { Ev, Ib } },
2073     { "rclQ",   { Ev, Ib } },
2074     { "rcrQ",   { Ev, Ib } },
2075     { "shlQ",   { Ev, Ib } },
2076     { "shrQ",   { Ev, Ib } },
2077     { "(bad)",  { XX } },
2078     { "sarQ",   { Ev, Ib } },
2079   },
2080   /* REG_C6 */
2081   {
2082     { "movA",   { Eb, Ib } },
2083     { "(bad)",  { XX } },
2084     { "(bad)",  { XX } },
2085     { "(bad)",  { XX } },
2086     { "(bad)",  { XX } },
2087     { "(bad)",  { XX } },
2088     { "(bad)",  { XX } },
2089     { "(bad)",  { XX } },
2090   },
2091   /* REG_C7 */
2092   {
2093     { "movQ",   { Ev, Iv } },
2094     { "(bad)",  { XX } },
2095     { "(bad)",  { XX } },
2096     { "(bad)",  { XX } },
2097     { "(bad)",  { XX } },
2098     { "(bad)",  { XX } },
2099     { "(bad)",  { XX } },
2100     { "(bad)",  { XX } },
2101   },
2102   /* REG_D0 */
2103   {
2104     { "rolA",   { Eb, I1 } },
2105     { "rorA",   { Eb, I1 } },
2106     { "rclA",   { Eb, I1 } },
2107     { "rcrA",   { Eb, I1 } },
2108     { "shlA",   { Eb, I1 } },
2109     { "shrA",   { Eb, I1 } },
2110     { "(bad)",  { XX } },
2111     { "sarA",   { Eb, I1 } },
2112   },
2113   /* REG_D1 */
2114   {
2115     { "rolQ",   { Ev, I1 } },
2116     { "rorQ",   { Ev, I1 } },
2117     { "rclQ",   { Ev, I1 } },
2118     { "rcrQ",   { Ev, I1 } },
2119     { "shlQ",   { Ev, I1 } },
2120     { "shrQ",   { Ev, I1 } },
2121     { "(bad)",  { XX } },
2122     { "sarQ",   { Ev, I1 } },
2123   },
2124   /* REG_D2 */
2125   {
2126     { "rolA",   { Eb, CL } },
2127     { "rorA",   { Eb, CL } },
2128     { "rclA",   { Eb, CL } },
2129     { "rcrA",   { Eb, CL } },
2130     { "shlA",   { Eb, CL } },
2131     { "shrA",   { Eb, CL } },
2132     { "(bad)",  { XX } },
2133     { "sarA",   { Eb, CL } },
2134   },
2135   /* REG_D3 */
2136   {
2137     { "rolQ",   { Ev, CL } },
2138     { "rorQ",   { Ev, CL } },
2139     { "rclQ",   { Ev, CL } },
2140     { "rcrQ",   { Ev, CL } },
2141     { "shlQ",   { Ev, CL } },
2142     { "shrQ",   { Ev, CL } },
2143     { "(bad)",  { XX } },
2144     { "sarQ",   { Ev, CL } },
2145   },
2146   /* REG_F6 */
2147   {
2148     { "testA",  { Eb, Ib } },
2149     { "(bad)",  { XX } },
2150     { "notA",   { Eb } },
2151     { "negA",   { Eb } },
2152     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2153     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2154     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2155     { "idivA",  { Eb } },       /* and idiv for consistency.               */
2156   },
2157   /* REG_F7 */
2158   {
2159     { "testQ",  { Ev, Iv } },
2160     { "(bad)",  { XX } },
2161     { "notQ",   { Ev } },
2162     { "negQ",   { Ev } },
2163     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2164     { "imulQ",  { Ev } },
2165     { "divQ",   { Ev } },
2166     { "idivQ",  { Ev } },
2167   },
2168   /* REG_FE */
2169   {
2170     { "incA",   { Eb } },
2171     { "decA",   { Eb } },
2172     { "(bad)",  { XX } },
2173     { "(bad)",  { XX } },
2174     { "(bad)",  { XX } },
2175     { "(bad)",  { XX } },
2176     { "(bad)",  { XX } },
2177     { "(bad)",  { XX } },
2178   },
2179   /* REG_FF */
2180   {
2181     { "incQ",   { Ev } },
2182     { "decQ",   { Ev } },
2183     { "callT",  { indirEv } },
2184     { "JcallT", { indirEp } },
2185     { "jmpT",   { indirEv } },
2186     { "JjmpT",  { indirEp } },
2187     { "pushU",  { stackEv } },
2188     { "(bad)",  { XX } },
2189   },
2190   /* REG_0F00 */
2191   {
2192     { "sldtD",  { Sv } },
2193     { "strD",   { Sv } },
2194     { "lldt",   { Ew } },
2195     { "ltr",    { Ew } },
2196     { "verr",   { Ew } },
2197     { "verw",   { Ew } },
2198     { "(bad)",  { XX } },
2199     { "(bad)",  { XX } },
2200   },
2201   /* REG_0F01 */
2202   {
2203     { MOD_TABLE (MOD_0F01_REG_0) },
2204     { MOD_TABLE (MOD_0F01_REG_1) },
2205     { MOD_TABLE (MOD_0F01_REG_2) },
2206     { MOD_TABLE (MOD_0F01_REG_3) },
2207     { "smswD",  { Sv } },
2208     { "(bad)",  { XX } },
2209     { "lmsw",   { Ew } },
2210     { MOD_TABLE (MOD_0F01_REG_7) },
2211   },
2212   /* REG_0F0D */
2213   {
2214     { "prefetch",       { Eb } },
2215     { "prefetchw",      { Eb } },
2216     { "(bad)",          { XX } },
2217     { "(bad)",          { XX } },
2218     { "(bad)",          { XX } },
2219     { "(bad)",          { XX } },
2220     { "(bad)",          { XX } },
2221     { "(bad)",          { XX } },
2222   },
2223   /* REG_0F18 */
2224   {
2225     { MOD_TABLE (MOD_0F18_REG_0) },
2226     { MOD_TABLE (MOD_0F18_REG_1) },
2227     { MOD_TABLE (MOD_0F18_REG_2) },
2228     { MOD_TABLE (MOD_0F18_REG_3) },
2229     { "(bad)",  { XX } },
2230     { "(bad)",  { XX } },
2231     { "(bad)",  { XX } },
2232     { "(bad)",  { XX } },
2233   },
2234   /* REG_0F71 */
2235   {
2236     { "(bad)",  { XX } },
2237     { "(bad)",  { XX } },
2238     { MOD_TABLE (MOD_0F71_REG_2) },
2239     { "(bad)",  { XX } },
2240     { MOD_TABLE (MOD_0F71_REG_4) },
2241     { "(bad)",  { XX } },
2242     { MOD_TABLE (MOD_0F71_REG_6) },
2243     { "(bad)",  { XX } },
2244   },
2245   /* REG_0F72 */
2246   {
2247     { "(bad)",  { XX } },
2248     { "(bad)",  { XX } },
2249     { MOD_TABLE (MOD_0F72_REG_2) },
2250     { "(bad)",  { XX } },
2251     { MOD_TABLE (MOD_0F72_REG_4) },
2252     { "(bad)",  { XX } },
2253     { MOD_TABLE (MOD_0F72_REG_6) },
2254     { "(bad)",  { XX } },
2255   },
2256   /* REG_0F73 */
2257   {
2258     { "(bad)",  { XX } },
2259     { "(bad)",  { XX } },
2260     { MOD_TABLE (MOD_0F73_REG_2) },
2261     { MOD_TABLE (MOD_0F73_REG_3) },
2262     { "(bad)",  { XX } },
2263     { "(bad)",  { XX } },
2264     { MOD_TABLE (MOD_0F73_REG_6) },
2265     { MOD_TABLE (MOD_0F73_REG_7) },
2266   },
2267   /* REG_0FA6 */
2268   {
2269     { "montmul",        { { OP_0f07, 0 } } },
2270     { "xsha1",          { { OP_0f07, 0 } } },
2271     { "xsha256",        { { OP_0f07, 0 } } },
2272     { "(bad)",          { { OP_0f07, 0 } } },
2273     { "(bad)",          { { OP_0f07, 0 } } },
2274     { "(bad)",          { { OP_0f07, 0 } } },
2275     { "(bad)",          { { OP_0f07, 0 } } },
2276     { "(bad)",          { { OP_0f07, 0 } } },
2277   },
2278   /* REG_0FA7 */
2279   {
2280     { "xstore-rng",     { { OP_0f07, 0 } } },
2281     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2282     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2283     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2284     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2285     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2286     { "(bad)",          { { OP_0f07, 0 } } },
2287     { "(bad)",          { { OP_0f07, 0 } } },
2288   },
2289   /* REG_0FAE */
2290   {
2291     { MOD_TABLE (MOD_0FAE_REG_0) },
2292     { MOD_TABLE (MOD_0FAE_REG_1) },
2293     { MOD_TABLE (MOD_0FAE_REG_2) },
2294     { MOD_TABLE (MOD_0FAE_REG_3) },
2295     { MOD_TABLE (MOD_0FAE_REG_4) },
2296     { MOD_TABLE (MOD_0FAE_REG_5) },
2297     { MOD_TABLE (MOD_0FAE_REG_6) },
2298     { MOD_TABLE (MOD_0FAE_REG_7) },
2299   },
2300   /* REG_0FBA */
2301   {
2302     { "(bad)",  { XX } },
2303     { "(bad)",  { XX } },
2304     { "(bad)",  { XX } },
2305     { "(bad)",  { XX } },
2306     { "btQ",    { Ev, Ib } },
2307     { "btsQ",   { Ev, Ib } },
2308     { "btrQ",   { Ev, Ib } },
2309     { "btcQ",   { Ev, Ib } },
2310   },
2311   /* REG_0FC7 */
2312   {
2313     { "(bad)",  { XX } },
2314     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2315     { "(bad)",  { XX } },
2316     { "(bad)",  { XX } },
2317     { "(bad)",  { XX } },
2318     { "(bad)",  { XX } },
2319     { MOD_TABLE (MOD_0FC7_REG_6) },
2320     { MOD_TABLE (MOD_0FC7_REG_7) },
2321   },
2322   /* REG_VEX_71 */
2323   {
2324     { "(bad)",  { XX } },
2325     { "(bad)",  { XX } },
2326     { MOD_TABLE (MOD_VEX_71_REG_2) },
2327     { "(bad)",  { XX } },
2328     { MOD_TABLE (MOD_VEX_71_REG_4) },
2329     { "(bad)",  { XX } },
2330     { MOD_TABLE (MOD_VEX_71_REG_6) },
2331     { "(bad)",  { XX } },
2332   },
2333   /* REG_VEX_72 */
2334   {
2335     { "(bad)",  { XX } },
2336     { "(bad)",  { XX } },
2337     { MOD_TABLE (MOD_VEX_72_REG_2) },
2338     { "(bad)",  { XX } },
2339     { MOD_TABLE (MOD_VEX_72_REG_4) },
2340     { "(bad)",  { XX } },
2341     { MOD_TABLE (MOD_VEX_72_REG_6) },
2342     { "(bad)",  { XX } },
2343   },
2344   /* REG_VEX_73 */
2345   {
2346     { "(bad)",  { XX } },
2347     { "(bad)",  { XX } },
2348     { MOD_TABLE (MOD_VEX_73_REG_2) },
2349     { MOD_TABLE (MOD_VEX_73_REG_3) },
2350     { "(bad)",  { XX } },
2351     { "(bad)",  { XX } },
2352     { MOD_TABLE (MOD_VEX_73_REG_6) },
2353     { MOD_TABLE (MOD_VEX_73_REG_7) },
2354   },
2355   /* REG_VEX_AE */
2356   {
2357     { "(bad)",  { XX } },
2358     { "(bad)",  { XX } },
2359     { MOD_TABLE (MOD_VEX_AE_REG_2) },
2360     { MOD_TABLE (MOD_VEX_AE_REG_3) },
2361     { "(bad)",  { XX } },
2362     { "(bad)",  { XX } },
2363     { "(bad)",  { XX } },
2364     { "(bad)",  { XX } },
2365   },
2366 };
2367
2368 static const struct dis386 prefix_table[][4] = {
2369   /* PREFIX_90 */
2370   {
2371     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2372     { "pause", { XX } },
2373     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2374     { "(bad)", { XX } },
2375   },
2376
2377   /* PREFIX_0F10 */
2378   {
2379     { "movups", { XM, EXx } },
2380     { "movss",  { XM, EXd } },
2381     { "movupd", { XM, EXx } },
2382     { "movsd",  { XM, EXq } },
2383   },
2384
2385   /* PREFIX_0F11 */
2386   {
2387     { "movups", { EXx, XM } },
2388     { "movss",  { EXd, XM } },
2389     { "movupd", { EXx, XM } },
2390     { "movsd",  { EXq, XM } },
2391   },
2392
2393   /* PREFIX_0F12 */
2394   {
2395     { MOD_TABLE (MOD_0F12_PREFIX_0) },
2396     { "movsldup", { XM, EXx } },
2397     { "movlpd", { XM, EXq } },
2398     { "movddup", { XM, EXq } },
2399   },
2400
2401   /* PREFIX_0F16 */
2402   {
2403     { MOD_TABLE (MOD_0F16_PREFIX_0) },
2404     { "movshdup", { XM, EXx } },
2405     { "movhpd", { XM, EXq } },
2406     { "(bad)",  { XX } },
2407   },
2408
2409   /* PREFIX_0F2A */
2410   {
2411     { "cvtpi2ps", { XM, EMCq } },
2412     { "cvtsi2ss%LQ", { XM, Ev } },
2413     { "cvtpi2pd", { XM, EMCq } },
2414     { "cvtsi2sd%LQ", { XM, Ev } },
2415   },
2416
2417   /* PREFIX_0F2B */
2418   {
2419     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2420     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2421     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2422     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2423   },
2424
2425   /* PREFIX_0F2C */
2426   {
2427     { "cvttps2pi", { MXC, EXq } },
2428     { "cvttss2siY", { Gv, EXd } },
2429     { "cvttpd2pi", { MXC, EXx } },
2430     { "cvttsd2siY", { Gv, EXq } },
2431   },
2432
2433   /* PREFIX_0F2D */
2434   {
2435     { "cvtps2pi", { MXC, EXq } },
2436     { "cvtss2siY", { Gv, EXd } },
2437     { "cvtpd2pi", { MXC, EXx } },
2438     { "cvtsd2siY", { Gv, EXq } },
2439   },
2440
2441   /* PREFIX_0F2E */
2442   {
2443     { "ucomiss",{ XM, EXd } },
2444     { "(bad)",  { XX } },
2445     { "ucomisd",{ XM, EXq } },
2446     { "(bad)",  { XX } },
2447   },
2448
2449   /* PREFIX_0F2F */
2450   {
2451     { "comiss", { XM, EXd } },
2452     { "(bad)",  { XX } },
2453     { "comisd", { XM, EXq } },
2454     { "(bad)",  { XX } },
2455   },
2456
2457   /* PREFIX_0F51 */
2458   {
2459     { "sqrtps", { XM, EXx } },
2460     { "sqrtss", { XM, EXd } },
2461     { "sqrtpd", { XM, EXx } },
2462     { "sqrtsd", { XM, EXq } },
2463   },
2464
2465   /* PREFIX_0F52 */
2466   {
2467     { "rsqrtps",{ XM, EXx } },
2468     { "rsqrtss",{ XM, EXd } },
2469     { "(bad)",  { XX } },
2470     { "(bad)",  { XX } },
2471   },
2472
2473   /* PREFIX_0F53 */
2474   {
2475     { "rcpps",  { XM, EXx } },
2476     { "rcpss",  { XM, EXd } },
2477     { "(bad)",  { XX } },
2478     { "(bad)",  { XX } },
2479   },
2480
2481   /* PREFIX_0F58 */
2482   {
2483     { "addps", { XM, EXx } },
2484     { "addss", { XM, EXd } },
2485     { "addpd", { XM, EXx } },
2486     { "addsd", { XM, EXq } },
2487   },
2488
2489   /* PREFIX_0F59 */
2490   {
2491     { "mulps",  { XM, EXx } },
2492     { "mulss",  { XM, EXd } },
2493     { "mulpd",  { XM, EXx } },
2494     { "mulsd",  { XM, EXq } },
2495   },
2496
2497   /* PREFIX_0F5A */
2498   {
2499     { "cvtps2pd", { XM, EXq } },
2500     { "cvtss2sd", { XM, EXd } },
2501     { "cvtpd2ps", { XM, EXx } },
2502     { "cvtsd2ss", { XM, EXq } },
2503   },
2504
2505   /* PREFIX_0F5B */
2506   {
2507     { "cvtdq2ps", { XM, EXx } },
2508     { "cvttps2dq", { XM, EXx } },
2509     { "cvtps2dq", { XM, EXx } },
2510     { "(bad)",  { XX } },
2511   },
2512
2513   /* PREFIX_0F5C */
2514   {
2515     { "subps",  { XM, EXx } },
2516     { "subss",  { XM, EXd } },
2517     { "subpd",  { XM, EXx } },
2518     { "subsd",  { XM, EXq } },
2519   },
2520
2521   /* PREFIX_0F5D */
2522   {
2523     { "minps",  { XM, EXx } },
2524     { "minss",  { XM, EXd } },
2525     { "minpd",  { XM, EXx } },
2526     { "minsd",  { XM, EXq } },
2527   },
2528
2529   /* PREFIX_0F5E */
2530   {
2531     { "divps",  { XM, EXx } },
2532     { "divss",  { XM, EXd } },
2533     { "divpd",  { XM, EXx } },
2534     { "divsd",  { XM, EXq } },
2535   },
2536
2537   /* PREFIX_0F5F */
2538   {
2539     { "maxps",  { XM, EXx } },
2540     { "maxss",  { XM, EXd } },
2541     { "maxpd",  { XM, EXx } },
2542     { "maxsd",  { XM, EXq } },
2543   },
2544
2545   /* PREFIX_0F60 */
2546   {
2547     { "punpcklbw",{ MX, EMd } },
2548     { "(bad)",  { XX } },
2549     { "punpcklbw",{ MX, EMx } },
2550     { "(bad)",  { XX } },
2551   },
2552
2553   /* PREFIX_0F61 */
2554   {
2555     { "punpcklwd",{ MX, EMd } },
2556     { "(bad)",  { XX } },
2557     { "punpcklwd",{ MX, EMx } },
2558     { "(bad)",  { XX } },
2559   },
2560
2561   /* PREFIX_0F62 */
2562   {
2563     { "punpckldq",{ MX, EMd } },
2564     { "(bad)",  { XX } },
2565     { "punpckldq",{ MX, EMx } },
2566     { "(bad)",  { XX } },
2567   },
2568
2569   /* PREFIX_0F6C */
2570   {
2571     { "(bad)",  { XX } },
2572     { "(bad)",  { XX } },
2573     { "punpcklqdq", { XM, EXx } },
2574     { "(bad)",  { XX } },
2575   },
2576
2577   /* PREFIX_0F6D */
2578   {
2579     { "(bad)",  { XX } },
2580     { "(bad)",  { XX } },
2581     { "punpckhqdq", { XM, EXx } },
2582     { "(bad)",  { XX } },
2583   },
2584
2585   /* PREFIX_0F6F */
2586   {
2587     { "movq",   { MX, EM } },
2588     { "movdqu", { XM, EXx } },
2589     { "movdqa", { XM, EXx } },
2590     { "(bad)",  { XX } },
2591   },
2592
2593   /* PREFIX_0F70 */
2594   {
2595     { "pshufw", { MX, EM, Ib } },
2596     { "pshufhw",{ XM, EXx, Ib } },
2597     { "pshufd", { XM, EXx, Ib } },
2598     { "pshuflw",{ XM, EXx, Ib } },
2599   },
2600
2601   /* PREFIX_0F73_REG_3 */
2602   {
2603     { "(bad)",  { XX } },
2604     { "(bad)",  { XX } },
2605     { "psrldq", { XS, Ib } },
2606     { "(bad)",  { XX } },
2607   },
2608
2609   /* PREFIX_0F73_REG_7 */
2610   {
2611     { "(bad)",  { XX } },
2612     { "(bad)",  { XX } },
2613     { "pslldq", { XS, Ib } },
2614     { "(bad)",  { XX } },
2615   },
2616
2617   /* PREFIX_0F78 */
2618   {
2619     {"vmread",  { Em, Gm } },
2620     {"(bad)",   { XX } },
2621     {"extrq",   { XS, Ib, Ib } },
2622     {"insertq", { XM, XS, Ib, Ib } },
2623   },
2624
2625   /* PREFIX_0F79 */
2626   {
2627     {"vmwrite", { Gm, Em } },
2628     {"(bad)",   { XX } },
2629     {"extrq",   { XM, XS } },
2630     {"insertq", { XM, XS } },
2631   },
2632
2633   /* PREFIX_0F7C */
2634   {
2635     { "(bad)",  { XX } },
2636     { "(bad)",  { XX } },
2637     { "haddpd", { XM, EXx } },
2638     { "haddps", { XM, EXx } },
2639   },
2640
2641   /* PREFIX_0F7D */
2642   {
2643     { "(bad)",  { XX } },
2644     { "(bad)",  { XX } },
2645     { "hsubpd", { XM, EXx } },
2646     { "hsubps", { XM, EXx } },
2647   },
2648
2649   /* PREFIX_0F7E */
2650   {
2651     { "movK",   { Edq, MX } },
2652     { "movq",   { XM, EXq } },
2653     { "movK",   { Edq, XM } },
2654     { "(bad)",  { XX } },
2655   },
2656
2657   /* PREFIX_0F7F */
2658   {
2659     { "movq",   { EM, MX } },
2660     { "movdqu", { EXx, XM } },
2661     { "movdqa", { EXx, XM } },
2662     { "(bad)",  { XX } },
2663   },
2664
2665   /* PREFIX_0FB8 */
2666   {
2667     { "(bad)", { XX } },
2668     { "popcntS", { Gv, Ev } },
2669     { "(bad)", { XX } },
2670     { "(bad)", { XX } },
2671   },
2672
2673   /* PREFIX_0FBD */
2674   {
2675     { "bsrS",   { Gv, Ev } },
2676     { "lzcntS", { Gv, Ev } },
2677     { "bsrS",   { Gv, Ev } },
2678     { "(bad)",  { XX } },
2679   },
2680
2681   /* PREFIX_0FC2 */
2682   {
2683     { "cmpps",  { XM, EXx, CMP } },
2684     { "cmpss",  { XM, EXd, CMP } },
2685     { "cmppd",  { XM, EXx, CMP } },
2686     { "cmpsd",  { XM, EXq, CMP } },
2687   },
2688
2689   /* PREFIX_0FC3 */
2690   {
2691     { "movntiS", { Ma, Gv } },
2692     { "(bad)",  { XX } },
2693     { "(bad)",  { XX } },
2694     { "(bad)",  { XX } },
2695   },
2696
2697   /* PREFIX_0FC7_REG_6 */
2698   {
2699     { "vmptrld",{ Mq } },
2700     { "vmxon",  { Mq } },
2701     { "vmclear",{ Mq } },
2702     { "(bad)",  { XX } },
2703   },
2704
2705   /* PREFIX_0FD0 */
2706   {
2707     { "(bad)",  { XX } },
2708     { "(bad)",  { XX } },
2709     { "addsubpd", { XM, EXx } },
2710     { "addsubps", { XM, EXx } },
2711   },
2712
2713   /* PREFIX_0FD6 */
2714   {
2715     { "(bad)",  { XX } },
2716     { "movq2dq",{ XM, MS } },
2717     { "movq",   { EXq, XM } },
2718     { "movdq2q",{ MX, XS } },
2719   },
2720
2721   /* PREFIX_0FE6 */
2722   {
2723     { "(bad)",  { XX } },
2724     { "cvtdq2pd", { XM, EXq } },
2725     { "cvttpd2dq", { XM, EXx } },
2726     { "cvtpd2dq", { XM, EXx } },
2727   },
2728
2729   /* PREFIX_0FE7 */
2730   {
2731     { "movntq", { Mq, MX } },
2732     { "(bad)",  { XX } },
2733     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
2734     { "(bad)",  { XX } },
2735   },
2736
2737   /* PREFIX_0FF0 */
2738   {
2739     { "(bad)",  { XX } },
2740     { "(bad)",  { XX } },
2741     { "(bad)",  { XX } },
2742     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
2743   },
2744
2745   /* PREFIX_0FF7 */
2746   {
2747     { "maskmovq", { MX, MS } },
2748     { "(bad)",  { XX } },
2749     { "maskmovdqu", { XM, XS } },
2750     { "(bad)",  { XX } },
2751   },
2752
2753   /* PREFIX_0F3810 */
2754   {
2755     { "(bad)",  { XX } },
2756     { "(bad)",  { XX } },
2757     { "pblendvb", { XM, EXx, XMM0 } },
2758     { "(bad)",  { XX } },
2759   },
2760
2761   /* PREFIX_0F3814 */
2762   {
2763     { "(bad)",  { XX } },
2764     { "(bad)",  { XX } },
2765     { "blendvps", { XM, EXx, XMM0 } },
2766     { "(bad)",  { XX } },
2767   },
2768
2769   /* PREFIX_0F3815 */
2770   {
2771     { "(bad)",  { XX } },
2772     { "(bad)",  { XX } },
2773     { "blendvpd", { XM, EXx, XMM0 } },
2774     { "(bad)",  { XX } },
2775   },
2776
2777   /* PREFIX_0F3817 */
2778   {
2779     { "(bad)",  { XX } },
2780     { "(bad)",  { XX } },
2781     { "ptest",  { XM, EXx } },
2782     { "(bad)",  { XX } },
2783   },
2784
2785   /* PREFIX_0F3820 */
2786   {
2787     { "(bad)",  { XX } },
2788     { "(bad)",  { XX } },
2789     { "pmovsxbw", { XM, EXq } },
2790     { "(bad)",  { XX } },
2791   },
2792
2793   /* PREFIX_0F3821 */
2794   {
2795     { "(bad)",  { XX } },
2796     { "(bad)",  { XX } },
2797     { "pmovsxbd", { XM, EXd } },
2798     { "(bad)",  { XX } },
2799   },
2800
2801   /* PREFIX_0F3822 */
2802   {
2803     { "(bad)",  { XX } },
2804     { "(bad)",  { XX } },
2805     { "pmovsxbq", { XM, EXw } },
2806     { "(bad)",  { XX } },
2807   },
2808
2809   /* PREFIX_0F3823 */
2810   {
2811     { "(bad)",  { XX } },
2812     { "(bad)",  { XX } },
2813     { "pmovsxwd", { XM, EXq } },
2814     { "(bad)",  { XX } },
2815   },
2816
2817   /* PREFIX_0F3824 */
2818   {
2819     { "(bad)",  { XX } },
2820     { "(bad)",  { XX } },
2821     { "pmovsxwq", { XM, EXd } },
2822     { "(bad)",  { XX } },
2823   },
2824
2825   /* PREFIX_0F3825 */
2826   {
2827     { "(bad)",  { XX } },
2828     { "(bad)",  { XX } },
2829     { "pmovsxdq", { XM, EXq } },
2830     { "(bad)",  { XX } },
2831   },
2832
2833   /* PREFIX_0F3828 */
2834   {
2835     { "(bad)",  { XX } },
2836     { "(bad)",  { XX } },
2837     { "pmuldq", { XM, EXx } },
2838     { "(bad)",  { XX } },
2839   },
2840
2841   /* PREFIX_0F3829 */
2842   {
2843     { "(bad)",  { XX } },
2844     { "(bad)",  { XX } },
2845     { "pcmpeqq", { XM, EXx } },
2846     { "(bad)",  { XX } },
2847   },
2848
2849   /* PREFIX_0F382A */
2850   {
2851     { "(bad)",  { XX } },
2852     { "(bad)",  { XX } },
2853     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
2854     { "(bad)",  { XX } },
2855   },
2856
2857   /* PREFIX_0F382B */
2858   {
2859     { "(bad)",  { XX } },
2860     { "(bad)",  { XX } },
2861     { "packusdw", { XM, EXx } },
2862     { "(bad)",  { XX } },
2863   },
2864
2865   /* PREFIX_0F3830 */
2866   {
2867     { "(bad)",  { XX } },
2868     { "(bad)",  { XX } },
2869     { "pmovzxbw", { XM, EXq } },
2870     { "(bad)",  { XX } },
2871   },
2872
2873   /* PREFIX_0F3831 */
2874   {
2875     { "(bad)",  { XX } },
2876     { "(bad)",  { XX } },
2877     { "pmovzxbd", { XM, EXd } },
2878     { "(bad)",  { XX } },
2879   },
2880
2881   /* PREFIX_0F3832 */
2882   {
2883     { "(bad)",  { XX } },
2884     { "(bad)",  { XX } },
2885     { "pmovzxbq", { XM, EXw } },
2886     { "(bad)",  { XX } },
2887   },
2888
2889   /* PREFIX_0F3833 */
2890   {
2891     { "(bad)",  { XX } },
2892     { "(bad)",  { XX } },
2893     { "pmovzxwd", { XM, EXq } },
2894     { "(bad)",  { XX } },
2895   },
2896
2897   /* PREFIX_0F3834 */
2898   {
2899     { "(bad)",  { XX } },
2900     { "(bad)",  { XX } },
2901     { "pmovzxwq", { XM, EXd } },
2902     { "(bad)",  { XX } },
2903   },
2904
2905   /* PREFIX_0F3835 */
2906   {
2907     { "(bad)",  { XX } },
2908     { "(bad)",  { XX } },
2909     { "pmovzxdq", { XM, EXq } },
2910     { "(bad)",  { XX } },
2911   },
2912
2913   /* PREFIX_0F3837 */
2914   {
2915     { "(bad)",  { XX } },
2916     { "(bad)",  { XX } },
2917     { "pcmpgtq", { XM, EXx } },
2918     { "(bad)",  { XX } },
2919   },
2920
2921   /* PREFIX_0F3838 */
2922   {
2923     { "(bad)",  { XX } },
2924     { "(bad)",  { XX } },
2925     { "pminsb", { XM, EXx } },
2926     { "(bad)",  { XX } },
2927   },
2928
2929   /* PREFIX_0F3839 */
2930   {
2931     { "(bad)",  { XX } },
2932     { "(bad)",  { XX } },
2933     { "pminsd", { XM, EXx } },
2934     { "(bad)",  { XX } },
2935   },
2936
2937   /* PREFIX_0F383A */
2938   {
2939     { "(bad)",  { XX } },
2940     { "(bad)",  { XX } },
2941     { "pminuw", { XM, EXx } },
2942     { "(bad)",  { XX } },
2943   },
2944
2945   /* PREFIX_0F383B */
2946   {
2947     { "(bad)",  { XX } },
2948     { "(bad)",  { XX } },
2949     { "pminud", { XM, EXx } },
2950     { "(bad)",  { XX } },
2951   },
2952
2953   /* PREFIX_0F383C */
2954   {
2955     { "(bad)",  { XX } },
2956     { "(bad)",  { XX } },
2957     { "pmaxsb", { XM, EXx } },
2958     { "(bad)",  { XX } },
2959   },
2960
2961   /* PREFIX_0F383D */
2962   {
2963     { "(bad)",  { XX } },
2964     { "(bad)",  { XX } },
2965     { "pmaxsd", { XM, EXx } },
2966     { "(bad)",  { XX } },
2967   },
2968
2969   /* PREFIX_0F383E */
2970   {
2971     { "(bad)",  { XX } },
2972     { "(bad)",  { XX } },
2973     { "pmaxuw", { XM, EXx } },
2974     { "(bad)",  { XX } },
2975   },
2976
2977   /* PREFIX_0F383F */
2978   {
2979     { "(bad)",  { XX } },
2980     { "(bad)",  { XX } },
2981     { "pmaxud", { XM, EXx } },
2982     { "(bad)",  { XX } },
2983   },
2984
2985   /* PREFIX_0F3840 */
2986   {
2987     { "(bad)",  { XX } },
2988     { "(bad)",  { XX } },
2989     { "pmulld", { XM, EXx } },
2990     { "(bad)",  { XX } },
2991   },
2992
2993   /* PREFIX_0F3841 */
2994   {
2995     { "(bad)",  { XX } },
2996     { "(bad)",  { XX } },
2997     { "phminposuw", { XM, EXx } },
2998     { "(bad)",  { XX } },
2999   },
3000
3001   /* PREFIX_0F38DB */
3002   {
3003     { "(bad)",  { XX } },
3004     { "(bad)",  { XX } },
3005     { "aesimc", { XM, EXx } },
3006     { "(bad)",  { XX } },
3007   },
3008
3009   /* PREFIX_0F38DC */
3010   {
3011     { "(bad)",  { XX } },
3012     { "(bad)",  { XX } },
3013     { "aesenc", { XM, EXx } },
3014     { "(bad)",  { XX } },
3015   },
3016
3017   /* PREFIX_0F38DD */
3018   {
3019     { "(bad)",  { XX } },
3020     { "(bad)",  { XX } },
3021     { "aesenclast", { XM, EXx } },
3022     { "(bad)",  { XX } },
3023   },
3024
3025   /* PREFIX_0F38DE */
3026   {
3027     { "(bad)",  { XX } },
3028     { "(bad)",  { XX } },
3029     { "aesdec", { XM, EXx } },
3030     { "(bad)",  { XX } },
3031   },
3032
3033   /* PREFIX_0F38DF */
3034   {
3035     { "(bad)",  { XX } },
3036     { "(bad)",  { XX } },
3037     { "aesdeclast", { XM, EXx } },
3038     { "(bad)",  { XX } },
3039   },
3040
3041   /* PREFIX_0F38F0 */
3042   {
3043     { "(bad)",  { XX } },
3044     { "(bad)",  { XX } },
3045     { "(bad)",  { XX } },
3046     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
3047   },
3048
3049   /* PREFIX_0F38F1 */
3050   {
3051     { "(bad)",  { XX } },
3052     { "(bad)",  { XX } },
3053     { "(bad)",  { XX } },
3054     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
3055   },
3056
3057   /* PREFIX_0F3A08 */
3058   {
3059     { "(bad)",  { XX } },
3060     { "(bad)",  { XX } },
3061     { "roundps", { XM, EXx, Ib } },
3062     { "(bad)",  { XX } },
3063   },
3064
3065   /* PREFIX_0F3A09 */
3066   {
3067     { "(bad)",  { XX } },
3068     { "(bad)",  { XX } },
3069     { "roundpd", { XM, EXx, Ib } },
3070     { "(bad)",  { XX } },
3071   },
3072
3073   /* PREFIX_0F3A0A */
3074   {
3075     { "(bad)",  { XX } },
3076     { "(bad)",  { XX } },
3077     { "roundss", { XM, EXd, Ib } },
3078     { "(bad)",  { XX } },
3079   },
3080
3081   /* PREFIX_0F3A0B */
3082   {
3083     { "(bad)",  { XX } },
3084     { "(bad)",  { XX } },
3085     { "roundsd", { XM, EXq, Ib } },
3086     { "(bad)",  { XX } },
3087   },
3088
3089   /* PREFIX_0F3A0C */
3090   {
3091     { "(bad)",  { XX } },
3092     { "(bad)",  { XX } },
3093     { "blendps", { XM, EXx, Ib } },
3094     { "(bad)",  { XX } },
3095   },
3096
3097   /* PREFIX_0F3A0D */
3098   {
3099     { "(bad)",  { XX } },
3100     { "(bad)",  { XX } },
3101     { "blendpd", { XM, EXx, Ib } },
3102     { "(bad)",  { XX } },
3103   },
3104
3105   /* PREFIX_0F3A0E */
3106   {
3107     { "(bad)",  { XX } },
3108     { "(bad)",  { XX } },
3109     { "pblendw", { XM, EXx, Ib } },
3110     { "(bad)",  { XX } },
3111   },
3112
3113   /* PREFIX_0F3A14 */
3114   {
3115     { "(bad)",  { XX } },
3116     { "(bad)",  { XX } },
3117     { "pextrb", { Edqb, XM, Ib } },
3118     { "(bad)",  { XX } },
3119   },
3120
3121   /* PREFIX_0F3A15 */
3122   {
3123     { "(bad)",  { XX } },
3124     { "(bad)",  { XX } },
3125     { "pextrw", { Edqw, XM, Ib } },
3126     { "(bad)",  { XX } },
3127   },
3128
3129   /* PREFIX_0F3A16 */
3130   {
3131     { "(bad)",  { XX } },
3132     { "(bad)",  { XX } },
3133     { "pextrK", { Edq, XM, Ib } },
3134     { "(bad)",  { XX } },
3135   },
3136
3137   /* PREFIX_0F3A17 */
3138   {
3139     { "(bad)",  { XX } },
3140     { "(bad)",  { XX } },
3141     { "extractps", { Edqd, XM, Ib } },
3142     { "(bad)",  { XX } },
3143   },
3144
3145   /* PREFIX_0F3A20 */
3146   {
3147     { "(bad)",  { XX } },
3148     { "(bad)",  { XX } },
3149     { "pinsrb", { XM, Edqb, Ib } },
3150     { "(bad)",  { XX } },
3151   },
3152
3153   /* PREFIX_0F3A21 */
3154   {
3155     { "(bad)",  { XX } },
3156     { "(bad)",  { XX } },
3157     { "insertps", { XM, EXd, Ib } },
3158     { "(bad)",  { XX } },
3159   },
3160
3161   /* PREFIX_0F3A22 */
3162   {
3163     { "(bad)",  { XX } },
3164     { "(bad)",  { XX } },
3165     { "pinsrK", { XM, Edq, Ib } },
3166     { "(bad)",  { XX } },
3167   },
3168
3169   /* PREFIX_0F3A40 */
3170   {
3171     { "(bad)",  { XX } },
3172     { "(bad)",  { XX } },
3173     { "dpps",   { XM, EXx, Ib } },
3174     { "(bad)",  { XX } },
3175   },
3176
3177   /* PREFIX_0F3A41 */
3178   {
3179     { "(bad)",  { XX } },
3180     { "(bad)",  { XX } },
3181     { "dppd",   { XM, EXx, Ib } },
3182     { "(bad)",  { XX } },
3183   },
3184
3185   /* PREFIX_0F3A42 */
3186   {
3187     { "(bad)",  { XX } },
3188     { "(bad)",  { XX } },
3189     { "mpsadbw", { XM, EXx, Ib } },
3190     { "(bad)",  { XX } },
3191   },
3192
3193   /* PREFIX_0F3A44 */
3194   {
3195     { "(bad)",  { XX } },
3196     { "(bad)",  { XX } },
3197     { "pclmulqdq", { XM, EXx, PCLMUL } },
3198     { "(bad)",  { XX } },
3199   },
3200
3201   /* PREFIX_0F3A60 */
3202   {
3203     { "(bad)",  { XX } },
3204     { "(bad)",  { XX } },
3205     { "pcmpestrm", { XM, EXx, Ib } },
3206     { "(bad)",  { XX } },
3207   },
3208
3209   /* PREFIX_0F3A61 */
3210   {
3211     { "(bad)",  { XX } },
3212     { "(bad)",  { XX } },
3213     { "pcmpestri", { XM, EXx, Ib } },
3214     { "(bad)",  { XX } },
3215   },
3216
3217   /* PREFIX_0F3A62 */
3218   {
3219     { "(bad)",  { XX } },
3220     { "(bad)",  { XX } },
3221     { "pcmpistrm", { XM, EXx, Ib } },
3222     { "(bad)",  { XX } },
3223   },
3224
3225   /* PREFIX_0F3A63 */
3226   {
3227     { "(bad)",  { XX } },
3228     { "(bad)",  { XX } },
3229     { "pcmpistri", { XM, EXx, Ib } },
3230     { "(bad)",  { XX } },
3231   },
3232
3233   /* PREFIX_0F3ADF */
3234   {
3235     { "(bad)",  { XX } },
3236     { "(bad)",  { XX } },
3237     { "aeskeygenassist", { XM, EXx, Ib } },
3238     { "(bad)",  { XX } },
3239   },
3240
3241   /* PREFIX_VEX_10 */
3242   {
3243     { "vmovups", { XM, EXx } },
3244     { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3245     { "vmovupd", { XM, EXx } },
3246     { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
3247   },
3248
3249   /* PREFIX_VEX_11 */
3250   {
3251     { "vmovups", { EXx, XM } },
3252     { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3253     { "vmovupd", { EXx, XM } },
3254     { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
3255   },
3256
3257   /* PREFIX_VEX_12 */
3258   {
3259     { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3260     { "vmovsldup", { XM, EXx } },
3261     { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3262     { "vmovddup", { XM, EXymmq } },
3263   },
3264
3265   /* PREFIX_VEX_16 */
3266   {
3267     { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3268     { "vmovshdup", { XM, EXx } },
3269     { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3270     { "(bad)",  { XX } },
3271   },
3272
3273   /* PREFIX_VEX_2A */
3274   {
3275     { "(bad)",  { XX } },
3276     { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3277     { "(bad)",  { XX } },
3278     { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
3279   },
3280
3281   /* PREFIX_VEX_2C */
3282   {
3283     { "(bad)",  { XX } },
3284     { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3285     { "(bad)",  { XX } },
3286     { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
3287   },
3288
3289   /* PREFIX_VEX_2D */
3290   {
3291     { "(bad)",  { XX } },
3292     { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3293     { "(bad)",  { XX } },
3294     { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
3295   },
3296
3297   /* PREFIX_VEX_2E */
3298   {
3299     { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3300     { "(bad)",  { XX } },
3301     { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3302     { "(bad)",  { XX } },
3303   },
3304
3305   /* PREFIX_VEX_2F */
3306   {
3307     { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3308     { "(bad)",  { XX } },
3309     { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3310     { "(bad)",  { XX } },
3311   },
3312
3313   /* PREFIX_VEX_51 */
3314   {
3315     { "vsqrtps", { XM, EXx } },
3316     { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3317     { "vsqrtpd", { XM, EXx } },
3318     { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
3319   },
3320
3321   /* PREFIX_VEX_52 */
3322   {
3323     { "vrsqrtps", { XM, EXx } },
3324     { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3325     { "(bad)",  { XX } },
3326     { "(bad)",  { XX } },
3327   },
3328
3329   /* PREFIX_VEX_53 */
3330   {
3331     { "vrcpps", { XM, EXx } },
3332     { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3333     { "(bad)",  { XX } },
3334     { "(bad)",  { XX } },
3335   },
3336
3337   /* PREFIX_VEX_58 */
3338   {
3339     { "vaddps", { XM, Vex, EXx } },
3340     { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3341     { "vaddpd", { XM, Vex, EXx } },
3342     { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
3343   },
3344
3345   /* PREFIX_VEX_59 */
3346   {
3347     { "vmulps", { XM, Vex, EXx } },
3348     { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3349     { "vmulpd", { XM, Vex, EXx } },
3350     { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
3351   },
3352
3353   /* PREFIX_VEX_5A */
3354   {
3355     { "vcvtps2pd", { XM, EXxmmq } },
3356     { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3357     { "vcvtpd2ps%XY", { XMM, EXx } },
3358     { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
3359   },
3360
3361   /* PREFIX_VEX_5B */
3362   {
3363     { "vcvtdq2ps", { XM, EXx } },
3364     { "vcvttps2dq", { XM, EXx } },
3365     { "vcvtps2dq", { XM, EXx } },
3366     { "(bad)",  { XX } },
3367   },
3368
3369   /* PREFIX_VEX_5C */
3370   {
3371     { "vsubps", { XM, Vex, EXx } },
3372     { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3373     { "vsubpd", { XM, Vex, EXx } },
3374     { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
3375   },
3376
3377   /* PREFIX_VEX_5D */
3378   {
3379     { "vminps", { XM, Vex, EXx } },
3380     { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3381     { "vminpd", { XM, Vex, EXx } },
3382     { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
3383   },
3384
3385   /* PREFIX_VEX_5E */
3386   {
3387     { "vdivps", { XM, Vex, EXx } },
3388     { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3389     { "vdivpd", { XM, Vex, EXx } },
3390     { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
3391   },
3392
3393   /* PREFIX_VEX_5F */
3394   {
3395     { "vmaxps", { XM, Vex, EXx } },
3396     { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3397     { "vmaxpd", { XM, Vex, EXx } },
3398     { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
3399   },
3400
3401   /* PREFIX_VEX_60 */
3402   {
3403     { "(bad)",  { XX } },
3404     { "(bad)",  { XX } },
3405     { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3406     { "(bad)",  { XX } },
3407   },
3408
3409   /* PREFIX_VEX_61 */
3410   {
3411     { "(bad)",  { XX } },
3412     { "(bad)",  { XX } },
3413     { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3414     { "(bad)",  { XX } },
3415   },
3416
3417   /* PREFIX_VEX_62 */
3418   {
3419     { "(bad)",  { XX } },
3420     { "(bad)",  { XX } },
3421     { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3422     { "(bad)",  { XX } },
3423   },
3424
3425   /* PREFIX_VEX_63 */
3426   {
3427     { "(bad)",  { XX } },
3428     { "(bad)",  { XX } },
3429     { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3430     { "(bad)",  { XX } },
3431   },
3432
3433   /* PREFIX_VEX_64 */
3434   {
3435     { "(bad)",  { XX } },
3436     { "(bad)",  { XX } },
3437     { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3438     { "(bad)",  { XX } },
3439   },
3440
3441   /* PREFIX_VEX_65 */
3442   {
3443     { "(bad)",  { XX } },
3444     { "(bad)",  { XX } },
3445     { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3446     { "(bad)",  { XX } },
3447   },
3448
3449   /* PREFIX_VEX_66 */
3450   {
3451     { "(bad)",  { XX } },
3452     { "(bad)",  { XX } },
3453     { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3454     { "(bad)",  { XX } },
3455   },
3456
3457   /* PREFIX_VEX_67 */
3458   {
3459     { "(bad)",  { XX } },
3460     { "(bad)",  { XX } },
3461     { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3462     { "(bad)",  { XX } },
3463   },
3464
3465   /* PREFIX_VEX_68 */
3466   {
3467     { "(bad)",  { XX } },
3468     { "(bad)",  { XX } },
3469     { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3470     { "(bad)",  { XX } },
3471   },
3472
3473   /* PREFIX_VEX_69 */
3474   {
3475     { "(bad)",  { XX } },
3476     { "(bad)",  { XX } },
3477     { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3478     { "(bad)",  { XX } },
3479   },
3480
3481   /* PREFIX_VEX_6A */
3482   {
3483     { "(bad)",  { XX } },
3484     { "(bad)",  { XX } },
3485     { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3486     { "(bad)",  { XX } },
3487   },
3488
3489   /* PREFIX_VEX_6B */
3490   {
3491     { "(bad)",  { XX } },
3492     { "(bad)",  { XX } },
3493     { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3494     { "(bad)",  { XX } },
3495   },
3496
3497   /* PREFIX_VEX_6C */
3498   {
3499     { "(bad)",  { XX } },
3500     { "(bad)",  { XX } },
3501     { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3502     { "(bad)",  { XX } },
3503   },
3504
3505   /* PREFIX_VEX_6D */
3506   {
3507     { "(bad)",  { XX } },
3508     { "(bad)",  { XX } },
3509     { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3510     { "(bad)",  { XX } },
3511   },
3512
3513   /* PREFIX_VEX_6E */
3514   {
3515     { "(bad)",  { XX } },
3516     { "(bad)",  { XX } },
3517     { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3518     { "(bad)",  { XX } },
3519   },
3520
3521   /* PREFIX_VEX_6F */
3522   {
3523     { "(bad)",  { XX } },
3524     { "vmovdqu", { XM, EXx } },
3525     { "vmovdqa", { XM, EXx } },
3526     { "(bad)",  { XX } },
3527   },
3528
3529   /* PREFIX_VEX_70 */
3530   {
3531     { "(bad)",  { XX } },
3532     { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3533     { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3534     { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3535   },
3536
3537   /* PREFIX_VEX_71_REG_2 */
3538   {
3539     { "(bad)",  { XX } },
3540     { "(bad)",  { XX } },
3541     { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3542     { "(bad)",  { XX } },
3543   },
3544
3545   /* PREFIX_VEX_71_REG_4 */
3546   {
3547     { "(bad)",  { XX } },
3548     { "(bad)",  { XX } },
3549     { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3550     { "(bad)",  { XX } },
3551   },
3552
3553   /* PREFIX_VEX_71_REG_6 */
3554   {
3555     { "(bad)",  { XX } },
3556     { "(bad)",  { XX } },
3557     { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3558     { "(bad)",  { XX } },
3559   },
3560
3561   /* PREFIX_VEX_72_REG_2 */
3562   {
3563     { "(bad)",  { XX } },
3564     { "(bad)",  { XX } },
3565     { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3566     { "(bad)",  { XX } },
3567   },
3568
3569   /* PREFIX_VEX_72_REG_4 */
3570   {
3571     { "(bad)",  { XX } },
3572     { "(bad)",  { XX } },
3573     { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3574     { "(bad)",  { XX } },
3575   },
3576
3577   /* PREFIX_VEX_72_REG_6 */
3578   {
3579     { "(bad)",  { XX } },
3580     { "(bad)",  { XX } },
3581     { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3582     { "(bad)",  { XX } },
3583   },
3584
3585   /* PREFIX_VEX_73_REG_2 */
3586   {
3587     { "(bad)",  { XX } },
3588     { "(bad)",  { XX } },
3589     { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3590     { "(bad)",  { XX } },
3591   },
3592
3593   /* PREFIX_VEX_73_REG_3 */
3594   {
3595     { "(bad)",  { XX } },
3596     { "(bad)",  { XX } },
3597     { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3598     { "(bad)",  { XX } },
3599   },
3600
3601   /* PREFIX_VEX_73_REG_6 */
3602   {
3603     { "(bad)",  { XX } },
3604     { "(bad)",  { XX } },
3605     { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3606     { "(bad)",  { XX } },
3607   },
3608
3609   /* PREFIX_VEX_73_REG_7 */
3610   {
3611     { "(bad)",  { XX } },
3612     { "(bad)",  { XX } },
3613     { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3614     { "(bad)",  { XX } },
3615   },
3616
3617   /* PREFIX_VEX_74 */
3618   {
3619     { "(bad)",  { XX } },
3620     { "(bad)",  { XX } },
3621     { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3622     { "(bad)",  { XX } },
3623   },
3624
3625   /* PREFIX_VEX_75 */
3626   {
3627     { "(bad)",  { XX } },
3628     { "(bad)",  { XX } },
3629     { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3630     { "(bad)",  { XX } },
3631   },
3632
3633   /* PREFIX_VEX_76 */
3634   {
3635     { "(bad)",  { XX } },
3636     { "(bad)",  { XX } },
3637     { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3638     { "(bad)",  { XX } },
3639   },
3640
3641   /* PREFIX_VEX_77 */
3642   {
3643     { "",       { VZERO } },
3644     { "(bad)",  { XX } },
3645     { "(bad)",  { XX } },
3646     { "(bad)",  { XX } },
3647   },
3648
3649   /* PREFIX_VEX_7C */
3650   {
3651     { "(bad)",  { XX } },
3652     { "(bad)",  { XX } },
3653     { "vhaddpd", { XM, Vex, EXx } },
3654     { "vhaddps", { XM, Vex, EXx } },
3655   },
3656
3657   /* PREFIX_VEX_7D */
3658   {
3659     { "(bad)",  { XX } },
3660     { "(bad)",  { XX } },
3661     { "vhsubpd", { XM, Vex, EXx } },
3662     { "vhsubps", { XM, Vex, EXx } },
3663   },
3664
3665   /* PREFIX_VEX_7E */
3666   {
3667     { "(bad)",  { XX } },
3668     { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3669     { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3670     { "(bad)",  { XX } },
3671   },
3672
3673   /* PREFIX_VEX_7F */
3674   {
3675     { "(bad)",  { XX } },
3676     { "vmovdqu", { EXx, XM } },
3677     { "vmovdqa", { EXx, XM } },
3678     { "(bad)",  { XX } },
3679   },
3680
3681   /* PREFIX_VEX_C2 */
3682   {
3683     { "vcmpps", { XM, Vex, EXx, VCMP } },
3684     { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3685     { "vcmppd", { XM, Vex, EXx, VCMP } },
3686     { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3687   },
3688
3689   /* PREFIX_VEX_C4 */
3690   {
3691     { "(bad)",  { XX } },
3692     { "(bad)",  { XX } },
3693     { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3694     { "(bad)",  { XX } },
3695   },
3696
3697   /* PREFIX_VEX_C5 */
3698   {
3699     { "(bad)",  { XX } },
3700     { "(bad)",  { XX } },
3701     { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3702     { "(bad)",  { XX } },
3703   },
3704
3705   /* PREFIX_VEX_D0 */
3706   {
3707     { "(bad)",  { XX } },
3708     { "(bad)",  { XX } },
3709     { "vaddsubpd", { XM, Vex, EXx } },
3710     { "vaddsubps", { XM, Vex, EXx } },
3711   },
3712
3713   /* PREFIX_VEX_D1 */
3714   {
3715     { "(bad)",  { XX } },
3716     { "(bad)",  { XX } },
3717     { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3718     { "(bad)",  { XX } },
3719   },
3720
3721   /* PREFIX_VEX_D2 */
3722   {
3723     { "(bad)",  { XX } },
3724     { "(bad)",  { XX } },
3725     { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3726     { "(bad)",  { XX } },
3727   },
3728
3729   /* PREFIX_VEX_D3 */
3730   {
3731     { "(bad)",  { XX } },
3732     { "(bad)",  { XX } },
3733     { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
3734     { "(bad)",  { XX } },
3735   },
3736
3737   /* PREFIX_VEX_D4 */
3738   {
3739     { "(bad)",  { XX } },
3740     { "(bad)",  { XX } },
3741     { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
3742     { "(bad)",  { XX } },
3743   },
3744
3745   /* PREFIX_VEX_D5 */
3746   {
3747     { "(bad)",  { XX } },
3748     { "(bad)",  { XX } },
3749     { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
3750     { "(bad)",  { XX } },
3751   },
3752
3753   /* PREFIX_VEX_D6 */
3754   {
3755     { "(bad)",  { XX } },
3756     { "(bad)",  { XX } },
3757     { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
3758     { "(bad)",  { XX } },
3759   },
3760
3761   /* PREFIX_VEX_D7 */
3762   {
3763     { "(bad)",  { XX } },
3764     { "(bad)",  { XX } },
3765     { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
3766     { "(bad)",  { XX } },
3767   },
3768
3769   /* PREFIX_VEX_D8 */
3770   {
3771     { "(bad)",  { XX } },
3772     { "(bad)",  { XX } },
3773     { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
3774     { "(bad)",  { XX } },
3775   },
3776
3777   /* PREFIX_VEX_D9 */
3778   {
3779     { "(bad)",  { XX } },
3780     { "(bad)",  { XX } },
3781     { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
3782     { "(bad)",  { XX } },
3783   },
3784
3785   /* PREFIX_VEX_DA */
3786   {
3787     { "(bad)",  { XX } },
3788     { "(bad)",  { XX } },
3789     { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
3790     { "(bad)",  { XX } },
3791   },
3792
3793   /* PREFIX_VEX_DB */
3794   {
3795     { "(bad)",  { XX } },
3796     { "(bad)",  { XX } },
3797     { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
3798     { "(bad)",  { XX } },
3799   },
3800
3801   /* PREFIX_VEX_DC */
3802   {
3803     { "(bad)",  { XX } },
3804     { "(bad)",  { XX } },
3805     { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
3806     { "(bad)",  { XX } },
3807   },
3808
3809   /* PREFIX_VEX_DD */
3810   {
3811     { "(bad)",  { XX } },
3812     { "(bad)",  { XX } },
3813     { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
3814     { "(bad)",  { XX } },
3815   },
3816
3817   /* PREFIX_VEX_DE */
3818   {
3819     { "(bad)",  { XX } },
3820     { "(bad)",  { XX } },
3821     { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
3822     { "(bad)",  { XX } },
3823   },
3824
3825   /* PREFIX_VEX_DF */
3826   {
3827     { "(bad)",  { XX } },
3828     { "(bad)",  { XX } },
3829     { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
3830     { "(bad)",  { XX } },
3831   },
3832
3833   /* PREFIX_VEX_E0 */
3834   {
3835     { "(bad)",  { XX } },
3836     { "(bad)",  { XX } },
3837     { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
3838     { "(bad)",  { XX } },
3839   },
3840
3841   /* PREFIX_VEX_E1 */
3842   {
3843     { "(bad)",  { XX } },
3844     { "(bad)",  { XX } },
3845     { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
3846     { "(bad)",  { XX } },
3847   },
3848
3849   /* PREFIX_VEX_E2 */
3850   {
3851     { "(bad)",  { XX } },
3852     { "(bad)",  { XX } },
3853     { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
3854     { "(bad)",  { XX } },
3855   },
3856
3857   /* PREFIX_VEX_E3 */
3858   {
3859     { "(bad)",  { XX } },
3860     { "(bad)",  { XX } },
3861     { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
3862     { "(bad)",  { XX } },
3863   },
3864
3865   /* PREFIX_VEX_E4 */
3866   {
3867     { "(bad)",  { XX } },
3868     { "(bad)",  { XX } },
3869     { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
3870     { "(bad)",  { XX } },
3871   },
3872
3873   /* PREFIX_VEX_E5 */
3874   {
3875     { "(bad)",  { XX } },
3876     { "(bad)",  { XX } },
3877     { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
3878     { "(bad)",  { XX } },
3879   },
3880
3881   /* PREFIX_VEX_E6 */
3882   {
3883     { "(bad)",  { XX } },
3884     { "vcvtdq2pd", { XM, EXxmmq } },
3885     { "vcvttpd2dq%XY", { XMM, EXx } },
3886     { "vcvtpd2dq%XY", { XMM, EXx } },
3887   },
3888
3889   /* PREFIX_VEX_E7 */
3890   {
3891     { "(bad)",  { XX } },
3892     { "(bad)",  { XX } },
3893     { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
3894     { "(bad)",  { XX } },
3895   },
3896
3897   /* PREFIX_VEX_E8 */
3898   {
3899     { "(bad)",  { XX } },
3900     { "(bad)",  { XX } },
3901     { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
3902     { "(bad)",  { XX } },
3903   },
3904
3905   /* PREFIX_VEX_E9 */
3906   {
3907     { "(bad)",  { XX } },
3908     { "(bad)",  { XX } },
3909     { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
3910     { "(bad)",  { XX } },
3911   },
3912
3913   /* PREFIX_VEX_EA */
3914   {
3915     { "(bad)",  { XX } },
3916     { "(bad)",  { XX } },
3917     { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
3918     { "(bad)",  { XX } },
3919   },
3920
3921   /* PREFIX_VEX_EB */
3922   {
3923     { "(bad)",  { XX } },
3924     { "(bad)",  { XX } },
3925     { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
3926     { "(bad)",  { XX } },
3927   },
3928
3929   /* PREFIX_VEX_EC */
3930   {
3931     { "(bad)",  { XX } },
3932     { "(bad)",  { XX } },
3933     { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
3934     { "(bad)",  { XX } },
3935   },
3936
3937   /* PREFIX_VEX_ED */
3938   {
3939     { "(bad)",  { XX } },
3940     { "(bad)",  { XX } },
3941     { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
3942     { "(bad)",  { XX } },
3943   },
3944
3945   /* PREFIX_VEX_EE */
3946   {
3947     { "(bad)",  { XX } },
3948     { "(bad)",  { XX } },
3949     { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
3950     { "(bad)",  { XX } },
3951   },
3952
3953   /* PREFIX_VEX_EF */
3954   {
3955     { "(bad)",  { XX } },
3956     { "(bad)",  { XX } },
3957     { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
3958     { "(bad)",  { XX } },
3959   },
3960
3961   /* PREFIX_VEX_F0 */
3962   {
3963     { "(bad)",  { XX } },
3964     { "(bad)",  { XX } },
3965     { "(bad)",  { XX } },
3966     { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
3967   },
3968
3969   /* PREFIX_VEX_F1 */
3970   {
3971     { "(bad)",  { XX } },
3972     { "(bad)",  { XX } },
3973     { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
3974     { "(bad)",  { XX } },
3975   },
3976
3977   /* PREFIX_VEX_F2 */
3978   {
3979     { "(bad)",  { XX } },
3980     { "(bad)",  { XX } },
3981     { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
3982     { "(bad)",  { XX } },
3983   },
3984
3985   /* PREFIX_VEX_F3 */
3986   {
3987     { "(bad)",  { XX } },
3988     { "(bad)",  { XX } },
3989     { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
3990     { "(bad)",  { XX } },
3991   },
3992
3993   /* PREFIX_VEX_F4 */
3994   {
3995     { "(bad)",  { XX } },
3996     { "(bad)",  { XX } },
3997     { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
3998     { "(bad)",  { XX } },
3999   },
4000
4001   /* PREFIX_VEX_F5 */
4002   {
4003     { "(bad)",  { XX } },
4004     { "(bad)",  { XX } },
4005     { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4006     { "(bad)",  { XX } },
4007   },
4008
4009   /* PREFIX_VEX_F6 */
4010   {
4011     { "(bad)",  { XX } },
4012     { "(bad)",  { XX } },
4013     { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4014     { "(bad)",  { XX } },
4015   },
4016
4017   /* PREFIX_VEX_F7 */
4018   {
4019     { "(bad)",  { XX } },
4020     { "(bad)",  { XX } },
4021     { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4022     { "(bad)",  { XX } },
4023   },
4024
4025   /* PREFIX_VEX_F8 */
4026   {
4027     { "(bad)",  { XX } },
4028     { "(bad)",  { XX } },
4029     { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4030     { "(bad)",  { XX } },
4031   },
4032
4033   /* PREFIX_VEX_F9 */
4034   {
4035     { "(bad)",  { XX } },
4036     { "(bad)",  { XX } },
4037     { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4038     { "(bad)",  { XX } },
4039   },
4040
4041   /* PREFIX_VEX_FA */
4042   {
4043     { "(bad)",  { XX } },
4044     { "(bad)",  { XX } },
4045     { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4046     { "(bad)",  { XX } },
4047   },
4048
4049   /* PREFIX_VEX_FB */
4050   {
4051     { "(bad)",  { XX } },
4052     { "(bad)",  { XX } },
4053     { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4054     { "(bad)",  { XX } },
4055   },
4056
4057   /* PREFIX_VEX_FC */
4058   {
4059     { "(bad)",  { XX } },
4060     { "(bad)",  { XX } },
4061     { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4062     { "(bad)",  { XX } },
4063   },
4064
4065   /* PREFIX_VEX_FD */
4066   {
4067     { "(bad)",  { XX } },
4068     { "(bad)",  { XX } },
4069     { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4070     { "(bad)",  { XX } },
4071   },
4072
4073   /* PREFIX_VEX_FE */
4074   {
4075     { "(bad)",  { XX } },
4076     { "(bad)",  { XX } },
4077     { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4078     { "(bad)",  { XX } },
4079   },
4080
4081   /* PREFIX_VEX_3800 */
4082   {
4083     { "(bad)",  { XX } },
4084     { "(bad)",  { XX } },
4085     { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4086     { "(bad)",  { XX } },
4087   },
4088
4089   /* PREFIX_VEX_3801 */
4090   {
4091     { "(bad)",  { XX } },
4092     { "(bad)",  { XX } },
4093     { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4094     { "(bad)",  { XX } },
4095   },
4096
4097   /* PREFIX_VEX_3802 */
4098   {
4099     { "(bad)",  { XX } },
4100     { "(bad)",  { XX } },
4101     { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4102     { "(bad)",  { XX } },
4103   },
4104
4105   /* PREFIX_VEX_3803 */
4106   {
4107     { "(bad)",  { XX } },
4108     { "(bad)",  { XX } },
4109     { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4110     { "(bad)",  { XX } },
4111   },
4112
4113   /* PREFIX_VEX_3804 */
4114   {
4115     { "(bad)",  { XX } },
4116     { "(bad)",  { XX } },
4117     { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4118     { "(bad)",  { XX } },
4119   },
4120
4121   /* PREFIX_VEX_3805 */
4122   {
4123     { "(bad)",  { XX } },
4124     { "(bad)",  { XX } },
4125     { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4126     { "(bad)",  { XX } },
4127   },
4128
4129   /* PREFIX_VEX_3806 */
4130   {
4131     { "(bad)",  { XX } },
4132     { "(bad)",  { XX } },
4133     { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4134     { "(bad)",  { XX } },
4135   },
4136
4137   /* PREFIX_VEX_3807 */
4138   {
4139     { "(bad)",  { XX } },
4140     { "(bad)",  { XX } },
4141     { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4142     { "(bad)",  { XX } },
4143   },
4144
4145   /* PREFIX_VEX_3808 */
4146   {
4147     { "(bad)",  { XX } },
4148     { "(bad)",  { XX } },
4149     { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4150     { "(bad)",  { XX } },
4151   },
4152
4153   /* PREFIX_VEX_3809 */
4154   {
4155     { "(bad)",  { XX } },
4156     { "(bad)",  { XX } },
4157     { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4158     { "(bad)",  { XX } },
4159   },
4160
4161   /* PREFIX_VEX_380A */
4162   {
4163     { "(bad)",  { XX } },
4164     { "(bad)",  { XX } },
4165     { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4166     { "(bad)",  { XX } },
4167   },
4168
4169   /* PREFIX_VEX_380B */
4170   {
4171     { "(bad)",  { XX } },
4172     { "(bad)",  { XX } },
4173     { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4174     { "(bad)",  { XX } },
4175   },
4176
4177   /* PREFIX_VEX_380C */
4178   {
4179     { "(bad)",  { XX } },
4180     { "(bad)",  { XX } },
4181     { "vpermilps", { XM, Vex, EXx } },
4182     { "(bad)",  { XX } },
4183   },
4184
4185   /* PREFIX_VEX_380D */
4186   {
4187     { "(bad)",  { XX } },
4188     { "(bad)",  { XX } },
4189     { "vpermilpd", { XM, Vex, EXx } },
4190     { "(bad)",  { XX } },
4191   },
4192
4193   /* PREFIX_VEX_380E */
4194   {
4195     { "(bad)",  { XX } },
4196     { "(bad)",  { XX } },
4197     { "vtestps", { XM, EXx } },
4198     { "(bad)",  { XX } },
4199   },
4200
4201   /* PREFIX_VEX_380F */
4202   {
4203     { "(bad)",  { XX } },
4204     { "(bad)",  { XX } },
4205     { "vtestpd", { XM, EXx } },
4206     { "(bad)",  { XX } },
4207   },
4208
4209   /* PREFIX_VEX_3817 */
4210   {
4211     { "(bad)",  { XX } },
4212     { "(bad)",  { XX } },
4213     { "vptest", { XM, EXx } },
4214     { "(bad)",  { XX } },
4215   },
4216
4217   /* PREFIX_VEX_3818 */
4218   {
4219     { "(bad)",  { XX } },
4220     { "(bad)",  { XX } },
4221     { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4222     { "(bad)",  { XX } },
4223   },
4224
4225   /* PREFIX_VEX_3819 */
4226   {
4227     { "(bad)",  { XX } },
4228     { "(bad)",  { XX } },
4229     { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4230     { "(bad)",  { XX } },
4231   },
4232
4233   /* PREFIX_VEX_381A */
4234   {
4235     { "(bad)",  { XX } },
4236     { "(bad)",  { XX } },
4237     { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4238     { "(bad)",  { XX } },
4239   },
4240
4241   /* PREFIX_VEX_381C */
4242   {
4243     { "(bad)",  { XX } },
4244     { "(bad)",  { XX } },
4245     { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4246     { "(bad)",  { XX } },
4247   },
4248
4249   /* PREFIX_VEX_381D */
4250   {
4251     { "(bad)",  { XX } },
4252     { "(bad)",  { XX } },
4253     { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4254     { "(bad)",  { XX } },
4255   },
4256
4257   /* PREFIX_VEX_381E */
4258   {
4259     { "(bad)",  { XX } },
4260     { "(bad)",  { XX } },
4261     { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4262     { "(bad)",  { XX } },
4263   },
4264
4265   /* PREFIX_VEX_3820 */
4266   {
4267     { "(bad)",  { XX } },
4268     { "(bad)",  { XX } },
4269     { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4270     { "(bad)",  { XX } },
4271   },
4272
4273   /* PREFIX_VEX_3821 */
4274   {
4275     { "(bad)",  { XX } },
4276     { "(bad)",  { XX } },
4277     { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4278     { "(bad)",  { XX } },
4279   },
4280
4281   /* PREFIX_VEX_3822 */
4282   {
4283     { "(bad)",  { XX } },
4284     { "(bad)",  { XX } },
4285     { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4286     { "(bad)",  { XX } },
4287   },
4288
4289   /* PREFIX_VEX_3823 */
4290   {
4291     { "(bad)",  { XX } },
4292     { "(bad)",  { XX } },
4293     { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4294     { "(bad)",  { XX } },
4295   },
4296
4297   /* PREFIX_VEX_3824 */
4298   {
4299     { "(bad)",  { XX } },
4300     { "(bad)",  { XX } },
4301     { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4302     { "(bad)",  { XX } },
4303   },
4304
4305   /* PREFIX_VEX_3825 */
4306   {
4307     { "(bad)",  { XX } },
4308     { "(bad)",  { XX } },
4309     { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4310     { "(bad)",  { XX } },
4311   },
4312
4313   /* PREFIX_VEX_3828 */
4314   {
4315     { "(bad)",  { XX } },
4316     { "(bad)",  { XX } },
4317     { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4318     { "(bad)",  { XX } },
4319   },
4320
4321   /* PREFIX_VEX_3829 */
4322   {
4323     { "(bad)",  { XX } },
4324     { "(bad)",  { XX } },
4325     { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4326     { "(bad)",  { XX } },
4327   },
4328
4329   /* PREFIX_VEX_382A */
4330   {
4331     { "(bad)",  { XX } },
4332     { "(bad)",  { XX } },
4333     { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4334     { "(bad)",  { XX } },
4335   },
4336
4337   /* PREFIX_VEX_382B */
4338   {
4339     { "(bad)",  { XX } },
4340     { "(bad)",  { XX } },
4341     { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4342     { "(bad)",  { XX } },
4343   },
4344
4345   /* PREFIX_VEX_382C */
4346   {
4347     { "(bad)",  { XX } },
4348     { "(bad)",  { XX } },
4349      { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4350     { "(bad)",  { XX } },
4351   },
4352
4353   /* PREFIX_VEX_382D */
4354   {
4355     { "(bad)",  { XX } },
4356     { "(bad)",  { XX } },
4357      { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4358     { "(bad)",  { XX } },
4359   },
4360
4361   /* PREFIX_VEX_382E */
4362   {
4363     { "(bad)",  { XX } },
4364     { "(bad)",  { XX } },
4365      { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4366     { "(bad)",  { XX } },
4367   },
4368
4369   /* PREFIX_VEX_382F */
4370   {
4371     { "(bad)",  { XX } },
4372     { "(bad)",  { XX } },
4373      { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4374     { "(bad)",  { XX } },
4375   },
4376
4377   /* PREFIX_VEX_3830 */
4378   {
4379     { "(bad)",  { XX } },
4380     { "(bad)",  { XX } },
4381     { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4382     { "(bad)",  { XX } },
4383   },
4384
4385   /* PREFIX_VEX_3831 */
4386   {
4387     { "(bad)",  { XX } },
4388     { "(bad)",  { XX } },
4389     { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4390     { "(bad)",  { XX } },
4391   },
4392
4393   /* PREFIX_VEX_3832 */
4394   {
4395     { "(bad)",  { XX } },
4396     { "(bad)",  { XX } },
4397     { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4398     { "(bad)",  { XX } },
4399   },
4400
4401   /* PREFIX_VEX_3833 */
4402   {
4403     { "(bad)",  { XX } },
4404     { "(bad)",  { XX } },
4405     { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4406     { "(bad)",  { XX } },
4407   },
4408
4409   /* PREFIX_VEX_3834 */
4410   {
4411     { "(bad)",  { XX } },
4412     { "(bad)",  { XX } },
4413     { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4414     { "(bad)",  { XX } },
4415   },
4416
4417   /* PREFIX_VEX_3835 */
4418   {
4419     { "(bad)",  { XX } },
4420     { "(bad)",  { XX } },
4421     { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4422     { "(bad)",  { XX } },
4423   },
4424
4425   /* PREFIX_VEX_3837 */
4426   {
4427     { "(bad)",  { XX } },
4428     { "(bad)",  { XX } },
4429     { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4430     { "(bad)",  { XX } },
4431   },
4432
4433   /* PREFIX_VEX_3838 */
4434   {
4435     { "(bad)",  { XX } },
4436     { "(bad)",  { XX } },
4437     { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4438     { "(bad)",  { XX } },
4439   },
4440
4441   /* PREFIX_VEX_3839 */
4442   {
4443     { "(bad)",  { XX } },
4444     { "(bad)",  { XX } },
4445     { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4446     { "(bad)",  { XX } },
4447   },
4448
4449   /* PREFIX_VEX_383A */
4450   {
4451     { "(bad)",  { XX } },
4452     { "(bad)",  { XX } },
4453     { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4454     { "(bad)",  { XX } },
4455   },
4456
4457   /* PREFIX_VEX_383B */
4458   {
4459     { "(bad)",  { XX } },
4460     { "(bad)",  { XX } },
4461     { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4462     { "(bad)",  { XX } },
4463   },
4464
4465   /* PREFIX_VEX_383C */
4466   {
4467     { "(bad)",  { XX } },
4468     { "(bad)",  { XX } },
4469     { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4470     { "(bad)",  { XX } },
4471   },
4472
4473   /* PREFIX_VEX_383D */
4474   {
4475     { "(bad)",  { XX } },
4476     { "(bad)",  { XX } },
4477     { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4478     { "(bad)",  { XX } },
4479   },
4480
4481   /* PREFIX_VEX_383E */
4482   {
4483     { "(bad)",  { XX } },
4484     { "(bad)",  { XX } },
4485     { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4486     { "(bad)",  { XX } },
4487   },
4488
4489   /* PREFIX_VEX_383F */
4490   {
4491     { "(bad)",  { XX } },
4492     { "(bad)",  { XX } },
4493     { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4494     { "(bad)",  { XX } },
4495   },
4496
4497   /* PREFIX_VEX_3840 */
4498   {
4499     { "(bad)",  { XX } },
4500     { "(bad)",  { XX } },
4501     { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4502     { "(bad)",  { XX } },
4503   },
4504
4505   /* PREFIX_VEX_3841 */
4506   {
4507     { "(bad)",  { XX } },
4508     { "(bad)",  { XX } },
4509     { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4510     { "(bad)",  { XX } },
4511   },
4512
4513   /* PREFIX_VEX_3A04 */
4514   {
4515     { "(bad)",  { XX } },
4516     { "(bad)",  { XX } },
4517     { "vpermilps", { XM, EXx, Ib } },
4518     { "(bad)",  { XX } },
4519   },
4520
4521   /* PREFIX_VEX_3A05 */
4522   {
4523     { "(bad)",  { XX } },
4524     { "(bad)",  { XX } },
4525     { "vpermilpd", { XM, EXx, Ib } },
4526     { "(bad)",  { XX } },
4527   },
4528
4529   /* PREFIX_VEX_3A06 */
4530   {
4531     { "(bad)",  { XX } },
4532     { "(bad)",  { XX } },
4533     { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4534     { "(bad)",  { XX } },
4535   },
4536
4537   /* PREFIX_VEX_3A08 */
4538   {
4539     { "(bad)",  { XX } },
4540     { "(bad)",  { XX } },
4541     { "vroundps", { XM, EXx, Ib } },
4542     { "(bad)",  { XX } },
4543   },
4544
4545   /* PREFIX_VEX_3A09 */
4546   {
4547     { "(bad)",  { XX } },
4548     { "(bad)",  { XX } },
4549     { "vroundpd", { XM, EXx, Ib } },
4550     { "(bad)",  { XX } },
4551   },
4552
4553   /* PREFIX_VEX_3A0A */
4554   {
4555     { "(bad)",  { XX } },
4556     { "(bad)",  { XX } },
4557     { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4558     { "(bad)",  { XX } },
4559   },
4560
4561   /* PREFIX_VEX_3A0B */
4562   {
4563     { "(bad)",  { XX } },
4564     { "(bad)",  { XX } },
4565     { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4566     { "(bad)",  { XX } },
4567   },
4568
4569   /* PREFIX_VEX_3A0C */
4570   {
4571     { "(bad)",  { XX } },
4572     { "(bad)",  { XX } },
4573     { "vblendps", { XM, Vex, EXx, Ib } },
4574     { "(bad)",  { XX } },
4575   },
4576
4577   /* PREFIX_VEX_3A0D */
4578   {
4579     { "(bad)",  { XX } },
4580     { "(bad)",  { XX } },
4581     { "vblendpd", { XM, Vex, EXx, Ib } },
4582     { "(bad)",  { XX } },
4583   },
4584
4585   /* PREFIX_VEX_3A0E */
4586   {
4587     { "(bad)",  { XX } },
4588     { "(bad)",  { XX } },
4589     { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
4590     { "(bad)",  { XX } },
4591   },
4592
4593   /* PREFIX_VEX_3A0F */
4594   {
4595     { "(bad)",  { XX } },
4596     { "(bad)",  { XX } },
4597     { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
4598     { "(bad)",  { XX } },
4599   },
4600
4601   /* PREFIX_VEX_3A14 */
4602   {
4603     { "(bad)",  { XX } },
4604     { "(bad)",  { XX } },
4605     { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
4606     { "(bad)",  { XX } },
4607   },
4608
4609   /* PREFIX_VEX_3A15 */
4610   {
4611     { "(bad)",  { XX } },
4612     { "(bad)",  { XX } },
4613     { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
4614     { "(bad)",  { XX } },
4615   },
4616
4617   /* PREFIX_VEX_3A16 */
4618   {
4619     { "(bad)",  { XX } },
4620     { "(bad)",  { XX } },
4621     { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
4622     { "(bad)",  { XX } },
4623   },
4624
4625   /* PREFIX_VEX_3A17 */
4626   {
4627     { "(bad)",  { XX } },
4628     { "(bad)",  { XX } },
4629     { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
4630     { "(bad)",  { XX } },
4631   },
4632
4633   /* PREFIX_VEX_3A18 */
4634   {
4635     { "(bad)",  { XX } },
4636     { "(bad)",  { XX } },
4637     { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
4638     { "(bad)",  { XX } },
4639   },
4640
4641   /* PREFIX_VEX_3A19 */
4642   {
4643     { "(bad)",  { XX } },
4644     { "(bad)",  { XX } },
4645     { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
4646     { "(bad)",  { XX } },
4647   },
4648
4649   /* PREFIX_VEX_3A20 */
4650   {
4651     { "(bad)",  { XX } },
4652     { "(bad)",  { XX } },
4653     { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
4654     { "(bad)",  { XX } },
4655   },
4656
4657   /* PREFIX_VEX_3A21 */
4658   {
4659     { "(bad)",  { XX } },
4660     { "(bad)",  { XX } },
4661     { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
4662     { "(bad)",  { XX } },
4663   },
4664
4665   /* PREFIX_VEX_3A22 */
4666   {
4667     { "(bad)",  { XX } },
4668     { "(bad)",  { XX } },
4669     { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
4670     { "(bad)",  { XX } },
4671   },
4672
4673   /* PREFIX_VEX_3A40 */
4674   {
4675     { "(bad)",  { XX } },
4676     { "(bad)",  { XX } },
4677     { "vdpps",  { XM, Vex, EXx, Ib } },
4678     { "(bad)",  { XX } },
4679   },
4680
4681   /* PREFIX_VEX_3A41 */
4682   {
4683     { "(bad)",  { XX } },
4684     { "(bad)",  { XX } },
4685     { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
4686     { "(bad)",  { XX } },
4687   },
4688
4689   /* PREFIX_VEX_3A42 */
4690   {
4691     { "(bad)",  { XX } },
4692     { "(bad)",  { XX } },
4693     { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
4694     { "(bad)",  { XX } },
4695   },
4696
4697   /* PREFIX_VEX_3A48 */
4698   {
4699     { "(bad)",  { XX } },
4700     { "(bad)",  { XX } },
4701     { "vpermil2ps", { XMVexW, Vex, EXVexW, EXVexW, VPERMIL2 } },
4702     { "(bad)",  { XX } },
4703   },
4704
4705   /* PREFIX_VEX_3A49 */
4706   {
4707     { "(bad)",  { XX } },
4708     { "(bad)",  { XX } },
4709     { "vpermil2pd", { XMVexW, Vex, EXVexW, EXVexW, VPERMIL2 } },
4710     { "(bad)",  { XX } },
4711   },
4712
4713   /* PREFIX_VEX_3A4A */
4714   {
4715     { "(bad)",  { XX } },
4716     { "(bad)",  { XX } },
4717     { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
4718     { "(bad)",  { XX } },
4719   },
4720
4721   /* PREFIX_VEX_3A4B */
4722   {
4723     { "(bad)",  { XX } },
4724     { "(bad)",  { XX } },
4725     { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
4726     { "(bad)",  { XX } },
4727   },
4728
4729   /* PREFIX_VEX_3A4C */
4730   {
4731     { "(bad)",  { XX } },
4732     { "(bad)",  { XX } },
4733     { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
4734     { "(bad)",  { XX } },
4735   },
4736
4737   /* PREFIX_VEX_3A5C */
4738   {
4739     { "(bad)",  { XX } },
4740     { "(bad)",  { XX } },
4741     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
4742     { "(bad)",  { XX } },
4743   },
4744
4745   /* PREFIX_VEX_3A5D */
4746   {
4747     { "(bad)",  { XX } },
4748     { "(bad)",  { XX } },
4749     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
4750     { "(bad)",  { XX } },
4751   },
4752
4753   /* PREFIX_VEX_3A5E */
4754   {
4755     { "(bad)",  { XX } },
4756     { "(bad)",  { XX } },
4757     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
4758     { "(bad)",  { XX } },
4759   },
4760
4761   /* PREFIX_VEX_3A5F */
4762   {
4763     { "(bad)",  { XX } },
4764     { "(bad)",  { XX } },
4765     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
4766     { "(bad)",  { XX } },
4767   },
4768
4769   /* PREFIX_VEX_3A60 */
4770   {
4771     { "(bad)",  { XX } },
4772     { "(bad)",  { XX } },
4773     { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
4774     { "(bad)",  { XX } },
4775   },
4776
4777   /* PREFIX_VEX_3A61 */
4778   {
4779     { "(bad)",  { XX } },
4780     { "(bad)",  { XX } },
4781     { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
4782     { "(bad)",  { XX } },
4783   },
4784
4785   /* PREFIX_VEX_3A62 */
4786   {
4787     { "(bad)",  { XX } },
4788     { "(bad)",  { XX } },
4789     { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
4790     { "(bad)",  { XX } },
4791   },
4792
4793   /* PREFIX_VEX_3A63 */
4794   {
4795     { "(bad)",  { XX } },
4796     { "(bad)",  { XX } },
4797     { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
4798     { "(bad)",  { XX } },
4799   },
4800
4801   /* PREFIX_VEX_3A68 */
4802   {
4803     { "(bad)",  { XX } },
4804     { "(bad)",  { XX } },
4805     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
4806     { "(bad)",  { XX } },
4807   },
4808
4809   /* PREFIX_VEX_3A69 */
4810   {
4811     { "(bad)",  { XX } },
4812     { "(bad)",  { XX } },
4813     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
4814     { "(bad)",  { XX } },
4815   },
4816
4817   /* PREFIX_VEX_3A6A */
4818   {
4819     { "(bad)",  { XX } },
4820     { "(bad)",  { XX } },
4821     { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
4822     { "(bad)",  { XX } },
4823   },
4824
4825   /* PREFIX_VEX_3A6B */
4826   {
4827     { "(bad)",  { XX } },
4828     { "(bad)",  { XX } },
4829     { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
4830     { "(bad)",  { XX } },
4831   },
4832
4833   /* PREFIX_VEX_3A6C */
4834   {
4835     { "(bad)",  { XX } },
4836     { "(bad)",  { XX } },
4837     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
4838     { "(bad)",  { XX } },
4839   },
4840
4841   /* PREFIX_VEX_3A6D */
4842   {
4843     { "(bad)",  { XX } },
4844     { "(bad)",  { XX } },
4845     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
4846     { "(bad)",  { XX } },
4847   },
4848
4849   /* PREFIX_VEX_3A6E */
4850   {
4851     { "(bad)",  { XX } },
4852     { "(bad)",  { XX } },
4853     { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
4854     { "(bad)",  { XX } },
4855   },
4856
4857   /* PREFIX_VEX_3A6F */
4858   {
4859     { "(bad)",  { XX } },
4860     { "(bad)",  { XX } },
4861     { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
4862     { "(bad)",  { XX } },
4863   },
4864
4865   /* PREFIX_VEX_3A78 */
4866   {
4867     { "(bad)",  { XX } },
4868     { "(bad)",  { XX } },
4869     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
4870     { "(bad)",  { XX } },
4871   },
4872
4873   /* PREFIX_VEX_3A79 */
4874   {
4875     { "(bad)",  { XX } },
4876     { "(bad)",  { XX } },
4877     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
4878     { "(bad)",  { XX } },
4879   },
4880
4881   /* PREFIX_VEX_3A7A */
4882   {
4883     { "(bad)",  { XX } },
4884     { "(bad)",  { XX } },
4885     { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
4886     { "(bad)",  { XX } },
4887   },
4888
4889   /* PREFIX_VEX_3A7B */
4890   {
4891     { "(bad)",  { XX } },
4892     { "(bad)",  { XX } },
4893     { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
4894     { "(bad)",  { XX } },
4895   },
4896
4897   /* PREFIX_VEX_3A7C */
4898   {
4899     { "(bad)",  { XX } },
4900     { "(bad)",  { XX } },
4901     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
4902     { "(bad)",  { XX } },
4903   },
4904
4905   /* PREFIX_VEX_3A7D */
4906   {
4907     { "(bad)",  { XX } },
4908     { "(bad)",  { XX } },
4909     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
4910     { "(bad)",  { XX } },
4911   },
4912
4913   /* PREFIX_VEX_3A7E */
4914   {
4915     { "(bad)",  { XX } },
4916     { "(bad)",  { XX } },
4917     { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
4918     { "(bad)",  { XX } },
4919   },
4920
4921   /* PREFIX_VEX_3A7F */
4922   {
4923     { "(bad)",  { XX } },
4924     { "(bad)",  { XX } },
4925     { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
4926     { "(bad)",  { XX } },
4927   },
4928 };
4929
4930 static const struct dis386 x86_64_table[][2] = {
4931   /* X86_64_06 */
4932   {
4933     { "push{T|}", { es } },
4934     { "(bad)", { XX } },
4935   },
4936
4937   /* X86_64_07 */
4938   {
4939     { "pop{T|}", { es } },
4940     { "(bad)", { XX } },
4941   },
4942
4943   /* X86_64_0D */
4944   {
4945     { "push{T|}", { cs } },
4946     { "(bad)", { XX } },
4947   },
4948
4949   /* X86_64_16 */
4950   {
4951     { "push{T|}", { ss } },
4952     { "(bad)", { XX } },
4953   },
4954
4955   /* X86_64_17 */
4956   {
4957     { "pop{T|}", { ss } },
4958     { "(bad)", { XX } },
4959   },
4960
4961   /* X86_64_1E */
4962   {
4963     { "push{T|}", { ds } },
4964     { "(bad)", { XX } },
4965   },
4966
4967   /* X86_64_1F */
4968   {
4969     { "pop{T|}", { ds } },
4970     { "(bad)", { XX } },
4971   },
4972
4973   /* X86_64_27 */
4974   {
4975     { "daa", { XX } },
4976     { "(bad)", { XX } },
4977   },
4978
4979   /* X86_64_2F */
4980   {
4981     { "das", { XX } },
4982     { "(bad)", { XX } },
4983   },
4984
4985   /* X86_64_37 */
4986   {
4987     { "aaa", { XX } },
4988     { "(bad)", { XX } },
4989   },
4990
4991   /* X86_64_3F */
4992   {
4993     { "aas", { XX } },
4994     { "(bad)", { XX } },
4995   },
4996
4997   /* X86_64_60 */
4998   {
4999     { "pusha{P|}", { XX } },
5000     { "(bad)", { XX } },
5001   },
5002
5003   /* X86_64_61 */
5004   {
5005     { "popa{P|}", { XX } },
5006     { "(bad)", { XX } },
5007   },
5008
5009   /* X86_64_62 */
5010   {
5011     { MOD_TABLE (MOD_62_32BIT) },
5012     { "(bad)", { XX } },
5013   },
5014
5015   /* X86_64_63 */
5016   {
5017     { "arpl", { Ew, Gw } },
5018     { "movs{lq|xd}", { Gv, Ed } },
5019   },
5020
5021   /* X86_64_6D */
5022   {
5023     { "ins{R|}", { Yzr, indirDX } },
5024     { "ins{G|}", { Yzr, indirDX } },
5025   },
5026
5027   /* X86_64_6F */
5028   {
5029     { "outs{R|}", { indirDXr, Xz } },
5030     { "outs{G|}", { indirDXr, Xz } },
5031   },
5032
5033   /* X86_64_9A */
5034   {
5035     { "Jcall{T|}", { Ap } },
5036     { "(bad)", { XX } },
5037   },
5038
5039   /* X86_64_C4 */
5040   {
5041     { MOD_TABLE (MOD_C4_32BIT) },
5042     { VEX_C4_TABLE (VEX_0F) },
5043   },
5044
5045   /* X86_64_C5 */
5046   {
5047     { MOD_TABLE (MOD_C5_32BIT) },
5048     { VEX_C5_TABLE (VEX_0F) },
5049   },
5050
5051   /* X86_64_CE */
5052   {
5053     { "into", { XX } },
5054     { "(bad)", { XX } },
5055   },
5056
5057   /* X86_64_D4 */
5058   {
5059     { "aam", { sIb } },
5060     { "(bad)", { XX } },
5061   },
5062
5063   /* X86_64_D5 */
5064   {
5065     { "aad", { sIb } },
5066     { "(bad)", { XX } },
5067   },
5068
5069   /* X86_64_EA */
5070   {
5071     { "Jjmp{T|}", { Ap } },
5072     { "(bad)", { XX } },
5073   },
5074
5075   /* X86_64_0F01_REG_0 */
5076   {
5077     { "sgdt{Q|IQ}", { M } },
5078     { "sgdt", { M } },
5079   },
5080
5081   /* X86_64_0F01_REG_1 */
5082   {
5083     { "sidt{Q|IQ}", { M } },
5084     { "sidt", { M } },
5085   },
5086
5087   /* X86_64_0F01_REG_2 */
5088   {
5089     { "lgdt{Q|Q}", { M } },
5090     { "lgdt", { M } },
5091   },
5092
5093   /* X86_64_0F01_REG_3 */
5094   {
5095     { "lidt{Q|Q}", { M } },
5096     { "lidt", { M } },
5097   },
5098 };
5099
5100 static const struct dis386 three_byte_table[][256] = {
5101   /* THREE_BYTE_0F24 */
5102   {
5103     /* 00 */
5104     { "fmaddps",        { { OP_DREX4, q_mode } } },
5105     { "fmaddpd",        { { OP_DREX4, q_mode } } },
5106     { "fmaddss",        { { OP_DREX4, w_mode } } },
5107     { "fmaddsd",        { { OP_DREX4, d_mode } } },
5108     { "fmaddps",        { { OP_DREX4, DREX_OC1 + q_mode } } },
5109     { "fmaddpd",        { { OP_DREX4, DREX_OC1 + q_mode } } },
5110     { "fmaddss",        { { OP_DREX4, DREX_OC1 + w_mode } } },
5111     { "fmaddsd",        { { OP_DREX4, DREX_OC1 + d_mode } } },
5112     /* 08 */
5113     { "fmsubps",        { { OP_DREX4, q_mode } } },
5114     { "fmsubpd",        { { OP_DREX4, q_mode } } },
5115     { "fmsubss",        { { OP_DREX4, w_mode } } },
5116     { "fmsubsd",        { { OP_DREX4, d_mode } } },
5117     { "fmsubps",        { { OP_DREX4, DREX_OC1 + q_mode } } },
5118     { "fmsubpd",        { { OP_DREX4, DREX_OC1 + q_mode } } },
5119     { "fmsubss",        { { OP_DREX4, DREX_OC1 + w_mode } } },
5120     { "fmsubsd",        { { OP_DREX4, DREX_OC1 + d_mode } } },
5121     /* 10 */
5122     { "fnmaddps",       { { OP_DREX4, q_mode } } },
5123     { "fnmaddpd",       { { OP_DREX4, q_mode } } },
5124     { "fnmaddss",       { { OP_DREX4, w_mode } } },
5125     { "fnmaddsd",       { { OP_DREX4, d_mode } } },
5126     { "fnmaddps",       { { OP_DREX4, DREX_OC1 + q_mode } } },
5127     { "fnmaddpd",       { { OP_DREX4, DREX_OC1 + q_mode } } },
5128     { "fnmaddss",       { { OP_DREX4, DREX_OC1 + w_mode } } },
5129     { "fnmaddsd",       { { OP_DREX4, DREX_OC1 + d_mode } } },
5130     /* 18 */
5131     { "fnmsubps",       { { OP_DREX4, q_mode } } },
5132     { "fnmsubpd",       { { OP_DREX4, q_mode } } },
5133     { "fnmsubss",       { { OP_DREX4, w_mode } } },
5134     { "fnmsubsd",       { { OP_DREX4, d_mode } } },
5135     { "fnmsubps",       { { OP_DREX4, DREX_OC1 + q_mode } } },
5136     { "fnmsubpd",       { { OP_DREX4, DREX_OC1 + q_mode } } },
5137     { "fnmsubss",       { { OP_DREX4, DREX_OC1 + w_mode } } },
5138     { "fnmsubsd",       { { OP_DREX4, DREX_OC1 + d_mode } } },
5139     /* 20 */
5140     { "permps",         { { OP_DREX4, q_mode } } },
5141     { "permpd",         { { OP_DREX4, q_mode } } },
5142     { "pcmov",          { { OP_DREX4, q_mode } } },
5143     { "pperm",          { { OP_DREX4, q_mode } } },
5144     { "permps",         { { OP_DREX4, DREX_OC1 + q_mode } } },
5145     { "permpd",         { { OP_DREX4, DREX_OC1 + q_mode } } },
5146     { "pcmov",          { { OP_DREX4, DREX_OC1 + w_mode } } },
5147     { "pperm",          { { OP_DREX4, DREX_OC1 + d_mode } } },
5148     /* 28 */
5149     { "(bad)",          { XX } },
5150     { "(bad)",          { XX } },
5151     { "(bad)",          { XX } },
5152     { "(bad)",          { XX } },
5153     { "(bad)",          { XX } },
5154     { "(bad)",          { XX } },
5155     { "(bad)",          { XX } },
5156     { "(bad)",          { XX } },
5157     /* 30 */
5158     { "(bad)",          { XX } },
5159     { "(bad)",          { XX } },
5160     { "(bad)",          { XX } },
5161     { "(bad)",          { XX } },
5162     { "(bad)",          { XX } },
5163     { "(bad)",          { XX } },
5164     { "(bad)",          { XX } },
5165     { "(bad)",          { XX } },
5166     /* 38 */
5167     { "(bad)",          { XX } },
5168     { "(bad)",          { XX } },
5169     { "(bad)",          { XX } },
5170     { "(bad)",          { XX } },
5171     { "(bad)",          { XX } },
5172     { "(bad)",          { XX } },
5173     { "(bad)",          { XX } },
5174     { "(bad)",          { XX } },
5175     /* 40 */
5176     { "protb",          { { OP_DREX3, q_mode } } },
5177     { "protw",          { { OP_DREX3, q_mode } } },
5178     { "protd",          { { OP_DREX3, q_mode } } },
5179     { "protq",          { { OP_DREX3, q_mode } } },
5180     { "pshlb",          { { OP_DREX3, q_mode } } },
5181     { "pshlw",          { { OP_DREX3, q_mode } } },
5182     { "pshld",          { { OP_DREX3, q_mode } } },
5183     { "pshlq",          { { OP_DREX3, q_mode } } },
5184     /* 48 */
5185     { "pshab",          { { OP_DREX3, q_mode } } },
5186     { "pshaw",          { { OP_DREX3, q_mode } } },
5187     { "pshad",          { { OP_DREX3, q_mode } } },
5188     { "pshaq",          { { OP_DREX3, q_mode } } },
5189     { "(bad)",          { XX } },
5190     { "(bad)",          { XX } },
5191     { "(bad)",          { XX } },
5192     { "(bad)",          { XX } },
5193     /* 50 */
5194     { "(bad)",          { XX } },
5195     { "(bad)",          { XX } },
5196     { "(bad)",          { XX } },
5197     { "(bad)",          { XX } },
5198     { "(bad)",          { XX } },
5199     { "(bad)",          { XX } },
5200     { "(bad)",          { XX } },
5201     { "(bad)",          { XX } },
5202     /* 58 */
5203     { "(bad)",          { XX } },
5204     { "(bad)",          { XX } },
5205     { "(bad)",          { XX } },
5206     { "(bad)",          { XX } },
5207     { "(bad)",          { XX } },
5208     { "(bad)",          { XX } },
5209     { "(bad)",          { XX } },
5210     { "(bad)",          { XX } },
5211     /* 60 */
5212     { "(bad)",          { XX } },
5213     { "(bad)",          { XX } },
5214     { "(bad)",          { XX } },
5215     { "(bad)",          { XX } },
5216     { "(bad)",          { XX } },
5217     { "(bad)",          { XX } },
5218     { "(bad)",          { XX } },
5219     { "(bad)",          { XX } },
5220     /* 68 */
5221     { "(bad)",          { XX } },
5222     { "(bad)",          { XX } },
5223     { "(bad)",          { XX } },
5224     { "(bad)",          { XX } },
5225     { "(bad)",          { XX } },
5226     { "(bad)",          { XX } },
5227     { "(bad)",          { XX } },
5228     { "(bad)",          { XX } },
5229     /* 70 */
5230     { "(bad)",          { XX } },
5231     { "(bad)",          { XX } },
5232     { "(bad)",          { XX } },
5233     { "(bad)",          { XX } },
5234     { "(bad)",          { XX } },
5235     { "(bad)",          { XX } },
5236     { "(bad)",          { XX } },
5237     { "(bad)",          { XX } },
5238     /* 78 */
5239     { "(bad)",          { XX } },
5240     { "(bad)",          { XX } },
5241     { "(bad)",          { XX } },
5242     { "(bad)",          { XX } },
5243     { "(bad)",          { XX } },
5244     { "(bad)",          { XX } },
5245     { "(bad)",          { XX } },
5246     { "(bad)",          { XX } },
5247     /* 80 */
5248     { "(bad)",          { XX } },
5249     { "(bad)",          { XX } },
5250     { "(bad)",          { XX } },
5251     { "(bad)",          { XX } },
5252     { "(bad)",          { XX } },
5253     { "pmacssww",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5254     { "pmacsswd",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5255     { "pmacssdql",      { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5256     /* 88 */
5257     { "(bad)",          { XX } },
5258     { "(bad)",          { XX } },
5259     { "(bad)",          { XX } },
5260     { "(bad)",          { XX } },
5261     { "(bad)",          { XX } },
5262     { "(bad)",          { XX } },
5263     { "pmacssdd",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5264     { "pmacssdqh",      { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5265     /* 90 */
5266     { "(bad)",          { XX } },
5267     { "(bad)",          { XX } },
5268     { "(bad)",          { XX } },
5269     { "(bad)",          { XX } },
5270     { "(bad)",          { XX } },
5271     { "pmacsww",        { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5272     { "pmacswd",        { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5273     { "pmacsdql",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5274     /* 98 */
5275     { "(bad)",          { XX } },
5276     { "(bad)",          { XX } },
5277     { "(bad)",          { XX } },
5278     { "(bad)",          { XX } },
5279     { "(bad)",          { XX } },
5280     { "(bad)",          { XX } },
5281     { "pmacsdd",        { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5282     { "pmacsdqh",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5283     /* a0 */
5284     { "(bad)",          { XX } },
5285     { "(bad)",          { XX } },
5286     { "(bad)",          { XX } },
5287     { "(bad)",          { XX } },
5288     { "(bad)",          { XX } },
5289     { "(bad)",          { XX } },
5290     { "pmadcsswd",      { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5291     { "(bad)",          { XX } },
5292     /* a8 */
5293     { "(bad)",          { XX } },
5294     { "(bad)",          { XX } },
5295     { "(bad)",          { XX } },
5296     { "(bad)",          { XX } },
5297     { "(bad)",          { XX } },
5298     { "(bad)",          { XX } },
5299     { "(bad)",          { XX } },
5300     { "(bad)",          { XX } },
5301     /* b0 */
5302     { "(bad)",          { XX } },
5303     { "(bad)",          { XX } },
5304     { "(bad)",          { XX } },
5305     { "(bad)",          { XX } },
5306     { "(bad)",          { XX } },
5307     { "(bad)",          { XX } },
5308     { "pmadcswd",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5309     { "(bad)",          { XX } },
5310     /* b8 */
5311     { "(bad)",          { XX } },
5312     { "(bad)",          { XX } },
5313     { "(bad)",          { XX } },
5314     { "(bad)",          { XX } },
5315     { "(bad)",          { XX } },
5316     { "(bad)",          { XX } },
5317     { "(bad)",          { XX } },
5318     { "(bad)",          { XX } },
5319     /* c0 */
5320     { "(bad)",          { XX } },
5321     { "(bad)",          { XX } },
5322     { "(bad)",          { XX } },
5323     { "(bad)",          { XX } },
5324     { "(bad)",          { XX } },
5325     { "(bad)",          { XX } },
5326     { "(bad)",          { XX } },
5327     { "(bad)",          { XX } },
5328     /* c8 */
5329     { "(bad)",          { XX } },
5330     { "(bad)",          { XX } },
5331     { "(bad)",          { XX } },
5332     { "(bad)",          { XX } },
5333     { "(bad)",          { XX } },
5334     { "(bad)",          { XX } },
5335     { "(bad)",          { XX } },
5336     { "(bad)",          { XX } },
5337     /* d0 */
5338     { "(bad)",          { XX } },
5339     { "(bad)",          { XX } },
5340     { "(bad)",          { XX } },
5341     { "(bad)",          { XX } },
5342     { "(bad)",          { XX } },
5343     { "(bad)",          { XX } },
5344     { "(bad)",          { XX } },
5345     { "(bad)",          { XX } },
5346     /* d8 */
5347     { "(bad)",          { XX } },
5348     { "(bad)",          { XX } },
5349     { "(bad)",          { XX } },
5350     { "(bad)",          { XX } },
5351     { "(bad)",          { XX } },
5352     { "(bad)",          { XX } },
5353     { "(bad)",          { XX } },
5354     { "(bad)",          { XX } },
5355     /* e0 */
5356     { "(bad)",          { XX } },
5357     { "(bad)",          { XX } },
5358     { "(bad)",          { XX } },
5359     { "(bad)",          { XX } },
5360     { "(bad)",          { XX } },
5361     { "(bad)",          { XX } },
5362     { "(bad)",          { XX } },
5363     { "(bad)",          { XX } },
5364     /* e8 */
5365     { "(bad)",          { XX } },
5366     { "(bad)",          { XX } },
5367     { "(bad)",          { XX } },
5368     { "(bad)",          { XX } },
5369     { "(bad)",          { XX } },
5370     { "(bad)",          { XX } },
5371     { "(bad)",          { XX } },
5372     { "(bad)",          { XX } },
5373     /* f0 */
5374     { "(bad)",          { XX } },
5375     { "(bad)",          { XX } },
5376     { "(bad)",          { XX } },
5377     { "(bad)",          { XX } },
5378     { "(bad)",          { XX } },
5379     { "(bad)",          { XX } },
5380     { "(bad)",          { XX } },
5381     { "(bad)",          { XX } },
5382     /* f8 */
5383     { "(bad)",          { XX } },
5384     { "(bad)",          { XX } },
5385     { "(bad)",          { XX } },
5386     { "(bad)",          { XX } },
5387     { "(bad)",          { XX } },
5388     { "(bad)",          { XX } },
5389     { "(bad)",          { XX } },
5390     { "(bad)",          { XX } },
5391   },
5392   /* THREE_BYTE_0F25 */
5393   {
5394     /* 00 */
5395     { "(bad)",          { XX } },
5396     { "(bad)",          { XX } },
5397     { "(bad)",          { XX } },
5398     { "(bad)",          { XX } },
5399     { "(bad)",          { XX } },
5400     { "(bad)",          { XX } },
5401     { "(bad)",          { XX } },
5402     { "(bad)",          { XX } },
5403     /* 08 */
5404     { "(bad)",          { XX } },
5405     { "(bad)",          { XX } },
5406     { "(bad)",          { XX } },
5407     { "(bad)",          { XX } },
5408     { "(bad)",          { XX } },
5409     { "(bad)",          { XX } },
5410     { "(bad)",          { XX } },
5411     { "(bad)",          { XX } },
5412     /* 10 */
5413     { "(bad)",          { XX } },
5414     { "(bad)",          { XX } },
5415     { "(bad)",          { XX } },
5416     { "(bad)",          { XX } },
5417     { "(bad)",          { XX } },
5418     { "(bad)",          { XX } },
5419     { "(bad)",          { XX } },
5420     { "(bad)",          { XX } },
5421     /* 18 */
5422     { "(bad)",          { XX } },
5423     { "(bad)",          { XX } },
5424     { "(bad)",          { XX } },
5425     { "(bad)",          { XX } },
5426     { "(bad)",          { XX } },
5427     { "(bad)",          { XX } },
5428     { "(bad)",          { XX } },
5429     { "(bad)",          { XX } },
5430     /* 20 */
5431     { "(bad)",          { XX } },
5432     { "(bad)",          { XX } },
5433     { "(bad)",          { XX } },
5434     { "(bad)",          { XX } },
5435     { "(bad)",          { XX } },
5436     { "(bad)",          { XX } },
5437     { "(bad)",          { XX } },
5438     { "(bad)",          { XX } },
5439     /* 28 */
5440     { "(bad)",          { XX } },
5441     { "(bad)",          { XX } },
5442     { "(bad)",          { XX } },
5443     { "(bad)",          { XX } },
5444     { "comps",          { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
5445     { "compd",          { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
5446     { "comss",          { { OP_DREX3, w_mode }, { OP_DREX_FCMP, b_mode } } },
5447     { "comsd",          { { OP_DREX3, d_mode }, { OP_DREX_FCMP, b_mode } } },
5448     /* 30 */
5449     { "(bad)",          { XX } },
5450     { "(bad)",          { XX } },
5451     { "(bad)",          { XX } },
5452     { "(bad)",          { XX } },
5453     { "(bad)",          { XX } },
5454     { "(bad)",          { XX } },
5455     { "(bad)",          { XX } },
5456     { "(bad)",          { XX } },
5457     /* 38 */
5458     { "(bad)",          { XX } },
5459     { "(bad)",          { XX } },
5460     { "(bad)",          { XX } },
5461     { "(bad)",          { XX } },
5462     { "(bad)",          { XX } },
5463     { "(bad)",          { XX } },
5464     { "(bad)",          { XX } },
5465     { "(bad)",          { XX } },
5466     /* 40 */
5467     { "(bad)",          { XX } },
5468     { "(bad)",          { XX } },
5469     { "(bad)",          { XX } },
5470     { "(bad)",          { XX } },
5471     { "(bad)",          { XX } },
5472     { "(bad)",          { XX } },
5473     { "(bad)",          { XX } },
5474     { "(bad)",          { XX } },
5475     /* 48 */
5476     { "(bad)",          { XX } },
5477     { "(bad)",          { XX } },
5478     { "(bad)",          { XX } },
5479     { "(bad)",          { XX } },
5480     { "pcomb",          { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5481     { "pcomw",          { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5482     { "pcomd",          { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5483     { "pcomq",          { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5484     /* 50 */
5485     { "(bad)",          { XX } },
5486     { "(bad)",          { XX } },
5487     { "(bad)",          { XX } },
5488     { "(bad)",          { XX } },
5489     { "(bad)",          { XX } },
5490     { "(bad)",          { XX } },
5491     { "(bad)",          { XX } },
5492     { "(bad)",          { XX } },
5493     /* 58 */
5494     { "(bad)",          { XX } },
5495     { "(bad)",          { XX } },
5496     { "(bad)",          { XX } },
5497     { "(bad)",          { XX } },
5498     { "(bad)",          { XX } },
5499     { "(bad)",          { XX } },
5500     { "(bad)",          { XX } },
5501     { "(bad)",          { XX } },
5502     /* 60 */
5503     { "(bad)",          { XX } },
5504     { "(bad)",          { XX } },
5505     { "(bad)",          { XX } },
5506     { "(bad)",          { XX } },
5507     { "(bad)",          { XX } },
5508     { "(bad)",          { XX } },
5509     { "(bad)",          { XX } },
5510     { "(bad)",          { XX } },
5511     /* 68 */
5512     { "(bad)",          { XX } },
5513     { "(bad)",          { XX } },
5514     { "(bad)",          { XX } },
5515     { "(bad)",          { XX } },
5516     { "pcomub",         { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5517     { "pcomuw",         { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5518     { "pcomud",         { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5519     { "pcomuq",         { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5520     /* 70 */
5521     { "(bad)",          { XX } },
5522     { "(bad)",          { XX } },
5523     { "(bad)",          { XX } },
5524     { "(bad)",          { XX } },
5525     { "(bad)",          { XX } },
5526     { "(bad)",          { XX } },
5527     { "(bad)",          { XX } },
5528     { "(bad)",          { XX } },
5529     /* 78 */
5530     { "(bad)",          { XX } },
5531     { "(bad)",          { XX } },
5532     { "(bad)",          { XX } },
5533     { "(bad)",          { XX } },
5534     { "(bad)",          { XX } },
5535     { "(bad)",          { XX } },
5536     { "(bad)",          { XX } },
5537     { "(bad)",          { XX } },
5538     /* 80 */
5539     { "(bad)",          { XX } },
5540     { "(bad)",          { XX } },
5541     { "(bad)",          { XX } },
5542     { "(bad)",          { XX } },
5543     { "(bad)",          { XX } },
5544     { "(bad)",          { XX } },
5545     { "(bad)",          { XX } },
5546     { "(bad)",          { XX } },
5547     /* 88 */
5548     { "(bad)",          { XX } },
5549     { "(bad)",          { XX } },
5550     { "(bad)",          { XX } },
5551     { "(bad)",          { XX } },
5552     { "(bad)",          { XX } },
5553     { "(bad)",          { XX } },
5554     { "(bad)",          { XX } },
5555     { "(bad)",          { XX } },
5556     /* 90 */
5557     { "(bad)",          { XX } },
5558     { "(bad)",          { XX } },
5559     { "(bad)",          { XX } },
5560     { "(bad)",          { XX } },
5561     { "(bad)",          { XX } },
5562     { "(bad)",          { XX } },
5563     { "(bad)",          { XX } },
5564     { "(bad)",          { XX } },
5565     /* 98 */
5566     { "(bad)",          { XX } },
5567     { "(bad)",          { XX } },
5568     { "(bad)",          { XX } },
5569     { "(bad)",          { XX } },
5570     { "(bad)",          { XX } },
5571     { "(bad)",          { XX } },
5572     { "(bad)",          { XX } },
5573     { "(bad)",          { XX } },
5574     /* a0 */
5575     { "(bad)",          { XX } },
5576     { "(bad)",          { XX } },
5577     { "(bad)",          { XX } },
5578     { "(bad)",          { XX } },
5579     { "(bad)",          { XX } },
5580     { "(bad)",          { XX } },
5581     { "(bad)",          { XX } },
5582     { "(bad)",          { XX } },
5583     /* a8 */
5584     { "(bad)",          { XX } },
5585     { "(bad)",          { XX } },
5586     { "(bad)",          { XX } },
5587     { "(bad)",          { XX } },
5588     { "(bad)",          { XX } },
5589     { "(bad)",          { XX } },
5590     { "(bad)",          { XX } },
5591     { "(bad)",          { XX } },
5592     /* b0 */
5593     { "(bad)",          { XX } },
5594     { "(bad)",          { XX } },
5595     { "(bad)",          { XX } },
5596     { "(bad)",          { XX } },
5597     { "(bad)",          { XX } },
5598     { "(bad)",          { XX } },
5599     { "(bad)",          { XX } },
5600     { "(bad)",          { XX } },
5601     /* b8 */
5602     { "(bad)",          { XX } },
5603     { "(bad)",          { XX } },
5604     { "(bad)",          { XX } },
5605     { "(bad)",          { XX } },
5606     { "(bad)",          { XX } },
5607     { "(bad)",          { XX } },
5608     { "(bad)",          { XX } },
5609     { "(bad)",          { XX } },
5610     /* c0 */
5611     { "(bad)",          { XX } },
5612     { "(bad)",          { XX } },
5613     { "(bad)",          { XX } },
5614     { "(bad)",          { XX } },
5615     { "(bad)",          { XX } },
5616     { "(bad)",          { XX } },
5617     { "(bad)",          { XX } },
5618     { "(bad)",          { XX } },
5619     /* c8 */
5620     { "(bad)",          { XX } },
5621     { "(bad)",          { XX } },
5622     { "(bad)",          { XX } },
5623     { "(bad)",          { XX } },
5624     { "(bad)",          { XX } },
5625     { "(bad)",          { XX } },
5626     { "(bad)",          { XX } },
5627     { "(bad)",          { XX } },
5628     /* d0 */
5629     { "(bad)",          { XX } },
5630     { "(bad)",          { XX } },
5631     { "(bad)",          { XX } },
5632     { "(bad)",          { XX } },
5633     { "(bad)",          { XX } },
5634     { "(bad)",          { XX } },
5635     { "(bad)",          { XX } },
5636     { "(bad)",          { XX } },
5637     /* d8 */
5638     { "(bad)",          { XX } },
5639     { "(bad)",          { XX } },
5640     { "(bad)",          { XX } },
5641     { "(bad)",          { XX } },
5642     { "(bad)",          { XX } },
5643     { "(bad)",          { XX } },
5644     { "(bad)",          { XX } },
5645     { "(bad)",          { XX } },
5646     /* e0 */
5647     { "(bad)",          { XX } },
5648     { "(bad)",          { XX } },
5649     { "(bad)",          { XX } },
5650     { "(bad)",          { XX } },
5651     { "(bad)",          { XX } },
5652     { "(bad)",          { XX } },
5653     { "(bad)",          { XX } },
5654     { "(bad)",          { XX } },
5655     /* e8 */
5656     { "(bad)",          { XX } },
5657     { "(bad)",          { XX } },
5658     { "(bad)",          { XX } },
5659     { "(bad)",          { XX } },
5660     { "(bad)",          { XX } },
5661     { "(bad)",          { XX } },
5662     { "(bad)",          { XX } },
5663     { "(bad)",          { XX } },
5664     /* f0 */
5665     { "(bad)",          { XX } },
5666     { "(bad)",          { XX } },
5667     { "(bad)",          { XX } },
5668     { "(bad)",          { XX } },
5669     { "(bad)",          { XX } },
5670     { "(bad)",          { XX } },
5671     { "(bad)",          { XX } },
5672     { "(bad)",          { XX } },
5673     /* f8 */
5674     { "(bad)",          { XX } },
5675     { "(bad)",          { XX } },
5676     { "(bad)",          { XX } },
5677     { "(bad)",          { XX } },
5678     { "(bad)",          { XX } },
5679     { "(bad)",          { XX } },
5680     { "(bad)",          { XX } },
5681     { "(bad)",          { XX } },
5682   },
5683   /* THREE_BYTE_0F38 */
5684   {
5685     /* 00 */
5686     { "pshufb",         { MX, EM } },
5687     { "phaddw",         { MX, EM } },
5688     { "phaddd",         { MX, EM } },
5689     { "phaddsw",        { MX, EM } },
5690     { "pmaddubsw",      { MX, EM } },
5691     { "phsubw",         { MX, EM } },
5692     { "phsubd",         { MX, EM } },
5693     { "phsubsw",        { MX, EM } },
5694     /* 08 */
5695     { "psignb",         { MX, EM } },
5696     { "psignw",         { MX, EM } },
5697     { "psignd",         { MX, EM } },
5698     { "pmulhrsw",       { MX, EM } },
5699     { "(bad)",          { XX } },
5700     { "(bad)",          { XX } },
5701     { "(bad)",          { XX } },
5702     { "(bad)",          { XX } },
5703     /* 10 */
5704     { PREFIX_TABLE (PREFIX_0F3810) },
5705     { "(bad)",          { XX } },
5706     { "(bad)",          { XX } },
5707     { "(bad)",          { XX } },
5708     { PREFIX_TABLE (PREFIX_0F3814) },
5709     { PREFIX_TABLE (PREFIX_0F3815) },
5710     { "(bad)",          { XX } },
5711     { PREFIX_TABLE (PREFIX_0F3817) },
5712     /* 18 */
5713     { "(bad)",          { XX } },
5714     { "(bad)",          { XX } },
5715     { "(bad)",          { XX } },
5716     { "(bad)",          { XX } },
5717     { "pabsb",          { MX, EM } },
5718     { "pabsw",          { MX, EM } },
5719     { "pabsd",          { MX, EM } },
5720     { "(bad)",          { XX } },
5721     /* 20 */
5722     { PREFIX_TABLE (PREFIX_0F3820) },
5723     { PREFIX_TABLE (PREFIX_0F3821) },
5724     { PREFIX_TABLE (PREFIX_0F3822) },
5725     { PREFIX_TABLE (PREFIX_0F3823) },
5726     { PREFIX_TABLE (PREFIX_0F3824) },
5727     { PREFIX_TABLE (PREFIX_0F3825) },
5728     { "(bad)",          { XX } },
5729     { "(bad)",          { XX } },
5730     /* 28 */
5731     { PREFIX_TABLE (PREFIX_0F3828) },
5732     { PREFIX_TABLE (PREFIX_0F3829) },
5733     { PREFIX_TABLE (PREFIX_0F382A) },
5734     { PREFIX_TABLE (PREFIX_0F382B) },
5735     { "(bad)",          { XX } },
5736     { "(bad)",          { XX } },
5737     { "(bad)",          { XX } },
5738     { "(bad)",          { XX } },
5739     /* 30 */
5740     { PREFIX_TABLE (PREFIX_0F3830) },
5741     { PREFIX_TABLE (PREFIX_0F3831) },
5742     { PREFIX_TABLE (PREFIX_0F3832) },
5743     { PREFIX_TABLE (PREFIX_0F3833) },
5744     { PREFIX_TABLE (PREFIX_0F3834) },
5745     { PREFIX_TABLE (PREFIX_0F3835) },
5746     { "(bad)",          { XX } },
5747     { PREFIX_TABLE (PREFIX_0F3837) },
5748     /* 38 */
5749     { PREFIX_TABLE (PREFIX_0F3838) },
5750     { PREFIX_TABLE (PREFIX_0F3839) },
5751     { PREFIX_TABLE (PREFIX_0F383A) },
5752     { PREFIX_TABLE (PREFIX_0F383B) },
5753     { PREFIX_TABLE (PREFIX_0F383C) },
5754     { PREFIX_TABLE (PREFIX_0F383D) },
5755     { PREFIX_TABLE (PREFIX_0F383E) },
5756     { PREFIX_TABLE (PREFIX_0F383F) },
5757     /* 40 */
5758     { PREFIX_TABLE (PREFIX_0F3840) },
5759     { PREFIX_TABLE (PREFIX_0F3841) },
5760     { "(bad)",          { XX } },
5761     { "(bad)",          { XX } },
5762     { "(bad)",          { XX } },
5763     { "(bad)",          { XX } },
5764     { "(bad)",          { XX } },
5765     { "(bad)",          { XX } },
5766     /* 48 */
5767     { "(bad)",          { XX } },
5768     { "(bad)",          { XX } },
5769     { "(bad)",          { XX } },
5770     { "(bad)",          { XX } },
5771     { "(bad)",          { XX } },
5772     { "(bad)",          { XX } },
5773     { "(bad)",          { XX } },
5774     { "(bad)",          { XX } },
5775     /* 50 */
5776     { "(bad)",          { XX } },
5777     { "(bad)",          { XX } },
5778     { "(bad)",          { XX } },
5779     { "(bad)",          { XX } },
5780     { "(bad)",          { XX } },
5781     { "(bad)",          { XX } },
5782     { "(bad)",          { XX } },
5783     { "(bad)",          { XX } },
5784     /* 58 */
5785     { "(bad)",          { XX } },
5786     { "(bad)",          { XX } },
5787     { "(bad)",          { XX } },
5788     { "(bad)",          { XX } },
5789     { "(bad)",          { XX } },
5790     { "(bad)",          { XX } },
5791     { "(bad)",          { XX } },
5792     { "(bad)",          { XX } },
5793     /* 60 */
5794     { "(bad)",          { XX } },
5795     { "(bad)",          { XX } },
5796     { "(bad)",          { XX } },
5797     { "(bad)",          { XX } },
5798     { "(bad)",          { XX } },
5799     { "(bad)",          { XX } },
5800     { "(bad)",          { XX } },
5801     { "(bad)",          { XX } },
5802     /* 68 */
5803     { "(bad)",          { XX } },
5804     { "(bad)",          { XX } },
5805     { "(bad)",          { XX } },
5806     { "(bad)",          { XX } },
5807     { "(bad)",          { XX } },
5808     { "(bad)",          { XX } },
5809     { "(bad)",          { XX } },
5810     { "(bad)",          { XX } },
5811     /* 70 */
5812     { "(bad)",          { XX } },
5813     { "(bad)",          { XX } },
5814     { "(bad)",          { XX } },
5815     { "(bad)",          { XX } },
5816     { "(bad)",          { XX } },
5817     { "(bad)",          { XX } },
5818     { "(bad)",          { XX } },
5819     { "(bad)",          { XX } },
5820     /* 78 */
5821     { "(bad)",          { XX } },
5822     { "(bad)",          { XX } },
5823     { "(bad)",          { XX } },
5824     { "(bad)",          { XX } },
5825     { "(bad)",          { XX } },
5826     { "(bad)",          { XX } },
5827     { "(bad)",          { XX } },
5828     { "(bad)",          { XX } },
5829     /* 80 */
5830     { "(bad)",          { XX } },
5831     { "(bad)",          { XX } },
5832     { "(bad)",          { XX } },
5833     { "(bad)",          { XX } },
5834     { "(bad)",          { XX } },
5835     { "(bad)",          { XX } },
5836     { "(bad)",          { XX } },
5837     { "(bad)",          { XX } },
5838     /* 88 */
5839     { "(bad)",          { XX } },
5840     { "(bad)",          { XX } },
5841     { "(bad)",          { XX } },
5842     { "(bad)",          { XX } },
5843     { "(bad)",          { XX } },
5844     { "(bad)",          { XX } },
5845     { "(bad)",          { XX } },
5846     { "(bad)",          { XX } },
5847     /* 90 */
5848     { "(bad)",          { XX } },
5849     { "(bad)",          { XX } },
5850     { "(bad)",          { XX } },
5851     { "(bad)",          { XX } },
5852     { "(bad)",          { XX } },
5853     { "(bad)",          { XX } },
5854     { "(bad)",          { XX } },
5855     { "(bad)",          { XX } },
5856     /* 98 */
5857     { "(bad)",          { XX } },
5858     { "(bad)",          { XX } },
5859     { "(bad)",          { XX } },
5860     { "(bad)",          { XX } },
5861     { "(bad)",          { XX } },
5862     { "(bad)",          { XX } },
5863     { "(bad)",          { XX } },
5864     { "(bad)",          { XX } },
5865     /* a0 */
5866     { "(bad)",          { XX } },
5867     { "(bad)",          { XX } },
5868     { "(bad)",          { XX } },
5869     { "(bad)",          { XX } },
5870     { "(bad)",          { XX } },
5871     { "(bad)",          { XX } },
5872     { "(bad)",          { XX } },
5873     { "(bad)",          { XX } },
5874     /* a8 */
5875     { "(bad)",          { XX } },
5876     { "(bad)",          { XX } },
5877     { "(bad)",          { XX } },
5878     { "(bad)",          { XX } },
5879     { "(bad)",          { XX } },
5880     { "(bad)",          { XX } },
5881     { "(bad)",          { XX } },
5882     { "(bad)",          { XX } },
5883     /* b0 */
5884     { "(bad)",          { XX } },
5885     { "(bad)",          { XX } },
5886     { "(bad)",          { XX } },
5887     { "(bad)",          { XX } },
5888     { "(bad)",          { XX } },
5889     { "(bad)",          { XX } },
5890     { "(bad)",          { XX } },
5891     { "(bad)",          { XX } },
5892     /* b8 */
5893     { "(bad)",          { XX } },
5894     { "(bad)",          { XX } },
5895     { "(bad)",          { XX } },
5896     { "(bad)",          { XX } },
5897     { "(bad)",          { XX } },
5898     { "(bad)",          { XX } },
5899     { "(bad)",          { XX } },
5900     { "(bad)",          { XX } },
5901     /* c0 */
5902     { "(bad)",          { XX } },
5903     { "(bad)",          { XX } },
5904     { "(bad)",          { XX } },
5905     { "(bad)",          { XX } },
5906     { "(bad)",          { XX } },
5907     { "(bad)",          { XX } },
5908     { "(bad)",          { XX } },
5909     { "(bad)",          { XX } },
5910     /* c8 */
5911     { "(bad)",          { XX } },
5912     { "(bad)",          { XX } },
5913     { "(bad)",          { XX } },
5914     { "(bad)",          { XX } },
5915     { "(bad)",          { XX } },
5916     { "(bad)",          { XX } },
5917     { "(bad)",          { XX } },
5918     { "(bad)",          { XX } },
5919     /* d0 */
5920     { "(bad)",          { XX } },
5921     { "(bad)",          { XX } },
5922     { "(bad)",          { XX } },
5923     { "(bad)",          { XX } },
5924     { "(bad)",          { XX } },
5925     { "(bad)",          { XX } },
5926     { "(bad)",          { XX } },
5927     { "(bad)",          { XX } },
5928     /* d8 */
5929     { "(bad)",          { XX } },
5930     { "(bad)",          { XX } },
5931     { "(bad)",          { XX } },
5932     { PREFIX_TABLE (PREFIX_0F38DB) },
5933     { PREFIX_TABLE (PREFIX_0F38DC) },
5934     { PREFIX_TABLE (PREFIX_0F38DD) },
5935     { PREFIX_TABLE (PREFIX_0F38DE) },
5936     { PREFIX_TABLE (PREFIX_0F38DF) },
5937     /* e0 */
5938     { "(bad)",          { XX } },
5939     { "(bad)",          { XX } },
5940     { "(bad)",          { XX } },
5941     { "(bad)",          { XX } },
5942     { "(bad)",          { XX } },
5943     { "(bad)",          { XX } },
5944     { "(bad)",          { XX } },
5945     { "(bad)",          { XX } },
5946     /* e8 */
5947     { "(bad)",          { XX } },
5948     { "(bad)",          { XX } },
5949     { "(bad)",          { XX } },
5950     { "(bad)",          { XX } },
5951     { "(bad)",          { XX } },
5952     { "(bad)",          { XX } },
5953     { "(bad)",          { XX } },
5954     { "(bad)",          { XX } },
5955     /* f0 */
5956     { PREFIX_TABLE (PREFIX_0F38F0) },
5957     { PREFIX_TABLE (PREFIX_0F38F1) },
5958     { "(bad)",          { XX } },
5959     { "(bad)",          { XX } },
5960     { "(bad)",          { XX } },
5961     { "(bad)",          { XX } },
5962     { "(bad)",          { XX } },
5963     { "(bad)",          { XX } },
5964     /* f8 */
5965     { "(bad)",          { XX } },
5966     { "(bad)",          { XX } },
5967     { "(bad)",          { XX } },
5968     { "(bad)",          { XX } },
5969     { "(bad)",          { XX } },
5970     { "(bad)",          { XX } },
5971     { "(bad)",          { XX } },
5972     { "(bad)",          { XX } },
5973   },
5974   /* THREE_BYTE_0F3A */
5975   {
5976     /* 00 */
5977     { "(bad)",          { XX } },
5978     { "(bad)",          { XX } },
5979     { "(bad)",          { XX } },
5980     { "(bad)",          { XX } },
5981     { "(bad)",          { XX } },
5982     { "(bad)",          { XX } },
5983     { "(bad)",          { XX } },
5984     { "(bad)",          { XX } },
5985     /* 08 */
5986     { PREFIX_TABLE (PREFIX_0F3A08) },
5987     { PREFIX_TABLE (PREFIX_0F3A09) },
5988     { PREFIX_TABLE (PREFIX_0F3A0A) },
5989     { PREFIX_TABLE (PREFIX_0F3A0B) },
5990     { PREFIX_TABLE (PREFIX_0F3A0C) },
5991     { PREFIX_TABLE (PREFIX_0F3A0D) },
5992     { PREFIX_TABLE (PREFIX_0F3A0E) },
5993     { "palignr",        { MX, EM, Ib } },
5994     /* 10 */
5995     { "(bad)",          { XX } },
5996     { "(bad)",          { XX } },
5997     { "(bad)",          { XX } },
5998     { "(bad)",          { XX } },
5999     { PREFIX_TABLE (PREFIX_0F3A14) },
6000     { PREFIX_TABLE (PREFIX_0F3A15) },
6001     { PREFIX_TABLE (PREFIX_0F3A16) },
6002     { PREFIX_TABLE (PREFIX_0F3A17) },
6003     /* 18 */
6004     { "(bad)",          { XX } },
6005     { "(bad)",          { XX } },
6006     { "(bad)",          { XX } },
6007     { "(bad)",          { XX } },
6008     { "(bad)",          { XX } },
6009     { "(bad)",          { XX } },
6010     { "(bad)",          { XX } },
6011     { "(bad)",          { XX } },
6012     /* 20 */
6013     { PREFIX_TABLE (PREFIX_0F3A20) },
6014     { PREFIX_TABLE (PREFIX_0F3A21) },
6015     { PREFIX_TABLE (PREFIX_0F3A22) },
6016     { "(bad)",          { XX } },
6017     { "(bad)",          { XX } },
6018     { "(bad)",          { XX } },
6019     { "(bad)",          { XX } },
6020     { "(bad)",          { XX } },
6021     /* 28 */
6022     { "(bad)",          { XX } },
6023     { "(bad)",          { XX } },
6024     { "(bad)",          { XX } },
6025     { "(bad)",          { XX } },
6026     { "(bad)",          { XX } },
6027     { "(bad)",          { XX } },
6028     { "(bad)",          { XX } },
6029     { "(bad)",          { XX } },
6030     /* 30 */
6031     { "(bad)",          { XX } },
6032     { "(bad)",          { XX } },
6033     { "(bad)",          { XX } },
6034     { "(bad)",          { XX } },
6035     { "(bad)",          { XX } },
6036     { "(bad)",          { XX } },
6037     { "(bad)",          { XX } },
6038     { "(bad)",          { XX } },
6039     /* 38 */
6040     { "(bad)",          { XX } },
6041     { "(bad)",          { XX } },
6042     { "(bad)",          { XX } },
6043     { "(bad)",          { XX } },
6044     { "(bad)",          { XX } },
6045     { "(bad)",          { XX } },
6046     { "(bad)",          { XX } },
6047     { "(bad)",          { XX } },
6048     /* 40 */
6049     { PREFIX_TABLE (PREFIX_0F3A40) },
6050     { PREFIX_TABLE (PREFIX_0F3A41) },
6051     { PREFIX_TABLE (PREFIX_0F3A42) },
6052     { "(bad)",          { XX } },
6053     { PREFIX_TABLE (PREFIX_0F3A44) },
6054     { "(bad)",          { XX } },
6055     { "(bad)",          { XX } },
6056     { "(bad)",          { XX } },
6057     /* 48 */
6058     { "(bad)",          { XX } },
6059     { "(bad)",          { XX } },
6060     { "(bad)",          { XX } },
6061     { "(bad)",          { XX } },
6062     { "(bad)",          { XX } },
6063     { "(bad)",          { XX } },
6064     { "(bad)",          { XX } },
6065     { "(bad)",          { XX } },
6066     /* 50 */
6067     { "(bad)",          { XX } },
6068     { "(bad)",          { XX } },
6069     { "(bad)",          { XX } },
6070     { "(bad)",          { XX } },
6071     { "(bad)",          { XX } },
6072     { "(bad)",          { XX } },
6073     { "(bad)",          { XX } },
6074     { "(bad)",          { XX } },
6075     /* 58 */
6076     { "(bad)",          { XX } },
6077     { "(bad)",          { XX } },
6078     { "(bad)",          { XX } },
6079     { "(bad)",          { XX } },
6080     { "(bad)",          { XX } },
6081     { "(bad)",          { XX } },
6082     { "(bad)",          { XX } },
6083     { "(bad)",          { XX } },
6084     /* 60 */
6085     { PREFIX_TABLE (PREFIX_0F3A60) },
6086     { PREFIX_TABLE (PREFIX_0F3A61) },
6087     { PREFIX_TABLE (PREFIX_0F3A62) },
6088     { PREFIX_TABLE (PREFIX_0F3A63) },
6089     { "(bad)",          { XX } },
6090     { "(bad)",          { XX } },
6091     { "(bad)",          { XX } },
6092     { "(bad)",          { XX } },
6093     /* 68 */
6094     { "(bad)",          { XX } },
6095     { "(bad)",          { XX } },
6096     { "(bad)",          { XX } },
6097     { "(bad)",          { XX } },
6098     { "(bad)",          { XX } },
6099     { "(bad)",          { XX } },
6100     { "(bad)",          { XX } },
6101     { "(bad)",          { XX } },
6102     /* 70 */
6103     { "(bad)",          { XX } },
6104     { "(bad)",          { XX } },
6105     { "(bad)",          { XX } },
6106     { "(bad)",          { XX } },
6107     { "(bad)",          { XX } },
6108     { "(bad)",          { XX } },
6109     { "(bad)",          { XX } },
6110     { "(bad)",          { XX } },
6111     /* 78 */
6112     { "(bad)",          { XX } },
6113     { "(bad)",          { XX } },
6114     { "(bad)",          { XX } },
6115     { "(bad)",          { XX } },
6116     { "(bad)",          { XX } },
6117     { "(bad)",          { XX } },
6118     { "(bad)",          { XX } },
6119     { "(bad)",          { XX } },
6120     /* 80 */
6121     { "(bad)",          { XX } },
6122     { "(bad)",          { XX } },
6123     { "(bad)",          { XX } },
6124     { "(bad)",          { XX } },
6125     { "(bad)",          { XX } },
6126     { "(bad)",          { XX } },
6127     { "(bad)",          { XX } },
6128     { "(bad)",          { XX } },
6129     /* 88 */
6130     { "(bad)",          { XX } },
6131     { "(bad)",          { XX } },
6132     { "(bad)",          { XX } },
6133     { "(bad)",          { XX } },
6134     { "(bad)",          { XX } },
6135     { "(bad)",          { XX } },
6136     { "(bad)",          { XX } },
6137     { "(bad)",          { XX } },
6138     /* 90 */
6139     { "(bad)",          { XX } },
6140     { "(bad)",          { XX } },
6141     { "(bad)",          { XX } },
6142     { "(bad)",          { XX } },
6143     { "(bad)",          { XX } },
6144     { "(bad)",          { XX } },
6145     { "(bad)",          { XX } },
6146     { "(bad)",          { XX } },
6147     /* 98 */
6148     { "(bad)",          { XX } },
6149     { "(bad)",          { XX } },
6150     { "(bad)",          { XX } },
6151     { "(bad)",          { XX } },
6152     { "(bad)",          { XX } },
6153     { "(bad)",          { XX } },
6154     { "(bad)",          { XX } },
6155     { "(bad)",          { XX } },
6156     /* a0 */
6157     { "(bad)",          { XX } },
6158     { "(bad)",          { XX } },
6159     { "(bad)",          { XX } },
6160     { "(bad)",          { XX } },
6161     { "(bad)",          { XX } },
6162     { "(bad)",          { XX } },
6163     { "(bad)",          { XX } },
6164     { "(bad)",          { XX } },
6165     /* a8 */
6166     { "(bad)",          { XX } },
6167     { "(bad)",          { XX } },
6168     { "(bad)",          { XX } },
6169     { "(bad)",          { XX } },
6170     { "(bad)",          { XX } },
6171     { "(bad)",          { XX } },
6172     { "(bad)",          { XX } },
6173     { "(bad)",          { XX } },
6174     /* b0 */
6175     { "(bad)",          { XX } },
6176     { "(bad)",          { XX } },
6177     { "(bad)",          { XX } },
6178     { "(bad)",          { XX } },
6179     { "(bad)",          { XX } },
6180     { "(bad)",          { XX } },
6181     { "(bad)",          { XX } },
6182     { "(bad)",          { XX } },
6183     /* b8 */
6184     { "(bad)",          { XX } },
6185     { "(bad)",          { XX } },
6186     { "(bad)",          { XX } },
6187     { "(bad)",          { XX } },
6188     { "(bad)",          { XX } },
6189     { "(bad)",          { XX } },
6190     { "(bad)",          { XX } },
6191     { "(bad)",          { XX } },
6192     /* c0 */
6193     { "(bad)",          { XX } },
6194     { "(bad)",          { XX } },
6195     { "(bad)",          { XX } },
6196     { "(bad)",          { XX } },
6197     { "(bad)",          { XX } },
6198     { "(bad)",          { XX } },
6199     { "(bad)",          { XX } },
6200     { "(bad)",          { XX } },
6201     /* c8 */
6202     { "(bad)",          { XX } },
6203     { "(bad)",          { XX } },
6204     { "(bad)",          { XX } },
6205     { "(bad)",          { XX } },
6206     { "(bad)",          { XX } },
6207     { "(bad)",          { XX } },
6208     { "(bad)",          { XX } },
6209     { "(bad)",          { XX } },
6210     /* d0 */
6211     { "(bad)",          { XX } },
6212     { "(bad)",          { XX } },
6213     { "(bad)",          { XX } },
6214     { "(bad)",          { XX } },
6215     { "(bad)",          { XX } },
6216     { "(bad)",          { XX } },
6217     { "(bad)",          { XX } },
6218     { "(bad)",          { XX } },
6219     /* d8 */
6220     { "(bad)",          { XX } },
6221     { "(bad)",          { XX } },
6222     { "(bad)",          { XX } },
6223     { "(bad)",          { XX } },
6224     { "(bad)",          { XX } },
6225     { "(bad)",          { XX } },
6226     { "(bad)",          { XX } },
6227     { PREFIX_TABLE (PREFIX_0F3ADF) },
6228     /* e0 */
6229     { "(bad)",          { XX } },
6230     { "(bad)",          { XX } },
6231     { "(bad)",          { XX } },
6232     { "(bad)",          { XX } },
6233     { "(bad)",          { XX } },
6234     { "(bad)",          { XX } },
6235     { "(bad)",          { XX } },
6236     { "(bad)",          { XX } },
6237     /* e8 */
6238     { "(bad)",          { XX } },
6239     { "(bad)",          { XX } },
6240     { "(bad)",          { XX } },
6241     { "(bad)",          { XX } },
6242     { "(bad)",          { XX } },
6243     { "(bad)",          { XX } },
6244     { "(bad)",          { XX } },
6245     { "(bad)",          { XX } },
6246     /* f0 */
6247     { "(bad)",          { XX } },
6248     { "(bad)",          { XX } },
6249     { "(bad)",          { XX } },
6250     { "(bad)",          { XX } },
6251     { "(bad)",          { XX } },
6252     { "(bad)",          { XX } },
6253     { "(bad)",          { XX } },
6254     { "(bad)",          { XX } },
6255     /* f8 */
6256     { "(bad)",          { XX } },
6257     { "(bad)",          { XX } },
6258     { "(bad)",          { XX } },
6259     { "(bad)",          { XX } },
6260     { "(bad)",          { XX } },
6261     { "(bad)",          { XX } },
6262     { "(bad)",          { XX } },
6263     { "(bad)",          { XX } },
6264   },
6265   /* THREE_BYTE_0F7A */
6266   {
6267     /* 00 */
6268     { "(bad)",          { XX } },
6269     { "(bad)",          { XX } },
6270     { "(bad)",          { XX } },
6271     { "(bad)",          { XX } },
6272     { "(bad)",          { XX } },
6273     { "(bad)",          { XX } },
6274     { "(bad)",          { XX } },
6275     { "(bad)",          { XX } },
6276     /* 08 */
6277     { "(bad)",          { XX } },
6278     { "(bad)",          { XX } },
6279     { "(bad)",          { XX } },
6280     { "(bad)",          { XX } },
6281     { "(bad)",          { XX } },
6282     { "(bad)",          { XX } },
6283     { "(bad)",          { XX } },
6284     { "(bad)",          { XX } },
6285     /* 10 */
6286     { "frczps",         { XM, EXq } },
6287     { "frczpd",         { XM, EXq } },
6288     { "frczss",         { XM, EXq } },
6289     { "frczsd",         { XM, EXq } },
6290     { "(bad)",          { XX } },
6291     { "(bad)",          { XX } },
6292     { "(bad)",          { XX } },
6293     { "(bad)",          { XX } },
6294     /* 18 */
6295     { "(bad)",          { XX } },
6296     { "(bad)",          { XX } },
6297     { "(bad)",          { XX } },
6298     { "(bad)",          { XX } },
6299     { "(bad)",          { XX } },
6300     { "(bad)",          { XX } },
6301     { "(bad)",          { XX } },
6302     { "(bad)",          { XX } },
6303     /* 20 */
6304     { "ptest",          { XX } },
6305     { "(bad)",          { XX } },
6306     { "(bad)",          { XX } },
6307     { "(bad)",          { XX } },
6308     { "(bad)",          { XX } },
6309     { "(bad)",          { XX } },
6310     { "(bad)",          { XX } },
6311     { "(bad)",          { XX } },
6312     /* 28 */
6313     { "(bad)",          { XX } },
6314     { "(bad)",          { XX } },
6315     { "(bad)",          { XX } },
6316     { "(bad)",          { XX } },
6317     { "(bad)",          { XX } },
6318     { "(bad)",          { XX } },
6319     { "(bad)",          { XX } },
6320     { "(bad)",          { XX } },
6321     /* 30 */
6322     { "cvtph2ps",       { XM, EXd } },
6323     { "cvtps2ph",       { EXd, XM } },
6324     { "(bad)",          { XX } },
6325     { "(bad)",          { XX } },
6326     { "(bad)",          { XX } },
6327     { "(bad)",          { XX } },
6328     { "(bad)",          { XX } },
6329     { "(bad)",          { XX } },
6330     /* 38 */
6331     { "(bad)",          { XX } },
6332     { "(bad)",          { XX } },
6333     { "(bad)",          { XX } },
6334     { "(bad)",          { XX } },
6335     { "(bad)",          { XX } },
6336     { "(bad)",          { XX } },
6337     { "(bad)",          { XX } },
6338     { "(bad)",          { XX } },
6339     /* 40 */
6340     { "(bad)",          { XX } },
6341     { "phaddbw",        { XM, EXq } },
6342     { "phaddbd",        { XM, EXq } },
6343     { "phaddbq",        { XM, EXq } },
6344     { "(bad)",          { XX } },
6345     { "(bad)",          { XX } },
6346     { "phaddwd",        { XM, EXq } },
6347     { "phaddwq",        { XM, EXq } },
6348     /* 48 */
6349     { "(bad)",          { XX } },
6350     { "(bad)",          { XX } },
6351     { "(bad)",          { XX } },
6352     { "phadddq",        { XM, EXq } },
6353     { "(bad)",          { XX } },
6354     { "(bad)",          { XX } },
6355     { "(bad)",          { XX } },
6356     { "(bad)",          { XX } },
6357     /* 50 */
6358     { "(bad)",          { XX } },
6359     { "phaddubw",       { XM, EXq } },
6360     { "phaddubd",       { XM, EXq } },
6361     { "phaddubq",       { XM, EXq } },
6362     { "(bad)",          { XX } },
6363     { "(bad)",          { XX } },
6364     { "phadduwd",       { XM, EXq } },
6365     { "phadduwq",       { XM, EXq } },
6366     /* 58 */
6367     { "(bad)",          { XX } },
6368     { "(bad)",          { XX } },
6369     { "(bad)",          { XX } },
6370     { "phaddudq",       { XM, EXq } },
6371     { "(bad)",          { XX } },
6372     { "(bad)",          { XX } },
6373     { "(bad)",          { XX } },
6374     { "(bad)",          { XX } },
6375     /* 60 */
6376     { "(bad)",          { XX } },
6377     { "phsubbw",        { XM, EXq } },
6378     { "phsubbd",        { XM, EXq } },
6379     { "phsubbq",        { XM, EXq } },
6380     { "(bad)",          { XX } },
6381     { "(bad)",          { XX } },
6382     { "(bad)",          { XX } },
6383     { "(bad)",          { XX } },
6384     /* 68 */
6385     { "(bad)",          { XX } },
6386     { "(bad)",          { XX } },
6387     { "(bad)",          { XX } },
6388     { "(bad)",          { XX } },
6389     { "(bad)",          { XX } },
6390     { "(bad)",          { XX } },
6391     { "(bad)",          { XX } },
6392     { "(bad)",          { XX } },
6393     /* 70 */
6394     { "(bad)",          { XX } },
6395     { "(bad)",          { XX } },
6396     { "(bad)",          { XX } },
6397     { "(bad)",          { XX } },
6398     { "(bad)",          { XX } },
6399     { "(bad)",          { XX } },
6400     { "(bad)",          { XX } },
6401     { "(bad)",          { XX } },
6402     /* 78 */
6403     { "(bad)",          { XX } },
6404     { "(bad)",          { XX } },
6405     { "(bad)",          { XX } },
6406     { "(bad)",          { XX } },
6407     { "(bad)",          { XX } },
6408     { "(bad)",          { XX } },
6409     { "(bad)",          { XX } },
6410     { "(bad)",          { XX } },
6411     /* 80 */
6412     { "(bad)",          { XX } },
6413     { "(bad)",          { XX } },
6414     { "(bad)",          { XX } },
6415     { "(bad)",          { XX } },
6416     { "(bad)",          { XX } },
6417     { "(bad)",          { XX } },
6418     { "(bad)",          { XX } },
6419     { "(bad)",          { XX } },
6420     /* 88 */
6421     { "(bad)",          { XX } },
6422     { "(bad)",          { XX } },
6423     { "(bad)",          { XX } },
6424     { "(bad)",          { XX } },
6425     { "(bad)",          { XX } },
6426     { "(bad)",          { XX } },
6427     { "(bad)",          { XX } },
6428     { "(bad)",          { XX } },
6429     /* 90 */
6430     { "(bad)",          { XX } },
6431     { "(bad)",          { XX } },
6432     { "(bad)",          { XX } },
6433     { "(bad)",          { XX } },
6434     { "(bad)",          { XX } },
6435     { "(bad)",          { XX } },
6436     { "(bad)",          { XX } },
6437     { "(bad)",          { XX } },
6438     /* 98 */
6439     { "(bad)",          { XX } },
6440     { "(bad)",          { XX } },
6441     { "(bad)",          { XX } },
6442     { "(bad)",          { XX } },
6443     { "(bad)",          { XX } },
6444     { "(bad)",          { XX } },
6445     { "(bad)",          { XX } },
6446     { "(bad)",          { XX } },
6447     /* a0 */
6448     { "(bad)",          { XX } },
6449     { "(bad)",          { XX } },
6450     { "(bad)",          { XX } },
6451     { "(bad)",          { XX } },
6452     { "(bad)",          { XX } },
6453     { "(bad)",          { XX } },
6454     { "(bad)",          { XX } },
6455     { "(bad)",          { XX } },
6456     /* a8 */
6457     { "(bad)",          { XX } },
6458     { "(bad)",          { XX } },
6459     { "(bad)",          { XX } },
6460     { "(bad)",          { XX } },
6461     { "(bad)",          { XX } },
6462     { "(bad)",          { XX } },
6463     { "(bad)",          { XX } },
6464     { "(bad)",          { XX } },
6465     /* b0 */
6466     { "(bad)",          { XX } },
6467     { "(bad)",          { XX } },
6468     { "(bad)",          { XX } },
6469     { "(bad)",          { XX } },
6470     { "(bad)",          { XX } },
6471     { "(bad)",          { XX } },
6472     { "(bad)",          { XX } },
6473     { "(bad)",          { XX } },
6474     /* b8 */
6475     { "(bad)",          { XX } },
6476     { "(bad)",          { XX } },
6477     { "(bad)",          { XX } },
6478     { "(bad)",          { XX } },
6479     { "(bad)",          { XX } },
6480     { "(bad)",          { XX } },
6481     { "(bad)",          { XX } },
6482     { "(bad)",          { XX } },
6483     /* c0 */
6484     { "(bad)",          { XX } },
6485     { "(bad)",          { XX } },
6486     { "(bad)",          { XX } },
6487     { "(bad)",          { XX } },
6488     { "(bad)",          { XX } },
6489     { "(bad)",          { XX } },
6490     { "(bad)",          { XX } },
6491     { "(bad)",          { XX } },
6492     /* c8 */
6493     { "(bad)",          { XX } },
6494     { "(bad)",          { XX } },
6495     { "(bad)",          { XX } },
6496     { "(bad)",          { XX } },
6497     { "(bad)",          { XX } },
6498     { "(bad)",          { XX } },
6499     { "(bad)",          { XX } },
6500     { "(bad)",          { XX } },
6501     /* d0 */
6502     { "(bad)",          { XX } },
6503     { "(bad)",          { XX } },
6504     { "(bad)",          { XX } },
6505     { "(bad)",          { XX } },
6506     { "(bad)",          { XX } },
6507     { "(bad)",          { XX } },
6508     { "(bad)",          { XX } },
6509     { "(bad)",          { XX } },
6510     /* d8 */
6511     { "(bad)",          { XX } },
6512     { "(bad)",          { XX } },
6513     { "(bad)",          { XX } },
6514     { "(bad)",          { XX } },
6515     { "(bad)",          { XX } },
6516     { "(bad)",          { XX } },
6517     { "(bad)",          { XX } },
6518     { "(bad)",          { XX } },
6519     /* e0 */
6520     { "(bad)",          { XX } },
6521     { "(bad)",          { XX } },
6522     { "(bad)",          { XX } },
6523     { "(bad)",          { XX } },
6524     { "(bad)",          { XX } },
6525     { "(bad)",          { XX } },
6526     { "(bad)",          { XX } },
6527     { "(bad)",          { XX } },
6528     /* e8 */
6529     { "(bad)",          { XX } },
6530     { "(bad)",          { XX } },
6531     { "(bad)",          { XX } },
6532     { "(bad)",          { XX } },
6533     { "(bad)",          { XX } },
6534     { "(bad)",          { XX } },
6535     { "(bad)",          { XX } },
6536     { "(bad)",          { XX } },
6537     /* f0 */
6538     { "(bad)",          { XX } },
6539     { "(bad)",          { XX } },
6540     { "(bad)",          { XX } },
6541     { "(bad)",          { XX } },
6542     { "(bad)",          { XX } },
6543     { "(bad)",          { XX } },
6544     { "(bad)",          { XX } },
6545     { "(bad)",          { XX } },
6546     /* f8 */
6547     { "(bad)",          { XX } },
6548     { "(bad)",          { XX } },
6549     { "(bad)",          { XX } },
6550     { "(bad)",          { XX } },
6551     { "(bad)",          { XX } },
6552     { "(bad)",          { XX } },
6553     { "(bad)",          { XX } },
6554     { "(bad)",          { XX } },
6555   },
6556   /* THREE_BYTE_0F7B */
6557   {
6558     /* 00 */
6559     { "(bad)",          { XX } },
6560     { "(bad)",          { XX } },
6561     { "(bad)",          { XX } },
6562     { "(bad)",          { XX } },
6563     { "(bad)",          { XX } },
6564     { "(bad)",          { XX } },
6565     { "(bad)",          { XX } },
6566     { "(bad)",          { XX } },
6567     /* 08 */
6568     { "(bad)",          { XX } },
6569     { "(bad)",          { XX } },
6570     { "(bad)",          { XX } },
6571     { "(bad)",          { XX } },
6572     { "(bad)",          { XX } },
6573     { "(bad)",          { XX } },
6574     { "(bad)",          { XX } },
6575     { "(bad)",          { XX } },
6576     /* 10 */
6577     { "(bad)",          { XX } },
6578     { "(bad)",          { XX } },
6579     { "(bad)",          { XX } },
6580     { "(bad)",          { XX } },
6581     { "(bad)",          { XX } },
6582     { "(bad)",          { XX } },
6583     { "(bad)",          { XX } },
6584     { "(bad)",          { XX } },
6585     /* 18 */
6586     { "(bad)",          { XX } },
6587     { "(bad)",          { XX } },
6588     { "(bad)",          { XX } },
6589     { "(bad)",          { XX } },
6590     { "(bad)",          { XX } },
6591     { "(bad)",          { XX } },
6592     { "(bad)",          { XX } },
6593     { "(bad)",          { XX } },
6594     /* 20 */
6595     { "(bad)",          { XX } },
6596     { "(bad)",          { XX } },
6597     { "(bad)",          { XX } },
6598     { "(bad)",          { XX } },
6599     { "(bad)",          { XX } },
6600     { "(bad)",          { XX } },
6601     { "(bad)",          { XX } },
6602     { "(bad)",          { XX } },
6603     /* 28 */
6604     { "(bad)",          { XX } },
6605     { "(bad)",          { XX } },
6606     { "(bad)",          { XX } },
6607     { "(bad)",          { XX } },
6608     { "(bad)",          { XX } },
6609     { "(bad)",          { XX } },
6610     { "(bad)",          { XX } },
6611     { "(bad)",          { XX } },
6612     /* 30 */
6613     { "(bad)",          { XX } },
6614     { "(bad)",          { XX } },
6615     { "(bad)",          { XX } },
6616     { "(bad)",          { XX } },
6617     { "(bad)",          { XX } },
6618     { "(bad)",          { XX } },
6619     { "(bad)",          { XX } },
6620     { "(bad)",          { XX } },
6621     /* 38 */
6622     { "(bad)",          { XX } },
6623     { "(bad)",          { XX } },
6624     { "(bad)",          { XX } },
6625     { "(bad)",          { XX } },
6626     { "(bad)",          { XX } },
6627     { "(bad)",          { XX } },
6628     { "(bad)",          { XX } },
6629     { "(bad)",          { XX } },
6630     /* 40 */
6631     { "protb",          { XM, EXq, Ib } },
6632     { "protw",          { XM, EXq, Ib } },
6633     { "protd",          { XM, EXq, Ib } },
6634     { "protq",          { XM, EXq, Ib } },
6635     { "pshlb",          { XM, EXq, Ib } },
6636     { "pshlw",          { XM, EXq, Ib } },
6637     { "pshld",          { XM, EXq, Ib } },
6638     { "pshlq",          { XM, EXq, Ib } },
6639     /* 48 */
6640     { "pshab",          { XM, EXq, Ib } },
6641     { "pshaw",          { XM, EXq, Ib } },
6642     { "pshad",          { XM, EXq, Ib } },
6643     { "pshaq",          { XM, EXq, Ib } },
6644     { "(bad)",          { XX } },
6645     { "(bad)",          { XX } },
6646     { "(bad)",          { XX } },
6647     { "(bad)",          { XX } },
6648     /* 50 */
6649     { "(bad)",          { XX } },
6650     { "(bad)",          { XX } },
6651     { "(bad)",          { XX } },
6652     { "(bad)",          { XX } },
6653     { "(bad)",          { XX } },
6654     { "(bad)",          { XX } },
6655     { "(bad)",          { XX } },
6656     { "(bad)",          { XX } },
6657     /* 58 */
6658     { "(bad)",          { XX } },
6659     { "(bad)",          { XX } },
6660     { "(bad)",          { XX } },
6661     { "(bad)",          { XX } },
6662     { "(bad)",          { XX } },
6663     { "(bad)",          { XX } },
6664     { "(bad)",          { XX } },
6665     { "(bad)",          { XX } },
6666     /* 60 */
6667     { "(bad)",          { XX } },
6668     { "(bad)",          { XX } },
6669     { "(bad)",          { XX } },
6670     { "(bad)",          { XX } },
6671     { "(bad)",          { XX } },
6672     { "(bad)",          { XX } },
6673     { "(bad)",          { XX } },
6674     { "(bad)",          { XX } },
6675     /* 68 */
6676     { "(bad)",          { XX } },
6677     { "(bad)",          { XX } },
6678     { "(bad)",          { XX } },
6679     { "(bad)",          { XX } },
6680     { "(bad)",          { XX } },
6681     { "(bad)",          { XX } },
6682     { "(bad)",          { XX } },
6683     { "(bad)",          { XX } },
6684     /* 70 */
6685     { "(bad)",          { XX } },
6686     { "(bad)",          { XX } },
6687     { "(bad)",          { XX } },
6688     { "(bad)",          { XX } },
6689     { "(bad)",          { XX } },
6690     { "(bad)",          { XX } },
6691     { "(bad)",          { XX } },
6692     { "(bad)",          { XX } },
6693     /* 78 */
6694     { "(bad)",          { XX } },
6695     { "(bad)",          { XX } },
6696     { "(bad)",          { XX } },
6697     { "(bad)",          { XX } },
6698     { "(bad)",          { XX } },
6699     { "(bad)",          { XX } },
6700     { "(bad)",          { XX } },
6701     { "(bad)",          { XX } },
6702     /* 80 */
6703     { "(bad)",          { XX } },
6704     { "(bad)",          { XX } },
6705     { "(bad)",          { XX } },
6706     { "(bad)",          { XX } },
6707     { "(bad)",          { XX } },
6708     { "(bad)",          { XX } },
6709     { "(bad)",          { XX } },
6710     { "(bad)",          { XX } },
6711     /* 88 */
6712     { "(bad)",          { XX } },
6713     { "(bad)",          { XX } },
6714     { "(bad)",          { XX } },
6715     { "(bad)",          { XX } },
6716     { "(bad)",          { XX } },
6717     { "(bad)",          { XX } },
6718     { "(bad)",          { XX } },
6719     { "(bad)",          { XX } },
6720     /* 90 */
6721     { "(bad)",          { XX } },
6722     { "(bad)",          { XX } },
6723     { "(bad)",          { XX } },
6724     { "(bad)",          { XX } },
6725     { "(bad)",          { XX } },
6726     { "(bad)",          { XX } },
6727     { "(bad)",          { XX } },
6728     { "(bad)",          { XX } },
6729     /* 98 */
6730     { "(bad)",          { XX } },
6731     { "(bad)",          { XX } },
6732     { "(bad)",          { XX } },
6733     { "(bad)",          { XX } },
6734     { "(bad)",          { XX } },
6735     { "(bad)",          { XX } },
6736     { "(bad)",          { XX } },
6737     { "(bad)",          { XX } },
6738     /* a0 */
6739     { "(bad)",          { XX } },
6740     { "(bad)",          { XX } },
6741     { "(bad)",          { XX } },
6742     { "(bad)",          { XX } },
6743     { "(bad)",          { XX } },
6744     { "(bad)",          { XX } },
6745     { "(bad)",          { XX } },
6746     { "(bad)",          { XX } },
6747     /* a8 */
6748     { "(bad)",          { XX } },
6749     { "(bad)",          { XX } },
6750     { "(bad)",          { XX } },
6751     { "(bad)",          { XX } },
6752     { "(bad)",          { XX } },
6753     { "(bad)",          { XX } },
6754     { "(bad)",          { XX } },
6755     { "(bad)",          { XX } },
6756     /* b0 */
6757     { "(bad)",          { XX } },
6758     { "(bad)",          { XX } },
6759     { "(bad)",          { XX } },
6760     { "(bad)",          { XX } },
6761     { "(bad)",          { XX } },
6762     { "(bad)",          { XX } },
6763     { "(bad)",          { XX } },
6764     { "(bad)",          { XX } },
6765     /* b8 */
6766     { "(bad)",          { XX } },
6767     { "(bad)",          { XX } },
6768     { "(bad)",          { XX } },
6769     { "(bad)",          { XX } },
6770     { "(bad)",          { XX } },
6771     { "(bad)",          { XX } },
6772     { "(bad)",          { XX } },
6773     { "(bad)",          { XX } },
6774     /* c0 */
6775     { "(bad)",          { XX } },
6776     { "(bad)",          { XX } },
6777     { "(bad)",          { XX } },
6778     { "(bad)",          { XX } },
6779     { "(bad)",          { XX } },
6780     { "(bad)",          { XX } },
6781     { "(bad)",          { XX } },
6782     { "(bad)",          { XX } },
6783     /* c8 */
6784     { "(bad)",          { XX } },
6785     { "(bad)",          { XX } },
6786     { "(bad)",          { XX } },
6787     { "(bad)",          { XX } },
6788     { "(bad)",          { XX } },
6789     { "(bad)",          { XX } },
6790     { "(bad)",          { XX } },
6791     { "(bad)",          { XX } },
6792     /* d0 */
6793     { "(bad)",          { XX } },
6794     { "(bad)",          { XX } },
6795     { "(bad)",          { XX } },
6796     { "(bad)",          { XX } },
6797     { "(bad)",          { XX } },
6798     { "(bad)",          { XX } },
6799     { "(bad)",          { XX } },
6800     { "(bad)",          { XX } },
6801     /* d8 */
6802     { "(bad)",          { XX } },
6803     { "(bad)",          { XX } },
6804     { "(bad)",          { XX } },
6805     { "(bad)",          { XX } },
6806     { "(bad)",          { XX } },
6807     { "(bad)",          { XX } },
6808     { "(bad)",          { XX } },
6809     { "(bad)",          { XX } },
6810     /* e0 */
6811     { "(bad)",          { XX } },
6812     { "(bad)",          { XX } },
6813     { "(bad)",          { XX } },
6814     { "(bad)",          { XX } },
6815     { "(bad)",          { XX } },
6816     { "(bad)",          { XX } },
6817     { "(bad)",          { XX } },
6818     { "(bad)",          { XX } },
6819     /* e8 */
6820     { "(bad)",          { XX } },
6821     { "(bad)",          { XX } },
6822     { "(bad)",          { XX } },
6823     { "(bad)",          { XX } },
6824     { "(bad)",          { XX } },
6825     { "(bad)",          { XX } },
6826     { "(bad)",          { XX } },
6827     { "(bad)",          { XX } },
6828     /* f0 */
6829     { "(bad)",          { XX } },
6830     { "(bad)",          { XX } },
6831     { "(bad)",          { XX } },
6832     { "(bad)",          { XX } },
6833     { "(bad)",          { XX } },
6834     { "(bad)",          { XX } },
6835     { "(bad)",          { XX } },
6836     { "(bad)",          { XX } },
6837     /* f8 */
6838     { "(bad)",          { XX } },
6839     { "(bad)",          { XX } },
6840     { "(bad)",          { XX } },
6841     { "(bad)",          { XX } },
6842     { "(bad)",          { XX } },
6843     { "(bad)",          { XX } },
6844     { "(bad)",          { XX } },
6845     { "(bad)",          { XX } },
6846   },
6847 };
6848
6849 static const struct dis386 vex_table[][256] = {
6850   /* VEX_0F */
6851   {
6852     /* 00 */
6853     { "(bad)",          { XX } },
6854     { "(bad)",          { XX } },
6855     { "(bad)",          { XX } },
6856     { "(bad)",          { XX } },
6857     { "(bad)",          { XX } },
6858     { "(bad)",          { XX } },
6859     { "(bad)",          { XX } },
6860     { "(bad)",          { XX } },
6861     /* 08 */
6862     { "(bad)",          { XX } },
6863     { "(bad)",          { XX } },
6864     { "(bad)",          { XX } },
6865     { "(bad)",          { XX } },
6866     { "(bad)",          { XX } },
6867     { "(bad)",          { XX } },
6868     { "(bad)",          { XX } },
6869     { "(bad)",          { XX } },
6870     /* 10 */
6871     { PREFIX_TABLE (PREFIX_VEX_10) },
6872     { PREFIX_TABLE (PREFIX_VEX_11) },
6873     { PREFIX_TABLE (PREFIX_VEX_12) },
6874     { MOD_TABLE (MOD_VEX_13) },
6875     { "vunpcklpX",      { XM, Vex, EXx } },
6876     { "vunpckhpX",      { XM, Vex, EXx } },
6877     { PREFIX_TABLE (PREFIX_VEX_16) },
6878     { MOD_TABLE (MOD_VEX_17) },
6879     /* 18 */
6880     { "(bad)",          { XX } },
6881     { "(bad)",          { XX } },
6882     { "(bad)",          { XX } },
6883     { "(bad)",          { XX } },
6884     { "(bad)",          { XX } },
6885     { "(bad)",          { XX } },
6886     { "(bad)",          { XX } },
6887     { "(bad)",          { XX } },
6888     /* 20 */
6889     { "(bad)",          { XX } },
6890     { "(bad)",          { XX } },
6891     { "(bad)",          { XX } },
6892     { "(bad)",          { XX } },
6893     { "(bad)",          { XX } },
6894     { "(bad)",          { XX } },
6895     { "(bad)",          { XX } },
6896     { "(bad)",          { XX } },
6897     /* 28 */
6898     { "vmovapX",        { XM, EXx } },
6899     { "vmovapX",        { EXx, XM } },
6900     { PREFIX_TABLE (PREFIX_VEX_2A) },
6901     { MOD_TABLE (MOD_VEX_2B) },
6902     { PREFIX_TABLE (PREFIX_VEX_2C) },
6903     { PREFIX_TABLE (PREFIX_VEX_2D) },
6904     { PREFIX_TABLE (PREFIX_VEX_2E) },
6905     { PREFIX_TABLE (PREFIX_VEX_2F) },
6906     /* 30 */
6907     { "(bad)",          { XX } },
6908     { "(bad)",          { XX } },
6909     { "(bad)",          { XX } },
6910     { "(bad)",          { XX } },
6911     { "(bad)",          { XX } },
6912     { "(bad)",          { XX } },
6913     { "(bad)",          { XX } },
6914     { "(bad)",          { XX } },
6915     /* 38 */
6916     { "(bad)",          { XX } },
6917     { "(bad)",          { XX } },
6918     { "(bad)",          { XX } },
6919     { "(bad)",          { XX } },
6920     { "(bad)",          { XX } },
6921     { "(bad)",          { XX } },
6922     { "(bad)",          { XX } },
6923     { "(bad)",          { XX } },
6924     /* 40 */
6925     { "(bad)",          { XX } },
6926     { "(bad)",          { XX } },
6927     { "(bad)",          { XX } },
6928     { "(bad)",          { XX } },
6929     { "(bad)",          { XX } },
6930     { "(bad)",          { XX } },
6931     { "(bad)",          { XX } },
6932     { "(bad)",          { XX } },
6933     /* 48 */
6934     { "(bad)",          { XX } },
6935     { "(bad)",          { XX } },
6936     { "(bad)",          { XX } },
6937     { "(bad)",          { XX } },
6938     { "(bad)",          { XX } },
6939     { "(bad)",          { XX } },
6940     { "(bad)",          { XX } },
6941     { "(bad)",          { XX } },
6942     /* 50 */
6943     { MOD_TABLE (MOD_VEX_51) },
6944     { PREFIX_TABLE (PREFIX_VEX_51) },
6945     { PREFIX_TABLE (PREFIX_VEX_52) },
6946     { PREFIX_TABLE (PREFIX_VEX_53) },
6947     { "vandpX",         { XM, Vex, EXx } },
6948     { "vandnpX",        { XM, Vex, EXx } },
6949     { "vorpX",          { XM, Vex, EXx } },
6950     { "vxorpX",         { XM, Vex, EXx } },
6951     /* 58 */
6952     { PREFIX_TABLE (PREFIX_VEX_58) },
6953     { PREFIX_TABLE (PREFIX_VEX_59) },
6954     { PREFIX_TABLE (PREFIX_VEX_5A) },
6955     { PREFIX_TABLE (PREFIX_VEX_5B) },
6956     { PREFIX_TABLE (PREFIX_VEX_5C) },
6957     { PREFIX_TABLE (PREFIX_VEX_5D) },
6958     { PREFIX_TABLE (PREFIX_VEX_5E) },
6959     { PREFIX_TABLE (PREFIX_VEX_5F) },
6960     /* 60 */
6961     { PREFIX_TABLE (PREFIX_VEX_60) },
6962     { PREFIX_TABLE (PREFIX_VEX_61) },
6963     { PREFIX_TABLE (PREFIX_VEX_62) },
6964     { PREFIX_TABLE (PREFIX_VEX_63) },
6965     { PREFIX_TABLE (PREFIX_VEX_64) },
6966     { PREFIX_TABLE (PREFIX_VEX_65) },
6967     { PREFIX_TABLE (PREFIX_VEX_66) },
6968     { PREFIX_TABLE (PREFIX_VEX_67) },
6969     /* 68 */
6970     { PREFIX_TABLE (PREFIX_VEX_68) },
6971     { PREFIX_TABLE (PREFIX_VEX_69) },
6972     { PREFIX_TABLE (PREFIX_VEX_6A) },
6973     { PREFIX_TABLE (PREFIX_VEX_6B) },
6974     { PREFIX_TABLE (PREFIX_VEX_6C) },
6975     { PREFIX_TABLE (PREFIX_VEX_6D) },
6976     { PREFIX_TABLE (PREFIX_VEX_6E) },
6977     { PREFIX_TABLE (PREFIX_VEX_6F) },
6978     /* 70 */
6979     { PREFIX_TABLE (PREFIX_VEX_70) },
6980     { REG_TABLE (REG_VEX_71) },
6981     { REG_TABLE (REG_VEX_72) },
6982     { REG_TABLE (REG_VEX_73) },
6983     { PREFIX_TABLE (PREFIX_VEX_74) },
6984     { PREFIX_TABLE (PREFIX_VEX_75) },
6985     { PREFIX_TABLE (PREFIX_VEX_76) },
6986     { PREFIX_TABLE (PREFIX_VEX_77) },
6987     /* 78 */
6988     { "(bad)",          { XX } },
6989     { "(bad)",          { XX } },
6990     { "(bad)",          { XX } },
6991     { "(bad)",          { XX } },
6992     { PREFIX_TABLE (PREFIX_VEX_7C) },
6993     { PREFIX_TABLE (PREFIX_VEX_7D) },
6994     { PREFIX_TABLE (PREFIX_VEX_7E) },
6995     { PREFIX_TABLE (PREFIX_VEX_7F) },
6996     /* 80 */
6997     { "(bad)",          { XX } },
6998     { "(bad)",          { XX } },
6999     { "(bad)",          { XX } },
7000     { "(bad)",          { XX } },
7001     { "(bad)",          { XX } },
7002     { "(bad)",          { XX } },
7003     { "(bad)",          { XX } },
7004     { "(bad)",          { XX } },
7005     /* 88 */
7006     { "(bad)",          { XX } },
7007     { "(bad)",          { XX } },
7008     { "(bad)",          { XX } },
7009     { "(bad)",          { XX } },
7010     { "(bad)",          { XX } },
7011     { "(bad)",          { XX } },
7012     { "(bad)",          { XX } },
7013     { "(bad)",          { XX } },
7014     /* 90 */
7015     { "(bad)",          { XX } },
7016     { "(bad)",          { XX } },
7017     { "(bad)",          { XX } },
7018     { "(bad)",          { XX } },
7019     { "(bad)",          { XX } },
7020     { "(bad)",          { XX } },
7021     { "(bad)",          { XX } },
7022     { "(bad)",          { XX } },
7023     /* 98 */
7024     { "(bad)",          { XX } },
7025     { "(bad)",          { XX } },
7026     { "(bad)",          { XX } },
7027     { "(bad)",          { XX } },
7028     { "(bad)",          { XX } },
7029     { "(bad)",          { XX } },
7030     { "(bad)",          { XX } },
7031     { "(bad)",          { XX } },
7032     /* a0 */
7033     { "(bad)",          { XX } },
7034     { "(bad)",          { XX } },
7035     { "(bad)",          { XX } },
7036     { "(bad)",          { XX } },
7037     { "(bad)",          { XX } },
7038     { "(bad)",          { XX } },
7039     { "(bad)",          { XX } },
7040     { "(bad)",          { XX } },
7041     /* a8 */
7042     { "(bad)",          { XX } },
7043     { "(bad)",          { XX } },
7044     { "(bad)",          { XX } },
7045     { "(bad)",          { XX } },
7046     { "(bad)",          { XX } },
7047     { "(bad)",          { XX } },
7048     { REG_TABLE (REG_VEX_AE) },
7049     { "(bad)",          { XX } },
7050     /* b0 */
7051     { "(bad)",          { XX } },
7052     { "(bad)",          { XX } },
7053     { "(bad)",          { XX } },
7054     { "(bad)",          { XX } },
7055     { "(bad)",          { XX } },
7056     { "(bad)",          { XX } },
7057     { "(bad)",          { XX } },
7058     { "(bad)",          { XX } },
7059     /* b8 */
7060     { "(bad)",          { XX } },
7061     { "(bad)",          { XX } },
7062     { "(bad)",          { XX } },
7063     { "(bad)",          { XX } },
7064     { "(bad)",          { XX } },
7065     { "(bad)",          { XX } },
7066     { "(bad)",          { XX } },
7067     { "(bad)",          { XX } },
7068     /* c0 */
7069     { "(bad)",          { XX } },
7070     { "(bad)",          { XX } },
7071     { PREFIX_TABLE (PREFIX_VEX_C2) },
7072     { "(bad)",          { XX } },
7073     { PREFIX_TABLE (PREFIX_VEX_C4) },
7074     { PREFIX_TABLE (PREFIX_VEX_C5) },
7075     { "vshufpX",        { XM, Vex, EXx, Ib } },
7076     { "(bad)",          { XX } },
7077     /* c8 */
7078     { "(bad)",          { XX } },
7079     { "(bad)",          { XX } },
7080     { "(bad)",          { XX } },
7081     { "(bad)",          { XX } },
7082     { "(bad)",          { XX } },
7083     { "(bad)",          { XX } },
7084     { "(bad)",          { XX } },
7085     { "(bad)",          { XX } },
7086     /* d0 */
7087     { PREFIX_TABLE (PREFIX_VEX_D0) },
7088     { PREFIX_TABLE (PREFIX_VEX_D1) },
7089     { PREFIX_TABLE (PREFIX_VEX_D2) },
7090     { PREFIX_TABLE (PREFIX_VEX_D3) },
7091     { PREFIX_TABLE (PREFIX_VEX_D4) },
7092     { PREFIX_TABLE (PREFIX_VEX_D5) },
7093     { PREFIX_TABLE (PREFIX_VEX_D6) },
7094     { PREFIX_TABLE (PREFIX_VEX_D7) },
7095     /* d8 */
7096     { PREFIX_TABLE (PREFIX_VEX_D8) },
7097     { PREFIX_TABLE (PREFIX_VEX_D9) },
7098     { PREFIX_TABLE (PREFIX_VEX_DA) },
7099     { PREFIX_TABLE (PREFIX_VEX_DB) },
7100     { PREFIX_TABLE (PREFIX_VEX_DC) },
7101     { PREFIX_TABLE (PREFIX_VEX_DD) },
7102     { PREFIX_TABLE (PREFIX_VEX_DE) },
7103     { PREFIX_TABLE (PREFIX_VEX_DF) },
7104     /* e0 */
7105     { PREFIX_TABLE (PREFIX_VEX_E0) },
7106     { PREFIX_TABLE (PREFIX_VEX_E1) },
7107     { PREFIX_TABLE (PREFIX_VEX_E2) },
7108     { PREFIX_TABLE (PREFIX_VEX_E3) },
7109     { PREFIX_TABLE (PREFIX_VEX_E4) },
7110     { PREFIX_TABLE (PREFIX_VEX_E5) },
7111     { PREFIX_TABLE (PREFIX_VEX_E6) },
7112     { PREFIX_TABLE (PREFIX_VEX_E7) },
7113     /* e8 */
7114     { PREFIX_TABLE (PREFIX_VEX_E8) },
7115     { PREFIX_TABLE (PREFIX_VEX_E9) },
7116     { PREFIX_TABLE (PREFIX_VEX_EA) },
7117     { PREFIX_TABLE (PREFIX_VEX_EB) },
7118     { PREFIX_TABLE (PREFIX_VEX_EC) },
7119     { PREFIX_TABLE (PREFIX_VEX_ED) },
7120     { PREFIX_TABLE (PREFIX_VEX_EE) },
7121     { PREFIX_TABLE (PREFIX_VEX_EF) },
7122     /* f0 */
7123     { PREFIX_TABLE (PREFIX_VEX_F0) },
7124     { PREFIX_TABLE (PREFIX_VEX_F1) },
7125     { PREFIX_TABLE (PREFIX_VEX_F2) },
7126     { PREFIX_TABLE (PREFIX_VEX_F3) },
7127     { PREFIX_TABLE (PREFIX_VEX_F4) },
7128     { PREFIX_TABLE (PREFIX_VEX_F5) },
7129     { PREFIX_TABLE (PREFIX_VEX_F6) },
7130     { PREFIX_TABLE (PREFIX_VEX_F7) },
7131     /* f8 */
7132     { PREFIX_TABLE (PREFIX_VEX_F8) },
7133     { PREFIX_TABLE (PREFIX_VEX_F9) },
7134     { PREFIX_TABLE (PREFIX_VEX_FA) },
7135     { PREFIX_TABLE (PREFIX_VEX_FB) },
7136     { PREFIX_TABLE (PREFIX_VEX_FC) },
7137     { PREFIX_TABLE (PREFIX_VEX_FD) },
7138     { PREFIX_TABLE (PREFIX_VEX_FE) },
7139     { "(bad)",          { XX } },
7140   },
7141   /* VEX_0F38 */
7142   {
7143     /* 00 */
7144     { PREFIX_TABLE (PREFIX_VEX_3800) },
7145     { PREFIX_TABLE (PREFIX_VEX_3801) },
7146     { PREFIX_TABLE (PREFIX_VEX_3802) },
7147     { PREFIX_TABLE (PREFIX_VEX_3803) },
7148     { PREFIX_TABLE (PREFIX_VEX_3804) },
7149     { PREFIX_TABLE (PREFIX_VEX_3805) },
7150     { PREFIX_TABLE (PREFIX_VEX_3806) },
7151     { PREFIX_TABLE (PREFIX_VEX_3807) },
7152     /* 08 */
7153     { PREFIX_TABLE (PREFIX_VEX_3808) },
7154     { PREFIX_TABLE (PREFIX_VEX_3809) },
7155     { PREFIX_TABLE (PREFIX_VEX_380A) },
7156     { PREFIX_TABLE (PREFIX_VEX_380B) },
7157     { PREFIX_TABLE (PREFIX_VEX_380C) },
7158     { PREFIX_TABLE (PREFIX_VEX_380D) },
7159     { PREFIX_TABLE (PREFIX_VEX_380E) },
7160     { PREFIX_TABLE (PREFIX_VEX_380F) },
7161     /* 10 */
7162     { "(bad)",          { XX } },
7163     { "(bad)",          { XX } },
7164     { "(bad)",          { XX } },
7165     { "(bad)",          { XX } },
7166     { "(bad)",          { XX } },
7167     { "(bad)",          { XX } },
7168     { "(bad)",          { XX } },
7169     { PREFIX_TABLE (PREFIX_VEX_3817) },
7170     /* 18 */
7171     { PREFIX_TABLE (PREFIX_VEX_3818) },
7172     { PREFIX_TABLE (PREFIX_VEX_3819) },
7173     { PREFIX_TABLE (PREFIX_VEX_381A) },
7174     { "(bad)",          { XX } },
7175     { PREFIX_TABLE (PREFIX_VEX_381C) },
7176     { PREFIX_TABLE (PREFIX_VEX_381D) },
7177     { PREFIX_TABLE (PREFIX_VEX_381E) },
7178     { "(bad)",          { XX } },
7179     /* 20 */
7180     { PREFIX_TABLE (PREFIX_VEX_3820) },
7181     { PREFIX_TABLE (PREFIX_VEX_3821) },
7182     { PREFIX_TABLE (PREFIX_VEX_3822) },
7183     { PREFIX_TABLE (PREFIX_VEX_3823) },
7184     { PREFIX_TABLE (PREFIX_VEX_3824) },
7185     { PREFIX_TABLE (PREFIX_VEX_3825) },
7186     { "(bad)",          { XX } },
7187     { "(bad)",          { XX } },
7188     /* 28 */
7189     { PREFIX_TABLE (PREFIX_VEX_3828) },
7190     { PREFIX_TABLE (PREFIX_VEX_3829) },
7191     { PREFIX_TABLE (PREFIX_VEX_382A) },
7192     { PREFIX_TABLE (PREFIX_VEX_382B) },
7193     { PREFIX_TABLE (PREFIX_VEX_382C) },
7194     { PREFIX_TABLE (PREFIX_VEX_382D) },
7195     { PREFIX_TABLE (PREFIX_VEX_382E) },
7196     { PREFIX_TABLE (PREFIX_VEX_382F) },
7197     /* 30 */
7198     { PREFIX_TABLE (PREFIX_VEX_3830) },
7199     { PREFIX_TABLE (PREFIX_VEX_3831) },
7200     { PREFIX_TABLE (PREFIX_VEX_3832) },
7201     { PREFIX_TABLE (PREFIX_VEX_3833) },
7202     { PREFIX_TABLE (PREFIX_VEX_3834) },
7203     { PREFIX_TABLE (PREFIX_VEX_3835) },
7204     { "(bad)",          { XX } },
7205     { PREFIX_TABLE (PREFIX_VEX_3837) },
7206     /* 38 */
7207     { PREFIX_TABLE (PREFIX_VEX_3838) },
7208     { PREFIX_TABLE (PREFIX_VEX_3839) },
7209     { PREFIX_TABLE (PREFIX_VEX_383A) },
7210     { PREFIX_TABLE (PREFIX_VEX_383B) },
7211     { PREFIX_TABLE (PREFIX_VEX_383C) },
7212     { PREFIX_TABLE (PREFIX_VEX_383D) },
7213     { PREFIX_TABLE (PREFIX_VEX_383E) },
7214     { PREFIX_TABLE (PREFIX_VEX_383F) },
7215     /* 40 */
7216     { PREFIX_TABLE (PREFIX_VEX_3840) },
7217     { PREFIX_TABLE (PREFIX_VEX_3841) },
7218     { "(bad)",          { XX } },
7219     { "(bad)",          { XX } },
7220     { "(bad)",          { XX } },
7221     { "(bad)",          { XX } },
7222     { "(bad)",          { XX } },
7223     { "(bad)",          { XX } },
7224     /* 48 */
7225     { "(bad)",          { XX } },
7226     { "(bad)",          { XX } },
7227     { "(bad)",          { XX } },
7228     { "(bad)",          { XX } },
7229     { "(bad)",          { XX } },
7230     { "(bad)",          { XX } },
7231     { "(bad)",          { XX } },
7232     { "(bad)",          { XX } },
7233     /* 50 */
7234     { "(bad)",          { XX } },
7235     { "(bad)",          { XX } },
7236     { "(bad)",          { XX } },
7237     { "(bad)",          { XX } },
7238     { "(bad)",          { XX } },
7239     { "(bad)",          { XX } },
7240     { "(bad)",          { XX } },
7241     { "(bad)",          { XX } },
7242     /* 58 */
7243     { "(bad)",          { XX } },
7244     { "(bad)",          { XX } },
7245     { "(bad)",          { XX } },
7246     { "(bad)",          { XX } },
7247     { "(bad)",          { XX } },
7248     { "(bad)",          { XX } },
7249     { "(bad)",          { XX } },
7250     { "(bad)",          { XX } },
7251     /* 60 */
7252     { "(bad)",          { XX } },
7253     { "(bad)",          { XX } },
7254     { "(bad)",          { XX } },
7255     { "(bad)",          { XX } },
7256     { "(bad)",          { XX } },
7257     { "(bad)",          { XX } },
7258     { "(bad)",          { XX } },
7259     { "(bad)",          { XX } },
7260     /* 68 */
7261     { "(bad)",          { XX } },
7262     { "(bad)",          { XX } },
7263     { "(bad)",          { XX } },
7264     { "(bad)",          { XX } },
7265     { "(bad)",          { XX } },
7266     { "(bad)",          { XX } },
7267     { "(bad)",          { XX } },
7268     { "(bad)",          { XX } },
7269     /* 70 */
7270     { "(bad)",          { XX } },
7271     { "(bad)",          { XX } },
7272     { "(bad)",          { XX } },
7273     { "(bad)",          { XX } },
7274     { "(bad)",          { XX } },
7275     { "(bad)",          { XX } },
7276     { "(bad)",          { XX } },
7277     { "(bad)",          { XX } },
7278     /* 78 */
7279     { "(bad)",          { XX } },
7280     { "(bad)",          { XX } },
7281     { "(bad)",          { XX } },
7282     { "(bad)",          { XX } },
7283     { "(bad)",          { XX } },
7284     { "(bad)",          { XX } },
7285     { "(bad)",          { XX } },
7286     { "(bad)",          { XX } },
7287     /* 80 */
7288     { "(bad)",          { XX } },
7289     { "(bad)",          { XX } },
7290     { "(bad)",          { XX } },
7291     { "(bad)",          { XX } },
7292     { "(bad)",          { XX } },
7293     { "(bad)",          { XX } },
7294     { "(bad)",          { XX } },
7295     { "(bad)",          { XX } },
7296     /* 88 */
7297     { "(bad)",          { XX } },
7298     { "(bad)",          { XX } },
7299     { "(bad)",          { XX } },
7300     { "(bad)",          { XX } },
7301     { "(bad)",          { XX } },
7302     { "(bad)",          { XX } },
7303     { "(bad)",          { XX } },
7304     { "(bad)",          { XX } },
7305     /* 90 */
7306     { "(bad)",          { XX } },
7307     { "(bad)",          { XX } },
7308     { "(bad)",          { XX } },
7309     { "(bad)",          { XX } },
7310     { "(bad)",          { XX } },
7311     { "(bad)",          { XX } },
7312     { "(bad)",          { XX } },
7313     { "(bad)",          { XX } },
7314     /* 98 */
7315     { "(bad)",          { XX } },
7316     { "(bad)",          { XX } },
7317     { "(bad)",          { XX } },
7318     { "(bad)",          { XX } },
7319     { "(bad)",          { XX } },
7320     { "(bad)",          { XX } },
7321     { "(bad)",          { XX } },
7322     { "(bad)",          { XX } },
7323     /* a0 */
7324     { "(bad)",          { XX } },
7325     { "(bad)",          { XX } },
7326     { "(bad)",          { XX } },
7327     { "(bad)",          { XX } },
7328     { "(bad)",          { XX } },
7329     { "(bad)",          { XX } },
7330     { "(bad)",          { XX } },
7331     { "(bad)",          { XX } },
7332     /* a8 */
7333     { "(bad)",          { XX } },
7334     { "(bad)",          { XX } },
7335     { "(bad)",          { XX } },
7336     { "(bad)",          { XX } },
7337     { "(bad)",          { XX } },
7338     { "(bad)",          { XX } },
7339     { "(bad)",          { XX } },
7340     { "(bad)",          { XX } },
7341     /* b0 */
7342     { "(bad)",          { XX } },
7343     { "(bad)",          { XX } },
7344     { "(bad)",          { XX } },
7345     { "(bad)",          { XX } },
7346     { "(bad)",          { XX } },
7347     { "(bad)",          { XX } },
7348     { "(bad)",          { XX } },
7349     { "(bad)",          { XX } },
7350     /* b8 */
7351     { "(bad)",          { XX } },
7352     { "(bad)",          { XX } },
7353     { "(bad)",          { XX } },
7354     { "(bad)",          { XX } },
7355     { "(bad)",          { XX } },
7356     { "(bad)",          { XX } },
7357     { "(bad)",          { XX } },
7358     { "(bad)",          { XX } },
7359     /* c0 */
7360     { "(bad)",          { XX } },
7361     { "(bad)",          { XX } },
7362     { "(bad)",          { XX } },
7363     { "(bad)",          { XX } },
7364     { "(bad)",          { XX } },
7365     { "(bad)",          { XX } },
7366     { "(bad)",          { XX } },
7367     { "(bad)",          { XX } },
7368     /* c8 */
7369     { "(bad)",          { XX } },
7370     { "(bad)",          { XX } },
7371     { "(bad)",          { XX } },
7372     { "(bad)",          { XX } },
7373     { "(bad)",          { XX } },
7374     { "(bad)",          { XX } },
7375     { "(bad)",          { XX } },
7376     { "(bad)",          { XX } },
7377     /* d0 */
7378     { "(bad)",          { XX } },
7379     { "(bad)",          { XX } },
7380     { "(bad)",          { XX } },
7381     { "(bad)",          { XX } },
7382     { "(bad)",          { XX } },
7383     { "(bad)",          { XX } },
7384     { "(bad)",          { XX } },
7385     { "(bad)",          { XX } },
7386     /* d8 */
7387     { "(bad)",          { XX } },
7388     { "(bad)",          { XX } },
7389     { "(bad)",          { XX } },
7390     { "(bad)",          { XX } },
7391     { "(bad)",          { XX } },
7392     { "(bad)",          { XX } },
7393     { "(bad)",          { XX } },
7394     { "(bad)",          { XX } },
7395     /* e0 */
7396     { "(bad)",          { XX } },
7397     { "(bad)",          { XX } },
7398     { "(bad)",          { XX } },
7399     { "(bad)",          { XX } },
7400     { "(bad)",          { XX } },
7401     { "(bad)",          { XX } },
7402     { "(bad)",          { XX } },
7403     { "(bad)",          { XX } },
7404     /* e8 */
7405     { "(bad)",          { XX } },
7406     { "(bad)",          { XX } },
7407     { "(bad)",          { XX } },
7408     { "(bad)",          { XX } },
7409     { "(bad)",          { XX } },
7410     { "(bad)",          { XX } },
7411     { "(bad)",          { XX } },
7412     { "(bad)",          { XX } },
7413     /* f0 */
7414     { "(bad)",          { XX } },
7415     { "(bad)",          { XX } },
7416     { "(bad)",          { XX } },
7417     { "(bad)",          { XX } },
7418     { "(bad)",          { XX } },
7419     { "(bad)",          { XX } },
7420     { "(bad)",          { XX } },
7421     { "(bad)",          { XX } },
7422     /* f8 */
7423     { "(bad)",          { XX } },
7424     { "(bad)",          { XX } },
7425     { "(bad)",          { XX } },
7426     { "(bad)",          { XX } },
7427     { "(bad)",          { XX } },
7428     { "(bad)",          { XX } },
7429     { "(bad)",          { XX } },
7430     { "(bad)",          { XX } },
7431   },
7432   /* VEX_0F3A */
7433   {
7434     /* 00 */
7435     { "(bad)",          { XX } },
7436     { "(bad)",          { XX } },
7437     { "(bad)",          { XX } },
7438     { "(bad)",          { XX } },
7439     { PREFIX_TABLE (PREFIX_VEX_3A04) },
7440     { PREFIX_TABLE (PREFIX_VEX_3A05) },
7441     { PREFIX_TABLE (PREFIX_VEX_3A06) },
7442     { "(bad)",          { XX } },
7443     /* 08 */
7444     { PREFIX_TABLE (PREFIX_VEX_3A08) },
7445     { PREFIX_TABLE (PREFIX_VEX_3A09) },
7446     { PREFIX_TABLE (PREFIX_VEX_3A0A) },
7447     { PREFIX_TABLE (PREFIX_VEX_3A0B) },
7448     { PREFIX_TABLE (PREFIX_VEX_3A0C) },
7449     { PREFIX_TABLE (PREFIX_VEX_3A0D) },
7450     { PREFIX_TABLE (PREFIX_VEX_3A0E) },
7451     { PREFIX_TABLE (PREFIX_VEX_3A0F) },
7452     /* 10 */
7453     { "(bad)",          { XX } },
7454     { "(bad)",          { XX } },
7455     { "(bad)",          { XX } },
7456     { "(bad)",          { XX } },
7457     { PREFIX_TABLE (PREFIX_VEX_3A14) },
7458     { PREFIX_TABLE (PREFIX_VEX_3A15) },
7459     { PREFIX_TABLE (PREFIX_VEX_3A16) },
7460     { PREFIX_TABLE (PREFIX_VEX_3A17) },
7461     /* 18 */
7462     { PREFIX_TABLE (PREFIX_VEX_3A18) },
7463     { PREFIX_TABLE (PREFIX_VEX_3A19) },
7464     { "(bad)",          { XX } },
7465     { "(bad)",          { XX } },
7466     { "(bad)",          { XX } },
7467     { "(bad)",          { XX } },
7468     { "(bad)",          { XX } },
7469     { "(bad)",          { XX } },
7470     /* 20 */
7471     { PREFIX_TABLE (PREFIX_VEX_3A20) },
7472     { PREFIX_TABLE (PREFIX_VEX_3A21) },
7473     { PREFIX_TABLE (PREFIX_VEX_3A22) },
7474     { "(bad)",          { XX } },
7475     { "(bad)",          { XX } },
7476     { "(bad)",          { XX } },
7477     { "(bad)",          { XX } },
7478     { "(bad)",          { XX } },
7479     /* 28 */
7480     { "(bad)",          { XX } },
7481     { "(bad)",          { XX } },
7482     { "(bad)",          { XX } },
7483     { "(bad)",          { XX } },
7484     { "(bad)",          { XX } },
7485     { "(bad)",          { XX } },
7486     { "(bad)",          { XX } },
7487     { "(bad)",          { XX } },
7488     /* 30 */
7489     { "(bad)",          { XX } },
7490     { "(bad)",          { XX } },
7491     { "(bad)",          { XX } },
7492     { "(bad)",          { XX } },
7493     { "(bad)",          { XX } },
7494     { "(bad)",          { XX } },
7495     { "(bad)",          { XX } },
7496     { "(bad)",          { XX } },
7497     /* 38 */
7498     { "(bad)",          { XX } },
7499     { "(bad)",          { XX } },
7500     { "(bad)",          { XX } },
7501     { "(bad)",          { XX } },
7502     { "(bad)",          { XX } },
7503     { "(bad)",          { XX } },
7504     { "(bad)",          { XX } },
7505     { "(bad)",          { XX } },
7506     /* 40 */
7507     { PREFIX_TABLE (PREFIX_VEX_3A40) },
7508     { PREFIX_TABLE (PREFIX_VEX_3A41) },
7509     { PREFIX_TABLE (PREFIX_VEX_3A42) },
7510     { "(bad)",          { XX } },
7511     { "(bad)",          { XX } },
7512     { "(bad)",          { XX } },
7513     { "(bad)",          { XX } },
7514     { "(bad)",          { XX } },
7515     /* 48 */
7516     { PREFIX_TABLE (PREFIX_VEX_3A48) },
7517     { PREFIX_TABLE (PREFIX_VEX_3A49) },
7518     { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7519     { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7520     { PREFIX_TABLE (PREFIX_VEX_3A4C) },
7521     { "(bad)",          { XX } },
7522     { "(bad)",          { XX } },
7523     { "(bad)",          { XX } },
7524     /* 50 */
7525     { "(bad)",          { XX } },
7526     { "(bad)",          { XX } },
7527     { "(bad)",          { XX } },
7528     { "(bad)",          { XX } },
7529     { "(bad)",          { XX } },
7530     { "(bad)",          { XX } },
7531     { "(bad)",          { XX } },
7532     { "(bad)",          { XX } },
7533     /* 58 */
7534     { "(bad)",          { XX } },
7535     { "(bad)",          { XX } },
7536     { "(bad)",          { XX } },
7537     { "(bad)",          { XX } },
7538     { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7539     { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7540     { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7541     { PREFIX_TABLE (PREFIX_VEX_3A5F) },
7542     /* 60 */
7543     { PREFIX_TABLE (PREFIX_VEX_3A60) },
7544     { PREFIX_TABLE (PREFIX_VEX_3A61) },
7545     { PREFIX_TABLE (PREFIX_VEX_3A62) },
7546     { PREFIX_TABLE (PREFIX_VEX_3A63) },
7547     { "(bad)",          { XX } },
7548     { "(bad)",          { XX } },
7549     { "(bad)",          { XX } },
7550     { "(bad)",          { XX } },
7551     /* 68 */
7552     { PREFIX_TABLE (PREFIX_VEX_3A68) },
7553     { PREFIX_TABLE (PREFIX_VEX_3A69) },
7554     { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7555     { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7556     { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7557     { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7558     { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7559     { PREFIX_TABLE (PREFIX_VEX_3A6F) },
7560     /* 70 */
7561     { "(bad)",          { XX } },
7562     { "(bad)",          { XX } },
7563     { "(bad)",          { XX } },
7564     { "(bad)",          { XX } },
7565     { "(bad)",          { XX } },
7566     { "(bad)",          { XX } },
7567     { "(bad)",          { XX } },
7568     { "(bad)",          { XX } },
7569     /* 78 */
7570     { PREFIX_TABLE (PREFIX_VEX_3A78) },
7571     { PREFIX_TABLE (PREFIX_VEX_3A79) },
7572     { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7573     { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7574     { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7575     { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7576     { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7577     { PREFIX_TABLE (PREFIX_VEX_3A7F) },
7578     /* 80 */
7579     { "(bad)",          { XX } },
7580     { "(bad)",          { XX } },
7581     { "(bad)",          { XX } },
7582     { "(bad)",          { XX } },
7583     { "(bad)",          { XX } },
7584     { "(bad)",          { XX } },
7585     { "(bad)",          { XX } },
7586     { "(bad)",          { XX } },
7587     /* 88 */
7588     { "(bad)",          { XX } },
7589     { "(bad)",          { XX } },
7590     { "(bad)",          { XX } },
7591     { "(bad)",          { XX } },
7592     { "(bad)",          { XX } },
7593     { "(bad)",          { XX } },
7594     { "(bad)",          { XX } },
7595     { "(bad)",          { XX } },
7596     /* 90 */
7597     { "(bad)",          { XX } },
7598     { "(bad)",          { XX } },
7599     { "(bad)",          { XX } },
7600     { "(bad)",          { XX } },
7601     { "(bad)",          { XX } },
7602     { "(bad)",          { XX } },
7603     { "(bad)",          { XX } },
7604     { "(bad)",          { XX } },
7605     /* 98 */
7606     { "(bad)",          { XX } },
7607     { "(bad)",          { XX } },
7608     { "(bad)",          { XX } },
7609     { "(bad)",          { XX } },
7610     { "(bad)",          { XX } },
7611     { "(bad)",          { XX } },
7612     { "(bad)",          { XX } },
7613     { "(bad)",          { XX } },
7614     /* a0 */
7615     { "(bad)",          { XX } },
7616     { "(bad)",          { XX } },
7617     { "(bad)",          { XX } },
7618     { "(bad)",          { XX } },
7619     { "(bad)",          { XX } },
7620     { "(bad)",          { XX } },
7621     { "(bad)",          { XX } },
7622     { "(bad)",          { XX } },
7623     /* a8 */
7624     { "(bad)",          { XX } },
7625     { "(bad)",          { XX } },
7626     { "(bad)",          { XX } },
7627     { "(bad)",          { XX } },
7628     { "(bad)",          { XX } },
7629     { "(bad)",          { XX } },
7630     { "(bad)",          { XX } },
7631     { "(bad)",          { XX } },
7632     /* b0 */
7633     { "(bad)",          { XX } },
7634     { "(bad)",          { XX } },
7635     { "(bad)",          { XX } },
7636     { "(bad)",          { XX } },
7637     { "(bad)",          { XX } },
7638     { "(bad)",          { XX } },
7639     { "(bad)",          { XX } },
7640     { "(bad)",          { XX } },
7641     /* b8 */
7642     { "(bad)",          { XX } },
7643     { "(bad)",          { XX } },
7644     { "(bad)",          { XX } },
7645     { "(bad)",          { XX } },
7646     { "(bad)",          { XX } },
7647     { "(bad)",          { XX } },
7648     { "(bad)",          { XX } },
7649     { "(bad)",          { XX } },
7650     /* c0 */
7651     { "(bad)",          { XX } },
7652     { "(bad)",          { XX } },
7653     { "(bad)",          { XX } },
7654     { "(bad)",          { XX } },
7655     { "(bad)",          { XX } },
7656     { "(bad)",          { XX } },
7657     { "(bad)",          { XX } },
7658     { "(bad)",          { XX } },
7659     /* c8 */
7660     { "(bad)",          { XX } },
7661     { "(bad)",          { XX } },
7662     { "(bad)",          { XX } },
7663     { "(bad)",          { XX } },
7664     { "(bad)",          { XX } },
7665     { "(bad)",          { XX } },
7666     { "(bad)",          { XX } },
7667     { "(bad)",          { XX } },
7668     /* d0 */
7669     { "(bad)",          { XX } },
7670     { "(bad)",          { XX } },
7671     { "(bad)",          { XX } },
7672     { "(bad)",          { XX } },
7673     { "(bad)",          { XX } },
7674     { "(bad)",          { XX } },
7675     { "(bad)",          { XX } },
7676     { "(bad)",          { XX } },
7677     /* d8 */
7678     { "(bad)",          { XX } },
7679     { "(bad)",          { XX } },
7680     { "(bad)",          { XX } },
7681     { "(bad)",          { XX } },
7682     { "(bad)",          { XX } },
7683     { "(bad)",          { XX } },
7684     { "(bad)",          { XX } },
7685     { "(bad)",          { XX } },
7686     /* e0 */
7687     { "(bad)",          { XX } },
7688     { "(bad)",          { XX } },
7689     { "(bad)",          { XX } },
7690     { "(bad)",          { XX } },
7691     { "(bad)",          { XX } },
7692     { "(bad)",          { XX } },
7693     { "(bad)",          { XX } },
7694     { "(bad)",          { XX } },
7695     /* e8 */
7696     { "(bad)",          { XX } },
7697     { "(bad)",          { XX } },
7698     { "(bad)",          { XX } },
7699     { "(bad)",          { XX } },
7700     { "(bad)",          { XX } },
7701     { "(bad)",          { XX } },
7702     { "(bad)",          { XX } },
7703     { "(bad)",          { XX } },
7704     /* f0 */
7705     { "(bad)",          { XX } },
7706     { "(bad)",          { XX } },
7707     { "(bad)",          { XX } },
7708     { "(bad)",          { XX } },
7709     { "(bad)",          { XX } },
7710     { "(bad)",          { XX } },
7711     { "(bad)",          { XX } },
7712     { "(bad)",          { XX } },
7713     /* f8 */
7714     { "(bad)",          { XX } },
7715     { "(bad)",          { XX } },
7716     { "(bad)",          { XX } },
7717     { "(bad)",          { XX } },
7718     { "(bad)",          { XX } },
7719     { "(bad)",          { XX } },
7720     { "(bad)",          { XX } },
7721     { "(bad)",          { XX } },
7722   },
7723 };
7724
7725 static const struct dis386 vex_len_table[][2] = {
7726   /* VEX_LEN_10_P_1 */
7727   {
7728     { "vmovss",         { XMVex, Vex128, EXd } },
7729     { "(bad)",          { XX } },
7730   },
7731
7732   /* VEX_LEN_10_P_3 */
7733   {
7734     { "vmovsd",         { XMVex, Vex128, EXq } },
7735     { "(bad)",          { XX } },
7736   },
7737
7738   /* VEX_LEN_11_P_1 */
7739   {
7740     { "vmovss",         { EXdVex, Vex128, XM } },
7741     { "(bad)",          { XX } },
7742   },
7743
7744   /* VEX_LEN_11_P_3 */
7745   {
7746     { "vmovsd",         { EXqVex, Vex128, XM } },
7747     { "(bad)",          { XX } },
7748   },
7749
7750   /* VEX_LEN_12_P_0_M_0 */
7751   {
7752     { "vmovlps",        { XM, Vex128, EXq } },
7753     { "(bad)",          { XX } },
7754   },
7755
7756   /* VEX_LEN_12_P_0_M_1 */
7757   {
7758     { "vmovhlps",       { XM, Vex128, EXq } },
7759     { "(bad)",          { XX } },
7760   },
7761
7762   /* VEX_LEN_12_P_2 */
7763   {
7764     { "vmovlpd",        { XM, Vex128, EXq } },
7765     { "(bad)",          { XX } },
7766   },
7767
7768   /* VEX_LEN_13_M_0 */
7769   {
7770     { "vmovlpX",        { EXq, XM } },
7771     { "(bad)",          { XX } },
7772   },
7773
7774   /* VEX_LEN_16_P_0_M_0 */
7775   {
7776     { "vmovhps",        { XM, Vex128, EXq } },
7777     { "(bad)",          { XX } },
7778   },
7779
7780   /* VEX_LEN_16_P_0_M_1 */
7781   {
7782     { "vmovlhps",       { XM, Vex128, EXq } },
7783     { "(bad)",          { XX } },
7784   },
7785
7786   /* VEX_LEN_16_P_2 */
7787   {
7788     { "vmovhpd",        { XM, Vex128, EXq } },
7789     { "(bad)",          { XX } },
7790   },
7791
7792   /* VEX_LEN_17_M_0 */
7793   {
7794     { "vmovhpX",        { EXq, XM } },
7795     { "(bad)",          { XX } },
7796   },
7797
7798   /* VEX_LEN_2A_P_1 */
7799   {
7800     { "vcvtsi2ss%LQ",   { XM, Vex128, Ev } },
7801     { "(bad)",          { XX } },
7802   },
7803
7804   /* VEX_LEN_2A_P_3 */
7805   {
7806     { "vcvtsi2sd%LQ",   { XM, Vex128, Ev } },
7807     { "(bad)",          { XX } },
7808   },
7809
7810   /* VEX_LEN_2B_M_0 */
7811   {
7812     { "vmovntpX",       { Mx, XM } },
7813     { "(bad)",          { XX } },
7814   },
7815
7816   /* VEX_LEN_2C_P_1 */
7817   {
7818     { "vcvttss2siY",    { Gv, EXd } },
7819     { "(bad)",          { XX } },
7820   },
7821
7822   /* VEX_LEN_2C_P_3 */
7823   {
7824     { "vcvttsd2siY",    { Gv, EXq } },
7825     { "(bad)",          { XX } },
7826   },
7827
7828   /* VEX_LEN_2D_P_1 */
7829   {
7830     { "vcvtss2siY",     { Gv, EXd } },
7831     { "(bad)",          { XX } },
7832   },
7833
7834   /* VEX_LEN_2D_P_3 */
7835   {
7836     { "vcvtsd2siY",     { Gv, EXq } },
7837     { "(bad)",          { XX } },
7838   },
7839
7840   /* VEX_LEN_2E_P_0 */
7841   {
7842     { "vucomiss",       { XM, EXd } },
7843     { "(bad)",          { XX } },
7844   },
7845
7846   /* VEX_LEN_2E_P_2 */
7847   {
7848     { "vucomisd",       { XM, EXq } },
7849     { "(bad)",          { XX } },
7850   },
7851
7852   /* VEX_LEN_2F_P_0 */
7853   {
7854     { "vcomiss",        { XM, EXd } },
7855     { "(bad)",          { XX } },
7856   },
7857
7858   /* VEX_LEN_2F_P_2 */
7859   {
7860     { "vcomisd",        { XM, EXq } },
7861     { "(bad)",          { XX } },
7862   },
7863
7864   /* VEX_LEN_51_P_1 */
7865   {
7866     { "vsqrtss",        { XM, Vex128, EXd } },
7867     { "(bad)",          { XX } },
7868   },
7869
7870   /* VEX_LEN_51_P_3 */
7871   {
7872     { "vsqrtsd",        { XM, Vex128, EXq } },
7873     { "(bad)",          { XX } },
7874   },
7875
7876   /* VEX_LEN_52_P_1 */
7877   {
7878     { "vrsqrtss",       { XM, Vex128, EXd } },
7879     { "(bad)",          { XX } },
7880   },
7881
7882   /* VEX_LEN_53_P_1 */
7883   {
7884     { "vrcpss",         { XM, Vex128, EXd } },
7885     { "(bad)",          { XX } },
7886   },
7887
7888   /* VEX_LEN_58_P_1 */
7889   {
7890     { "vaddss",         { XM, Vex128, EXd } },
7891     { "(bad)",          { XX } },
7892   },
7893
7894   /* VEX_LEN_58_P_3 */
7895   {
7896     { "vaddsd",         { XM, Vex128, EXq } },
7897     { "(bad)",          { XX } },
7898   },
7899
7900   /* VEX_LEN_59_P_1 */
7901   {
7902     { "vmulss",         { XM, Vex128, EXd } },
7903     { "(bad)",          { XX } },
7904   },
7905
7906   /* VEX_LEN_59_P_3 */
7907   {
7908     { "vmulsd",         { XM, Vex128, EXq } },
7909     { "(bad)",          { XX } },
7910   },
7911
7912   /* VEX_LEN_5A_P_1 */
7913   {
7914     { "vcvtss2sd",      { XM, Vex128, EXd } },
7915     { "(bad)",          { XX } },
7916   },
7917
7918   /* VEX_LEN_5A_P_3 */
7919   {
7920     { "vcvtsd2ss",      { XM, Vex128, EXq } },
7921     { "(bad)",          { XX } },
7922   },
7923
7924   /* VEX_LEN_5C_P_1 */
7925   {
7926     { "vsubss",         { XM, Vex128, EXd } },
7927     { "(bad)",          { XX } },
7928   },
7929
7930   /* VEX_LEN_5C_P_3 */
7931   {
7932     { "vsubsd",         { XM, Vex128, EXq } },
7933     { "(bad)",          { XX } },
7934   },
7935
7936   /* VEX_LEN_5D_P_1 */
7937   {
7938     { "vminss",         { XM, Vex128, EXd } },
7939     { "(bad)",          { XX } },
7940   },
7941
7942   /* VEX_LEN_5D_P_3 */
7943   {
7944     { "vminsd",         { XM, Vex128, EXq } },
7945     { "(bad)",          { XX } },
7946   },
7947
7948   /* VEX_LEN_5E_P_1 */
7949   {
7950     { "vdivss",         { XM, Vex128, EXd } },
7951     { "(bad)",          { XX } },
7952   },
7953
7954   /* VEX_LEN_5E_P_3 */
7955   {
7956     { "vdivsd",         { XM, Vex128, EXq } },
7957     { "(bad)",          { XX } },
7958   },
7959
7960   /* VEX_LEN_5F_P_1 */
7961   {
7962     { "vmaxss",         { XM, Vex128, EXd } },
7963     { "(bad)",          { XX } },
7964   },
7965
7966   /* VEX_LEN_5F_P_3 */
7967   {
7968     { "vmaxsd",         { XM, Vex128, EXq } },
7969     { "(bad)",          { XX } },
7970   },
7971
7972   /* VEX_LEN_60_P_2 */
7973   {
7974     { "vpunpcklbw",     { XM, Vex128, EXx } },
7975     { "(bad)",          { XX } },
7976   },
7977
7978   /* VEX_LEN_61_P_2 */
7979   {
7980     { "vpunpcklwd",     { XM, Vex128, EXx } },
7981     { "(bad)",          { XX } },
7982   },
7983
7984   /* VEX_LEN_62_P_2 */
7985   {
7986     { "vpunpckldq",     { XM, Vex128, EXx } },
7987     { "(bad)",          { XX } },
7988   },
7989
7990   /* VEX_LEN_63_P_2 */
7991   {
7992     { "vpacksswb",      { XM, Vex128, EXx } },
7993     { "(bad)",          { XX } },
7994   },
7995
7996   /* VEX_LEN_64_P_2 */
7997   {
7998     { "vpcmpgtb",       { XM, Vex128, EXx } },
7999     { "(bad)",          { XX } },
8000   },
8001
8002   /* VEX_LEN_65_P_2 */
8003   {
8004     { "vpcmpgtw",       { XM, Vex128, EXx } },
8005     { "(bad)",          { XX } },
8006   },
8007
8008   /* VEX_LEN_66_P_2 */
8009   {
8010     { "vpcmpgtd",       { XM, Vex128, EXx } },
8011     { "(bad)",          { XX } },
8012   },
8013
8014   /* VEX_LEN_67_P_2 */
8015   {
8016     { "vpackuswb",      { XM, Vex128, EXx } },
8017     { "(bad)",          { XX } },
8018   },
8019
8020   /* VEX_LEN_68_P_2 */
8021   {
8022     { "vpunpckhbw",     { XM, Vex128, EXx } },
8023     { "(bad)",          { XX } },
8024   },
8025
8026   /* VEX_LEN_69_P_2 */
8027   {
8028     { "vpunpckhwd",     { XM, Vex128, EXx } },
8029     { "(bad)",          { XX } },
8030   },
8031
8032   /* VEX_LEN_6A_P_2 */
8033   {
8034     { "vpunpckhdq",     { XM, Vex128, EXx } },
8035     { "(bad)",          { XX } },
8036   },
8037
8038   /* VEX_LEN_6B_P_2 */
8039   {
8040     { "vpackssdw",      { XM, Vex128, EXx } },
8041     { "(bad)",          { XX } },
8042   },
8043
8044   /* VEX_LEN_6C_P_2 */
8045   {
8046     { "vpunpcklqdq",    { XM, Vex128, EXx } },
8047     { "(bad)",          { XX } },
8048   },
8049
8050   /* VEX_LEN_6D_P_2 */
8051   {
8052     { "vpunpckhqdq",    { XM, Vex128, EXx } },
8053     { "(bad)",          { XX } },
8054   },
8055
8056   /* VEX_LEN_6E_P_2 */
8057   {
8058     { "vmovK",          { XM, Edq } },
8059     { "(bad)",          { XX } },
8060   },
8061
8062   /* VEX_LEN_70_P_1 */
8063   {
8064     { "vpshufhw",       { XM, EXx, Ib } },
8065     { "(bad)",          { XX } },
8066   },
8067
8068   /* VEX_LEN_70_P_2 */
8069   {
8070     { "vpshufd",        { XM, EXx, Ib } },
8071     { "(bad)",          { XX } },
8072   },
8073
8074   /* VEX_LEN_70_P_3 */
8075   {
8076     { "vpshuflw",       { XM, EXx, Ib } },
8077     { "(bad)",          { XX } },
8078   },
8079
8080   /* VEX_LEN_71_R_2_P_2 */
8081   {
8082     { "vpsrlw",         { Vex128, XS, Ib } },
8083     { "(bad)",          { XX } },
8084   },
8085
8086   /* VEX_LEN_71_R_4_P_2 */
8087   {
8088     { "vpsraw",         { Vex128, XS, Ib } },
8089     { "(bad)",          { XX } },
8090   },
8091
8092   /* VEX_LEN_71_R_6_P_2 */
8093   {
8094     { "vpsllw",         { Vex128, XS, Ib } },
8095     { "(bad)",          { XX } },
8096   },
8097
8098   /* VEX_LEN_72_R_2_P_2 */
8099   {
8100     { "vpsrld",         { Vex128, XS, Ib } },
8101     { "(bad)",          { XX } },
8102   },
8103
8104   /* VEX_LEN_72_R_4_P_2 */
8105   {
8106     { "vpsrad",         { Vex128, XS, Ib } },
8107     { "(bad)",          { XX } },
8108   },
8109
8110   /* VEX_LEN_72_R_6_P_2 */
8111   {
8112     { "vpslld",         { Vex128, XS, Ib } },
8113     { "(bad)",          { XX } },
8114   },
8115
8116   /* VEX_LEN_73_R_2_P_2 */
8117   {
8118     { "vpsrlq",         { Vex128, XS, Ib } },
8119     { "(bad)",          { XX } },
8120   },
8121
8122   /* VEX_LEN_73_R_3_P_2 */
8123   {
8124     { "vpsrldq",        { Vex128, XS, Ib } },
8125     { "(bad)",          { XX } },
8126   },
8127
8128   /* VEX_LEN_73_R_6_P_2 */
8129   {
8130     { "vpsllq",         { Vex128, XS, Ib } },
8131     { "(bad)",          { XX } },
8132   },
8133
8134   /* VEX_LEN_73_R_7_P_2 */
8135   {
8136     { "vpslldq",        { Vex128, XS, Ib } },
8137     { "(bad)",          { XX } },
8138   },
8139
8140   /* VEX_LEN_74_P_2 */
8141   {
8142     { "vpcmpeqb",       { XM, Vex128, EXx } },
8143     { "(bad)",          { XX } },
8144   },
8145
8146   /* VEX_LEN_75_P_2 */
8147   {
8148     { "vpcmpeqw",       { XM, Vex128, EXx } },
8149     { "(bad)",          { XX } },
8150   },
8151
8152   /* VEX_LEN_76_P_2 */
8153   {
8154     { "vpcmpeqd",       { XM, Vex128, EXx } },
8155     { "(bad)",          { XX } },
8156   },
8157
8158   /* VEX_LEN_7E_P_1 */
8159   {
8160     { "vmovq",          { XM, EXq } },
8161     { "(bad)",          { XX } },
8162   },
8163
8164   /* VEX_LEN_7E_P_2 */
8165   {
8166     { "vmovK",          { Edq, XM } },
8167     { "(bad)",          { XX } },
8168   },
8169
8170   /* VEX_LEN_AE_R_2_M0 */
8171   {
8172     { "vldmxcsr",       { Md } },
8173     { "(bad)",          { XX } },
8174   },
8175
8176   /* VEX_LEN_AE_R_3_M0 */
8177   {
8178     { "vstmxcsr",       { Md } },
8179     { "(bad)",          { XX } },
8180   },
8181
8182   /* VEX_LEN_C2_P_1 */
8183   {
8184     { "vcmpss",         { XM, Vex128, EXd, VCMP } },
8185     { "(bad)",          { XX } },
8186   },
8187
8188   /* VEX_LEN_C2_P_3 */
8189   {
8190     { "vcmpsd",         { XM, Vex128, EXq, VCMP } },
8191     { "(bad)",          { XX } },
8192   },
8193
8194   /* VEX_LEN_C4_P_2 */
8195   {
8196     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
8197     { "(bad)",          { XX } },
8198   },
8199
8200   /* VEX_LEN_C5_P_2 */
8201   {
8202     { "vpextrw",        { Gdq, XS, Ib } },
8203     { "(bad)",          { XX } },
8204   },
8205
8206   /* VEX_LEN_D1_P_2 */
8207   {
8208     { "vpsrlw",         { XM, Vex128, EXx } },
8209     { "(bad)",          { XX } },
8210   },
8211
8212   /* VEX_LEN_D2_P_2 */
8213   {
8214     { "vpsrld",         { XM, Vex128, EXx } },
8215     { "(bad)",          { XX } },
8216   },
8217
8218   /* VEX_LEN_D3_P_2 */
8219   {
8220     { "vpsrlq",         { XM, Vex128, EXx } },
8221     { "(bad)",          { XX } },
8222   },
8223
8224   /* VEX_LEN_D4_P_2 */
8225   {
8226     { "vpaddq",         { XM, Vex128, EXx } },
8227     { "(bad)",          { XX } },
8228   },
8229
8230   /* VEX_LEN_D5_P_2 */
8231   {
8232     { "vpmullw",        { XM, Vex128, EXx } },
8233     { "(bad)",          { XX } },
8234   },
8235
8236   /* VEX_LEN_D6_P_2 */
8237   {
8238     { "vmovq",          { EXq, XM } },
8239     { "(bad)",          { XX } },
8240   },
8241
8242   /* VEX_LEN_D7_P_2_M_1 */
8243   {
8244     { "vpmovmskb",      { Gdq, XS } },
8245     { "(bad)",          { XX } },
8246   },
8247
8248   /* VEX_LEN_D8_P_2 */
8249   {
8250     { "vpsubusb",       { XM, Vex128, EXx } },
8251     { "(bad)",          { XX } },
8252   },
8253
8254   /* VEX_LEN_D9_P_2 */
8255   {
8256     { "vpsubusw",       { XM, Vex128, EXx } },
8257     { "(bad)",          { XX } },
8258   },
8259
8260   /* VEX_LEN_DA_P_2 */
8261   {
8262     { "vpminub",        { XM, Vex128, EXx } },
8263     { "(bad)",          { XX } },
8264   },
8265
8266   /* VEX_LEN_DB_P_2 */
8267   {
8268     { "vpand",          { XM, Vex128, EXx } },
8269     { "(bad)",          { XX } },
8270   },
8271
8272   /* VEX_LEN_DC_P_2 */
8273   {
8274     { "vpaddusb",       { XM, Vex128, EXx } },
8275     { "(bad)",          { XX } },
8276   },
8277
8278   /* VEX_LEN_DD_P_2 */
8279   {
8280     { "vpaddusw",       { XM, Vex128, EXx } },
8281     { "(bad)",          { XX } },
8282   },
8283
8284   /* VEX_LEN_DE_P_2 */
8285   {
8286     { "vpmaxub",        { XM, Vex128, EXx } },
8287     { "(bad)",          { XX } },
8288   },
8289
8290   /* VEX_LEN_DF_P_2 */
8291   {
8292     { "vpandn",         { XM, Vex128, EXx } },
8293     { "(bad)",          { XX } },
8294   },
8295
8296   /* VEX_LEN_E0_P_2 */
8297   {
8298     { "vpavgb",         { XM, Vex128, EXx } },
8299     { "(bad)",          { XX } },
8300   },
8301
8302   /* VEX_LEN_E1_P_2 */
8303   {
8304     { "vpsraw",         { XM, Vex128, EXx } },
8305     { "(bad)",          { XX } },
8306   },
8307
8308   /* VEX_LEN_E2_P_2 */
8309   {
8310     { "vpsrad",         { XM, Vex128, EXx } },
8311     { "(bad)",          { XX } },
8312   },
8313
8314   /* VEX_LEN_E3_P_2 */
8315   {
8316     { "vpavgw",         { XM, Vex128, EXx } },
8317     { "(bad)",          { XX } },
8318   },
8319
8320   /* VEX_LEN_E4_P_2 */
8321   {
8322     { "vpmulhuw",       { XM, Vex128, EXx } },
8323     { "(bad)",          { XX } },
8324   },
8325
8326   /* VEX_LEN_E5_P_2 */
8327   {
8328     { "vpmulhw",        { XM, Vex128, EXx } },
8329     { "(bad)",          { XX } },
8330   },
8331
8332   /* VEX_LEN_E7_P_2_M_0 */
8333   {
8334     { "vmovntdq",       { Mx, XM } },
8335     { "(bad)",          { XX } },
8336   },
8337
8338   /* VEX_LEN_E8_P_2 */
8339   {
8340     { "vpsubsb",        { XM, Vex128, EXx } },
8341     { "(bad)",          { XX } },
8342   },
8343
8344   /* VEX_LEN_E9_P_2 */
8345   {
8346     { "vpsubsw",        { XM, Vex128, EXx } },
8347     { "(bad)",          { XX } },
8348   },
8349
8350   /* VEX_LEN_EA_P_2 */
8351   {
8352     { "vpminsw",        { XM, Vex128, EXx } },
8353     { "(bad)",          { XX } },
8354   },
8355
8356   /* VEX_LEN_EB_P_2 */
8357   {
8358     { "vpor",           { XM, Vex128, EXx } },
8359     { "(bad)",          { XX } },
8360   },
8361
8362   /* VEX_LEN_EC_P_2 */
8363   {
8364     { "vpaddsb",        { XM, Vex128, EXx } },
8365     { "(bad)",          { XX } },
8366   },
8367
8368   /* VEX_LEN_ED_P_2 */
8369   {
8370     { "vpaddsw",        { XM, Vex128, EXx } },
8371     { "(bad)",          { XX } },
8372   },
8373
8374   /* VEX_LEN_EE_P_2 */
8375   {
8376     { "vpmaxsw",        { XM, Vex128, EXx } },
8377     { "(bad)",          { XX } },
8378   },
8379
8380   /* VEX_LEN_EF_P_2 */
8381   {
8382     { "vpxor",          { XM, Vex128, EXx } },
8383     { "(bad)",          { XX } },
8384   },
8385
8386   /* VEX_LEN_F1_P_2 */
8387   {
8388     { "vpsllw",         { XM, Vex128, EXx } },
8389     { "(bad)",          { XX } },
8390   },
8391
8392   /* VEX_LEN_F2_P_2 */
8393   {
8394     { "vpslld",         { XM, Vex128, EXx } },
8395     { "(bad)",          { XX } },
8396   },
8397
8398   /* VEX_LEN_F3_P_2 */
8399   {
8400     { "vpsllq",         { XM, Vex128, EXx } },
8401     { "(bad)",          { XX } },
8402   },
8403
8404   /* VEX_LEN_F4_P_2 */
8405   {
8406     { "vpmuludq",       { XM, Vex128, EXx } },
8407     { "(bad)",          { XX } },
8408   },
8409
8410   /* VEX_LEN_F5_P_2 */
8411   {
8412     { "vpmaddwd",       { XM, Vex128, EXx } },
8413     { "(bad)",          { XX } },
8414   },
8415
8416   /* VEX_LEN_F6_P_2 */
8417   {
8418     { "vpsadbw",        { XM, Vex128, EXx } },
8419     { "(bad)",          { XX } },
8420   },
8421
8422   /* VEX_LEN_F7_P_2 */
8423   {
8424     { "vmaskmovdqu",    { XM, XS } },
8425     { "(bad)",          { XX } },
8426   },
8427
8428   /* VEX_LEN_F8_P_2 */
8429   {
8430     { "vpsubb",         { XM, Vex128, EXx } },
8431     { "(bad)",          { XX } },
8432   },
8433
8434   /* VEX_LEN_F9_P_2 */
8435   {
8436     { "vpsubw",         { XM, Vex128, EXx } },
8437     { "(bad)",          { XX } },
8438   },
8439
8440   /* VEX_LEN_FA_P_2 */
8441   {
8442     { "vpsubd",         { XM, Vex128, EXx } },
8443     { "(bad)",          { XX } },
8444   },
8445
8446   /* VEX_LEN_FB_P_2 */
8447   {
8448     { "vpsubq",         { XM, Vex128, EXx } },
8449     { "(bad)",          { XX } },
8450   },
8451
8452   /* VEX_LEN_FC_P_2 */
8453   {
8454     { "vpaddb",         { XM, Vex128, EXx } },
8455     { "(bad)",          { XX } },
8456   },
8457
8458   /* VEX_LEN_FD_P_2 */
8459   {
8460     { "vpaddw",         { XM, Vex128, EXx } },
8461     { "(bad)",          { XX } },
8462   },
8463
8464   /* VEX_LEN_FE_P_2 */
8465   {
8466     { "vpaddd",         { XM, Vex128, EXx } },
8467     { "(bad)",          { XX } },
8468   },
8469
8470   /* VEX_LEN_3800_P_2 */
8471   {
8472     { "vpshufb",        { XM, Vex128, EXx } },
8473     { "(bad)",          { XX } },
8474   },
8475
8476   /* VEX_LEN_3801_P_2 */
8477   {
8478     { "vphaddw",        { XM, Vex128, EXx } },
8479     { "(bad)",          { XX } },
8480   },
8481
8482   /* VEX_LEN_3802_P_2 */
8483   {
8484     { "vphaddd",        { XM, Vex128, EXx } },
8485     { "(bad)",          { XX } },
8486   },
8487
8488   /* VEX_LEN_3803_P_2 */
8489   {
8490     { "vphaddsw",       { XM, Vex128, EXx } },
8491     { "(bad)",          { XX } },
8492   },
8493
8494   /* VEX_LEN_3804_P_2 */
8495   {
8496     { "vpmaddubsw",     { XM, Vex128, EXx } },
8497     { "(bad)",          { XX } },
8498   },
8499
8500   /* VEX_LEN_3805_P_2 */
8501   {
8502     { "vphsubw",        { XM, Vex128, EXx } },
8503     { "(bad)",          { XX } },
8504   },
8505
8506   /* VEX_LEN_3806_P_2 */
8507   {
8508     { "vphsubd",        { XM, Vex128, EXx } },
8509     { "(bad)",          { XX } },
8510   },
8511
8512   /* VEX_LEN_3807_P_2 */
8513   {
8514     { "vphsubsw",       { XM, Vex128, EXx } },
8515     { "(bad)",          { XX } },
8516   },
8517
8518   /* VEX_LEN_3808_P_2 */
8519   {
8520     { "vpsignb",        { XM, Vex128, EXx } },
8521     { "(bad)",          { XX } },
8522   },
8523
8524   /* VEX_LEN_3809_P_2 */
8525   {
8526     { "vpsignw",        { XM, Vex128, EXx } },
8527     { "(bad)",          { XX } },
8528   },
8529
8530   /* VEX_LEN_380A_P_2 */
8531   {
8532     { "vpsignd",        { XM, Vex128, EXx } },
8533     { "(bad)",          { XX } },
8534   },
8535
8536   /* VEX_LEN_380B_P_2 */
8537   {
8538     { "vpmulhrsw",      { XM, Vex128, EXx } },
8539     { "(bad)",          { XX } },
8540   },
8541
8542   /* VEX_LEN_3819_P_2_M_0 */
8543   {
8544     { "(bad)",          { XX } },
8545     { "vbroadcastsd",   { XM, Mq } },
8546   },
8547
8548   /* VEX_LEN_381A_P_2_M_0 */
8549   {
8550     { "(bad)",          { XX } },
8551     { "vbroadcastf128", { XM, Mxmm } },
8552   },
8553
8554   /* VEX_LEN_381C_P_2 */
8555   {
8556     { "vpabsb",         { XM, EXx } },
8557     { "(bad)",          { XX } },
8558   },
8559
8560   /* VEX_LEN_381D_P_2 */
8561   {
8562     { "vpabsw",         { XM, EXx } },
8563     { "(bad)",          { XX } },
8564   },
8565
8566   /* VEX_LEN_381E_P_2 */
8567   {
8568     { "vpabsd",         { XM, EXx } },
8569     { "(bad)",          { XX } },
8570   },
8571
8572   /* VEX_LEN_3820_P_2 */
8573   {
8574     { "vpmovsxbw",      { XM, EXq } },
8575     { "(bad)",          { XX } },
8576   },
8577
8578   /* VEX_LEN_3821_P_2 */
8579   {
8580     { "vpmovsxbd",      { XM, EXd } },
8581     { "(bad)",          { XX } },
8582   },
8583
8584   /* VEX_LEN_3822_P_2 */
8585   {
8586     { "vpmovsxbq",      { XM, EXw } },
8587     { "(bad)",          { XX } },
8588   },
8589
8590   /* VEX_LEN_3823_P_2 */
8591   {
8592     { "vpmovsxwd",      { XM, EXq } },
8593     { "(bad)",          { XX } },
8594   },
8595
8596   /* VEX_LEN_3824_P_2 */
8597   {
8598     { "vpmovsxwq",      { XM, EXd } },
8599     { "(bad)",          { XX } },
8600   },
8601
8602   /* VEX_LEN_3825_P_2 */
8603   {
8604     { "vpmovsxdq",      { XM, EXq } },
8605     { "(bad)",          { XX } },
8606   },
8607
8608   /* VEX_LEN_3828_P_2 */
8609   {
8610     { "vpmuldq",        { XM, Vex128, EXx } },
8611     { "(bad)",          { XX } },
8612   },
8613
8614   /* VEX_LEN_3829_P_2 */
8615   {
8616     { "vpcmpeqq",       { XM, Vex128, EXx } },
8617     { "(bad)",          { XX } },
8618   },
8619
8620   /* VEX_LEN_382A_P_2_M_0 */
8621   {
8622     { "vmovntdqa",      { XM, Mx } },
8623     { "(bad)",          { XX } },
8624   },
8625
8626   /* VEX_LEN_382B_P_2 */
8627   {
8628     { "vpackusdw",      { XM, Vex128, EXx } },
8629     { "(bad)",          { XX } },
8630   },
8631
8632   /* VEX_LEN_3830_P_2 */
8633   {
8634     { "vpmovzxbw",      { XM, EXq } },
8635     { "(bad)",          { XX } },
8636   },
8637
8638   /* VEX_LEN_3831_P_2 */
8639   {
8640     { "vpmovzxbd",      { XM, EXd } },
8641     { "(bad)",          { XX } },
8642   },
8643
8644   /* VEX_LEN_3832_P_2 */
8645   {
8646     { "vpmovzxbq",      { XM, EXw } },
8647     { "(bad)",          { XX } },
8648   },
8649
8650   /* VEX_LEN_3833_P_2 */
8651   {
8652     { "vpmovzxwd",      { XM, EXq } },
8653     { "(bad)",          { XX } },
8654   },
8655
8656   /* VEX_LEN_3834_P_2 */
8657   {
8658     { "vpmovzxwq",      { XM, EXd } },
8659     { "(bad)",          { XX } },
8660   },
8661
8662   /* VEX_LEN_3835_P_2 */
8663   {
8664     { "vpmovzxdq",      { XM, EXq } },
8665     { "(bad)",          { XX } },
8666   },
8667
8668   /* VEX_LEN_3837_P_2 */
8669   {
8670     { "vpcmpgtq",       { XM, Vex128, EXx } },
8671     { "(bad)",          { XX } },
8672   },
8673
8674   /* VEX_LEN_3838_P_2 */
8675   {
8676     { "vpminsb",        { XM, Vex128, EXx } },
8677     { "(bad)",          { XX } },
8678   },
8679
8680   /* VEX_LEN_3839_P_2 */
8681   {
8682     { "vpminsd",        { XM, Vex128, EXx } },
8683     { "(bad)",          { XX } },
8684   },
8685
8686   /* VEX_LEN_383A_P_2 */
8687   {
8688     { "vpminuw",        { XM, Vex128, EXx } },
8689     { "(bad)",          { XX } },
8690   },
8691
8692   /* VEX_LEN_383B_P_2 */
8693   {
8694     { "vpminud",        { XM, Vex128, EXx } },
8695     { "(bad)",          { XX } },
8696   },
8697
8698   /* VEX_LEN_383C_P_2 */
8699   {
8700     { "vpmaxsb",        { XM, Vex128, EXx } },
8701     { "(bad)",          { XX } },
8702   },
8703
8704   /* VEX_LEN_383D_P_2 */
8705   {
8706     { "vpmaxsd",        { XM, Vex128, EXx } },
8707     { "(bad)",          { XX } },
8708   },
8709
8710   /* VEX_LEN_383E_P_2 */
8711   {
8712     { "vpmaxuw",        { XM, Vex128, EXx } },
8713     { "(bad)",          { XX } },
8714   },
8715
8716   /* VEX_LEN_383F_P_2 */
8717   {
8718     { "vpmaxud",        { XM, Vex128, EXx } },
8719     { "(bad)",          { XX } },
8720   },
8721
8722   /* VEX_LEN_3840_P_2 */
8723   {
8724     { "vpmulld",        { XM, Vex128, EXx } },
8725     { "(bad)",          { XX } },
8726   },
8727
8728   /* VEX_LEN_3841_P_2 */
8729   {
8730     { "vphminposuw",    { XM, EXx } },
8731     { "(bad)",          { XX } },
8732   },
8733
8734   /* VEX_LEN_3A06_P_2 */
8735   {
8736     { "(bad)",          { XX } },
8737     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
8738   },
8739
8740   /* VEX_LEN_3A0A_P_2 */
8741   {
8742     { "vroundss",       { XM, Vex128, EXd, Ib } },
8743     { "(bad)",          { XX } },
8744   },
8745
8746   /* VEX_LEN_3A0B_P_2 */
8747   {
8748     { "vroundsd",       { XM, Vex128, EXq, Ib } },
8749     { "(bad)",          { XX } },
8750   },
8751
8752   /* VEX_LEN_3A0E_P_2 */
8753   {
8754     { "vpblendw",       { XM, Vex128, EXx, Ib } },
8755     { "(bad)",          { XX } },
8756   },
8757
8758   /* VEX_LEN_3A0F_P_2 */
8759   {
8760     { "vpalignr",       { XM, Vex128, EXx, Ib } },
8761     { "(bad)",          { XX } },
8762   },
8763
8764   /* VEX_LEN_3A14_P_2 */
8765   {
8766     { "vpextrb",        { Edqb, XM, Ib } },
8767     { "(bad)",          { XX } },
8768   },
8769
8770   /* VEX_LEN_3A15_P_2 */
8771   {
8772     { "vpextrw",        { Edqw, XM, Ib } },
8773     { "(bad)",          { XX } },
8774   },
8775
8776   /* VEX_LEN_3A16_P_2  */
8777   {
8778     { "vpextrK",        { Edq, XM, Ib } },
8779     { "(bad)",          { XX } },
8780   },
8781
8782   /* VEX_LEN_3A17_P_2 */
8783   {
8784     { "vextractps",     { Edqd, XM, Ib } },
8785     { "(bad)",          { XX } },
8786   },
8787
8788   /* VEX_LEN_3A18_P_2 */
8789   {
8790     { "(bad)",          { XX } },
8791     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
8792   },
8793
8794   /* VEX_LEN_3A19_P_2 */
8795   {
8796     { "(bad)",          { XX } },
8797     { "vextractf128",   { EXxmm, XM, Ib } },
8798   },
8799
8800   /* VEX_LEN_3A20_P_2 */
8801   {
8802     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
8803     { "(bad)",          { XX } },
8804   },
8805
8806   /* VEX_LEN_3A21_P_2 */
8807   {
8808     { "vinsertps",      { XM, Vex128, EXd, Ib } },
8809     { "(bad)",          { XX } },
8810   },
8811
8812   /* VEX_LEN_3A22_P_2 */
8813   {
8814     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
8815     { "(bad)",          { XX } },
8816   },
8817
8818   /* VEX_LEN_3A41_P_2 */
8819   {
8820     { "vdppd",          { XM, Vex128, EXx, Ib } },
8821     { "(bad)",          { XX } },
8822   },
8823
8824   /* VEX_LEN_3A42_P_2 */
8825   {
8826     { "vmpsadbw",       { XM, Vex128, EXx, Ib } },
8827     { "(bad)",          { XX } },
8828   },
8829
8830   /* VEX_LEN_3A4C_P_2 */
8831   {
8832     { "vpblendvb",      { XM, Vex128, EXx, XMVexI4 } },
8833     { "(bad)",          { XX } },
8834   },
8835
8836   /* VEX_LEN_3A60_P_2 */
8837   {
8838     { "vpcmpestrm",     { XM, EXx, Ib } },
8839     { "(bad)",          { XX } },
8840   },
8841
8842   /* VEX_LEN_3A61_P_2 */
8843   {
8844     { "vpcmpestri",     { XM, EXx, Ib } },
8845     { "(bad)",          { XX } },
8846   },
8847
8848   /* VEX_LEN_3A62_P_2 */
8849   {
8850     { "vpcmpistrm",     { XM, EXx, Ib } },
8851     { "(bad)",          { XX } },
8852   },
8853
8854   /* VEX_LEN_3A63_P_2 */
8855   {
8856     { "vpcmpistri",     { XM, EXx, Ib } },
8857     { "(bad)",          { XX } },
8858   },
8859
8860   /* VEX_LEN_3A6A_P_2 */
8861   {
8862     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8863     { "(bad)",          { XX } },
8864   },
8865
8866   /* VEX_LEN_3A6B_P_2 */
8867   {
8868     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8869     { "(bad)",          { XX } },
8870   },
8871
8872   /* VEX_LEN_3A6E_P_2 */
8873   {
8874     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8875     { "(bad)",          { XX } },
8876   },
8877
8878   /* VEX_LEN_3A6F_P_2 */
8879   {
8880     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8881     { "(bad)",          { XX } },
8882   },
8883
8884   /* VEX_LEN_3A7A_P_2 */
8885   {
8886     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8887     { "(bad)",          { XX } },
8888   },
8889
8890   /* VEX_LEN_3A7B_P_2 */
8891   {
8892     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8893     { "(bad)",          { XX } },
8894   },
8895
8896   /* VEX_LEN_3A7E_P_2 */
8897   {
8898     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8899     { "(bad)",          { XX } },
8900   },
8901
8902   /* VEX_LEN_3A7F_P_2 */
8903   {
8904     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8905     { "(bad)",          { XX } },
8906   },
8907 };
8908
8909 static const struct dis386 mod_table[][2] = {
8910   {
8911     /* MOD_8D */
8912     { "leaS",           { Gv, M } },
8913     { "(bad)",          { XX } },
8914   },
8915   {
8916     /* MOD_0F01_REG_0 */
8917     { X86_64_TABLE (X86_64_0F01_REG_0) },
8918     { RM_TABLE (RM_0F01_REG_0) },
8919   },
8920   {
8921     /* MOD_0F01_REG_1 */
8922     { X86_64_TABLE (X86_64_0F01_REG_1) },
8923     { RM_TABLE (RM_0F01_REG_1) },
8924   },
8925   {
8926     /* MOD_0F01_REG_2 */
8927     { X86_64_TABLE (X86_64_0F01_REG_2) },
8928     { RM_TABLE (RM_0F01_REG_2) },
8929   },
8930   {
8931     /* MOD_0F01_REG_3 */
8932     { X86_64_TABLE (X86_64_0F01_REG_3) },
8933     { RM_TABLE (RM_0F01_REG_3) },
8934   },
8935   {
8936     /* MOD_0F01_REG_7 */
8937     { "invlpg",         { Mb } },
8938     { RM_TABLE (RM_0F01_REG_7) },
8939   },
8940   {
8941     /* MOD_0F12_PREFIX_0 */
8942     { "movlps",         { XM, EXq } },
8943     { "movhlps",        { XM, EXq } },
8944   },
8945   {
8946     /* MOD_0F13 */
8947     { "movlpX",         { EXq, XM } },
8948     { "(bad)",          { XX } },
8949   },
8950   {
8951     /* MOD_0F16_PREFIX_0 */
8952     { "movhps",         { XM, EXq } },
8953     { "movlhps",        { XM, EXq } },
8954   },
8955   {
8956     /* MOD_0F17 */
8957     { "movhpX",         { EXq, XM } },
8958     { "(bad)",          { XX } },
8959   },
8960   {
8961     /* MOD_0F18_REG_0 */
8962     { "prefetchnta",    { Mb } },
8963     { "(bad)",          { XX } },
8964   },
8965   {
8966     /* MOD_0F18_REG_1 */
8967     { "prefetcht0",     { Mb } },
8968     { "(bad)",          { XX } },
8969   },
8970   {
8971     /* MOD_0F18_REG_2 */
8972     { "prefetcht1",     { Mb } },
8973     { "(bad)",          { XX } },
8974   },
8975   {
8976     /* MOD_0F18_REG_3 */
8977     { "prefetcht2",     { Mb } },
8978     { "(bad)",          { XX } },
8979   },
8980   {
8981     /* MOD_0F20 */
8982     { "(bad)",          { XX } },
8983     { "movZ",           { Rm, Cm } },
8984   },
8985   {
8986     /* MOD_0F21 */
8987     { "(bad)",          { XX } },
8988     { "movZ",           { Rm, Dm } },
8989   },
8990   {
8991     /* MOD_0F22 */
8992     { "(bad)",          { XX } },
8993     { "movZ",           { Cm, Rm } },
8994   },
8995   {
8996     /* MOD_0F23 */
8997     { "(bad)",          { XX } },
8998     { "movZ",           { Dm, Rm } },
8999   },
9000   {
9001     /* MOD_0F24 */
9002     { THREE_BYTE_TABLE (THREE_BYTE_0F24) },
9003     { "movL",           { Rd, Td } },
9004   },
9005   {
9006     /* MOD_0F26 */
9007     { "(bad)",          { XX } },
9008     { "movL",           { Td, Rd } },
9009   },
9010   {
9011     /* MOD_0F2B_PREFIX_0 */
9012     {"movntps",         { Mx, XM } },
9013     { "(bad)",          { XX } },
9014   },
9015   {
9016     /* MOD_0F2B_PREFIX_1 */
9017     {"movntss",         { Md, XM } },
9018     { "(bad)",          { XX } },
9019   },
9020   {
9021     /* MOD_0F2B_PREFIX_2 */
9022     {"movntpd",         { Mx, XM } },
9023     { "(bad)",          { XX } },
9024   },
9025   {
9026     /* MOD_0F2B_PREFIX_3 */
9027     {"movntsd",         { Mq, XM } },
9028     { "(bad)",          { XX } },
9029   },
9030   {
9031     /* MOD_0F51 */
9032     { "(bad)",          { XX } },
9033     { "movmskpX",       { Gdq, XS } },
9034   },
9035   {
9036     /* MOD_0F71_REG_2 */
9037     { "(bad)",          { XX } },
9038     { "psrlw",          { MS, Ib } },
9039   },
9040   {
9041     /* MOD_0F71_REG_4 */
9042     { "(bad)",          { XX } },
9043     { "psraw",          { MS, Ib } },
9044   },
9045   {
9046     /* MOD_0F71_REG_6 */
9047     { "(bad)",          { XX } },
9048     { "psllw",          { MS, Ib } },
9049   },
9050   {
9051     /* MOD_0F72_REG_2 */
9052     { "(bad)",          { XX } },
9053     { "psrld",          { MS, Ib } },
9054   },
9055   {
9056     /* MOD_0F72_REG_4 */
9057     { "(bad)",          { XX } },
9058     { "psrad",          { MS, Ib } },
9059   },
9060   {
9061     /* MOD_0F72_REG_6 */
9062     { "(bad)",          { XX } },
9063     { "pslld",          { MS, Ib } },
9064   },
9065   {
9066     /* MOD_0F73_REG_2 */
9067     { "(bad)",          { XX } },
9068     { "psrlq",          { MS, Ib } },
9069   },
9070   {
9071     /* MOD_0F73_REG_3 */
9072     { "(bad)",          { XX } },
9073     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
9074   },
9075   {
9076     /* MOD_0F73_REG_6 */
9077     { "(bad)",          { XX } },
9078     { "psllq",          { MS, Ib } },
9079   },
9080   {
9081     /* MOD_0F73_REG_7 */
9082     { "(bad)",          { XX } },
9083     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
9084   },
9085   {
9086     /* MOD_0FAE_REG_0 */
9087     { "fxsave",         { M } },
9088     { "(bad)",          { XX } },
9089   },
9090   {
9091     /* MOD_0FAE_REG_1 */
9092     { "fxrstor",        { M } },
9093     { "(bad)",          { XX } },
9094   },
9095   {
9096     /* MOD_0FAE_REG_2 */
9097     { "ldmxcsr",        { Md } },
9098     { "(bad)",          { XX } },
9099   },
9100   {
9101     /* MOD_0FAE_REG_3 */
9102     { "stmxcsr",        { Md } },
9103     { "(bad)",          { XX } },
9104   },
9105   {
9106     /* MOD_0FAE_REG_4 */
9107     { "xsave",          { M } },
9108     { "(bad)",          { XX } },
9109   },
9110   {
9111     /* MOD_0FAE_REG_5 */
9112     { "xrstor",         { M } },
9113     { RM_TABLE (RM_0FAE_REG_5) },
9114   },
9115   {
9116     /* MOD_0FAE_REG_6 */
9117     { "xsaveopt",       { M } },
9118     { RM_TABLE (RM_0FAE_REG_6) },
9119   },
9120   {
9121     /* MOD_0FAE_REG_7 */
9122     { "clflush",        { Mb } },
9123     { RM_TABLE (RM_0FAE_REG_7) },
9124   },
9125   {
9126     /* MOD_0FB2 */
9127     { "lssS",           { Gv, Mp } },
9128     { "(bad)",          { XX } },
9129   },
9130   {
9131     /* MOD_0FB4 */
9132     { "lfsS",           { Gv, Mp } },
9133     { "(bad)",          { XX } },
9134   },
9135   {
9136     /* MOD_0FB5 */
9137     { "lgsS",           { Gv, Mp } },
9138     { "(bad)",          { XX } },
9139   },
9140   {
9141     /* MOD_0FC7_REG_6 */
9142     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
9143     { "(bad)",          { XX } },
9144   },
9145   {
9146     /* MOD_0FC7_REG_7 */
9147     { "vmptrst",        { Mq } },
9148     { "(bad)",          { XX } },
9149   },
9150   {
9151     /* MOD_0FD7 */
9152     { "(bad)",          { XX } },
9153     { "pmovmskb",       { Gdq, MS } },
9154   },
9155   {
9156     /* MOD_0FE7_PREFIX_2 */
9157     { "movntdq",        { Mx, XM } },
9158     { "(bad)",          { XX } },
9159   },
9160   {
9161     /* MOD_0FF0_PREFIX_3 */
9162     { "lddqu",          { XM, M } },
9163     { "(bad)",          { XX } },
9164   },
9165   {
9166     /* MOD_0F382A_PREFIX_2 */
9167     { "movntdqa",       { XM, Mx } },
9168     { "(bad)",          { XX } },
9169   },
9170   {
9171     /* MOD_62_32BIT */
9172     { "bound{S|}",      { Gv, Ma } },
9173     { "(bad)",          { XX } },
9174   },
9175   {
9176     /* MOD_C4_32BIT */
9177     { "lesS",           { Gv, Mp } },
9178     { VEX_C4_TABLE (VEX_0F) },
9179   },
9180   {
9181     /* MOD_C5_32BIT */
9182     { "ldsS",           { Gv, Mp } },
9183     { VEX_C5_TABLE (VEX_0F) },
9184   },
9185   {
9186     /* MOD_VEX_12_PREFIX_0 */
9187     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
9188     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
9189   },
9190   {
9191     /* MOD_VEX_13 */
9192     { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
9193     { "(bad)",          { XX } },
9194   },
9195   {
9196     /* MOD_VEX_16_PREFIX_0 */
9197     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
9198     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
9199   },
9200   {
9201     /* MOD_VEX_17 */
9202     { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
9203     { "(bad)",          { XX } },
9204   },
9205   {
9206     /* MOD_VEX_2B */
9207     { VEX_LEN_TABLE (VEX_LEN_2B_M_0) },
9208     { "(bad)",          { XX } },
9209   },
9210   {
9211     /* MOD_VEX_51 */
9212     { "(bad)",          { XX } },
9213     { "vmovmskpX",      { Gdq, XS } },
9214   },
9215   {
9216     /* MOD_VEX_71_REG_2 */
9217     { "(bad)",          { XX } },
9218     { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
9219   },
9220   {
9221     /* MOD_VEX_71_REG_4 */
9222     { "(bad)",          { XX } },
9223     { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
9224   },
9225   {
9226     /* MOD_VEX_71_REG_6 */
9227     { "(bad)",          { XX } },
9228     { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
9229   },
9230   {
9231     /* MOD_VEX_72_REG_2 */
9232     { "(bad)",          { XX } },
9233     { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
9234   },
9235   {
9236     /* MOD_VEX_72_REG_4 */
9237     { "(bad)",          { XX } },
9238     { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
9239   },
9240   {
9241     /* MOD_VEX_72_REG_6 */
9242     { "(bad)",          { XX } },
9243     { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
9244   },
9245   {
9246     /* MOD_VEX_73_REG_2 */
9247     { "(bad)",          { XX } },
9248     { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
9249   },
9250   {
9251     /* MOD_VEX_73_REG_3 */
9252     { "(bad)",          { XX } },
9253     { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
9254   },
9255   {
9256     /* MOD_VEX_73_REG_6 */
9257     { "(bad)",          { XX } },
9258     { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
9259   },
9260   {
9261     /* MOD_VEX_73_REG_7 */
9262     { "(bad)",          { XX } },
9263     { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
9264   },
9265   {
9266     /* MOD_VEX_AE_REG_2 */
9267     { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
9268     { "(bad)",          { XX } },
9269   },
9270   {
9271     /* MOD_VEX_AE_REG_3 */
9272     { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
9273     { "(bad)",          { XX } },
9274   },
9275   {
9276     /* MOD_VEX_D7_PREFIX_2 */
9277     { "(bad)",          { XX } },
9278     { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
9279   },
9280   {
9281     /* MOD_VEX_E7_PREFIX_2 */
9282     { VEX_LEN_TABLE (VEX_LEN_E7_P_2_M_0) },
9283     { "(bad)",          { XX } },
9284   },
9285   {
9286     /* MOD_VEX_F0_PREFIX_3 */
9287     { "vlddqu",         { XM, M } },
9288     { "(bad)",          { XX } },
9289   },
9290   {
9291     /* MOD_VEX_3818_PREFIX_2 */
9292     { "vbroadcastss",   { XM, Md } },
9293     { "(bad)",          { XX } },
9294   },
9295   {
9296     /* MOD_VEX_3819_PREFIX_2 */
9297     { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
9298     { "(bad)",          { XX } },
9299   },
9300   {
9301     /* MOD_VEX_381A_PREFIX_2 */
9302     { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
9303     { "(bad)",          { XX } },
9304   },
9305   {
9306     /* MOD_VEX_382A_PREFIX_2 */
9307     { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
9308     { "(bad)",          { XX } },
9309   },
9310   {
9311     /* MOD_VEX_382C_PREFIX_2 */
9312     { "vmaskmovps",     { XM, Vex, Mx } },
9313     { "(bad)",          { XX } },
9314   },
9315   {
9316     /* MOD_VEX_382D_PREFIX_2 */
9317     { "vmaskmovpd",     { XM, Vex, Mx } },
9318     { "(bad)",          { XX } },
9319   },
9320   {
9321     /* MOD_VEX_382E_PREFIX_2 */
9322     { "vmaskmovps",     { Mx, Vex, XM } },
9323     { "(bad)",          { XX } },
9324   },
9325   {
9326     /* MOD_VEX_382F_PREFIX_2 */
9327     { "vmaskmovpd",     { Mx, Vex, XM } },
9328     { "(bad)",          { XX } },
9329   },
9330 };
9331
9332 static const struct dis386 rm_table[][8] = {
9333   {
9334     /* RM_0F01_REG_0 */
9335     { "(bad)",          { XX } },
9336     { "vmcall",         { Skip_MODRM } },
9337     { "vmlaunch",       { Skip_MODRM } },
9338     { "vmresume",       { Skip_MODRM } },
9339     { "vmxoff",         { Skip_MODRM } },
9340     { "(bad)",          { XX } },
9341     { "(bad)",          { XX } },
9342     { "(bad)",          { XX } },
9343   },
9344   {
9345     /* RM_0F01_REG_1 */
9346     { "monitor",        { { OP_Monitor, 0 } } },
9347     { "mwait",          { { OP_Mwait, 0 } } },
9348     { "(bad)",          { XX } },
9349     { "(bad)",          { XX } },
9350     { "(bad)",          { XX } },
9351     { "(bad)",          { XX } },
9352     { "(bad)",          { XX } },
9353     { "(bad)",          { XX } },
9354   },
9355   {
9356     /* RM_0F01_REG_2 */
9357     { "xgetbv",         { Skip_MODRM } },
9358     { "xsetbv",         { Skip_MODRM } },
9359     { "(bad)",          { XX } },
9360     { "(bad)",          { XX } },
9361     { "(bad)",          { XX } },
9362     { "(bad)",          { XX } },
9363     { "(bad)",          { XX } },
9364     { "(bad)",          { XX } },
9365   },
9366   {
9367     /* RM_0F01_REG_3 */
9368     { "vmrun",          { Skip_MODRM } },
9369     { "vmmcall",        { Skip_MODRM } },
9370     { "vmload",         { Skip_MODRM } },
9371     { "vmsave",         { Skip_MODRM } },
9372     { "stgi",           { Skip_MODRM } },
9373     { "clgi",           { Skip_MODRM } },
9374     { "skinit",         { Skip_MODRM } },
9375     { "invlpga",        { Skip_MODRM } },
9376   },
9377   {
9378     /* RM_0F01_REG_7 */
9379     { "swapgs",         { Skip_MODRM } },
9380     { "rdtscp",         { Skip_MODRM } },
9381     { "(bad)",          { XX } },
9382     { "(bad)",          { XX } },
9383     { "(bad)",          { XX } },
9384     { "(bad)",          { XX } },
9385     { "(bad)",          { XX } },
9386     { "(bad)",          { XX } },
9387   },
9388   {
9389     /* RM_0FAE_REG_5 */
9390     { "lfence",         { Skip_MODRM } },
9391     { "(bad)",          { XX } },
9392     { "(bad)",          { XX } },
9393     { "(bad)",          { XX } },
9394     { "(bad)",          { XX } },
9395     { "(bad)",          { XX } },
9396     { "(bad)",          { XX } },
9397     { "(bad)",          { XX } },
9398   },
9399   {
9400     /* RM_0FAE_REG_6 */
9401     { "mfence",         { Skip_MODRM } },
9402     { "(bad)",          { XX } },
9403     { "(bad)",          { XX } },
9404     { "(bad)",          { XX } },
9405     { "(bad)",          { XX } },
9406     { "(bad)",          { XX } },
9407     { "(bad)",          { XX } },
9408     { "(bad)",          { XX } },
9409   },
9410   {
9411     /* RM_0FAE_REG_7 */
9412     { "sfence",         { Skip_MODRM } },
9413     { "(bad)",          { XX } },
9414     { "(bad)",          { XX } },
9415     { "(bad)",          { XX } },
9416     { "(bad)",          { XX } },
9417     { "(bad)",          { XX } },
9418     { "(bad)",          { XX } },
9419     { "(bad)",          { XX } },
9420   },
9421 };
9422
9423 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
9424
9425 static void
9426 ckprefix (void)
9427 {
9428   int newrex;
9429   rex = 0;
9430   rex_original = 0;
9431   rex_ignored = 0;
9432   prefixes = 0;
9433   used_prefixes = 0;
9434   rex_used = 0;
9435   while (1)
9436     {
9437       FETCH_DATA (the_info, codep + 1);
9438       newrex = 0;
9439       switch (*codep)
9440         {
9441         /* REX prefixes family.  */
9442         case 0x40:
9443         case 0x41:
9444         case 0x42:
9445         case 0x43:
9446         case 0x44:
9447         case 0x45:
9448         case 0x46:
9449         case 0x47:
9450         case 0x48:
9451         case 0x49:
9452         case 0x4a:
9453         case 0x4b:
9454         case 0x4c:
9455         case 0x4d:
9456         case 0x4e:
9457         case 0x4f:
9458             if (address_mode == mode_64bit)
9459               newrex = *codep;
9460             else
9461               return;
9462           break;
9463         case 0xf3:
9464           prefixes |= PREFIX_REPZ;
9465           break;
9466         case 0xf2:
9467           prefixes |= PREFIX_REPNZ;
9468           break;
9469         case 0xf0:
9470           prefixes |= PREFIX_LOCK;
9471           break;
9472         case 0x2e:
9473           prefixes |= PREFIX_CS;
9474           break;
9475         case 0x36:
9476           prefixes |= PREFIX_SS;
9477           break;
9478         case 0x3e:
9479           prefixes |= PREFIX_DS;
9480           break;
9481         case 0x26:
9482           prefixes |= PREFIX_ES;
9483           break;
9484         case 0x64:
9485           prefixes |= PREFIX_FS;
9486           break;
9487         case 0x65:
9488           prefixes |= PREFIX_GS;
9489           break;
9490         case 0x66:
9491           prefixes |= PREFIX_DATA;
9492           break;
9493         case 0x67:
9494           prefixes |= PREFIX_ADDR;
9495           break;
9496         case FWAIT_OPCODE:
9497           /* fwait is really an instruction.  If there are prefixes
9498              before the fwait, they belong to the fwait, *not* to the
9499              following instruction.  */
9500           if (prefixes || rex)
9501             {
9502               prefixes |= PREFIX_FWAIT;
9503               codep++;
9504               return;
9505             }
9506           prefixes = PREFIX_FWAIT;
9507           break;
9508         default:
9509           return;
9510         }
9511       /* Rex is ignored when followed by another prefix.  */
9512       if (rex)
9513         {
9514           rex_used = rex;
9515           return;
9516         }
9517       rex = newrex;
9518       rex_original = rex;
9519       codep++;
9520     }
9521 }
9522
9523 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
9524    prefix byte.  */
9525
9526 static const char *
9527 prefix_name (int pref, int sizeflag)
9528 {
9529   static const char *rexes [16] =
9530     {
9531       "rex",            /* 0x40 */
9532       "rex.B",          /* 0x41 */
9533       "rex.X",          /* 0x42 */
9534       "rex.XB",         /* 0x43 */
9535       "rex.R",          /* 0x44 */
9536       "rex.RB",         /* 0x45 */
9537       "rex.RX",         /* 0x46 */
9538       "rex.RXB",        /* 0x47 */
9539       "rex.W",          /* 0x48 */
9540       "rex.WB",         /* 0x49 */
9541       "rex.WX",         /* 0x4a */
9542       "rex.WXB",        /* 0x4b */
9543       "rex.WR",         /* 0x4c */
9544       "rex.WRB",        /* 0x4d */
9545       "rex.WRX",        /* 0x4e */
9546       "rex.WRXB",       /* 0x4f */
9547     };
9548
9549   switch (pref)
9550     {
9551     /* REX prefixes family.  */
9552     case 0x40:
9553     case 0x41:
9554     case 0x42:
9555     case 0x43:
9556     case 0x44:
9557     case 0x45:
9558     case 0x46:
9559     case 0x47:
9560     case 0x48:
9561     case 0x49:
9562     case 0x4a:
9563     case 0x4b:
9564     case 0x4c:
9565     case 0x4d:
9566     case 0x4e:
9567     case 0x4f:
9568       return rexes [pref - 0x40];
9569     case 0xf3:
9570       return "repz";
9571     case 0xf2:
9572       return "repnz";
9573     case 0xf0:
9574       return "lock";
9575     case 0x2e:
9576       return "cs";
9577     case 0x36:
9578       return "ss";
9579     case 0x3e:
9580       return "ds";
9581     case 0x26:
9582       return "es";
9583     case 0x64:
9584       return "fs";
9585     case 0x65:
9586       return "gs";
9587     case 0x66:
9588       return (sizeflag & DFLAG) ? "data16" : "data32";
9589     case 0x67:
9590       if (address_mode == mode_64bit)
9591         return (sizeflag & AFLAG) ? "addr32" : "addr64";
9592       else
9593         return (sizeflag & AFLAG) ? "addr16" : "addr32";
9594     case FWAIT_OPCODE:
9595       return "fwait";
9596     default:
9597       return NULL;
9598     }
9599 }
9600
9601 static char op_out[MAX_OPERANDS][100];
9602 static int op_ad, op_index[MAX_OPERANDS];
9603 static int two_source_ops;
9604 static bfd_vma op_address[MAX_OPERANDS];
9605 static bfd_vma op_riprel[MAX_OPERANDS];
9606 static bfd_vma start_pc;
9607
9608 /*
9609  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9610  *   (see topic "Redundant prefixes" in the "Differences from 8086"
9611  *   section of the "Virtual 8086 Mode" chapter.)
9612  * 'pc' should be the address of this instruction, it will
9613  *   be used to print the target address if this is a relative jump or call
9614  * The function returns the length of this instruction in bytes.
9615  */
9616
9617 static char intel_syntax;
9618 static char intel_mnemonic = !SYSV386_COMPAT;
9619 static char open_char;
9620 static char close_char;
9621 static char separator_char;
9622 static char scale_char;
9623
9624 /* Here for backwards compatibility.  When gdb stops using
9625    print_insn_i386_att and print_insn_i386_intel these functions can
9626    disappear, and print_insn_i386 be merged into print_insn.  */
9627 int
9628 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9629 {
9630   intel_syntax = 0;
9631
9632   return print_insn (pc, info);
9633 }
9634
9635 int
9636 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9637 {
9638   intel_syntax = 1;
9639
9640   return print_insn (pc, info);
9641 }
9642
9643 int
9644 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9645 {
9646   intel_syntax = -1;
9647
9648   return print_insn (pc, info);
9649 }
9650
9651 void
9652 print_i386_disassembler_options (FILE *stream)
9653 {
9654   fprintf (stream, _("\n\
9655 The following i386/x86-64 specific disassembler options are supported for use\n\
9656 with the -M switch (multiple options should be separated by commas):\n"));
9657
9658   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
9659   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
9660   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
9661   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
9662   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
9663   fprintf (stream, _("  att-mnemonic\n"
9664                      "              Display instruction in AT&T mnemonic\n"));
9665   fprintf (stream, _("  intel-mnemonic\n"
9666                      "              Display instruction in Intel mnemonic\n"));
9667   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
9668   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
9669   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
9670   fprintf (stream, _("  data32      Assume 32bit data size\n"));
9671   fprintf (stream, _("  data16      Assume 16bit data size\n"));
9672   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
9673 }
9674
9675 /* Get a pointer to struct dis386 with a valid name.  */
9676
9677 static const struct dis386 *
9678 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
9679 {
9680   int index, vex_table_index;
9681
9682   if (dp->name != NULL)
9683     return dp;
9684
9685   switch (dp->op[0].bytemode)
9686     {
9687     case USE_REG_TABLE:
9688       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9689       break;
9690
9691     case USE_MOD_TABLE:
9692       index = modrm.mod == 0x3 ? 1 : 0;
9693       dp = &mod_table[dp->op[1].bytemode][index];
9694       break;
9695
9696     case USE_RM_TABLE:
9697       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9698       break;
9699
9700     case USE_PREFIX_TABLE:
9701       if (need_vex)
9702         {
9703           /* The prefix in VEX is implicit.  */
9704           switch (vex.prefix)
9705             {
9706             case 0:
9707               index = 0;
9708               break;
9709             case REPE_PREFIX_OPCODE:
9710               index = 1;
9711               break;
9712             case DATA_PREFIX_OPCODE:
9713               index = 2;
9714               break;
9715             case REPNE_PREFIX_OPCODE:
9716               index = 3;
9717               break;
9718             default:
9719               abort ();
9720               break;
9721             }
9722         }
9723       else
9724         {
9725           index = 0;
9726           used_prefixes |= (prefixes & PREFIX_REPZ);
9727           if (prefixes & PREFIX_REPZ)
9728             {
9729               index = 1;
9730               repz_prefix = NULL;
9731             }
9732           else
9733             {
9734               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
9735                  PREFIX_DATA.  */
9736               used_prefixes |= (prefixes & PREFIX_REPNZ);
9737               if (prefixes & PREFIX_REPNZ)
9738                 {
9739                   index = 3;
9740                   repnz_prefix = NULL;
9741                 }
9742               else
9743                 {
9744                   used_prefixes |= (prefixes & PREFIX_DATA);
9745                   if (prefixes & PREFIX_DATA)
9746                     {
9747                       index = 2;
9748                       data_prefix = NULL;
9749                     }
9750                 }
9751             }
9752         }
9753       dp = &prefix_table[dp->op[1].bytemode][index];
9754       break;
9755
9756     case USE_X86_64_TABLE:
9757       index = address_mode == mode_64bit ? 1 : 0;
9758       dp = &x86_64_table[dp->op[1].bytemode][index];
9759       break;
9760
9761     case USE_3BYTE_TABLE:
9762       FETCH_DATA (info, codep + 2);
9763       index = *codep++;
9764       dp = &three_byte_table[dp->op[1].bytemode][index];
9765       modrm.mod = (*codep >> 6) & 3;
9766       modrm.reg = (*codep >> 3) & 7;
9767       modrm.rm = *codep & 7;
9768       break;
9769
9770     case USE_VEX_LEN_TABLE:
9771       if (!need_vex)
9772         abort ();
9773
9774       switch (vex.length)
9775         {
9776         case 128:
9777           index = 0;
9778           break;
9779         case 256:
9780           index = 1;
9781           break;
9782         default:
9783           abort ();
9784           break;
9785         }
9786
9787       dp = &vex_len_table[dp->op[1].bytemode][index];
9788       break;
9789
9790     case USE_VEX_C4_TABLE:
9791       FETCH_DATA (info, codep + 3);
9792       /* All bits in the REX prefix are ignored.  */
9793       rex_ignored = rex;
9794       rex = ~(*codep >> 5) & 0x7;
9795       switch ((*codep & 0x1f))
9796         {
9797         default:
9798           BadOp ();
9799         case 0x1:
9800           vex_table_index = 0;
9801           break;
9802         case 0x2:
9803           vex_table_index = 1;
9804           break;
9805         case 0x3:
9806           vex_table_index = 2;
9807           break;
9808         }
9809       codep++;
9810       vex.w = *codep & 0x80;
9811       if (vex.w && address_mode == mode_64bit)
9812         rex |= REX_W;
9813
9814       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9815       if (address_mode != mode_64bit
9816           && vex.register_specifier > 0x7)
9817         BadOp ();
9818
9819       vex.length = (*codep & 0x4) ? 256 : 128;
9820       switch ((*codep & 0x3))
9821         {
9822         case 0:
9823           vex.prefix = 0;
9824           break;
9825         case 1:
9826           vex.prefix = DATA_PREFIX_OPCODE;
9827           break;
9828         case 2:
9829           vex.prefix = REPE_PREFIX_OPCODE;
9830           break;
9831         case 3:
9832           vex.prefix = REPNE_PREFIX_OPCODE;
9833           break;
9834         }
9835       need_vex = 1;
9836       need_vex_reg = 1;
9837       codep++;
9838       index = *codep++;
9839       dp = &vex_table[vex_table_index][index];
9840       /* There is no MODRM byte for VEX [82|77].  */
9841       if (index != 0x77 && index != 0x82)
9842         {
9843           FETCH_DATA (info, codep + 1);
9844           modrm.mod = (*codep >> 6) & 3;
9845           modrm.reg = (*codep >> 3) & 7;
9846           modrm.rm = *codep & 7;
9847         }
9848       break;
9849
9850     case USE_VEX_C5_TABLE:
9851       FETCH_DATA (info, codep + 2);
9852       /* All bits in the REX prefix are ignored.  */
9853       rex_ignored = rex;
9854       rex = (*codep & 0x80) ? 0 : REX_R;
9855
9856       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9857       if (address_mode != mode_64bit
9858           && vex.register_specifier > 0x7)
9859         BadOp ();
9860
9861       vex.length = (*codep & 0x4) ? 256 : 128;
9862       switch ((*codep & 0x3))
9863         {
9864         case 0:
9865           vex.prefix = 0;
9866           break;
9867         case 1:
9868           vex.prefix = DATA_PREFIX_OPCODE;
9869           break;
9870         case 2:
9871           vex.prefix = REPE_PREFIX_OPCODE;
9872           break;
9873         case 3:
9874           vex.prefix = REPNE_PREFIX_OPCODE;
9875           break;
9876         }
9877       need_vex = 1;
9878       need_vex_reg = 1;
9879       codep++;
9880       index = *codep++;
9881       dp = &vex_table[dp->op[1].bytemode][index];
9882       /* There is no MODRM byte for VEX [82|77].  */
9883       if (index != 0x77 && index != 0x82)
9884         {
9885           FETCH_DATA (info, codep + 1);
9886           modrm.mod = (*codep >> 6) & 3;
9887           modrm.reg = (*codep >> 3) & 7;
9888           modrm.rm = *codep & 7;
9889         }
9890       break;
9891
9892     default:
9893       oappend (INTERNAL_DISASSEMBLER_ERROR);
9894       return NULL;
9895     }
9896
9897   if (dp->name != NULL)
9898     return dp;
9899   else
9900     return get_valid_dis386 (dp, info);
9901 }
9902
9903 static int
9904 print_insn (bfd_vma pc, disassemble_info *info)
9905 {
9906   const struct dis386 *dp;
9907   int i;
9908   char *op_txt[MAX_OPERANDS];
9909   int needcomma;
9910   int sizeflag;
9911   const char *p;
9912   struct dis_private priv;
9913   unsigned char op;
9914   char prefix_obuf[32];
9915   char *prefix_obufp;
9916
9917   if (info->mach == bfd_mach_x86_64_intel_syntax
9918       || info->mach == bfd_mach_x86_64)
9919     address_mode = mode_64bit;
9920   else
9921     address_mode = mode_32bit;
9922
9923   if (intel_syntax == (char) -1)
9924     intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
9925                     || info->mach == bfd_mach_x86_64_intel_syntax);
9926
9927   if (info->mach == bfd_mach_i386_i386
9928       || info->mach == bfd_mach_x86_64
9929       || info->mach == bfd_mach_i386_i386_intel_syntax
9930       || info->mach == bfd_mach_x86_64_intel_syntax)
9931     priv.orig_sizeflag = AFLAG | DFLAG;
9932   else if (info->mach == bfd_mach_i386_i8086)
9933     priv.orig_sizeflag = 0;
9934   else
9935     abort ();
9936
9937   for (p = info->disassembler_options; p != NULL; )
9938     {
9939       if (CONST_STRNEQ (p, "x86-64"))
9940         {
9941           address_mode = mode_64bit;
9942           priv.orig_sizeflag = AFLAG | DFLAG;
9943         }
9944       else if (CONST_STRNEQ (p, "i386"))
9945         {
9946           address_mode = mode_32bit;
9947           priv.orig_sizeflag = AFLAG | DFLAG;
9948         }
9949       else if (CONST_STRNEQ (p, "i8086"))
9950         {
9951           address_mode = mode_16bit;
9952           priv.orig_sizeflag = 0;
9953         }
9954       else if (CONST_STRNEQ (p, "intel"))
9955         {
9956           intel_syntax = 1;
9957           if (CONST_STRNEQ (p + 5, "-mnemonic"))
9958             intel_mnemonic = 1;
9959         }
9960       else if (CONST_STRNEQ (p, "att"))
9961         {
9962           intel_syntax = 0;
9963           if (CONST_STRNEQ (p + 3, "-mnemonic"))
9964             intel_mnemonic = 0;
9965         }
9966       else if (CONST_STRNEQ (p, "addr"))
9967         {
9968           if (address_mode == mode_64bit)
9969             {
9970               if (p[4] == '3' && p[5] == '2')
9971                 priv.orig_sizeflag &= ~AFLAG;
9972               else if (p[4] == '6' && p[5] == '4')
9973                 priv.orig_sizeflag |= AFLAG;
9974             }
9975           else
9976             {
9977               if (p[4] == '1' && p[5] == '6')
9978                 priv.orig_sizeflag &= ~AFLAG;
9979               else if (p[4] == '3' && p[5] == '2')
9980                 priv.orig_sizeflag |= AFLAG;
9981             }
9982         }
9983       else if (CONST_STRNEQ (p, "data"))
9984         {
9985           if (p[4] == '1' && p[5] == '6')
9986             priv.orig_sizeflag &= ~DFLAG;
9987           else if (p[4] == '3' && p[5] == '2')
9988             priv.orig_sizeflag |= DFLAG;
9989         }
9990       else if (CONST_STRNEQ (p, "suffix"))
9991         priv.orig_sizeflag |= SUFFIX_ALWAYS;
9992
9993       p = strchr (p, ',');
9994       if (p != NULL)
9995         p++;
9996     }
9997
9998   if (intel_syntax)
9999     {
10000       names64 = intel_names64;
10001       names32 = intel_names32;
10002       names16 = intel_names16;
10003       names8 = intel_names8;
10004       names8rex = intel_names8rex;
10005       names_seg = intel_names_seg;
10006       index64 = intel_index64;
10007       index32 = intel_index32;
10008       index16 = intel_index16;
10009       open_char = '[';
10010       close_char = ']';
10011       separator_char = '+';
10012       scale_char = '*';
10013     }
10014   else
10015     {
10016       names64 = att_names64;
10017       names32 = att_names32;
10018       names16 = att_names16;
10019       names8 = att_names8;
10020       names8rex = att_names8rex;
10021       names_seg = att_names_seg;
10022       index64 = att_index64;
10023       index32 = att_index32;
10024       index16 = att_index16;
10025       open_char = '(';
10026       close_char =  ')';
10027       separator_char = ',';
10028       scale_char = ',';
10029     }
10030
10031   /* The output looks better if we put 7 bytes on a line, since that
10032      puts most long word instructions on a single line.  */
10033   info->bytes_per_line = 7;
10034
10035   info->private_data = &priv;
10036   priv.max_fetched = priv.the_buffer;
10037   priv.insn_start = pc;
10038
10039   obuf[0] = 0;
10040   for (i = 0; i < MAX_OPERANDS; ++i)
10041     {
10042       op_out[i][0] = 0;
10043       op_index[i] = -1;
10044     }
10045
10046   the_info = info;
10047   start_pc = pc;
10048   start_codep = priv.the_buffer;
10049   codep = priv.the_buffer;
10050
10051   if (setjmp (priv.bailout) != 0)
10052     {
10053       const char *name;
10054
10055       /* Getting here means we tried for data but didn't get it.  That
10056          means we have an incomplete instruction of some sort.  Just
10057          print the first byte as a prefix or a .byte pseudo-op.  */
10058       if (codep > priv.the_buffer)
10059         {
10060           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10061           if (name != NULL)
10062             (*info->fprintf_func) (info->stream, "%s", name);
10063           else
10064             {
10065               /* Just print the first byte as a .byte instruction.  */
10066               (*info->fprintf_func) (info->stream, ".byte 0x%x",
10067                                      (unsigned int) priv.the_buffer[0]);
10068             }
10069
10070           return 1;
10071         }
10072
10073       return -1;
10074     }
10075
10076   obufp = obuf;
10077   ckprefix ();
10078
10079   insn_codep = codep;
10080   sizeflag = priv.orig_sizeflag;
10081
10082   FETCH_DATA (info, codep + 1);
10083   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
10084
10085   if (((prefixes & PREFIX_FWAIT)
10086        && ((*codep < 0xd8) || (*codep > 0xdf)))
10087       || (rex && rex_used))
10088     {
10089       const char *name;
10090
10091       /* fwait not followed by floating point instruction, or rex followed
10092          by other prefixes.  Print the first prefix.  */
10093       name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10094       if (name == NULL)
10095         name = INTERNAL_DISASSEMBLER_ERROR;
10096       (*info->fprintf_func) (info->stream, "%s", name);
10097       return 1;
10098     }
10099
10100   op = 0;
10101   if (*codep == 0x0f)
10102     {
10103       unsigned char threebyte;
10104       FETCH_DATA (info, codep + 2);
10105       threebyte = *++codep;
10106       dp = &dis386_twobyte[threebyte];
10107       need_modrm = twobyte_has_modrm[*codep];
10108       codep++;
10109     }
10110   else
10111     {
10112       dp = &dis386[*codep];
10113       need_modrm = onebyte_has_modrm[*codep];
10114       codep++;
10115     }
10116
10117   if ((prefixes & PREFIX_REPZ))
10118     {
10119       repz_prefix = "repz ";
10120       used_prefixes |= PREFIX_REPZ;
10121     }
10122   else
10123     repz_prefix = NULL;
10124
10125   if ((prefixes & PREFIX_REPNZ))
10126     {
10127       repnz_prefix = "repnz ";
10128       used_prefixes |= PREFIX_REPNZ;
10129     }
10130   else
10131     repnz_prefix = NULL;
10132
10133   if ((prefixes & PREFIX_LOCK))
10134     {
10135       lock_prefix = "lock ";
10136       used_prefixes |= PREFIX_LOCK;
10137     }
10138   else
10139     lock_prefix = NULL;
10140
10141   addr_prefix = NULL;
10142   if (prefixes & PREFIX_ADDR)
10143     {
10144       sizeflag ^= AFLAG;
10145       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
10146         {
10147           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
10148             addr_prefix = "addr32 ";
10149           else
10150             addr_prefix = "addr16 ";
10151           used_prefixes |= PREFIX_ADDR;
10152         }
10153     }
10154
10155   data_prefix = NULL;
10156   if ((prefixes & PREFIX_DATA))
10157     {
10158       sizeflag ^= DFLAG;
10159       if (dp->op[2].bytemode == cond_jump_mode
10160           && dp->op[0].bytemode == v_mode
10161           && !intel_syntax)
10162         {
10163           if (sizeflag & DFLAG)
10164             data_prefix = "data32 ";
10165           else
10166             data_prefix = "data16 ";
10167           used_prefixes |= PREFIX_DATA;
10168         }
10169     }
10170
10171   if (need_modrm)
10172     {
10173       FETCH_DATA (info, codep + 1);
10174       modrm.mod = (*codep >> 6) & 3;
10175       modrm.reg = (*codep >> 3) & 7;
10176       modrm.rm = *codep & 7;
10177     }
10178
10179   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
10180     {
10181       dofloat (sizeflag);
10182     }
10183   else
10184     {
10185       need_vex = 0;
10186       need_vex_reg = 0;
10187       vex_i4_done = 0;
10188       dp = get_valid_dis386 (dp, info);
10189       if (dp != NULL && putop (dp->name, sizeflag) == 0)
10190         {
10191           for (i = 0; i < MAX_OPERANDS; ++i)
10192             {
10193               obufp = op_out[i];
10194               op_ad = MAX_OPERANDS - 1 - i;
10195               if (dp->op[i].rtn)
10196                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
10197             }
10198         }
10199     }
10200
10201   /* See if any prefixes were not used.  If so, print the first one
10202      separately.  If we don't do this, we'll wind up printing an
10203      instruction stream which does not precisely correspond to the
10204      bytes we are disassembling.  */
10205   if ((prefixes & ~used_prefixes) != 0)
10206     {
10207       const char *name;
10208
10209       name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10210       if (name == NULL)
10211         name = INTERNAL_DISASSEMBLER_ERROR;
10212       (*info->fprintf_func) (info->stream, "%s", name);
10213       return 1;
10214     }
10215   if ((rex_original & ~rex_used) || rex_ignored)
10216     {
10217       const char *name;
10218       name = prefix_name (rex_original, priv.orig_sizeflag);
10219       if (name == NULL)
10220         name = INTERNAL_DISASSEMBLER_ERROR;
10221       (*info->fprintf_func) (info->stream, "%s ", name);
10222     }
10223
10224   prefix_obuf[0] = 0;
10225   prefix_obufp = prefix_obuf;
10226   if (lock_prefix)
10227     prefix_obufp = stpcpy (prefix_obufp, lock_prefix);
10228   if (repz_prefix)
10229     prefix_obufp = stpcpy (prefix_obufp, repz_prefix);
10230   if (repnz_prefix)
10231     prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);
10232   if (addr_prefix)
10233     prefix_obufp = stpcpy (prefix_obufp, addr_prefix);
10234   if (data_prefix)
10235     prefix_obufp = stpcpy (prefix_obufp, data_prefix);
10236
10237   if (prefix_obuf[0] != 0)
10238     (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
10239
10240   obufp = obuf + strlen (obuf);
10241   for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
10242     oappend (" ");
10243   oappend (" ");
10244   (*info->fprintf_func) (info->stream, "%s", obuf);
10245
10246   /* The enter and bound instructions are printed with operands in the same
10247      order as the intel book; everything else is printed in reverse order.  */
10248   if (intel_syntax || two_source_ops)
10249     {
10250       bfd_vma riprel;
10251
10252       for (i = 0; i < MAX_OPERANDS; ++i)
10253         op_txt[i] = op_out[i];
10254
10255       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10256         {
10257           op_ad = op_index[i];
10258           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
10259           op_index[MAX_OPERANDS - 1 - i] = op_ad;
10260           riprel = op_riprel[i];
10261           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
10262           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10263         }
10264     }
10265   else
10266     {
10267       for (i = 0; i < MAX_OPERANDS; ++i)
10268         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
10269     }
10270
10271   needcomma = 0;
10272   for (i = 0; i < MAX_OPERANDS; ++i)
10273     if (*op_txt[i])
10274       {
10275         if (needcomma)
10276           (*info->fprintf_func) (info->stream, ",");
10277         if (op_index[i] != -1 && !op_riprel[i])
10278           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
10279         else
10280           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
10281         needcomma = 1;
10282       }
10283
10284   for (i = 0; i < MAX_OPERANDS; i++)
10285     if (op_index[i] != -1 && op_riprel[i])
10286       {
10287         (*info->fprintf_func) (info->stream, "        # ");
10288         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
10289                                                 + op_address[op_index[i]]), info);
10290         break;
10291       }
10292   return codep - priv.the_buffer;
10293 }
10294
10295 static const char *float_mem[] = {
10296   /* d8 */
10297   "fadd{s|}",
10298   "fmul{s|}",
10299   "fcom{s|}",
10300   "fcomp{s|}",
10301   "fsub{s|}",
10302   "fsubr{s|}",
10303   "fdiv{s|}",
10304   "fdivr{s|}",
10305   /* d9 */
10306   "fld{s|}",
10307   "(bad)",
10308   "fst{s|}",
10309   "fstp{s|}",
10310   "fldenvIC",
10311   "fldcw",
10312   "fNstenvIC",
10313   "fNstcw",
10314   /* da */
10315   "fiadd{l|}",
10316   "fimul{l|}",
10317   "ficom{l|}",
10318   "ficomp{l|}",
10319   "fisub{l|}",
10320   "fisubr{l|}",
10321   "fidiv{l|}",
10322   "fidivr{l|}",
10323   /* db */
10324   "fild{l|}",
10325   "fisttp{l|}",
10326   "fist{l|}",
10327   "fistp{l|}",
10328   "(bad)",
10329   "fld{t||t|}",
10330   "(bad)",
10331   "fstp{t||t|}",
10332   /* dc */
10333   "fadd{l|}",
10334   "fmul{l|}",
10335   "fcom{l|}",
10336   "fcomp{l|}",
10337   "fsub{l|}",
10338   "fsubr{l|}",
10339   "fdiv{l|}",
10340   "fdivr{l|}",
10341   /* dd */
10342   "fld{l|}",
10343   "fisttp{ll|}",
10344   "fst{l||}",
10345   "fstp{l|}",
10346   "frstorIC",
10347   "(bad)",
10348   "fNsaveIC",
10349   "fNstsw",
10350   /* de */
10351   "fiadd",
10352   "fimul",
10353   "ficom",
10354   "ficomp",
10355   "fisub",
10356   "fisubr",
10357   "fidiv",
10358   "fidivr",
10359   /* df */
10360   "fild",
10361   "fisttp",
10362   "fist",
10363   "fistp",
10364   "fbld",
10365   "fild{ll|}",
10366   "fbstp",
10367   "fistp{ll|}",
10368 };
10369
10370 static const unsigned char float_mem_mode[] = {
10371   /* d8 */
10372   d_mode,
10373   d_mode,
10374   d_mode,
10375   d_mode,
10376   d_mode,
10377   d_mode,
10378   d_mode,
10379   d_mode,
10380   /* d9 */
10381   d_mode,
10382   0,
10383   d_mode,
10384   d_mode,
10385   0,
10386   w_mode,
10387   0,
10388   w_mode,
10389   /* da */
10390   d_mode,
10391   d_mode,
10392   d_mode,
10393   d_mode,
10394   d_mode,
10395   d_mode,
10396   d_mode,
10397   d_mode,
10398   /* db */
10399   d_mode,
10400   d_mode,
10401   d_mode,
10402   d_mode,
10403   0,
10404   t_mode,
10405   0,
10406   t_mode,
10407   /* dc */
10408   q_mode,
10409   q_mode,
10410   q_mode,
10411   q_mode,
10412   q_mode,
10413   q_mode,
10414   q_mode,
10415   q_mode,
10416   /* dd */
10417   q_mode,
10418   q_mode,
10419   q_mode,
10420   q_mode,
10421   0,
10422   0,
10423   0,
10424   w_mode,
10425   /* de */
10426   w_mode,
10427   w_mode,
10428   w_mode,
10429   w_mode,
10430   w_mode,
10431   w_mode,
10432   w_mode,
10433   w_mode,
10434   /* df */
10435   w_mode,
10436   w_mode,
10437   w_mode,
10438   w_mode,
10439   t_mode,
10440   q_mode,
10441   t_mode,
10442   q_mode
10443 };
10444
10445 #define ST { OP_ST, 0 }
10446 #define STi { OP_STi, 0 }
10447
10448 #define FGRPd9_2 NULL, { { NULL, 0 } }
10449 #define FGRPd9_4 NULL, { { NULL, 1 } }
10450 #define FGRPd9_5 NULL, { { NULL, 2 } }
10451 #define FGRPd9_6 NULL, { { NULL, 3 } }
10452 #define FGRPd9_7 NULL, { { NULL, 4 } }
10453 #define FGRPda_5 NULL, { { NULL, 5 } }
10454 #define FGRPdb_4 NULL, { { NULL, 6 } }
10455 #define FGRPde_3 NULL, { { NULL, 7 } }
10456 #define FGRPdf_4 NULL, { { NULL, 8 } }
10457
10458 static const struct dis386 float_reg[][8] = {
10459   /* d8 */
10460   {
10461     { "fadd",   { ST, STi } },
10462     { "fmul",   { ST, STi } },
10463     { "fcom",   { STi } },
10464     { "fcomp",  { STi } },
10465     { "fsub",   { ST, STi } },
10466     { "fsubr",  { ST, STi } },
10467     { "fdiv",   { ST, STi } },
10468     { "fdivr",  { ST, STi } },
10469   },
10470   /* d9 */
10471   {
10472     { "fld",    { STi } },
10473     { "fxch",   { STi } },
10474     { FGRPd9_2 },
10475     { "(bad)",  { XX } },
10476     { FGRPd9_4 },
10477     { FGRPd9_5 },
10478     { FGRPd9_6 },
10479     { FGRPd9_7 },
10480   },
10481   /* da */
10482   {
10483     { "fcmovb", { ST, STi } },
10484     { "fcmove", { ST, STi } },
10485     { "fcmovbe",{ ST, STi } },
10486     { "fcmovu", { ST, STi } },
10487     { "(bad)",  { XX } },
10488     { FGRPda_5 },
10489     { "(bad)",  { XX } },
10490     { "(bad)",  { XX } },
10491   },
10492   /* db */
10493   {
10494     { "fcmovnb",{ ST, STi } },
10495     { "fcmovne",{ ST, STi } },
10496     { "fcmovnbe",{ ST, STi } },
10497     { "fcmovnu",{ ST, STi } },
10498     { FGRPdb_4 },
10499     { "fucomi", { ST, STi } },
10500     { "fcomi",  { ST, STi } },
10501     { "(bad)",  { XX } },
10502   },
10503   /* dc */
10504   {
10505     { "fadd",   { STi, ST } },
10506     { "fmul",   { STi, ST } },
10507     { "(bad)",  { XX } },
10508     { "(bad)",  { XX } },
10509     { "fsub!M", { STi, ST } },
10510     { "fsubM",  { STi, ST } },
10511     { "fdiv!M", { STi, ST } },
10512     { "fdivM",  { STi, ST } },
10513   },
10514   /* dd */
10515   {
10516     { "ffree",  { STi } },
10517     { "(bad)",  { XX } },
10518     { "fst",    { STi } },
10519     { "fstp",   { STi } },
10520     { "fucom",  { STi } },
10521     { "fucomp", { STi } },
10522     { "(bad)",  { XX } },
10523     { "(bad)",  { XX } },
10524   },
10525   /* de */
10526   {
10527     { "faddp",  { STi, ST } },
10528     { "fmulp",  { STi, ST } },
10529     { "(bad)",  { XX } },
10530     { FGRPde_3 },
10531     { "fsub!Mp", { STi, ST } },
10532     { "fsubMp", { STi, ST } },
10533     { "fdiv!Mp", { STi, ST } },
10534     { "fdivMp", { STi, ST } },
10535   },
10536   /* df */
10537   {
10538     { "ffreep", { STi } },
10539     { "(bad)",  { XX } },
10540     { "(bad)",  { XX } },
10541     { "(bad)",  { XX } },
10542     { FGRPdf_4 },
10543     { "fucomip", { ST, STi } },
10544     { "fcomip", { ST, STi } },
10545     { "(bad)",  { XX } },
10546   },
10547 };
10548
10549 static char *fgrps[][8] = {
10550   /* d9_2  0 */
10551   {
10552     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10553   },
10554
10555   /* d9_4  1 */
10556   {
10557     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10558   },
10559
10560   /* d9_5  2 */
10561   {
10562     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10563   },
10564
10565   /* d9_6  3 */
10566   {
10567     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10568   },
10569
10570   /* d9_7  4 */
10571   {
10572     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10573   },
10574
10575   /* da_5  5 */
10576   {
10577     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10578   },
10579
10580   /* db_4  6 */
10581   {
10582     "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
10583     "fNsetpm(287 only)","(bad)","(bad)","(bad)",
10584   },
10585
10586   /* de_3  7 */
10587   {
10588     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10589   },
10590
10591   /* df_4  8 */
10592   {
10593     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10594   },
10595 };
10596
10597 static void
10598 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10599                int sizeflag ATTRIBUTE_UNUSED)
10600 {
10601   /* Skip mod/rm byte.  */
10602   MODRM_CHECK;
10603   codep++;
10604 }
10605
10606 static void
10607 dofloat (int sizeflag)
10608 {
10609   const struct dis386 *dp;
10610   unsigned char floatop;
10611
10612   floatop = codep[-1];
10613
10614   if (modrm.mod != 3)
10615     {
10616       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10617
10618       putop (float_mem[fp_indx], sizeflag);
10619       obufp = op_out[0];
10620       op_ad = 2;
10621       OP_E (float_mem_mode[fp_indx], sizeflag);
10622       return;
10623     }
10624   /* Skip mod/rm byte.  */
10625   MODRM_CHECK;
10626   codep++;
10627
10628   dp = &float_reg[floatop - 0xd8][modrm.reg];
10629   if (dp->name == NULL)
10630     {
10631       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10632
10633       /* Instruction fnstsw is only one with strange arg.  */
10634       if (floatop == 0xdf && codep[-1] == 0xe0)
10635         strcpy (op_out[0], names16[0]);
10636     }
10637   else
10638     {
10639       putop (dp->name, sizeflag);
10640
10641       obufp = op_out[0];
10642       op_ad = 2;
10643       if (dp->op[0].rtn)
10644         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10645
10646       obufp = op_out[1];
10647       op_ad = 1;
10648       if (dp->op[1].rtn)
10649         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10650     }
10651 }
10652
10653 static void
10654 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10655 {
10656   oappend ("%st" + intel_syntax);
10657 }
10658
10659 static void
10660 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10661 {
10662   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10663   oappend (scratchbuf + intel_syntax);
10664 }
10665
10666 /* Capital letters in template are macros.  */
10667 static int
10668 putop (const char *template, int sizeflag)
10669 {
10670   const char *p;
10671   int alt = 0;
10672   int cond = 1;
10673   unsigned int l = 0, len = 1;
10674   char last[4];
10675
10676 #define SAVE_LAST(c)                    \
10677   if (l < len && l < sizeof (last))     \
10678     last[l++] = c;                      \
10679   else                                  \
10680     abort ();
10681
10682   for (p = template; *p; p++)
10683     {
10684       switch (*p)
10685         {
10686         default:
10687           *obufp++ = *p;
10688           break;
10689         case '%':
10690           len++;
10691           break;
10692         case '!':
10693           cond = 0;
10694           break;
10695         case '{':
10696           alt = 0;
10697           if (intel_syntax)
10698             {
10699               while (*++p != '|')
10700                 if (*p == '}' || *p == '\0')
10701                   abort ();
10702             }
10703           /* Fall through.  */
10704         case 'I':
10705           alt = 1;
10706           continue;
10707         case '|':
10708           while (*++p != '}')
10709             {
10710               if (*p == '\0')
10711                 abort ();
10712             }
10713           break;
10714         case '}':
10715           break;
10716         case 'A':
10717           if (intel_syntax)
10718             break;
10719           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10720             *obufp++ = 'b';
10721           break;
10722         case 'B':
10723           if (intel_syntax)
10724             break;
10725           if (sizeflag & SUFFIX_ALWAYS)
10726             *obufp++ = 'b';
10727           break;
10728         case 'C':
10729           if (intel_syntax && !alt)
10730             break;
10731           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10732             {
10733               if (sizeflag & DFLAG)
10734                 *obufp++ = intel_syntax ? 'd' : 'l';
10735               else
10736                 *obufp++ = intel_syntax ? 'w' : 's';
10737               used_prefixes |= (prefixes & PREFIX_DATA);
10738             }
10739           break;
10740         case 'D':
10741           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10742             break;
10743           USED_REX (REX_W);
10744           if (modrm.mod == 3)
10745             {
10746               if (rex & REX_W)
10747                 *obufp++ = 'q';
10748               else if (sizeflag & DFLAG)
10749                 *obufp++ = intel_syntax ? 'd' : 'l';
10750               else
10751                 *obufp++ = 'w';
10752               used_prefixes |= (prefixes & PREFIX_DATA);
10753             }
10754           else
10755             *obufp++ = 'w';
10756           break;
10757         case 'E':               /* For jcxz/jecxz */
10758           if (address_mode == mode_64bit)
10759             {
10760               if (sizeflag & AFLAG)
10761                 *obufp++ = 'r';
10762               else
10763                 *obufp++ = 'e';
10764             }
10765           else
10766             if (sizeflag & AFLAG)
10767               *obufp++ = 'e';
10768           used_prefixes |= (prefixes & PREFIX_ADDR);
10769           break;
10770         case 'F':
10771           if (intel_syntax)
10772             break;
10773           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10774             {
10775               if (sizeflag & AFLAG)
10776                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10777               else
10778                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10779               used_prefixes |= (prefixes & PREFIX_ADDR);
10780             }
10781           break;
10782         case 'G':
10783           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10784             break;
10785           if ((rex & REX_W) || (sizeflag & DFLAG))
10786             *obufp++ = 'l';
10787           else
10788             *obufp++ = 'w';
10789           if (!(rex & REX_W))
10790             used_prefixes |= (prefixes & PREFIX_DATA);
10791           break;
10792         case 'H':
10793           if (intel_syntax)
10794             break;
10795           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10796               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10797             {
10798               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10799               *obufp++ = ',';
10800               *obufp++ = 'p';
10801               if (prefixes & PREFIX_DS)
10802                 *obufp++ = 't';
10803               else
10804                 *obufp++ = 'n';
10805             }
10806           break;
10807         case 'J':
10808           if (intel_syntax)
10809             break;
10810           *obufp++ = 'l';
10811           break;
10812         case 'K':
10813           USED_REX (REX_W);
10814           if (rex & REX_W)
10815             *obufp++ = 'q';
10816           else
10817             *obufp++ = 'd';
10818           break;
10819         case 'Z':
10820           if (intel_syntax)
10821             break;
10822           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
10823             {
10824               *obufp++ = 'q';
10825               break;
10826             }
10827           /* Fall through.  */
10828           goto case_L;
10829         case 'L':
10830           if (l != 0 || len != 1)
10831             {
10832               SAVE_LAST (*p);
10833               break;
10834             }
10835 case_L:
10836           if (intel_syntax)
10837             break;
10838           if (sizeflag & SUFFIX_ALWAYS)
10839             *obufp++ = 'l';
10840           break;
10841         case 'M':
10842           if (intel_mnemonic != cond)
10843             *obufp++ = 'r';
10844           break;
10845         case 'N':
10846           if ((prefixes & PREFIX_FWAIT) == 0)
10847             *obufp++ = 'n';
10848           else
10849             used_prefixes |= PREFIX_FWAIT;
10850           break;
10851         case 'O':
10852           USED_REX (REX_W);
10853           if (rex & REX_W)
10854             *obufp++ = 'o';
10855           else if (intel_syntax && (sizeflag & DFLAG))
10856             *obufp++ = 'q';
10857           else
10858             *obufp++ = 'd';
10859           if (!(rex & REX_W))
10860             used_prefixes |= (prefixes & PREFIX_DATA);
10861           break;
10862         case 'T':
10863           if (intel_syntax)
10864             break;
10865           if (address_mode == mode_64bit && (sizeflag & DFLAG))
10866             {
10867               *obufp++ = 'q';
10868               break;
10869             }
10870           /* Fall through.  */
10871         case 'P':
10872           if (intel_syntax)
10873             break;
10874           if ((prefixes & PREFIX_DATA)
10875               || (rex & REX_W)
10876               || (sizeflag & SUFFIX_ALWAYS))
10877             {
10878               USED_REX (REX_W);
10879               if (rex & REX_W)
10880                 *obufp++ = 'q';
10881               else
10882                 {
10883                    if (sizeflag & DFLAG)
10884                       *obufp++ = 'l';
10885                    else
10886                      *obufp++ = 'w';
10887                 }
10888               used_prefixes |= (prefixes & PREFIX_DATA);
10889             }
10890           break;
10891         case 'U':
10892           if (intel_syntax)
10893             break;
10894           if (address_mode == mode_64bit && (sizeflag & DFLAG))
10895             {
10896               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10897                 *obufp++ = 'q';
10898               break;
10899             }
10900           /* Fall through.  */
10901           goto case_Q;
10902         case 'Q':
10903           if (l == 0 && len == 1)
10904             {
10905 case_Q:
10906               if (intel_syntax && !alt)
10907                 break;
10908               USED_REX (REX_W);
10909               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10910                 {
10911                   if (rex & REX_W)
10912                     *obufp++ = 'q';
10913                   else
10914                     {
10915                       if (sizeflag & DFLAG)
10916                         *obufp++ = intel_syntax ? 'd' : 'l';
10917                       else
10918                         *obufp++ = 'w';
10919                     }
10920                   used_prefixes |= (prefixes & PREFIX_DATA);
10921                 }
10922             }
10923           else
10924             {
10925               if (l != 1 || len != 2 || last[0] != 'L')
10926                 {
10927                   SAVE_LAST (*p);
10928                   break;
10929                 }
10930               if (intel_syntax
10931                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
10932                 break;
10933               if ((rex & REX_W))
10934                 {
10935                   USED_REX (REX_W);
10936                   *obufp++ = 'q';
10937                 }
10938               else
10939                 *obufp++ = 'l';
10940             }
10941           break;
10942         case 'R':
10943           USED_REX (REX_W);
10944           if (rex & REX_W)
10945             *obufp++ = 'q';
10946           else if (sizeflag & DFLAG)
10947             {
10948               if (intel_syntax)
10949                   *obufp++ = 'd';
10950               else
10951                   *obufp++ = 'l';
10952             }
10953           else
10954             *obufp++ = 'w';
10955           if (intel_syntax && !p[1]
10956               && ((rex & REX_W) || (sizeflag & DFLAG)))
10957             *obufp++ = 'e';
10958           if (!(rex & REX_W))
10959             used_prefixes |= (prefixes & PREFIX_DATA);
10960           break;
10961         case 'V':
10962           if (intel_syntax)
10963             break;
10964           if (address_mode == mode_64bit && (sizeflag & DFLAG))
10965             {
10966               if (sizeflag & SUFFIX_ALWAYS)
10967                 *obufp++ = 'q';
10968               break;
10969             }
10970           /* Fall through.  */
10971         case 'S':
10972           if (intel_syntax)
10973             break;
10974           if (sizeflag & SUFFIX_ALWAYS)
10975             {
10976               if (rex & REX_W)
10977                 *obufp++ = 'q';
10978               else
10979                 {
10980                   if (sizeflag & DFLAG)
10981                     *obufp++ = 'l';
10982                   else
10983                     *obufp++ = 'w';
10984                   used_prefixes |= (prefixes & PREFIX_DATA);
10985                 }
10986             }
10987           break;
10988         case 'X':
10989           if (l != 0 || len != 1)
10990             {
10991               SAVE_LAST (*p);
10992               break;
10993             }
10994           if (need_vex && vex.prefix)
10995             {
10996               if (vex.prefix == DATA_PREFIX_OPCODE)
10997                 *obufp++ = 'd';
10998               else
10999                 *obufp++ = 's';
11000             }
11001           else if (prefixes & PREFIX_DATA)
11002             *obufp++ = 'd';
11003           else
11004             *obufp++ = 's';
11005           used_prefixes |= (prefixes & PREFIX_DATA);
11006           break;
11007         case 'Y':
11008           if (l == 0 && len == 1)
11009             {
11010               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
11011                 break;
11012               if (rex & REX_W)
11013                 {
11014                   USED_REX (REX_W);
11015                   *obufp++ = 'q';
11016                 }
11017               break;
11018             }
11019           else
11020             {
11021               if (l != 1 || len != 2 || last[0] != 'X')
11022                 {
11023                   SAVE_LAST (*p);
11024                   break;
11025                 }
11026               if (!need_vex)
11027                 abort ();
11028               if (intel_syntax
11029                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11030                 break;
11031               switch (vex.length)
11032                 {
11033                 case 128:
11034                   *obufp++ = 'x';
11035                   break;
11036                 case 256:
11037                   *obufp++ = 'y';
11038                   break;
11039                 default:
11040                   abort ();
11041                 }
11042             }
11043           break;
11044           /* implicit operand size 'l' for i386 or 'q' for x86-64 */
11045         case 'W':
11046           /* operand size flag for cwtl, cbtw */
11047           USED_REX (REX_W);
11048           if (rex & REX_W)
11049             {
11050               if (intel_syntax)
11051                 *obufp++ = 'd';
11052               else
11053                 *obufp++ = 'l';
11054             }
11055           else if (sizeflag & DFLAG)
11056             *obufp++ = 'w';
11057           else
11058             *obufp++ = 'b';
11059           if (!(rex & REX_W))
11060             used_prefixes |= (prefixes & PREFIX_DATA);
11061           break;
11062         }
11063       alt = 0;
11064     }
11065   *obufp = 0;
11066   return 0;
11067 }
11068
11069 static void
11070 oappend (const char *s)
11071 {
11072   strcpy (obufp, s);
11073   obufp += strlen (s);
11074 }
11075
11076 static void
11077 append_seg (void)
11078 {
11079   if (prefixes & PREFIX_CS)
11080     {
11081       used_prefixes |= PREFIX_CS;
11082       oappend ("%cs:" + intel_syntax);
11083     }
11084   if (prefixes & PREFIX_DS)
11085     {
11086       used_prefixes |= PREFIX_DS;
11087       oappend ("%ds:" + intel_syntax);
11088     }
11089   if (prefixes & PREFIX_SS)
11090     {
11091       used_prefixes |= PREFIX_SS;
11092       oappend ("%ss:" + intel_syntax);
11093     }
11094   if (prefixes & PREFIX_ES)
11095     {
11096       used_prefixes |= PREFIX_ES;
11097       oappend ("%es:" + intel_syntax);
11098     }
11099   if (prefixes & PREFIX_FS)
11100     {
11101       used_prefixes |= PREFIX_FS;
11102       oappend ("%fs:" + intel_syntax);
11103     }
11104   if (prefixes & PREFIX_GS)
11105     {
11106       used_prefixes |= PREFIX_GS;
11107       oappend ("%gs:" + intel_syntax);
11108     }
11109 }
11110
11111 static void
11112 OP_indirE (int bytemode, int sizeflag)
11113 {
11114   if (!intel_syntax)
11115     oappend ("*");
11116   OP_E (bytemode, sizeflag);
11117 }
11118
11119 static void
11120 print_operand_value (char *buf, int hex, bfd_vma disp)
11121 {
11122   if (address_mode == mode_64bit)
11123     {
11124       if (hex)
11125         {
11126           char tmp[30];
11127           int i;
11128           buf[0] = '0';
11129           buf[1] = 'x';
11130           sprintf_vma (tmp, disp);
11131           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
11132           strcpy (buf + 2, tmp + i);
11133         }
11134       else
11135         {
11136           bfd_signed_vma v = disp;
11137           char tmp[30];
11138           int i;
11139           if (v < 0)
11140             {
11141               *(buf++) = '-';
11142               v = -disp;
11143               /* Check for possible overflow on 0x8000000000000000.  */
11144               if (v < 0)
11145                 {
11146                   strcpy (buf, "9223372036854775808");
11147                   return;
11148                 }
11149             }
11150           if (!v)
11151             {
11152               strcpy (buf, "0");
11153               return;
11154             }
11155
11156           i = 0;
11157           tmp[29] = 0;
11158           while (v)
11159             {
11160               tmp[28 - i] = (v % 10) + '0';
11161               v /= 10;
11162               i++;
11163             }
11164           strcpy (buf, tmp + 29 - i);
11165         }
11166     }
11167   else
11168     {
11169       if (hex)
11170         sprintf (buf, "0x%x", (unsigned int) disp);
11171       else
11172         sprintf (buf, "%d", (int) disp);
11173     }
11174 }
11175
11176 /* Put DISP in BUF as signed hex number.  */
11177
11178 static void
11179 print_displacement (char *buf, bfd_vma disp)
11180 {
11181   bfd_signed_vma val = disp;
11182   char tmp[30];
11183   int i, j = 0;
11184
11185   if (val < 0)
11186     {
11187       buf[j++] = '-';
11188       val = -disp;
11189
11190       /* Check for possible overflow.  */
11191       if (val < 0)
11192         {
11193           switch (address_mode)
11194             {
11195             case mode_64bit:
11196               strcpy (buf + j, "0x8000000000000000");
11197               break;
11198             case mode_32bit:
11199               strcpy (buf + j, "0x80000000");
11200               break;
11201             case mode_16bit:
11202               strcpy (buf + j, "0x8000");
11203               break;
11204             }
11205           return;
11206         }
11207     }
11208
11209   buf[j++] = '0';
11210   buf[j++] = 'x';
11211
11212   sprintf_vma (tmp, val);
11213   for (i = 0; tmp[i] == '0'; i++)
11214     continue;
11215   if (tmp[i] == '\0')
11216     i--;
11217   strcpy (buf + j, tmp + i);
11218 }
11219
11220 static void
11221 intel_operand_size (int bytemode, int sizeflag)
11222 {
11223   switch (bytemode)
11224     {
11225     case b_mode:
11226     case dqb_mode:
11227       oappend ("BYTE PTR ");
11228       break;
11229     case w_mode:
11230     case dqw_mode:
11231       oappend ("WORD PTR ");
11232       break;
11233     case stack_v_mode:
11234       if (address_mode == mode_64bit && (sizeflag & DFLAG))
11235         {
11236           oappend ("QWORD PTR ");
11237           used_prefixes |= (prefixes & PREFIX_DATA);
11238           break;
11239         }
11240       /* FALLTHRU */
11241     case v_mode:
11242     case dq_mode:
11243       USED_REX (REX_W);
11244       if (rex & REX_W)
11245         oappend ("QWORD PTR ");
11246       else if ((sizeflag & DFLAG) || bytemode == dq_mode)
11247         oappend ("DWORD PTR ");
11248       else
11249         oappend ("WORD PTR ");
11250       used_prefixes |= (prefixes & PREFIX_DATA);
11251       break;
11252     case z_mode:
11253       if ((rex & REX_W) || (sizeflag & DFLAG))
11254         *obufp++ = 'D';
11255       oappend ("WORD PTR ");
11256       if (!(rex & REX_W))
11257         used_prefixes |= (prefixes & PREFIX_DATA);
11258       break;
11259     case a_mode:
11260       if (sizeflag & DFLAG)
11261         oappend ("QWORD PTR ");
11262       else
11263         oappend ("DWORD PTR ");
11264       used_prefixes |= (prefixes & PREFIX_DATA);
11265       break;
11266     case d_mode:
11267     case dqd_mode:
11268       oappend ("DWORD PTR ");
11269       break;
11270     case q_mode:
11271       oappend ("QWORD PTR ");
11272       break;
11273     case m_mode:
11274       if (address_mode == mode_64bit)
11275         oappend ("QWORD PTR ");
11276       else
11277         oappend ("DWORD PTR ");
11278       break;
11279     case f_mode:
11280       if (sizeflag & DFLAG)
11281         oappend ("FWORD PTR ");
11282       else
11283         oappend ("DWORD PTR ");
11284       used_prefixes |= (prefixes & PREFIX_DATA);
11285       break;
11286     case t_mode:
11287       oappend ("TBYTE PTR ");
11288       break;
11289     case x_mode:
11290       if (need_vex)
11291         {
11292           switch (vex.length)
11293             {
11294             case 128:
11295               oappend ("XMMWORD PTR ");
11296               break;
11297             case 256:
11298               oappend ("YMMWORD PTR ");
11299               break;
11300             default:
11301               abort ();
11302             }
11303         }
11304       else
11305         oappend ("XMMWORD PTR ");
11306       break;
11307     case xmm_mode:
11308       oappend ("XMMWORD PTR ");
11309       break;
11310     case xmmq_mode:
11311       if (!need_vex)
11312         abort ();
11313
11314       switch (vex.length)
11315         {
11316         case 128:
11317           oappend ("QWORD PTR ");
11318           break;
11319         case 256:
11320           oappend ("XMMWORD PTR ");
11321           break;
11322         default:
11323           abort ();
11324         }
11325       break;
11326     case ymmq_mode:
11327       if (!need_vex)
11328         abort ();
11329
11330       switch (vex.length)
11331         {
11332         case 128:
11333           oappend ("QWORD PTR ");
11334           break;
11335         case 256:
11336           oappend ("YMMWORD PTR ");
11337           break;
11338         default:
11339           abort ();
11340         }
11341       break;
11342     case o_mode:
11343       oappend ("OWORD PTR ");
11344       break;
11345     default:
11346       break;
11347     }
11348 }
11349
11350 static void
11351 OP_E_register (int bytemode, int sizeflag)
11352 {
11353   int reg = modrm.rm;
11354   const char **names;
11355
11356   USED_REX (REX_B);
11357   if ((rex & REX_B))
11358     reg += 8;
11359
11360   switch (bytemode)
11361     {
11362     case b_mode:
11363       USED_REX (0);
11364       if (rex)
11365         names = names8rex;
11366       else
11367         names = names8;
11368       break;
11369     case w_mode:
11370       names = names16;
11371       break;
11372     case d_mode:
11373       names = names32;
11374       break;
11375     case q_mode:
11376       names = names64;
11377       break;
11378     case m_mode:
11379       names = address_mode == mode_64bit ? names64 : names32;
11380       break;
11381     case stack_v_mode:
11382       if (address_mode == mode_64bit && (sizeflag & DFLAG))
11383         {
11384           names = names64;
11385           used_prefixes |= (prefixes & PREFIX_DATA);
11386           break;
11387         }
11388       bytemode = v_mode;
11389       /* FALLTHRU */
11390     case v_mode:
11391     case dq_mode:
11392     case dqb_mode:
11393     case dqd_mode:
11394     case dqw_mode:
11395       USED_REX (REX_W);
11396       if (rex & REX_W)
11397         names = names64;
11398       else if ((sizeflag & DFLAG) || bytemode != v_mode)
11399         names = names32;
11400       else
11401         names = names16;
11402       used_prefixes |= (prefixes & PREFIX_DATA);
11403       break;
11404     case 0:
11405       return;
11406     default:
11407       oappend (INTERNAL_DISASSEMBLER_ERROR);
11408       return;
11409     }
11410   oappend (names[reg]);
11411 }
11412
11413 static void
11414 OP_E_memory (int bytemode, int sizeflag, int has_drex)
11415 {
11416   bfd_vma disp = 0;
11417   int add = (rex & REX_B) ? 8 : 0;
11418   int riprel = 0;
11419
11420   USED_REX (REX_B);
11421   if (intel_syntax)
11422     intel_operand_size (bytemode, sizeflag);
11423   append_seg ();
11424
11425   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11426     {
11427       /* 32/64 bit address mode */
11428       int havedisp;
11429       int havesib;
11430       int havebase;
11431       int haveindex;
11432       int needindex;
11433       int base, rbase;
11434       int index = 0;
11435       int scale = 0;
11436
11437       havesib = 0;
11438       havebase = 1;
11439       haveindex = 0;
11440       base = modrm.rm;
11441
11442       if (base == 4)
11443         {
11444           havesib = 1;
11445           FETCH_DATA (the_info, codep + 1);
11446           index = (*codep >> 3) & 7;
11447           scale = (*codep >> 6) & 3;
11448           base = *codep & 7;
11449           USED_REX (REX_X);
11450           if (rex & REX_X)
11451             index += 8;
11452           haveindex = index != 4;
11453           codep++;
11454         }
11455       rbase = base + add;
11456
11457       /* If we have a DREX byte, skip it now
11458          (it has already been handled) */
11459       if (has_drex)
11460         {
11461           FETCH_DATA (the_info, codep + 1);
11462           codep++;
11463         }
11464
11465       switch (modrm.mod)
11466         {
11467         case 0:
11468           if (base == 5)
11469             {
11470               havebase = 0;
11471               if (address_mode == mode_64bit && !havesib)
11472                 riprel = 1;
11473               disp = get32s ();
11474             }
11475           break;
11476         case 1:
11477           FETCH_DATA (the_info, codep + 1);
11478           disp = *codep++;
11479           if ((disp & 0x80) != 0)
11480             disp -= 0x100;
11481           break;
11482         case 2:
11483           disp = get32s ();
11484           break;
11485         }
11486
11487       /* In 32bit mode, we need index register to tell [offset] from
11488          [eiz*1 + offset].  */
11489       needindex = (havesib
11490                    && !havebase
11491                    && !haveindex
11492                    && address_mode == mode_32bit);
11493       havedisp = (havebase
11494                   || needindex
11495                   || (havesib && (haveindex || scale != 0)));
11496
11497       if (!intel_syntax)
11498         if (modrm.mod != 0 || base == 5)
11499           {
11500             if (havedisp || riprel)
11501               print_displacement (scratchbuf, disp);
11502             else
11503               print_operand_value (scratchbuf, 1, disp);
11504             oappend (scratchbuf);
11505             if (riprel)
11506               {
11507                 set_op (disp, 1);
11508                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
11509               }
11510           }
11511
11512       if (havebase || haveindex || riprel)
11513         used_prefixes |= PREFIX_ADDR;
11514
11515       if (havedisp || (intel_syntax && riprel))
11516         {
11517           *obufp++ = open_char;
11518           if (intel_syntax && riprel)
11519             {
11520               set_op (disp, 1);
11521               oappend (sizeflag & AFLAG ? "rip" : "eip");
11522             }
11523           *obufp = '\0';
11524           if (havebase)
11525             oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
11526                      ? names64[rbase] : names32[rbase]);
11527           if (havesib)
11528             {
11529               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
11530                  print index to tell base + index from base.  */
11531               if (scale != 0
11532                   || needindex
11533                   || haveindex
11534                   || (havebase && base != ESP_REG_NUM))
11535                 {
11536                   if (!intel_syntax || havebase)
11537                     {
11538                       *obufp++ = separator_char;
11539                       *obufp = '\0';
11540                     }
11541                   if (haveindex)
11542                     oappend (address_mode == mode_64bit
11543                              && (sizeflag & AFLAG)
11544                              ? names64[index] : names32[index]);
11545                   else
11546                     oappend (address_mode == mode_64bit
11547                              && (sizeflag & AFLAG)
11548                              ? index64 : index32);
11549
11550                   *obufp++ = scale_char;
11551                   *obufp = '\0';
11552                   sprintf (scratchbuf, "%d", 1 << scale);
11553                   oappend (scratchbuf);
11554                 }
11555             }
11556           if (intel_syntax
11557               && (disp || modrm.mod != 0 || base == 5))
11558             {
11559               if (!havedisp || (bfd_signed_vma) disp >= 0)
11560                 {
11561                   *obufp++ = '+';
11562                   *obufp = '\0';
11563                 }
11564               else if (modrm.mod != 1)
11565                 {
11566                   *obufp++ = '-';
11567                   *obufp = '\0';
11568                   disp = - (bfd_signed_vma) disp;
11569                 }
11570
11571               if (havedisp)
11572                 print_displacement (scratchbuf, disp);
11573               else
11574                 print_operand_value (scratchbuf, 1, disp);
11575               oappend (scratchbuf);
11576             }
11577
11578           *obufp++ = close_char;
11579           *obufp = '\0';
11580         }
11581       else if (intel_syntax)
11582         {
11583           if (modrm.mod != 0 || base == 5)
11584             {
11585               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11586                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11587                 ;
11588               else
11589                 {
11590                   oappend (names_seg[ds_reg - es_reg]);
11591                   oappend (":");
11592                 }
11593               print_operand_value (scratchbuf, 1, disp);
11594               oappend (scratchbuf);
11595             }
11596         }
11597     }
11598   else
11599     { /* 16 bit address mode */
11600       switch (modrm.mod)
11601         {
11602         case 0:
11603           if (modrm.rm == 6)
11604             {
11605               disp = get16 ();
11606               if ((disp & 0x8000) != 0)
11607                 disp -= 0x10000;
11608             }
11609           break;
11610         case 1:
11611           FETCH_DATA (the_info, codep + 1);
11612           disp = *codep++;
11613           if ((disp & 0x80) != 0)
11614             disp -= 0x100;
11615           break;
11616         case 2:
11617           disp = get16 ();
11618           if ((disp & 0x8000) != 0)
11619             disp -= 0x10000;
11620           break;
11621         }
11622
11623       if (!intel_syntax)
11624         if (modrm.mod != 0 || modrm.rm == 6)
11625           {
11626             print_displacement (scratchbuf, disp);
11627             oappend (scratchbuf);
11628           }
11629
11630       if (modrm.mod != 0 || modrm.rm != 6)
11631         {
11632           *obufp++ = open_char;
11633           *obufp = '\0';
11634           oappend (index16[modrm.rm]);
11635           if (intel_syntax
11636               && (disp || modrm.mod != 0 || modrm.rm == 6))
11637             {
11638               if ((bfd_signed_vma) disp >= 0)
11639                 {
11640                   *obufp++ = '+';
11641                   *obufp = '\0';
11642                 }
11643               else if (modrm.mod != 1)
11644                 {
11645                   *obufp++ = '-';
11646                   *obufp = '\0';
11647                   disp = - (bfd_signed_vma) disp;
11648                 }
11649
11650               print_displacement (scratchbuf, disp);
11651               oappend (scratchbuf);
11652             }
11653
11654           *obufp++ = close_char;
11655           *obufp = '\0';
11656         }
11657       else if (intel_syntax)
11658         {
11659           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11660                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11661             ;
11662           else
11663             {
11664               oappend (names_seg[ds_reg - es_reg]);
11665               oappend (":");
11666             }
11667           print_operand_value (scratchbuf, 1, disp & 0xffff);
11668           oappend (scratchbuf);
11669         }
11670     }
11671 }
11672
11673 static void
11674 OP_E_extended (int bytemode, int sizeflag, int has_drex)
11675 {
11676   /* Skip mod/rm byte.  */
11677   MODRM_CHECK;
11678   codep++;
11679
11680   if (modrm.mod == 3)
11681     OP_E_register (bytemode, sizeflag);
11682   else
11683     OP_E_memory (bytemode, sizeflag, has_drex);
11684 }
11685
11686 static void
11687 OP_E (int bytemode, int sizeflag)
11688 {
11689   OP_E_extended (bytemode, sizeflag, 0);
11690 }
11691
11692
11693 static void
11694 OP_G (int bytemode, int sizeflag)
11695 {
11696   int add = 0;
11697   USED_REX (REX_R);
11698   if (rex & REX_R)
11699     add += 8;
11700   switch (bytemode)
11701     {
11702     case b_mode:
11703       USED_REX (0);
11704       if (rex)
11705         oappend (names8rex[modrm.reg + add]);
11706       else
11707         oappend (names8[modrm.reg + add]);
11708       break;
11709     case w_mode:
11710       oappend (names16[modrm.reg + add]);
11711       break;
11712     case d_mode:
11713       oappend (names32[modrm.reg + add]);
11714       break;
11715     case q_mode:
11716       oappend (names64[modrm.reg + add]);
11717       break;
11718     case v_mode:
11719     case dq_mode:
11720     case dqb_mode:
11721     case dqd_mode:
11722     case dqw_mode:
11723       USED_REX (REX_W);
11724       if (rex & REX_W)
11725         oappend (names64[modrm.reg + add]);
11726       else if ((sizeflag & DFLAG) || bytemode != v_mode)
11727         oappend (names32[modrm.reg + add]);
11728       else
11729         oappend (names16[modrm.reg + add]);
11730       used_prefixes |= (prefixes & PREFIX_DATA);
11731       break;
11732     case m_mode:
11733       if (address_mode == mode_64bit)
11734         oappend (names64[modrm.reg + add]);
11735       else
11736         oappend (names32[modrm.reg + add]);
11737       break;
11738     default:
11739       oappend (INTERNAL_DISASSEMBLER_ERROR);
11740       break;
11741     }
11742 }
11743
11744 static bfd_vma
11745 get64 (void)
11746 {
11747   bfd_vma x;
11748 #ifdef BFD64
11749   unsigned int a;
11750   unsigned int b;
11751
11752   FETCH_DATA (the_info, codep + 8);
11753   a = *codep++ & 0xff;
11754   a |= (*codep++ & 0xff) << 8;
11755   a |= (*codep++ & 0xff) << 16;
11756   a |= (*codep++ & 0xff) << 24;
11757   b = *codep++ & 0xff;
11758   b |= (*codep++ & 0xff) << 8;
11759   b |= (*codep++ & 0xff) << 16;
11760   b |= (*codep++ & 0xff) << 24;
11761   x = a + ((bfd_vma) b << 32);
11762 #else
11763   abort ();
11764   x = 0;
11765 #endif
11766   return x;
11767 }
11768
11769 static bfd_signed_vma
11770 get32 (void)
11771 {
11772   bfd_signed_vma x = 0;
11773
11774   FETCH_DATA (the_info, codep + 4);
11775   x = *codep++ & (bfd_signed_vma) 0xff;
11776   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11777   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11778   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11779   return x;
11780 }
11781
11782 static bfd_signed_vma
11783 get32s (void)
11784 {
11785   bfd_signed_vma x = 0;
11786
11787   FETCH_DATA (the_info, codep + 4);
11788   x = *codep++ & (bfd_signed_vma) 0xff;
11789   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11790   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11791   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11792
11793   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
11794
11795   return x;
11796 }
11797
11798 static int
11799 get16 (void)
11800 {
11801   int x = 0;
11802
11803   FETCH_DATA (the_info, codep + 2);
11804   x = *codep++ & 0xff;
11805   x |= (*codep++ & 0xff) << 8;
11806   return x;
11807 }
11808
11809 static void
11810 set_op (bfd_vma op, int riprel)
11811 {
11812   op_index[op_ad] = op_ad;
11813   if (address_mode == mode_64bit)
11814     {
11815       op_address[op_ad] = op;
11816       op_riprel[op_ad] = riprel;
11817     }
11818   else
11819     {
11820       /* Mask to get a 32-bit address.  */
11821       op_address[op_ad] = op & 0xffffffff;
11822       op_riprel[op_ad] = riprel & 0xffffffff;
11823     }
11824 }
11825
11826 static void
11827 OP_REG (int code, int sizeflag)
11828 {
11829   const char *s;
11830   int add;
11831   USED_REX (REX_B);
11832   if (rex & REX_B)
11833     add = 8;
11834   else
11835     add = 0;
11836
11837   switch (code)
11838     {
11839     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
11840     case sp_reg: case bp_reg: case si_reg: case di_reg:
11841       s = names16[code - ax_reg + add];
11842       break;
11843     case es_reg: case ss_reg: case cs_reg:
11844     case ds_reg: case fs_reg: case gs_reg:
11845       s = names_seg[code - es_reg + add];
11846       break;
11847     case al_reg: case ah_reg: case cl_reg: case ch_reg:
11848     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
11849       USED_REX (0);
11850       if (rex)
11851         s = names8rex[code - al_reg + add];
11852       else
11853         s = names8[code - al_reg];
11854       break;
11855     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
11856     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
11857       if (address_mode == mode_64bit && (sizeflag & DFLAG))
11858         {
11859           s = names64[code - rAX_reg + add];
11860           break;
11861         }
11862       code += eAX_reg - rAX_reg;
11863       /* Fall through.  */
11864     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
11865     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
11866       USED_REX (REX_W);
11867       if (rex & REX_W)
11868         s = names64[code - eAX_reg + add];
11869       else if (sizeflag & DFLAG)
11870         s = names32[code - eAX_reg + add];
11871       else
11872         s = names16[code - eAX_reg + add];
11873       used_prefixes |= (prefixes & PREFIX_DATA);
11874       break;
11875     default:
11876       s = INTERNAL_DISASSEMBLER_ERROR;
11877       break;
11878     }
11879   oappend (s);
11880 }
11881
11882 static void
11883 OP_IMREG (int code, int sizeflag)
11884 {
11885   const char *s;
11886
11887   switch (code)
11888     {
11889     case indir_dx_reg:
11890       if (intel_syntax)
11891         s = "dx";
11892       else
11893         s = "(%dx)";
11894       break;
11895     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
11896     case sp_reg: case bp_reg: case si_reg: case di_reg:
11897       s = names16[code - ax_reg];
11898       break;
11899     case es_reg: case ss_reg: case cs_reg:
11900     case ds_reg: case fs_reg: case gs_reg:
11901       s = names_seg[code - es_reg];
11902       break;
11903     case al_reg: case ah_reg: case cl_reg: case ch_reg:
11904     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
11905       USED_REX (0);
11906       if (rex)
11907         s = names8rex[code - al_reg];
11908       else
11909         s = names8[code - al_reg];
11910       break;
11911     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
11912     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
11913       USED_REX (REX_W);
11914       if (rex & REX_W)
11915         s = names64[code - eAX_reg];
11916       else if (sizeflag & DFLAG)
11917         s = names32[code - eAX_reg];
11918       else
11919         s = names16[code - eAX_reg];
11920       used_prefixes |= (prefixes & PREFIX_DATA);
11921       break;
11922     case z_mode_ax_reg:
11923       if ((rex & REX_W) || (sizeflag & DFLAG))
11924         s = *names32;
11925       else
11926         s = *names16;
11927       if (!(rex & REX_W))
11928         used_prefixes |= (prefixes & PREFIX_DATA);
11929       break;
11930     default:
11931       s = INTERNAL_DISASSEMBLER_ERROR;
11932       break;
11933     }
11934   oappend (s);
11935 }
11936
11937 static void
11938 OP_I (int bytemode, int sizeflag)
11939 {
11940   bfd_signed_vma op;
11941   bfd_signed_vma mask = -1;
11942
11943   switch (bytemode)
11944     {
11945     case b_mode:
11946       FETCH_DATA (the_info, codep + 1);
11947       op = *codep++;
11948       mask = 0xff;
11949       break;
11950     case q_mode:
11951       if (address_mode == mode_64bit)
11952         {
11953           op = get32s ();
11954           break;
11955         }
11956       /* Fall through.  */
11957     case v_mode:
11958       USED_REX (REX_W);
11959       if (rex & REX_W)
11960         op = get32s ();
11961       else if (sizeflag & DFLAG)
11962         {
11963           op = get32 ();
11964           mask = 0xffffffff;
11965         }
11966       else
11967         {
11968           op = get16 ();
11969           mask = 0xfffff;
11970         }
11971       used_prefixes |= (prefixes & PREFIX_DATA);
11972       break;
11973     case w_mode:
11974       mask = 0xfffff;
11975       op = get16 ();
11976       break;
11977     case const_1_mode:
11978       if (intel_syntax)
11979         oappend ("1");
11980       return;
11981     default:
11982       oappend (INTERNAL_DISASSEMBLER_ERROR);
11983       return;
11984     }
11985
11986   op &= mask;
11987   scratchbuf[0] = '$';
11988   print_operand_value (scratchbuf + 1, 1, op);
11989   oappend (scratchbuf + intel_syntax);
11990   scratchbuf[0] = '\0';
11991 }
11992
11993 static void
11994 OP_I64 (int bytemode, int sizeflag)
11995 {
11996   bfd_signed_vma op;
11997   bfd_signed_vma mask = -1;
11998
11999   if (address_mode != mode_64bit)
12000     {
12001       OP_I (bytemode, sizeflag);
12002       return;
12003     }
12004
12005   switch (bytemode)
12006     {
12007     case b_mode:
12008       FETCH_DATA (the_info, codep + 1);
12009       op = *codep++;
12010       mask = 0xff;
12011       break;
12012     case v_mode:
12013       USED_REX (REX_W);
12014       if (rex & REX_W)
12015         op = get64 ();
12016       else if (sizeflag & DFLAG)
12017         {
12018           op = get32 ();
12019           mask = 0xffffffff;
12020         }
12021       else
12022         {
12023           op = get16 ();
12024           mask = 0xfffff;
12025         }
12026       used_prefixes |= (prefixes & PREFIX_DATA);
12027       break;
12028     case w_mode:
12029       mask = 0xfffff;
12030       op = get16 ();
12031       break;
12032     default:
12033       oappend (INTERNAL_DISASSEMBLER_ERROR);
12034       return;
12035     }
12036
12037   op &= mask;
12038   scratchbuf[0] = '$';
12039   print_operand_value (scratchbuf + 1, 1, op);
12040   oappend (scratchbuf + intel_syntax);
12041   scratchbuf[0] = '\0';
12042 }
12043
12044 static void
12045 OP_sI (int bytemode, int sizeflag)
12046 {
12047   bfd_signed_vma op;
12048   bfd_signed_vma mask = -1;
12049
12050   switch (bytemode)
12051     {
12052     case b_mode:
12053       FETCH_DATA (the_info, codep + 1);
12054       op = *codep++;
12055       if ((op & 0x80) != 0)
12056         op -= 0x100;
12057       mask = 0xffffffff;
12058       break;
12059     case v_mode:
12060       USED_REX (REX_W);
12061       if (rex & REX_W)
12062         op = get32s ();
12063       else if (sizeflag & DFLAG)
12064         {
12065           op = get32s ();
12066           mask = 0xffffffff;
12067         }
12068       else
12069         {
12070           mask = 0xffffffff;
12071           op = get16 ();
12072           if ((op & 0x8000) != 0)
12073             op -= 0x10000;
12074         }
12075       used_prefixes |= (prefixes & PREFIX_DATA);
12076       break;
12077     case w_mode:
12078       op = get16 ();
12079       mask = 0xffffffff;
12080       if ((op & 0x8000) != 0)
12081         op -= 0x10000;
12082       break;
12083     default:
12084       oappend (INTERNAL_DISASSEMBLER_ERROR);
12085       return;
12086     }
12087
12088   scratchbuf[0] = '$';
12089   print_operand_value (scratchbuf + 1, 1, op);
12090   oappend (scratchbuf + intel_syntax);
12091 }
12092
12093 static void
12094 OP_J (int bytemode, int sizeflag)
12095 {
12096   bfd_vma disp;
12097   bfd_vma mask = -1;
12098   bfd_vma segment = 0;
12099
12100   switch (bytemode)
12101     {
12102     case b_mode:
12103       FETCH_DATA (the_info, codep + 1);
12104       disp = *codep++;
12105       if ((disp & 0x80) != 0)
12106         disp -= 0x100;
12107       break;
12108     case v_mode:
12109       if ((sizeflag & DFLAG) || (rex & REX_W))
12110         disp = get32s ();
12111       else
12112         {
12113           disp = get16 ();
12114           if ((disp & 0x8000) != 0)
12115             disp -= 0x10000;
12116           /* In 16bit mode, address is wrapped around at 64k within
12117              the same segment.  Otherwise, a data16 prefix on a jump
12118              instruction means that the pc is masked to 16 bits after
12119              the displacement is added!  */
12120           mask = 0xffff;
12121           if ((prefixes & PREFIX_DATA) == 0)
12122             segment = ((start_pc + codep - start_codep)
12123                        & ~((bfd_vma) 0xffff));
12124         }
12125       used_prefixes |= (prefixes & PREFIX_DATA);
12126       break;
12127     default:
12128       oappend (INTERNAL_DISASSEMBLER_ERROR);
12129       return;
12130     }
12131   disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
12132   set_op (disp, 0);
12133   print_operand_value (scratchbuf, 1, disp);
12134   oappend (scratchbuf);
12135 }
12136
12137 static void
12138 OP_SEG (int bytemode, int sizeflag)
12139 {
12140   if (bytemode == w_mode)
12141     oappend (names_seg[modrm.reg]);
12142   else
12143     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12144 }
12145
12146 static void
12147 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12148 {
12149   int seg, offset;
12150
12151   if (sizeflag & DFLAG)
12152     {
12153       offset = get32 ();
12154       seg = get16 ();
12155     }
12156   else
12157     {
12158       offset = get16 ();
12159       seg = get16 ();
12160     }
12161   used_prefixes |= (prefixes & PREFIX_DATA);
12162   if (intel_syntax)
12163     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12164   else
12165     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12166   oappend (scratchbuf);
12167 }
12168
12169 static void
12170 OP_OFF (int bytemode, int sizeflag)
12171 {
12172   bfd_vma off;
12173
12174   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12175     intel_operand_size (bytemode, sizeflag);
12176   append_seg ();
12177
12178   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12179     off = get32 ();
12180   else
12181     off = get16 ();
12182
12183   if (intel_syntax)
12184     {
12185       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12186                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
12187         {
12188           oappend (names_seg[ds_reg - es_reg]);
12189           oappend (":");
12190         }
12191     }
12192   print_operand_value (scratchbuf, 1, off);
12193   oappend (scratchbuf);
12194 }
12195
12196 static void
12197 OP_OFF64 (int bytemode, int sizeflag)
12198 {
12199   bfd_vma off;
12200
12201   if (address_mode != mode_64bit
12202       || (prefixes & PREFIX_ADDR))
12203     {
12204       OP_OFF (bytemode, sizeflag);
12205       return;
12206     }
12207
12208   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12209     intel_operand_size (bytemode, sizeflag);
12210   append_seg ();
12211
12212   off = get64 ();
12213
12214   if (intel_syntax)
12215     {
12216       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12217                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
12218         {
12219           oappend (names_seg[ds_reg - es_reg]);
12220           oappend (":");
12221         }
12222     }
12223   print_operand_value (scratchbuf, 1, off);
12224   oappend (scratchbuf);
12225 }
12226
12227 static void
12228 ptr_reg (int code, int sizeflag)
12229 {
12230   const char *s;
12231
12232   *obufp++ = open_char;
12233   used_prefixes |= (prefixes & PREFIX_ADDR);
12234   if (address_mode == mode_64bit)
12235     {
12236       if (!(sizeflag & AFLAG))
12237         s = names32[code - eAX_reg];
12238       else
12239         s = names64[code - eAX_reg];
12240     }
12241   else if (sizeflag & AFLAG)
12242     s = names32[code - eAX_reg];
12243   else
12244     s = names16[code - eAX_reg];
12245   oappend (s);
12246   *obufp++ = close_char;
12247   *obufp = 0;
12248 }
12249
12250 static void
12251 OP_ESreg (int code, int sizeflag)
12252 {
12253   if (intel_syntax)
12254     {
12255       switch (codep[-1])
12256         {
12257         case 0x6d:      /* insw/insl */
12258           intel_operand_size (z_mode, sizeflag);
12259           break;
12260         case 0xa5:      /* movsw/movsl/movsq */
12261         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12262         case 0xab:      /* stosw/stosl */
12263         case 0xaf:      /* scasw/scasl */
12264           intel_operand_size (v_mode, sizeflag);
12265           break;
12266         default:
12267           intel_operand_size (b_mode, sizeflag);
12268         }
12269     }
12270   oappend ("%es:" + intel_syntax);
12271   ptr_reg (code, sizeflag);
12272 }
12273
12274 static void
12275 OP_DSreg (int code, int sizeflag)
12276 {
12277   if (intel_syntax)
12278     {
12279       switch (codep[-1])
12280         {
12281         case 0x6f:      /* outsw/outsl */
12282           intel_operand_size (z_mode, sizeflag);
12283           break;
12284         case 0xa5:      /* movsw/movsl/movsq */
12285         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12286         case 0xad:      /* lodsw/lodsl/lodsq */
12287           intel_operand_size (v_mode, sizeflag);
12288           break;
12289         default:
12290           intel_operand_size (b_mode, sizeflag);
12291         }
12292     }
12293   if ((prefixes
12294        & (PREFIX_CS
12295           | PREFIX_DS
12296           | PREFIX_SS
12297           | PREFIX_ES
12298           | PREFIX_FS
12299           | PREFIX_GS)) == 0)
12300     prefixes |= PREFIX_DS;
12301   append_seg ();
12302   ptr_reg (code, sizeflag);
12303 }
12304
12305 static void
12306 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12307 {
12308   int add;
12309   if (rex & REX_R)
12310     {
12311       USED_REX (REX_R);
12312       add = 8;
12313     }
12314   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
12315     {
12316       lock_prefix = NULL;
12317       used_prefixes |= PREFIX_LOCK;
12318       add = 8;
12319     }
12320   else
12321     add = 0;
12322   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
12323   oappend (scratchbuf + intel_syntax);
12324 }
12325
12326 static void
12327 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12328 {
12329   int add;
12330   USED_REX (REX_R);
12331   if (rex & REX_R)
12332     add = 8;
12333   else
12334     add = 0;
12335   if (intel_syntax)
12336     sprintf (scratchbuf, "db%d", modrm.reg + add);
12337   else
12338     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
12339   oappend (scratchbuf);
12340 }
12341
12342 static void
12343 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12344 {
12345   sprintf (scratchbuf, "%%tr%d", modrm.reg);
12346   oappend (scratchbuf + intel_syntax);
12347 }
12348
12349 static void
12350 OP_R (int bytemode, int sizeflag)
12351 {
12352   if (modrm.mod == 3)
12353     OP_E (bytemode, sizeflag);
12354   else
12355     BadOp ();
12356 }
12357
12358 static void
12359 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12360 {
12361   used_prefixes |= (prefixes & PREFIX_DATA);
12362   if (prefixes & PREFIX_DATA)
12363     {
12364       int add;
12365       USED_REX (REX_R);
12366       if (rex & REX_R)
12367         add = 8;
12368       else
12369         add = 0;
12370       sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12371     }
12372   else
12373     sprintf (scratchbuf, "%%mm%d", modrm.reg);
12374   oappend (scratchbuf + intel_syntax);
12375 }
12376
12377 static void
12378 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12379 {
12380   int add;
12381   USED_REX (REX_R);
12382   if (rex & REX_R)
12383     add = 8;
12384   else
12385     add = 0;
12386   if (need_vex && bytemode != xmm_mode)
12387     {
12388       switch (vex.length)
12389         {
12390         case 128:
12391           sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12392           break;
12393         case 256:
12394           sprintf (scratchbuf, "%%ymm%d", modrm.reg + add);
12395           break;
12396         default:
12397           abort ();
12398         }
12399     }
12400   else
12401     sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12402   oappend (scratchbuf + intel_syntax);
12403 }
12404
12405 static void
12406 OP_EM (int bytemode, int sizeflag)
12407 {
12408   if (modrm.mod != 3)
12409     {
12410       if (intel_syntax && bytemode == v_mode)
12411         {
12412           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12413           used_prefixes |= (prefixes & PREFIX_DATA);
12414         }
12415       OP_E (bytemode, sizeflag);
12416       return;
12417     }
12418
12419   /* Skip mod/rm byte.  */
12420   MODRM_CHECK;
12421   codep++;
12422   used_prefixes |= (prefixes & PREFIX_DATA);
12423   if (prefixes & PREFIX_DATA)
12424     {
12425       int add;
12426
12427       USED_REX (REX_B);
12428       if (rex & REX_B)
12429         add = 8;
12430       else
12431         add = 0;
12432       sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12433     }
12434   else
12435     sprintf (scratchbuf, "%%mm%d", modrm.rm);
12436   oappend (scratchbuf + intel_syntax);
12437 }
12438
12439 /* cvt* are the only instructions in sse2 which have
12440    both SSE and MMX operands and also have 0x66 prefix
12441    in their opcode. 0x66 was originally used to differentiate
12442    between SSE and MMX instruction(operands). So we have to handle the
12443    cvt* separately using OP_EMC and OP_MXC */
12444 static void
12445 OP_EMC (int bytemode, int sizeflag)
12446 {
12447   if (modrm.mod != 3)
12448     {
12449       if (intel_syntax && bytemode == v_mode)
12450         {
12451           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12452           used_prefixes |= (prefixes & PREFIX_DATA);
12453         }
12454       OP_E (bytemode, sizeflag);
12455       return;
12456     }
12457
12458   /* Skip mod/rm byte.  */
12459   MODRM_CHECK;
12460   codep++;
12461   used_prefixes |= (prefixes & PREFIX_DATA);
12462   sprintf (scratchbuf, "%%mm%d", modrm.rm);
12463   oappend (scratchbuf + intel_syntax);
12464 }
12465
12466 static void
12467 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12468 {
12469   used_prefixes |= (prefixes & PREFIX_DATA);
12470   sprintf (scratchbuf, "%%mm%d", modrm.reg);
12471   oappend (scratchbuf + intel_syntax);
12472 }
12473
12474 static void
12475 OP_EX (int bytemode, int sizeflag)
12476 {
12477   int add;
12478   if (modrm.mod != 3)
12479     {
12480       OP_E (bytemode, sizeflag);
12481       return;
12482     }
12483   USED_REX (REX_B);
12484   if (rex & REX_B)
12485     add = 8;
12486   else
12487     add = 0;
12488
12489   /* Skip mod/rm byte.  */
12490   MODRM_CHECK;
12491   codep++;
12492   if (need_vex
12493       && bytemode != xmm_mode
12494       && bytemode != xmmq_mode)
12495     {
12496       switch (vex.length)
12497         {
12498         case 128:
12499           sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12500           break;
12501         case 256:
12502           sprintf (scratchbuf, "%%ymm%d", modrm.rm + add);
12503           break;
12504         default:
12505           abort ();
12506         }
12507     }
12508   else
12509     sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12510   oappend (scratchbuf + intel_syntax);
12511 }
12512
12513 static void
12514 OP_MS (int bytemode, int sizeflag)
12515 {
12516   if (modrm.mod == 3)
12517     OP_EM (bytemode, sizeflag);
12518   else
12519     BadOp ();
12520 }
12521
12522 static void
12523 OP_XS (int bytemode, int sizeflag)
12524 {
12525   if (modrm.mod == 3)
12526     OP_EX (bytemode, sizeflag);
12527   else
12528     BadOp ();
12529 }
12530
12531 static void
12532 OP_M (int bytemode, int sizeflag)
12533 {
12534   if (modrm.mod == 3)
12535     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12536     BadOp ();
12537   else
12538     OP_E (bytemode, sizeflag);
12539 }
12540
12541 static void
12542 OP_0f07 (int bytemode, int sizeflag)
12543 {
12544   if (modrm.mod != 3 || modrm.rm != 0)
12545     BadOp ();
12546   else
12547     OP_E (bytemode, sizeflag);
12548 }
12549
12550 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12551    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
12552
12553 static void
12554 NOP_Fixup1 (int bytemode, int sizeflag)
12555 {
12556   if ((prefixes & PREFIX_DATA) != 0
12557       || (rex != 0
12558           && rex != 0x48
12559           && address_mode == mode_64bit))
12560     OP_REG (bytemode, sizeflag);
12561   else
12562     strcpy (obuf, "nop");
12563 }
12564
12565 static void
12566 NOP_Fixup2 (int bytemode, int sizeflag)
12567 {
12568   if ((prefixes & PREFIX_DATA) != 0
12569       || (rex != 0
12570           && rex != 0x48
12571           && address_mode == mode_64bit))
12572     OP_IMREG (bytemode, sizeflag);
12573 }
12574
12575 static const char *const Suffix3DNow[] = {
12576 /* 00 */        NULL,           NULL,           NULL,           NULL,
12577 /* 04 */        NULL,           NULL,           NULL,           NULL,
12578 /* 08 */        NULL,           NULL,           NULL,           NULL,
12579 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
12580 /* 10 */        NULL,           NULL,           NULL,           NULL,
12581 /* 14 */        NULL,           NULL,           NULL,           NULL,
12582 /* 18 */        NULL,           NULL,           NULL,           NULL,
12583 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
12584 /* 20 */        NULL,           NULL,           NULL,           NULL,
12585 /* 24 */        NULL,           NULL,           NULL,           NULL,
12586 /* 28 */        NULL,           NULL,           NULL,           NULL,
12587 /* 2C */        NULL,           NULL,           NULL,           NULL,
12588 /* 30 */        NULL,           NULL,           NULL,           NULL,
12589 /* 34 */        NULL,           NULL,           NULL,           NULL,
12590 /* 38 */        NULL,           NULL,           NULL,           NULL,
12591 /* 3C */        NULL,           NULL,           NULL,           NULL,
12592 /* 40 */        NULL,           NULL,           NULL,           NULL,
12593 /* 44 */        NULL,           NULL,           NULL,           NULL,
12594 /* 48 */        NULL,           NULL,           NULL,           NULL,
12595 /* 4C */        NULL,           NULL,           NULL,           NULL,
12596 /* 50 */        NULL,           NULL,           NULL,           NULL,
12597 /* 54 */        NULL,           NULL,           NULL,           NULL,
12598 /* 58 */        NULL,           NULL,           NULL,           NULL,
12599 /* 5C */        NULL,           NULL,           NULL,           NULL,
12600 /* 60 */        NULL,           NULL,           NULL,           NULL,
12601 /* 64 */        NULL,           NULL,           NULL,           NULL,
12602 /* 68 */        NULL,           NULL,           NULL,           NULL,
12603 /* 6C */        NULL,           NULL,           NULL,           NULL,
12604 /* 70 */        NULL,           NULL,           NULL,           NULL,
12605 /* 74 */        NULL,           NULL,           NULL,           NULL,
12606 /* 78 */        NULL,           NULL,           NULL,           NULL,
12607 /* 7C */        NULL,           NULL,           NULL,           NULL,
12608 /* 80 */        NULL,           NULL,           NULL,           NULL,
12609 /* 84 */        NULL,           NULL,           NULL,           NULL,
12610 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
12611 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
12612 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
12613 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
12614 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
12615 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
12616 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
12617 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
12618 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
12619 /* AC */        NULL,           NULL,           "pfacc",        NULL,
12620 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
12621 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
12622 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
12623 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
12624 /* C0 */        NULL,           NULL,           NULL,           NULL,
12625 /* C4 */        NULL,           NULL,           NULL,           NULL,
12626 /* C8 */        NULL,           NULL,           NULL,           NULL,
12627 /* CC */        NULL,           NULL,           NULL,           NULL,
12628 /* D0 */        NULL,           NULL,           NULL,           NULL,
12629 /* D4 */        NULL,           NULL,           NULL,           NULL,
12630 /* D8 */        NULL,           NULL,           NULL,           NULL,
12631 /* DC */        NULL,           NULL,           NULL,           NULL,
12632 /* E0 */        NULL,           NULL,           NULL,           NULL,
12633 /* E4 */        NULL,           NULL,           NULL,           NULL,
12634 /* E8 */        NULL,           NULL,           NULL,           NULL,
12635 /* EC */        NULL,           NULL,           NULL,           NULL,
12636 /* F0 */        NULL,           NULL,           NULL,           NULL,
12637 /* F4 */        NULL,           NULL,           NULL,           NULL,
12638 /* F8 */        NULL,           NULL,           NULL,           NULL,
12639 /* FC */        NULL,           NULL,           NULL,           NULL,
12640 };
12641
12642 static void
12643 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12644 {
12645   const char *mnemonic;
12646
12647   FETCH_DATA (the_info, codep + 1);
12648   /* AMD 3DNow! instructions are specified by an opcode suffix in the
12649      place where an 8-bit immediate would normally go.  ie. the last
12650      byte of the instruction.  */
12651   obufp = obuf + strlen (obuf);
12652   mnemonic = Suffix3DNow[*codep++ & 0xff];
12653   if (mnemonic)
12654     oappend (mnemonic);
12655   else
12656     {
12657       /* Since a variable sized modrm/sib chunk is between the start
12658          of the opcode (0x0f0f) and the opcode suffix, we need to do
12659          all the modrm processing first, and don't know until now that
12660          we have a bad opcode.  This necessitates some cleaning up.  */
12661       op_out[0][0] = '\0';
12662       op_out[1][0] = '\0';
12663       BadOp ();
12664     }
12665 }
12666
12667 static const char *simd_cmp_op[] = {
12668   "eq",
12669   "lt",
12670   "le",
12671   "unord",
12672   "neq",
12673   "nlt",
12674   "nle",
12675   "ord"
12676 };
12677
12678 static void
12679 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12680 {
12681   unsigned int cmp_type;
12682
12683   FETCH_DATA (the_info, codep + 1);
12684   cmp_type = *codep++ & 0xff;
12685   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
12686     {
12687       char suffix [3];
12688       char *p = obuf + strlen (obuf) - 2;
12689       suffix[0] = p[0];
12690       suffix[1] = p[1];
12691       suffix[2] = '\0';
12692       sprintf (p, "%s%s", simd_cmp_op[cmp_type], suffix);
12693     }
12694   else
12695     {
12696       /* We have a reserved extension byte.  Output it directly.  */
12697       scratchbuf[0] = '$';
12698       print_operand_value (scratchbuf + 1, 1, cmp_type);
12699       oappend (scratchbuf + intel_syntax);
12700       scratchbuf[0] = '\0';
12701     }
12702 }
12703
12704 static void
12705 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
12706           int sizeflag ATTRIBUTE_UNUSED)
12707 {
12708   /* mwait %eax,%ecx  */
12709   if (!intel_syntax)
12710     {
12711       const char **names = (address_mode == mode_64bit
12712                             ? names64 : names32);
12713       strcpy (op_out[0], names[0]);
12714       strcpy (op_out[1], names[1]);
12715       two_source_ops = 1;
12716     }
12717   /* Skip mod/rm byte.  */
12718   MODRM_CHECK;
12719   codep++;
12720 }
12721
12722 static void
12723 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
12724             int sizeflag ATTRIBUTE_UNUSED)
12725 {
12726   /* monitor %eax,%ecx,%edx"  */
12727   if (!intel_syntax)
12728     {
12729       const char **op1_names;
12730       const char **names = (address_mode == mode_64bit
12731                             ? names64 : names32);
12732
12733       if (!(prefixes & PREFIX_ADDR))
12734         op1_names = (address_mode == mode_16bit
12735                      ? names16 : names);
12736       else
12737         {
12738           /* Remove "addr16/addr32".  */
12739           addr_prefix = NULL;
12740           op1_names = (address_mode != mode_32bit
12741                        ? names32 : names16);
12742           used_prefixes |= PREFIX_ADDR;
12743         }
12744       strcpy (op_out[0], op1_names[0]);
12745       strcpy (op_out[1], names[1]);
12746       strcpy (op_out[2], names[2]);
12747       two_source_ops = 1;
12748     }
12749   /* Skip mod/rm byte.  */
12750   MODRM_CHECK;
12751   codep++;
12752 }
12753
12754 static void
12755 BadOp (void)
12756 {
12757   /* Throw away prefixes and 1st. opcode byte.  */
12758   codep = insn_codep + 1;
12759   oappend ("(bad)");
12760 }
12761
12762 static void
12763 REP_Fixup (int bytemode, int sizeflag)
12764 {
12765   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
12766      lods and stos.  */
12767   if (prefixes & PREFIX_REPZ)
12768     repz_prefix = "rep ";
12769
12770   switch (bytemode)
12771     {
12772     case al_reg:
12773     case eAX_reg:
12774     case indir_dx_reg:
12775       OP_IMREG (bytemode, sizeflag);
12776       break;
12777     case eDI_reg:
12778       OP_ESreg (bytemode, sizeflag);
12779       break;
12780     case eSI_reg:
12781       OP_DSreg (bytemode, sizeflag);
12782       break;
12783     default:
12784       abort ();
12785       break;
12786     }
12787 }
12788
12789 static void
12790 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
12791 {
12792   USED_REX (REX_W);
12793   if (rex & REX_W)
12794     {
12795       /* Change cmpxchg8b to cmpxchg16b.  */
12796       char *p = obuf + strlen (obuf) - 2;
12797       strcpy (p, "16b");
12798       bytemode = o_mode;
12799     }
12800   OP_M (bytemode, sizeflag);
12801 }
12802
12803 static void
12804 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
12805 {
12806   if (need_vex)
12807     {
12808       switch (vex.length)
12809         {
12810         case 128:
12811           sprintf (scratchbuf, "%%xmm%d", reg);
12812           break;
12813         case 256:
12814           sprintf (scratchbuf, "%%ymm%d", reg);
12815           break;
12816         default:
12817           abort ();
12818         }
12819     }
12820   else
12821     sprintf (scratchbuf, "%%xmm%d", reg);
12822   oappend (scratchbuf + intel_syntax);
12823 }
12824
12825 static void
12826 CRC32_Fixup (int bytemode, int sizeflag)
12827 {
12828   /* Add proper suffix to "crc32".  */
12829   char *p = obuf + strlen (obuf);
12830
12831   switch (bytemode)
12832     {
12833     case b_mode:
12834       if (intel_syntax)
12835         break;
12836
12837       *p++ = 'b';
12838       break;
12839     case v_mode:
12840       if (intel_syntax)
12841         break;
12842
12843       USED_REX (REX_W);
12844       if (rex & REX_W)
12845         *p++ = 'q';
12846       else if (sizeflag & DFLAG)
12847         *p++ = 'l';
12848       else
12849         *p++ = 'w';
12850       used_prefixes |= (prefixes & PREFIX_DATA);
12851       break;
12852     default:
12853       oappend (INTERNAL_DISASSEMBLER_ERROR);
12854       break;
12855     }
12856   *p = '\0';
12857
12858   if (modrm.mod == 3)
12859     {
12860       int add;
12861
12862       /* Skip mod/rm byte.  */
12863       MODRM_CHECK;
12864       codep++;
12865
12866       USED_REX (REX_B);
12867       add = (rex & REX_B) ? 8 : 0;
12868       if (bytemode == b_mode)
12869         {
12870           USED_REX (0);
12871           if (rex)
12872             oappend (names8rex[modrm.rm + add]);
12873           else
12874             oappend (names8[modrm.rm + add]);
12875         }
12876       else
12877         {
12878           USED_REX (REX_W);
12879           if (rex & REX_W)
12880             oappend (names64[modrm.rm + add]);
12881           else if ((prefixes & PREFIX_DATA))
12882             oappend (names16[modrm.rm + add]);
12883           else
12884             oappend (names32[modrm.rm + add]);
12885         }
12886     }
12887   else
12888     OP_E (bytemode, sizeflag);
12889 }
12890
12891 /* Print a DREX argument as either a register or memory operation.  */
12892 static void
12893 print_drex_arg (unsigned int reg, int bytemode, int sizeflag)
12894 {
12895   if (reg == DREX_REG_UNKNOWN)
12896     BadOp ();
12897
12898   else if (reg != DREX_REG_MEMORY)
12899     {
12900       sprintf (scratchbuf, "%%xmm%d", reg);
12901       oappend (scratchbuf + intel_syntax);
12902     }
12903
12904   else
12905     OP_E_extended (bytemode, sizeflag, 1);
12906 }
12907
12908 /* SSE5 instructions that have 4 arguments are encoded as:
12909    0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>.
12910
12911    The <sub-opcode> byte has 1 bit (0x4) that is combined with 1 bit in
12912    the DREX field (0x8) to determine how the arguments are laid out.
12913    The destination register must be the same register as one of the
12914    inputs, and it is encoded in the DREX byte.  No REX prefix is used
12915    for these instructions, since the DREX field contains the 3 extension
12916    bits provided by the REX prefix.
12917
12918    The bytemode argument adds 2 extra bits for passing extra information:
12919         DREX_OC1        -- Set the OC1 bit to indicate dest == 1st arg
12920         DREX_NO_OC0     -- OC0 in DREX is invalid
12921         (but pretend it is set).  */
12922
12923 static void
12924 OP_DREX4 (int flag_bytemode, int sizeflag)
12925 {
12926   unsigned int drex_byte;
12927   unsigned int regs[4];
12928   unsigned int modrm_regmem;
12929   unsigned int modrm_reg;
12930   unsigned int drex_reg;
12931   int bytemode;
12932   int rex_save = rex;
12933   int rex_used_save = rex_used;
12934   int has_sib = 0;
12935   int oc1 = (flag_bytemode & DREX_OC1) ? 2 : 0;
12936   int oc0;
12937   int i;
12938
12939   bytemode = flag_bytemode & ~ DREX_MASK;
12940
12941   for (i = 0; i < 4; i++)
12942     regs[i] = DREX_REG_UNKNOWN;
12943
12944   /* Determine if we have a SIB byte in addition to MODRM before the
12945      DREX byte.  */
12946   if (((sizeflag & AFLAG) || address_mode == mode_64bit)
12947       && (modrm.mod != 3)
12948       && (modrm.rm == 4))
12949     has_sib = 1;
12950
12951   /* Get the DREX byte.  */
12952   FETCH_DATA (the_info, codep + 2 + has_sib);
12953   drex_byte = codep[has_sib+1];
12954   drex_reg = DREX_XMM (drex_byte);
12955   modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
12956
12957   /* Is OC0 legal?  If not, hardwire oc0 == 1.  */
12958   if (flag_bytemode & DREX_NO_OC0)
12959     {
12960       oc0 = 1;
12961       if (DREX_OC0 (drex_byte))
12962         BadOp ();
12963     }
12964   else
12965     oc0 = DREX_OC0 (drex_byte);
12966
12967   if (modrm.mod == 3)
12968     {
12969       /* regmem == register  */
12970       modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
12971       rex = rex_used = 0;
12972       /* skip modrm/drex since we don't call OP_E_extended  */
12973       codep += 2;
12974     }
12975   else
12976     {
12977       /* regmem == memory, fill in appropriate REX bits  */
12978       modrm_regmem = DREX_REG_MEMORY;
12979       rex = drex_byte & (REX_B | REX_X | REX_R);
12980       if (rex)
12981         rex |= REX_OPCODE;
12982       rex_used = rex;
12983     }
12984
12985   /* Based on the OC1/OC0 bits, lay out the arguments in the correct
12986      order.  */
12987   switch (oc0 + oc1)
12988     {
12989     default:
12990       BadOp ();
12991       return;
12992
12993     case 0:
12994       regs[0] = modrm_regmem;
12995       regs[1] = modrm_reg;
12996       regs[2] = drex_reg;
12997       regs[3] = drex_reg;
12998       break;
12999
13000     case 1:
13001       regs[0] = modrm_reg;
13002       regs[1] = modrm_regmem;
13003       regs[2] = drex_reg;
13004       regs[3] = drex_reg;
13005       break;
13006
13007     case 2:
13008       regs[0] = drex_reg;
13009       regs[1] = modrm_regmem;
13010       regs[2] = modrm_reg;
13011       regs[3] = drex_reg;
13012       break;
13013
13014     case 3:
13015       regs[0] = drex_reg;
13016       regs[1] = modrm_reg;
13017       regs[2] = modrm_regmem;
13018       regs[3] = drex_reg;
13019       break;
13020     }
13021
13022   /* Print out the arguments.  */
13023   for (i = 0; i < 4; i++)
13024     {
13025       int j = (intel_syntax) ? 3 - i : i;
13026       if (i > 0)
13027         {
13028           *obufp++ = ',';
13029           *obufp = '\0';
13030         }
13031
13032       print_drex_arg (regs[j], bytemode, sizeflag);
13033     }
13034
13035   rex = rex_save;
13036   rex_used = rex_used_save;
13037 }
13038
13039 /* SSE5 instructions that have 3 arguments, and are encoded as:
13040    0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>    (or)
13041    0f 25 <sub-opcode> <modrm> <optional-sib> <drex> <offset> <cmp-byte>
13042
13043    The DREX field has 1 bit (0x8) to determine how the arguments are
13044    laid out. The destination register is encoded in the DREX byte.
13045    No REX prefix is used for these instructions, since the DREX field
13046    contains the 3 extension bits provided by the REX prefix.  */
13047
13048 static void
13049 OP_DREX3 (int flag_bytemode, int sizeflag)
13050 {
13051   unsigned int drex_byte;
13052   unsigned int regs[3];
13053   unsigned int modrm_regmem;
13054   unsigned int modrm_reg;
13055   unsigned int drex_reg;
13056   int bytemode;
13057   int rex_save = rex;
13058   int rex_used_save = rex_used;
13059   int has_sib = 0;
13060   int oc0;
13061   int i;
13062
13063   bytemode = flag_bytemode & ~ DREX_MASK;
13064
13065   for (i = 0; i < 3; i++)
13066     regs[i] = DREX_REG_UNKNOWN;
13067
13068   /* Determine if we have a SIB byte in addition to MODRM before the
13069      DREX byte.  */
13070   if (((sizeflag & AFLAG) || address_mode == mode_64bit)
13071       && (modrm.mod != 3)
13072       && (modrm.rm == 4))
13073     has_sib = 1;
13074
13075   /* Get the DREX byte.  */
13076   FETCH_DATA (the_info, codep + 2 + has_sib);
13077   drex_byte = codep[has_sib+1];
13078   drex_reg = DREX_XMM (drex_byte);
13079   modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
13080
13081   /* Is OC0 legal?  If not, hardwire oc0 == 0 */
13082   oc0 = DREX_OC0 (drex_byte);
13083   if ((flag_bytemode & DREX_NO_OC0) && oc0)
13084     BadOp ();
13085
13086   if (modrm.mod == 3)
13087     {
13088       /* regmem == register */
13089       modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
13090       rex = rex_used = 0;
13091       /* skip modrm/drex since we don't call OP_E_extended.  */
13092       codep += 2;
13093     }
13094   else
13095     {
13096       /* regmem == memory, fill in appropriate REX bits.  */
13097       modrm_regmem = DREX_REG_MEMORY;
13098       rex = drex_byte & (REX_B | REX_X | REX_R);
13099       if (rex)
13100         rex |= REX_OPCODE;
13101       rex_used = rex;
13102     }
13103
13104   /* Based on the OC1/OC0 bits, lay out the arguments in the correct
13105      order.  */
13106   switch (oc0)
13107     {
13108     default:
13109       BadOp ();
13110       return;
13111
13112     case 0:
13113       regs[0] = modrm_regmem;
13114       regs[1] = modrm_reg;
13115       regs[2] = drex_reg;
13116       break;
13117
13118     case 1:
13119       regs[0] = modrm_reg;
13120       regs[1] = modrm_regmem;
13121       regs[2] = drex_reg;
13122       break;
13123     }
13124
13125   /* Print out the arguments.  */
13126   for (i = 0; i < 3; i++)
13127     {
13128       int j = (intel_syntax) ? 2 - i : i;
13129       if (i > 0)
13130         {
13131           *obufp++ = ',';
13132           *obufp = '\0';
13133         }
13134
13135       print_drex_arg (regs[j], bytemode, sizeflag);
13136     }
13137
13138   rex = rex_save;
13139   rex_used = rex_used_save;
13140 }
13141
13142 /* Emit a floating point comparison for comp<xx> instructions.  */
13143
13144 static void
13145 OP_DREX_FCMP (int bytemode ATTRIBUTE_UNUSED,
13146               int sizeflag ATTRIBUTE_UNUSED)
13147 {
13148   unsigned char byte;
13149
13150   static const char *const cmp_test[] = {
13151     "eq",
13152     "lt",
13153     "le",
13154     "unord",
13155     "ne",
13156     "nlt",
13157     "nle",
13158     "ord",
13159     "ueq",
13160     "ult",
13161     "ule",
13162     "false",
13163     "une",
13164     "unlt",
13165     "unle",
13166     "true"
13167   };
13168
13169   FETCH_DATA (the_info, codep + 1);
13170   byte = *codep & 0xff;
13171
13172   if (byte >= ARRAY_SIZE (cmp_test)
13173       || obuf[0] != 'c'
13174       || obuf[1] != 'o'
13175       || obuf[2] != 'm')
13176     {
13177       /* The instruction isn't one we know about, so just append the
13178          extension byte as a numeric value.  */
13179       OP_I (b_mode, 0);
13180     }
13181
13182   else
13183     {
13184       sprintf (scratchbuf, "com%s%s", cmp_test[byte], obuf+3);
13185       strcpy (obuf, scratchbuf);
13186       codep++;
13187     }
13188 }
13189
13190 /* Emit an integer point comparison for pcom<xx> instructions,
13191    rewriting the instruction to have the test inside of it.  */
13192
13193 static void
13194 OP_DREX_ICMP (int bytemode ATTRIBUTE_UNUSED,
13195               int sizeflag ATTRIBUTE_UNUSED)
13196 {
13197   unsigned char byte;
13198
13199   static const char *const cmp_test[] = {
13200     "lt",
13201     "le",
13202     "gt",
13203     "ge",
13204     "eq",
13205     "ne",
13206     "false",
13207     "true"
13208   };
13209
13210   FETCH_DATA (the_info, codep + 1);
13211   byte = *codep & 0xff;
13212
13213   if (byte >= ARRAY_SIZE (cmp_test)
13214       || obuf[0] != 'p'
13215       || obuf[1] != 'c'
13216       || obuf[2] != 'o'
13217       || obuf[3] != 'm')
13218     {
13219       /* The instruction isn't one we know about, so just print the
13220          comparison test byte as a numeric value.  */
13221       OP_I (b_mode, 0);
13222     }
13223
13224   else
13225     {
13226       sprintf (scratchbuf, "pcom%s%s", cmp_test[byte], obuf+4);
13227       strcpy (obuf, scratchbuf);
13228       codep++;
13229     }
13230 }
13231
13232 /* Display the destination register operand for instructions with
13233    VEX. */
13234
13235 static void
13236 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13237 {
13238   if (!need_vex)
13239     abort ();
13240
13241   if (!need_vex_reg)
13242     return;
13243
13244   switch (vex.length)
13245     {
13246     case 128:
13247       switch (bytemode)
13248         {
13249         case vex_mode:
13250         case vex128_mode:
13251           break;
13252         default:
13253           abort ();
13254           return;
13255         }
13256
13257       sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
13258       break;
13259     case 256:
13260       switch (bytemode)
13261         {
13262         case vex_mode:
13263         case vex256_mode:
13264           break;
13265         default:
13266           abort ();
13267           return;
13268         }
13269
13270       sprintf (scratchbuf, "%%ymm%d", vex.register_specifier);
13271       break;
13272     default:
13273       abort ();
13274       break;
13275     }
13276   oappend (scratchbuf + intel_syntax);
13277 }
13278
13279 static void
13280 OP_EX_VexW (int bytemode, int sizeflag)
13281 {
13282   int reg = -1;
13283   static unsigned char vex_i4;
13284
13285   if (!vex_i4_done)
13286     {
13287       int bytes_before_imm = 0;
13288
13289       /* Skip mod/rm byte once. We will be called twice. */
13290       MODRM_CHECK;
13291       codep++;
13292
13293       if (modrm.mod != 3)
13294         {
13295           /* There are SIB/displacement bytes.  */
13296           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13297             {
13298               /* 32/64 bit address mode */
13299               int base = modrm.rm;
13300
13301               /* Check SIB byte.  */
13302               if (base == 4)
13303                 {
13304                   FETCH_DATA (the_info, codep + 1);
13305                   base = *codep & 7;
13306                   bytes_before_imm++;
13307                 }
13308
13309               switch (modrm.mod)
13310                 {
13311                 case 0:
13312                   /* When modrm.rm == 5 or modrm.rm == 4 and base in
13313                      SIB == 5, there is a 4 byte displacement.  */
13314                   if (base != 5)
13315                     /* No displacement. */
13316                     break;
13317                 case 2:
13318                   /* 4 byte displacement.  */
13319                   bytes_before_imm += 4;
13320                   break;
13321                 case 1:
13322                   /* 1 byte displacement.  */
13323                   bytes_before_imm++;
13324                   break;
13325                 }
13326             }
13327           else
13328             { /* 16 bit address mode */
13329               switch (modrm.mod)
13330                 {
13331                 case 0:
13332                   /* When modrm.rm == 6, there is a 2 byte
13333                      displacement.  */
13334                   if (modrm.rm != 6)
13335                     /* No displacement. */
13336                     break;
13337                 case 2:
13338                   /* 2 byte displacement.  */
13339                   bytes_before_imm += 2;
13340                   break;
13341                 case 1:
13342                   /* 1 byte displacement.  */
13343                   bytes_before_imm++;
13344                   break;
13345                 }
13346             }
13347         }
13348
13349       FETCH_DATA (the_info, codep + bytes_before_imm + 1);
13350       vex_i4 = codep [bytes_before_imm];
13351       vex_i4_done = 1;
13352       if (vex.w)
13353         reg = vex_i4 >> 4;
13354     }
13355   else
13356     {
13357       if (!vex.w)
13358         reg = vex_i4 >> 4;
13359     }
13360
13361   if (reg == -1 && modrm.mod != 3)
13362     {
13363       OP_E_memory (bytemode, sizeflag, 0);
13364       return;
13365     }
13366   else
13367     {
13368       if (reg == -1)
13369         {
13370           reg = modrm.rm;
13371           USED_REX (REX_B);
13372           if (rex & REX_B)
13373             reg += 8;
13374         }
13375       else if (reg > 7 && address_mode != mode_64bit)
13376         BadOp ();
13377     }
13378
13379   switch (vex.length)
13380     {
13381     case 128:
13382       sprintf (scratchbuf, "%%xmm%d", reg);
13383       break;
13384     case 256:
13385       sprintf (scratchbuf, "%%ymm%d", reg);
13386       break;
13387     default:
13388       abort ();
13389     }
13390   oappend (scratchbuf + intel_syntax);
13391 }
13392
13393 static void
13394 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
13395              int sizeflag ATTRIBUTE_UNUSED)
13396 {
13397   /* Skip the immediate byte and check for invalid bits.  */
13398   FETCH_DATA (the_info, codep + 1);
13399   if (*codep++ & 0xf)
13400     BadOp ();
13401 }
13402
13403 static void
13404 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13405 {
13406   int reg;
13407   FETCH_DATA (the_info, codep + 1);
13408   reg = *codep++;
13409
13410   if (bytemode != x_mode)
13411     abort ();
13412
13413   if (reg & 0xf)
13414       BadOp ();
13415
13416   reg >>= 4;
13417   switch (vex.length)
13418     {
13419     case 128:
13420       sprintf (scratchbuf, "%%xmm%d", reg);
13421       break;
13422     case 256:
13423       sprintf (scratchbuf, "%%ymm%d", reg);
13424       break;
13425     default:
13426       abort ();
13427     }
13428   oappend (scratchbuf + intel_syntax);
13429 }
13430
13431 static void
13432 OP_XMM_VexW (int bytemode, int sizeflag)
13433 {
13434   /* Turn off the REX.W bit since it is used for swapping operands
13435      now.  */
13436   rex &= ~REX_W;
13437   OP_XMM (bytemode, sizeflag);
13438 }
13439
13440 static void
13441 OP_EX_Vex (int bytemode, int sizeflag)
13442 {
13443   if (modrm.mod != 3)
13444     {
13445       if (vex.register_specifier != 0)
13446         BadOp ();
13447       need_vex_reg = 0;
13448     }
13449   OP_EX (bytemode, sizeflag);
13450 }
13451
13452 static void
13453 OP_XMM_Vex (int bytemode, int sizeflag)
13454 {
13455   if (modrm.mod != 3)
13456     {
13457       if (vex.register_specifier != 0)
13458         BadOp ();
13459       need_vex_reg = 0;
13460     }
13461   OP_XMM (bytemode, sizeflag);
13462 }
13463
13464 static void
13465 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13466 {
13467   switch (vex.length)
13468     {
13469     case 128:
13470       strcpy (obuf, "vzeroupper");
13471       break;
13472     case 256:
13473       strcpy (obuf, "vzeroall");
13474       break;
13475     default:
13476       abort ();
13477     }
13478 }
13479
13480 static const char *vex_cmp_op[] = {
13481   "eq",
13482   "lt",
13483   "le",
13484   "unord",
13485   "neq",
13486   "nlt",
13487   "nle",
13488   "ord",
13489   "eq_uq",
13490   "nge",
13491   "ngt",
13492   "false",
13493   "neq_oq",
13494   "ge",
13495   "gt",
13496   "true",
13497   "eq_os",
13498   "lt_oq",
13499   "le_oq",
13500   "unord_s",
13501   "neq_us",
13502   "nlt_uq",
13503   "nle_uq",
13504   "ord_s",
13505   "eq_us",
13506   "nge_uq",
13507   "ngt_uq",
13508   "false_os",
13509   "neq_os",
13510   "ge_oq",
13511   "gt_oq",
13512   "true_us"
13513 };
13514
13515 static void
13516 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13517 {
13518   unsigned int cmp_type;
13519
13520   FETCH_DATA (the_info, codep + 1);
13521   cmp_type = *codep++ & 0xff;
13522   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
13523     {
13524       char suffix [3];
13525       char *p = obuf + strlen (obuf) - 2;
13526       suffix[0] = p[0];
13527       suffix[1] = p[1];
13528       suffix[2] = '\0';
13529       sprintf (p, "%s%s", vex_cmp_op[cmp_type], suffix);
13530     }
13531   else
13532     {
13533       /* We have a reserved extension byte.  Output it directly.  */
13534       scratchbuf[0] = '$';
13535       print_operand_value (scratchbuf + 1, 1, cmp_type);
13536       oappend (scratchbuf + intel_syntax);
13537       scratchbuf[0] = '\0';
13538     }
13539 }
13540
13541 static const char *pclmul_op[] = {
13542   "lql",
13543   "hql",
13544   "lqh",
13545   "hqh"
13546 };
13547
13548 static void
13549 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13550               int sizeflag ATTRIBUTE_UNUSED)
13551 {
13552   unsigned int pclmul_type;
13553
13554   FETCH_DATA (the_info, codep + 1);
13555   pclmul_type = *codep++ & 0xff;
13556   switch (pclmul_type)
13557     {
13558     case 0x10:
13559       pclmul_type = 2;
13560       break;
13561     case 0x11:
13562       pclmul_type = 3;
13563       break;
13564     default:
13565       break;
13566     }
13567   if (pclmul_type < ARRAY_SIZE (pclmul_op))
13568     {
13569       char suffix [4];
13570       char *p = obuf + strlen (obuf) - 3;
13571       suffix[0] = p[0];
13572       suffix[1] = p[1];
13573       suffix[2] = p[2];
13574       suffix[3] = '\0';
13575       sprintf (p, "%s%s", pclmul_op[pclmul_type], suffix);
13576     }
13577   else
13578     {
13579       /* We have a reserved extension byte.  Output it directly.  */
13580       scratchbuf[0] = '$';
13581       print_operand_value (scratchbuf + 1, 1, pclmul_type);
13582       oappend (scratchbuf + intel_syntax);
13583       scratchbuf[0] = '\0';
13584     }
13585 }
13586
13587 static const char *vpermil2_op[] = {
13588   "td",
13589   "td",
13590   "mo",
13591   "mz"
13592 };
13593
13594 static void
13595 VPERMIL2_Fixup (int bytemode ATTRIBUTE_UNUSED,
13596                 int sizeflag ATTRIBUTE_UNUSED)
13597 {
13598   unsigned int vpermil2_type;
13599
13600   FETCH_DATA (the_info, codep + 1);
13601   vpermil2_type = *codep++ & 0xf;
13602   if (vpermil2_type < ARRAY_SIZE (vpermil2_op))
13603     {
13604       char suffix [4];
13605       char *p = obuf + strlen (obuf) - 3;
13606       suffix[0] = p[0];
13607       suffix[1] = p[1];
13608       suffix[2] = p[2];
13609       suffix[3] = '\0';
13610       sprintf (p, "%s%s", vpermil2_op[vpermil2_type], suffix);
13611     }
13612   else
13613     {
13614       /* We have a reserved extension byte.  Output it directly.  */
13615       scratchbuf[0] = '$';
13616       print_operand_value (scratchbuf + 1, 1, vpermil2_type);
13617       oappend (scratchbuf + intel_syntax);
13618       scratchbuf[0] = '\0';
13619     }
13620 }