gas/config/m68k-parse.h

   1 /* m68k-parse.h -- header file for m68k assembler
   2    Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000,
   3    2003, 2004, 2005, 2006, 2007, 2009 Free Software Foundation, Inc.
   4
   5    This file is part of GAS, the GNU Assembler.
   6
   7    GAS is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GAS is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #ifndef M68K_PARSE_H
  23 #define M68K_PARSE_H
  24
  25 /* This header file defines things which are shared between the
  26    operand parser in m68k.y and the m68k assembler proper in
  27    tc-m68k.c.  */
  28
  29 /* The various m68k registers.  */
  30
  31 /* DATA and ADDR have to be contiguous, so that reg-DATA gives
  32    0-7==data reg, 8-15==addr reg for operands that take both types.
  33
  34    We don't use forms like "ADDR0 = ADDR" here because this file is
  35    likely to be used on an Apollo, and the broken Apollo compiler
  36    gives an `undefined variable' error if we do that, according to
  37    troy@cbme.unsw.edu.au.  */
  38
  39 #define DATA DATA0
  40 #define ADDR ADDR0
  41 #define SP ADDR7
  42 #define BAD BAD0
  43 #define BAC BAC0
  44
  45 enum m68k_register
  46 {
  47   DATA0 = 1,                    /*   1- 8 == data registers 0-7 */
  48   DATA1,
  49   DATA2,
  50   DATA3,
  51   DATA4,
  52   DATA5,
  53   DATA6,
  54   DATA7,
  55
  56   ADDR0,
  57   ADDR1,
  58   ADDR2,
  59   ADDR3,
  60   ADDR4,
  61   ADDR5,
  62   ADDR6,
  63   ADDR7,
  64
  65   FP0,                          /* Eight FP registers */
  66   FP1,
  67   FP2,
  68   FP3,
  69   FP4,
  70   FP5,
  71   FP6,
  72   FP7,
  73
  74   COP0,                         /* Co-processor #0-#7 */
  75   COP1,
  76   COP2,
  77   COP3,
  78   COP4,
  79   COP5,
  80   COP6,
  81   COP7,
  82
  83   PC,                           /* Program counter */
  84   ZPC,                          /* Hack for Program space, but 0 addressing */
  85   SR,                           /* Status Reg */
  86   CCR,                          /* Condition code Reg */
  87   ACC,                          /* Accumulator Reg0 (EMAC or ACC on MAC).  */
  88   ACC1,                         /* Accumulator Reg 1 (EMAC).  */
  89   ACC2,                         /* Accumulator Reg 2 (EMAC).  */
  90   ACC3,                         /* Accumulator Reg 3 (EMAC).  */
  91   ACCEXT01,                     /* Accumulator extension 0&1 (EMAC).  */
  92   ACCEXT23,                     /* Accumulator extension 2&3 (EMAC).  */
  93   MACSR,                        /* MAC Status Reg */
  94   MASK,                         /* Modulus Reg */
  95
  96   /* These have to be grouped together for the movec instruction to work.  */
  97   USP,                          /*  User Stack Pointer */
  98   ISP,                          /*  Interrupt stack pointer */
  99   SFC,
 100   DFC,
 101   CACR,
 102   VBR,
 103   CAAR,
 104   CPUCR,
 105   MSP,
 106   ITT0,
 107   ITT1,
 108   DTT0,
 109   DTT1,
 110   MMUSR,
 111   TC,
 112   SRP,
 113   URP,
 114   BUSCR,                        /* 68060 added these.  */
 115   PCR,
 116   ROMBAR,                       /* mcf5200 added these.  */
 117   RAMBAR_ALT,                   /* Some CF chips have RAMBAR using
 118                                    RAMBAR0's number */
 119   RAMBAR0,
 120   RAMBAR1,
 121   MMUBAR,                       /* mcfv4e added these.  */
 122   ROMBAR0,                      /* mcfv4e added these.  */
 123   ROMBAR1,                      /* mcfv4e added these.  */
 124   MPCR, EDRAMBAR, SECMBAR,      /* mcfv4e added these.  */
 125   PCR1U0, PCR1L0, PCR1U1, PCR1L1,/* mcfv4e added these.  */
 126   PCR2U0, PCR2L0, PCR2U1, PCR2L1,/* mcfv4e added these.  */
 127   PCR3U0, PCR3L0, PCR3U1, PCR3L1,/* mcfv4e added these.  */
 128   MBAR0, MBAR1,                 /* mcfv4e added these.  */
 129   ACR0, ACR1, ACR2, ACR3,       /* mcf5200 added these.  */
 130   ACR4, ACR5, ACR6, ACR7,       /* mcf54418 added these.  */
 131   FLASHBAR, RAMBAR,             /* mcf528x added these.  */
 132   MBAR2,                        /* mcf5249 added this.  */
 133   MBAR,
 134   RGPIOBAR,                     /* mcf54418 added this.  */
 135   ASID,                         /* m5475.  */
 136   CAC,                          /* fido added this.  */
 137   MBO,
 138 #define last_movec_reg MBO
 139   /* End of movec ordering constraints.  */
 140
 141   FPI,
 142   FPS,
 143   FPC,
 144
 145   DRP,                          /* 68851 or 68030 MMU regs */
 146   CRP,
 147   CAL,
 148   VAL,
 149   SCC,
 150   AC,
 151   BAD0,
 152   BAD1,
 153   BAD2,
 154   BAD3,
 155   BAD4,
 156   BAD5,
 157   BAD6,
 158   BAD7,
 159   BAC0,
 160   BAC1,
 161   BAC2,
 162   BAC3,
 163   BAC4,
 164   BAC5,
 165   BAC6,
 166   BAC7,
 167   PSR,                          /* aka MMUSR on 68030 (but not MMUSR on 68040)
 168                                    and ACUSR on 68ec030 */
 169   PCSR,
 170
 171   IC,                           /* instruction cache token */
 172   DC,                           /* data cache token */
 173   NC,                           /* no cache token */
 174   BC,                           /* both caches token */
 175
 176   TT0,                          /* 68030 access control unit regs */
 177   TT1,
 178
 179   ZDATA0,                       /* suppressed data registers.  */
 180   ZDATA1,
 181   ZDATA2,
 182   ZDATA3,
 183   ZDATA4,
 184   ZDATA5,
 185   ZDATA6,
 186   ZDATA7,
 187
 188   ZADDR0,                       /* suppressed address registers.  */
 189   ZADDR1,
 190   ZADDR2,
 191   ZADDR3,
 192   ZADDR4,
 193   ZADDR5,
 194   ZADDR6,
 195   ZADDR7,
 196
 197   /* Upper and lower half of data and address registers.  Order *must*
 198      be DATAxL, ADDRxL, DATAxU, ADDRxU.  */
 199   DATA0L,                       /* lower half of data registers */
 200   DATA1L,
 201   DATA2L,
 202   DATA3L,
 203   DATA4L,
 204   DATA5L,
 205   DATA6L,
 206   DATA7L,
 207
 208   ADDR0L,                       /* lower half of address registers */
 209   ADDR1L,
 210   ADDR2L,
 211   ADDR3L,
 212   ADDR4L,
 213   ADDR5L,
 214   ADDR6L,
 215   ADDR7L,
 216
 217   DATA0U,                       /* upper half of data registers */
 218   DATA1U,
 219   DATA2U,
 220   DATA3U,
 221   DATA4U,
 222   DATA5U,
 223   DATA6U,
 224   DATA7U,
 225
 226   ADDR0U,                       /* upper half of address registers */
 227   ADDR1U,
 228   ADDR2U,
 229   ADDR3U,
 230   ADDR4U,
 231   ADDR5U,
 232   ADDR6U,
 233   ADDR7U,
 234 };
 235
 236 /* Size information.  */
 237
 238 enum m68k_size
 239 {
 240   /* Unspecified.  */
 241   SIZE_UNSPEC,
 242
 243   /* Byte.  */
 244   SIZE_BYTE,
 245
 246   /* Word (2 bytes).  */
 247   SIZE_WORD,
 248
 249   /* Longword (4 bytes).  */
 250   SIZE_LONG
 251 };
 252
 253 /* The structure used to hold information about an index register.  */
 254
 255 struct m68k_indexreg
 256 {
 257   /* The index register itself.  */
 258   enum m68k_register reg;
 259
 260   /* The size to use.  */
 261   enum m68k_size size;
 262
 263   /* The value to scale by.  */
 264   int scale;
 265 };
 266
 267 #ifdef OBJ_ELF
 268 /* The type of a PIC expression.  */
 269
 270 enum pic_relocation
 271 {
 272   pic_none,                     /* not pic */
 273   pic_plt_pcrel,                /* @PLTPC */
 274   pic_got_pcrel,                /* @GOTPC */
 275   pic_plt_off,                  /* @PLT */
 276   pic_got_off,                  /* @GOT */
 277   pic_tls_gd,                   /* @TLSGD */
 278   pic_tls_ldm,                  /* @TLSLDM */
 279   pic_tls_ldo,                  /* @TLSLDO */
 280   pic_tls_ie,                   /* @TLSIE */
 281   pic_tls_le                    /* @TLSLE */
 282 };
 283 #endif
 284
 285 /* The structure used to hold information about an expression.  */
 286
 287 struct m68k_exp
 288 {
 289   /* The size to use.  */
 290   enum m68k_size size;
 291
 292 #ifdef OBJ_ELF
 293   /* The type of pic relocation if any.  */
 294   enum pic_relocation pic_reloc;
 295 #endif
 296
 297   /* The expression itself.  */
 298   expressionS exp;
 299 };
 300
 301 /* The operand modes.  */
 302
 303 enum m68k_operand_type
 304 {
 305   IMMED = 1,
 306   ABSL,
 307   DREG,
 308   AREG,
 309   FPREG,
 310   CONTROL,
 311   AINDR,
 312   AINC,
 313   ADEC,
 314   DISP,
 315   BASE,
 316   POST,
 317   PRE,
 318   LSH,  /* MAC/EMAC scalefactor '<<'.  */
 319   RSH,  /* MAC/EMAC scalefactor '>>'.  */
 320   REGLST
 321 };
 322
 323 /* The structure used to hold a parsed operand.  */
 324
 325 struct m68k_op
 326 {
 327   /* The type of operand.  */
 328   enum m68k_operand_type mode;
 329
 330   /* The main register.  */
 331   enum m68k_register reg;
 332
 333   /* The register mask for mode REGLST.  */
 334   unsigned long mask;
 335
 336   /* An error message.  */
 337   const char *error;
 338
 339   /* The index register.  */
 340   struct m68k_indexreg index;
 341
 342   /* The displacement.  */
 343   struct m68k_exp disp;
 344
 345   /* The outer displacement.  */
 346   struct m68k_exp odisp;
 347
 348   /* Is a trailing '&' added to an <ea>? (for MAC/EMAC mask addressing).  */
 349   int trailing_ampersand;
 350 };
 351
 352 #endif /* ! defined (M68K_PARSE_H) */
 353
 354 /* The parsing function.  */
 355
 356 extern int m68k_ip_op (char *, struct m68k_op *);
 357
 358 /* Whether register prefixes are optional.  */
 359 extern int flag_reg_prefix_optional;