opcodes/fr30-dis.c

   1 /* Disassembler interface for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 THIS FILE IS MACHINE GENERATED WITH CGEN.
   5 - the resultant file is machine generated, cgen-dis.in isn't
   6
   7 Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
   8
   9 This file is part of the GNU Binutils and GDB, the GNU debugger.
  10
  11 This program is free software; you can redistribute it and/or modify
  12 it under the terms of the GNU General Public License as published by
  13 the Free Software Foundation; either version 2, or (at your option)
  14 any later version.
  15
  16 This program is distributed in the hope that it will be useful,
  17 but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 GNU General Public License for more details.
  20
  21 You should have received a copy of the GNU General Public License
  22 along with this program; if not, write to the Free Software Foundation, Inc.,
  23 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  24
  25 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
  26    Keep that in mind.  */
  27
  28 #include "sysdep.h"
  29 #include <stdio.h>
  30 #include "ansidecl.h"
  31 #include "dis-asm.h"
  32 #include "bfd.h"
  33 #include "symcat.h"
  34 #include "fr30-desc.h"
  35 #include "fr30-opc.h"
  36 #include "opintl.h"
  37
  38 /* Default text to print if an instruction isn't recognized.  */
  39 #define UNKNOWN_INSN_MSG _("*unknown*")
  40
  41 static void print_normal
  42      PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
  43 static void print_address
  44      PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
  45 static void print_keyword
  46      PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
  47 static void print_insn_normal
  48      PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
  49               bfd_vma, int));
  50 static int print_insn
  51      PARAMS ((CGEN_CPU_DESC, bfd_vma,  disassemble_info *, char *, unsigned));
  52 static int default_print_insn
  53      PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
  54 static int read_insn
  55      PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
  56               CGEN_EXTRACT_INFO *, unsigned long *));
  57 \f
  58 /* -- disassembler routines inserted here */
  59
  60 /* -- dis.c */
  61 static void print_register_list
  62   PARAMS ((PTR, long, long, int));
  63 static void print_hi_register_list_ld
  64   PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
  65 static void print_low_register_list_ld
  66   PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
  67 static void print_hi_register_list_st
  68   PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
  69 static void print_low_register_list_st
  70   PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
  71 static void print_m4
  72   PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
  73
  74 static void
  75 print_register_list (dis_info, value, offset, load_store)
  76      PTR dis_info;
  77      long value;
  78      long offset;
  79      int load_store; /* 0 == load, 1 == store */
  80 {
  81   disassemble_info *info = dis_info;
  82   int mask;
  83   int index = 0;
  84   char* comma = "";
  85
  86   if (load_store)
  87     mask = 0x80;
  88   else
  89     mask = 1;
  90
  91   if (value & mask)
  92     {
  93       (*info->fprintf_func) (info->stream, "r%i", index + offset);
  94       comma = ",";
  95     }
  96
  97   for (index = 1; index <= 7; ++index)
  98     {
  99       if (load_store)
 100         mask >>= 1;
 101       else
 102         mask <<= 1;
 103
 104       if (value & mask)
 105         {
 106           (*info->fprintf_func) (info->stream, "%sr%i", comma, index + offset);
 107           comma = ",";
 108         }
 109     }
 110 }
 111
 112 static void
 113 print_hi_register_list_ld (cd, dis_info, value, attrs, pc, length)
 114      CGEN_CPU_DESC cd;
 115      PTR dis_info;
 116      long value;
 117      unsigned int attrs;
 118      bfd_vma pc;
 119      int length;
 120 {
 121   print_register_list (dis_info, value, 8, 0/*load*/);
 122 }
 123
 124 static void
 125 print_low_register_list_ld (cd, dis_info, value, attrs, pc, length)
 126      CGEN_CPU_DESC cd;
 127      PTR dis_info;
 128      long value;
 129      unsigned int attrs;
 130      bfd_vma pc;
 131      int length;
 132 {
 133   print_register_list (dis_info, value, 0, 0/*load*/);
 134 }
 135
 136 static void
 137 print_hi_register_list_st (cd, dis_info, value, attrs, pc, length)
 138      CGEN_CPU_DESC cd;
 139      PTR dis_info;
 140      long value;
 141      unsigned int attrs;
 142      bfd_vma pc;
 143      int length;
 144 {
 145   print_register_list (dis_info, value, 8, 1/*store*/);
 146 }
 147
 148 static void
 149 print_low_register_list_st (cd, dis_info, value, attrs, pc, length)
 150      CGEN_CPU_DESC cd;
 151      PTR dis_info;
 152      long value;
 153      unsigned int attrs;
 154      bfd_vma pc;
 155      int length;
 156 {
 157   print_register_list (dis_info, value, 0, 1/*store*/);
 158 }
 159
 160 static void
 161 print_m4 (cd, dis_info, value, attrs, pc, length)
 162      CGEN_CPU_DESC cd;
 163      PTR dis_info;
 164      long value;
 165      unsigned int attrs;
 166      bfd_vma pc;
 167      int length;
 168 {
 169   disassemble_info *info = (disassemble_info *) dis_info;
 170   (*info->fprintf_func) (info->stream, "%ld", value);
 171 }
 172 /* -- */
 173
 174 void fr30_cgen_print_operand
 175   PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
 176            void const *, bfd_vma, int));
 177
 178 /* Main entry point for printing operands.
 179    XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
 180    of dis-asm.h on cgen.h.
 181
 182    This function is basically just a big switch statement.  Earlier versions
 183    used tables to look up the function to use, but
 184    - if the table contains both assembler and disassembler functions then
 185      the disassembler contains much of the assembler and vice-versa,
 186    - there's a lot of inlining possibilities as things grow,
 187    - using a switch statement avoids the function call overhead.
 188
 189    This function could be moved into `print_insn_normal', but keeping it
 190    separate makes clear the interface between `print_insn_normal' and each of
 191    the handlers.
 192 */
 193
 194 void
 195 fr30_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
 196      CGEN_CPU_DESC cd;
 197      int opindex;
 198      PTR xinfo;
 199      CGEN_FIELDS *fields;
 200      void const *attrs ATTRIBUTE_UNUSED;
 201      bfd_vma pc;
 202      int length;
 203 {
 204  disassemble_info *info = (disassemble_info *) xinfo;
 205
 206   switch (opindex)
 207     {
 208     case FR30_OPERAND_CRI :
 209       print_keyword (cd, info, & fr30_cgen_opval_cr_names, fields->f_CRi, 0);
 210       break;
 211     case FR30_OPERAND_CRJ :
 212       print_keyword (cd, info, & fr30_cgen_opval_cr_names, fields->f_CRj, 0);
 213       break;
 214     case FR30_OPERAND_R13 :
 215       print_keyword (cd, info, & fr30_cgen_opval_h_r13, 0, 0);
 216       break;
 217     case FR30_OPERAND_R14 :
 218       print_keyword (cd, info, & fr30_cgen_opval_h_r14, 0, 0);
 219       break;
 220     case FR30_OPERAND_R15 :
 221       print_keyword (cd, info, & fr30_cgen_opval_h_r15, 0, 0);
 222       break;
 223     case FR30_OPERAND_RI :
 224       print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Ri, 0);
 225       break;
 226     case FR30_OPERAND_RIC :
 227       print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Ric, 0);
 228       break;
 229     case FR30_OPERAND_RJ :
 230       print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Rj, 0);
 231       break;
 232     case FR30_OPERAND_RJC :
 233       print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Rjc, 0);
 234       break;
 235     case FR30_OPERAND_RS1 :
 236       print_keyword (cd, info, & fr30_cgen_opval_dr_names, fields->f_Rs1, 0);
 237       break;
 238     case FR30_OPERAND_RS2 :
 239       print_keyword (cd, info, & fr30_cgen_opval_dr_names, fields->f_Rs2, 0);
 240       break;
 241     case FR30_OPERAND_CC :
 242       print_normal (cd, info, fields->f_cc, 0, pc, length);
 243       break;
 244     case FR30_OPERAND_CCC :
 245       print_normal (cd, info, fields->f_ccc, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 246       break;
 247     case FR30_OPERAND_DIR10 :
 248       print_normal (cd, info, fields->f_dir10, 0, pc, length);
 249       break;
 250     case FR30_OPERAND_DIR8 :
 251       print_normal (cd, info, fields->f_dir8, 0, pc, length);
 252       break;
 253     case FR30_OPERAND_DIR9 :
 254       print_normal (cd, info, fields->f_dir9, 0, pc, length);
 255       break;
 256     case FR30_OPERAND_DISP10 :
 257       print_normal (cd, info, fields->f_disp10, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 258       break;
 259     case FR30_OPERAND_DISP8 :
 260       print_normal (cd, info, fields->f_disp8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 261       break;
 262     case FR30_OPERAND_DISP9 :
 263       print_normal (cd, info, fields->f_disp9, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 264       break;
 265     case FR30_OPERAND_I20 :
 266       print_normal (cd, info, fields->f_i20, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
 267       break;
 268     case FR30_OPERAND_I32 :
 269       print_normal (cd, info, fields->f_i32, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
 270       break;
 271     case FR30_OPERAND_I8 :
 272       print_normal (cd, info, fields->f_i8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 273       break;
 274     case FR30_OPERAND_LABEL12 :
 275       print_address (cd, info, fields->f_rel12, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
 276       break;
 277     case FR30_OPERAND_LABEL9 :
 278       print_address (cd, info, fields->f_rel9, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
 279       break;
 280     case FR30_OPERAND_M4 :
 281       print_m4 (cd, info, fields->f_m4, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 282       break;
 283     case FR30_OPERAND_PS :
 284       print_keyword (cd, info, & fr30_cgen_opval_h_ps, 0, 0);
 285       break;
 286     case FR30_OPERAND_REGLIST_HI_LD :
 287       print_hi_register_list_ld (cd, info, fields->f_reglist_hi_ld, 0, pc, length);
 288       break;
 289     case FR30_OPERAND_REGLIST_HI_ST :
 290       print_hi_register_list_st (cd, info, fields->f_reglist_hi_st, 0, pc, length);
 291       break;
 292     case FR30_OPERAND_REGLIST_LOW_LD :
 293       print_low_register_list_ld (cd, info, fields->f_reglist_low_ld, 0, pc, length);
 294       break;
 295     case FR30_OPERAND_REGLIST_LOW_ST :
 296       print_low_register_list_st (cd, info, fields->f_reglist_low_st, 0, pc, length);
 297       break;
 298     case FR30_OPERAND_S10 :
 299       print_normal (cd, info, fields->f_s10, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 300       break;
 301     case FR30_OPERAND_U10 :
 302       print_normal (cd, info, fields->f_u10, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 303       break;
 304     case FR30_OPERAND_U4 :
 305       print_normal (cd, info, fields->f_u4, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 306       break;
 307     case FR30_OPERAND_U4C :
 308       print_normal (cd, info, fields->f_u4c, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 309       break;
 310     case FR30_OPERAND_U8 :
 311       print_normal (cd, info, fields->f_u8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 312       break;
 313     case FR30_OPERAND_UDISP6 :
 314       print_normal (cd, info, fields->f_udisp6, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 315       break;
 316
 317     default :
 318       /* xgettext:c-format */
 319       fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
 320                opindex);
 321     abort ();
 322   }
 323 }
 324
 325 cgen_print_fn * const fr30_cgen_print_handlers[] =
 326 {
 327   print_insn_normal,
 328 };
 329
 330
 331 void
 332 fr30_cgen_init_dis (cd)
 333      CGEN_CPU_DESC cd;
 334 {
 335   fr30_cgen_init_opcode_table (cd);
 336   fr30_cgen_init_ibld_table (cd);
 337   cd->print_handlers = & fr30_cgen_print_handlers[0];
 338   cd->print_operand = fr30_cgen_print_operand;
 339 }
 340
 341 \f
 342 /* Default print handler.  */
 343
 344 static void
 345 print_normal (cd, dis_info, value, attrs, pc, length)
 346      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
 347      PTR dis_info;
 348      long value;
 349      unsigned int attrs;
 350      bfd_vma pc ATTRIBUTE_UNUSED;
 351      int length ATTRIBUTE_UNUSED;
 352 {
 353   disassemble_info *info = (disassemble_info *) dis_info;
 354
 355 #ifdef CGEN_PRINT_NORMAL
 356   CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
 357 #endif
 358
 359   /* Print the operand as directed by the attributes.  */
 360   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
 361     ; /* nothing to do */
 362   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
 363     (*info->fprintf_func) (info->stream, "%ld", value);
 364   else
 365     (*info->fprintf_func) (info->stream, "0x%lx", value);
 366 }
 367
 368 /* Default address handler.  */
 369
 370 static void
 371 print_address (cd, dis_info, value, attrs, pc, length)
 372      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
 373      PTR dis_info;
 374      bfd_vma value;
 375      unsigned int attrs;
 376      bfd_vma pc ATTRIBUTE_UNUSED;
 377      int length ATTRIBUTE_UNUSED;
 378 {
 379   disassemble_info *info = (disassemble_info *) dis_info;
 380
 381 #ifdef CGEN_PRINT_ADDRESS
 382   CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
 383 #endif
 384
 385   /* Print the operand as directed by the attributes.  */
 386   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
 387     ; /* nothing to do */
 388   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
 389     (*info->print_address_func) (value, info);
 390   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
 391     (*info->print_address_func) (value, info);
 392   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
 393     (*info->fprintf_func) (info->stream, "%ld", (long) value);
 394   else
 395     (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
 396 }
 397
 398 /* Keyword print handler.  */
 399
 400 static void
 401 print_keyword (cd, dis_info, keyword_table, value, attrs)
 402      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
 403      PTR dis_info;
 404      CGEN_KEYWORD *keyword_table;
 405      long value;
 406      unsigned int attrs ATTRIBUTE_UNUSED;
 407 {
 408   disassemble_info *info = (disassemble_info *) dis_info;
 409   const CGEN_KEYWORD_ENTRY *ke;
 410
 411   ke = cgen_keyword_lookup_value (keyword_table, value);
 412   if (ke != NULL)
 413     (*info->fprintf_func) (info->stream, "%s", ke->name);
 414   else
 415     (*info->fprintf_func) (info->stream, "???");
 416 }
 417 \f
 418 /* Default insn printer.
 419
 420    DIS_INFO is defined as `PTR' so the disassembler needn't know anything
 421    about disassemble_info.  */
 422
 423 static void
 424 print_insn_normal (cd, dis_info, insn, fields, pc, length)
 425      CGEN_CPU_DESC cd;
 426      PTR dis_info;
 427      const CGEN_INSN *insn;
 428      CGEN_FIELDS *fields;
 429      bfd_vma pc;
 430      int length;
 431 {
 432   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
 433   disassemble_info *info = (disassemble_info *) dis_info;
 434   const CGEN_SYNTAX_CHAR_TYPE *syn;
 435
 436   CGEN_INIT_PRINT (cd);
 437
 438   for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
 439     {
 440       if (CGEN_SYNTAX_MNEMONIC_P (*syn))
 441         {
 442           (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
 443           continue;
 444         }
 445       if (CGEN_SYNTAX_CHAR_P (*syn))
 446         {
 447           (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
 448           continue;
 449         }
 450
 451       /* We have an operand.  */
 452       fr30_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
 453                                  fields, CGEN_INSN_ATTRS (insn), pc, length);
 454     }
 455 }
 456 \f
 457 /* Subroutine of print_insn. Reads an insn into the given buffers and updates
 458    the extract info.
 459    Returns 0 if all is well, non-zero otherwise.  */
 460
 461 static int
 462 read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
 463      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
 464      bfd_vma pc;
 465      disassemble_info *info;
 466      char *buf;
 467      int buflen;
 468      CGEN_EXTRACT_INFO *ex_info;
 469      unsigned long *insn_value;
 470 {
 471   int status = (*info->read_memory_func) (pc, buf, buflen, info);
 472   if (status != 0)
 473     {
 474       (*info->memory_error_func) (status, pc, info);
 475       return -1;
 476     }
 477
 478   ex_info->dis_info = info;
 479   ex_info->valid = (1 << buflen) - 1;
 480   ex_info->insn_bytes = buf;
 481
 482   *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
 483   return 0;
 484 }
 485
 486 /* Utility to print an insn.
 487    BUF is the base part of the insn, target byte order, BUFLEN bytes long.
 488    The result is the size of the insn in bytes or zero for an unknown insn
 489    or -1 if an error occurs fetching data (memory_error_func will have
 490    been called).  */
 491
 492 static int
 493 print_insn (cd, pc, info, buf, buflen)
 494      CGEN_CPU_DESC cd;
 495      bfd_vma pc;
 496      disassemble_info *info;
 497      char *buf;
 498      unsigned int buflen;
 499 {
 500   CGEN_INSN_INT insn_value;
 501   const CGEN_INSN_LIST *insn_list;
 502   CGEN_EXTRACT_INFO ex_info;
 503
 504   /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
 505   insn_value = cgen_get_insn_value (cd, buf, buflen * 8);
 506
 507   /* Fill in ex_info fields like read_insn would.  Don't actually call
 508      read_insn, since the incoming buffer is already read (and possibly
 509      modified a la m32r).  */
 510   ex_info.valid = (1 << buflen) - 1;
 511   ex_info.dis_info = info;
 512   ex_info.insn_bytes = buf;
 513
 514   /* The instructions are stored in hash lists.
 515      Pick the first one and keep trying until we find the right one.  */
 516
 517   insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
 518   while (insn_list != NULL)
 519     {
 520       const CGEN_INSN *insn = insn_list->insn;
 521       CGEN_FIELDS fields;
 522       int length;
 523       unsigned long insn_value_cropped;
 524
 525 #ifdef CGEN_VALIDATE_INSN_SUPPORTED
 526       /* Not needed as insn shouldn't be in hash lists if not supported.  */
 527       /* Supported by this cpu?  */
 528       if (! fr30_cgen_insn_supported (cd, insn))
 529         {
 530           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 531           continue;
 532         }
 533 #endif
 534
 535       /* Basic bit mask must be correct.  */
 536       /* ??? May wish to allow target to defer this check until the extract
 537          handler.  */
 538
 539       /* Base size may exceed this instruction's size.  Extract the
 540          relevant part from the buffer. */
 541       if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
 542           (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
 543         insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
 544                                            info->endian == BFD_ENDIAN_BIG);
 545       else
 546         insn_value_cropped = insn_value;
 547
 548       if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
 549           == CGEN_INSN_BASE_VALUE (insn))
 550         {
 551           /* Printing is handled in two passes.  The first pass parses the
 552              machine insn and extracts the fields.  The second pass prints
 553              them.  */
 554
 555           /* Make sure the entire insn is loaded into insn_value, if it
 556              can fit.  */
 557           if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
 558               (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
 559             {
 560               unsigned long full_insn_value;
 561               int rc = read_insn (cd, pc, info, buf,
 562                                   CGEN_INSN_BITSIZE (insn) / 8,
 563                                   & ex_info, & full_insn_value);
 564               if (rc != 0)
 565                 return rc;
 566               length = CGEN_EXTRACT_FN (cd, insn)
 567                 (cd, insn, &ex_info, full_insn_value, &fields, pc);
 568             }
 569           else
 570             length = CGEN_EXTRACT_FN (cd, insn)
 571               (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
 572
 573           /* length < 0 -> error */
 574           if (length < 0)
 575             return length;
 576           if (length > 0)
 577             {
 578               CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
 579               /* length is in bits, result is in bytes */
 580               return length / 8;
 581             }
 582         }
 583
 584       insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 585     }
 586
 587   return 0;
 588 }
 589
 590 /* Default value for CGEN_PRINT_INSN.
 591    The result is the size of the insn in bytes or zero for an unknown insn
 592    or -1 if an error occured fetching bytes.  */
 593
 594 #ifndef CGEN_PRINT_INSN
 595 #define CGEN_PRINT_INSN default_print_insn
 596 #endif
 597
 598 static int
 599 default_print_insn (cd, pc, info)
 600      CGEN_CPU_DESC cd;
 601      bfd_vma pc;
 602      disassemble_info *info;
 603 {
 604   char buf[CGEN_MAX_INSN_SIZE];
 605   int buflen;
 606   int status;
 607
 608   /* Attempt to read the base part of the insn.  */
 609   buflen = cd->base_insn_bitsize / 8;
 610   status = (*info->read_memory_func) (pc, buf, buflen, info);
 611
 612   /* Try again with the minimum part, if min < base.  */
 613   if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
 614     {
 615       buflen = cd->min_insn_bitsize / 8;
 616       status = (*info->read_memory_func) (pc, buf, buflen, info);
 617     }
 618
 619   if (status != 0)
 620     {
 621       (*info->memory_error_func) (status, pc, info);
 622       return -1;
 623     }
 624
 625   return print_insn (cd, pc, info, buf, buflen);
 626 }
 627
 628 /* Main entry point.
 629    Print one instruction from PC on INFO->STREAM.
 630    Return the size of the instruction (in bytes).  */
 631
 632 int
 633 print_insn_fr30 (pc, info)
 634      bfd_vma pc;
 635      disassemble_info *info;
 636 {
 637   static CGEN_CPU_DESC cd = 0;
 638   static int prev_isa;
 639   static int prev_mach;
 640   static int prev_endian;
 641   int length;
 642   int isa,mach;
 643   int endian = (info->endian == BFD_ENDIAN_BIG
 644                 ? CGEN_ENDIAN_BIG
 645                 : CGEN_ENDIAN_LITTLE);
 646   enum bfd_architecture arch;
 647
 648   /* ??? gdb will set mach but leave the architecture as "unknown" */
 649 #ifndef CGEN_BFD_ARCH
 650 #define CGEN_BFD_ARCH bfd_arch_fr30
 651 #endif
 652   arch = info->arch;
 653   if (arch == bfd_arch_unknown)
 654     arch = CGEN_BFD_ARCH;
 655
 656   /* There's no standard way to compute the machine or isa number
 657      so we leave it to the target.  */
 658 #ifdef CGEN_COMPUTE_MACH
 659   mach = CGEN_COMPUTE_MACH (info);
 660 #else
 661   mach = info->mach;
 662 #endif
 663
 664 #ifdef CGEN_COMPUTE_ISA
 665   isa = CGEN_COMPUTE_ISA (info);
 666 #else
 667   isa = 0;
 668 #endif
 669
 670   /* If we've switched cpu's, close the current table and open a new one.  */
 671   if (cd
 672       && (isa != prev_isa
 673           || mach != prev_mach
 674           || endian != prev_endian))
 675     {
 676       fr30_cgen_cpu_close (cd);
 677       cd = 0;
 678     }
 679
 680   /* If we haven't initialized yet, initialize the opcode table.  */
 681   if (! cd)
 682     {
 683       const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
 684       const char *mach_name;
 685
 686       if (!arch_type)
 687         abort ();
 688       mach_name = arch_type->printable_name;
 689
 690       prev_isa = isa;
 691       prev_mach = mach;
 692       prev_endian = endian;
 693       cd = fr30_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
 694                                  CGEN_CPU_OPEN_BFDMACH, mach_name,
 695                                  CGEN_CPU_OPEN_ENDIAN, prev_endian,
 696                                  CGEN_CPU_OPEN_END);
 697       if (!cd)
 698         abort ();
 699       fr30_cgen_init_dis (cd);
 700     }
 701
 702   /* We try to have as much common code as possible.
 703      But at this point some targets need to take over.  */
 704   /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
 705      but if not possible try to move this hook elsewhere rather than
 706      have two hooks.  */
 707   length = CGEN_PRINT_INSN (cd, pc, info);
 708   if (length > 0)
 709     return length;
 710   if (length < 0)
 711     return -1;
 712
 713   (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 714   return cd->default_insn_bitsize / 8;
 715 }