1 /* Disassembler interface for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
4 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 - the resultant file is machine generated, cgen-dis.in isn't
7 Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
9 This file is part of the GNU Binutils and GDB, the GNU debugger.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software Foundation, Inc.,
23 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
25 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
34 #include "m32r-desc.h"
38 /* Default text to print if an instruction isn't recognized. */
39 #define UNKNOWN_INSN_MSG _("*unknown*")
41 static void print_normal
42 PARAMS ((CGEN_CPU_DESC
, PTR
, long, unsigned int, bfd_vma
, int));
43 static void print_address
44 PARAMS ((CGEN_CPU_DESC
, PTR
, bfd_vma
, unsigned int, bfd_vma
, int));
45 static void print_keyword
46 PARAMS ((CGEN_CPU_DESC
, PTR
, CGEN_KEYWORD
*, long, unsigned int));
47 static void print_insn_normal
48 PARAMS ((CGEN_CPU_DESC
, PTR
, const CGEN_INSN
*, CGEN_FIELDS
*,
51 PARAMS ((CGEN_CPU_DESC
, bfd_vma
, disassemble_info
*, char *, unsigned));
52 static int default_print_insn
53 PARAMS ((CGEN_CPU_DESC
, bfd_vma
, disassemble_info
*));
55 PARAMS ((CGEN_CPU_DESC
, bfd_vma
, disassemble_info
*, char *, int,
56 CGEN_EXTRACT_INFO
*, unsigned long *));
58 /* -- disassembler routines inserted here */
61 static void print_hash
PARAMS ((CGEN_CPU_DESC
, PTR
, long, unsigned, bfd_vma
, int));
62 static int my_print_insn
PARAMS ((CGEN_CPU_DESC
, bfd_vma
, disassemble_info
*));
64 /* Immediate values are prefixed with '#'. */
66 #define CGEN_PRINT_NORMAL(cd, info, value, attrs, pc, length) \
69 if (CGEN_BOOL_ATTR ((attrs), CGEN_OPERAND_HASH_PREFIX)) \
70 (*info->fprintf_func) (info->stream, "#"); \
74 /* Handle '#' prefixes as operands. */
77 print_hash (cd
, dis_info
, value
, attrs
, pc
, length
)
85 disassemble_info
*info
= (disassemble_info
*) dis_info
;
86 (*info
->fprintf_func
) (info
->stream
, "#");
89 #undef CGEN_PRINT_INSN
90 #define CGEN_PRINT_INSN my_print_insn
93 my_print_insn (cd
, pc
, info
)
96 disassemble_info
*info
;
98 char buffer
[CGEN_MAX_INSN_SIZE
];
101 int buflen
= (pc
& 3) == 0 ? 4 : 2;
103 /* Read the base part of the insn. */
105 status
= (*info
->read_memory_func
) (pc
, buf
, buflen
, info
);
108 (*info
->memory_error_func
) (status
, pc
, info
);
113 if ((pc
& 3) == 0 && (buf
[0] & 0x80) != 0)
114 return print_insn (cd
, pc
, info
, buf
, buflen
);
116 /* Print the first insn. */
119 if (print_insn (cd
, pc
, info
, buf
, 2) == 0)
120 (*info
->fprintf_func
) (info
->stream
, UNKNOWN_INSN_MSG
);
127 (*info
->fprintf_func
) (info
->stream
, " || ");
131 (*info
->fprintf_func
) (info
->stream
, " -> ");
133 /* The "& 3" is to pass a consistent address.
134 Parallel insns arguably both begin on the word boundary.
135 Also, branch insns are calculated relative to the word boundary. */
136 if (print_insn (cd
, pc
& ~ (bfd_vma
) 3, info
, buf
, 2) == 0)
137 (*info
->fprintf_func
) (info
->stream
, UNKNOWN_INSN_MSG
);
139 return (pc
& 3) ? 2 : 4;
144 void m32r_cgen_print_operand
145 PARAMS ((CGEN_CPU_DESC
, int, PTR
, CGEN_FIELDS
*,
146 void const *, bfd_vma
, int));
148 /* Main entry point for printing operands.
149 XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
150 of dis-asm.h on cgen.h.
152 This function is basically just a big switch statement. Earlier versions
153 used tables to look up the function to use, but
154 - if the table contains both assembler and disassembler functions then
155 the disassembler contains much of the assembler and vice-versa,
156 - there's a lot of inlining possibilities as things grow,
157 - using a switch statement avoids the function call overhead.
159 This function could be moved into `print_insn_normal', but keeping it
160 separate makes clear the interface between `print_insn_normal' and each of
165 m32r_cgen_print_operand (cd
, opindex
, xinfo
, fields
, attrs
, pc
, length
)
170 void const *attrs ATTRIBUTE_UNUSED
;
174 disassemble_info
*info
= (disassemble_info
*) xinfo
;
178 case M32R_OPERAND_ACC
:
179 print_keyword (cd
, info
, & m32r_cgen_opval_h_accums
, fields
->f_acc
, 0);
181 case M32R_OPERAND_ACCD
:
182 print_keyword (cd
, info
, & m32r_cgen_opval_h_accums
, fields
->f_accd
, 0);
184 case M32R_OPERAND_ACCS
:
185 print_keyword (cd
, info
, & m32r_cgen_opval_h_accums
, fields
->f_accs
, 0);
187 case M32R_OPERAND_DCR
:
188 print_keyword (cd
, info
, & m32r_cgen_opval_cr_names
, fields
->f_r1
, 0);
190 case M32R_OPERAND_DISP16
:
191 print_address (cd
, info
, fields
->f_disp16
, 0|(1<<CGEN_OPERAND_RELOC
)|(1<<CGEN_OPERAND_PCREL_ADDR
), pc
, length
);
193 case M32R_OPERAND_DISP24
:
194 print_address (cd
, info
, fields
->f_disp24
, 0|(1<<CGEN_OPERAND_RELAX
)|(1<<CGEN_OPERAND_RELOC
)|(1<<CGEN_OPERAND_PCREL_ADDR
), pc
, length
);
196 case M32R_OPERAND_DISP8
:
197 print_address (cd
, info
, fields
->f_disp8
, 0|(1<<CGEN_OPERAND_RELAX
)|(1<<CGEN_OPERAND_RELOC
)|(1<<CGEN_OPERAND_PCREL_ADDR
), pc
, length
);
199 case M32R_OPERAND_DR
:
200 print_keyword (cd
, info
, & m32r_cgen_opval_gr_names
, fields
->f_r1
, 0);
202 case M32R_OPERAND_HASH
:
203 print_hash (cd
, info
, 0, 0|(1<<CGEN_OPERAND_SIGNED
), pc
, length
);
205 case M32R_OPERAND_HI16
:
206 print_normal (cd
, info
, fields
->f_hi16
, 0|(1<<CGEN_OPERAND_SIGN_OPT
), pc
, length
);
208 case M32R_OPERAND_IMM1
:
209 print_normal (cd
, info
, fields
->f_imm1
, 0|(1<<CGEN_OPERAND_HASH_PREFIX
), pc
, length
);
211 case M32R_OPERAND_SCR
:
212 print_keyword (cd
, info
, & m32r_cgen_opval_cr_names
, fields
->f_r2
, 0);
214 case M32R_OPERAND_SIMM16
:
215 print_normal (cd
, info
, fields
->f_simm16
, 0|(1<<CGEN_OPERAND_SIGNED
)|(1<<CGEN_OPERAND_HASH_PREFIX
), pc
, length
);
217 case M32R_OPERAND_SIMM8
:
218 print_normal (cd
, info
, fields
->f_simm8
, 0|(1<<CGEN_OPERAND_SIGNED
)|(1<<CGEN_OPERAND_HASH_PREFIX
), pc
, length
);
220 case M32R_OPERAND_SLO16
:
221 print_normal (cd
, info
, fields
->f_simm16
, 0|(1<<CGEN_OPERAND_SIGNED
), pc
, length
);
223 case M32R_OPERAND_SR
:
224 print_keyword (cd
, info
, & m32r_cgen_opval_gr_names
, fields
->f_r2
, 0);
226 case M32R_OPERAND_SRC1
:
227 print_keyword (cd
, info
, & m32r_cgen_opval_gr_names
, fields
->f_r1
, 0);
229 case M32R_OPERAND_SRC2
:
230 print_keyword (cd
, info
, & m32r_cgen_opval_gr_names
, fields
->f_r2
, 0);
232 case M32R_OPERAND_UIMM16
:
233 print_normal (cd
, info
, fields
->f_uimm16
, 0|(1<<CGEN_OPERAND_HASH_PREFIX
), pc
, length
);
235 case M32R_OPERAND_UIMM24
:
236 print_address (cd
, info
, fields
->f_uimm24
, 0|(1<<CGEN_OPERAND_HASH_PREFIX
)|(1<<CGEN_OPERAND_RELOC
)|(1<<CGEN_OPERAND_ABS_ADDR
), pc
, length
);
238 case M32R_OPERAND_UIMM4
:
239 print_normal (cd
, info
, fields
->f_uimm4
, 0|(1<<CGEN_OPERAND_HASH_PREFIX
), pc
, length
);
241 case M32R_OPERAND_UIMM5
:
242 print_normal (cd
, info
, fields
->f_uimm5
, 0|(1<<CGEN_OPERAND_HASH_PREFIX
), pc
, length
);
244 case M32R_OPERAND_ULO16
:
245 print_normal (cd
, info
, fields
->f_uimm16
, 0, pc
, length
);
249 /* xgettext:c-format */
250 fprintf (stderr
, _("Unrecognized field %d while printing insn.\n"),
256 cgen_print_fn
* const m32r_cgen_print_handlers
[] =
263 m32r_cgen_init_dis (cd
)
266 m32r_cgen_init_opcode_table (cd
);
267 m32r_cgen_init_ibld_table (cd
);
268 cd
->print_handlers
= & m32r_cgen_print_handlers
[0];
269 cd
->print_operand
= m32r_cgen_print_operand
;
273 /* Default print handler. */
276 print_normal (cd
, dis_info
, value
, attrs
, pc
, length
)
277 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED
;
281 bfd_vma pc ATTRIBUTE_UNUSED
;
282 int length ATTRIBUTE_UNUSED
;
284 disassemble_info
*info
= (disassemble_info
*) dis_info
;
286 #ifdef CGEN_PRINT_NORMAL
287 CGEN_PRINT_NORMAL (cd
, info
, value
, attrs
, pc
, length
);
290 /* Print the operand as directed by the attributes. */
291 if (CGEN_BOOL_ATTR (attrs
, CGEN_OPERAND_SEM_ONLY
))
292 ; /* nothing to do */
293 else if (CGEN_BOOL_ATTR (attrs
, CGEN_OPERAND_SIGNED
))
294 (*info
->fprintf_func
) (info
->stream
, "%ld", value
);
296 (*info
->fprintf_func
) (info
->stream
, "0x%lx", value
);
299 /* Default address handler. */
302 print_address (cd
, dis_info
, value
, attrs
, pc
, length
)
303 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED
;
307 bfd_vma pc ATTRIBUTE_UNUSED
;
308 int length ATTRIBUTE_UNUSED
;
310 disassemble_info
*info
= (disassemble_info
*) dis_info
;
312 #ifdef CGEN_PRINT_ADDRESS
313 CGEN_PRINT_ADDRESS (cd
, info
, value
, attrs
, pc
, length
);
316 /* Print the operand as directed by the attributes. */
317 if (CGEN_BOOL_ATTR (attrs
, CGEN_OPERAND_SEM_ONLY
))
318 ; /* nothing to do */
319 else if (CGEN_BOOL_ATTR (attrs
, CGEN_OPERAND_PCREL_ADDR
))
320 (*info
->print_address_func
) (value
, info
);
321 else if (CGEN_BOOL_ATTR (attrs
, CGEN_OPERAND_ABS_ADDR
))
322 (*info
->print_address_func
) (value
, info
);
323 else if (CGEN_BOOL_ATTR (attrs
, CGEN_OPERAND_SIGNED
))
324 (*info
->fprintf_func
) (info
->stream
, "%ld", (long) value
);
326 (*info
->fprintf_func
) (info
->stream
, "0x%lx", (long) value
);
329 /* Keyword print handler. */
332 print_keyword (cd
, dis_info
, keyword_table
, value
, attrs
)
333 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED
;
335 CGEN_KEYWORD
*keyword_table
;
337 unsigned int attrs ATTRIBUTE_UNUSED
;
339 disassemble_info
*info
= (disassemble_info
*) dis_info
;
340 const CGEN_KEYWORD_ENTRY
*ke
;
342 ke
= cgen_keyword_lookup_value (keyword_table
, value
);
344 (*info
->fprintf_func
) (info
->stream
, "%s", ke
->name
);
346 (*info
->fprintf_func
) (info
->stream
, "???");
349 /* Default insn printer.
351 DIS_INFO is defined as `PTR' so the disassembler needn't know anything
352 about disassemble_info. */
355 print_insn_normal (cd
, dis_info
, insn
, fields
, pc
, length
)
358 const CGEN_INSN
*insn
;
363 const CGEN_SYNTAX
*syntax
= CGEN_INSN_SYNTAX (insn
);
364 disassemble_info
*info
= (disassemble_info
*) dis_info
;
365 const CGEN_SYNTAX_CHAR_TYPE
*syn
;
367 CGEN_INIT_PRINT (cd
);
369 for (syn
= CGEN_SYNTAX_STRING (syntax
); *syn
; ++syn
)
371 if (CGEN_SYNTAX_MNEMONIC_P (*syn
))
373 (*info
->fprintf_func
) (info
->stream
, "%s", CGEN_INSN_MNEMONIC (insn
));
376 if (CGEN_SYNTAX_CHAR_P (*syn
))
378 (*info
->fprintf_func
) (info
->stream
, "%c", CGEN_SYNTAX_CHAR (*syn
));
382 /* We have an operand. */
383 m32r_cgen_print_operand (cd
, CGEN_SYNTAX_FIELD (*syn
), info
,
384 fields
, CGEN_INSN_ATTRS (insn
), pc
, length
);
388 /* Subroutine of print_insn. Reads an insn into the given buffers and updates
390 Returns 0 if all is well, non-zero otherwise. */
393 read_insn (cd
, pc
, info
, buf
, buflen
, ex_info
, insn_value
)
394 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED
;
396 disassemble_info
*info
;
399 CGEN_EXTRACT_INFO
*ex_info
;
400 unsigned long *insn_value
;
402 int status
= (*info
->read_memory_func
) (pc
, buf
, buflen
, info
);
405 (*info
->memory_error_func
) (status
, pc
, info
);
409 ex_info
->dis_info
= info
;
410 ex_info
->valid
= (1 << buflen
) - 1;
411 ex_info
->insn_bytes
= buf
;
413 *insn_value
= bfd_get_bits (buf
, buflen
* 8, info
->endian
== BFD_ENDIAN_BIG
);
417 /* Utility to print an insn.
418 BUF is the base part of the insn, target byte order, BUFLEN bytes long.
419 The result is the size of the insn in bytes or zero for an unknown insn
420 or -1 if an error occurs fetching data (memory_error_func will have
424 print_insn (cd
, pc
, info
, buf
, buflen
)
427 disassemble_info
*info
;
431 CGEN_INSN_INT insn_value
;
432 const CGEN_INSN_LIST
*insn_list
;
433 CGEN_EXTRACT_INFO ex_info
;
435 /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
436 insn_value
= cgen_get_insn_value (cd
, buf
, buflen
* 8);
438 /* Fill in ex_info fields like read_insn would. Don't actually call
439 read_insn, since the incoming buffer is already read (and possibly
440 modified a la m32r). */
441 ex_info
.valid
= (1 << buflen
) - 1;
442 ex_info
.dis_info
= info
;
443 ex_info
.insn_bytes
= buf
;
445 /* The instructions are stored in hash lists.
446 Pick the first one and keep trying until we find the right one. */
448 insn_list
= CGEN_DIS_LOOKUP_INSN (cd
, buf
, insn_value
);
449 while (insn_list
!= NULL
)
451 const CGEN_INSN
*insn
= insn_list
->insn
;
454 unsigned long insn_value_cropped
;
456 #ifdef CGEN_VALIDATE_INSN_SUPPORTED
457 /* Not needed as insn shouldn't be in hash lists if not supported. */
458 /* Supported by this cpu? */
459 if (! m32r_cgen_insn_supported (cd
, insn
))
461 insn_list
= CGEN_DIS_NEXT_INSN (insn_list
);
466 /* Basic bit mask must be correct. */
467 /* ??? May wish to allow target to defer this check until the extract
470 /* Base size may exceed this instruction's size. Extract the
471 relevant part from the buffer. */
472 if ((unsigned) (CGEN_INSN_BITSIZE (insn
) / 8) < buflen
&&
473 (unsigned) (CGEN_INSN_BITSIZE (insn
) / 8) <= sizeof (unsigned long))
474 insn_value_cropped
= bfd_get_bits (buf
, CGEN_INSN_BITSIZE (insn
),
475 info
->endian
== BFD_ENDIAN_BIG
);
477 insn_value_cropped
= insn_value
;
479 if ((insn_value_cropped
& CGEN_INSN_BASE_MASK (insn
))
480 == CGEN_INSN_BASE_VALUE (insn
))
482 /* Printing is handled in two passes. The first pass parses the
483 machine insn and extracts the fields. The second pass prints
486 /* Make sure the entire insn is loaded into insn_value, if it
488 if (((unsigned) CGEN_INSN_BITSIZE (insn
) > cd
->base_insn_bitsize
) &&
489 (unsigned) (CGEN_INSN_BITSIZE (insn
) / 8) <= sizeof (unsigned long))
491 unsigned long full_insn_value
;
492 int rc
= read_insn (cd
, pc
, info
, buf
,
493 CGEN_INSN_BITSIZE (insn
) / 8,
494 & ex_info
, & full_insn_value
);
497 length
= CGEN_EXTRACT_FN (cd
, insn
)
498 (cd
, insn
, &ex_info
, full_insn_value
, &fields
, pc
);
501 length
= CGEN_EXTRACT_FN (cd
, insn
)
502 (cd
, insn
, &ex_info
, insn_value_cropped
, &fields
, pc
);
504 /* length < 0 -> error */
509 CGEN_PRINT_FN (cd
, insn
) (cd
, info
, insn
, &fields
, pc
, length
);
510 /* length is in bits, result is in bytes */
515 insn_list
= CGEN_DIS_NEXT_INSN (insn_list
);
521 /* Default value for CGEN_PRINT_INSN.
522 The result is the size of the insn in bytes or zero for an unknown insn
523 or -1 if an error occured fetching bytes. */
525 #ifndef CGEN_PRINT_INSN
526 #define CGEN_PRINT_INSN default_print_insn
530 default_print_insn (cd
, pc
, info
)
533 disassemble_info
*info
;
535 char buf
[CGEN_MAX_INSN_SIZE
];
539 /* Attempt to read the base part of the insn. */
540 buflen
= cd
->base_insn_bitsize
/ 8;
541 status
= (*info
->read_memory_func
) (pc
, buf
, buflen
, info
);
543 /* Try again with the minimum part, if min < base. */
544 if (status
!= 0 && (cd
->min_insn_bitsize
< cd
->base_insn_bitsize
))
546 buflen
= cd
->min_insn_bitsize
/ 8;
547 status
= (*info
->read_memory_func
) (pc
, buf
, buflen
, info
);
552 (*info
->memory_error_func
) (status
, pc
, info
);
556 return print_insn (cd
, pc
, info
, buf
, buflen
);
560 Print one instruction from PC on INFO->STREAM.
561 Return the size of the instruction (in bytes). */
564 print_insn_m32r (pc
, info
)
566 disassemble_info
*info
;
568 static CGEN_CPU_DESC cd
= 0;
570 static int prev_mach
;
571 static int prev_endian
;
574 int endian
= (info
->endian
== BFD_ENDIAN_BIG
576 : CGEN_ENDIAN_LITTLE
);
577 enum bfd_architecture arch
;
579 /* ??? gdb will set mach but leave the architecture as "unknown" */
580 #ifndef CGEN_BFD_ARCH
581 #define CGEN_BFD_ARCH bfd_arch_m32r
584 if (arch
== bfd_arch_unknown
)
585 arch
= CGEN_BFD_ARCH
;
587 /* There's no standard way to compute the machine or isa number
588 so we leave it to the target. */
589 #ifdef CGEN_COMPUTE_MACH
590 mach
= CGEN_COMPUTE_MACH (info
);
595 #ifdef CGEN_COMPUTE_ISA
596 isa
= CGEN_COMPUTE_ISA (info
);
601 /* If we've switched cpu's, close the current table and open a new one. */
605 || endian
!= prev_endian
))
607 m32r_cgen_cpu_close (cd
);
611 /* If we haven't initialized yet, initialize the opcode table. */
614 const bfd_arch_info_type
*arch_type
= bfd_lookup_arch (arch
, mach
);
615 const char *mach_name
;
619 mach_name
= arch_type
->printable_name
;
623 prev_endian
= endian
;
624 cd
= m32r_cgen_cpu_open (CGEN_CPU_OPEN_ISAS
, prev_isa
,
625 CGEN_CPU_OPEN_BFDMACH
, mach_name
,
626 CGEN_CPU_OPEN_ENDIAN
, prev_endian
,
630 m32r_cgen_init_dis (cd
);
633 /* We try to have as much common code as possible.
634 But at this point some targets need to take over. */
635 /* ??? Some targets may need a hook elsewhere. Try to avoid this,
636 but if not possible try to move this hook elsewhere rather than
638 length
= CGEN_PRINT_INSN (cd
, pc
, info
);
644 (*info
->fprintf_func
) (info
->stream
, UNKNOWN_INSN_MSG
);
645 return cd
->default_insn_bitsize
/ 8;