opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright 2007
   3    Free Software Foundation, Inc.
   4
   5    This file is part of GAS, the GNU Assembler.
   6
   7    GAS is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2, or (at your option)
  10    any later version.
  11
  12    GAS is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "opcode/i386.h"
  23
  24 typedef struct template
  25 {
  26   /* instruction name sans width suffix ("mov" for movl insns) */
  27   char *name;
  28
  29   /* how many operands */
  30   unsigned int operands;
  31
  32   /* base_opcode is the fundamental opcode byte without optional
  33      prefix(es).  */
  34   unsigned int base_opcode;
  35 #define Opcode_D        0x2 /* Direction bit:
  36                                set if Reg --> Regmem;
  37                                unset if Regmem --> Reg. */
  38 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
  39 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
  40
  41   /* extension_opcode is the 3 bit extension for group <n> insns.
  42      This field is also used to store the 8-bit opcode suffix for the
  43      AMD 3DNow! instructions.
  44      If this template has no extension opcode (the usual case) use None */
  45   unsigned int extension_opcode;
  46 #define None 0xffff             /* If no extension_opcode is possible.  */
  47
  48   /* cpu feature flags */
  49   unsigned int cpu_flags;
  50 #define Cpu186            0x1   /* i186 or better required */
  51 #define Cpu286            0x2   /* i286 or better required */
  52 #define Cpu386            0x4   /* i386 or better required */
  53 #define Cpu486            0x8   /* i486 or better required */
  54 #define Cpu586           0x10   /* i585 or better required */
  55 #define Cpu686           0x20   /* i686 or better required */
  56 #define CpuP4            0x40   /* Pentium4 or better required */
  57 #define CpuK6            0x80   /* AMD K6 or better required*/
  58 #define CpuSledgehammer 0x100   /* Sledgehammer or better required */
  59 #define CpuMMX          0x200   /* MMX support required */
  60 #define CpuMMX2         0x400   /* extended MMX support (with SSE or 3DNow!Ext) required */
  61 #define CpuSSE          0x800   /* Streaming SIMD extensions required */
  62 #define CpuSSE2        0x1000   /* Streaming SIMD extensions 2 required */
  63 #define Cpu3dnow       0x2000   /* 3dnow! support required */
  64 #define Cpu3dnowA      0x4000   /* 3dnow!Extensions support required */
  65 #define CpuSSE3        0x8000   /* Streaming SIMD extensions 3 required */
  66 #define CpuPadLock    0x10000   /* VIA PadLock required */
  67 #define CpuSVME       0x20000   /* AMD Secure Virtual Machine Ext-s required */
  68 #define CpuVMX        0x40000   /* VMX Instructions required */
  69 #define CpuSSSE3      0x80000   /* Supplemental Streaming SIMD extensions 3 required */
  70 #define CpuSSE4a     0x100000   /* SSE4a New Instuctions required */
  71 #define CpuABM       0x200000   /* ABM New Instructions required */
  72 #define CpuSSE4_1    0x400000   /* SSE4.1 Instructions required */
  73 #define CpuSSE4_2    0x800000   /* SSE4.2 Instructions required */
  74
  75 /* SSE4.1/4.2 Instructions required */
  76 #define CpuSSE4      (CpuSSE4_1|CpuSSE4_2)
  77
  78   /* These flags are set by gas depending on the flag_code.  */
  79 #define Cpu64        0x4000000   /* 64bit support required  */
  80 #define CpuNo64      0x8000000   /* Not supported in the 64bit mode  */
  81
  82   /* The default value for unknown CPUs - enable all features to avoid problems.  */
  83 #define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
  84         |CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuVMX \
  85         |Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuSSE4_1 \
  86         |CpuSSE4_2|CpuABM|CpuSSE4a)
  87
  88   /* the bits in opcode_modifier are used to generate the final opcode from
  89      the base_opcode.  These bits also are used to detect alternate forms of
  90      the same instruction */
  91   unsigned int opcode_modifier;
  92
  93   /* opcode_modifier bits: */
  94 #define D                  0x1  /* has direction bit. */
  95 #define W                  0x2  /* set if operands can be words or dwords
  96                                    encoded the canonical way */
  97 #define Modrm              0x4  /* insn has a modrm byte. */
  98 #define ShortForm          0x8  /* register is in low 3 bits of opcode */
  99 #define Jump              0x10  /* special case for jump insns.  */
 100 #define JumpDword         0x20  /* call and jump */
 101 #define JumpByte          0x40  /* loop and jecxz */
 102 #define JumpInterSegment  0x80  /* special case for intersegment leaps/calls */
 103 #define FloatMF          0x100  /* FP insn memory format bit, sized by 0x4 */
 104 #define FloatR           0x200  /* src/dest swap for floats. */
 105 #define FloatD           0x400  /* has float insn direction bit. */
 106 #define Size16           0x800  /* needs size prefix if in 32-bit mode */
 107 #define Size32          0x1000  /* needs size prefix if in 16-bit mode */
 108 #define Size64          0x2000  /* needs size prefix if in 64-bit mode */
 109 #define IgnoreSize      0x4000  /* instruction ignores operand size prefix */
 110 #define DefaultSize     0x8000  /* default insn size depends on mode */
 111 #define No_bSuf        0x10000  /* b suffix on instruction illegal */
 112 #define No_wSuf        0x20000  /* w suffix on instruction illegal */
 113 #define No_lSuf        0x40000  /* l suffix on instruction illegal */
 114 #define No_sSuf        0x80000  /* s suffix on instruction illegal */
 115 #define No_qSuf       0x100000  /* q suffix on instruction illegal */
 116 #define No_xSuf       0x200000  /* x suffix on instruction illegal */
 117 #define FWait         0x400000  /* instruction needs FWAIT */
 118 #define IsString      0x800000  /* quick test for string instructions */
 119 #define regKludge    0x1000000  /* fake an extra reg operand for clr, imul
 120                                    and special register processing for
 121                                    some instructions.  */
 122 #define IsPrefix     0x2000000  /* opcode is a prefix */
 123 #define ImmExt       0x4000000  /* instruction has extension in 8 bit imm */
 124 #define NoRex64      0x8000000  /* instruction don't need Rex64 prefix.  */
 125 #define Rex64       0x10000000  /* instruction require Rex64 prefix.  */
 126 #define Ugh         0x20000000  /* deprecated fp insn, gets a warning */
 127
 128   /* operand_types[i] describes the type of operand i.  This is made
 129      by OR'ing together all of the possible type masks.  (e.g.
 130      'operand_types[i] = Reg|Imm' specifies that operand i can be
 131      either a register or an immediate operand.  */
 132   unsigned int operand_types[MAX_OPERANDS];
 133
 134   /* operand_types[i] bits */
 135   /* register */
 136 #define Reg8               0x1  /* 8 bit reg */
 137 #define Reg16              0x2  /* 16 bit reg */
 138 #define Reg32              0x4  /* 32 bit reg */
 139 #define Reg64              0x8  /* 64 bit reg */
 140   /* immediate */
 141 #define Imm8              0x10  /* 8 bit immediate */
 142 #define Imm8S             0x20  /* 8 bit immediate sign extended */
 143 #define Imm16             0x40  /* 16 bit immediate */
 144 #define Imm32             0x80  /* 32 bit immediate */
 145 #define Imm32S           0x100  /* 32 bit immediate sign extended */
 146 #define Imm64            0x200  /* 64 bit immediate */
 147 #define Imm1             0x400  /* 1 bit immediate */
 148   /* memory */
 149 #define BaseIndex        0x800
 150   /* Disp8,16,32 are used in different ways, depending on the
 151      instruction.  For jumps, they specify the size of the PC relative
 152      displacement, for baseindex type instructions, they specify the
 153      size of the offset relative to the base register, and for memory
 154      offset instructions such as `mov 1234,%al' they specify the size of
 155      the offset relative to the segment base.  */
 156 #define Disp8           0x1000  /* 8 bit displacement */
 157 #define Disp16          0x2000  /* 16 bit displacement */
 158 #define Disp32          0x4000  /* 32 bit displacement */
 159 #define Disp32S         0x8000  /* 32 bit signed displacement */
 160 #define Disp64         0x10000  /* 64 bit displacement */
 161   /* specials */
 162 #define InOutPortReg   0x20000  /* register to hold in/out port addr = dx */
 163 #define ShiftCount     0x40000  /* register to hold shift count = cl */
 164 #define Control        0x80000  /* Control register */
 165 #define Debug         0x100000  /* Debug register */
 166 #define Test          0x200000  /* Test register */
 167 #define FloatReg      0x400000  /* Float register */
 168 #define FloatAcc      0x800000  /* Float stack top %st(0) */
 169 #define SReg2        0x1000000  /* 2 bit segment register */
 170 #define SReg3        0x2000000  /* 3 bit segment register */
 171 #define Acc          0x4000000  /* Accumulator %al or %ax or %eax */
 172 #define JumpAbsolute 0x8000000
 173 #define RegMMX      0x10000000  /* MMX register */
 174 #define RegXMM      0x20000000  /* XMM registers in PIII */
 175 #define EsSeg       0x40000000  /* String insn operand with fixed es segment */
 176
 177   /* RegMem is for instructions with a modrm byte where the register
 178      destination operand should be encoded in the mod and regmem fields.
 179      Normally, it will be encoded in the reg field. We add a RegMem
 180      flag to the destination register operand to indicate that it should
 181      be encoded in the regmem field.  */
 182 #define RegMem      0x80000000
 183
 184 #define Reg     (Reg8|Reg16|Reg32|Reg64) /* gen'l register */
 185 #define WordReg (Reg16|Reg32|Reg64)
 186 #define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
 187 #define Imm     (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
 188 #define EncImm  (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
 189 #define Disp    (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
 190 #define AnyMem  (Disp8|Disp16|Disp32|Disp32S|BaseIndex) /* General memory */
 191   /* The following aliases are defined because the opcode table
 192      carefully specifies the allowed memory types for each instruction.
 193      At the moment we can only tell a memory reference size by the
 194      instruction suffix, so there's not much point in defining Mem8,
 195      Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
 196      the suffix directly to check memory operands.  */
 197 #define LLongMem AnyMem         /* 64 bits (or more) */
 198 #define LongMem AnyMem          /* 32 bit memory ref */
 199 #define ShortMem AnyMem         /* 16 bit memory ref */
 200 #define WordMem AnyMem          /* 16, 32 or 64 bit memory ref */
 201 #define ByteMem AnyMem          /* 8 bit memory ref */
 202 }
 203 template;
 204
 205 extern const template i386_optab[];
 206
 207 /* these are for register name --> number & type hash lookup */
 208 typedef struct
 209 {
 210   char *reg_name;
 211   unsigned int reg_type;
 212   unsigned int reg_flags;
 213 #define RegRex      0x1  /* Extended register.  */
 214 #define RegRex64    0x2  /* Extended 8 bit register.  */
 215   unsigned int reg_num;
 216 }
 217 reg_entry;
 218
 219 /* Entries in i386_regtab.  */
 220 #define REGNAM_AL 1
 221 #define REGNAM_AX 25
 222 #define REGNAM_EAX 41
 223
 224 extern const reg_entry i386_regtab[];
 225 extern const unsigned int i386_regtab_size;
 226
 227 typedef struct
 228 {
 229   char *seg_name;
 230   unsigned int seg_prefix;
 231 }
 232 seg_entry;
 233
 234 extern const seg_entry cs;
 235 extern const seg_entry ds;
 236 extern const seg_entry ss;
 237 extern const seg_entry es;
 238 extern const seg_entry fs;
 239 extern const seg_entry gs;