bfd/cpu-ia64-opc.c

   1 /* Copyright (C) 1998, 1999  Free Software Foundation, Inc.
   2    Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
   3
   4 This file is part of BFD, the Binary File Descriptor library.
   5
   6 This program is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 2 of the License, or
   9 (at your option) any later version.
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with this program; if not, write to the Free Software
  18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  19
  20
  21 /* Logically, this code should be part of libopcode but since some of
  22    the operand insertion/extraction functions help bfd to implement
  23    relocations, this code is included as part of elf64-ia64.c.  This
  24    avoids circular dependencies between libopcode and libbfd and also
  25    obviates the need for applications to link in libopcode when all
  26    they really want is libbfd.
  27
  28    --davidm Mon Apr 13 22:14:02 1998 */
  29
  30 #include "../opcodes/ia64-opc.h"
  31
  32 #define NELEMS(a)  ((int) (sizeof (a) / sizeof ((a)[0])))
  33
  34 static const char*
  35 ins_rsvd (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
  36 {
  37   return "internal error---this shouldn't happen";
  38 }
  39
  40 static const char*
  41 ext_rsvd (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
  42 {
  43   return "internal error---this shouldn't happen";
  44 }
  45
  46 static const char*
  47 ins_const (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
  48 {
  49   return 0;
  50 }
  51
  52 static const char*
  53 ext_const (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
  54 {
  55   return 0;
  56 }
  57
  58 static const char*
  59 ins_reg (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
  60 {
  61   if (value >= 1u << self->field[0].bits)
  62     return "register number out of range";
  63
  64   *code |= value << self->field[0].shift;
  65   return 0;
  66 }
  67
  68 static const char*
  69 ext_reg (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
  70 {
  71   *valuep = ((code >> self->field[0].shift)
  72              & ((1u << self->field[0].bits) - 1));
  73   return 0;
  74 }
  75
  76 static const char*
  77 ins_immu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
  78 {
  79   ia64_insn new = 0;
  80   int i;
  81
  82   for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
  83     {
  84       new |= ((value & ((((ia64_insn) 1) << self->field[i].bits) - 1))
  85               << self->field[i].shift);
  86       value >>= self->field[i].bits;
  87     }
  88   if (value)
  89     return "integer operand out of range";
  90
  91   *code |= new;
  92   return 0;
  93 }
  94
  95 static const char*
  96 ext_immu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
  97 {
  98   BFD_HOST_U_64_BIT value = 0;
  99   int i, bits = 0, total = 0;
 100
 101   for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
 102     {
 103       bits = self->field[i].bits;
 104       value |= ((code >> self->field[i].shift)
 105                 & ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
 106       total += bits;
 107     }
 108   *valuep = value;
 109   return 0;
 110 }
 111
 112 static const char*
 113 ins_immus8 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 114 {
 115   if (value & 0x7)
 116     return "value not an integer multiple of 8";
 117   return ins_immu (self, value >> 3, code);
 118 }
 119
 120 static const char*
 121 ext_immus8 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 122 {
 123   const char *result;
 124
 125   result = ext_immu (self, code, valuep);
 126   if (result)
 127     return result;
 128
 129   *valuep = *valuep << 3;
 130   return 0;
 131 }
 132
 133 static const char*
 134 ins_imms_scaled (const struct ia64_operand *self, ia64_insn value,
 135                  ia64_insn *code, int scale)
 136 {
 137   BFD_HOST_64_BIT svalue = value, sign_bit;
 138   ia64_insn new = 0;
 139   int i;
 140
 141   svalue >>= scale;
 142
 143   for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
 144     {
 145       new |= ((svalue & ((((ia64_insn) 1) << self->field[i].bits) - 1))
 146               << self->field[i].shift);
 147       sign_bit = (svalue >> (self->field[i].bits - 1)) & 1;
 148       svalue >>= self->field[i].bits;
 149     }
 150   if ((!sign_bit && svalue != 0) || (sign_bit && svalue != -1))
 151     return "integer operand out of range";
 152
 153   *code |= new;
 154   return 0;
 155 }
 156
 157 static const char*
 158 ext_imms_scaled (const struct ia64_operand *self, ia64_insn code,
 159                  ia64_insn *valuep, int scale)
 160 {
 161   int i, bits = 0, total = 0, shift;
 162   BFD_HOST_64_BIT val = 0;
 163
 164   for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
 165     {
 166       bits = self->field[i].bits;
 167       val |= ((code >> self->field[i].shift)
 168               & ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
 169       total += bits;
 170     }
 171   /* sign extend: */
 172   shift = 8*sizeof (val) - total;
 173   val = (val << shift) >> shift;
 174
 175   *valuep = (val << scale);
 176   return 0;
 177 }
 178
 179 static const char*
 180 ins_imms (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 181 {
 182   return ins_imms_scaled (self, value, code, 0);
 183 }
 184
 185 static const char*
 186 ins_immsu4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 187 {
 188   if (value == (BFD_HOST_U_64_BIT) 0x100000000)
 189     value = 0;
 190   else
 191     value = (((BFD_HOST_64_BIT)value << 32) >> 32);
 192
 193   return ins_imms_scaled (self, value, code, 0);
 194 }
 195
 196 static const char*
 197 ext_imms (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 198 {
 199   return ext_imms_scaled (self, code, valuep, 0);
 200 }
 201
 202 static const char*
 203 ins_immsm1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 204 {
 205   --value;
 206   return ins_imms_scaled (self, value, code, 0);
 207 }
 208
 209 static const char*
 210 ins_immsm1u4 (const struct ia64_operand *self, ia64_insn value,
 211               ia64_insn *code)
 212 {
 213   if (value == (BFD_HOST_U_64_BIT) 0x100000000)
 214     value = 0;
 215   else
 216     value = (((BFD_HOST_64_BIT)value << 32) >> 32);
 217
 218   --value;
 219   return ins_imms_scaled (self, value, code, 0);
 220 }
 221
 222 static const char*
 223 ext_immsm1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 224 {
 225   const char *res = ext_imms_scaled (self, code, valuep, 0);
 226
 227   ++*valuep;
 228   return res;
 229 }
 230
 231 static const char*
 232 ins_imms1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 233 {
 234   return ins_imms_scaled (self, value, code, 1);
 235 }
 236
 237 static const char*
 238 ext_imms1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 239 {
 240   return ext_imms_scaled (self, code, valuep, 1);
 241 }
 242
 243 static const char*
 244 ins_imms4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 245 {
 246   return ins_imms_scaled (self, value, code, 4);
 247 }
 248
 249 static const char*
 250 ext_imms4 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 251 {
 252   return ext_imms_scaled (self, code, valuep, 4);
 253 }
 254
 255 static const char*
 256 ins_imms16 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 257 {
 258   return ins_imms_scaled (self, value, code, 16);
 259 }
 260
 261 static const char*
 262 ext_imms16 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 263 {
 264   return ext_imms_scaled (self, code, valuep, 16);
 265 }
 266
 267 static const char*
 268 ins_cimmu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 269 {
 270   ia64_insn mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
 271   return ins_immu (self, value ^ mask, code);
 272 }
 273
 274 static const char*
 275 ext_cimmu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 276 {
 277   const char *result;
 278   ia64_insn mask;
 279
 280   mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
 281   result = ext_immu (self, code, valuep);
 282   if (!result)
 283     {
 284       mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
 285       *valuep ^= mask;
 286     }
 287   return result;
 288 }
 289
 290 static const char*
 291 ins_cnt (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 292 {
 293   --value;
 294   if (value >= ((BFD_HOST_U_64_BIT) 1) << self->field[0].bits)
 295     return "count out of range";
 296
 297   *code |= value << self->field[0].shift;
 298   return 0;
 299 }
 300
 301 static const char*
 302 ext_cnt (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 303 {
 304   *valuep = ((code >> self->field[0].shift)
 305              & ((((BFD_HOST_U_64_BIT) 1) << self->field[0].bits) - 1)) + 1;
 306   return 0;
 307 }
 308
 309 static const char*
 310 ins_cnt2b (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 311 {
 312   --value;
 313
 314   if (value > 2)
 315     return "count must be in range 1..3";
 316
 317   *code |= value << self->field[0].shift;
 318   return 0;
 319 }
 320
 321 static const char*
 322 ext_cnt2b (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 323 {
 324   *valuep = ((code >> self->field[0].shift) & 0x3) + 1;
 325   return 0;
 326 }
 327
 328 static const char*
 329 ins_cnt2c (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 330 {
 331   switch (value)
 332     {
 333     case 0:     value = 0; break;
 334     case 7:     value = 1; break;
 335     case 15:    value = 2; break;
 336     case 16:    value = 3; break;
 337     default:    return "count must be 0, 7, 15, or 16";
 338     }
 339   *code |= value << self->field[0].shift;
 340   return 0;
 341 }
 342
 343 static const char*
 344 ext_cnt2c (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 345 {
 346   ia64_insn value;
 347
 348   value = (code >> self->field[0].shift) & 0x3;
 349   switch (value)
 350     {
 351     case 0: value =  0; break;
 352     case 1: value =  7; break;
 353     case 2: value = 15; break;
 354     case 3: value = 16; break;
 355     }
 356   *valuep = value;
 357   return 0;
 358 }
 359
 360 static const char*
 361 ins_inc3 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 362 {
 363   BFD_HOST_64_BIT val = value;
 364   BFD_HOST_U_64_BIT sign = 0;
 365
 366   if (val < 0)
 367     {
 368       sign = 0x4;
 369       value = -value;
 370     }
 371   switch (value)
 372     {
 373     case  1:    value = 3; break;
 374     case  4:    value = 2; break;
 375     case  8:    value = 1; break;
 376     case 16:    value = 0; break;
 377     default:    return "count must be +/- 1, 4, 8, or 16";
 378     }
 379   *code |= (sign | value) << self->field[0].shift;
 380   return 0;
 381 }
 382
 383 static const char*
 384 ext_inc3 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 385 {
 386   BFD_HOST_64_BIT val;
 387   int negate;
 388
 389   val = (code >> self->field[0].shift) & 0x7;
 390   negate = val & 0x4;
 391   switch (val & 0x3)
 392     {
 393     case 0: val = 16; break;
 394     case 1: val =  8; break;
 395     case 2: val =  4; break;
 396     case 3: val =  1; break;
 397     }
 398   if (negate)
 399     val = -val;
 400
 401   *valuep = val;
 402   return 0;
 403 }
 404
 405 #define CST     IA64_OPND_CLASS_CST
 406 #define REG     IA64_OPND_CLASS_REG
 407 #define IND     IA64_OPND_CLASS_IND
 408 #define ABS     IA64_OPND_CLASS_ABS
 409 #define REL     IA64_OPND_CLASS_REL
 410
 411 #define SDEC    IA64_OPND_FLAG_DECIMAL_SIGNED
 412 #define UDEC    IA64_OPND_FLAG_DECIMAL_UNSIGNED
 413
 414 const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
 415   {
 416     /* constants: */
 417     { CST, ins_const, ext_const, "NIL",         {{ 0, }}, 0, "<none>" },
 418     { CST, ins_const, ext_const, "ar.ccv",      {{ 0, }}, 0, "ar.ccv" },
 419     { CST, ins_const, ext_const, "ar.pfs",      {{ 0, }}, 0, "ar.pfs" },
 420     { CST, ins_const, ext_const, "1",           {{ 0, }}, 0, "1" },
 421     { CST, ins_const, ext_const, "8",           {{ 0, }}, 0, "1" },
 422     { CST, ins_const, ext_const, "16",          {{ 0, }}, 0, "16" },
 423     { CST, ins_const, ext_const, "r0",          {{ 0, }}, 0, "r0" },
 424     { CST, ins_const, ext_const, "ip",          {{ 0, }}, 0, "ip" },
 425     { CST, ins_const, ext_const, "pr",          {{ 0, }}, 0, "pr" },
 426     { CST, ins_const, ext_const, "pr.rot",      {{ 0, }}, 0, "pr.rot" },
 427     { CST, ins_const, ext_const, "psr",         {{ 0, }}, 0, "psr" },
 428     { CST, ins_const, ext_const, "psr.l",       {{ 0, }}, 0, "psr.l" },
 429     { CST, ins_const, ext_const, "psr.um",      {{ 0, }}, 0, "psr.um" },
 430
 431     /* register operands: */
 432     { REG, ins_reg,   ext_reg,  "ar", {{ 7, 20}}, 0,            /* AR3 */
 433       "an application register" },
 434     { REG, ins_reg,   ext_reg,   "b", {{ 3,  6}}, 0,            /* B1 */
 435       "a branch register" },
 436     { REG, ins_reg,   ext_reg,   "b", {{ 3, 13}}, 0,            /* B2 */
 437       "a branch register"},
 438     { REG, ins_reg,   ext_reg,  "cr", {{ 7, 20}}, 0,            /* CR */
 439       "a control register"},
 440     { REG, ins_reg,   ext_reg,   "f", {{ 7,  6}}, 0,            /* F1 */
 441       "a floating-point register" },
 442     { REG, ins_reg,   ext_reg,   "f", {{ 7, 13}}, 0,            /* F2 */
 443       "a floating-point register" },
 444     { REG, ins_reg,   ext_reg,   "f", {{ 7, 20}}, 0,            /* F3 */
 445       "a floating-point register" },
 446     { REG, ins_reg,   ext_reg,   "f", {{ 7, 27}}, 0,            /* F4 */
 447       "a floating-point register" },
 448     { REG, ins_reg,   ext_reg,   "p", {{ 6,  6}}, 0,            /* P1 */
 449       "a predicate register" },
 450     { REG, ins_reg,   ext_reg,   "p", {{ 6, 27}}, 0,            /* P2 */
 451       "a predicate register" },
 452     { REG, ins_reg,   ext_reg,   "r", {{ 7,  6}}, 0,            /* R1 */
 453       "a general register" },
 454     { REG, ins_reg,   ext_reg,   "r", {{ 7, 13}}, 0,            /* R2 */
 455       "a general register" },
 456     { REG, ins_reg,   ext_reg,   "r", {{ 7, 20}}, 0,            /* R3 */
 457       "a general register" },
 458     { REG, ins_reg,   ext_reg,   "r", {{ 2, 20}}, 0,            /* R3_2 */
 459       "a general register r0-r3" },
 460
 461     /* indirect operands: */
 462     { IND, ins_reg,   ext_reg,  "cpuid", {{7, 20}}, 0,          /* CPUID_R3 */
 463       "a cpuid register" },
 464     { IND, ins_reg,   ext_reg,  "dbr",   {{7, 20}}, 0,          /* DBR_R3 */
 465       "a dbr register" },
 466     { IND, ins_reg,   ext_reg,  "dtr",   {{7, 20}}, 0,          /* DTR_R3 */
 467       "a dtr register" },
 468     { IND, ins_reg,   ext_reg,  "itr",   {{7, 20}}, 0,          /* ITR_R3 */
 469       "an itr register" },
 470     { IND, ins_reg,   ext_reg,  "ibr",   {{7, 20}}, 0,          /* IBR_R3 */
 471       "an ibr register" },
 472     { IND, ins_reg,   ext_reg,  "",      {{7, 20}}, 0,          /* MR3 */
 473       "an indirect memory address" },
 474     { IND, ins_reg,   ext_reg,  "msr",   {{7, 20}}, 0,          /* MSR_R3 */
 475       "an msr register" },
 476     { IND, ins_reg,   ext_reg,  "pkr",   {{7, 20}}, 0,          /* PKR_R3 */
 477       "a pkr register" },
 478     { IND, ins_reg,   ext_reg,  "pmc",   {{7, 20}}, 0,          /* PMC_R3 */
 479       "a pmc register" },
 480     { IND, ins_reg,   ext_reg,  "pmd",   {{7, 20}}, 0,          /* PMD_R3 */
 481       "a pmd register" },
 482     { IND, ins_reg,   ext_reg,  "rr",    {{7, 20}}, 0,          /* RR_R3 */
 483       "an rr register" },
 484
 485     /* immediate operands: */
 486     { ABS, ins_cimmu, ext_cimmu, 0, {{ 5, 20 }}, UDEC,          /* CCNT5 */
 487       "a 5-bit count (0-31)" },
 488     { ABS, ins_cnt,   ext_cnt,   0, {{ 2, 27 }}, UDEC,          /* CNT2a */
 489       "a 2-bit count (1-4)" },
 490     { ABS, ins_cnt2b, ext_cnt2b, 0, {{ 2, 27 }}, UDEC,          /* CNT2b */
 491       "a 2-bit count (1-3)" },
 492     { ABS, ins_cnt2c, ext_cnt2c, 0, {{ 2, 30 }}, UDEC,          /* CNT2c */
 493       "a count (0, 7, 15, or 16)" },
 494     { ABS, ins_immu,  ext_immu,  0, {{ 5, 14}}, UDEC,           /* CNT5 */
 495       "a 5-bit count (0-31)" },
 496     { ABS, ins_immu,  ext_immu,  0, {{ 6, 27}}, UDEC,           /* CNT6 */
 497       "a 6-bit count (0-63)" },
 498     { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 20}}, UDEC,           /* CPOS6a */
 499       "a 6-bit bit pos (0-63)" },
 500     { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 14}}, UDEC,           /* CPOS6b */
 501       "a 6-bit bit pos (0-63)" },
 502     { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 31}}, UDEC,           /* CPOS6c */
 503       "a 6-bit bit pos (0-63)" },
 504     { ABS, ins_imms,  ext_imms,  0, {{ 1, 36}}, SDEC,           /* IMM1 */
 505       "a 1-bit integer (-1, 0)" },
 506     { ABS, ins_immu,  ext_immu,  0, {{ 2, 13}}, UDEC,           /* IMMU2 */
 507       "a 2-bit unsigned (0-3)" },
 508     { ABS, ins_immu,  ext_immu,  0, {{ 7, 13}}, 0,              /* IMMU7a */
 509       "a 7-bit unsigned (0-127)" },
 510     { ABS, ins_immu,  ext_immu,  0, {{ 7, 20}}, 0,              /* IMMU7b */
 511       "a 7-bit unsigned (0-127)" },
 512     { ABS, ins_immu,  ext_immu,  0, {{ 7, 13}}, UDEC,           /* SOF */
 513       "a frame size (register count)" },
 514     { ABS, ins_immu,  ext_immu,  0, {{ 7, 20}}, UDEC,           /* SOL */
 515       "a local register count" },
 516     { ABS, ins_immus8,ext_immus8,0, {{ 4, 27}}, UDEC,           /* SOR */
 517       "a rotating register count (integer multiple of 8)" },
 518     { ABS, ins_imms,  ext_imms,  0,                             /* IMM8 */
 519       {{ 7, 13}, { 1, 36}}, SDEC,
 520       "an 8-bit integer (-128-127)" },
 521     { ABS, ins_immsu4,  ext_imms,  0,                           /* IMM8U4 */
 522       {{ 7, 13}, { 1, 36}}, SDEC,
 523       "an 8-bit signed integer for 32-bit unsigned compare (-128-127)" },
 524     { ABS, ins_immsm1,  ext_immsm1,  0,                         /* IMM8M1 */
 525       {{ 7, 13}, { 1, 36}}, SDEC,
 526       "an 8-bit integer (-127-128)" },
 527     { ABS, ins_immsm1u4,  ext_immsm1,  0,                       /* IMM8M1U4 */
 528       {{ 7, 13}, { 1, 36}}, SDEC,
 529       "an 8-bit integer for 32-bit unsigned compare (-127-(-1),1-128,0x100000000)" },
 530     { ABS, ins_immsm1,  ext_immsm1,  0,                         /* IMM8M1U8 */
 531       {{ 7, 13}, { 1, 36}}, SDEC,
 532       "an 8-bit integer for 64-bit unsigned compare (-127-(-1),1-128,0x10000000000000000)" },
 533     { ABS, ins_immu,  ext_immu,  0, {{ 2, 33}, { 7, 20}}, 0,    /* IMMU9 */
 534       "a 9-bit unsigned (0-511)" },
 535     { ABS, ins_imms,  ext_imms,  0,                             /* IMM9a */
 536       {{ 7,  6}, { 1, 27}, { 1, 36}}, SDEC,
 537       "a 9-bit integer (-256-255)" },
 538     { ABS, ins_imms,  ext_imms, 0,                              /* IMM9b */
 539       {{ 7, 13}, { 1, 27}, { 1, 36}}, SDEC,
 540       "a 9-bit integer (-256-255)" },
 541     { ABS, ins_imms,  ext_imms, 0,                              /* IMM14 */
 542       {{ 7, 13}, { 6, 27}, { 1, 36}}, SDEC,
 543       "a 14-bit integer (-8192-8191)" },
 544     { ABS, ins_imms1, ext_imms1, 0,                             /* IMM17 */
 545       {{ 7,  6}, { 8, 24}, { 1, 36}}, 0,
 546       "a 17-bit integer (-65536-65535)" },
 547     { ABS, ins_immu,  ext_immu,  0, {{20,  6}, { 1, 36}}, 0,    /* IMMU21 */
 548       "a 21-bit unsigned" },
 549     { ABS, ins_imms,  ext_imms,  0,                             /* IMM22 */
 550       {{ 7, 13}, { 9, 27}, { 5, 22}, { 1, 36}}, SDEC,
 551       "a 22-bit integer" },
 552     { ABS, ins_immu,  ext_immu,  0,                             /* IMMU24 */
 553       {{21,  6}, { 2, 31}, { 1, 36}}, 0,
 554       "a 24-bit unsigned" },
 555     { ABS, ins_imms16,ext_imms16,0, {{27,  6}, { 1, 36}}, 0,    /* IMM44 */
 556       "a 44-bit unsigned (least 16 bits ignored/zeroes)" },
 557     { ABS, ins_rsvd,  ext_rsvd, 0, {{0,  0}}, 0,                /* IMMU62 */
 558       "a 62-bit unsigned" },
 559     { ABS, ins_rsvd,  ext_rsvd, 0, {{0,  0}}, 0,                /* IMMU64 */
 560       "a 64-bit unsigned" },
 561     { ABS, ins_inc3,  ext_inc3,  0, {{ 3, 13}}, SDEC,           /* INC3 */
 562       "an increment (+/- 1, 4, 8, or 16)" },
 563     { ABS, ins_cnt,   ext_cnt,   0, {{ 4, 27}}, UDEC,           /* LEN4 */
 564       "a 4-bit length (1-16)" },
 565     { ABS, ins_cnt,   ext_cnt,   0, {{ 6, 27}}, UDEC,           /* LEN6 */
 566       "a 6-bit length (1-64)" },
 567     { ABS, ins_immu,  ext_immu,  0, {{ 4, 20}}, 0,              /* MBTYPE4 */
 568       "a mix type (@rev, @mix, @shuf, @alt, or @brcst)" },
 569     { ABS, ins_immu,  ext_immu,  0, {{ 8, 20}}, 0,              /* MBTYPE8 */
 570       "an 8-bit mix type" },
 571     { ABS, ins_immu,  ext_immu,  0, {{ 6, 14}}, UDEC,           /* POS6 */
 572       "a 6-bit bit pos (0-63)" },
 573     { REL, ins_imms4, ext_imms4, 0, {{ 7,  6}, { 2, 33}}, 0,    /* TAG13 */
 574       "a branch tag" },
 575     { REL, ins_imms4, ext_imms4, 0, {{ 9, 24}}, 0,              /* TAG13b */
 576       "a branch tag" },
 577     { REL, ins_imms4, ext_imms4, 0, {{20,  6}, { 1, 36}}, 0,    /* TGT25 */
 578       "a branch target" },
 579     { REL, ins_imms4, ext_imms4, 0,                             /* TGT25b */
 580       {{ 7,  6}, {13, 20}, { 1, 36}}, 0,
 581       "a branch target" },
 582     { REL, ins_imms4, ext_imms4, 0, {{20, 13}, { 1, 36}}, 0,    /* TGT25c */
 583       "a branch target" },
 584     { REL, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0,                  /* TGT64  */
 585       "a branch target" },
 586   };