opcodes/fr30-desc.c

   1 /* CPU data for fr30.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #include "sysdep.h"
  26 #include <ctype.h>
  27 #include <stdio.h>
  28 #include <stdarg.h>
  29 #include "ansidecl.h"
  30 #include "bfd.h"
  31 #include "symcat.h"
  32 #include "fr30-desc.h"
  33 #include "fr30-opc.h"
  34 #include "opintl.h"
  35 #include "libiberty.h"
  36
  37 /* Attributes.  */
  38
  39 static const CGEN_ATTR_ENTRY bool_attr[] =
  40 {
  41   { "#f", 0 },
  42   { "#t", 1 },
  43   { 0, 0 }
  44 };
  45
  46 static const CGEN_ATTR_ENTRY MACH_attr[] =
  47 {
  48   { "base", MACH_BASE },
  49   { "fr30", MACH_FR30 },
  50   { "max", MACH_MAX },
  51   { 0, 0 }
  52 };
  53
  54 static const CGEN_ATTR_ENTRY ISA_attr[] =
  55 {
  56   { "fr30", ISA_FR30 },
  57   { "max", ISA_MAX },
  58   { 0, 0 }
  59 };
  60
  61 const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[] =
  62 {
  63   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  64   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  65   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  66   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  67   { "RESERVED", &bool_attr[0], &bool_attr[0] },
  68   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  69   { "SIGNED", &bool_attr[0], &bool_attr[0] },
  70   { 0, 0, 0 }
  71 };
  72
  73 const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
  74 {
  75   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  76   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  77   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
  78   { "PC", &bool_attr[0], &bool_attr[0] },
  79   { "PROFILE", &bool_attr[0], &bool_attr[0] },
  80   { 0, 0, 0 }
  81 };
  82
  83 const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
  84 {
  85   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  86   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  87   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  88   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  89   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  90   { "SIGNED", &bool_attr[0], &bool_attr[0] },
  91   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
  92   { "RELAX", &bool_attr[0], &bool_attr[0] },
  93   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
  94   { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
  95   { 0, 0, 0 }
  96 };
  97
  98 const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
  99 {
 100   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 101   { "ALIAS", &bool_attr[0], &bool_attr[0] },
 102   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 103   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
 104   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
 105   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
 106   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 107   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
 108   { "RELAX", &bool_attr[0], &bool_attr[0] },
 109   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
 110   { "PBB", &bool_attr[0], &bool_attr[0] },
 111   { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 112   { 0, 0, 0 }
 113 };
 114
 115 /* Instruction set variants.  */
 116
 117 static const CGEN_ISA fr30_cgen_isa_table[] = {
 118   { "fr30", 16, 16, 16, 48 },
 119   { 0, 0, 0, 0, 0 }
 120 };
 121
 122 /* Machine variants.  */
 123
 124 static const CGEN_MACH fr30_cgen_mach_table[] = {
 125   { "fr30", "fr30", MACH_FR30 },
 126   { 0, 0, 0 }
 127 };
 128
 129 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_gr_names_entries[] =
 130 {
 131   { "r0", 0, {0, {0}}, 0, 0 },
 132   { "r1", 1, {0, {0}}, 0, 0 },
 133   { "r2", 2, {0, {0}}, 0, 0 },
 134   { "r3", 3, {0, {0}}, 0, 0 },
 135   { "r4", 4, {0, {0}}, 0, 0 },
 136   { "r5", 5, {0, {0}}, 0, 0 },
 137   { "r6", 6, {0, {0}}, 0, 0 },
 138   { "r7", 7, {0, {0}}, 0, 0 },
 139   { "r8", 8, {0, {0}}, 0, 0 },
 140   { "r9", 9, {0, {0}}, 0, 0 },
 141   { "r10", 10, {0, {0}}, 0, 0 },
 142   { "r11", 11, {0, {0}}, 0, 0 },
 143   { "r12", 12, {0, {0}}, 0, 0 },
 144   { "r13", 13, {0, {0}}, 0, 0 },
 145   { "r14", 14, {0, {0}}, 0, 0 },
 146   { "r15", 15, {0, {0}}, 0, 0 },
 147   { "ac", 13, {0, {0}}, 0, 0 },
 148   { "fp", 14, {0, {0}}, 0, 0 },
 149   { "sp", 15, {0, {0}}, 0, 0 }
 150 };
 151
 152 CGEN_KEYWORD fr30_cgen_opval_gr_names =
 153 {
 154   & fr30_cgen_opval_gr_names_entries[0],
 155   19,
 156   0, 0, 0, 0
 157 };
 158
 159 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_cr_names_entries[] =
 160 {
 161   { "cr0", 0, {0, {0}}, 0, 0 },
 162   { "cr1", 1, {0, {0}}, 0, 0 },
 163   { "cr2", 2, {0, {0}}, 0, 0 },
 164   { "cr3", 3, {0, {0}}, 0, 0 },
 165   { "cr4", 4, {0, {0}}, 0, 0 },
 166   { "cr5", 5, {0, {0}}, 0, 0 },
 167   { "cr6", 6, {0, {0}}, 0, 0 },
 168   { "cr7", 7, {0, {0}}, 0, 0 },
 169   { "cr8", 8, {0, {0}}, 0, 0 },
 170   { "cr9", 9, {0, {0}}, 0, 0 },
 171   { "cr10", 10, {0, {0}}, 0, 0 },
 172   { "cr11", 11, {0, {0}}, 0, 0 },
 173   { "cr12", 12, {0, {0}}, 0, 0 },
 174   { "cr13", 13, {0, {0}}, 0, 0 },
 175   { "cr14", 14, {0, {0}}, 0, 0 },
 176   { "cr15", 15, {0, {0}}, 0, 0 }
 177 };
 178
 179 CGEN_KEYWORD fr30_cgen_opval_cr_names =
 180 {
 181   & fr30_cgen_opval_cr_names_entries[0],
 182   16,
 183   0, 0, 0, 0
 184 };
 185
 186 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_dr_names_entries[] =
 187 {
 188   { "tbr", 0, {0, {0}}, 0, 0 },
 189   { "rp", 1, {0, {0}}, 0, 0 },
 190   { "ssp", 2, {0, {0}}, 0, 0 },
 191   { "usp", 3, {0, {0}}, 0, 0 },
 192   { "mdh", 4, {0, {0}}, 0, 0 },
 193   { "mdl", 5, {0, {0}}, 0, 0 }
 194 };
 195
 196 CGEN_KEYWORD fr30_cgen_opval_dr_names =
 197 {
 198   & fr30_cgen_opval_dr_names_entries[0],
 199   6,
 200   0, 0, 0, 0
 201 };
 202
 203 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
 204 {
 205   { "ps", 0, {0, {0}}, 0, 0 }
 206 };
 207
 208 CGEN_KEYWORD fr30_cgen_opval_h_ps =
 209 {
 210   & fr30_cgen_opval_h_ps_entries[0],
 211   1,
 212   0, 0, 0, 0
 213 };
 214
 215 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
 216 {
 217   { "r13", 0, {0, {0}}, 0, 0 }
 218 };
 219
 220 CGEN_KEYWORD fr30_cgen_opval_h_r13 =
 221 {
 222   & fr30_cgen_opval_h_r13_entries[0],
 223   1,
 224   0, 0, 0, 0
 225 };
 226
 227 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
 228 {
 229   { "r14", 0, {0, {0}}, 0, 0 }
 230 };
 231
 232 CGEN_KEYWORD fr30_cgen_opval_h_r14 =
 233 {
 234   & fr30_cgen_opval_h_r14_entries[0],
 235   1,
 236   0, 0, 0, 0
 237 };
 238
 239 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
 240 {
 241   { "r15", 0, {0, {0}}, 0, 0 }
 242 };
 243
 244 CGEN_KEYWORD fr30_cgen_opval_h_r15 =
 245 {
 246   & fr30_cgen_opval_h_r15_entries[0],
 247   1,
 248   0, 0, 0, 0
 249 };
 250
 251
 252
 253 /* The hardware table.  */
 254
 255 #define A(a) (1 << CONCAT2 (CGEN_HW_,a))
 256
 257 const CGEN_HW_ENTRY fr30_cgen_hw_table[] =
 258 {
 259   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 260   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 261   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 262   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 263   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 264   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
 265   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
 266   { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
 267   { "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_dr_names, { 0, { (1<<MACH_BASE) } } },
 268   { "h-ps", HW_H_PS, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, { (1<<MACH_BASE) } } },
 269   { "h-r13", HW_H_R13, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, { (1<<MACH_BASE) } } },
 270   { "h-r14", HW_H_R14, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, { (1<<MACH_BASE) } } },
 271   { "h-r15", HW_H_R15, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, { (1<<MACH_BASE) } } },
 272   { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 273   { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 274   { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 275   { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 276   { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 277   { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 278   { "h-tbit", HW_H_TBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 279   { "h-d0bit", HW_H_D0BIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 280   { "h-d1bit", HW_H_D1BIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 281   { "h-ccr", HW_H_CCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 282   { "h-scr", HW_H_SCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 283   { "h-ilm", HW_H_ILM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 284   { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
 285 };
 286
 287 #undef A
 288
 289 /* The instruction field table.  */
 290
 291 #define A(a) (1 << CONCAT2 (CGEN_IFLD_,a))
 292
 293 const CGEN_IFLD fr30_cgen_ifld_table[] =
 294 {
 295   { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
 296   { FR30_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
 297   { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { 0, { (1<<MACH_BASE) } }  },
 298   { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { 0, { (1<<MACH_BASE) } }  },
 299   { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 300   { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
 301   { FR30_F_OP5, "f-op5", 0, 16, 4, 1, { 0, { (1<<MACH_BASE) } }  },
 302   { FR30_F_CC, "f-cc", 0, 16, 4, 4, { 0, { (1<<MACH_BASE) } }  },
 303   { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { 0, { (1<<MACH_BASE) } }  },
 304   { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 305   { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
 306   { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 307   { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
 308   { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 309   { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
 310   { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 311   { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
 312   { FR30_F_U4, "f-u4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 313   { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
 314   { FR30_F_I4, "f-i4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 315   { FR30_F_M4, "f-m4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 316   { FR30_F_U8, "f-u8", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 317   { FR30_F_I8, "f-i8", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } }  },
 318   { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 319   { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { 0, { (1<<MACH_BASE) } }  },
 320   { FR30_F_I32, "f-i32", 16, 32, 0, 32, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
 321   { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 322   { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } }  },
 323   { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } }  },
 324   { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } }  },
 325   { FR30_F_S10, "f-s10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 326   { FR30_F_U10, "f-u10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 327   { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 328   { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 329   { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 330   { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 331   { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 332   { FR30_F_REGLIST_HI_ST, "f-reglist_hi_st", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 333   { FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 334   { FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 335   { FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 336   { 0, 0, 0, 0, 0, 0, {0, {0}} }
 337 };
 338
 339 #undef A
 340
 341 /* The operand table.  */
 342
 343 #define A(a) (1 << CONCAT2 (CGEN_OPERAND_,a))
 344 #define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
 345
 346 const CGEN_OPERAND fr30_cgen_operand_table[] =
 347 {
 348 /* pc: program counter */
 349   { "pc", FR30_OPERAND_PC, HW_H_PC, 0, 0,
 350     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 351 /* Ri: destination register */
 352   { "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4,
 353     { 0, { (1<<MACH_BASE) } }  },
 354 /* Rj: source register */
 355   { "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4,
 356     { 0, { (1<<MACH_BASE) } }  },
 357 /* Ric: target register coproc insn */
 358   { "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4,
 359     { 0, { (1<<MACH_BASE) } }  },
 360 /* Rjc: source register coproc insn */
 361   { "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4,
 362     { 0, { (1<<MACH_BASE) } }  },
 363 /* CRi: coprocessor register */
 364   { "CRi", FR30_OPERAND_CRI, HW_H_CR, 12, 4,
 365     { 0, { (1<<MACH_BASE) } }  },
 366 /* CRj: coprocessor register */
 367   { "CRj", FR30_OPERAND_CRJ, HW_H_CR, 8, 4,
 368     { 0, { (1<<MACH_BASE) } }  },
 369 /* Rs1: dedicated register */
 370   { "Rs1", FR30_OPERAND_RS1, HW_H_DR, 8, 4,
 371     { 0, { (1<<MACH_BASE) } }  },
 372 /* Rs2: dedicated register */
 373   { "Rs2", FR30_OPERAND_RS2, HW_H_DR, 12, 4,
 374     { 0, { (1<<MACH_BASE) } }  },
 375 /* R13: General Register 13 */
 376   { "R13", FR30_OPERAND_R13, HW_H_R13, 0, 0,
 377     { 0, { (1<<MACH_BASE) } }  },
 378 /* R14: General Register 14 */
 379   { "R14", FR30_OPERAND_R14, HW_H_R14, 0, 0,
 380     { 0, { (1<<MACH_BASE) } }  },
 381 /* R15: General Register 15 */
 382   { "R15", FR30_OPERAND_R15, HW_H_R15, 0, 0,
 383     { 0, { (1<<MACH_BASE) } }  },
 384 /* ps: Program Status register */
 385   { "ps", FR30_OPERAND_PS, HW_H_PS, 0, 0,
 386     { 0, { (1<<MACH_BASE) } }  },
 387 /* u4: 4  bit unsigned immediate */
 388   { "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4,
 389     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 390 /* u4c: 4  bit unsigned immediate */
 391   { "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4,
 392     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 393 /* u8: 8  bit unsigned immediate */
 394   { "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8,
 395     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 396 /* i8: 8  bit unsigned immediate */
 397   { "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8,
 398     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 399 /* udisp6: 6  bit unsigned immediate */
 400   { "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4,
 401     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 402 /* disp8: 8  bit signed   immediate */
 403   { "disp8", FR30_OPERAND_DISP8, HW_H_SINT, 4, 8,
 404     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 405 /* disp9: 9  bit signed   immediate */
 406   { "disp9", FR30_OPERAND_DISP9, HW_H_SINT, 4, 8,
 407     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 408 /* disp10: 10 bit signed   immediate */
 409   { "disp10", FR30_OPERAND_DISP10, HW_H_SINT, 4, 8,
 410     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 411 /* s10: 10 bit signed   immediate */
 412   { "s10", FR30_OPERAND_S10, HW_H_SINT, 8, 8,
 413     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 414 /* u10: 10 bit unsigned immediate */
 415   { "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8,
 416     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 417 /* i32: 32 bit immediate */
 418   { "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32,
 419     { 0|A(HASH_PREFIX)|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
 420 /* m4: 4  bit negative immediate */
 421   { "m4", FR30_OPERAND_M4, HW_H_SINT, 8, 4,
 422     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 423 /* i20: 20 bit immediate */
 424   { "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20,
 425     { 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
 426 /* dir8: 8  bit direct address */
 427   { "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8,
 428     { 0, { (1<<MACH_BASE) } }  },
 429 /* dir9: 9  bit direct address */
 430   { "dir9", FR30_OPERAND_DIR9, HW_H_UINT, 8, 8,
 431     { 0, { (1<<MACH_BASE) } }  },
 432 /* dir10: 10 bit direct address */
 433   { "dir10", FR30_OPERAND_DIR10, HW_H_UINT, 8, 8,
 434     { 0, { (1<<MACH_BASE) } }  },
 435 /* label9: 9  bit pc relative address */
 436   { "label9", FR30_OPERAND_LABEL9, HW_H_IADDR, 8, 8,
 437     { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 438 /* label12: 12 bit pc relative address */
 439   { "label12", FR30_OPERAND_LABEL12, HW_H_IADDR, 5, 11,
 440     { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 441 /* reglist_low_ld: 8 bit low register mask for ldm */
 442   { "reglist_low_ld", FR30_OPERAND_REGLIST_LOW_LD, HW_H_UINT, 8, 8,
 443     { 0, { (1<<MACH_BASE) } }  },
 444 /* reglist_hi_ld: 8 bit high register mask for ldm */
 445   { "reglist_hi_ld", FR30_OPERAND_REGLIST_HI_LD, HW_H_UINT, 8, 8,
 446     { 0, { (1<<MACH_BASE) } }  },
 447 /* reglist_low_st: 8 bit low register mask for stm */
 448   { "reglist_low_st", FR30_OPERAND_REGLIST_LOW_ST, HW_H_UINT, 8, 8,
 449     { 0, { (1<<MACH_BASE) } }  },
 450 /* reglist_hi_st: 8 bit high register mask for stm */
 451   { "reglist_hi_st", FR30_OPERAND_REGLIST_HI_ST, HW_H_UINT, 8, 8,
 452     { 0, { (1<<MACH_BASE) } }  },
 453 /* cc: condition codes */
 454   { "cc", FR30_OPERAND_CC, HW_H_UINT, 4, 4,
 455     { 0, { (1<<MACH_BASE) } }  },
 456 /* ccc: coprocessor calc */
 457   { "ccc", FR30_OPERAND_CCC, HW_H_UINT, 0, 8,
 458     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 459 /* nbit: negative   bit */
 460   { "nbit", FR30_OPERAND_NBIT, HW_H_NBIT, 0, 0,
 461     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 462 /* vbit: overflow   bit */
 463   { "vbit", FR30_OPERAND_VBIT, HW_H_VBIT, 0, 0,
 464     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 465 /* zbit: zero       bit */
 466   { "zbit", FR30_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
 467     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 468 /* cbit: carry      bit */
 469   { "cbit", FR30_OPERAND_CBIT, HW_H_CBIT, 0, 0,
 470     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 471 /* ibit: interrupt  bit */
 472   { "ibit", FR30_OPERAND_IBIT, HW_H_IBIT, 0, 0,
 473     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 474 /* sbit: stack      bit */
 475   { "sbit", FR30_OPERAND_SBIT, HW_H_SBIT, 0, 0,
 476     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 477 /* tbit: trace trap bit */
 478   { "tbit", FR30_OPERAND_TBIT, HW_H_TBIT, 0, 0,
 479     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 480 /* d0bit: division 0 bit */
 481   { "d0bit", FR30_OPERAND_D0BIT, HW_H_D0BIT, 0, 0,
 482     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 483 /* d1bit: division 1 bit */
 484   { "d1bit", FR30_OPERAND_D1BIT, HW_H_D1BIT, 0, 0,
 485     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 486 /* ccr: condition code bits */
 487   { "ccr", FR30_OPERAND_CCR, HW_H_CCR, 0, 0,
 488     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 489 /* scr: system condition bits */
 490   { "scr", FR30_OPERAND_SCR, HW_H_SCR, 0, 0,
 491     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 492 /* ilm: interrupt level mask */
 493   { "ilm", FR30_OPERAND_ILM, HW_H_ILM, 0, 0,
 494     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 495   { 0, 0, 0, 0, 0, {0, {0}} }
 496 };
 497
 498 #undef A
 499
 500 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
 501 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 502
 503 /* The instruction table.  */
 504
 505 static const CGEN_IBASE fr30_cgen_insn_table[MAX_INSNS] =
 506 {
 507   /* Special null first entry.
 508      A `num' value of zero is thus invalid.
 509      Also, the special `invalid' insn resides here.  */
 510   { 0, 0, 0, 0, {0, {0}} },
 511 /* add $Rj,$Ri */
 512   {
 513     FR30_INSN_ADD, "add", "add", 16,
 514     { 0, { (1<<MACH_BASE) } }
 515   },
 516 /* add $u4,$Ri */
 517   {
 518     FR30_INSN_ADDI, "addi", "add", 16,
 519     { 0, { (1<<MACH_BASE) } }
 520   },
 521 /* add2 $m4,$Ri */
 522   {
 523     FR30_INSN_ADD2, "add2", "add2", 16,
 524     { 0, { (1<<MACH_BASE) } }
 525   },
 526 /* addc $Rj,$Ri */
 527   {
 528     FR30_INSN_ADDC, "addc", "addc", 16,
 529     { 0, { (1<<MACH_BASE) } }
 530   },
 531 /* addn $Rj,$Ri */
 532   {
 533     FR30_INSN_ADDN, "addn", "addn", 16,
 534     { 0, { (1<<MACH_BASE) } }
 535   },
 536 /* addn $u4,$Ri */
 537   {
 538     FR30_INSN_ADDNI, "addni", "addn", 16,
 539     { 0, { (1<<MACH_BASE) } }
 540   },
 541 /* addn2 $m4,$Ri */
 542   {
 543     FR30_INSN_ADDN2, "addn2", "addn2", 16,
 544     { 0, { (1<<MACH_BASE) } }
 545   },
 546 /* sub $Rj,$Ri */
 547   {
 548     FR30_INSN_SUB, "sub", "sub", 16,
 549     { 0, { (1<<MACH_BASE) } }
 550   },
 551 /* subc $Rj,$Ri */
 552   {
 553     FR30_INSN_SUBC, "subc", "subc", 16,
 554     { 0, { (1<<MACH_BASE) } }
 555   },
 556 /* subn $Rj,$Ri */
 557   {
 558     FR30_INSN_SUBN, "subn", "subn", 16,
 559     { 0, { (1<<MACH_BASE) } }
 560   },
 561 /* cmp $Rj,$Ri */
 562   {
 563     FR30_INSN_CMP, "cmp", "cmp", 16,
 564     { 0, { (1<<MACH_BASE) } }
 565   },
 566 /* cmp $u4,$Ri */
 567   {
 568     FR30_INSN_CMPI, "cmpi", "cmp", 16,
 569     { 0, { (1<<MACH_BASE) } }
 570   },
 571 /* cmp2 $m4,$Ri */
 572   {
 573     FR30_INSN_CMP2, "cmp2", "cmp2", 16,
 574     { 0, { (1<<MACH_BASE) } }
 575   },
 576 /* and $Rj,$Ri */
 577   {
 578     FR30_INSN_AND, "and", "and", 16,
 579     { 0, { (1<<MACH_BASE) } }
 580   },
 581 /* or $Rj,$Ri */
 582   {
 583     FR30_INSN_OR, "or", "or", 16,
 584     { 0, { (1<<MACH_BASE) } }
 585   },
 586 /* eor $Rj,$Ri */
 587   {
 588     FR30_INSN_EOR, "eor", "eor", 16,
 589     { 0, { (1<<MACH_BASE) } }
 590   },
 591 /* and $Rj,@$Ri */
 592   {
 593     FR30_INSN_ANDM, "andm", "and", 16,
 594     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 595   },
 596 /* andh $Rj,@$Ri */
 597   {
 598     FR30_INSN_ANDH, "andh", "andh", 16,
 599     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 600   },
 601 /* andb $Rj,@$Ri */
 602   {
 603     FR30_INSN_ANDB, "andb", "andb", 16,
 604     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 605   },
 606 /* or $Rj,@$Ri */
 607   {
 608     FR30_INSN_ORM, "orm", "or", 16,
 609     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 610   },
 611 /* orh $Rj,@$Ri */
 612   {
 613     FR30_INSN_ORH, "orh", "orh", 16,
 614     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 615   },
 616 /* orb $Rj,@$Ri */
 617   {
 618     FR30_INSN_ORB, "orb", "orb", 16,
 619     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 620   },
 621 /* eor $Rj,@$Ri */
 622   {
 623     FR30_INSN_EORM, "eorm", "eor", 16,
 624     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 625   },
 626 /* eorh $Rj,@$Ri */
 627   {
 628     FR30_INSN_EORH, "eorh", "eorh", 16,
 629     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 630   },
 631 /* eorb $Rj,@$Ri */
 632   {
 633     FR30_INSN_EORB, "eorb", "eorb", 16,
 634     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 635   },
 636 /* bandl $u4,@$Ri */
 637   {
 638     FR30_INSN_BANDL, "bandl", "bandl", 16,
 639     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 640   },
 641 /* borl $u4,@$Ri */
 642   {
 643     FR30_INSN_BORL, "borl", "borl", 16,
 644     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 645   },
 646 /* beorl $u4,@$Ri */
 647   {
 648     FR30_INSN_BEORL, "beorl", "beorl", 16,
 649     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 650   },
 651 /* bandh $u4,@$Ri */
 652   {
 653     FR30_INSN_BANDH, "bandh", "bandh", 16,
 654     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 655   },
 656 /* borh $u4,@$Ri */
 657   {
 658     FR30_INSN_BORH, "borh", "borh", 16,
 659     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 660   },
 661 /* beorh $u4,@$Ri */
 662   {
 663     FR30_INSN_BEORH, "beorh", "beorh", 16,
 664     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 665   },
 666 /* btstl $u4,@$Ri */
 667   {
 668     FR30_INSN_BTSTL, "btstl", "btstl", 16,
 669     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 670   },
 671 /* btsth $u4,@$Ri */
 672   {
 673     FR30_INSN_BTSTH, "btsth", "btsth", 16,
 674     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 675   },
 676 /* mul $Rj,$Ri */
 677   {
 678     FR30_INSN_MUL, "mul", "mul", 16,
 679     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 680   },
 681 /* mulu $Rj,$Ri */
 682   {
 683     FR30_INSN_MULU, "mulu", "mulu", 16,
 684     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 685   },
 686 /* mulh $Rj,$Ri */
 687   {
 688     FR30_INSN_MULH, "mulh", "mulh", 16,
 689     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 690   },
 691 /* muluh $Rj,$Ri */
 692   {
 693     FR30_INSN_MULUH, "muluh", "muluh", 16,
 694     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 695   },
 696 /* div0s $Ri */
 697   {
 698     FR30_INSN_DIV0S, "div0s", "div0s", 16,
 699     { 0, { (1<<MACH_BASE) } }
 700   },
 701 /* div0u $Ri */
 702   {
 703     FR30_INSN_DIV0U, "div0u", "div0u", 16,
 704     { 0, { (1<<MACH_BASE) } }
 705   },
 706 /* div1 $Ri */
 707   {
 708     FR30_INSN_DIV1, "div1", "div1", 16,
 709     { 0, { (1<<MACH_BASE) } }
 710   },
 711 /* div2 $Ri */
 712   {
 713     FR30_INSN_DIV2, "div2", "div2", 16,
 714     { 0, { (1<<MACH_BASE) } }
 715   },
 716 /* div3 */
 717   {
 718     FR30_INSN_DIV3, "div3", "div3", 16,
 719     { 0, { (1<<MACH_BASE) } }
 720   },
 721 /* div4s */
 722   {
 723     FR30_INSN_DIV4S, "div4s", "div4s", 16,
 724     { 0, { (1<<MACH_BASE) } }
 725   },
 726 /* lsl $Rj,$Ri */
 727   {
 728     FR30_INSN_LSL, "lsl", "lsl", 16,
 729     { 0, { (1<<MACH_BASE) } }
 730   },
 731 /* lsl $u4,$Ri */
 732   {
 733     FR30_INSN_LSLI, "lsli", "lsl", 16,
 734     { 0, { (1<<MACH_BASE) } }
 735   },
 736 /* lsl2 $u4,$Ri */
 737   {
 738     FR30_INSN_LSL2, "lsl2", "lsl2", 16,
 739     { 0, { (1<<MACH_BASE) } }
 740   },
 741 /* lsr $Rj,$Ri */
 742   {
 743     FR30_INSN_LSR, "lsr", "lsr", 16,
 744     { 0, { (1<<MACH_BASE) } }
 745   },
 746 /* lsr $u4,$Ri */
 747   {
 748     FR30_INSN_LSRI, "lsri", "lsr", 16,
 749     { 0, { (1<<MACH_BASE) } }
 750   },
 751 /* lsr2 $u4,$Ri */
 752   {
 753     FR30_INSN_LSR2, "lsr2", "lsr2", 16,
 754     { 0, { (1<<MACH_BASE) } }
 755   },
 756 /* asr $Rj,$Ri */
 757   {
 758     FR30_INSN_ASR, "asr", "asr", 16,
 759     { 0, { (1<<MACH_BASE) } }
 760   },
 761 /* asr $u4,$Ri */
 762   {
 763     FR30_INSN_ASRI, "asri", "asr", 16,
 764     { 0, { (1<<MACH_BASE) } }
 765   },
 766 /* asr2 $u4,$Ri */
 767   {
 768     FR30_INSN_ASR2, "asr2", "asr2", 16,
 769     { 0, { (1<<MACH_BASE) } }
 770   },
 771 /* ldi:8 $i8,$Ri */
 772   {
 773     FR30_INSN_LDI8, "ldi8", "ldi:8", 16,
 774     { 0, { (1<<MACH_BASE) } }
 775   },
 776 /* ldi:20 $i20,$Ri */
 777   {
 778     FR30_INSN_LDI20, "ldi20", "ldi:20", 32,
 779     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 780   },
 781 /* ldi:32 $i32,$Ri */
 782   {
 783     FR30_INSN_LDI32, "ldi32", "ldi:32", 48,
 784     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 785   },
 786 /* ld @$Rj,$Ri */
 787   {
 788     FR30_INSN_LD, "ld", "ld", 16,
 789     { 0, { (1<<MACH_BASE) } }
 790   },
 791 /* lduh @$Rj,$Ri */
 792   {
 793     FR30_INSN_LDUH, "lduh", "lduh", 16,
 794     { 0, { (1<<MACH_BASE) } }
 795   },
 796 /* ldub @$Rj,$Ri */
 797   {
 798     FR30_INSN_LDUB, "ldub", "ldub", 16,
 799     { 0, { (1<<MACH_BASE) } }
 800   },
 801 /* ld @($R13,$Rj),$Ri */
 802   {
 803     FR30_INSN_LDR13, "ldr13", "ld", 16,
 804     { 0, { (1<<MACH_BASE) } }
 805   },
 806 /* lduh @($R13,$Rj),$Ri */
 807   {
 808     FR30_INSN_LDR13UH, "ldr13uh", "lduh", 16,
 809     { 0, { (1<<MACH_BASE) } }
 810   },
 811 /* ldub @($R13,$Rj),$Ri */
 812   {
 813     FR30_INSN_LDR13UB, "ldr13ub", "ldub", 16,
 814     { 0, { (1<<MACH_BASE) } }
 815   },
 816 /* ld @($R14,$disp10),$Ri */
 817   {
 818     FR30_INSN_LDR14, "ldr14", "ld", 16,
 819     { 0, { (1<<MACH_BASE) } }
 820   },
 821 /* lduh @($R14,$disp9),$Ri */
 822   {
 823     FR30_INSN_LDR14UH, "ldr14uh", "lduh", 16,
 824     { 0, { (1<<MACH_BASE) } }
 825   },
 826 /* ldub @($R14,$disp8),$Ri */
 827   {
 828     FR30_INSN_LDR14UB, "ldr14ub", "ldub", 16,
 829     { 0, { (1<<MACH_BASE) } }
 830   },
 831 /* ld @($R15,$udisp6),$Ri */
 832   {
 833     FR30_INSN_LDR15, "ldr15", "ld", 16,
 834     { 0, { (1<<MACH_BASE) } }
 835   },
 836 /* ld @$R15+,$Ri */
 837   {
 838     FR30_INSN_LDR15GR, "ldr15gr", "ld", 16,
 839     { 0, { (1<<MACH_BASE) } }
 840   },
 841 /* ld @$R15+,$Rs2 */
 842   {
 843     FR30_INSN_LDR15DR, "ldr15dr", "ld", 16,
 844     { 0, { (1<<MACH_BASE) } }
 845   },
 846 /* ld @$R15+,$ps */
 847   {
 848     FR30_INSN_LDR15PS, "ldr15ps", "ld", 16,
 849     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 850   },
 851 /* st $Ri,@$Rj */
 852   {
 853     FR30_INSN_ST, "st", "st", 16,
 854     { 0, { (1<<MACH_BASE) } }
 855   },
 856 /* sth $Ri,@$Rj */
 857   {
 858     FR30_INSN_STH, "sth", "sth", 16,
 859     { 0, { (1<<MACH_BASE) } }
 860   },
 861 /* stb $Ri,@$Rj */
 862   {
 863     FR30_INSN_STB, "stb", "stb", 16,
 864     { 0, { (1<<MACH_BASE) } }
 865   },
 866 /* st $Ri,@($R13,$Rj) */
 867   {
 868     FR30_INSN_STR13, "str13", "st", 16,
 869     { 0, { (1<<MACH_BASE) } }
 870   },
 871 /* sth $Ri,@($R13,$Rj) */
 872   {
 873     FR30_INSN_STR13H, "str13h", "sth", 16,
 874     { 0, { (1<<MACH_BASE) } }
 875   },
 876 /* stb $Ri,@($R13,$Rj) */
 877   {
 878     FR30_INSN_STR13B, "str13b", "stb", 16,
 879     { 0, { (1<<MACH_BASE) } }
 880   },
 881 /* st $Ri,@($R14,$disp10) */
 882   {
 883     FR30_INSN_STR14, "str14", "st", 16,
 884     { 0, { (1<<MACH_BASE) } }
 885   },
 886 /* sth $Ri,@($R14,$disp9) */
 887   {
 888     FR30_INSN_STR14H, "str14h", "sth", 16,
 889     { 0, { (1<<MACH_BASE) } }
 890   },
 891 /* stb $Ri,@($R14,$disp8) */
 892   {
 893     FR30_INSN_STR14B, "str14b", "stb", 16,
 894     { 0, { (1<<MACH_BASE) } }
 895   },
 896 /* st $Ri,@($R15,$udisp6) */
 897   {
 898     FR30_INSN_STR15, "str15", "st", 16,
 899     { 0, { (1<<MACH_BASE) } }
 900   },
 901 /* st $Ri,@-$R15 */
 902   {
 903     FR30_INSN_STR15GR, "str15gr", "st", 16,
 904     { 0, { (1<<MACH_BASE) } }
 905   },
 906 /* st $Rs2,@-$R15 */
 907   {
 908     FR30_INSN_STR15DR, "str15dr", "st", 16,
 909     { 0, { (1<<MACH_BASE) } }
 910   },
 911 /* st $ps,@-$R15 */
 912   {
 913     FR30_INSN_STR15PS, "str15ps", "st", 16,
 914     { 0, { (1<<MACH_BASE) } }
 915   },
 916 /* mov $Rj,$Ri */
 917   {
 918     FR30_INSN_MOV, "mov", "mov", 16,
 919     { 0, { (1<<MACH_BASE) } }
 920   },
 921 /* mov $Rs1,$Ri */
 922   {
 923     FR30_INSN_MOVDR, "movdr", "mov", 16,
 924     { 0, { (1<<MACH_BASE) } }
 925   },
 926 /* mov $ps,$Ri */
 927   {
 928     FR30_INSN_MOVPS, "movps", "mov", 16,
 929     { 0, { (1<<MACH_BASE) } }
 930   },
 931 /* mov $Ri,$Rs1 */
 932   {
 933     FR30_INSN_MOV2DR, "mov2dr", "mov", 16,
 934     { 0, { (1<<MACH_BASE) } }
 935   },
 936 /* mov $Ri,$ps */
 937   {
 938     FR30_INSN_MOV2PS, "mov2ps", "mov", 16,
 939     { 0, { (1<<MACH_BASE) } }
 940   },
 941 /* jmp @$Ri */
 942   {
 943     FR30_INSN_JMP, "jmp", "jmp", 16,
 944     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
 945   },
 946 /* jmp:d @$Ri */
 947   {
 948     FR30_INSN_JMPD, "jmpd", "jmp:d", 16,
 949     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 950   },
 951 /* call @$Ri */
 952   {
 953     FR30_INSN_CALLR, "callr", "call", 16,
 954     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
 955   },
 956 /* call:d @$Ri */
 957   {
 958     FR30_INSN_CALLRD, "callrd", "call:d", 16,
 959     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 960   },
 961 /* call $label12 */
 962   {
 963     FR30_INSN_CALL, "call", "call", 16,
 964     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
 965   },
 966 /* call:d $label12 */
 967   {
 968     FR30_INSN_CALLD, "calld", "call:d", 16,
 969     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 970   },
 971 /* ret */
 972   {
 973     FR30_INSN_RET, "ret", "ret", 16,
 974     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
 975   },
 976 /* ret:d */
 977   {
 978     FR30_INSN_RET_D, "ret:d", "ret:d", 16,
 979     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 980   },
 981 /* int $u8 */
 982   {
 983     FR30_INSN_INT, "int", "int", 16,
 984     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
 985   },
 986 /* inte */
 987   {
 988     FR30_INSN_INTE, "inte", "inte", 16,
 989     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
 990   },
 991 /* reti */
 992   {
 993     FR30_INSN_RETI, "reti", "reti", 16,
 994     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
 995   },
 996 /* bra:d $label9 */
 997   {
 998     FR30_INSN_BRAD, "brad", "bra:d", 16,
 999     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1000   },
1001 /* bra $label9 */
1002   {
1003     FR30_INSN_BRA, "bra", "bra", 16,
1004     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1005   },
1006 /* bno:d $label9 */
1007   {
1008     FR30_INSN_BNOD, "bnod", "bno:d", 16,
1009     { 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1010   },
1011 /* bno $label9 */
1012   {
1013     FR30_INSN_BNO, "bno", "bno", 16,
1014     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1015   },
1016 /* beq:d $label9 */
1017   {
1018     FR30_INSN_BEQD, "beqd", "beq:d", 16,
1019     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1020   },
1021 /* beq $label9 */
1022   {
1023     FR30_INSN_BEQ, "beq", "beq", 16,
1024     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1025   },
1026 /* bne:d $label9 */
1027   {
1028     FR30_INSN_BNED, "bned", "bne:d", 16,
1029     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1030   },
1031 /* bne $label9 */
1032   {
1033     FR30_INSN_BNE, "bne", "bne", 16,
1034     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1035   },
1036 /* bc:d $label9 */
1037   {
1038     FR30_INSN_BCD, "bcd", "bc:d", 16,
1039     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1040   },
1041 /* bc $label9 */
1042   {
1043     FR30_INSN_BC, "bc", "bc", 16,
1044     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1045   },
1046 /* bnc:d $label9 */
1047   {
1048     FR30_INSN_BNCD, "bncd", "bnc:d", 16,
1049     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1050   },
1051 /* bnc $label9 */
1052   {
1053     FR30_INSN_BNC, "bnc", "bnc", 16,
1054     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1055   },
1056 /* bn:d $label9 */
1057   {
1058     FR30_INSN_BND, "bnd", "bn:d", 16,
1059     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1060   },
1061 /* bn $label9 */
1062   {
1063     FR30_INSN_BN, "bn", "bn", 16,
1064     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1065   },
1066 /* bp:d $label9 */
1067   {
1068     FR30_INSN_BPD, "bpd", "bp:d", 16,
1069     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1070   },
1071 /* bp $label9 */
1072   {
1073     FR30_INSN_BP, "bp", "bp", 16,
1074     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1075   },
1076 /* bv:d $label9 */
1077   {
1078     FR30_INSN_BVD, "bvd", "bv:d", 16,
1079     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1080   },
1081 /* bv $label9 */
1082   {
1083     FR30_INSN_BV, "bv", "bv", 16,
1084     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1085   },
1086 /* bnv:d $label9 */
1087   {
1088     FR30_INSN_BNVD, "bnvd", "bnv:d", 16,
1089     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1090   },
1091 /* bnv $label9 */
1092   {
1093     FR30_INSN_BNV, "bnv", "bnv", 16,
1094     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1095   },
1096 /* blt:d $label9 */
1097   {
1098     FR30_INSN_BLTD, "bltd", "blt:d", 16,
1099     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1100   },
1101 /* blt $label9 */
1102   {
1103     FR30_INSN_BLT, "blt", "blt", 16,
1104     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1105   },
1106 /* bge:d $label9 */
1107   {
1108     FR30_INSN_BGED, "bged", "bge:d", 16,
1109     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1110   },
1111 /* bge $label9 */
1112   {
1113     FR30_INSN_BGE, "bge", "bge", 16,
1114     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1115   },
1116 /* ble:d $label9 */
1117   {
1118     FR30_INSN_BLED, "bled", "ble:d", 16,
1119     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1120   },
1121 /* ble $label9 */
1122   {
1123     FR30_INSN_BLE, "ble", "ble", 16,
1124     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1125   },
1126 /* bgt:d $label9 */
1127   {
1128     FR30_INSN_BGTD, "bgtd", "bgt:d", 16,
1129     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1130   },
1131 /* bgt $label9 */
1132   {
1133     FR30_INSN_BGT, "bgt", "bgt", 16,
1134     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1135   },
1136 /* bls:d $label9 */
1137   {
1138     FR30_INSN_BLSD, "blsd", "bls:d", 16,
1139     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1140   },
1141 /* bls $label9 */
1142   {
1143     FR30_INSN_BLS, "bls", "bls", 16,
1144     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1145   },
1146 /* bhi:d $label9 */
1147   {
1148     FR30_INSN_BHID, "bhid", "bhi:d", 16,
1149     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1150   },
1151 /* bhi $label9 */
1152   {
1153     FR30_INSN_BHI, "bhi", "bhi", 16,
1154     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1155   },
1156 /* dmov $R13,@$dir10 */
1157   {
1158     FR30_INSN_DMOVR13, "dmovr13", "dmov", 16,
1159     { 0, { (1<<MACH_BASE) } }
1160   },
1161 /* dmovh $R13,@$dir9 */
1162   {
1163     FR30_INSN_DMOVR13H, "dmovr13h", "dmovh", 16,
1164     { 0, { (1<<MACH_BASE) } }
1165   },
1166 /* dmovb $R13,@$dir8 */
1167   {
1168     FR30_INSN_DMOVR13B, "dmovr13b", "dmovb", 16,
1169     { 0, { (1<<MACH_BASE) } }
1170   },
1171 /* dmov @$R13+,@$dir10 */
1172   {
1173     FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov", 16,
1174     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1175   },
1176 /* dmovh @$R13+,@$dir9 */
1177   {
1178     FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh", 16,
1179     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1180   },
1181 /* dmovb @$R13+,@$dir8 */
1182   {
1183     FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb", 16,
1184     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1185   },
1186 /* dmov @$R15+,@$dir10 */
1187   {
1188     FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov", 16,
1189     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1190   },
1191 /* dmov @$dir10,$R13 */
1192   {
1193     FR30_INSN_DMOV2R13, "dmov2r13", "dmov", 16,
1194     { 0, { (1<<MACH_BASE) } }
1195   },
1196 /* dmovh @$dir9,$R13 */
1197   {
1198     FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh", 16,
1199     { 0, { (1<<MACH_BASE) } }
1200   },
1201 /* dmovb @$dir8,$R13 */
1202   {
1203     FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb", 16,
1204     { 0, { (1<<MACH_BASE) } }
1205   },
1206 /* dmov @$dir10,@$R13+ */
1207   {
1208     FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov", 16,
1209     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1210   },
1211 /* dmovh @$dir9,@$R13+ */
1212   {
1213     FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh", 16,
1214     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1215   },
1216 /* dmovb @$dir8,@$R13+ */
1217   {
1218     FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb", 16,
1219     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1220   },
1221 /* dmov @$dir10,@-$R15 */
1222   {
1223     FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov", 16,
1224     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1225   },
1226 /* ldres @$Ri+,$u4 */
1227   {
1228     FR30_INSN_LDRES, "ldres", "ldres", 16,
1229     { 0, { (1<<MACH_BASE) } }
1230   },
1231 /* stres $u4,@$Ri+ */
1232   {
1233     FR30_INSN_STRES, "stres", "stres", 16,
1234     { 0, { (1<<MACH_BASE) } }
1235   },
1236 /* copop $u4c,$ccc,$CRj,$CRi */
1237   {
1238     FR30_INSN_COPOP, "copop", "copop", 32,
1239     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1240   },
1241 /* copld $u4c,$ccc,$Rjc,$CRi */
1242   {
1243     FR30_INSN_COPLD, "copld", "copld", 32,
1244     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1245   },
1246 /* copst $u4c,$ccc,$CRj,$Ric */
1247   {
1248     FR30_INSN_COPST, "copst", "copst", 32,
1249     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1250   },
1251 /* copsv $u4c,$ccc,$CRj,$Ric */
1252   {
1253     FR30_INSN_COPSV, "copsv", "copsv", 32,
1254     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1255   },
1256 /* nop */
1257   {
1258     FR30_INSN_NOP, "nop", "nop", 16,
1259     { 0, { (1<<MACH_BASE) } }
1260   },
1261 /* andccr $u8 */
1262   {
1263     FR30_INSN_ANDCCR, "andccr", "andccr", 16,
1264     { 0, { (1<<MACH_BASE) } }
1265   },
1266 /* orccr $u8 */
1267   {
1268     FR30_INSN_ORCCR, "orccr", "orccr", 16,
1269     { 0, { (1<<MACH_BASE) } }
1270   },
1271 /* stilm $u8 */
1272   {
1273     FR30_INSN_STILM, "stilm", "stilm", 16,
1274     { 0, { (1<<MACH_BASE) } }
1275   },
1276 /* addsp $s10 */
1277   {
1278     FR30_INSN_ADDSP, "addsp", "addsp", 16,
1279     { 0, { (1<<MACH_BASE) } }
1280   },
1281 /* extsb $Ri */
1282   {
1283     FR30_INSN_EXTSB, "extsb", "extsb", 16,
1284     { 0, { (1<<MACH_BASE) } }
1285   },
1286 /* extub $Ri */
1287   {
1288     FR30_INSN_EXTUB, "extub", "extub", 16,
1289     { 0, { (1<<MACH_BASE) } }
1290   },
1291 /* extsh $Ri */
1292   {
1293     FR30_INSN_EXTSH, "extsh", "extsh", 16,
1294     { 0, { (1<<MACH_BASE) } }
1295   },
1296 /* extuh $Ri */
1297   {
1298     FR30_INSN_EXTUH, "extuh", "extuh", 16,
1299     { 0, { (1<<MACH_BASE) } }
1300   },
1301 /* ldm0 ($reglist_low_ld) */
1302   {
1303     FR30_INSN_LDM0, "ldm0", "ldm0", 16,
1304     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1305   },
1306 /* ldm1 ($reglist_hi_ld) */
1307   {
1308     FR30_INSN_LDM1, "ldm1", "ldm1", 16,
1309     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1310   },
1311 /* stm0 ($reglist_low_st) */
1312   {
1313     FR30_INSN_STM0, "stm0", "stm0", 16,
1314     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1315   },
1316 /* stm1 ($reglist_hi_st) */
1317   {
1318     FR30_INSN_STM1, "stm1", "stm1", 16,
1319     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1320   },
1321 /* enter $u10 */
1322   {
1323     FR30_INSN_ENTER, "enter", "enter", 16,
1324     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1325   },
1326 /* leave */
1327   {
1328     FR30_INSN_LEAVE, "leave", "leave", 16,
1329     { 0, { (1<<MACH_BASE) } }
1330   },
1331 /* xchb @$Rj,$Ri */
1332   {
1333     FR30_INSN_XCHB, "xchb", "xchb", 16,
1334     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1335   },
1336 };
1337
1338 #undef A
1339 #undef MNEM
1340 #undef OP
1341
1342 /* Initialize anything needed to be done once, before any cpu_open call.  */
1343
1344 static void
1345 init_tables ()
1346 {
1347 }
1348
1349 /* Subroutine of fr30_cgen_cpu_open to look up a mach via its bfd name.  */
1350
1351 static const CGEN_MACH *
1352 lookup_mach_via_bfd_name (table, name)
1353      const CGEN_MACH *table;
1354      const char *name;
1355 {
1356   while (table->name)
1357     {
1358       if (strcmp (name, table->bfd_name) == 0)
1359         return table;
1360       ++table;
1361     }
1362   abort ();
1363 }
1364
1365 /* Subroutine of fr30_cgen_cpu_open to build the hardware table.  */
1366
1367 static void
1368 build_hw_table (cd)
1369      CGEN_CPU_TABLE *cd;
1370 {
1371   int i;
1372   int machs = cd->machs;
1373   const CGEN_HW_ENTRY *init = & fr30_cgen_hw_table[0];
1374   /* MAX_HW is only an upper bound on the number of selected entries.
1375      However each entry is indexed by it's enum so there can be holes in
1376      the table.  */
1377   const CGEN_HW_ENTRY **selected =
1378     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1379
1380   cd->hw_table.init_entries = init;
1381   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1382   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1383   /* ??? For now we just use machs to determine which ones we want.  */
1384   for (i = 0; init[i].name != NULL; ++i)
1385     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1386         & machs)
1387       selected[init[i].type] = &init[i];
1388   cd->hw_table.entries = selected;
1389   cd->hw_table.num_entries = MAX_HW;
1390 }
1391
1392 /* Subroutine of fr30_cgen_cpu_open to build the hardware table.  */
1393
1394 static void
1395 build_ifield_table (cd)
1396      CGEN_CPU_TABLE *cd;
1397 {
1398   cd->ifld_table = & fr30_cgen_ifld_table[0];
1399 }
1400
1401 /* Subroutine of fr30_cgen_cpu_open to build the hardware table.  */
1402
1403 static void
1404 build_operand_table (cd)
1405      CGEN_CPU_TABLE *cd;
1406 {
1407   int i;
1408   int machs = cd->machs;
1409   const CGEN_OPERAND *init = & fr30_cgen_operand_table[0];
1410   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1411      However each entry is indexed by it's enum so there can be holes in
1412      the table.  */
1413   const CGEN_OPERAND **selected =
1414     (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1415
1416   cd->operand_table.init_entries = init;
1417   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1418   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1419   /* ??? For now we just use mach to determine which ones we want.  */
1420   for (i = 0; init[i].name != NULL; ++i)
1421     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1422         & machs)
1423       selected[init[i].type] = &init[i];
1424   cd->operand_table.entries = selected;
1425   cd->operand_table.num_entries = MAX_OPERANDS;
1426 }
1427
1428 /* Subroutine of fr30_cgen_cpu_open to build the hardware table.
1429    ??? This could leave out insns not supported by the specified mach/isa,
1430    but that would cause errors like "foo only supported by bar" to become
1431    "unknown insn", so for now we include all insns and require the app to
1432    do the checking later.
1433    ??? On the other hand, parsing of such insns may require their hardware or
1434    operand elements to be in the table [which they mightn't be].  */
1435
1436 static void
1437 build_insn_table (cd)
1438      CGEN_CPU_TABLE *cd;
1439 {
1440   int i;
1441   const CGEN_IBASE *ib = & fr30_cgen_insn_table[0];
1442   CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1443
1444   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1445   for (i = 0; i < MAX_INSNS; ++i)
1446     insns[i].base = &ib[i];
1447   cd->insn_table.init_entries = insns;
1448   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1449   cd->insn_table.num_init_entries = MAX_INSNS;
1450 }
1451
1452 /* Subroutine of fr30_cgen_cpu_open to rebuild the tables.  */
1453
1454 static void
1455 fr30_cgen_rebuild_tables (cd)
1456      CGEN_CPU_TABLE *cd;
1457 {
1458   int i,n_isas;
1459   unsigned int isas = cd->isas;
1460 #if 0
1461   unsigned int machs = cd->machs;
1462 #endif
1463
1464   cd->int_insn_p = CGEN_INT_INSN_P;
1465
1466   /* Data derived from the isa spec.  */
1467 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
1468   cd->default_insn_bitsize = UNSET;
1469   cd->base_insn_bitsize = UNSET;
1470   cd->min_insn_bitsize = 65535; /* some ridiculously big number */
1471   cd->max_insn_bitsize = 0;
1472   for (i = 0; i < MAX_ISAS; ++i)
1473     if (((1 << i) & isas) != 0)
1474       {
1475         const CGEN_ISA *isa = & fr30_cgen_isa_table[i];
1476
1477         /* Default insn sizes of all selected isas must be equal or we set
1478            the result to 0, meaning "unknown".  */
1479         if (cd->default_insn_bitsize == UNSET)
1480           cd->default_insn_bitsize = isa->default_insn_bitsize;
1481         else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1482           ; /* this is ok */
1483         else
1484           cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1485
1486         /* Base insn sizes of all selected isas must be equal or we set
1487            the result to 0, meaning "unknown".  */
1488         if (cd->base_insn_bitsize == UNSET)
1489           cd->base_insn_bitsize = isa->base_insn_bitsize;
1490         else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1491           ; /* this is ok */
1492         else
1493           cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1494
1495         /* Set min,max insn sizes.  */
1496         if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1497           cd->min_insn_bitsize = isa->min_insn_bitsize;
1498         if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1499           cd->max_insn_bitsize = isa->max_insn_bitsize;
1500
1501         ++n_isas;
1502       }
1503
1504 #if 0 /* Does nothing?? */
1505   /* Data derived from the mach spec.  */
1506   for (i = 0; i < MAX_MACHS; ++i)
1507     if (((1 << i) & machs) != 0)
1508       {
1509         const CGEN_MACH *mach = & fr30_cgen_mach_table[i];
1510
1511         ++n_machs;
1512       }
1513 #endif
1514
1515   /* Determine which hw elements are used by MACH.  */
1516   build_hw_table (cd);
1517
1518   /* Build the ifield table.  */
1519   build_ifield_table (cd);
1520
1521   /* Determine which operands are used by MACH/ISA.  */
1522   build_operand_table (cd);
1523
1524   /* Build the instruction table.  */
1525   build_insn_table (cd);
1526 }
1527
1528 /* Initialize a cpu table and return a descriptor.
1529    It's much like opening a file, and must be the first function called.
1530    The arguments are a set of (type/value) pairs, terminated with
1531    CGEN_CPU_OPEN_END.
1532
1533    Currently supported values:
1534    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
1535    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
1536    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1537    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
1538    CGEN_CPU_OPEN_END:     terminates arguments
1539
1540    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1541    precluded.
1542
1543    ??? We only support ISO C stdargs here, not K&R.
1544    Laziness, plus experiment to see if anything requires K&R - eventually
1545    K&R will no longer be supported - e.g. GDB is currently trying this.  */
1546
1547 CGEN_CPU_DESC
1548 fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1549 {
1550   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1551   static int init_p;
1552   unsigned int isas = 0;  /* 0 = "unspecified" */
1553   unsigned int machs = 0; /* 0 = "unspecified" */
1554   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1555   va_list ap;
1556
1557   if (! init_p)
1558     {
1559       init_tables ();
1560       init_p = 1;
1561     }
1562
1563   memset (cd, 0, sizeof (*cd));
1564
1565   va_start (ap, arg_type);
1566   while (arg_type != CGEN_CPU_OPEN_END)
1567     {
1568       switch (arg_type)
1569         {
1570         case CGEN_CPU_OPEN_ISAS :
1571           isas = va_arg (ap, unsigned int);
1572           break;
1573         case CGEN_CPU_OPEN_MACHS :
1574           machs = va_arg (ap, unsigned int);
1575           break;
1576         case CGEN_CPU_OPEN_BFDMACH :
1577           {
1578             const char *name = va_arg (ap, const char *);
1579             const CGEN_MACH *mach =
1580               lookup_mach_via_bfd_name (fr30_cgen_mach_table, name);
1581
1582             machs |= mach->num << 1;
1583             break;
1584           }
1585         case CGEN_CPU_OPEN_ENDIAN :
1586           endian = va_arg (ap, enum cgen_endian);
1587           break;
1588         default :
1589           fprintf (stderr, "fr30_cgen_cpu_open: unsupported argument `%d'\n",
1590                    arg_type);
1591           abort (); /* ??? return NULL? */
1592         }
1593       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1594     }
1595   va_end (ap);
1596
1597   /* mach unspecified means "all" */
1598   if (machs == 0)
1599     machs = (1 << MAX_MACHS) - 1;
1600   /* base mach is always selected */
1601   machs |= 1;
1602   /* isa unspecified means "all" */
1603   if (isas == 0)
1604     isas = (1 << MAX_ISAS) - 1;
1605   if (endian == CGEN_ENDIAN_UNKNOWN)
1606     {
1607       /* ??? If target has only one, could have a default.  */
1608       fprintf (stderr, "fr30_cgen_cpu_open: no endianness specified\n");
1609       abort ();
1610     }
1611
1612   cd->isas = isas;
1613   cd->machs = machs;
1614   cd->endian = endian;
1615   /* FIXME: for the sparc case we can determine insn-endianness statically.
1616      The worry here is where both data and insn endian can be independently
1617      chosen, in which case this function will need another argument.
1618      Actually, will want to allow for more arguments in the future anyway.  */
1619   cd->insn_endian = endian;
1620
1621   /* Table (re)builder.  */
1622   cd->rebuild_tables = fr30_cgen_rebuild_tables;
1623   fr30_cgen_rebuild_tables (cd);
1624
1625   /* Default to not allowing signed overflow.  */
1626   cd->signed_overflow_ok_p = 0;
1627
1628   return (CGEN_CPU_DESC) cd;
1629 }
1630
1631 /* Cover fn to fr30_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1632    MACH_NAME is the bfd name of the mach.  */
1633
1634 CGEN_CPU_DESC
1635 fr30_cgen_cpu_open_1 (mach_name, endian)
1636      const char *mach_name;
1637      enum cgen_endian endian;
1638 {
1639   return fr30_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1640                                CGEN_CPU_OPEN_ENDIAN, endian,
1641                                CGEN_CPU_OPEN_END);
1642 }
1643
1644 /* Close a cpu table.
1645    ??? This can live in a machine independent file, but there's currently
1646    no place to put this file (there's no libcgen).  libopcodes is the wrong
1647    place as some simulator ports use this but they don't use libopcodes.  */
1648
1649 void
1650 fr30_cgen_cpu_close (cd)
1651      CGEN_CPU_DESC cd;
1652 {
1653   if (cd->insn_table.init_entries)
1654     free ((CGEN_INSN *) cd->insn_table.init_entries);
1655   if (cd->hw_table.entries)
1656     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1657   free (cd);
1658 }
1659