opcodes/ia64-opc-a.c

   1 /* ia64-opc-a.c -- IA-64 `A' opcode table.
   2    Copyright (C) 1998, 1999 Free Software Foundation, Inc.
   3    Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
   4
   5    This file is part of GDB, GAS, and the GNU binutils.
   6
   7    GDB, GAS, and the GNU binutils are free software; you can redistribute
   8    them and/or modify them under the terms of the GNU General Public
   9    License as published by the Free Software Foundation; either version
  10    2, or (at your option) any later version.
  11
  12    GDB, GAS, and the GNU binutils are distributed in the hope that they
  13    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15    the GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING.  If not, write to the
  19    Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  20    02111-1307, USA.  */
  21
  22 #include "ia64-opc.h"
  23
  24 #define A       IA64_TYPE_A, 1
  25 #define A2      IA64_TYPE_A, 2
  26
  27 /* instruction bit fields: */
  28 #define bC(x)           (((ia64_insn) ((x) & 0x1)) << 12)
  29 #define bImm14(x)       ((((ia64_insn) (((x) >>  0) & 0x7f)) << 13) | \
  30                          (((ia64_insn) (((x) >>  7) & 0x3f)) << 27) | \
  31                          (((ia64_insn) (((x) >> 13) & 0x01)) << 36))
  32 #define bR3a(x)         (((ia64_insn) ((x) & 0x7f)) << 20)
  33 #define bR3b(x)         (((ia64_insn) ((x) & 0x3)) << 20)
  34 #define bTa(x)          (((ia64_insn) ((x) & 0x1)) << 33)
  35 #define bTb(x)          (((ia64_insn) ((x) & 0x1)) << 36)
  36 #define bVe(x)          (((ia64_insn) ((x) & 0x1)) << 33)
  37 #define bX(x)           (((ia64_insn) ((x) & 0x1)) << 33)
  38 #define bX2(x)          (((ia64_insn) ((x) & 0x3)) << 34)
  39 #define bX2a(x)         (((ia64_insn) ((x) & 0x3)) << 34)
  40 #define bX2b(x)         (((ia64_insn) ((x) & 0x3)) << 27)
  41 #define bX4(x)          (((ia64_insn) ((x) & 0xf)) << 29)
  42 #define bZa(x)          (((ia64_insn) ((x) & 0x1)) << 36)
  43 #define bZb(x)          (((ia64_insn) ((x) & 0x1)) << 33)
  44
  45 /* instruction bit masks: */
  46 #define mC      bC (-1)
  47 #define mImm14  bImm14 (-1)
  48 #define mR3a    bR3a (-1)
  49 #define mR3b    bR3b (-1)
  50 #define mTa     bTa (-1)
  51 #define mTb     bTb (-1)
  52 #define mVe     bVe (-1)
  53 #define mX      bX (-1)
  54 #define mX2     bX2 (-1)
  55 #define mX2a    bX2a (-1)
  56 #define mX2b    bX2b (-1)
  57 #define mX4     bX4 (-1)
  58 #define mZa     bZa (-1)
  59 #define mZb     bZb (-1)
  60
  61 #define OpR3b(a,b)              (bOp (a) | bR3b (b)), (mOp | mR3b)
  62 #define OpX2aVe(a,b,c)          (bOp (a) | bX2a (b) | bVe (c)), \
  63                                 (mOp | mX2a | mVe)
  64 #define OpX2aVeR3a(a,b,c,d)     (bOp (a) | bX2a (b) | bVe (c) | bR3a (d)), \
  65                                 (mOp | mX2a | mVe | mR3a)
  66 #define OpX2aVeImm14(a,b,c,d)   (bOp (a) | bX2a (b) | bVe (c) | bImm14 (d)), \
  67                                 (mOp | mX2a | mVe | mImm14)
  68 #define OpX2aVeX4(a,b,c,d)      (bOp (a) | bX2a (b) | bVe (c) | bX4 (d)), \
  69                                 (mOp | mX2a | mVe | mX4)
  70 #define OpX2aVeX4X2b(a,b,c,d,e) \
  71         (bOp (a) | bX2a (b) | bVe (c) | bX4 (d) | bX2b (e)), \
  72         (mOp | mX2a | mVe | mX4 | mX2b)
  73 #define OpX2TbTaC(a,b,c,d,e) \
  74         (bOp (a) | bX2 (b) | bTb (c) | bTa (d) | bC (e)), \
  75         (mOp | mX2 | mTb | mTa | mC)
  76 #define OpX2TaC(a,b,c,d)        (bOp (a) | bX2 (b) | bTa (c) | bC (d)), \
  77                                 (mOp | mX2 | mTa | mC)
  78 #define OpX2aZaZbX4(a,b,c,d,e) \
  79         (bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e)), \
  80         (mOp | mX2a | mZa | mZb | mX4)
  81 #define OpX2aZaZbX4X2b(a,b,c,d,e,f) \
  82         (bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e) | bX2b (f)), \
  83         (mOp | mX2a | mZa | mZb | mX4 | mX2b)
  84
  85 struct ia64_opcode ia64_opcodes_a[] =
  86   {
  87     /* A-type instruction encodings (sorted according to major opcode) */
  88
  89     {"add",      A, OpX2aVeX4X2b (8, 0, 0, 0, 0), {R1, R2, R3}},
  90     {"add",      A, OpX2aVeX4X2b (8, 0, 0, 0, 1), {R1, R2, R3, C1}},
  91     {"sub",      A, OpX2aVeX4X2b (8, 0, 0, 1, 1), {R1, R2, R3}},
  92     {"sub",      A, OpX2aVeX4X2b (8, 0, 0, 1, 0), {R1, R2, R3, C1}},
  93     {"addp4",    A, OpX2aVeX4X2b (8, 0, 0, 2, 0), {R1, R2, R3}},
  94     {"and",      A, OpX2aVeX4X2b (8, 0, 0, 3, 0), {R1, R2, R3}},
  95     {"andcm",    A, OpX2aVeX4X2b (8, 0, 0, 3, 1), {R1, R2, R3}},
  96     {"or",       A, OpX2aVeX4X2b (8, 0, 0, 3, 2), {R1, R2, R3}},
  97     {"xor",      A, OpX2aVeX4X2b (8, 0, 0, 3, 3), {R1, R2, R3}},
  98     {"shladd",   A, OpX2aVeX4 (8, 0, 0, 4), {R1, R2, CNT2a, R3}},
  99     {"shladdp4", A, OpX2aVeX4 (8, 0, 0, 6), {R1, R2, CNT2a, R3}},
 100     {"sub",      A, OpX2aVeX4X2b (8, 0, 0, 9, 1), {R1, IMM8, R3}},
 101     {"and",      A, OpX2aVeX4X2b (8, 0, 0, 0xb, 0), {R1, IMM8, R3}},
 102     {"andcm",    A, OpX2aVeX4X2b (8, 0, 0, 0xb, 1), {R1, IMM8, R3}},
 103     {"or",       A, OpX2aVeX4X2b (8, 0, 0, 0xb, 2), {R1, IMM8, R3}},
 104     {"xor",      A, OpX2aVeX4X2b (8, 0, 0, 0xb, 3), {R1, IMM8, R3}},
 105     {"mov",      A, OpX2aVeImm14 (8, 2, 0, 0), {R1, R3}},
 106     {"mov",      A, OpX2aVeR3a (8, 2, 0, 0), {R1, IMM14}, PSEUDO},
 107     {"adds",     A, OpX2aVe (8, 2, 0), {R1, IMM14, R3}},
 108     {"addp4",    A, OpX2aVe (8, 3, 0), {R1, IMM14, R3}},
 109     {"padd1",            A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 0), {R1, R2, R3}},
 110     {"padd2",            A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 0), {R1, R2, R3}},
 111     {"padd4",            A, OpX2aZaZbX4X2b (8, 1, 1, 0, 0, 0), {R1, R2, R3}},
 112     {"padd1.sss",        A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 1), {R1, R2, R3}},
 113     {"padd2.sss",        A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 1), {R1, R2, R3}},
 114     {"padd1.uuu",        A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 2), {R1, R2, R3}},
 115     {"padd2.uuu",        A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 2), {R1, R2, R3}},
 116     {"padd1.uus",        A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 3), {R1, R2, R3}},
 117     {"padd2.uus",        A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 3), {R1, R2, R3}},
 118     {"psub1",            A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 0), {R1, R2, R3}},
 119     {"psub2",            A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 0), {R1, R2, R3}},
 120     {"psub4",            A, OpX2aZaZbX4X2b (8, 1, 1, 0, 1, 0), {R1, R2, R3}},
 121     {"psub1.sss",        A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 1), {R1, R2, R3}},
 122     {"psub2.sss",        A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 1), {R1, R2, R3}},
 123     {"psub1.uuu",        A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 2), {R1, R2, R3}},
 124     {"psub2.uuu",        A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 2), {R1, R2, R3}},
 125     {"psub1.uus",        A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 3), {R1, R2, R3}},
 126     {"psub2.uus",        A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 3), {R1, R2, R3}},
 127     {"pavg1",            A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 2), {R1, R2, R3}},
 128     {"pavg2",            A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 2), {R1, R2, R3}},
 129     {"pavg1.raz",        A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 3), {R1, R2, R3}},
 130     {"pavg2.raz",        A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 3), {R1, R2, R3}},
 131     {"pavgsub1",         A, OpX2aZaZbX4X2b (8, 1, 0, 0, 3, 2), {R1, R2, R3}},
 132     {"pavgsub2",         A, OpX2aZaZbX4X2b (8, 1, 0, 1, 3, 2), {R1, R2, R3}},
 133     {"pcmp1.eq",         A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 0), {R1, R2, R3}},
 134     {"pcmp2.eq",         A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 0), {R1, R2, R3}},
 135     {"pcmp4.eq",         A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 0), {R1, R2, R3}},
 136     {"pcmp1.gt",         A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 1), {R1, R2, R3}},
 137     {"pcmp2.gt",         A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 1), {R1, R2, R3}},
 138     {"pcmp4.gt",         A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 1), {R1, R2, R3}},
 139     {"pshladd2",         A, OpX2aZaZbX4 (8, 1, 0, 1, 4), {R1, R2, CNT2b, R3}},
 140     {"pshradd2",         A, OpX2aZaZbX4 (8, 1, 0, 1, 6), {R1, R2, CNT2b, R3}},
 141
 142     {"mov",              A, OpR3b (9, 0), {R1, IMM22}, PSEUDO},
 143     {"addl",             A, Op    (9),    {R1, IMM22, R3_2}},
 144
 145     {"cmp.lt",           A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R2, R3}},
 146     {"cmp.le",           A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R3, R2}},
 147     {"cmp.gt",           A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R3, R2}},
 148     {"cmp.ge",           A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R2, R3}},
 149     {"cmp.lt.unc",       A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R2, R3}},
 150     {"cmp.le.unc",       A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R3, R2}},
 151     {"cmp.gt.unc",       A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R3, R2}},
 152     {"cmp.ge.unc",       A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R2, R3}},
 153     {"cmp.eq.and",       A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}},
 154     {"cmp.ne.andcm",     A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO},
 155     {"cmp.ne.and",       A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}},
 156     {"cmp.eq.andcm",     A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO},
 157     {"cmp4.lt",          A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R2, R3}},
 158     {"cmp4.le",          A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R3, R2}},
 159     {"cmp4.gt",          A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R3, R2}},
 160     {"cmp4.ge",          A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R2, R3}},
 161     {"cmp4.lt.unc",      A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R2, R3}},
 162     {"cmp4.le.unc",      A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R3, R2}},
 163     {"cmp4.gt.unc",      A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R3, R2}},
 164     {"cmp4.ge.unc",      A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R2, R3}},
 165     {"cmp4.eq.and",      A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}},
 166     {"cmp4.ne.andcm",    A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO},
 167     {"cmp4.ne.and",      A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}},
 168     {"cmp4.eq.andcm",    A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO},
 169     {"cmp.gt.and",       A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}},
 170     {"cmp.le.andcm",     A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO},
 171     {"cmp.le.and",       A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}},
 172     {"cmp.gt.andcm",     A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO},
 173     {"cmp.ge.and",       A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}},
 174     {"cmp.lt.andcm",     A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO},
 175     {"cmp.lt.and",       A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}},
 176     {"cmp.ge.andcm",     A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO},
 177     {"cmp4.gt.and",      A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}},
 178     {"cmp4.le.andcm",    A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO},
 179     {"cmp4.le.and",      A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}},
 180     {"cmp4.gt.andcm",    A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO},
 181     {"cmp4.ge.and",      A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}},
 182     {"cmp4.lt.andcm",    A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO},
 183     {"cmp4.lt.and",      A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}},
 184     {"cmp4.ge.andcm",    A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO},
 185     {"cmp.lt",           A2, OpX2TaC   (0xc, 2, 0, 0), {P1, P2, IMM8, R3}},
 186     {"cmp.le",           A2, OpX2TaC   (0xc, 2, 0, 0), {P1, P2, IMM8M1, R3}},
 187     {"cmp.gt",           A2, OpX2TaC   (0xc, 2, 0, 0), {P2, P1, IMM8M1, R3}},
 188     {"cmp.ge",           A2, OpX2TaC   (0xc, 2, 0, 0), {P2, P1, IMM8, R3}},
 189     {"cmp.lt.unc",       A2, OpX2TaC   (0xc, 2, 0, 1), {P1, P2, IMM8, R3}},
 190     {"cmp.le.unc",       A2, OpX2TaC   (0xc, 2, 0, 1), {P1, P2, IMM8M1, R3}},
 191     {"cmp.gt.unc",       A2, OpX2TaC   (0xc, 2, 0, 1), {P2, P1, IMM8M1, R3}},
 192     {"cmp.ge.unc",       A2, OpX2TaC   (0xc, 2, 0, 1), {P2, P1, IMM8, R3}},
 193     {"cmp.eq.and",       A2, OpX2TaC   (0xc, 2, 1, 0), {P1, P2, IMM8, R3}},
 194     {"cmp.ne.andcm",     A2, OpX2TaC   (0xc, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO},
 195     {"cmp.ne.and",       A2, OpX2TaC   (0xc, 2, 1, 1), {P1, P2, IMM8, R3}},
 196     {"cmp.eq.andcm",     A2, OpX2TaC   (0xc, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO},
 197     {"cmp4.lt",          A2, OpX2TaC   (0xc, 3, 0, 0), {P1, P2, IMM8, R3}},
 198     {"cmp4.le",          A2, OpX2TaC   (0xc, 3, 0, 0), {P1, P2, IMM8M1, R3}},
 199     {"cmp4.gt",          A2, OpX2TaC   (0xc, 3, 0, 0), {P2, P1, IMM8M1, R3}},
 200     {"cmp4.ge",          A2, OpX2TaC   (0xc, 3, 0, 0), {P2, P1, IMM8, R3}},
 201     {"cmp4.lt.unc",      A2, OpX2TaC   (0xc, 3, 0, 1), {P1, P2, IMM8, R3}},
 202     {"cmp4.le.unc",      A2, OpX2TaC   (0xc, 3, 0, 1), {P1, P2, IMM8M1, R3}},
 203     {"cmp4.gt.unc",      A2, OpX2TaC   (0xc, 3, 0, 1), {P2, P1, IMM8M1, R3}},
 204     {"cmp4.ge.unc",      A2, OpX2TaC   (0xc, 3, 0, 1), {P2, P1, IMM8, R3}},
 205     {"cmp4.eq.and",      A2, OpX2TaC   (0xc, 3, 1, 0), {P1, P2, IMM8, R3}},
 206     {"cmp4.ne.andcm",    A2, OpX2TaC   (0xc, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO},
 207     {"cmp4.ne.and",      A2, OpX2TaC   (0xc, 3, 1, 1), {P1, P2, IMM8, R3}},
 208     {"cmp4.eq.andcm",    A2, OpX2TaC   (0xc, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO},
 209     {"cmp.ltu",          A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R2, R3}},
 210     {"cmp.leu",          A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R3, R2}},
 211     {"cmp.gtu",          A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R3, R2}},
 212     {"cmp.geu",          A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R2, R3}},
 213     {"cmp.ltu.unc",      A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R2, R3}},
 214     {"cmp.leu.unc",      A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R3, R2}},
 215     {"cmp.gtu.unc",      A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R3, R2}},
 216     {"cmp.geu.unc",      A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R2, R3}},
 217     {"cmp.eq.or",        A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}},
 218     {"cmp.ne.orcm",      A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO},
 219     {"cmp.ne.or",        A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}},
 220     {"cmp.eq.orcm",      A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO},
 221     {"cmp4.ltu",         A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R2, R3}},
 222     {"cmp4.leu",         A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R3, R2}},
 223     {"cmp4.gtu",         A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R3, R2}},
 224     {"cmp4.geu",         A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R2, R3}},
 225     {"cmp4.ltu.unc",     A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R2, R3}},
 226     {"cmp4.leu.unc",     A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R3, R2}},
 227     {"cmp4.gtu.unc",     A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R3, R2}},
 228     {"cmp4.geu.unc",     A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R2, R3}},
 229     {"cmp4.eq.or",       A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}},
 230     {"cmp4.ne.orcm",     A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO},
 231     {"cmp4.ne.or",       A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}},
 232     {"cmp4.eq.orcm",     A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO},
 233     {"cmp.gt.or",        A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}},
 234     {"cmp.le.orcm",      A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO},
 235     {"cmp.le.or",        A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}},
 236     {"cmp.gt.orcm",      A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO},
 237     {"cmp.ge.or",        A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}},
 238     {"cmp.lt.orcm",      A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO},
 239     {"cmp.lt.or",        A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}},
 240     {"cmp.ge.orcm",      A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO},
 241     {"cmp4.gt.or",       A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}},
 242     {"cmp4.le.orcm",     A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO},
 243     {"cmp4.le.or",       A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}},
 244     {"cmp4.gt.orcm",     A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO},
 245     {"cmp4.ge.or",       A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}},
 246     {"cmp4.lt.orcm",     A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO},
 247     {"cmp4.lt.or",       A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}},
 248     {"cmp4.ge.orcm",     A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO},
 249     {"cmp.ltu",          A2, OpX2TaC   (0xd, 2, 0, 0), {P1, P2, IMM8, R3}},
 250     {"cmp.leu",          A2, OpX2TaC   (0xd, 2, 0, 0), {P1, P2, IMM8M1U8, R3}},
 251     {"cmp.gtu",          A2, OpX2TaC   (0xd, 2, 0, 0), {P2, P1, IMM8M1U8, R3}},
 252     {"cmp.geu",          A2, OpX2TaC   (0xd, 2, 0, 0), {P2, P1, IMM8, R3}},
 253     {"cmp.ltu.unc",      A2, OpX2TaC   (0xd, 2, 0, 1), {P1, P2, IMM8, R3}},
 254     {"cmp.leu.unc",      A2, OpX2TaC   (0xd, 2, 0, 1), {P1, P2, IMM8M1U8, R3}},
 255     {"cmp.gtu.unc",      A2, OpX2TaC   (0xd, 2, 0, 1), {P2, P1, IMM8M1U8, R3}},
 256     {"cmp.geu.unc",      A2, OpX2TaC   (0xd, 2, 0, 1), {P2, P1, IMM8, R3}},
 257     {"cmp.eq.or",        A2, OpX2TaC   (0xd, 2, 1, 0), {P1, P2, IMM8, R3}},
 258     {"cmp.ne.orcm",      A2, OpX2TaC   (0xd, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO},
 259     {"cmp.ne.or",        A2, OpX2TaC   (0xd, 2, 1, 1), {P1, P2, IMM8, R3}},
 260     {"cmp.eq.orcm",      A2, OpX2TaC   (0xd, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO},
 261     {"cmp4.ltu",         A2, OpX2TaC   (0xd, 3, 0, 0), {P1, P2, IMM8U4, R3}},
 262     {"cmp4.leu",         A2, OpX2TaC   (0xd, 3, 0, 0), {P1, P2, IMM8M1U4, R3}},
 263     {"cmp4.gtu",         A2, OpX2TaC   (0xd, 3, 0, 0), {P2, P1, IMM8M1U4, R3}},
 264     {"cmp4.geu",         A2, OpX2TaC   (0xd, 3, 0, 0), {P2, P1, IMM8U4, R3}},
 265     {"cmp4.ltu.unc",     A2, OpX2TaC   (0xd, 3, 0, 1), {P1, P2, IMM8U4, R3}},
 266     {"cmp4.leu.unc",     A2, OpX2TaC   (0xd, 3, 0, 1), {P1, P2, IMM8M1U4, R3}},
 267     {"cmp4.gtu.unc",     A2, OpX2TaC   (0xd, 3, 0, 1), {P2, P1, IMM8M1U4, R3}},
 268     {"cmp4.geu.unc",     A2, OpX2TaC   (0xd, 3, 0, 1), {P2, P1, IMM8U4, R3}},
 269     {"cmp4.eq.or",       A2, OpX2TaC   (0xd, 3, 1, 0), {P1, P2, IMM8, R3}},
 270     {"cmp4.ne.orcm",     A2, OpX2TaC   (0xd, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO},
 271     {"cmp4.ne.or",       A2, OpX2TaC   (0xd, 3, 1, 1), {P1, P2, IMM8, R3}},
 272     {"cmp4.eq.orcm",     A2, OpX2TaC   (0xd, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO},
 273     {"cmp.eq",           A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P1, P2, R2, R3}},
 274     {"cmp.ne",           A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P2, P1, R2, R3}},
 275     {"cmp.eq.unc",       A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P1, P2, R2, R3}},
 276     {"cmp.ne.unc",       A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P2, P1, R2, R3}},
 277     {"cmp.eq.or.andcm",  A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P1, P2, R2, R3}},
 278     {"cmp.ne.and.orcm",  A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO},
 279     {"cmp.ne.or.andcm",  A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P1, P2, R2, R3}},
 280     {"cmp.eq.and.orcm",  A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO},
 281     {"cmp4.eq",          A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P1, P2, R2, R3}},
 282     {"cmp4.ne",          A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P2, P1, R2, R3}},
 283     {"cmp4.eq.unc",      A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P1, P2, R2, R3}},
 284     {"cmp4.ne.unc",      A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P2, P1, R2, R3}},
 285     {"cmp4.eq.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P1, P2, R2, R3}},
 286     {"cmp4.ne.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO},
 287     {"cmp4.ne.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P1, P2, R2, R3}},
 288     {"cmp4.eq.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO},
 289     {"cmp.gt.or.andcm",  A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P1, P2, GR0, R3}},
 290     {"cmp.le.and.orcm",  A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO},
 291     {"cmp.le.or.andcm",  A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P1, P2, GR0, R3}},
 292     {"cmp.gt.and.orcm",  A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO},
 293     {"cmp.ge.or.andcm",  A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P1, P2, GR0, R3}},
 294     {"cmp.lt.and.orcm",  A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO},
 295     {"cmp.lt.or.andcm",  A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P1, P2, GR0, R3}},
 296     {"cmp.ge.and.orcm",  A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO},
 297     {"cmp4.gt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P1, P2, GR0, R3}},
 298     {"cmp4.le.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO},
 299     {"cmp4.le.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P1, P2, GR0, R3}},
 300     {"cmp4.gt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO},
 301     {"cmp4.ge.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P1, P2, GR0, R3}},
 302     {"cmp4.lt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO},
 303     {"cmp4.lt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P1, P2, GR0, R3}},
 304     {"cmp4.ge.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO},
 305     {"cmp.eq",           A2, OpX2TaC   (0xe, 2, 0, 0), {P1, P2, IMM8, R3}},
 306     {"cmp.ne",           A2, OpX2TaC   (0xe, 2, 0, 0), {P2, P1, IMM8, R3}},
 307     {"cmp.eq.unc",       A2, OpX2TaC   (0xe, 2, 0, 1), {P1, P2, IMM8, R3}},
 308     {"cmp.ne.unc",       A2, OpX2TaC   (0xe, 2, 0, 1), {P2, P1, IMM8, R3}},
 309     {"cmp.eq.or.andcm",  A2, OpX2TaC   (0xe, 2, 1, 0), {P1, P2, IMM8, R3}},
 310     {"cmp.ne.and.orcm",  A2, OpX2TaC   (0xe, 2, 1, 0), {P2, P1, IMM8, R3}, PSEUDO},
 311     {"cmp.ne.or.andcm",  A2, OpX2TaC   (0xe, 2, 1, 1), {P1, P2, IMM8, R3}},
 312     {"cmp.eq.and.orcm",  A2, OpX2TaC   (0xe, 2, 1, 1), {P2, P1, IMM8, R3}, PSEUDO},
 313     {"cmp4.eq",          A2, OpX2TaC   (0xe, 3, 0, 0), {P1, P2, IMM8, R3}},
 314     {"cmp4.ne",          A2, OpX2TaC   (0xe, 3, 0, 0), {P2, P1, IMM8, R3}},
 315     {"cmp4.eq.unc",      A2, OpX2TaC   (0xe, 3, 0, 1), {P1, P2, IMM8, R3}},
 316     {"cmp4.ne.unc",      A2, OpX2TaC   (0xe, 3, 0, 1), {P2, P1, IMM8, R3}},
 317     {"cmp4.eq.or.andcm", A2, OpX2TaC   (0xe, 3, 1, 0), {P1, P2, IMM8, R3}},
 318     {"cmp4.ne.and.orcm", A2, OpX2TaC   (0xe, 3, 1, 0), {P2, P1, IMM8, R3}, PSEUDO},
 319     {"cmp4.ne.or.andcm", A2, OpX2TaC   (0xe, 3, 1, 1), {P1, P2, IMM8, R3}},
 320     {"cmp4.eq.and.orcm", A2, OpX2TaC   (0xe, 3, 1, 1), {P2, P1, IMM8, R3}, PSEUDO},
 321
 322     {0}
 323   };
 324
 325 #undef A
 326 #undef A2
 327 #undef bC
 328 #undef bImm14
 329 #undef bR3a
 330 #undef bR3b
 331 #undef bTa
 332 #undef bTb
 333 #undef bVe
 334 #undef bX
 335 #undef bX2
 336 #undef bX2a
 337 #undef bX2b
 338 #undef bX4
 339 #undef bZa
 340 #undef bZb
 341 #undef mC
 342 #undef mImm14
 343 #undef mR3a
 344 #undef mR3b
 345 #undef mTa
 346 #undef mTb
 347 #undef mVe
 348 #undef mX
 349 #undef mX2
 350 #undef mX2a
 351 #undef mX2b
 352 #undef mX4
 353 #undef mZa
 354 #undef mZb
 355 #undef OpR3a
 356 #undef OpR3b
 357 #undef OpX2aVe
 358 #undef OpX2aVeImm14
 359 #undef OpX2aVeX4
 360 #undef OpX2aVeX4X2b
 361 #undef OpX2TbTaC
 362 #undef OpX2TaC
 363 #undef OpX2aZaZbX4
 364 #undef OpX2aZaZbX4X2b