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[binutils.git] / opcodes / m68hc11-opc.c
blob1e37971ee819932d4617a3fc3aee3b1752575e9f
1 /* m68hc11-opc.c -- Motorola 68HC11 & 68HC12 opcode list
2 Copyright 1999, 2000 Free Software Foundation, Inc.
3 Written by Stephane Carrez (stcarrez@worldnet.fr)
4
5 This file is part of GDB, GAS, and the GNU binutils.
6
7 GDB, GAS, and the GNU binutils are free software; you can redistribute
8 them and/or modify them under the terms of the GNU General Public
9 License as published by the Free Software Foundation; either version
10 2, or (at your option) any later version.
11
12 GDB, GAS, and the GNU binutils are distributed in the hope that they
13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15 the GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22 #include <stdio.h>
23 #include "ansidecl.h"
24 #include "opcode/m68hc11.h"
25
26 #define TABLE_SIZE(X) (sizeof(X) / sizeof(X[0]))
27
28 /* Combination of CCR flags. */
29 #define M6811_ZC_BIT M6811_Z_BIT|M6811_C_BIT
30 #define M6811_NZ_BIT M6811_N_BIT|M6811_Z_BIT
31 #define M6811_NZV_BIT M6811_N_BIT|M6811_Z_BIT|M6811_V_BIT
32 #define M6811_NZC_BIT M6811_N_BIT|M6811_Z_BIT|M6811_C_BIT
33 #define M6811_NVC_BIT M6811_N_BIT|M6811_V_BIT|M6811_C_BIT
34 #define M6811_ZVC_BIT M6811_Z_BIT|M6811_V_BIT|M6811_C_BIT
35 #define M6811_NZVC_BIT M6811_ZVC_BIT|M6811_N_BIT
36 #define M6811_HNZVC_BIT M6811_NZVC_BIT|M6811_H_BIT
37 #define M6811_HNVC_BIT M6811_NVC_BIT|M6811_H_BIT
38 #define M6811_VC_BIT M6811_V_BIT|M6811_C_BIT
39
40 /* Flags when the insn only changes some CCR flags. */
41 #define CHG_NONE 0,0,0
42 #define CHG_Z 0,0,M6811_Z_BIT
43 #define CHG_C 0,0,M6811_C_BIT
44 #define CHG_ZVC 0,0,M6811_ZVC_BIT
45 #define CHG_NZC 0,0,M6811_NZC_BIT
46 #define CHG_NZV 0,0,M6811_NZV_BIT
47 #define CHG_NZVC 0,0,M6811_NZVC_BIT
48 #define CHG_HNZVC 0,0,M6811_HNZVC_BIT
49 #define CHG_ALL 0,0,0xff
50
51 /* The insn clears and changes some flags. */
52 #define CLR_I 0,M6811_I_BIT,0
53 #define CLR_C 0,M6811_C_BIT,0
54 #define CLR_V 0,M6811_V_BIT,0
55 #define CLR_V_CHG_ZC 0,M6811_V_BIT,M6811_ZC_BIT
56 #define CLR_V_CHG_NZ 0,M6811_V_BIT,M6811_NZ_BIT
57 #define CLR_V_CHG_ZVC 0,M6811_V_BIT,M6811_ZVC_BIT
58 #define CLR_N_CHG_ZVC 0,M6811_N_BIT,M6811_ZVC_BIT /* Used by lsr */
59 #define CLR_VC_CHG_NZ 0,M6811_VC_BIT,M6811_NZ_BIT
60
61 /* The insn sets some flags. */
62 #define SET_I M6811_I_BIT,0,0
63 #define SET_C M6811_C_BIT,0,0
64 #define SET_V M6811_V_BIT,0,0
65 #define SET_Z_CLR_NVC M6811_Z_BIT,M6811_NVC_BIT,0
66 #define SET_C_CLR_V_CHG_NZ M6811_C_BIT,M6811_V_BIT,M6811_NZ_BIT
67 #define SET_Z_CHG_HNVC M6811_Z_BIT,0,M6811_HNVC_BIT
68
69 #define _M 0xff
70 #define OP_NONE M6811_OP_NONE
71 #define OP_PAGE2 M6811_OP_PAGE2
72 #define OP_PAGE3 M6811_OP_PAGE3
73 #define OP_PAGE4 M6811_OP_PAGE4
74 #define OP_IMM8 M6811_OP_IMM8
75 #define OP_IMM16 M6811_OP_IMM16
76 #define OP_IX M6811_OP_IX
77 #define OP_IY M6811_OP_IY
78 #define OP_IND16 M6811_OP_IND16
79 #define OP_IDX M6812_OP_IDX
80 #define OP_IDX_1 M6812_OP_IDX_1
81 #define OP_IDX_2 M6812_OP_IDX_2
82 #define OP_D_IDX M6812_OP_D_IDX
83 #define OP_D_IDX_2 M6812_OP_D_IDX_2
84 #define OP_DIRECT M6811_OP_DIRECT
85 #define OP_BITMASK M6811_OP_BITMASK
86 #define OP_JUMP_REL M6811_OP_JUMP_REL
87 #define OP_JUMP_REL16 M6812_OP_JUMP_REL16
88 #define OP_REG M6812_OP_REG
89 #define OP_REG_1 M6812_OP_REG
90 #define OP_REG_2 M6812_OP_REG_2
91 #define OP_IDX_p2 M6812_OP_IDX_P2
92 #define OP_IND16_p2 M6812_OP_IND16_P2
93 #define OP_TRAP_ID M6812_OP_TRAP_ID
94 #define OP_EXG_MARKER M6812_OP_EXG_MARKER
95 #define OP_TFR_MARKER M6812_OP_TFR_MARKER
96 #define OP_DBEQ_MARKER (M6812_OP_DBCC_MARKER|M6812_OP_EQ_MARKER)
97 #define OP_DBNE_MARKER (M6812_OP_DBCC_MARKER)
98 #define OP_TBEQ_MARKER (M6812_OP_TBCC_MARKER|M6812_OP_EQ_MARKER)
99 #define OP_TBNE_MARKER (M6812_OP_TBCC_MARKER)
100 #define OP_IBEQ_MARKER (M6812_OP_IBCC_MARKER|M6812_OP_EQ_MARKER)
101 #define OP_IBNE_MARKER (M6812_OP_IBCC_MARKER)
102
103 /*
104 { "test", OP_NONE, 1, 0x00, 5, _M, CHG_NONE, cpu6811 },
105 +-- cpu
106 Name -+ +------- Insn CCR changes
107 Format ------+ +----------- Max # cycles
108 Size --------------------+ +--------------- Min # cycles
109 +--------------------- Opcode
110 */
111 const struct m68hc11_opcode m68hc11_opcodes[] = {
112 { "aba", OP_NONE, 1, 0x1b, 2, 2, CHG_HNZVC, cpu6811 },
113 { "aba", OP_NONE | OP_PAGE2,2, 0x06, 2, 2, CHG_HNZVC, cpu6812 },
114 { "abx", OP_NONE, 1, 0x3a, 3, 3, CHG_NONE, cpu6811 },
115 { "aby", OP_NONE | OP_PAGE2,2, 0x3a, 4, 4, CHG_NONE, cpu6811 },
116
117 { "adca", OP_IMM8, 2, 0x89, 1, 1, CHG_HNZVC, cpu6811|cpu6812 },
118 { "adca", OP_DIRECT, 2, 0x99, 3, 3, CHG_HNZVC, cpu6811|cpu6812 },
119 { "adca", OP_IND16, 3, 0xb9, 3, 3, CHG_HNZVC, cpu6811|cpu6812 },
120 { "adca", OP_IX, 2, 0xa9, 4, 4, CHG_HNZVC, cpu6811 },
121 { "adca", OP_IY | OP_PAGE2, 3, 0xa9, 5, 5, CHG_HNZVC, cpu6811 },
122 { "adca", OP_IDX, 2, 0xa9, 3, 3, CHG_HNZVC, cpu6812 },
123 { "adca", OP_IDX_1, 3, 0xa9, 3, 3, CHG_HNZVC, cpu6812 },
124 { "adca", OP_IDX_2, 4, 0xa9, 4, 4, CHG_HNZVC, cpu6812 },
125 { "adca", OP_D_IDX, 2, 0xa9, 6, 6, CHG_HNZVC, cpu6812 },
126 { "adca", OP_D_IDX_2, 4, 0xa9, 6, 6, CHG_HNZVC, cpu6812 },
127
128 { "adcb", OP_IMM8, 2, 0xc9, 1, 1, CHG_HNZVC, cpu6811|cpu6812 },
129 { "adcb", OP_DIRECT, 2, 0xd9, 3, 3, CHG_HNZVC, cpu6811|cpu6812 },
130 { "adcb", OP_IND16, 3, 0xf9, 3, 3, CHG_HNZVC, cpu6811|cpu6812 },
131 { "adcb", OP_IX, 2, 0xe9, 4, 4, CHG_HNZVC, cpu6811 },
132 { "adcb", OP_IY | OP_PAGE2, 3, 0xe9, 5, 5, CHG_HNZVC, cpu6811 },
133 { "adcb", OP_IDX, 2, 0xe9, 3, 3, CHG_HNZVC, cpu6812 },
134 { "adcb", OP_IDX_1, 3, 0xe9, 3, 3, CHG_HNZVC, cpu6812 },
135 { "adcb", OP_IDX_2, 4, 0xe9, 4, 4, CHG_HNZVC, cpu6812 },
136 { "adcb", OP_D_IDX, 2, 0xe9, 6, 6, CHG_HNZVC, cpu6812 },
137 { "adcb", OP_D_IDX_2, 4, 0xe9, 6, 6, CHG_HNZVC, cpu6812 },
138
139 { "adda", OP_IMM8, 2, 0x8b, 1, 1, CHG_HNZVC, cpu6811|cpu6812 },
140 { "adda", OP_DIRECT, 2, 0x9b, 3, 3, CHG_HNZVC, cpu6811|cpu6812 },
141 { "adda", OP_IND16, 3, 0xbb, 3, 3, CHG_HNZVC, cpu6811|cpu6812 },
142 { "adda", OP_IX, 2, 0xab, 4, 4, CHG_HNZVC, cpu6811 },
143 { "adda", OP_IY | OP_PAGE2, 3, 0xab, 5, 5, CHG_HNZVC, cpu6811 },
144 { "adda", OP_IDX, 2, 0xab, 3, 3, CHG_HNZVC, cpu6812 },
145 { "adda", OP_IDX_1, 3, 0xab, 3, 3, CHG_HNZVC, cpu6812 },
146 { "adda", OP_IDX_2, 4, 0xab, 4, 4, CHG_HNZVC, cpu6812 },
147 { "adda", OP_D_IDX, 2, 0xab, 6, 6, CHG_HNZVC, cpu6812 },
148 { "adda", OP_D_IDX_2, 4, 0xab, 6, 6, CHG_HNZVC, cpu6812 },
149
150 { "addb", OP_IMM8, 2, 0xcb, 1, 1, CHG_HNZVC, cpu6811|cpu6812 },
151 { "addb", OP_DIRECT, 2, 0xdb, 3, 3, CHG_HNZVC, cpu6811|cpu6812 },
152 { "addb", OP_IND16, 3, 0xfb, 3, 3, CHG_HNZVC, cpu6811|cpu6812 },
153 { "addb", OP_IX, 2, 0xeb, 4, 4, CHG_HNZVC, cpu6811 },
154 { "addb", OP_IY | OP_PAGE2, 3, 0xeb, 5, 5, CHG_HNZVC, cpu6811 },
155 { "addb", OP_IDX, 2, 0xeb, 3, 3, CHG_HNZVC, cpu6812 },
156 { "addb", OP_IDX_1, 3, 0xeb, 3, 3, CHG_HNZVC, cpu6812 },
157 { "addb", OP_IDX_2, 4, 0xeb, 4, 4, CHG_HNZVC, cpu6812 },
158 { "addb", OP_D_IDX, 2, 0xeb, 6, 6, CHG_HNZVC, cpu6812 },
159 { "addb", OP_D_IDX_2, 4, 0xeb, 6, 6, CHG_HNZVC, cpu6812 },
160
161 { "addd", OP_IMM16, 3, 0xc3, 2, 2, CHG_NZVC, cpu6811|cpu6812 },
162 { "addd", OP_DIRECT, 2, 0xd3, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
163 { "addd", OP_IND16, 3, 0xf3, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
164 { "addd", OP_IX, 2, 0xe3, 6, 6, CHG_NZVC, cpu6811 },
165 { "addd", OP_IY | OP_PAGE2, 3, 0xe3, 7, 7, CHG_NZVC, cpu6811 },
166 { "addd", OP_IDX, 2, 0xe3, 3, 3, CHG_NZVC, cpu6812 },
167 { "addd", OP_IDX_1, 3, 0xe3, 3, 3, CHG_NZVC, cpu6812 },
168 { "addd", OP_IDX_2, 4, 0xe3, 4, 4, CHG_NZVC, cpu6812 },
169 { "addd", OP_D_IDX, 2, 0xe3, 6, 6, CHG_NZVC, cpu6812 },
170 { "addd", OP_D_IDX_2, 4, 0xe3, 6, 6, CHG_NZVC, cpu6812 },
171
172 { "anda", OP_IMM8, 2, 0x84, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
173 { "anda", OP_DIRECT, 2, 0x94, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
174 { "anda", OP_IND16, 3, 0xb4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
175 { "anda", OP_IX, 2, 0xa4, 4, 4, CLR_V_CHG_NZ, cpu6811 },
176 { "anda", OP_IY | OP_PAGE2, 3, 0xa4, 5, 5, CLR_V_CHG_NZ, cpu6811 },
177 { "anda", OP_IDX, 2, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu6812 },
178 { "anda", OP_IDX_1, 3, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu6812 },
179 { "anda", OP_IDX_2, 4, 0xa4, 4, 4, CLR_V_CHG_NZ, cpu6812 },
180 { "anda", OP_D_IDX, 2, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu6812 },
181 { "anda", OP_D_IDX_2, 4, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu6812 },
182
183 { "andb", OP_IMM8, 2, 0xc4, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
184 { "andb", OP_DIRECT, 2, 0xd4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
185 { "andb", OP_IND16, 3, 0xf4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
186 { "andb", OP_IX, 2, 0xe4, 4, 4, CLR_V_CHG_NZ, cpu6811 },
187 { "andb", OP_IY | OP_PAGE2, 3, 0xe4, 5, 5, CLR_V_CHG_NZ, cpu6811 },
188 { "andb", OP_IDX, 2, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu6812 },
189 { "andb", OP_IDX_1, 3, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu6812 },
190 { "andb", OP_IDX_2, 4, 0xe4, 4, 4, CLR_V_CHG_NZ, cpu6812 },
191 { "andb", OP_D_IDX, 2, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu6812 },
192 { "andb", OP_D_IDX_2, 4, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu6812 },
193
194 { "andcc", OP_IMM8, 2, 0x10, 1, 1, CHG_ALL, cpu6812 },
195
196 { "asl", OP_IND16, 3, 0x78, 4, 4, CHG_NZVC, cpu6811|cpu6812 },
197 { "asl", OP_IX, 2, 0x68, 6, 6, CHG_NZVC, cpu6811 },
198 { "asl", OP_IY | OP_PAGE2, 3, 0x68, 7, 7, CHG_NZVC, cpu6811 },
199 { "asl", OP_IDX, 2, 0x68, 3, 3, CHG_NZVC, cpu6812 },
200 { "asl", OP_IDX_1, 3, 0x68, 4, 4, CHG_NZVC, cpu6812 },
201 { "asl", OP_IDX_2, 4, 0x68, 5, 5, CHG_NZVC, cpu6812 },
202 { "asl", OP_D_IDX, 2, 0x68, 6, 6, CHG_NZVC, cpu6812 },
203 { "asl", OP_D_IDX_2, 4, 0x68, 6, 6, CHG_NZVC, cpu6812 },
204
205 { "asla", OP_NONE, 1, 0x48, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
206 { "aslb", OP_NONE, 1, 0x58, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
207 { "asld", OP_NONE, 1, 0x05, 3, 3, CHG_NZVC, cpu6811 },
208 { "asld", OP_NONE, 1, 0x59, 1, 1, CHG_NZVC, cpu6812 },
209
210 { "asr", OP_IND16, 3, 0x77, 4, 4, CHG_NZVC, cpu6811|cpu6812 },
211 { "asr", OP_IX, 2, 0x67, 6, 6, CHG_NZVC, cpu6811 },
212 { "asr", OP_IY | OP_PAGE2, 3, 0x67, 7, 7, CHG_NZVC, cpu6811 },
213 { "asr", OP_IDX, 2, 0x67, 3, 3, CHG_NZVC, cpu6812 },
214 { "asr", OP_IDX_1, 3, 0x67, 4, 4, CHG_NZVC, cpu6812 },
215 { "asr", OP_IDX_2, 4, 0x67, 5, 5, CHG_NZVC, cpu6812 },
216 { "asr", OP_D_IDX, 2, 0x67, 6, 6, CHG_NZVC, cpu6812 },
217 { "asr", OP_D_IDX_2, 4, 0x67, 6, 6, CHG_NZVC, cpu6812 },
218
219 { "asra", OP_NONE, 1, 0x47, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
220 { "asrb", OP_NONE, 1, 0x57, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
221
222 { "bcc", OP_JUMP_REL, 2, 0x24, 1, 3, CHG_NONE, cpu6811|cpu6812 },
223
224 { "bclr", OP_BITMASK|OP_DIRECT, 3, 0x15, 6, 6, CLR_V_CHG_NZ, cpu6811 },
225 { "bclr", OP_BITMASK|OP_IX, 3, 0x1d, 7, 7, CLR_V_CHG_NZ, cpu6811 },
226 { "bclr", OP_BITMASK|OP_IY|OP_PAGE2, 4, 0x1d, 8, 8, CLR_V_CHG_NZ, cpu6811},
227 { "bclr", OP_BITMASK|OP_DIRECT, 3, 0x4d, 4, 4, CLR_V_CHG_NZ, cpu6812 },
228 { "bclr", OP_BITMASK|OP_IND16, 4, 0x1d, 4, 4, CLR_V_CHG_NZ, cpu6812 },
229 { "bclr", OP_BITMASK|OP_IDX, 3, 0x0d, 4, 4, CLR_V_CHG_NZ, cpu6812 },
230 { "bclr", OP_BITMASK|OP_IDX_1, 4, 0x0d, 4, 4, CLR_V_CHG_NZ, cpu6812 },
231 { "bclr", OP_BITMASK|OP_IDX_2, 5, 0x0d, 6, 6, CLR_V_CHG_NZ, cpu6812 },
232
233 { "bcs", OP_JUMP_REL, 2, 0x25, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
234 { "beq", OP_JUMP_REL, 2, 0x27, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
235 { "bge", OP_JUMP_REL, 2, 0x2c, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
236
237 { "bgnd", OP_NONE, 1, 0x00, 5, 5, CHG_NONE, cpu6811 | cpu6812 },
238
239 { "bgt", OP_JUMP_REL, 2, 0x2e, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
240 { "bhi", OP_JUMP_REL, 2, 0x22, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
241 { "bhs", OP_JUMP_REL, 2, 0x24, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
242
243 { "bita", OP_IMM8, 2, 0x85, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
244 { "bita", OP_DIRECT, 2, 0x95, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
245 { "bita", OP_IND16, 3, 0xb5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
246 { "bita", OP_IX, 2, 0xa5, 4, 4, CLR_V_CHG_NZ, cpu6811 },
247 { "bita", OP_IY | OP_PAGE2, 3, 0xa5, 5, 5, CLR_V_CHG_NZ, cpu6811 },
248 { "bita", OP_IDX, 2, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu6812 },
249 { "bita", OP_IDX_1, 3, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu6812 },
250 { "bita", OP_IDX_2, 4, 0xa5, 4, 4, CLR_V_CHG_NZ, cpu6812 },
251 { "bita", OP_D_IDX, 2, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu6812 },
252 { "bita", OP_D_IDX_2, 4, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu6812 },
253
254 { "bitb", OP_IMM8, 2, 0xc5, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
255 { "bitb", OP_DIRECT, 2, 0xd5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
256 { "bitb", OP_IND16, 3, 0xf5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
257 { "bitb", OP_IX, 2, 0xe5, 4, 4, CLR_V_CHG_NZ, cpu6811 },
258 { "bitb", OP_IY | OP_PAGE2, 3, 0xe5, 5, 5, CLR_V_CHG_NZ, cpu6811 },
259 { "bitb", OP_IDX, 2, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu6812 },
260 { "bitb", OP_IDX_1, 3, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu6812 },
261 { "bitb", OP_IDX_2, 4, 0xe5, 4, 4, CLR_V_CHG_NZ, cpu6812 },
262 { "bitb", OP_D_IDX, 2, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu6812 },
263 { "bitb", OP_D_IDX_2, 4, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu6812 },
264
265 { "ble", OP_JUMP_REL, 2, 0x2f, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
266 { "blo", OP_JUMP_REL, 2, 0x25, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
267 { "bls", OP_JUMP_REL, 2, 0x23, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
268 { "blt", OP_JUMP_REL, 2, 0x2d, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
269 { "bmi", OP_JUMP_REL, 2, 0x2b, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
270 { "bne", OP_JUMP_REL, 2, 0x26, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
271 { "bpl", OP_JUMP_REL, 2, 0x2a, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
272 { "bra", OP_JUMP_REL, 2, 0x20, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
273
274 { "brclr", OP_BITMASK | OP_JUMP_REL
275 | OP_DIRECT, 4, 0x13, 6, 6, CHG_NONE, cpu6811 },
276 { "brclr", OP_BITMASK | OP_JUMP_REL
277 | OP_IX, 4, 0x1f, 7, 7, CHG_NONE, cpu6811 },
278 { "brclr", OP_BITMASK | OP_JUMP_REL
279 | OP_IY | OP_PAGE2, 5, 0x1f, 8, 8, CHG_NONE, cpu6811 },
280 { "brclr", OP_BITMASK | OP_JUMP_REL
281 | OP_DIRECT, 4, 0x4f, 4, 4, CHG_NONE, cpu6812 },
282 { "brclr", OP_BITMASK | OP_JUMP_REL
283 | OP_IND16, 5, 0x1f, 5, 5, CHG_NONE, cpu6812 },
284 { "brclr", OP_BITMASK | OP_JUMP_REL
285 | OP_IDX, 4, 0x0f, 4, 4, CHG_NONE, cpu6812 },
286 { "brclr", OP_BITMASK | OP_JUMP_REL
287 | OP_IDX_1, 5, 0x0f, 6, 6, CHG_NONE, cpu6812 },
288 { "brclr", OP_BITMASK
289 | OP_JUMP_REL
290 | OP_IDX_2, 6, 0x0f, 8, 8, CHG_NONE, cpu6812 },
291
292 { "brn", OP_JUMP_REL, 2, 0x21, 1, 3, CHG_NONE, cpu6811|cpu6812 },
293
294 { "brset", OP_BITMASK | OP_JUMP_REL
295 | OP_DIRECT, 4, 0x12, 6, 6, CHG_NONE, cpu6811 },
296 { "brset", OP_BITMASK
297 | OP_JUMP_REL
298 | OP_IX, 4, 0x1e, 7, 7, CHG_NONE, cpu6811 },
299 { "brset", OP_BITMASK | OP_JUMP_REL
300 | OP_IY | OP_PAGE2, 5, 0x1e, 8, 8, CHG_NONE, cpu6811 },
301 { "brset", OP_BITMASK | OP_JUMP_REL
302 | OP_DIRECT, 4, 0x4e, 4, 4, CHG_NONE, cpu6812 },
303 { "brset", OP_BITMASK | OP_JUMP_REL
304 | OP_IND16, 5, 0x1e, 5, 5, CHG_NONE, cpu6812 },
305 { "brset", OP_BITMASK | OP_JUMP_REL
306 | OP_IDX, 4, 0x0e, 4, 4, CHG_NONE, cpu6812 },
307 { "brset", OP_BITMASK | OP_JUMP_REL
308 | OP_IDX_1, 5, 0x0e, 6, 6, CHG_NONE, cpu6812 },
309 { "brset", OP_BITMASK | OP_JUMP_REL
310 | OP_IDX_2, 6, 0x0e, 8, 8, CHG_NONE, cpu6812 },
311
312
313 { "bset", OP_BITMASK | OP_DIRECT, 3, 0x14, 6, 6, CLR_V_CHG_NZ, cpu6811 },
314 { "bset", OP_BITMASK | OP_IX, 3, 0x1c, 7, 7, CLR_V_CHG_NZ, cpu6811 },
315 { "bset", OP_BITMASK|OP_IY|OP_PAGE2, 4, 0x1c, 8, 8, CLR_V_CHG_NZ, cpu6811 },
316 { "bset", OP_BITMASK|OP_DIRECT, 3, 0x4c, 4, 4, CLR_V_CHG_NZ, cpu6812 },
317 { "bset", OP_BITMASK|OP_IND16, 4, 0x1c, 4, 4, CLR_V_CHG_NZ, cpu6812 },
318 { "bset", OP_BITMASK|OP_IDX, 3, 0x0c, 4, 4, CLR_V_CHG_NZ, cpu6812 },
319 { "bset", OP_BITMASK|OP_IDX_1, 4, 0x0c, 4, 4, CLR_V_CHG_NZ, cpu6812 },
320 { "bset", OP_BITMASK|OP_IDX_2, 5, 0x0c, 6, 6, CLR_V_CHG_NZ, cpu6812 },
321
322 { "bsr", OP_JUMP_REL, 2, 0x8d, 6, 6, CHG_NONE, cpu6811 },
323 { "bsr", OP_JUMP_REL, 2, 0x07, 4, 4, CHG_NONE, cpu6812 },
324
325 { "bvc", OP_JUMP_REL, 2, 0x28, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
326 { "bvs", OP_JUMP_REL, 2, 0x29, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
327
328 { "call", OP_IND16, 4, 0x4a, 8, 8, CHG_NONE, cpu6812 },
329 { "call", OP_IDX, 3, 0x4b, 8, 8, CHG_NONE, cpu6812 },
330 { "call", OP_IDX_1, 4, 0x4b, 8, 8, CHG_NONE, cpu6812 },
331 { "call", OP_IDX_2, 5, 0x4b, 9, 9, CHG_NONE, cpu6812 },
332 { "call", OP_D_IDX, 2, 0x4b, 10, 10, CHG_NONE, cpu6812 },
333 { "call", OP_D_IDX_2, 4, 0x4b, 10, 10, CHG_NONE, cpu6812 },
334
335 { "cba", OP_NONE, 1, 0x11, 2, 2, CHG_NZVC, cpu6811 },
336 { "cba", OP_NONE | OP_PAGE2,2, 0x17, 2, 2, CHG_NZVC, cpu6812 },
337
338 { "clc", OP_NONE, 1, 0x0c, 2, 2, CLR_C, cpu6811 },
339 { "cli", OP_NONE, 1, 0x0e, 2, 2, CLR_I, cpu6811 },
340
341 { "clr", OP_IND16, 3, 0x7f, 6, 6, SET_Z_CLR_NVC, cpu6811 },
342 { "clr", OP_IX, 2, 0x6f, 6, 6, SET_Z_CLR_NVC, cpu6811 },
343 { "clr", OP_IY | OP_PAGE2, 3, 0x6f, 7, 7, SET_Z_CLR_NVC, cpu6811 },
344 { "clr", OP_IND16, 3, 0x79, 3, 3, SET_Z_CLR_NVC, cpu6812 },
345 { "clr", OP_IDX, 2, 0x69, 2, 2, SET_Z_CLR_NVC, cpu6812 },
346 { "clr", OP_IDX_1, 3, 0x69, 3, 3, SET_Z_CLR_NVC, cpu6812 },
347 { "clr", OP_IDX_2, 4, 0x69, 4, 4, SET_Z_CLR_NVC, cpu6812 },
348 { "clr", OP_D_IDX, 2, 0x69, 5, 5, SET_Z_CLR_NVC, cpu6812 },
349 { "clr", OP_D_IDX_2, 4, 0x69, 5, 5, SET_Z_CLR_NVC, cpu6812 },
350
351 { "clra", OP_NONE, 1, 0x4f, 2, 2, SET_Z_CLR_NVC, cpu6811 },
352 { "clrb", OP_NONE, 1, 0x5f, 2, 2, SET_Z_CLR_NVC, cpu6811 },
353 { "clra", OP_NONE, 1, 0x87, 1, 1, SET_Z_CLR_NVC, cpu6812 },
354 { "clrb", OP_NONE, 1, 0xc7, 1, 1, SET_Z_CLR_NVC, cpu6812 },
355
356 { "clv", OP_NONE, 1, 0x0a, 2, 2, CLR_V, cpu6811 },
357
358 { "cmpa", OP_IMM8, 2, 0x81, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
359 { "cmpa", OP_DIRECT, 2, 0x91, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
360 { "cmpa", OP_IND16, 3, 0xb1, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
361 { "cmpa", OP_IX, 2, 0xa1, 4, 4, CHG_NZVC, cpu6811 },
362 { "cmpa", OP_IY | OP_PAGE2, 3, 0xa1, 5, 5, CHG_NZVC, cpu6811 },
363 { "cmpa", OP_IDX, 2, 0xa1, 3, 3, CHG_NZVC, cpu6812 },
364 { "cmpa", OP_IDX_1, 3, 0xa1, 3, 3, CHG_NZVC, cpu6812 },
365 { "cmpa", OP_IDX_2, 4, 0xa1, 4, 4, CHG_NZVC, cpu6812 },
366 { "cmpa", OP_D_IDX, 2, 0xa1, 6, 6, CHG_NZVC, cpu6812 },
367 { "cmpa", OP_D_IDX_2, 4, 0xa1, 6, 6, CHG_NZVC, cpu6812 },
368
369 { "cmpb", OP_IMM8, 2, 0xc1, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
370 { "cmpb", OP_DIRECT, 2, 0xd1, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
371 { "cmpb", OP_IND16, 3, 0xf1, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
372 { "cmpb", OP_IX, 2, 0xe1, 4, 4, CHG_NZVC, cpu6811 },
373 { "cmpb", OP_IY | OP_PAGE2, 3, 0xe1, 5, 5, CHG_NZVC, cpu6811 },
374 { "cmpb", OP_IDX, 2, 0xe1, 3, 3, CHG_NZVC, cpu6812 },
375 { "cmpb", OP_IDX_1, 3, 0xe1, 3, 3, CHG_NZVC, cpu6812 },
376 { "cmpb", OP_IDX_2, 4, 0xe1, 4, 4, CHG_NZVC, cpu6812 },
377 { "cmpb", OP_D_IDX, 2, 0xe1, 6, 6, CHG_NZVC, cpu6812 },
378 { "cmpb", OP_D_IDX_2, 4, 0xe1, 6, 6, CHG_NZVC, cpu6812 },
379
380 { "com", OP_IND16, 3, 0x73, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6811 },
381 { "com", OP_IX, 2, 0x63, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6811 },
382 { "com", OP_IY | OP_PAGE2, 3, 0x63, 7, 7, SET_C_CLR_V_CHG_NZ, cpu6811 },
383 { "com", OP_IND16, 3, 0x71, 4, 4, SET_C_CLR_V_CHG_NZ, cpu6812 },
384 { "com", OP_IDX, 2, 0x61, 3, 3, SET_C_CLR_V_CHG_NZ, cpu6812 },
385 { "com", OP_IDX_1, 3, 0x61, 4, 4, SET_C_CLR_V_CHG_NZ, cpu6812 },
386 { "com", OP_IDX_2, 4, 0x61, 5, 5, SET_C_CLR_V_CHG_NZ, cpu6812 },
387 { "com", OP_D_IDX, 2, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6812 },
388 { "com", OP_D_IDX_2, 4, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6812 },
389
390 { "coma", OP_NONE, 1, 0x43, 2, 2, SET_C_CLR_V_CHG_NZ, cpu6811 },
391 { "coma", OP_NONE, 1, 0x41, 1, 1, SET_C_CLR_V_CHG_NZ, cpu6812 },
392 { "comb", OP_NONE, 1, 0x53, 2, 2, SET_C_CLR_V_CHG_NZ, cpu6811 },
393 { "comb", OP_NONE, 1, 0x51, 1, 1, SET_C_CLR_V_CHG_NZ, cpu6812 },
394
395 { "cpd", OP_IMM16 | OP_PAGE3, 4, 0x83, 5, 5, CHG_NZVC, cpu6811 },
396 { "cpd", OP_DIRECT | OP_PAGE3, 3, 0x93, 6, 6, CHG_NZVC, cpu6811 },
397 { "cpd", OP_IND16 | OP_PAGE3, 4, 0xb3, 7, 7, CHG_NZVC, cpu6811 },
398 { "cpd", OP_IX | OP_PAGE3, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811 },
399 { "cpd", OP_IY | OP_PAGE4, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811 },
400 { "cpd", OP_IMM16, 3, 0x8c, 2, 2, CHG_NZVC, cpu6812 },
401 { "cpd", OP_DIRECT, 2, 0x9c, 3, 3, CHG_NZVC, cpu6812 },
402 { "cpd", OP_IND16, 3, 0xbc, 3, 3, CHG_NZVC, cpu6812 },
403 { "cpd", OP_IDX, 2, 0xac, 3, 3, CHG_NZVC, cpu6812 },
404 { "cpd", OP_IDX_1, 3, 0xac, 3, 3, CHG_NZVC, cpu6812 },
405 { "cpd", OP_IDX_2, 4, 0xac, 4, 4, CHG_NZVC, cpu6812 },
406 { "cpd", OP_D_IDX, 2, 0xac, 6, 6, CHG_NZVC, cpu6812 },
407 { "cpd", OP_D_IDX_2, 4, 0xac, 6, 6, CHG_NZVC, cpu6812 },
408
409 { "cps", OP_IMM16, 3, 0x8f, 2, 2, CHG_NZVC, cpu6812 },
410 { "cps", OP_DIRECT, 2, 0x9f, 3, 3, CHG_NZVC, cpu6812 },
411 { "cps", OP_IND16, 3, 0xbf, 3, 3, CHG_NZVC, cpu6812 },
412 { "cps", OP_IDX, 2, 0xaf, 3, 3, CHG_NZVC, cpu6812 },
413 { "cps", OP_IDX_1, 3, 0xaf, 3, 3, CHG_NZVC, cpu6812 },
414 { "cps", OP_IDX_2, 4, 0xaf, 4, 4, CHG_NZVC, cpu6812 },
415 { "cps", OP_D_IDX, 2, 0xaf, 6, 6, CHG_NZVC, cpu6812 },
416 { "cps", OP_D_IDX_2, 4, 0xaf, 6, 6, CHG_NZVC, cpu6812 },
417
418 { "cpx", OP_IMM16, 3, 0x8c, 4, 4, CHG_NZVC, cpu6811 },
419 { "cpx", OP_DIRECT, 2, 0x9c, 5, 5, CHG_NZVC, cpu6811 },
420 { "cpx", OP_IND16, 3, 0xbc, 5, 5, CHG_NZVC, cpu6811 },
421 { "cpx", OP_IX, 2, 0xac, 6, 6, CHG_NZVC, cpu6811 },
422 { "cpx", OP_IY | OP_PAGE4, 3, 0xac, 7, 7, CHG_NZVC, cpu6811 },
423 { "cpx", OP_IMM16, 3, 0x8e, 2, 2, CHG_NZVC, cpu6812 },
424 { "cpx", OP_DIRECT, 2, 0x9e, 3, 3, CHG_NZVC, cpu6812 },
425 { "cpx", OP_IND16, 3, 0xbe, 3, 3, CHG_NZVC, cpu6812 },
426 { "cpx", OP_IDX, 2, 0xae, 3, 3, CHG_NZVC, cpu6812 },
427 { "cpx", OP_IDX_1, 3, 0xae, 3, 3, CHG_NZVC, cpu6812 },
428 { "cpx", OP_IDX_2, 4, 0xae, 4, 4, CHG_NZVC, cpu6812 },
429 { "cpx", OP_D_IDX, 2, 0xae, 6, 6, CHG_NZVC, cpu6812 },
430 { "cpx", OP_D_IDX_2, 4, 0xae, 6, 6, CHG_NZVC, cpu6812 },
431
432 { "cpy", OP_PAGE2 | OP_IMM16, 4, 0x8c, 5, 5, CHG_NZVC, cpu6811 },
433 { "cpy", OP_PAGE2 | OP_DIRECT, 3, 0x9c, 6, 6, CHG_NZVC, cpu6811 },
434 { "cpy", OP_PAGE2 | OP_IY, 3, 0xac, 7, 7, CHG_NZVC, cpu6811 },
435 { "cpy", OP_PAGE2 | OP_IND16, 4, 0xbc, 7, 7, CHG_NZVC, cpu6811 },
436 { "cpy", OP_PAGE3 | OP_IX, 3, 0xac, 7, 7, CHG_NZVC, cpu6811 },
437 { "cpy", OP_IMM16, 3, 0x8d, 2, 2, CHG_NZVC, cpu6812 },
438 { "cpy", OP_DIRECT, 2, 0x9d, 3, 3, CHG_NZVC, cpu6812 },
439 { "cpy", OP_IND16, 3, 0xbd, 3, 3, CHG_NZVC, cpu6812 },
440 { "cpy", OP_IDX, 2, 0xad, 3, 3, CHG_NZVC, cpu6812 },
441 { "cpy", OP_IDX_1, 3, 0xad, 3, 3, CHG_NZVC, cpu6812 },
442 { "cpy", OP_IDX_2, 4, 0xad, 4, 4, CHG_NZVC, cpu6812 },
443 { "cpy", OP_D_IDX, 2, 0xad, 6, 6, CHG_NZVC, cpu6812 },
444 { "cpy", OP_D_IDX_2, 4, 0xad, 6, 6, CHG_NZVC, cpu6812 },
445
446 /* After 'daa', the Z flag is undefined. Mark it as changed. */
447 { "daa", OP_NONE, 1, 0x19, 2, 2, CHG_NZVC, cpu6811 },
448 { "daa", OP_NONE | OP_PAGE2, 2, 0x07, 3, 3, CHG_NZVC, cpu6812 },
449
450 { "dbeq", OP_DBEQ_MARKER
451 | OP_REG | OP_JUMP_REL,3, 0x04, 3, 3, CHG_NONE, cpu6812 },
452 { "dbne", OP_DBNE_MARKER
453 | OP_REG | OP_JUMP_REL,3, 0x04, 3, 3, CHG_NONE, cpu6812 },
454
455 { "dec", OP_IX, 2, 0x6a, 6, 6, CHG_NZV, cpu6811 },
456 { "dec", OP_IND16, 3, 0x7a, 6, 6, CHG_NZV, cpu6811 },
457 { "dec", OP_IY | OP_PAGE2, 3, 0x6a, 7, 7, CHG_NZV, cpu6811 },
458 { "dec", OP_IND16, 3, 0x73, 4, 4, CHG_NZV, cpu6812 },
459 { "dec", OP_IDX, 2, 0x63, 3, 3, CHG_NZV, cpu6812 },
460 { "dec", OP_IDX_1, 3, 0x63, 4, 4, CHG_NZV, cpu6812 },
461 { "dec", OP_IDX_2, 4, 0x63, 5, 5, CHG_NZV, cpu6812 },
462 { "dec", OP_D_IDX, 2, 0x63, 6, 6, CHG_NZV, cpu6812 },
463 { "dec", OP_D_IDX_2, 4, 0x63, 6, 6, CHG_NZV, cpu6812 },
464
465 { "des", OP_NONE, 1, 0x34, 3, 3, CHG_NONE, cpu6811 },
466
467 { "deca", OP_NONE, 1, 0x4a, 2, 2, CHG_NZV, cpu6811 },
468 { "deca", OP_NONE, 1, 0x43, 1, 1, CHG_NZV, cpu6812 },
469 { "decb", OP_NONE, 1, 0x5a, 2, 2, CHG_NZV, cpu6811 },
470 { "decb", OP_NONE, 1, 0x53, 1, 1, CHG_NZV, cpu6812 },
471
472 { "dex", OP_NONE, 1, 0x09, 1, 1, CHG_Z, cpu6812|cpu6811 },
473 { "dey", OP_NONE | OP_PAGE2, 2, 0x09, 4, 4, CHG_Z, cpu6811 },
474 { "dey", OP_NONE, 1, 0x03, 1, 1, CHG_Z, cpu6812 },
475
476 { "ediv", OP_NONE, 1, 0x11, 11, 11, CHG_NZVC, cpu6812 },
477 { "edivs", OP_NONE | OP_PAGE2, 2, 0x14, 12, 12, CHG_NZVC, cpu6812 },
478 { "emacs", OP_IND16 | OP_PAGE2, 4, 0x12, 13, 13, CHG_NZVC, cpu6812 },
479
480 { "emaxd", OP_IDX | OP_PAGE2, 3, 0x1a, 4, 4, CHG_NZVC, cpu6812 },
481 { "emaxd", OP_IDX_1 | OP_PAGE2, 4, 0x1a, 4, 4, CHG_NZVC, cpu6812 },
482 { "emaxd", OP_IDX_2 | OP_PAGE2, 5, 0x1a, 5, 5, CHG_NZVC, cpu6812 },
483 { "emaxd", OP_D_IDX | OP_PAGE2, 3, 0x1a, 7, 7, CHG_NZVC, cpu6812 },
484 { "emaxd", OP_D_IDX_2 | OP_PAGE2, 5, 0x1a, 7, 7, CHG_NZVC, cpu6812 },
485
486 { "emaxm", OP_IDX | OP_PAGE2, 3, 0x1e, 4, 4, CHG_NZVC, cpu6812 },
487 { "emaxm", OP_IDX_1 | OP_PAGE2, 4, 0x1e, 5, 5, CHG_NZVC, cpu6812 },
488 { "emaxm", OP_IDX_2 | OP_PAGE2, 5, 0x1e, 6, 6, CHG_NZVC, cpu6812 },
489 { "emaxm", OP_D_IDX | OP_PAGE2, 3, 0x1e, 7, 7, CHG_NZVC, cpu6812 },
490 { "emaxm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1e, 7, 7, CHG_NZVC, cpu6812 },
491
492 { "emind", OP_IDX | OP_PAGE2, 3, 0x1b, 4, 4, CHG_NZVC, cpu6812 },
493 { "emind", OP_IDX_1 | OP_PAGE2, 4, 0x1b, 4, 4, CHG_NZVC, cpu6812 },
494 { "emind", OP_IDX_2 | OP_PAGE2, 5, 0x1b, 5, 5, CHG_NZVC, cpu6812 },
495 { "emind", OP_D_IDX | OP_PAGE2, 3, 0x1b, 7, 7, CHG_NZVC, cpu6812 },
496 { "emind", OP_D_IDX_2 | OP_PAGE2, 5, 0x1b, 7, 7, CHG_NZVC, cpu6812 },
497
498 { "eminm", OP_IDX | OP_PAGE2, 3, 0x1f, 4, 4, CHG_NZVC, cpu6812 },
499 { "eminm", OP_IDX_1 | OP_PAGE2, 4, 0x1f, 5, 5, CHG_NZVC, cpu6812 },
500 { "eminm", OP_IDX_2 | OP_PAGE2, 5, 0x1f, 6, 6, CHG_NZVC, cpu6812 },
501 { "eminm", OP_D_IDX | OP_PAGE2, 3, 0x1f, 7, 7, CHG_NZVC, cpu6812 },
502 { "eminm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1f, 7, 7, CHG_NZVC, cpu6812 },
503
504 { "emul", OP_NONE, 1, 0x13, 3, 3, CHG_NZC, cpu6812 },
505 { "emuls", OP_NONE | OP_PAGE2, 2, 0x13, 3, 3, CHG_NZC, cpu6812 },
506
507 { "eora", OP_IMM8, 2, 0x88, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
508 { "eora", OP_DIRECT, 2, 0x98, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
509 { "eora", OP_IND16, 3, 0xb8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
510 { "eora", OP_IX, 2, 0xa8, 4, 4, CLR_V_CHG_NZ, cpu6811 },
511 { "eora", OP_IY | OP_PAGE2, 3, 0xa8, 5, 5, CLR_V_CHG_NZ, cpu6811 },
512 { "eora", OP_IDX, 2, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu6812 },
513 { "eora", OP_IDX_1, 3, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu6812 },
514 { "eora", OP_IDX_2, 4, 0xa8, 4, 4, CLR_V_CHG_NZ, cpu6812 },
515 { "eora", OP_D_IDX, 2, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu6812 },
516 { "eora", OP_D_IDX_2, 4, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu6812 },
517
518 { "eorb", OP_IMM8, 2, 0xc8, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
519 { "eorb", OP_DIRECT, 2, 0xd8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
520 { "eorb", OP_IND16, 3, 0xf8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
521 { "eorb", OP_IX, 2, 0xe8, 4, 4, CLR_V_CHG_NZ, cpu6811 },
522 { "eorb", OP_IY | OP_PAGE2, 3, 0xe8, 5, 5, CLR_V_CHG_NZ, cpu6811 },
523 { "eorb", OP_IDX, 2, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu6812 },
524 { "eorb", OP_IDX_1, 3, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu6812 },
525 { "eorb", OP_IDX_2, 4, 0xe8, 4, 4, CLR_V_CHG_NZ, cpu6812 },
526 { "eorb", OP_D_IDX, 2, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu6812 },
527 { "eorb", OP_D_IDX_2, 4, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu6812 },
528
529 { "etbl", OP_IDX | OP_PAGE2,3, 0x3f, 10, 10, CHG_NZC, cpu6812 },
530
531 { "exg", OP_EXG_MARKER
532 | OP_REG | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812 },
533
534 { "fdiv", OP_NONE, 1, 0x03, 3, 41, CHG_ZVC, cpu6811},
535 { "fdiv", OP_NONE | OP_PAGE2, 2, 0x11, 12, 12, CHG_ZVC, cpu6812 },
536
537 { "ibeq", OP_IBEQ_MARKER
538 | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 },
539 { "ibne", OP_IBNE_MARKER
540 | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 },
541
542 { "idiv", OP_NONE, 1, 0x02, 3, 41, CLR_V_CHG_ZC, cpu6811},
543 { "idiv", OP_NONE | OP_PAGE2, 2, 0x10, 12, 12, CLR_V_CHG_ZC, cpu6812 },
544 { "idivs", OP_NONE | OP_PAGE2, 2, 0x15, 12, 12, CHG_NZVC, cpu6812 },
545
546 { "inc", OP_IX, 2, 0x6c, 6, 6, CHG_NZV, cpu6811 },
547 { "inc", OP_IND16, 3, 0x7c, 6, 6, CHG_NZV, cpu6811 },
548 { "inc", OP_IY | OP_PAGE2, 3, 0x6c, 7, 7, CHG_NZV, cpu6811 },
549 { "inc", OP_IND16, 3, 0x72, 4, 4, CHG_NZV, cpu6812 },
550 { "inc", OP_IDX, 2, 0x62, 3, 3, CHG_NZV, cpu6812 },
551 { "inc", OP_IDX_1, 3, 0x62, 4, 4, CHG_NZV, cpu6812 },
552 { "inc", OP_IDX_2, 4, 0x62, 5, 5, CHG_NZV, cpu6812 },
553 { "inc", OP_D_IDX, 2, 0x62, 6, 6, CHG_NZV, cpu6812 },
554 { "inc", OP_D_IDX_2, 4, 0x62, 6, 6, CHG_NZV, cpu6812 },
555
556 { "inca", OP_NONE, 1, 0x4c, 2, 2, CHG_NZV, cpu6811 },
557 { "inca", OP_NONE, 1, 0x42, 1, 1, CHG_NZV, cpu6812 },
558 { "incb", OP_NONE, 1, 0x5c, 2, 2, CHG_NZV, cpu6811 },
559 { "incb", OP_NONE, 1, 0x52, 1, 1, CHG_NZV, cpu6812 },
560
561 { "ins", OP_NONE, 1, 0x31, 3, 3, CHG_NONE, cpu6811 },
562
563 { "inx", OP_NONE, 1, 0x08, 1, 1, CHG_Z, cpu6811|cpu6812 },
564 { "iny", OP_NONE |OP_PAGE2, 2, 0x08, 4, 4, CHG_Z, cpu6811 },
565 { "iny", OP_NONE, 1, 0x02, 1, 1, CHG_Z, cpu6812 },
566
567 { "jmp", OP_IND16, 3, 0x7e, 3, 3, CHG_NONE, cpu6811 },
568 { "jmp", OP_IX, 2, 0x6e, 3, 3, CHG_NONE, cpu6811 },
569 { "jmp", OP_IY | OP_PAGE2, 3, 0x6e, 4, 4, CHG_NONE, cpu6811 },
570 { "jmp", OP_IND16, 3, 0x06, 3, 3, CHG_NONE, cpu6812 },
571 { "jmp", OP_IDX, 2, 0x05, 3, 3, CHG_NONE, cpu6812 },
572 { "jmp", OP_IDX_1, 3, 0x05, 3, 3, CHG_NONE, cpu6812 },
573 { "jmp", OP_IDX_2, 4, 0x05, 4, 4, CHG_NONE, cpu6812 },
574 { "jmp", OP_D_IDX, 2, 0x05, 6, 6, CHG_NONE, cpu6812 },
575 { "jmp", OP_D_IDX_2, 4, 0x05, 6, 6, CHG_NONE, cpu6812 },
576
577 { "jsr", OP_DIRECT, 2, 0x9d, 5, 5, CHG_NONE, cpu6811 },
578 { "jsr", OP_IND16, 3, 0xbd, 6, 6, CHG_NONE, cpu6811 },
579 { "jsr", OP_IX, 2, 0xad, 6, 6, CHG_NONE, cpu6811 },
580 { "jsr", OP_IY | OP_PAGE2, 3, 0xad, 6, 6, CHG_NONE, cpu6811 },
581 { "jsr", OP_DIRECT, 2, 0x17, 4, 4, CHG_NONE, cpu6812 },
582 { "jsr", OP_IND16, 3, 0x16, 4, 3, CHG_NONE, cpu6812 },
583 { "jsr", OP_IDX, 2, 0x15, 4, 4, CHG_NONE, cpu6812 },
584 { "jsr", OP_IDX_1, 3, 0x15, 4, 4, CHG_NONE, cpu6812 },
585 { "jsr", OP_IDX_2, 4, 0x15, 5, 5, CHG_NONE, cpu6812 },
586 { "jsr", OP_D_IDX, 2, 0x15, 7, 7, CHG_NONE, cpu6812 },
587 { "jsr", OP_D_IDX_2, 4, 0x15, 7, 7, CHG_NONE, cpu6812 },
588
589 { "lbcc", OP_JUMP_REL16 | OP_PAGE2, 4, 0x24, 3, 4, CHG_NONE, cpu6812 },
590 { "lbcs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x25, 3, 4, CHG_NONE, cpu6812 },
591 { "lbeq", OP_JUMP_REL16 | OP_PAGE2, 4, 0x27, 3, 4, CHG_NONE, cpu6812 },
592 { "lbge", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2c, 3, 4, CHG_NONE, cpu6812 },
593 { "lbgt", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2e, 3, 4, CHG_NONE, cpu6812 },
594 { "lbhi", OP_JUMP_REL16 | OP_PAGE2, 4, 0x22, 3, 4, CHG_NONE, cpu6812 },
595 { "lbhs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x24, 3, 4, CHG_NONE, cpu6812 },
596 { "lble", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2f, 3, 4, CHG_NONE, cpu6812 },
597 { "lblo", OP_JUMP_REL16 | OP_PAGE2, 4, 0x25, 3, 4, CHG_NONE, cpu6812 },
598 { "lbls", OP_JUMP_REL16 | OP_PAGE2, 4, 0x23, 3, 4, CHG_NONE, cpu6812 },
599 { "lblt", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2d, 3, 4, CHG_NONE, cpu6812 },
600 { "lbmi", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2b, 3, 4, CHG_NONE, cpu6812 },
601 { "lbne", OP_JUMP_REL16 | OP_PAGE2, 4, 0x26, 3, 4, CHG_NONE, cpu6812 },
602 { "lbpl", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2a, 3, 4, CHG_NONE, cpu6812 },
603 { "lbra", OP_JUMP_REL16 | OP_PAGE2, 4, 0x20, 4, 4, CHG_NONE, cpu6812 },
604 { "lbrn", OP_JUMP_REL16 | OP_PAGE2, 4, 0x21, 3, 3, CHG_NONE, cpu6812 },
605 { "lbvc", OP_JUMP_REL16 | OP_PAGE2, 4, 0x28, 3, 4, CHG_NONE, cpu6812 },
606 { "lbvs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x29, 3, 4, CHG_NONE, cpu6812 },
607
608 { "ldaa", OP_IMM8, 2, 0x86, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
609 { "ldaa", OP_DIRECT, 2, 0x96, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
610 { "ldaa", OP_IND16, 3, 0xb6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
611 { "ldaa", OP_IX, 2, 0xa6, 4, 4, CLR_V_CHG_NZ, cpu6811 },
612 { "ldaa", OP_IY | OP_PAGE2, 3, 0xa6, 5, 5, CLR_V_CHG_NZ, cpu6811 },
613 { "ldaa", OP_IDX, 2, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu6812 },
614 { "ldaa", OP_IDX_1, 3, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu6812 },
615 { "ldaa", OP_IDX_2, 4, 0xa6, 4, 4, CLR_V_CHG_NZ, cpu6812 },
616 { "ldaa", OP_D_IDX, 2, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu6812 },
617 { "ldaa", OP_D_IDX_2, 4, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu6812 },
618
619 { "ldab", OP_IMM8, 2, 0xc6, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
620 { "ldab", OP_DIRECT, 2, 0xd6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
621 { "ldab", OP_IND16, 3, 0xf6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
622 { "ldab", OP_IX, 2, 0xe6, 4, 4, CLR_V_CHG_NZ, cpu6811 },
623 { "ldab", OP_IY | OP_PAGE2, 3, 0xe6, 5, 5, CLR_V_CHG_NZ, cpu6811 },
624 { "ldab", OP_IDX, 2, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu6812 },
625 { "ldab", OP_IDX_1, 3, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu6812 },
626 { "ldab", OP_IDX_2, 4, 0xe6, 4, 4, CLR_V_CHG_NZ, cpu6812 },
627 { "ldab", OP_D_IDX, 2, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu6812 },
628 { "ldab", OP_D_IDX_2, 4, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu6812 },
629
630 { "ldd", OP_IMM16, 3, 0xcc, 2, 2, CLR_V_CHG_NZ, cpu6811|cpu6812 },
631 { "ldd", OP_DIRECT, 2, 0xdc, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
632 { "ldd", OP_IND16, 3, 0xfc, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
633 { "ldd", OP_IX, 2, 0xec, 5, 5, CLR_V_CHG_NZ, cpu6811 },
634 { "ldd", OP_IY | OP_PAGE2, 3, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6811 },
635 { "ldd", OP_IDX, 2, 0xec, 3, 3, CLR_V_CHG_NZ, cpu6812 },
636 { "ldd", OP_IDX_1, 3, 0xec, 3, 3, CLR_V_CHG_NZ, cpu6812 },
637 { "ldd", OP_IDX_2, 4, 0xec, 4, 4, CLR_V_CHG_NZ, cpu6812 },
638 { "ldd", OP_D_IDX, 2, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6812 },
639 { "ldd", OP_D_IDX_2, 4, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6812 },
640
641 { "lds", OP_IMM16, 3, 0x8e, 3, 3, CLR_V_CHG_NZ, cpu6811 },
642 { "lds", OP_DIRECT, 2, 0x9e, 4, 4, CLR_V_CHG_NZ, cpu6811 },
643 { "lds", OP_IND16, 3, 0xbe, 5, 5, CLR_V_CHG_NZ, cpu6811 },
644 { "lds", OP_IX, 2, 0xae, 5, 5, CLR_V_CHG_NZ, cpu6811 },
645 { "lds", OP_IY | OP_PAGE2, 3, 0xae, 6, 6, CLR_V_CHG_NZ, cpu6811 },
646 { "lds", OP_IMM16, 3, 0xcf, 2, 2, CLR_V_CHG_NZ, cpu6812 },
647 { "lds", OP_DIRECT, 2, 0xdf, 3, 3, CLR_V_CHG_NZ, cpu6812 },
648 { "lds", OP_IND16, 3, 0xff, 3, 3, CLR_V_CHG_NZ, cpu6812 },
649 { "lds", OP_IDX, 2, 0xef, 3, 3, CLR_V_CHG_NZ, cpu6812 },
650 { "lds", OP_IDX_1, 3, 0xef, 3, 3, CLR_V_CHG_NZ, cpu6812 },
651 { "lds", OP_IDX_2, 4, 0xef, 4, 4, CLR_V_CHG_NZ, cpu6812 },
652 { "lds", OP_D_IDX, 2, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6812 },
653 { "lds", OP_D_IDX_2, 4, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6812 },
654
655 { "ldx", OP_IMM16, 3, 0xce, 2, 2, CLR_V_CHG_NZ, cpu6811|cpu6812 },
656 { "ldx", OP_DIRECT, 2, 0xde, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
657 { "ldx", OP_IND16, 3, 0xfe, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
658 { "ldx", OP_IX, 2, 0xee, 5, 5, CLR_V_CHG_NZ, cpu6811 },
659 { "ldx", OP_IY | OP_PAGE4, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811 },
660 { "ldx", OP_IDX, 2, 0xee, 3, 3, CLR_V_CHG_NZ, cpu6812 },
661 { "ldx", OP_IDX_1, 3, 0xee, 3, 3, CLR_V_CHG_NZ, cpu6812 },
662 { "ldx", OP_IDX_2, 4, 0xee, 4, 4, CLR_V_CHG_NZ, cpu6812 },
663 { "ldx", OP_D_IDX, 2, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6812 },
664 { "ldx", OP_D_IDX_2, 4, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6812 },
665
666 { "ldy", OP_IMM16 | OP_PAGE2, 4, 0xce, 4, 4, CLR_V_CHG_NZ, cpu6811 },
667 { "ldy", OP_DIRECT | OP_PAGE2, 3, 0xde, 5, 5, CLR_V_CHG_NZ, cpu6811 },
668 { "ldy", OP_IND16 | OP_PAGE2, 4, 0xfe, 6, 6, CLR_V_CHG_NZ, cpu6811 },
669 { "ldy", OP_IX | OP_PAGE3, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811 },
670 { "ldy", OP_IY | OP_PAGE2, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811 },
671 { "ldy", OP_IMM16, 3, 0xcd, 2, 2, CLR_V_CHG_NZ, cpu6812 },
672 { "ldy", OP_DIRECT, 2, 0xdd, 3, 3, CLR_V_CHG_NZ, cpu6812 },
673 { "ldy", OP_IND16, 3, 0xfd, 3, 3, CLR_V_CHG_NZ, cpu6812 },
674 { "ldy", OP_IDX, 2, 0xed, 3, 3, CLR_V_CHG_NZ, cpu6812 },
675 { "ldy", OP_IDX_1, 3, 0xed, 3, 3, CLR_V_CHG_NZ, cpu6812 },
676 { "ldy", OP_IDX_2, 4, 0xed, 4, 4, CLR_V_CHG_NZ, cpu6812 },
677 { "ldy", OP_D_IDX, 2, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6812 },
678 { "ldy", OP_D_IDX_2, 4, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6812 },
679
680 { "leas", OP_IDX, 2, 0x1b, 2, 2, CHG_NONE, cpu6812 },
681 { "leas", OP_IDX_1, 3, 0x1b, 2, 2, CHG_NONE, cpu6812 },
682 { "leas", OP_IDX_2, 4, 0x1b, 2, 2, CHG_NONE, cpu6812 },
683
684 { "leax", OP_IDX, 2, 0x1a, 2, 2, CHG_NONE, cpu6812 },
685 { "leax", OP_IDX_1, 3, 0x1a, 2, 2, CHG_NONE, cpu6812 },
686 { "leax", OP_IDX_2, 4, 0x1a, 2, 2, CHG_NONE, cpu6812 },
687
688 { "leay", OP_IDX, 2, 0x19, 2, 2, CHG_NONE, cpu6812 },
689 { "leay", OP_IDX_1, 3, 0x19, 2, 2, CHG_NONE, cpu6812 },
690 { "leay", OP_IDX_2, 4, 0x19, 2, 2, CHG_NONE, cpu6812 },
691
692 { "lsl", OP_IND16, 3, 0x78, 4, 4, CHG_NZVC, cpu6811|cpu6812 },
693 { "lsl", OP_IX, 2, 0x68, 6, 6, CHG_NZVC, cpu6811 },
694 { "lsl", OP_IY | OP_PAGE2, 3, 0x68, 7, 7, CHG_NZVC, cpu6811 },
695 { "lsl", OP_IDX, 2, 0x68, 3, 3, CHG_NZVC, cpu6812 },
696 { "lsl", OP_IDX_1, 3, 0x68, 4, 4, CHG_NZVC, cpu6812 },
697 { "lsl", OP_IDX_2, 4, 0x68, 5, 5, CHG_NZVC, cpu6812 },
698 { "lsl", OP_D_IDX, 2, 0x68, 6, 6, CHG_NZVC, cpu6812 },
699 { "lsl", OP_D_IDX_2, 4, 0x68, 6, 6, CHG_NZVC, cpu6812 },
700
701 { "lsla", OP_NONE, 1, 0x48, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
702 { "lslb", OP_NONE, 1, 0x58, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
703 { "lsld", OP_NONE, 1, 0x05, 3, 3, CHG_NZVC, cpu6811 },
704 { "lsld", OP_NONE, 1, 0x59, 1, 1, CHG_NZVC, cpu6812 },
705
706 { "lsr", OP_IND16, 3, 0x74, 4, 4, CLR_N_CHG_ZVC, cpu6811|cpu6812},
707 { "lsr", OP_IX, 2, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6811 },
708 { "lsr", OP_IY | OP_PAGE2, 3, 0x64, 7, 7, CLR_V_CHG_ZVC, cpu6811 },
709 { "lsr", OP_IDX, 2, 0x64, 3, 3, CLR_N_CHG_ZVC, cpu6812 },
710 { "lsr", OP_IDX_1, 3, 0x64, 4, 4, CLR_N_CHG_ZVC, cpu6812 },
711 { "lsr", OP_IDX_2, 4, 0x64, 5, 5, CLR_N_CHG_ZVC, cpu6812 },
712 { "lsr", OP_D_IDX, 2, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6812 },
713 { "lsr", OP_D_IDX_2, 4, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6812 },
714
715 { "lsra", OP_NONE, 1, 0x44, 1, 1, CLR_N_CHG_ZVC, cpu6811|cpu6812},
716 { "lsrb", OP_NONE, 1, 0x54, 1, 1, CLR_N_CHG_ZVC, cpu6811|cpu6812},
717 { "lsrd", OP_NONE, 1, 0x04, 3, 3, CLR_N_CHG_ZVC, cpu6811 },
718 { "lsrd", OP_NONE, 1, 0x49, 1, 1, CLR_N_CHG_ZVC, cpu6812 },
719
720 { "maxa", OP_IDX | OP_PAGE2, 3, 0x18, 4, 4, CHG_NZVC, cpu6812 },
721 { "maxa", OP_IDX_1 | OP_PAGE2, 4, 0x18, 4, 4, CHG_NZVC, cpu6812 },
722 { "maxa", OP_IDX_2 | OP_PAGE2, 5, 0x18, 5, 5, CHG_NZVC, cpu6812 },
723 { "maxa", OP_D_IDX | OP_PAGE2, 3, 0x18, 7, 7, CHG_NZVC, cpu6812 },
724 { "maxa", OP_D_IDX_2 | OP_PAGE2, 5, 0x18, 7, 7, CHG_NZVC, cpu6812 },
725
726 { "maxm", OP_IDX | OP_PAGE2, 3, 0x1c, 4, 4, CHG_NZVC, cpu6812 },
727 { "maxm", OP_IDX_1 | OP_PAGE2, 4, 0x1c, 5, 5, CHG_NZVC, cpu6812 },
728 { "maxm", OP_IDX_2 | OP_PAGE2, 5, 0x1c, 6, 6, CHG_NZVC, cpu6812 },
729 { "maxm", OP_D_IDX | OP_PAGE2, 3, 0x1c, 7, 7, CHG_NZVC, cpu6812 },
730 { "maxm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1c, 7, 7, CHG_NZVC, cpu6812 },
731
732 { "mem", OP_NONE, 1, 0x01, 5, 5, CHG_HNZVC, cpu6812 },
733
734 { "mina", OP_IDX | OP_PAGE2, 3, 0x19, 4, 4, CHG_NZVC, cpu6812 },
735 { "mina", OP_IDX_1 | OP_PAGE2, 4, 0x19, 4, 4, CHG_NZVC, cpu6812 },
736 { "mina", OP_IDX_2 | OP_PAGE2, 5, 0x19, 5, 5, CHG_NZVC, cpu6812 },
737 { "mina", OP_D_IDX | OP_PAGE2, 3, 0x19, 7, 7, CHG_NZVC, cpu6812 },
738 { "mina", OP_D_IDX_2 | OP_PAGE2, 5, 0x19, 7, 7, CHG_NZVC, cpu6812 },
739
740 { "minm", OP_IDX | OP_PAGE2, 3, 0x1d, 4, 4, CHG_NZVC, cpu6812 },
741 { "minm", OP_IDX_1 | OP_PAGE2, 4, 0x1d, 5, 5, CHG_NZVC, cpu6812 },
742 { "minm", OP_IDX_2 | OP_PAGE2, 5, 0x1d, 6, 6, CHG_NZVC, cpu6812 },
743 { "minm", OP_D_IDX | OP_PAGE2, 3, 0x1d, 7, 7, CHG_NZVC, cpu6812 },
744 { "minm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1d, 7, 7, CHG_NZVC, cpu6812 },
745
746 { "movb", OP_IMM8|OP_IND16_p2|OP_PAGE2, 5, 0x0b, 4, 4, CHG_NONE, cpu6812 },
747 { "movb", OP_IMM8|OP_IDX_p2|OP_PAGE2, 4, 0x08, 4, 4, CHG_NONE, cpu6812 },
748 { "movb", OP_IND16|OP_IND16_p2|OP_PAGE2, 6, 0x0c, 6, 6, CHG_NONE, cpu6812 },
749 { "movb", OP_IND16 | OP_IDX_p2 | OP_PAGE2, 5, 0x09, 5, 5, CHG_NONE, cpu6812 },
750 { "movb", OP_IDX | OP_IND16_p2 | OP_PAGE2, 5, 0x0d, 5, 5, CHG_NONE, cpu6812 },
751 { "movb", OP_IDX | OP_IDX_p2 | OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu6812 },
752
753 { "movw", OP_IMM16 | OP_IND16_p2 | OP_PAGE2, 6, 0x03, 5, 5, CHG_NONE, cpu6812 },
754 { "movw", OP_IMM16 | OP_IDX_p2 | OP_PAGE2, 5, 0x00, 4, 4, CHG_NONE, cpu6812 },
755 { "movw", OP_IND16 | OP_IND16_p2 | OP_PAGE2, 6, 0x04, 6, 6, CHG_NONE, cpu6812 },
756 { "movw", OP_IND16 | OP_IDX_p2 | OP_PAGE2, 5, 0x01, 5, 5, CHG_NONE, cpu6812 },
757 { "movw", OP_IDX | OP_IND16_p2 | OP_PAGE2, 5, 0x05, 5, 5, CHG_NONE, cpu6812 },
758 { "movw", OP_IDX | OP_IDX_p2 | OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu6812 },
759
760 { "mul", OP_NONE, 1, 0x3d, 3, 10, CHG_C, cpu6811 },
761 { "mul", OP_NONE, 1, 0x12, 3, 3, CHG_C, cpu6812 },
762
763 { "neg", OP_IND16, 3, 0x70, 4, 4, CHG_NZVC, cpu6811|cpu6812 },
764 { "neg", OP_IX, 2, 0x60, 6, 6, CHG_NZVC, cpu6811 },
765 { "neg", OP_IY | OP_PAGE2, 3, 0x60, 7, 7, CHG_NZVC, cpu6811 },
766 { "neg", OP_IDX, 2, 0x60, 3, 3, CHG_NZVC, cpu6812 },
767 { "neg", OP_IDX_1, 3, 0x60, 4, 4, CHG_NZVC, cpu6812 },
768 { "neg", OP_IDX_2, 4, 0x60, 5, 5, CHG_NZVC, cpu6812 },
769 { "neg", OP_D_IDX, 2, 0x60, 6, 6, CHG_NZVC, cpu6812 },
770 { "neg", OP_D_IDX_2, 4, 0x60, 6, 6, CHG_NZVC, cpu6812 },
771
772 { "nega", OP_NONE, 1, 0x40, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
773 { "negb", OP_NONE, 1, 0x50, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
774 { "nop", OP_NONE, 1, 0x01, 2, 2, CHG_NONE, cpu6811 },
775 { "nop", OP_NONE, 1, 0xa7, 1, 1, CHG_NONE, cpu6812 },
776
777 { "oraa", OP_IMM8, 2, 0x8a, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
778 { "oraa", OP_DIRECT, 2, 0x9a, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
779 { "oraa", OP_IND16, 3, 0xba, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
780 { "oraa", OP_IX, 2, 0xaa, 4, 4, CLR_V_CHG_NZ, cpu6811 },
781 { "oraa", OP_IY | OP_PAGE2, 3, 0xaa, 5, 5, CLR_V_CHG_NZ, cpu6811 },
782 { "oraa", OP_IDX, 2, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu6812 },
783 { "oraa", OP_IDX_1, 3, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu6812 },
784 { "oraa", OP_IDX_2, 4, 0xaa, 4, 4, CLR_V_CHG_NZ, cpu6812 },
785 { "oraa", OP_D_IDX, 2, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu6812 },
786 { "oraa", OP_D_IDX_2, 4, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu6812 },
787
788 { "orab", OP_IMM8, 2, 0xca, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
789 { "orab", OP_DIRECT, 2, 0xda, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
790 { "orab", OP_IND16, 3, 0xfa, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
791 { "orab", OP_IX, 2, 0xea, 4, 4, CLR_V_CHG_NZ, cpu6811 },
792 { "orab", OP_IY | OP_PAGE2, 3, 0xea, 5, 5, CLR_V_CHG_NZ, cpu6811 },
793 { "orab", OP_IDX, 2, 0xea, 3, 3, CLR_V_CHG_NZ, cpu6812 },
794 { "orab", OP_IDX_1, 3, 0xea, 3, 3, CLR_V_CHG_NZ, cpu6812 },
795 { "orab", OP_IDX_2, 4, 0xea, 4, 4, CLR_V_CHG_NZ, cpu6812 },
796 { "orab", OP_D_IDX, 2, 0xea, 6, 6, CLR_V_CHG_NZ, cpu6812 },
797 { "orab", OP_D_IDX_2, 4, 0xea, 6, 6, CLR_V_CHG_NZ, cpu6812 },
798
799 { "orcc", OP_IMM8, 2, 0x14, 1, 1, CHG_ALL, cpu6812 },
800
801 { "psha", OP_NONE, 1, 0x36, 2, 2, CHG_NONE, cpu6811|cpu6812 },
802 { "pshb", OP_NONE, 1, 0x37, 2, 2, CHG_NONE, cpu6811|cpu6812 },
803 { "pshc", OP_NONE, 1, 0x39, 2, 2, CHG_NONE, cpu6812 },
804 { "pshd", OP_NONE, 1, 0x3b, 2, 2, CHG_NONE, cpu6812 },
805 { "pshx", OP_NONE, 1, 0x3c, 4, 4, CHG_NONE, cpu6811 },
806 { "pshx", OP_NONE, 1, 0x34, 2, 2, CHG_NONE, cpu6812 },
807 { "pshy", OP_NONE | OP_PAGE2,2, 0x3c, 5, 5, CHG_NONE, cpu6811 },
808 { "pshy", OP_NONE, 1, 0x35, 2, 2, CHG_NONE, cpu6812 },
809
810 { "pula", OP_NONE, 1, 0x32, 3, 3, CHG_NONE, cpu6811|cpu6812 },
811 { "pulb", OP_NONE, 1, 0x33, 3, 3, CHG_NONE, cpu6811|cpu6812 },
812 { "pulc", OP_NONE, 1, 0x38, 3, 3, CHG_NONE, cpu6812 },
813 { "puld", OP_NONE, 1, 0x3a, 3, 3, CHG_NONE, cpu6812 },
814 { "pulx", OP_NONE, 1, 0x38, 5, 5, CHG_NONE, cpu6811 },
815 { "pulx", OP_NONE, 1, 0x30, 3, 3, CHG_NONE, cpu6812 },
816 { "puly", OP_NONE | OP_PAGE2,2, 0x38, 6, 6, CHG_NONE, cpu6811 },
817 { "puly", OP_NONE, 1, 0x31, 3, 3, CHG_NONE, cpu6812 },
818
819 { "rev", OP_NONE | OP_PAGE2, 2, 0x3a, _M, _M, CHG_HNZVC, cpu6812 },
820 { "revw", OP_NONE | OP_PAGE2, 2, 0x3b, _M, _M, CHG_HNZVC, cpu6812 },
821
822 { "rol", OP_IND16, 3, 0x79, 6, 6, CHG_NZVC, cpu6811 },
823 { "rol", OP_IX, 2, 0x69, 6, 6, CHG_NZVC, cpu6811 },
824 { "rol", OP_IY | OP_PAGE2, 3, 0x69, 7, 7, CHG_NZVC, cpu6811 },
825 { "rol", OP_IND16, 3, 0x75, 4, 4, CHG_NZVC, cpu6812 },
826 { "rol", OP_IDX, 2, 0x65, 3, 3, CHG_NZVC, cpu6812 },
827 { "rol", OP_IDX_1, 3, 0x65, 4, 4, CHG_NZVC, cpu6812 },
828 { "rol", OP_IDX_2, 4, 0x65, 5, 5, CHG_NZVC, cpu6812 },
829 { "rol", OP_D_IDX, 2, 0x65, 6, 6, CHG_NZVC, cpu6812 },
830 { "rol", OP_D_IDX_2, 4, 0x65, 6, 6, CHG_NZVC, cpu6812 },
831
832 { "rola", OP_NONE, 1, 0x49, 2, 2, CHG_NZVC, cpu6811 },
833 { "rola", OP_NONE, 1, 0x45, 1, 1, CHG_NZVC, cpu6812 },
834 { "rolb", OP_NONE, 1, 0x59, 2, 2, CHG_NZVC, cpu6811 },
835 { "rolb", OP_NONE, 1, 0x55, 1, 1, CHG_NZVC, cpu6812 },
836
837 { "ror", OP_IND16, 3, 0x76, 4, 4, CHG_NZVC, cpu6811|cpu6812 },
838 { "ror", OP_IX, 2, 0x66, 6, 6, CHG_NZVC, cpu6811 },
839 { "ror", OP_IY | OP_PAGE2, 3, 0x66, 7, 7, CHG_NZVC, cpu6811 },
840 { "ror", OP_IDX, 2, 0x66, 3, 3, CHG_NZVC, cpu6812 },
841 { "ror", OP_IDX_1, 3, 0x66, 4, 4, CHG_NZVC, cpu6812 },
842 { "ror", OP_IDX_2, 4, 0x66, 5, 5, CHG_NZVC, cpu6812 },
843 { "ror", OP_D_IDX, 2, 0x66, 6, 6, CHG_NZVC, cpu6812 },
844 { "ror", OP_D_IDX_2, 4, 0x66, 6, 6, CHG_NZVC, cpu6812 },
845
846 { "rora", OP_NONE, 1, 0x46, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
847 { "rorb", OP_NONE, 1, 0x56, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
848
849 { "rtc", OP_NONE, 1, 0x0a, 6, 6, CHG_NONE, cpu6812 },
850 { "rti", OP_NONE, 1, 0x3b, 12, 12, CHG_ALL, cpu6811},
851 { "rti", OP_NONE, 1, 0x0b, 8, 10, CHG_ALL, cpu6812},
852 { "rts", OP_NONE, 1, 0x39, 5, 5, CHG_NONE, cpu6811 },
853 { "rts", OP_NONE, 1, 0x3d, 5, 5, CHG_NONE, cpu6812 },
854
855 { "sba", OP_NONE, 1, 0x10, 2, 2, CHG_NZVC, cpu6811 },
856 { "sba", OP_NONE | OP_PAGE2, 2, 0x16, 2, 2, CHG_NZVC, cpu6812 },
857
858 { "sbca", OP_IMM8, 2, 0x82, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
859 { "sbca", OP_DIRECT, 2, 0x92, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
860 { "sbca", OP_IND16, 3, 0xb2, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
861 { "sbca", OP_IX, 2, 0xa2, 4, 4, CHG_NZVC, cpu6811 },
862 { "sbca", OP_IY | OP_PAGE2, 3, 0xa2, 5, 5, CHG_NZVC, cpu6811 },
863 { "sbca", OP_IDX, 2, 0xa2, 3, 3, CHG_NZVC, cpu6812 },
864 { "sbca", OP_IDX_1, 3, 0xa2, 3, 3, CHG_NZVC, cpu6812 },
865 { "sbca", OP_IDX_2, 4, 0xa2, 4, 4, CHG_NZVC, cpu6812 },
866 { "sbca", OP_D_IDX, 2, 0xa2, 6, 6, CHG_NZVC, cpu6812 },
867 { "sbca", OP_D_IDX_2, 4, 0xa2, 6, 6, CHG_NZVC, cpu6812 },
868
869 { "sbcb", OP_IMM8, 2, 0xc2, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
870 { "sbcb", OP_DIRECT, 2, 0xd2, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
871 { "sbcb", OP_IND16, 3, 0xf2, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
872 { "sbcb", OP_IX, 2, 0xe2, 4, 4, CHG_NZVC, cpu6811 },
873 { "sbcb", OP_IY | OP_PAGE2, 3, 0xe2, 5, 5, CHG_NZVC, cpu6811 },
874 { "sbcb", OP_IDX, 2, 0xe2, 3, 3, CHG_NZVC, cpu6812 },
875 { "sbcb", OP_IDX_1, 3, 0xe2, 3, 3, CHG_NZVC, cpu6812 },
876 { "sbcb", OP_IDX_2, 4, 0xe2, 4, 4, CHG_NZVC, cpu6812 },
877 { "sbcb", OP_D_IDX, 2, 0xe2, 6, 6, CHG_NZVC, cpu6812 },
878 { "sbcb", OP_D_IDX_2, 4, 0xe2, 6, 6, CHG_NZVC, cpu6812 },
879
880 { "sec", OP_NONE, 1, 0x0d, 2, 2, SET_C, cpu6811 },
881 { "sei", OP_NONE, 1, 0x0f, 2, 2, SET_I, cpu6811 },
882 { "sev", OP_NONE, 1, 0x0b, 2, 2, SET_V, cpu6811 },
883
884 { "sex", M6812_OP_SEX_MARKER
885 | OP_REG | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812 },
886
887 { "staa", OP_IND16, 3, 0xb7, 4, 4, CLR_V_CHG_NZ, cpu6811 },
888 { "staa", OP_DIRECT, 2, 0x97, 3, 3, CLR_V_CHG_NZ, cpu6811 },
889 { "staa", OP_IX, 2, 0xa7, 4, 4, CLR_V_CHG_NZ, cpu6811 },
890 { "staa", OP_IY | OP_PAGE2, 3, 0xa7, 5, 5, CLR_V_CHG_NZ, cpu6811 },
891 { "staa", OP_DIRECT, 2, 0x5a, 2, 2, CLR_V_CHG_NZ, cpu6812 },
892 { "staa", OP_IND16, 3, 0x7a, 3, 3, CLR_V_CHG_NZ, cpu6812 },
893 { "staa", OP_IDX, 2, 0x6a, 2, 2, CLR_V_CHG_NZ, cpu6812 },
894 { "staa", OP_IDX_1, 3, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu6812 },
895 { "staa", OP_IDX_2, 4, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu6812 },
896 { "staa", OP_D_IDX, 2, 0x6a, 5, 5, CLR_V_CHG_NZ, cpu6812 },
897 { "staa", OP_D_IDX_2, 4, 0x6a, 5, 5, CLR_V_CHG_NZ, cpu6812 },
898
899 { "stab", OP_IND16, 3, 0xf7, 4, 4, CLR_V_CHG_NZ, cpu6811 },
900 { "stab", OP_DIRECT, 2, 0xd7, 3, 3, CLR_V_CHG_NZ, cpu6811 },
901 { "stab", OP_IX, 2, 0xe7, 4, 4, CLR_V_CHG_NZ, cpu6811 },
902 { "stab", OP_IY | OP_PAGE2, 3, 0xe7, 5, 5, CLR_V_CHG_NZ, cpu6811 },
903 { "stab", OP_DIRECT, 2, 0x5b, 2, 2, CLR_V_CHG_NZ, cpu6812 },
904 { "stab", OP_IND16, 3, 0x7b, 3, 3, CLR_V_CHG_NZ, cpu6812 },
905 { "stab", OP_IDX, 2, 0x6b, 2, 2, CLR_V_CHG_NZ, cpu6812 },
906 { "stab", OP_IDX_1, 3, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu6812 },
907 { "stab", OP_IDX_2, 4, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu6812 },
908 { "stab", OP_D_IDX, 2, 0x6b, 5, 5, CLR_V_CHG_NZ, cpu6812 },
909 { "stab", OP_D_IDX_2, 4, 0x6b, 5, 5, CLR_V_CHG_NZ, cpu6812 },
910
911 { "std", OP_IND16, 3, 0xfd, 5, 5, CLR_V_CHG_NZ, cpu6811 },
912 { "std", OP_DIRECT, 2, 0xdd, 4, 4, CLR_V_CHG_NZ, cpu6811 },
913 { "std", OP_IX, 2, 0xed, 5, 5, CLR_V_CHG_NZ, cpu6811 },
914 { "std", OP_IY | OP_PAGE2, 3, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6811 },
915 { "std", OP_DIRECT, 2, 0x5c, 2, 2, CLR_V_CHG_NZ, cpu6812 },
916 { "std", OP_IND16, 3, 0x7c, 3, 3, CLR_V_CHG_NZ, cpu6812 },
917 { "std", OP_IDX, 2, 0x6c, 2, 2, CLR_V_CHG_NZ, cpu6812 },
918 { "std", OP_IDX_1, 3, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu6812 },
919 { "std", OP_IDX_2, 4, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu6812 },
920 { "std", OP_D_IDX, 2, 0x6c, 5, 5, CLR_V_CHG_NZ, cpu6812 },
921 { "std", OP_D_IDX_2, 4, 0x6c, 5, 5, CLR_V_CHG_NZ, cpu6812 },
922
923 { "stop", OP_NONE, 1, 0xcf, 2, 2, CHG_NONE, cpu6811 },
924 { "stop", OP_NONE | OP_PAGE2,2, 0x3e, 2, 9, CHG_NONE, cpu6812 },
925
926 { "sts", OP_IND16, 3, 0xbf, 5, 5, CLR_V_CHG_NZ, cpu6811 },
927 { "sts", OP_DIRECT, 2, 0x9f, 4, 4, CLR_V_CHG_NZ, cpu6811 },
928 { "sts", OP_IX, 2, 0xaf, 5, 5, CLR_V_CHG_NZ, cpu6811 },
929 { "sts", OP_IY | OP_PAGE2, 3, 0xaf, 6, 6, CLR_V_CHG_NZ, cpu6811 },
930 { "sts", OP_DIRECT, 2, 0x5f, 2, 2, CLR_V_CHG_NZ, cpu6812 },
931 { "sts", OP_IND16, 3, 0x7f, 3, 3, CLR_V_CHG_NZ, cpu6812 },
932 { "sts", OP_IDX, 2, 0x6f, 2, 2, CLR_V_CHG_NZ, cpu6812 },
933 { "sts", OP_IDX_1, 3, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu6812 },
934 { "sts", OP_IDX_2, 4, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu6812 },
935 { "sts", OP_D_IDX, 2, 0x6f, 5, 5, CLR_V_CHG_NZ, cpu6812 },
936 { "sts", OP_D_IDX_2, 4, 0x6f, 5, 5, CLR_V_CHG_NZ, cpu6812 },
937
938 { "stx", OP_IND16, 3, 0xff, 5, 5, CLR_V_CHG_NZ, cpu6811 },
939 { "stx", OP_DIRECT, 2, 0xdf, 4, 4, CLR_V_CHG_NZ, cpu6811 },
940 { "stx", OP_IX, 2, 0xef, 5, 5, CLR_V_CHG_NZ, cpu6811 },
941 { "stx", OP_IY | OP_PAGE4, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811 },
942 { "stx", OP_DIRECT, 2, 0x5e, 2, 2, CLR_V_CHG_NZ, cpu6812 },
943 { "stx", OP_IND16, 3, 0x7e, 3, 3, CLR_V_CHG_NZ, cpu6812 },
944 { "stx", OP_IDX, 2, 0x6e, 2, 2, CLR_V_CHG_NZ, cpu6812 },
945 { "stx", OP_IDX_1, 3, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu6812 },
946 { "stx", OP_IDX_2, 4, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu6812 },
947 { "stx", OP_D_IDX, 2, 0x6e, 5, 5, CLR_V_CHG_NZ, cpu6812 },
948 { "stx", OP_D_IDX_2, 4, 0x6e, 5, 5, CLR_V_CHG_NZ, cpu6812 },
949
950 { "sty", OP_IND16 | OP_PAGE2, 4, 0xff, 6, 6, CLR_V_CHG_NZ, cpu6811 },
951 { "sty", OP_DIRECT | OP_PAGE2, 3, 0xdf, 5, 5, CLR_V_CHG_NZ, cpu6811 },
952 { "sty", OP_IY | OP_PAGE2, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811 },
953 { "sty", OP_IX | OP_PAGE3, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811 },
954 { "sty", OP_DIRECT, 2, 0x5d, 2, 2, CLR_V_CHG_NZ, cpu6812 },
955 { "sty", OP_IND16, 3, 0x7d, 3, 3, CLR_V_CHG_NZ, cpu6812 },
956 { "sty", OP_IDX, 2, 0x6d, 2, 2, CLR_V_CHG_NZ, cpu6812 },
957 { "sty", OP_IDX_1, 3, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu6812 },
958 { "sty", OP_IDX_2, 4, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu6812 },
959 { "sty", OP_D_IDX, 2, 0x6d, 5, 5, CLR_V_CHG_NZ, cpu6812 },
960 { "sty", OP_D_IDX_2, 4, 0x6d, 5, 5, CLR_V_CHG_NZ, cpu6812 },
961
962 { "suba", OP_IMM8, 2, 0x80, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
963 { "suba", OP_DIRECT, 2, 0x90, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
964 { "suba", OP_IND16, 3, 0xb0, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
965 { "suba", OP_IX, 2, 0xa0, 4, 4, CHG_NZVC, cpu6811 },
966 { "suba", OP_IY | OP_PAGE2, 3, 0xa0, 5, 5, CHG_NZVC, cpu6811 },
967 { "suba", OP_IDX, 2, 0xa0, 3, 3, CHG_NZVC, cpu6812 },
968 { "suba", OP_IDX_1, 3, 0xa0, 3, 3, CHG_NZVC, cpu6812 },
969 { "suba", OP_IDX_2, 4, 0xa0, 4, 4, CHG_NZVC, cpu6812 },
970 { "suba", OP_D_IDX, 2, 0xa0, 6, 6, CHG_NZVC, cpu6812 },
971 { "suba", OP_D_IDX_2, 4, 0xa0, 6, 6, CHG_NZVC, cpu6812 },
972
973 { "subb", OP_IMM8, 2, 0xc0, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
974 { "subb", OP_DIRECT, 2, 0xd0, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
975 { "subb", OP_IND16, 3, 0xf0, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
976 { "subb", OP_IX, 2, 0xe0, 4, 4, CHG_NZVC, cpu6811 },
977 { "subb", OP_IY | OP_PAGE2, 3, 0xe0, 5, 5, CHG_NZVC, cpu6811 },
978 { "subb", OP_IDX, 2, 0xe0, 3, 3, CHG_NZVC, cpu6812 },
979 { "subb", OP_IDX_1, 3, 0xe0, 3, 3, CHG_NZVC, cpu6812 },
980 { "subb", OP_IDX_2, 4, 0xe0, 4, 4, CHG_NZVC, cpu6812 },
981 { "subb", OP_D_IDX, 2, 0xe0, 6, 6, CHG_NZVC, cpu6812 },
982 { "subb", OP_D_IDX_2, 4, 0xe0, 6, 6, CHG_NZVC, cpu6812 },
983
984 { "subd", OP_IMM16, 3, 0x83, 2, 2, CHG_NZVC, cpu6811|cpu6812 },
985 { "subd", OP_DIRECT, 2, 0x93, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
986 { "subd", OP_IND16, 3, 0xb3, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
987 { "subd", OP_IX, 2, 0xa3, 6, 6, CHG_NZVC, cpu6811 },
988 { "subd", OP_IY | OP_PAGE2, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811 },
989 { "subd", OP_IDX, 2, 0xa3, 3, 3, CHG_NZVC, cpu6812 },
990 { "subd", OP_IDX_1, 3, 0xa3, 3, 3, CHG_NZVC, cpu6812 },
991 { "subd", OP_IDX_2, 4, 0xa3, 4, 4, CHG_NZVC, cpu6812 },
992 { "subd", OP_D_IDX, 2, 0xa3, 6, 6, CHG_NZVC, cpu6812 },
993 { "subd", OP_D_IDX_2, 4, 0xa3, 6, 6, CHG_NZVC, cpu6812 },
994
995 { "swi", OP_NONE, 1, 0x3f, 9, 9, CHG_NONE, cpu6811|cpu6812 },
996
997 { "tab", OP_NONE, 1, 0x16, 2, 2, CLR_V_CHG_NZ, cpu6811 },
998 { "tab", OP_NONE | OP_PAGE2,2, 0x0e, 2, 2, CLR_V_CHG_NZ, cpu6812 },
999
1000 { "tap", OP_NONE, 1, 0x06, 2, 2, CHG_ALL, cpu6811 },
1001
1002 { "tba", OP_NONE, 1, 0x17, 2, 2, CLR_V_CHG_NZ, cpu6811 },
1003 { "tba", OP_NONE | OP_PAGE2,2, 0x0f, 2, 2, CLR_V_CHG_NZ, cpu6812 },
1004
1005 { "test", OP_NONE, 1, 0x00, 5, _M, CHG_NONE, cpu6811 },
1006
1007 { "tpa", OP_NONE, 1, 0x07, 2, 2, CHG_NONE, cpu6811 },
1008
1009 { "tbeq", OP_TBEQ_MARKER
1010 | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 },
1011
1012 { "tbl", OP_IDX | OP_PAGE2, 3, 0x3d, 8, 8, CHG_NZC, cpu6812 },
1013
1014 { "tbne", OP_TBNE_MARKER
1015 | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 },
1016
1017 { "tfr", OP_TFR_MARKER
1018 | OP_REG_1 | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812 },
1019
1020 { "trap", OP_IMM8 | OP_TRAP_ID, 2, 0x18, 11, 11, SET_I, cpu6812 },
1021
1022 { "tst", OP_IND16, 3, 0x7d, 6, 6, CLR_VC_CHG_NZ, cpu6811 },
1023 { "tst", OP_IX, 2, 0x6d, 6, 6, CLR_VC_CHG_NZ, cpu6811 },
1024 { "tst", OP_IY | OP_PAGE2, 3, 0x6d, 7, 7, CLR_VC_CHG_NZ, cpu6811 },
1025 { "tst", OP_IND16, 3, 0xf7, 3, 3, CLR_VC_CHG_NZ, cpu6812 },
1026 { "tst", OP_IDX, 2, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu6812 },
1027 { "tst", OP_IDX_1, 3, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu6812 },
1028 { "tst", OP_IDX_2, 4, 0xe7, 4, 4, CLR_VC_CHG_NZ, cpu6812 },
1029 { "tst", OP_D_IDX, 2, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu6812 },
1030 { "tst", OP_D_IDX_2, 4, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu6812 },
1031
1032 { "tsta", OP_NONE, 1, 0x4d, 2, 2, CLR_VC_CHG_NZ, cpu6811 },
1033 { "tsta", OP_NONE, 1, 0x97, 1, 1, CLR_VC_CHG_NZ, cpu6812 },
1034 { "tstb", OP_NONE, 1, 0x5d, 2, 2, CLR_VC_CHG_NZ, cpu6811 },
1035 { "tstb", OP_NONE, 1, 0xd7, 1, 1, CLR_VC_CHG_NZ, cpu6812 },
1036
1037 { "tsx", OP_NONE, 1, 0x30, 3, 3, CHG_NONE, cpu6811 },
1038 { "tsy", OP_NONE | OP_PAGE2,2, 0x30, 4, 4, CHG_NONE, cpu6811 },
1039 { "txs", OP_NONE, 1, 0x35, 3, 3, CHG_NONE, cpu6811 },
1040 { "tys", OP_NONE | OP_PAGE2,2, 0x35, 4, 4, CHG_NONE, cpu6811 },
1041
1042 { "wai", OP_NONE, 1, 0x3e, 5, _M, CHG_NONE, cpu6811|cpu6812 },
1043
1044 { "wav", OP_NONE | OP_PAGE2, 2, 0x3c, 8, _M, SET_Z_CHG_HNVC, cpu6812 },
1045
1046 { "xgdx", OP_NONE, 1, 0x8f, 3, 3, CHG_NONE, cpu6811 },
1047 { "xgdy", OP_NONE | OP_PAGE2,2, 0x8f, 4, 4, CHG_NONE, cpu6811 }
1048 };
1049
1050 const int m68hc11_num_opcodes = TABLE_SIZE (m68hc11_opcodes);
1051
1052 /* The following alias table provides source compatibility to
1053 move from 68HC11 assembly to 68HC12. */
1054 const struct m68hc12_opcode_alias m68hc12_alias[] = {
1055 { "abx", "leax b,x", 2, 0x1a, 0xe5 },
1056 { "aby", "leay b,y", 2, 0x19, 0xed },
1057 { "clc", "andcc #$fe", 2, 0x10, 0xfe },
1058 { "cli", "andcc #$ef", 2, 0x10, 0xef },
1059 { "clv", "andcc #$fd", 2, 0x10, 0xfd },
1060 { "des", "leas -1,sp", 2, 0x1b, 0x9f },
1061 { "ins", "leas 1,sp", 2, 0x1b, 0x81 },
1062 { "sec", "orcc #$01", 2, 0x14, 0x01 },
1063 { "sei", "orcc #$10", 2, 0x14, 0x10 },
1064 { "sev", "orcc #$02", 2, 0x14, 0x02 },
1065 { "tap", "tfr a,ccr", 2, 0xb7, 0x02 },
1066 { "tpa", "tfr ccr,a", 2, 0xb7, 0x20 },
1067 { "tsx", "tfr sp,x", 2, 0xb7, 0x75 },
1068 { "tsy", "tfr sp,y", 2, 0xb7, 0x76 },
1069 { "txs", "tfr x,sp", 2, 0xb7, 0x57 },
1070 { "tys", "tfr y,sp", 2, 0xb7, 0x67 },
1071 { "xgdx","exg d,x", 2, 0xb7, 0xc5 },
1072 { "xgdy","exg d,y", 2, 0xb7, 0xc6 }
1073 };
1074 const int m68hc12_num_alias = TABLE_SIZE (m68hc12_alias);
git-cvsimport of binutils cvsroot