opcodes/mcore-opc.h

   1 /* Assembler instructions for Motorola's Mcore processor
   2    Copyright (C) 1999, 2000 Free Software Foundation, Inc.
   3
   4
   5 This program is free software; you can redistribute it and/or modify
   6 it under the terms of the GNU General Public License as published by
   7 the Free Software Foundation; either version 2 of the License, or
   8 (at your option) any later version.
   9
  10 This program is distributed in the hope that it will be useful,
  11 but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 GNU General Public License for more details.
  14
  15 You should have received a copy of the GNU General Public License
  16 along with this program; if not, write to the Free Software
  17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  18
  19 #include "ansidecl.h"
  20
  21 typedef enum
  22 {
  23   O0,    OT,   O1,   OC,   O2,    X1,    OI,    OB,
  24   OMa,   SI,   I7,   LS,   BR,    BL,    LR,    LJ,
  25   RM,    RQ,   JSR,  JMP,  OBRa,  OBRb,  OBRc,  OBR2,
  26   O1R1,  OMb,  OMc,  SIa,
  27   MULSH, OPSR,
  28   JC,    JU,   JL,   RSI,  DO21,  OB2
  29 }
  30 mcore_opclass;
  31
  32 typedef struct inst
  33 {
  34   char *         name;
  35   mcore_opclass  opclass;
  36   unsigned char  transfer;
  37   unsigned short inst;
  38 }
  39 mcore_opcode_info;
  40
  41 #ifdef DEFINE_TABLE
  42 mcore_opcode_info mcore_table[] =
  43 {
  44   { "bkpt",     O0,     0,      0x0000 },
  45   { "sync",     O0,     0,      0x0001 },
  46   { "rte",      O0,     1,      0x0002 },
  47   { "rfe",      O0,     1,      0x0002 },
  48   { "rfi",      O0,     1,      0x0003 },
  49   { "stop",     O0,     0,      0x0004 },
  50   { "wait",     O0,     0,      0x0005 },
  51   { "doze",     O0,     0,      0x0006 },
  52   { "idly4",    O0,     0,      0x0007 },
  53   { "trap",     OT,     0,      0x0008 },
  54 /* SPACE:                       0x000C - 0x000F */
  55 /* SPACE:                       0x0010 - 0x001F */
  56   { "mvc",      O1,     0,      0x0020 },
  57   { "mvcv",     O1,     0,      0x0030 },
  58   { "ldq",      RQ,     0,      0x0040 },
  59   { "stq",      RQ,     0,      0x0050 },
  60   { "ldm",      RM,     0,      0x0060 },
  61   { "stm",      RM,     0,      0x0070 },
  62   { "dect",     O1,     0,      0x0080 },
  63   { "decf",     O1,     0,      0x0090 },
  64   { "inct",     O1,     0,      0x00A0 },
  65   { "incf",     O1,     0,      0x00B0 },
  66   { "jmp",      JMP,    2,      0x00C0 },
  67 #define MCORE_INST_JMP  0x00C0
  68   { "jsr",      JSR,    0,      0x00D0 },
  69 #define MCORE_INST_JSR  0x00E0
  70   { "ff1",      O1,     0,      0x00E0 },
  71   { "brev",     O1,     0,      0x00F0 },
  72   { "xtrb3",    X1,     0,      0x0100 },
  73   { "xtrb2",    X1,     0,      0x0110 },
  74   { "xtrb1",    X1,     0,      0x0120 },
  75   { "xtrb0",    X1,     0,      0x0130 },
  76   { "zextb",    O1,     0,      0x0140 },
  77   { "sextb",    O1,     0,      0x0150 },
  78   { "zexth",    O1,     0,      0x0160 },
  79   { "sexth",    O1,     0,      0x0170 },
  80   { "declt",    O1,     0,      0x0180 },
  81   { "tstnbz",   O1,     0,      0x0190 },
  82   { "decgt",    O1,     0,      0x01A0 },
  83   { "decne",    O1,     0,      0x01B0 },
  84   { "clrt",     O1,     0,      0x01C0 },
  85   { "clrf",     O1,     0,      0x01D0 },
  86   { "abs",      O1,     0,      0x01E0 },
  87   { "not",      O1,     0,      0x01F0 },
  88   { "movt",     O2,     0,      0x0200 },
  89   { "mult",     O2,     0,      0x0300 },
  90   { "loopt",    BL,     0,      0x0400 },
  91   { "subu",     O2,     0,      0x0500 },
  92   { "sub",      O2,     0,      0x0500 }, /* Official alias.  */
  93   { "addc",     O2,     0,      0x0600 },
  94   { "subc",     O2,     0,      0x0700 },
  95 /* SPACE: 0x0800-0x08ff for a diadic operation */
  96 /* SPACE: 0x0900-0x09ff for a diadic operation */
  97   { "movf",     O2,     0,      0x0A00 },
  98   { "lsr",      O2,     0,      0x0B00 },
  99   { "cmphs",    O2,     0,      0x0C00 },
 100   { "cmplt",    O2,     0,      0x0D00 },
 101   { "tst",      O2,     0,      0x0E00 },
 102   { "cmpne",    O2,     0,      0x0F00 },
 103   { "mfcr",     OC,     0,      0x1000 },
 104   { "psrclr",   OPSR,   0,      0x11F0 },
 105   { "psrset",   OPSR,   0,      0x11F8 },
 106   { "mov",      O2,     0,      0x1200 },
 107   { "bgenr",    O2,     0,      0x1300 },
 108   { "rsub",     O2,     0,      0x1400 },
 109   { "ixw",      O2,     0,      0x1500 },
 110   { "and",      O2,     0,      0x1600 },
 111   { "xor",      O2,     0,      0x1700 },
 112   { "mtcr",     OC,     0,      0x1800 },
 113   { "asr",      O2,     0,      0x1A00 },
 114   { "lsl",      O2,     0,      0x1B00 },
 115   { "addu",     O2,     0,      0x1C00 },
 116   { "add",      O2,     0,      0x1C00 }, /* Official alias.  */
 117   { "ixh",      O2,     0,      0x1D00 },
 118   { "or",       O2,     0,      0x1E00 },
 119   { "andn",     O2,     0,      0x1F00 },
 120   { "addi",     OI,     0,      0x2000 },
 121 #define MCORE_INST_ADDI 0x2000
 122   { "cmplti",   OI,     0,      0x2200 },
 123   { "subi",     OI,     0,      0x2400 },
 124 /* SPACE: 0x2600-0x27ff open for a register+immediate  operation */
 125   { "rsubi",    OB,     0,      0x2800 },
 126   { "cmpnei",   OB,     0,      0x2A00 },
 127   { "bmaski",   OMa,    0,      0x2C00 },
 128   { "divu",     O1R1,   0,      0x2C10 },
 129 /* SPACE:                       0x2c20 - 0x2c7f */
 130   { "bmaski",   OMb,    0,      0x2C80 },
 131   { "bmaski",   OMc,    0,      0x2D00 },
 132   { "andi",     OB,     0,      0x2E00 },
 133   { "bclri",    OB,     0,      0x3000 },
 134 /* SPACE:                       0x3200 - 0x320f */
 135   { "divs",     O1R1,   0,      0x3210 },
 136 /* SPACE:                       0x3220 - 0x326f */
 137   { "bgeni",    OBRa,   0,      0x3270 },
 138   { "bgeni",    OBRb,   0,      0x3280 },
 139   { "bgeni",    OBRc,   0,      0x3300 },
 140   { "bseti",    OB,     0,      0x3400 },
 141   { "btsti",    OB,     0,      0x3600 },
 142   { "xsr",      O1,     0,      0x3800 },
 143   { "rotli",    SIa,    0,      0x3800 },
 144   { "asrc",     O1,     0,      0x3A00 },
 145   { "asri",     SIa,    0,      0x3A00 },
 146   { "lslc",     O1,     0,      0x3C00 },
 147   { "lsli",     SIa,    0,      0x3C00 },
 148   { "lsrc",     O1,     0,      0x3E00 },
 149   { "lsri",     SIa,    0,      0x3E00 },
 150 /* SPACE:                       0x4000 - 0x5fff */
 151   { "movi",     I7,     0,      0x6000 },
 152 #define MCORE_INST_BMASKI_ALT   0x6000
 153 #define MCORE_INST_BGENI_ALT    0x6000
 154   { "mulsh",    MULSH,  0,      0x6800 },
 155   { "muls.h",   MULSH,  0,      0x6800 },
 156 /* SPACE:                       0x6900 - 0x6FFF */
 157   { "jmpi",     LJ,     1,      0x7000 },
 158   { "jsri",     LJ,     0,      0x7F00 },
 159 #define MCORE_INST_JMPI 0x7000
 160   { "lrw",      LR,     0,      0x7000 },
 161 #define MCORE_INST_JSRI 0x7F00
 162   { "ld",       LS,     0,      0x8000 },
 163   { "ldw",      LS,     0,      0x8000 },
 164   { "ld.w",     LS,     0,      0x8000 },
 165   { "st",       LS,     0,      0x9000 },
 166   { "stw",      LS,     0,      0x9000 },
 167   { "st.w",     LS,     0,      0x9000 },
 168   { "ldb",      LS,     0,      0xA000 },
 169   { "ld.b",     LS,     0,      0xA000 },
 170   { "stb",      LS,     0,      0xB000 },
 171   { "st.b",     LS,     0,      0xB000 },
 172   { "ldh",      LS,     0,      0xC000 },
 173   { "ld.h",     LS,     0,      0xC000 },
 174   { "sth",      LS,     0,      0xD000 },
 175   { "st.h",     LS,     0,      0xD000 },
 176   { "bt",       BR,     0,      0xE000 },
 177   { "bf",       BR,     0,      0xE800 },
 178   { "br",       BR,     1,      0xF000 },
 179 #define MCORE_INST_BR   0xF000
 180   { "bsr",      BR,     0,      0xF800 },
 181 #define MCORE_INST_BSR  0xF800
 182
 183 /* The following are relaxable branches */
 184   { "jbt",      JC,     0,      0xE000 },
 185   { "jbf",      JC,     0,      0xE800 },
 186   { "jbr",      JU,     1,      0xF000 },
 187   { "jbsr",     JL,     0,      0xF800 },
 188
 189 /* The following are aliases for other instructions */
 190   { "rts",      O0,     2,      0x00CF },  /* jmp r15 */
 191   { "rolc",     DO21,   0,      0x0600 },  /* addc rd,rd */
 192   { "rotlc",    DO21,   0,      0x0600 },  /* addc rd,rd */
 193   { "setc",     O0,     0,      0x0C00 },  /* cmphs r0,r0 */
 194   { "clrc",     O0,     0,      0x0F00 },  /* cmpne r0,r0 */
 195   { "tstle",    O1,     0,      0x2200 },  /* cmplti rd,1 */
 196   { "cmplei",   OB,     0,      0x2200 },  /* cmplei rd,X -> cmplti rd,X+1 */
 197   { "neg",      O1,     0,      0x2800 },  /* rsubi rd,0 */
 198   { "tstne",    O1,     0,      0x2A00 },  /* cmpnei rd,0 */
 199   { "tstlt",    O1,     0,      0x37F0 },  /* btsti rx,31 */
 200   { "mclri",    OB2,    0,      0x3000 },  /* bclri rx,log2(imm) */
 201   { "mgeni",    OBR2,   0,      0x3200 },  /* bgeni rx,log2(imm) */
 202   { "mseti",    OB2,    0,      0x3400 },  /* bseti rx,log2(imm) */
 203   { "mtsti",    OB2,    0,      0x3600 },  /* btsti rx,log2(imm) */
 204   { "rori",     RSI,    0,      0x3800 },
 205   { "rotri",    RSI,    0,      0x3800 },
 206   { "nop",      O0,     0,      0x1200 },  /* mov r0, r0 */
 207   { 0,          0,      0,      0 }
 208 };
 209 #endif