opcodes/mips16-opc.c

   1 /* mips16-opc.c.  Mips16 opcode table.
   2    Copyright 1996, 1997 Free Software Foundation, Inc.
   3    Contributed by Ian Lance Taylor, Cygnus Support
   4
   5 This file is part of GDB, GAS, and the GNU binutils.
   6
   7 GDB, GAS, and the GNU binutils are free software; you can redistribute
   8 them and/or modify them under the terms of the GNU General Public
   9 License as published by the Free Software Foundation; either version
  10 1, or (at your option) any later version.
  11
  12 GDB, GAS, and the GNU binutils are distributed in the hope that they
  13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15 the GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this file; see the file COPYING.  If not, write to the Free
  19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  20 02111-1307, USA.  */
  21
  22 #include <stdio.h>
  23 #include "sysdep.h"
  24 #include "opcode/mips.h"
  25
  26 /* This is the opcodes table for the mips16 processor.  The format of
  27    this table is intentionally identical to the one in mips-opc.c.
  28    However, the special letters that appear in the argument string are
  29    different, and the table uses some different flags.  */
  30
  31 /* Use some short hand macros to keep down the length of the lines in
  32    the opcodes table.  */
  33
  34 #define UBD     INSN_UNCOND_BRANCH_DELAY
  35 #define BR      MIPS16_INSN_BRANCH
  36
  37 #define WR_x    MIPS16_INSN_WRITE_X
  38 #define WR_y    MIPS16_INSN_WRITE_Y
  39 #define WR_z    MIPS16_INSN_WRITE_Z
  40 #define WR_T    MIPS16_INSN_WRITE_T
  41 #define WR_SP   MIPS16_INSN_WRITE_SP
  42 #define WR_31   MIPS16_INSN_WRITE_31
  43 #define WR_Y    MIPS16_INSN_WRITE_GPR_Y
  44
  45 #define RD_x    MIPS16_INSN_READ_X
  46 #define RD_y    MIPS16_INSN_READ_Y
  47 #define RD_Z    MIPS16_INSN_READ_Z
  48 #define RD_T    MIPS16_INSN_READ_T
  49 #define RD_SP   MIPS16_INSN_READ_SP
  50 #define RD_31   MIPS16_INSN_READ_31
  51 #define RD_PC   MIPS16_INSN_READ_PC
  52 #define RD_X    MIPS16_INSN_READ_GPR_X
  53
  54 #define WR_HI   INSN_WRITE_HI
  55 #define WR_LO   INSN_WRITE_LO
  56 #define RD_HI   INSN_READ_HI
  57 #define RD_LO   INSN_READ_LO
  58
  59 #define TRAP    INSN_TRAP
  60
  61 #define I3      INSN_ISA3
  62
  63 #define T3      INSN_3900
  64
  65 const struct mips_opcode mips16_opcodes[] = {
  66 {"nop",     "",         0x6500, 0xffff, RD_Z }, /* move $0,$Z */
  67 {"la",      "x,A",      0x0800, 0xf800, WR_x|RD_PC },
  68 {"abs",     "x,w",      0, (int) M_ABS, INSN_MACRO },
  69 {"addiu",   "y,x,4",    0x4000, 0xf810, WR_y|RD_x },
  70 {"addiu",   "x,k",      0x4800, 0xf800, WR_x|RD_x },
  71 {"addiu",   "S,K",      0x6300, 0xff00, WR_SP|RD_SP },
  72 {"addiu",   "S,S,K",    0x6300, 0xff00, WR_SP|RD_SP },
  73 {"addiu",   "x,P,V",    0x0800, 0xf800, WR_x|RD_PC },
  74 {"addiu",   "x,S,V",    0x0000, 0xf800, WR_x|RD_SP },
  75 {"addu",    "z,v,y",    0xe001, 0xf803, WR_z|RD_x|RD_y },
  76 {"addu",    "y,x,4",    0x4000, 0xf810, WR_y|RD_x },
  77 {"addu",    "x,k",      0x4800, 0xf800, WR_x|RD_x },
  78 {"addu",    "S,K",      0x6300, 0xff00, WR_SP|RD_SP },
  79 {"addu",    "S,S,K",    0x6300, 0xff00, WR_SP|RD_SP },
  80 {"addu",    "x,P,V",    0x0800, 0xf800, WR_x|RD_PC },
  81 {"addu",    "x,S,V",    0x0000, 0xf800, WR_x|RD_SP },
  82 {"and",     "x,y",      0xe80c, 0xf81f, WR_x|RD_x|RD_y },
  83 {"b",       "q",        0x1000, 0xf800, BR},
  84 {"beq",     "x,y,p",    0, (int) M_BEQ, INSN_MACRO },
  85 {"beq",     "x,U,p",    0, (int) M_BEQ_I, INSN_MACRO },
  86 {"beqz",    "x,p",      0x2000, 0xf800, BR|RD_x },
  87 {"bge",     "x,y,p",    0, (int) M_BGE, INSN_MACRO },
  88 {"bge",     "x,8,p",    0, (int) M_BGE_I, INSN_MACRO },
  89 {"bgeu",    "x,y,p",    0, (int) M_BGEU, INSN_MACRO },
  90 {"bgeu",    "x,8,p",    0, (int) M_BGEU_I, INSN_MACRO },
  91 {"bgt",     "x,y,p",    0, (int) M_BGT, INSN_MACRO },
  92 {"bgt",     "x,8,p",    0, (int) M_BGT_I, INSN_MACRO },
  93 {"bgtu",    "x,y,p",    0, (int) M_BGTU, INSN_MACRO },
  94 {"bgtu",    "x,8,p",    0, (int) M_BGTU_I, INSN_MACRO },
  95 {"ble",     "x,y,p",    0, (int) M_BLE, INSN_MACRO },
  96 {"ble",     "x,8,p",    0, (int) M_BLE_I, INSN_MACRO },
  97 {"bleu",    "x,y,p",    0, (int) M_BLEU, INSN_MACRO },
  98 {"bleu",    "x,8,p",    0, (int) M_BLEU_I, INSN_MACRO },
  99 {"blt",     "x,y,p",    0, (int) M_BLT, INSN_MACRO },
 100 {"blt",     "x,8,p",    0, (int) M_BLT_I, INSN_MACRO },
 101 {"bltu",    "x,y,p",    0, (int) M_BLTU, INSN_MACRO },
 102 {"bltu",    "x,8,p",    0, (int) M_BLTU_I, INSN_MACRO },
 103 {"bne",     "x,y,p",    0, (int) M_BNE, INSN_MACRO },
 104 {"bne",     "x,U,p",    0, (int) M_BNE_I, INSN_MACRO },
 105 {"bnez",    "x,p",      0x2800, 0xf800, BR|RD_x },
 106 {"break",   "6",        0xe805, 0xf81f, TRAP },
 107 {"bteqz",   "p",        0x6000, 0xff00, BR|RD_T },
 108 {"btnez",   "p",        0x6100, 0xff00, BR|RD_T },
 109 {"cmpi",    "x,U",      0x7000, 0xf800, WR_T|RD_x },
 110 {"cmp",     "x,y",      0xe80a, 0xf81f, WR_T|RD_x|RD_y },
 111 {"cmp",     "x,U",      0x7000, 0xf800, WR_T|RD_x },
 112 {"dla",     "y,E",      0xfe00, 0xff00, WR_y|RD_PC, I3 },
 113 {"daddiu",  "y,x,4",    0x4010, 0xf810, WR_y|RD_x, I3 },
 114 {"daddiu",  "y,j",      0xfd00, 0xff00, WR_y|RD_y, I3 },
 115 {"daddiu",  "S,K",      0xfb00, 0xff00, WR_SP|RD_SP, I3 },
 116 {"daddiu",  "S,S,K",    0xfb00, 0xff00, WR_SP|RD_SP, I3 },
 117 {"daddiu",  "y,P,W",    0xfe00, 0xff00, WR_y|RD_PC, I3 },
 118 {"daddiu",  "y,S,W",    0xff00, 0xff00, WR_y|RD_SP, I3 },
 119 {"daddu",   "z,v,y",    0xe000, 0xf803, WR_z|RD_x|RD_y, I3 },
 120 {"daddu",   "y,x,4",    0x4010, 0xf810, WR_y|RD_x, I3 },
 121 {"daddu",   "y,j",      0xfd00, 0xff00, WR_y|RD_y, I3 },
 122 {"daddu",   "S,K",      0xfb00, 0xff00, WR_SP|RD_SP, I3 },
 123 {"daddu",   "S,S,K",    0xfb00, 0xff00, WR_SP|RD_SP, I3 },
 124 {"daddu",   "y,P,W",    0xfe00, 0xff00, WR_y|RD_PC, I3 },
 125 {"daddu",   "y,S,W",    0xff00, 0xff00, WR_y|RD_SP, I3 },
 126 {"ddiv",    "0,x,y",    0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 },
 127 {"ddiv",    "z,v,y",    0, (int) M_DDIV_3, INSN_MACRO },
 128 {"ddivu",   "0,x,y",    0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 },
 129 {"ddivu",   "z,v,y",    0, (int) M_DDIVU_3, INSN_MACRO },
 130 {"div",     "0,x,y",    0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO },
 131 {"div",     "z,v,y",    0, (int) M_DIV_3, INSN_MACRO },
 132 {"divu",    "0,x,y",    0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO },
 133 {"divu",    "z,v,y",    0, (int) M_DIVU_3, INSN_MACRO },
 134 {"dmul",    "z,v,y",    0, (int) M_DMUL, INSN_MACRO, I3 },
 135 {"dmult",   "x,y",      0xe81c, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 },
 136 {"dmultu",  "x,y",      0xe81d, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 },
 137 {"drem",    "0,x,y",    0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 },
 138 {"drem",    "z,v,y",    0, (int) M_DREM_3, INSN_MACRO },
 139 {"dremu",   "0,x,y",    0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 },
 140 {"dremu",   "z,v,y",    0, (int) M_DREMU_3, INSN_MACRO },
 141 {"dsllv",   "y,x",      0xe814, 0xf81f, WR_y|RD_y|RD_x, I3 },
 142 {"dsll",    "x,w,[",    0x3001, 0xf803, WR_x|RD_y, I3 },
 143 {"dsll",    "y,x",      0xe814, 0xf81f, WR_y|RD_y|RD_x, I3 },
 144 {"dsrav",   "y,x",      0xe817, 0xf81f, WR_y|RD_y|RD_x, I3 },
 145 {"dsra",    "y,]",      0xe813, 0xf81f, WR_y|RD_y, I3 },
 146 {"dsra",    "y,x",      0xe817, 0xf81f, WR_y|RD_y|RD_x, I3 },
 147 {"dsrlv",   "y,x",      0xe816, 0xf81f, WR_y|RD_y|RD_x, I3 },
 148 {"dsrl",    "y,]",      0xe808, 0xf81f, WR_y|RD_y, I3 },
 149 {"dsrl",    "y,x",      0xe816, 0xf81f, WR_y|RD_y|RD_x, I3 },
 150 {"dsubu",   "z,v,y",    0xe002, 0xf803, WR_z|RD_x|RD_y, I3 },
 151 {"dsubu",   "y,x,4",    0, (int) M_DSUBU_I, INSN_MACRO },
 152 {"dsubu",   "y,j",      0, (int) M_DSUBU_I_2, INSN_MACRO },
 153 {"exit",    "L",        0xed09, 0xff1f, TRAP },
 154 {"exit",    "L",        0xee09, 0xff1f, TRAP },
 155 {"exit",    "L",        0xef09, 0xff1f, TRAP },
 156 {"entry",   "l",        0xe809, 0xf81f, TRAP },
 157 {"extend",  "e",        0xf000, 0xf800, 0 },
 158 {"jalr",    "x",        0xe840, 0xf8ff, UBD|WR_31|RD_x },
 159 {"jalr",    "R,x",      0xe840, 0xf8ff, UBD|WR_31|RD_x },
 160 {"jal",     "x",        0xe840, 0xf8ff, UBD|WR_31|RD_x },
 161 {"jal",     "R,x",      0xe840, 0xf8ff, UBD|WR_31|RD_x },
 162 {"jal",     "a",        0x1800, 0xfc00, UBD|WR_31 },
 163 {"jalx",    "a",        0x1c00, 0xfc00, UBD|WR_31 },
 164 {"jr",      "x",        0xe800, 0xf8ff, UBD|RD_x },
 165 {"jr",      "R",        0xe820, 0xffff, UBD|RD_31 },
 166 {"j",       "x",        0xe800, 0xf8ff, UBD|RD_x },
 167 {"j",       "R",        0xe820, 0xffff, UBD|RD_31 },
 168 {"lb",      "y,5(x)",   0x8000, 0xf800, WR_y|RD_x },
 169 {"lbu",     "y,5(x)",   0xa000, 0xf800, WR_y|RD_x },
 170 {"ld",      "y,D(x)",   0x3800, 0xf800, WR_y|RD_x, I3 },
 171 {"ld",      "y,B",      0xfc00, 0xff00, WR_y|RD_PC, I3 },
 172 {"ld",      "y,D(P)",   0xfc00, 0xff00, WR_y|RD_PC, I3 },
 173 {"ld",      "y,D(S)",   0xf800, 0xff00, WR_y|RD_SP, I3 },
 174 {"lh",      "y,H(x)",   0x8800, 0xf800, WR_y|RD_x },
 175 {"lhu",     "y,H(x)",   0xa800, 0xf800, WR_y|RD_x },
 176 {"li",      "x,U",      0x6800, 0xf800, WR_x },
 177 {"lw",      "y,W(x)",   0x9800, 0xf800, WR_y|RD_x },
 178 {"lw",      "x,A",      0xb000, 0xf800, WR_x|RD_PC },
 179 {"lw",      "x,V(P)",   0xb000, 0xf800, WR_x|RD_PC },
 180 {"lw",      "x,V(S)",   0x9000, 0xf800, WR_x|RD_SP },
 181 {"lwu",     "y,W(x)",   0xb800, 0xf800, WR_y|RD_x, I3 },
 182 {"mfhi",    "x",        0xe810, 0xf8ff, WR_x|RD_HI },
 183 {"mflo",    "x",        0xe812, 0xf8ff, WR_x|RD_LO },
 184 {"move",    "y,X",      0x6700, 0xff00, WR_y|RD_X },
 185 {"move",    "Y,Z",      0x6500, 0xff00, WR_Y|RD_Z },
 186 {"mul",     "z,v,y",    0, (int) M_MUL, INSN_MACRO },
 187 {"mult",    "x,y",      0xe818, 0xf81f, RD_x|RD_y|WR_HI|WR_LO },
 188 {"multu",   "x,y",      0xe819, 0xf81f, RD_x|RD_y|WR_HI|WR_LO },
 189 {"neg",     "x,w",      0xe80b, 0xf81f, WR_x|RD_y },
 190 {"not",     "x,w",      0xe80f, 0xf81f, WR_x|RD_y },
 191 {"or",      "x,y",      0xe80d, 0xf81f, WR_x|RD_x|RD_y },
 192 {"rem",     "0,x,y",    0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO },
 193 {"rem",     "z,v,y",    0, (int) M_REM_3, INSN_MACRO },
 194 {"remu",    "0,x,y",    0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO },
 195 {"remu",    "z,v,y",    0, (int) M_REMU_3, INSN_MACRO },
 196 {"sb",      "y,5(x)",   0xc000, 0xf800, RD_y|RD_x },
 197 {"sd",      "y,D(x)",   0x7800, 0xf800, RD_y|RD_x, I3 },
 198 {"sd",      "y,D(S)",   0xf900, 0xff00, RD_y|RD_PC, I3 },
 199 {"sd",      "R,C(S)",   0xfa00, 0xff00, RD_31|RD_PC },
 200 {"sh",      "y,H(x)",   0xc800, 0xf800, RD_y|RD_x },
 201 {"sllv",    "y,x",      0xe804, 0xf81f, WR_y|RD_y|RD_x },
 202 {"sll",     "x,w,<",    0x3000, 0xf803, WR_x|RD_y },
 203 {"sll",     "y,x",      0xe804, 0xf81f, WR_y|RD_y|RD_x },
 204 {"slti",    "x,8",      0x5000, 0xf800, WR_T|RD_x },
 205 {"slt",     "x,y",      0xe802, 0xf81f, WR_T|RD_x|RD_y },
 206 {"slt",     "x,8",      0x5000, 0xf800, WR_T|RD_x },
 207 {"sltiu",   "x,8",      0x5800, 0xf800, WR_T|RD_x },
 208 {"sltu",    "x,y",      0xe803, 0xf81f, WR_T|RD_x|RD_y },
 209 {"sltu",    "x,8",      0x5800, 0xf800, WR_T|RD_x },
 210 {"srav",    "y,x",      0xe807, 0xf81f, WR_y|RD_y|RD_x },
 211 {"sra",     "x,w,<",    0x3003, 0xf803, WR_x|RD_y },
 212 {"sra",     "y,x",      0xe807, 0xf81f, WR_y|RD_y|RD_x },
 213 {"srlv",    "y,x",      0xe806, 0xf81f, WR_y|RD_y|RD_x },
 214 {"srl",     "x,w,<",    0x3002, 0xf803, WR_x|RD_y },
 215 {"srl",     "y,x",      0xe806, 0xf81f, WR_y|RD_y|RD_x },
 216 {"subu",    "z,v,y",    0xe003, 0xf803, WR_z|RD_x|RD_y },
 217 {"subu",    "y,x,4",    0, (int) M_SUBU_I, INSN_MACRO },
 218 {"subu",    "x,k",      0, (int) M_SUBU_I_2, INSN_MACRO },
 219 {"sw",      "y,W(x)",   0xd800, 0xf800, RD_y|RD_x },
 220 {"sw",      "x,V(S)",   0xd000, 0xf800, RD_x|RD_SP },
 221 {"sw",      "R,V(S)",   0x6200, 0xff00, RD_31|RD_SP },
 222 {"xor",     "x,y",      0xe80e, 0xf81f, WR_x|RD_x|RD_y },
 223 };
 224
 225 const int bfd_mips16_num_opcodes =
 226   ((sizeof mips16_opcodes) / (sizeof (mips16_opcodes[0])));