include/opcode/avr.h

   1 /* Opcode table for the Atmel AVR micro controllers.
   2
   3    Copyright 2000, 2001, 2004, 2006, 2008 Free Software Foundation, Inc.
   4    Contributed by Denis Chertykov <denisc@overta.ru>
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 2, or (at your option)
   9    any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
  19
  20 #define AVR_ISA_1200  0x0001 /* In the beginning there was ...  */
  21 #define AVR_ISA_LPM   0x0002 /* device has LPM */
  22 #define AVR_ISA_LPMX  0x0004 /* device has LPM Rd,Z[+] */
  23 #define AVR_ISA_SRAM  0x0008 /* device has SRAM (LD, ST, PUSH, POP, ...) */
  24 #define AVR_ISA_MEGA  0x0020 /* device has >8K program memory (JMP and CALL
  25                                 supported, no 8K wrap on RJMP and RCALL) */
  26 #define AVR_ISA_MUL   0x0040 /* device has new core (MUL, FMUL, ...) */
  27 #define AVR_ISA_ELPM  0x0080 /* device has >64K program memory (ELPM) */
  28 #define AVR_ISA_ELPMX 0x0100 /* device has ELPM Rd,Z[+] */
  29 #define AVR_ISA_SPM   0x0200 /* device can program itself */
  30 #define AVR_ISA_BRK   0x0400 /* device has BREAK (on-chip debug) */
  31 #define AVR_ISA_EIND  0x0800 /* device has >128K program memory (none yet) */
  32 #define AVR_ISA_MOVW  0x1000 /* device has MOVW */
  33
  34 #define AVR_ISA_TINY1 (AVR_ISA_1200 | AVR_ISA_LPM)
  35 #define AVR_ISA_PWMx  (AVR_ISA_M8   | AVR_ISA_BRK)
  36 #define AVR_ISA_2xxx  (AVR_ISA_TINY1 | AVR_ISA_SRAM)
  37 /* For the attiny26 which is missing LPM Rd,Z+.  */
  38 #define AVR_ISA_2xxe  (AVR_ISA_2xxx | AVR_ISA_LPMX)
  39 #define AVR_ISA_RF401 (AVR_ISA_2xxx | AVR_ISA_MOVW | AVR_ISA_LPMX)
  40 #define AVR_ISA_TINY2 (AVR_ISA_2xxx | AVR_ISA_MOVW | AVR_ISA_LPMX | \
  41                        AVR_ISA_SPM  | AVR_ISA_BRK)
  42 #define AVR_ISA_M8    (AVR_ISA_2xxx | AVR_ISA_MUL | AVR_ISA_MOVW | \
  43                        AVR_ISA_LPMX | AVR_ISA_SPM)
  44 #define AVR_ISA_M603  (AVR_ISA_2xxx | AVR_ISA_MEGA)
  45 #define AVR_ISA_M103  (AVR_ISA_M603 | AVR_ISA_ELPM)
  46 #define AVR_ISA_USB162 (AVR_ISA_M603 | AVR_ISA_MOVW | \
  47                        AVR_ISA_LPMX | AVR_ISA_SPM)
  48 #define AVR_ISA_AVR3 (AVR_ISA_M603 | AVR_ISA_MOVW | \
  49                        AVR_ISA_LPMX | AVR_ISA_SPM  | AVR_ISA_ELPM)
  50 #define AVR_ISA_M161  (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_MOVW | \
  51                        AVR_ISA_LPMX | AVR_ISA_SPM)
  52 #define AVR_ISA_94K   (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_MOVW | AVR_ISA_LPMX)
  53 #define AVR_ISA_M323  (AVR_ISA_M161 | AVR_ISA_BRK)
  54 #define AVR_ISA_M128  (AVR_ISA_M323 | AVR_ISA_ELPM | AVR_ISA_ELPMX)
  55
  56 #define AVR_ISA_ALL   0xFFFF
  57
  58 #define REGISTER_P(x) ((x) == 'r'               \
  59                        || (x) == 'd'            \
  60                        || (x) == 'w'            \
  61                        || (x) == 'a'            \
  62                        || (x) == 'v')
  63
  64 /* Undefined combination of operands - does the register
  65    operand overlap with pre-decremented or post-incremented
  66    pointer register (like ld r31,Z+)?  */
  67 #define AVR_UNDEF_P(x) (((x) & 0xFFED) == 0x91E5 ||             \
  68   ((x) & 0xFDEF) == 0x91AD || ((x) & 0xFDEF) == 0x91AE ||       \
  69   ((x) & 0xFDEF) == 0x91C9 || ((x) & 0xFDEF) == 0x91CA ||       \
  70   ((x) & 0xFDEF) == 0x91E1 || ((x) & 0xFDEF) == 0x91E2)
  71
  72 /* Is this a skip instruction {cpse,sbic,sbis,sbrc,sbrs}?  */
  73 #define AVR_SKIP_P(x) (((x) & 0xFC00) == 0x1000 ||              \
  74   ((x) & 0xFD00) == 0x9900 || ((x) & 0xFC08) == 0xFC00)
  75
  76 /* Is this `ldd r,b+0' or `std b+0,r' (b={Y,Z}, disassembled as
  77    `ld r,b' or `st b,r' respectively - next opcode entry)?  */
  78 #define AVR_DISP0_P(x) (((x) & 0xFC07) == 0x8000)
  79
  80 /* constraint letters
  81    r - any register
  82    d - `ldi' register (r16-r31)
  83    v - `movw' even register (r0, r2, ..., r28, r30)
  84    a - `fmul' register (r16-r23)
  85    w - `adiw' register (r24,r26,r28,r30)
  86    e - pointer registers (X,Y,Z)
  87    b - base pointer register and displacement ([YZ]+disp)
  88    z - Z pointer register (for [e]lpm Rd,Z[+])
  89    M - immediate value from 0 to 255
  90    n - immediate value from 0 to 255 ( n = ~M ). Relocation impossible
  91    s - immediate value from 0 to 7
  92    P - Port address value from 0 to 63. (in, out)
  93    p - Port address value from 0 to 31. (cbi, sbi, sbic, sbis)
  94    K - immediate value from 0 to 63 (used in `adiw', `sbiw')
  95    i - immediate value
  96    l - signed pc relative offset from -64 to 63
  97    L - signed pc relative offset from -2048 to 2047
  98    h - absolute code address (call, jmp)
  99    S - immediate value from 0 to 7 (S = s << 4)
 100    ? - use this opcode entry if no parameters, else use next opcode entry
 101
 102    Order is important - some binary opcodes have more than one name,
 103    the disassembler will only see the first match.
 104
 105    Remaining undefined opcodes (1699 total - some of them might work
 106    as normal instructions if not all of the bits are decoded):
 107
 108     0x0001...0x00ff    (255) (known to be decoded as `nop' by the old core)
 109    "100100xxxxxxx011"  (128) 0x9[0-3][0-9a-f][3b]
 110    "100100xxxxxx1000"   (64) 0x9[0-3][0-9a-f]8
 111    "1001001xxxxx01xx"  (128) 0x9[23][0-9a-f][4-7]
 112    "1001010xxxxx0100"   (32) 0x9[45][0-9a-f]4
 113    "1001010x001x1001"    (4) 0x9[45][23]9
 114    "1001010x01xx1001"    (8) 0x9[45][4-7]9
 115    "1001010x1xxx1001"   (16) 0x9[45][8-9a-f]9
 116    "1001010xxxxx1011"   (32) 0x9[45][0-9a-f]b
 117    "10010101001x1000"    (2) 0x95[23]8
 118    "1001010101xx1000"    (4) 0x95[4-7]8
 119    "1001010110111000"    (1) 0x95b8
 120    "1001010111111000"    (1) 0x95f8 (`espm' removed in databook update)
 121    "11111xxxxxxx1xxx" (1024) 0xf[8-9a-f][0-9a-f][8-9a-f]
 122  */
 123
 124 AVR_INSN (clc,  "",    "1001010010001000", 1, AVR_ISA_1200, 0x9488)
 125 AVR_INSN (clh,  "",    "1001010011011000", 1, AVR_ISA_1200, 0x94d8)
 126 AVR_INSN (cli,  "",    "1001010011111000", 1, AVR_ISA_1200, 0x94f8)
 127 AVR_INSN (cln,  "",    "1001010010101000", 1, AVR_ISA_1200, 0x94a8)
 128 AVR_INSN (cls,  "",    "1001010011001000", 1, AVR_ISA_1200, 0x94c8)
 129 AVR_INSN (clt,  "",    "1001010011101000", 1, AVR_ISA_1200, 0x94e8)
 130 AVR_INSN (clv,  "",    "1001010010111000", 1, AVR_ISA_1200, 0x94b8)
 131 AVR_INSN (clz,  "",    "1001010010011000", 1, AVR_ISA_1200, 0x9498)
 132
 133 AVR_INSN (sec,  "",    "1001010000001000", 1, AVR_ISA_1200, 0x9408)
 134 AVR_INSN (seh,  "",    "1001010001011000", 1, AVR_ISA_1200, 0x9458)
 135 AVR_INSN (sei,  "",    "1001010001111000", 1, AVR_ISA_1200, 0x9478)
 136 AVR_INSN (sen,  "",    "1001010000101000", 1, AVR_ISA_1200, 0x9428)
 137 AVR_INSN (ses,  "",    "1001010001001000", 1, AVR_ISA_1200, 0x9448)
 138 AVR_INSN (set,  "",    "1001010001101000", 1, AVR_ISA_1200, 0x9468)
 139 AVR_INSN (sev,  "",    "1001010000111000", 1, AVR_ISA_1200, 0x9438)
 140 AVR_INSN (sez,  "",    "1001010000011000", 1, AVR_ISA_1200, 0x9418)
 141
 142    /* Same as {cl,se}[chinstvz] above.  */
 143 AVR_INSN (bclr, "S",   "100101001SSS1000", 1, AVR_ISA_1200, 0x9488)
 144 AVR_INSN (bset, "S",   "100101000SSS1000", 1, AVR_ISA_1200, 0x9408)
 145
 146 AVR_INSN (icall,"",    "1001010100001001", 1, AVR_ISA_2xxx, 0x9509)
 147 AVR_INSN (ijmp, "",    "1001010000001001", 1, AVR_ISA_2xxx, 0x9409)
 148
 149 AVR_INSN (lpm,  "?",   "1001010111001000", 1, AVR_ISA_TINY1,0x95c8)
 150 AVR_INSN (lpm,  "r,z", "1001000ddddd010+", 1, AVR_ISA_LPMX, 0x9004)
 151 AVR_INSN (elpm, "?",   "1001010111011000", 1, AVR_ISA_ELPM, 0x95d8)
 152 AVR_INSN (elpm, "r,z", "1001000ddddd011+", 1, AVR_ISA_ELPMX,0x9006)
 153
 154 AVR_INSN (nop,  "",    "0000000000000000", 1, AVR_ISA_1200, 0x0000)
 155 AVR_INSN (ret,  "",    "1001010100001000", 1, AVR_ISA_1200, 0x9508)
 156 AVR_INSN (reti, "",    "1001010100011000", 1, AVR_ISA_1200, 0x9518)
 157 AVR_INSN (sleep,"",    "1001010110001000", 1, AVR_ISA_1200, 0x9588)
 158 AVR_INSN (break,"",    "1001010110011000", 1, AVR_ISA_BRK,  0x9598)
 159 AVR_INSN (wdr,  "",    "1001010110101000", 1, AVR_ISA_1200, 0x95a8)
 160 AVR_INSN (spm,  "",    "1001010111101000", 1, AVR_ISA_SPM,  0x95e8)
 161
 162 AVR_INSN (adc,  "r,r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00)
 163 AVR_INSN (add,  "r,r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00)
 164 AVR_INSN (and,  "r,r", "001000rdddddrrrr", 1, AVR_ISA_1200, 0x2000)
 165 AVR_INSN (cp,   "r,r", "000101rdddddrrrr", 1, AVR_ISA_1200, 0x1400)
 166 AVR_INSN (cpc,  "r,r", "000001rdddddrrrr", 1, AVR_ISA_1200, 0x0400)
 167 AVR_INSN (cpse, "r,r", "000100rdddddrrrr", 1, AVR_ISA_1200, 0x1000)
 168 AVR_INSN (eor,  "r,r", "001001rdddddrrrr", 1, AVR_ISA_1200, 0x2400)
 169 AVR_INSN (mov,  "r,r", "001011rdddddrrrr", 1, AVR_ISA_1200, 0x2c00)
 170 AVR_INSN (mul,  "r,r", "100111rdddddrrrr", 1, AVR_ISA_MUL,  0x9c00)
 171 AVR_INSN (or,   "r,r", "001010rdddddrrrr", 1, AVR_ISA_1200, 0x2800)
 172 AVR_INSN (sbc,  "r,r", "000010rdddddrrrr", 1, AVR_ISA_1200, 0x0800)
 173 AVR_INSN (sub,  "r,r", "000110rdddddrrrr", 1, AVR_ISA_1200, 0x1800)
 174
 175    /* Shorthand for {eor,add,adc,and} r,r above.  */
 176 AVR_INSN (clr,  "r=r", "001001rdddddrrrr", 1, AVR_ISA_1200, 0x2400)
 177 AVR_INSN (lsl,  "r=r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00)
 178 AVR_INSN (rol,  "r=r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00)
 179 AVR_INSN (tst,  "r=r", "001000rdddddrrrr", 1, AVR_ISA_1200, 0x2000)
 180
 181 AVR_INSN (andi, "d,M", "0111KKKKddddKKKK", 1, AVR_ISA_1200, 0x7000)
 182   /*XXX special case*/
 183 AVR_INSN (cbr,  "d,n", "0111KKKKddddKKKK", 1, AVR_ISA_1200, 0x7000)
 184
 185 AVR_INSN (ldi,  "d,M", "1110KKKKddddKKKK", 1, AVR_ISA_1200, 0xe000)
 186 AVR_INSN (ser,  "d",   "11101111dddd1111", 1, AVR_ISA_1200, 0xef0f)
 187
 188 AVR_INSN (ori,  "d,M", "0110KKKKddddKKKK", 1, AVR_ISA_1200, 0x6000)
 189 AVR_INSN (sbr,  "d,M", "0110KKKKddddKKKK", 1, AVR_ISA_1200, 0x6000)
 190
 191 AVR_INSN (cpi,  "d,M", "0011KKKKddddKKKK", 1, AVR_ISA_1200, 0x3000)
 192 AVR_INSN (sbci, "d,M", "0100KKKKddddKKKK", 1, AVR_ISA_1200, 0x4000)
 193 AVR_INSN (subi, "d,M", "0101KKKKddddKKKK", 1, AVR_ISA_1200, 0x5000)
 194
 195 AVR_INSN (sbrc, "r,s", "1111110rrrrr0sss", 1, AVR_ISA_1200, 0xfc00)
 196 AVR_INSN (sbrs, "r,s", "1111111rrrrr0sss", 1, AVR_ISA_1200, 0xfe00)
 197 AVR_INSN (bld,  "r,s", "1111100ddddd0sss", 1, AVR_ISA_1200, 0xf800)
 198 AVR_INSN (bst,  "r,s", "1111101ddddd0sss", 1, AVR_ISA_1200, 0xfa00)
 199
 200 AVR_INSN (in,   "r,P", "10110PPdddddPPPP", 1, AVR_ISA_1200, 0xb000)
 201 AVR_INSN (out,  "P,r", "10111PPrrrrrPPPP", 1, AVR_ISA_1200, 0xb800)
 202
 203 AVR_INSN (adiw, "w,K", "10010110KKddKKKK", 1, AVR_ISA_2xxx, 0x9600)
 204 AVR_INSN (sbiw, "w,K", "10010111KKddKKKK", 1, AVR_ISA_2xxx, 0x9700)
 205
 206 AVR_INSN (cbi,  "p,s", "10011000pppppsss", 1, AVR_ISA_1200, 0x9800)
 207 AVR_INSN (sbi,  "p,s", "10011010pppppsss", 1, AVR_ISA_1200, 0x9a00)
 208 AVR_INSN (sbic, "p,s", "10011001pppppsss", 1, AVR_ISA_1200, 0x9900)
 209 AVR_INSN (sbis, "p,s", "10011011pppppsss", 1, AVR_ISA_1200, 0x9b00)
 210
 211 AVR_INSN (brcc, "l",   "111101lllllll000", 1, AVR_ISA_1200, 0xf400)
 212 AVR_INSN (brcs, "l",   "111100lllllll000", 1, AVR_ISA_1200, 0xf000)
 213 AVR_INSN (breq, "l",   "111100lllllll001", 1, AVR_ISA_1200, 0xf001)
 214 AVR_INSN (brge, "l",   "111101lllllll100", 1, AVR_ISA_1200, 0xf404)
 215 AVR_INSN (brhc, "l",   "111101lllllll101", 1, AVR_ISA_1200, 0xf405)
 216 AVR_INSN (brhs, "l",   "111100lllllll101", 1, AVR_ISA_1200, 0xf005)
 217 AVR_INSN (brid, "l",   "111101lllllll111", 1, AVR_ISA_1200, 0xf407)
 218 AVR_INSN (brie, "l",   "111100lllllll111", 1, AVR_ISA_1200, 0xf007)
 219 AVR_INSN (brlo, "l",   "111100lllllll000", 1, AVR_ISA_1200, 0xf000)
 220 AVR_INSN (brlt, "l",   "111100lllllll100", 1, AVR_ISA_1200, 0xf004)
 221 AVR_INSN (brmi, "l",   "111100lllllll010", 1, AVR_ISA_1200, 0xf002)
 222 AVR_INSN (brne, "l",   "111101lllllll001", 1, AVR_ISA_1200, 0xf401)
 223 AVR_INSN (brpl, "l",   "111101lllllll010", 1, AVR_ISA_1200, 0xf402)
 224 AVR_INSN (brsh, "l",   "111101lllllll000", 1, AVR_ISA_1200, 0xf400)
 225 AVR_INSN (brtc, "l",   "111101lllllll110", 1, AVR_ISA_1200, 0xf406)
 226 AVR_INSN (brts, "l",   "111100lllllll110", 1, AVR_ISA_1200, 0xf006)
 227 AVR_INSN (brvc, "l",   "111101lllllll011", 1, AVR_ISA_1200, 0xf403)
 228 AVR_INSN (brvs, "l",   "111100lllllll011", 1, AVR_ISA_1200, 0xf003)
 229
 230    /* Same as br?? above.  */
 231 AVR_INSN (brbc, "s,l", "111101lllllllsss", 1, AVR_ISA_1200, 0xf400)
 232 AVR_INSN (brbs, "s,l", "111100lllllllsss", 1, AVR_ISA_1200, 0xf000)
 233
 234 AVR_INSN (rcall, "L",  "1101LLLLLLLLLLLL", 1, AVR_ISA_1200, 0xd000)
 235 AVR_INSN (rjmp,  "L",  "1100LLLLLLLLLLLL", 1, AVR_ISA_1200, 0xc000)
 236
 237 AVR_INSN (call, "h",   "1001010hhhhh111h", 2, AVR_ISA_MEGA, 0x940e)
 238 AVR_INSN (jmp,  "h",   "1001010hhhhh110h", 2, AVR_ISA_MEGA, 0x940c)
 239
 240 AVR_INSN (asr,  "r",   "1001010rrrrr0101", 1, AVR_ISA_1200, 0x9405)
 241 AVR_INSN (com,  "r",   "1001010rrrrr0000", 1, AVR_ISA_1200, 0x9400)
 242 AVR_INSN (dec,  "r",   "1001010rrrrr1010", 1, AVR_ISA_1200, 0x940a)
 243 AVR_INSN (inc,  "r",   "1001010rrrrr0011", 1, AVR_ISA_1200, 0x9403)
 244 AVR_INSN (lsr,  "r",   "1001010rrrrr0110", 1, AVR_ISA_1200, 0x9406)
 245 AVR_INSN (neg,  "r",   "1001010rrrrr0001", 1, AVR_ISA_1200, 0x9401)
 246 AVR_INSN (pop,  "r",   "1001000rrrrr1111", 1, AVR_ISA_2xxx, 0x900f)
 247 AVR_INSN (push, "r",   "1001001rrrrr1111", 1, AVR_ISA_2xxx, 0x920f)
 248 AVR_INSN (ror,  "r",   "1001010rrrrr0111", 1, AVR_ISA_1200, 0x9407)
 249 AVR_INSN (swap, "r",   "1001010rrrrr0010", 1, AVR_ISA_1200, 0x9402)
 250
 251    /* Known to be decoded as `nop' by the old core.  */
 252 AVR_INSN (movw, "v,v", "00000001ddddrrrr", 1, AVR_ISA_MOVW, 0x0100)
 253 AVR_INSN (muls, "d,d", "00000010ddddrrrr", 1, AVR_ISA_MUL,  0x0200)
 254 AVR_INSN (mulsu,"a,a", "000000110ddd0rrr", 1, AVR_ISA_MUL,  0x0300)
 255 AVR_INSN (fmul, "a,a", "000000110ddd1rrr", 1, AVR_ISA_MUL,  0x0308)
 256 AVR_INSN (fmuls,"a,a", "000000111ddd0rrr", 1, AVR_ISA_MUL,  0x0380)
 257 AVR_INSN (fmulsu,"a,a","000000111ddd1rrr", 1, AVR_ISA_MUL,  0x0388)
 258
 259 AVR_INSN (sts,  "i,r", "1001001ddddd0000", 2, AVR_ISA_2xxx, 0x9200)
 260 AVR_INSN (lds,  "r,i", "1001000ddddd0000", 2, AVR_ISA_2xxx, 0x9000)
 261
 262    /* Special case for b+0, `e' must be next entry after `b',
 263       b={Y=1,Z=0}, ee={X=11,Y=10,Z=00}, !=1 if -e or e+ or X.  */
 264 AVR_INSN (ldd,  "r,b", "10o0oo0dddddbooo", 1, AVR_ISA_2xxx, 0x8000)
 265 AVR_INSN (ld,   "r,e", "100!000dddddee-+", 1, AVR_ISA_1200, 0x8000)
 266 AVR_INSN (std,  "b,r", "10o0oo1rrrrrbooo", 1, AVR_ISA_2xxx, 0x8200)
 267 AVR_INSN (st,   "e,r", "100!001rrrrree-+", 1, AVR_ISA_1200, 0x8200)
 268
 269    /* These are for devices that don't exist yet
 270       (>128K program memory, PC = EIND:Z).  */
 271 AVR_INSN (eicall, "",  "1001010100011001", 1, AVR_ISA_EIND, 0x9519)
 272 AVR_INSN (eijmp, "",   "1001010000011001", 1, AVR_ISA_EIND, 0x9419)
 273