opcodes/sparc-dis.c

   1 /* Print SPARC instructions.
   2    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2000, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
   4
   5    This program is free software; you can redistribute it and/or modify
   6    it under the terms of the GNU General Public License as published by
   7    the Free Software Foundation; either version 2 of the License, or
   8    (at your option) any later version.
   9
  10    This program is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13    GNU General Public License for more details.
  14
  15    You should have received a copy of the GNU General Public License
  16    along with this program; if not, write to the Free Software
  17    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  18    MA 02110-1301, USA.  */
  19
  20 #include <stdio.h>
  21
  22 #include "sysdep.h"
  23 #include "opcode/sparc.h"
  24 #include "dis-asm.h"
  25 #include "libiberty.h"
  26 #include "opintl.h"
  27
  28 /* Bitmask of v9 architectures.  */
  29 #define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
  30                  | (1 << SPARC_OPCODE_ARCH_V9A) \
  31                  | (1 << SPARC_OPCODE_ARCH_V9B))
  32 /* 1 if INSN is for v9 only.  */
  33 #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
  34 /* 1 if INSN is for v9.  */
  35 #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
  36
  37 /* The sorted opcode table.  */
  38 static const sparc_opcode **sorted_opcodes;
  39
  40 /* For faster lookup, after insns are sorted they are hashed.  */
  41 /* ??? I think there is room for even more improvement.  */
  42
  43 #define HASH_SIZE 256
  44 /* It is important that we only look at insn code bits as that is how the
  45    opcode table is hashed.  OPCODE_BITS is a table of valid bits for each
  46    of the main types (0,1,2,3).  */
  47 static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
  48 #define HASH_INSN(INSN) \
  49   ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
  50 typedef struct sparc_opcode_hash
  51 {
  52   struct sparc_opcode_hash *next;
  53   const sparc_opcode *opcode;
  54 } sparc_opcode_hash;
  55
  56 static sparc_opcode_hash *opcode_hash_table[HASH_SIZE];
  57
  58 /* Sign-extend a value which is N bits long.  */
  59 #define SEX(value, bits) \
  60         ((((int)(value)) << ((8 * sizeof (int)) - bits))        \
  61                          >> ((8 * sizeof (int)) - bits) )
  62
  63 static  char *reg_names[] =
  64 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
  65   "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
  66   "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
  67   "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
  68   "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
  69   "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
  70   "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
  71   "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
  72   "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
  73   "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
  74   "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
  75   "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
  76 /* psr, wim, tbr, fpsr, cpsr are v8 only.  */
  77   "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
  78 };
  79
  80 #define freg_names      (&reg_names[4 * 8])
  81
  82 /* These are ordered according to there register number in
  83    rdpr and wrpr insns.  */
  84 static char *v9_priv_reg_names[] =
  85 {
  86   "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
  87   "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
  88   "wstate", "fq"
  89   /* "ver" - special cased */
  90 };
  91
  92 /* These are ordered according to there register number in
  93    rd and wr insns (-16).  */
  94 static char *v9a_asr_reg_names[] =
  95 {
  96   "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
  97   "softint", "tick_cmpr", "sys_tick", "sys_tick_cmpr"
  98 };
  99
 100 /* Macros used to extract instruction fields.  Not all fields have
 101    macros defined here, only those which are actually used.  */
 102
 103 #define X_RD(i)      (((i) >> 25) & 0x1f)
 104 #define X_RS1(i)     (((i) >> 14) & 0x1f)
 105 #define X_LDST_I(i)  (((i) >> 13) & 1)
 106 #define X_ASI(i)     (((i) >> 5) & 0xff)
 107 #define X_RS2(i)     (((i) >> 0) & 0x1f)
 108 #define X_IMM(i,n)   (((i) >> 0) & ((1 << (n)) - 1))
 109 #define X_SIMM(i,n)  SEX (X_IMM ((i), (n)), (n))
 110 #define X_DISP22(i)  (((i) >> 0) & 0x3fffff)
 111 #define X_IMM22(i)   X_DISP22 (i)
 112 #define X_DISP30(i)  (((i) >> 0) & 0x3fffffff)
 113
 114 /* These are for v9.  */
 115 #define X_DISP16(i)  (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
 116 #define X_DISP19(i)  (((i) >> 0) & 0x7ffff)
 117 #define X_MEMBAR(i)  ((i) & 0x7f)
 118
 119 /* Here is the union which was used to extract instruction fields
 120    before the shift and mask macros were written.
 121
 122    union sparc_insn
 123      {
 124        unsigned long int code;
 125        struct
 126          {
 127            unsigned int anop:2;
 128            #define      op      ldst.anop
 129            unsigned int anrd:5;
 130            #define      rd      ldst.anrd
 131            unsigned int op3:6;
 132            unsigned int anrs1:5;
 133            #define      rs1     ldst.anrs1
 134            unsigned int i:1;
 135            unsigned int anasi:8;
 136            #define      asi     ldst.anasi
 137            unsigned int anrs2:5;
 138            #define      rs2     ldst.anrs2
 139            #define      shcnt   rs2
 140          } ldst;
 141        struct
 142          {
 143            unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
 144            unsigned int IMM13:13;
 145            #define      imm13   IMM13.IMM13
 146          } IMM13;
 147        struct
 148          {
 149            unsigned int anop:2;
 150            unsigned int a:1;
 151            unsigned int cond:4;
 152            unsigned int op2:3;
 153            unsigned int DISP22:22;
 154            #define      disp22  branch.DISP22
 155            #define      imm22   disp22
 156          } branch;
 157        struct
 158          {
 159            unsigned int anop:2;
 160            unsigned int a:1;
 161            unsigned int z:1;
 162            unsigned int rcond:3;
 163            unsigned int op2:3;
 164            unsigned int DISP16HI:2;
 165            unsigned int p:1;
 166            unsigned int _rs1:5;
 167            unsigned int DISP16LO:14;
 168          } branch16;
 169        struct
 170          {
 171            unsigned int anop:2;
 172            unsigned int adisp30:30;
 173            #define      disp30  call.adisp30
 174          } call;
 175      };  */
 176
 177 /* Nonzero if INSN is the opcode for a delayed branch.  */
 178
 179 static int
 180 is_delayed_branch (unsigned long insn)
 181 {
 182   sparc_opcode_hash *op;
 183
 184   for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
 185     {
 186       const sparc_opcode *opcode = op->opcode;
 187
 188       if ((opcode->match & insn) == opcode->match
 189           && (opcode->lose & insn) == 0)
 190         return opcode->flags & F_DELAYED;
 191     }
 192   return 0;
 193 }
 194
 195 /* extern void qsort (); */
 196
 197 /* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value
 198    to compare_opcodes.  */
 199 static unsigned int current_arch_mask;
 200
 201 /* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values.  */
 202
 203 static int
 204 compute_arch_mask (unsigned long mach)
 205 {
 206   switch (mach)
 207     {
 208     case 0 :
 209     case bfd_mach_sparc :
 210       return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8);
 211     case bfd_mach_sparc_sparclet :
 212       return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
 213     case bfd_mach_sparc_sparclite :
 214     case bfd_mach_sparc_sparclite_le :
 215       /* sparclites insns are recognized by default (because that's how
 216          they've always been treated, for better or worse).  Kludge this by
 217          indicating generic v8 is also selected.  */
 218       return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
 219               | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));
 220     case bfd_mach_sparc_v8plus :
 221     case bfd_mach_sparc_v9 :
 222       return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
 223     case bfd_mach_sparc_v8plusa :
 224     case bfd_mach_sparc_v9a :
 225       return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
 226     case bfd_mach_sparc_v8plusb :
 227     case bfd_mach_sparc_v9b :
 228       return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
 229     }
 230   abort ();
 231 }
 232
 233 /* Compare opcodes A and B.  */
 234
 235 static int
 236 compare_opcodes (const void * a, const void * b)
 237 {
 238   sparc_opcode *op0 = * (sparc_opcode **) a;
 239   sparc_opcode *op1 = * (sparc_opcode **) b;
 240   unsigned long int match0 = op0->match, match1 = op1->match;
 241   unsigned long int lose0 = op0->lose, lose1 = op1->lose;
 242   register unsigned int i;
 243
 244   /* If one (and only one) insn isn't supported by the current architecture,
 245      prefer the one that is.  If neither are supported, but they're both for
 246      the same architecture, continue processing.  Otherwise (both unsupported
 247      and for different architectures), prefer lower numbered arch's (fudged
 248      by comparing the bitmasks).  */
 249   if (op0->architecture & current_arch_mask)
 250     {
 251       if (! (op1->architecture & current_arch_mask))
 252         return -1;
 253     }
 254   else
 255     {
 256       if (op1->architecture & current_arch_mask)
 257         return 1;
 258       else if (op0->architecture != op1->architecture)
 259         return op0->architecture - op1->architecture;
 260     }
 261
 262   /* If a bit is set in both match and lose, there is something
 263      wrong with the opcode table.  */
 264   if (match0 & lose0)
 265     {
 266       fprintf
 267         (stderr,
 268          /* xgettext:c-format */
 269          _("Internal error:  bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
 270          op0->name, match0, lose0);
 271       op0->lose &= ~op0->match;
 272       lose0 = op0->lose;
 273     }
 274
 275   if (match1 & lose1)
 276     {
 277       fprintf
 278         (stderr,
 279          /* xgettext:c-format */
 280          _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
 281          op1->name, match1, lose1);
 282       op1->lose &= ~op1->match;
 283       lose1 = op1->lose;
 284     }
 285
 286   /* Because the bits that are variable in one opcode are constant in
 287      another, it is important to order the opcodes in the right order.  */
 288   for (i = 0; i < 32; ++i)
 289     {
 290       unsigned long int x = 1 << i;
 291       int x0 = (match0 & x) != 0;
 292       int x1 = (match1 & x) != 0;
 293
 294       if (x0 != x1)
 295         return x1 - x0;
 296     }
 297
 298   for (i = 0; i < 32; ++i)
 299     {
 300       unsigned long int x = 1 << i;
 301       int x0 = (lose0 & x) != 0;
 302       int x1 = (lose1 & x) != 0;
 303
 304       if (x0 != x1)
 305         return x1 - x0;
 306     }
 307
 308   /* They are functionally equal.  So as long as the opcode table is
 309      valid, we can put whichever one first we want, on aesthetic grounds.  */
 310
 311   /* Our first aesthetic ground is that aliases defer to real insns.  */
 312   {
 313     int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
 314
 315     if (alias_diff != 0)
 316       /* Put the one that isn't an alias first.  */
 317       return alias_diff;
 318   }
 319
 320   /* Except for aliases, two "identical" instructions had
 321      better have the same opcode.  This is a sanity check on the table.  */
 322   i = strcmp (op0->name, op1->name);
 323   if (i)
 324     {
 325       if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary.  */
 326         return i;
 327       else
 328         fprintf (stderr,
 329                  /* xgettext:c-format */
 330                  _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
 331                  op0->name, op1->name);
 332     }
 333
 334   /* Fewer arguments are preferred.  */
 335   {
 336     int length_diff = strlen (op0->args) - strlen (op1->args);
 337
 338     if (length_diff != 0)
 339       /* Put the one with fewer arguments first.  */
 340       return length_diff;
 341   }
 342
 343   /* Put 1+i before i+1.  */
 344   {
 345     char *p0 = (char *) strchr (op0->args, '+');
 346     char *p1 = (char *) strchr (op1->args, '+');
 347
 348     if (p0 && p1)
 349       {
 350         /* There is a plus in both operands.  Note that a plus
 351            sign cannot be the first character in args,
 352            so the following [-1]'s are valid.  */
 353         if (p0[-1] == 'i' && p1[1] == 'i')
 354           /* op0 is i+1 and op1 is 1+i, so op1 goes first.  */
 355           return 1;
 356         if (p0[1] == 'i' && p1[-1] == 'i')
 357           /* op0 is 1+i and op1 is i+1, so op0 goes first.  */
 358           return -1;
 359       }
 360   }
 361
 362   /* Put 1,i before i,1.  */
 363   {
 364     int i0 = strncmp (op0->args, "i,1", 3) == 0;
 365     int i1 = strncmp (op1->args, "i,1", 3) == 0;
 366
 367     if (i0 ^ i1)
 368       return i0 - i1;
 369   }
 370
 371   /* They are, as far as we can tell, identical.
 372      Since qsort may have rearranged the table partially, there is
 373      no way to tell which one was first in the opcode table as
 374      written, so just say there are equal.  */
 375   /* ??? This is no longer true now that we sort a vector of pointers,
 376      not the table itself.  */
 377   return 0;
 378 }
 379
 380 /* Build a hash table from the opcode table.
 381    OPCODE_TABLE is a sorted list of pointers into the opcode table.  */
 382
 383 static void
 384 build_hash_table (const sparc_opcode **opcode_table,
 385                   sparc_opcode_hash **hash_table,
 386                   int num_opcodes)
 387 {
 388   int i;
 389   int hash_count[HASH_SIZE];
 390   static sparc_opcode_hash *hash_buf = NULL;
 391
 392   /* Start at the end of the table and work backwards so that each
 393      chain is sorted.  */
 394
 395   memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
 396   memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
 397   if (hash_buf != NULL)
 398     free (hash_buf);
 399   hash_buf = xmalloc (sizeof (* hash_buf) * num_opcodes);
 400   for (i = num_opcodes - 1; i >= 0; --i)
 401     {
 402       int hash = HASH_INSN (opcode_table[i]->match);
 403       sparc_opcode_hash *h = &hash_buf[i];
 404
 405       h->next = hash_table[hash];
 406       h->opcode = opcode_table[i];
 407       hash_table[hash] = h;
 408       ++hash_count[hash];
 409     }
 410
 411 #if 0 /* for debugging */
 412   {
 413     int min_count = num_opcodes, max_count = 0;
 414     int total;
 415
 416     for (i = 0; i < HASH_SIZE; ++i)
 417       {
 418         if (hash_count[i] < min_count)
 419           min_count = hash_count[i];
 420         if (hash_count[i] > max_count)
 421           max_count = hash_count[i];
 422         total += hash_count[i];
 423       }
 424
 425     printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
 426             min_count, max_count, (double) total / HASH_SIZE);
 427   }
 428 #endif
 429 }
 430
 431 /* Print one instruction from MEMADDR on INFO->STREAM.
 432
 433    We suffix the instruction with a comment that gives the absolute
 434    address involved, as well as its symbolic form, if the instruction
 435    is preceded by a findable `sethi' and it either adds an immediate
 436    displacement to that register, or it is an `add' or `or' instruction
 437    on that register.  */
 438
 439 int
 440 print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
 441 {
 442   FILE *stream = info->stream;
 443   bfd_byte buffer[4];
 444   unsigned long insn;
 445   sparc_opcode_hash *op;
 446   /* Nonzero of opcode table has been initialized.  */
 447   static int opcodes_initialized = 0;
 448   /* bfd mach number of last call.  */
 449   static unsigned long current_mach = 0;
 450   bfd_vma (*getword) (const void *);
 451
 452   if (!opcodes_initialized
 453       || info->mach != current_mach)
 454     {
 455       int i;
 456
 457       current_arch_mask = compute_arch_mask (info->mach);
 458
 459       if (!opcodes_initialized)
 460         sorted_opcodes =
 461           xmalloc (sparc_num_opcodes * sizeof (sparc_opcode *));
 462       /* Reset the sorted table so we can resort it.  */
 463       for (i = 0; i < sparc_num_opcodes; ++i)
 464         sorted_opcodes[i] = &sparc_opcodes[i];
 465       qsort ((char *) sorted_opcodes, sparc_num_opcodes,
 466              sizeof (sorted_opcodes[0]), compare_opcodes);
 467
 468       build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes);
 469       current_mach = info->mach;
 470       opcodes_initialized = 1;
 471     }
 472
 473   {
 474     int status =
 475       (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
 476
 477     if (status != 0)
 478       {
 479         (*info->memory_error_func) (status, memaddr, info);
 480         return -1;
 481       }
 482   }
 483
 484   /* On SPARClite variants such as DANlite (sparc86x), instructions
 485      are always big-endian even when the machine is in little-endian mode.  */
 486   if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite)
 487     getword = bfd_getb32;
 488   else
 489     getword = bfd_getl32;
 490
 491   insn = getword (buffer);
 492
 493   info->insn_info_valid = 1;                    /* We do return this info.  */
 494   info->insn_type = dis_nonbranch;              /* Assume non branch insn.  */
 495   info->branch_delay_insns = 0;                 /* Assume no delay.  */
 496   info->target = 0;                             /* Assume no target known.  */
 497
 498   for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
 499     {
 500       const sparc_opcode *opcode = op->opcode;
 501
 502       /* If the insn isn't supported by the current architecture, skip it.  */
 503       if (! (opcode->architecture & current_arch_mask))
 504         continue;
 505
 506       if ((opcode->match & insn) == opcode->match
 507           && (opcode->lose & insn) == 0)
 508         {
 509           /* Nonzero means that we have found an instruction which has
 510              the effect of adding or or'ing the imm13 field to rs1.  */
 511           int imm_added_to_rs1 = 0;
 512           int imm_ored_to_rs1 = 0;
 513
 514           /* Nonzero means that we have found a plus sign in the args
 515              field of the opcode table.  */
 516           int found_plus = 0;
 517
 518           /* Nonzero means we have an annulled branch.  */
 519           int is_annulled = 0;
 520
 521           /* Do we have an `add' or `or' instruction combining an
 522              immediate with rs1?  */
 523           if (opcode->match == 0x80102000) /* or */
 524             imm_ored_to_rs1 = 1;
 525           if (opcode->match == 0x80002000) /* add */
 526             imm_added_to_rs1 = 1;
 527
 528           if (X_RS1 (insn) != X_RD (insn)
 529               && strchr (opcode->args, 'r') != 0)
 530               /* Can't do simple format if source and dest are different.  */
 531               continue;
 532           if (X_RS2 (insn) != X_RD (insn)
 533               && strchr (opcode->args, 'O') != 0)
 534               /* Can't do simple format if source and dest are different.  */
 535               continue;
 536
 537           (*info->fprintf_func) (stream, opcode->name);
 538
 539           {
 540             const char *s;
 541
 542             if (opcode->args[0] != ',')
 543               (*info->fprintf_func) (stream, " ");
 544
 545             for (s = opcode->args; *s != '\0'; ++s)
 546               {
 547                 while (*s == ',')
 548                   {
 549                     (*info->fprintf_func) (stream, ",");
 550                     ++s;
 551                     switch (*s)
 552                       {
 553                       case 'a':
 554                         (*info->fprintf_func) (stream, "a");
 555                         is_annulled = 1;
 556                         ++s;
 557                         continue;
 558                       case 'N':
 559                         (*info->fprintf_func) (stream, "pn");
 560                         ++s;
 561                         continue;
 562
 563                       case 'T':
 564                         (*info->fprintf_func) (stream, "pt");
 565                         ++s;
 566                         continue;
 567
 568                       default:
 569                         break;
 570                       }
 571                   }
 572
 573                 (*info->fprintf_func) (stream, " ");
 574
 575                 switch (*s)
 576                   {
 577                   case '+':
 578                     found_plus = 1;
 579                     /* Fall through.  */
 580
 581                   default:
 582                     (*info->fprintf_func) (stream, "%c", *s);
 583                     break;
 584
 585                   case '#':
 586                     (*info->fprintf_func) (stream, "0");
 587                     break;
 588
 589 #define reg(n)  (*info->fprintf_func) (stream, "%%%s", reg_names[n])
 590                   case '1':
 591                   case 'r':
 592                     reg (X_RS1 (insn));
 593                     break;
 594
 595                   case '2':
 596                   case 'O':
 597                     reg (X_RS2 (insn));
 598                     break;
 599
 600                   case 'd':
 601                     reg (X_RD (insn));
 602                     break;
 603 #undef  reg
 604
 605 #define freg(n)         (*info->fprintf_func) (stream, "%%%s", freg_names[n])
 606 #define fregx(n)        (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)])
 607                   case 'e':
 608                     freg (X_RS1 (insn));
 609                     break;
 610                   case 'v':     /* Double/even.  */
 611                   case 'V':     /* Quad/multiple of 4.  */
 612                     fregx (X_RS1 (insn));
 613                     break;
 614
 615                   case 'f':
 616                     freg (X_RS2 (insn));
 617                     break;
 618                   case 'B':     /* Double/even.  */
 619                   case 'R':     /* Quad/multiple of 4.  */
 620                     fregx (X_RS2 (insn));
 621                     break;
 622
 623                   case 'g':
 624                     freg (X_RD (insn));
 625                     break;
 626                   case 'H':     /* Double/even.  */
 627                   case 'J':     /* Quad/multiple of 4.  */
 628                     fregx (X_RD (insn));
 629                     break;
 630 #undef  freg
 631 #undef  fregx
 632
 633 #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
 634                   case 'b':
 635                     creg (X_RS1 (insn));
 636                     break;
 637
 638                   case 'c':
 639                     creg (X_RS2 (insn));
 640                     break;
 641
 642                   case 'D':
 643                     creg (X_RD (insn));
 644                     break;
 645 #undef  creg
 646
 647                   case 'h':
 648                     (*info->fprintf_func) (stream, "%%hi(%#x)",
 649                                            ((unsigned) 0xFFFFFFFF
 650                                             & ((int) X_IMM22 (insn) << 10)));
 651                     break;
 652
 653                   case 'i':     /* 13 bit immediate.  */
 654                   case 'I':     /* 11 bit immediate.  */
 655                   case 'j':     /* 10 bit immediate.  */
 656                     {
 657                       int imm;
 658
 659                       if (*s == 'i')
 660                         imm = X_SIMM (insn, 13);
 661                       else if (*s == 'I')
 662                         imm = X_SIMM (insn, 11);
 663                       else
 664                         imm = X_SIMM (insn, 10);
 665
 666                       /* Check to see whether we have a 1+i, and take
 667                          note of that fact.
 668
 669                          Note: because of the way we sort the table,
 670                          we will be matching 1+i rather than i+1,
 671                          so it is OK to assume that i is after +,
 672                          not before it.  */
 673                       if (found_plus)
 674                         imm_added_to_rs1 = 1;
 675
 676                       if (imm <= 9)
 677                         (*info->fprintf_func) (stream, "%d", imm);
 678                       else
 679                         (*info->fprintf_func) (stream, "%#x", imm);
 680                     }
 681                     break;
 682
 683                   case 'X':     /* 5 bit unsigned immediate.  */
 684                   case 'Y':     /* 6 bit unsigned immediate.  */
 685                     {
 686                       int imm = X_IMM (insn, *s == 'X' ? 5 : 6);
 687
 688                       if (imm <= 9)
 689                         (info->fprintf_func) (stream, "%d", imm);
 690                       else
 691                         (info->fprintf_func) (stream, "%#x", (unsigned) imm);
 692                     }
 693                     break;
 694
 695                   case '3':
 696                     (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3));
 697                     break;
 698
 699                   case 'K':
 700                     {
 701                       int mask = X_MEMBAR (insn);
 702                       int bit = 0x40, printed_one = 0;
 703                       const char *name;
 704
 705                       if (mask == 0)
 706                         (info->fprintf_func) (stream, "0");
 707                       else
 708                         while (bit)
 709                           {
 710                             if (mask & bit)
 711                               {
 712                                 if (printed_one)
 713                                   (info->fprintf_func) (stream, "|");
 714                                 name = sparc_decode_membar (bit);
 715                                 (info->fprintf_func) (stream, "%s", name);
 716                                 printed_one = 1;
 717                               }
 718                             bit >>= 1;
 719                           }
 720                       break;
 721                     }
 722
 723                   case 'k':
 724                     info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
 725                     (*info->print_address_func) (info->target, info);
 726                     break;
 727
 728                   case 'G':
 729                     info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4;
 730                     (*info->print_address_func) (info->target, info);
 731                     break;
 732
 733                   case '6':
 734                   case '7':
 735                   case '8':
 736                   case '9':
 737                     (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0');
 738                     break;
 739
 740                   case 'z':
 741                     (*info->fprintf_func) (stream, "%%icc");
 742                     break;
 743
 744                   case 'Z':
 745                     (*info->fprintf_func) (stream, "%%xcc");
 746                     break;
 747
 748                   case 'E':
 749                     (*info->fprintf_func) (stream, "%%ccr");
 750                     break;
 751
 752                   case 's':
 753                     (*info->fprintf_func) (stream, "%%fprs");
 754                     break;
 755
 756                   case 'o':
 757                     (*info->fprintf_func) (stream, "%%asi");
 758                     break;
 759
 760                   case 'W':
 761                     (*info->fprintf_func) (stream, "%%tick");
 762                     break;
 763
 764                   case 'P':
 765                     (*info->fprintf_func) (stream, "%%pc");
 766                     break;
 767
 768                   case '?':
 769                     if (X_RS1 (insn) == 31)
 770                       (*info->fprintf_func) (stream, "%%ver");
 771                     else if ((unsigned) X_RS1 (insn) < 16)
 772                       (*info->fprintf_func) (stream, "%%%s",
 773                                              v9_priv_reg_names[X_RS1 (insn)]);
 774                     else
 775                       (*info->fprintf_func) (stream, "%%reserved");
 776                     break;
 777
 778                   case '!':
 779                     if ((unsigned) X_RD (insn) < 15)
 780                       (*info->fprintf_func) (stream, "%%%s",
 781                                              v9_priv_reg_names[X_RD (insn)]);
 782                     else
 783                       (*info->fprintf_func) (stream, "%%reserved");
 784                     break;
 785
 786                   case '/':
 787                     if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25)
 788                       (*info->fprintf_func) (stream, "%%reserved");
 789                     else
 790                       (*info->fprintf_func) (stream, "%%%s",
 791                                              v9a_asr_reg_names[X_RS1 (insn)-16]);
 792                     break;
 793
 794                   case '_':
 795                     if (X_RD (insn) < 16 || X_RD (insn) > 25)
 796                       (*info->fprintf_func) (stream, "%%reserved");
 797                     else
 798                       (*info->fprintf_func) (stream, "%%%s",
 799                                              v9a_asr_reg_names[X_RD (insn)-16]);
 800                     break;
 801
 802                   case '*':
 803                     {
 804                       const char *name = sparc_decode_prefetch (X_RD (insn));
 805
 806                       if (name)
 807                         (*info->fprintf_func) (stream, "%s", name);
 808                       else
 809                         (*info->fprintf_func) (stream, "%ld", X_RD (insn));
 810                       break;
 811                     }
 812
 813                   case 'M':
 814                     (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn));
 815                     break;
 816
 817                   case 'm':
 818                     (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn));
 819                     break;
 820
 821                   case 'L':
 822                     info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
 823                     (*info->print_address_func) (info->target, info);
 824                     break;
 825
 826                   case 'n':
 827                     (*info->fprintf_func)
 828                       (stream, "%#x", SEX (X_DISP22 (insn), 22));
 829                     break;
 830
 831                   case 'l':
 832                     info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4;
 833                     (*info->print_address_func) (info->target, info);
 834                     break;
 835
 836                   case 'A':
 837                     {
 838                       const char *name = sparc_decode_asi (X_ASI (insn));
 839
 840                       if (name)
 841                         (*info->fprintf_func) (stream, "%s", name);
 842                       else
 843                         (*info->fprintf_func) (stream, "(%ld)", X_ASI (insn));
 844                       break;
 845                     }
 846
 847                   case 'C':
 848                     (*info->fprintf_func) (stream, "%%csr");
 849                     break;
 850
 851                   case 'F':
 852                     (*info->fprintf_func) (stream, "%%fsr");
 853                     break;
 854
 855                   case 'p':
 856                     (*info->fprintf_func) (stream, "%%psr");
 857                     break;
 858
 859                   case 'q':
 860                     (*info->fprintf_func) (stream, "%%fq");
 861                     break;
 862
 863                   case 'Q':
 864                     (*info->fprintf_func) (stream, "%%cq");
 865                     break;
 866
 867                   case 't':
 868                     (*info->fprintf_func) (stream, "%%tbr");
 869                     break;
 870
 871                   case 'w':
 872                     (*info->fprintf_func) (stream, "%%wim");
 873                     break;
 874
 875                   case 'x':
 876                     (*info->fprintf_func) (stream, "%ld",
 877                                            ((X_LDST_I (insn) << 8)
 878                                             + X_ASI (insn)));
 879                     break;
 880
 881                   case 'y':
 882                     (*info->fprintf_func) (stream, "%%y");
 883                     break;
 884
 885                   case 'u':
 886                   case 'U':
 887                     {
 888                       int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn);
 889                       const char *name = sparc_decode_sparclet_cpreg (val);
 890
 891                       if (name)
 892                         (*info->fprintf_func) (stream, "%s", name);
 893                       else
 894                         (*info->fprintf_func) (stream, "%%cpreg(%d)", val);
 895                       break;
 896                     }
 897                   }
 898               }
 899           }
 900
 901           /* If we are adding or or'ing something to rs1, then
 902              check to see whether the previous instruction was
 903              a sethi to the same register as in the sethi.
 904              If so, attempt to print the result of the add or
 905              or (in this context add and or do the same thing)
 906              and its symbolic value.  */
 907           if (imm_ored_to_rs1 || imm_added_to_rs1)
 908             {
 909               unsigned long prev_insn;
 910               int errcode;
 911
 912               if (memaddr >= 4)
 913                 errcode =
 914                   (*info->read_memory_func)
 915                   (memaddr - 4, buffer, sizeof (buffer), info);
 916               else
 917                 errcode = 1;
 918
 919               prev_insn = getword (buffer);
 920
 921               if (errcode == 0)
 922                 {
 923                   /* If it is a delayed branch, we need to look at the
 924                      instruction before the delayed branch.  This handles
 925                      sequences such as:
 926
 927                      sethi %o1, %hi(_foo), %o1
 928                      call _printf
 929                      or %o1, %lo(_foo), %o1  */
 930
 931                   if (is_delayed_branch (prev_insn))
 932                     {
 933                       if (memaddr >= 8)
 934                         errcode = (*info->read_memory_func)
 935                           (memaddr - 8, buffer, sizeof (buffer), info);
 936                       else
 937                         errcode = 1;
 938
 939                       prev_insn = getword (buffer);
 940                     }
 941                 }
 942
 943               /* If there was a problem reading memory, then assume
 944                  the previous instruction was not sethi.  */
 945               if (errcode == 0)
 946                 {
 947                   /* Is it sethi to the same register?  */
 948                   if ((prev_insn & 0xc1c00000) == 0x01000000
 949                       && X_RD (prev_insn) == X_RS1 (insn))
 950                     {
 951                       (*info->fprintf_func) (stream, "\t! ");
 952                       info->target =
 953                         ((unsigned) 0xFFFFFFFF
 954                          & ((int) X_IMM22 (prev_insn) << 10));
 955                       if (imm_added_to_rs1)
 956                         info->target += X_SIMM (insn, 13);
 957                       else
 958                         info->target |= X_SIMM (insn, 13);
 959                       (*info->print_address_func) (info->target, info);
 960                       info->insn_type = dis_dref;
 961                       info->data_size = 4;  /* FIXME!!! */
 962                     }
 963                 }
 964             }
 965
 966           if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
 967             {
 968                 /* FIXME -- check is_annulled flag.  */
 969               if (opcode->flags & F_UNBR)
 970                 info->insn_type = dis_branch;
 971               if (opcode->flags & F_CONDBR)
 972                 info->insn_type = dis_condbranch;
 973               if (opcode->flags & F_JSR)
 974                 info->insn_type = dis_jsr;
 975               if (opcode->flags & F_DELAYED)
 976                 info->branch_delay_insns = 1;
 977             }
 978
 979           return sizeof (buffer);
 980         }
 981     }
 982
 983   info->insn_type = dis_noninsn;        /* Mark as non-valid instruction.  */
 984   (*info->fprintf_func) (stream, _("unknown"));
 985   return sizeof (buffer);
 986 }