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PR ld/1775
[binutils.git] / gas / config / bfin-parse.y
blob7751b688d005a91002ef920f27ae29aca1ecf1de
1 /* bfin-parse.y ADI Blackfin parser
2 Copyright 2005
3 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
21 %{
22
23 #include <stdio.h>
24 #include "bfin-aux.h"
25 #include <stdarg.h>
26 #include <obstack.h>
27
28 #define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \
29 bfin_gen_dsp32alu (HL, aopcde, aop, s, x, dst0, dst1, src0, src1)
30
31 #define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
32 bfin_gen_dsp32mac (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
33 dst, src0, src1, w0)
34
35 #define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
36 bfin_gen_dsp32mult (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
37 dst, src0, src1, w0)
38
39 #define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls) \
40 bfin_gen_dsp32shift (sopcde, dst0, src0, src1, sop, hls)
41
42 #define DSP32SHIFTIMM(sopcde, dst0, immag, src1, sop, hls) \
43 bfin_gen_dsp32shiftimm (sopcde, dst0, immag, src1, sop, hls)
44
45 #define LDIMMHALF_R(reg, h, s, z, hword) \
46 bfin_gen_ldimmhalf (reg, h, s, z, hword, 1)
47
48 #define LDIMMHALF_R5(reg, h, s, z, hword) \
49 bfin_gen_ldimmhalf (reg, h, s, z, hword, 2)
50
51 #define LDSTIDXI(ptr, reg, w, sz, z, offset) \
52 bfin_gen_ldstidxi (ptr, reg, w, sz, z, offset)
53
54 #define LDST(ptr, reg, aop, sz, z, w) \
55 bfin_gen_ldst (ptr, reg, aop, sz, z, w)
56
57 #define LDSTII(ptr, reg, offset, w, op) \
58 bfin_gen_ldstii (ptr, reg, offset, w, op)
59
60 #define DSPLDST(i, m, reg, aop, w) \
61 bfin_gen_dspldst (i, reg, aop, w, m)
62
63 #define LDSTPMOD(ptr, reg, idx, aop, w) \
64 bfin_gen_ldstpmod (ptr, reg, aop, w, idx)
65
66 #define LDSTIIFP(offset, reg, w) \
67 bfin_gen_ldstiifp (reg, offset, w)
68
69 #define LOGI2OP(dst, src, opc) \
70 bfin_gen_logi2op (opc, src, dst.regno & CODE_MASK)
71
72 #define ALU2OP(dst, src, opc) \
73 bfin_gen_alu2op (dst, src, opc)
74
75 #define BRCC(t, b, offset) \
76 bfin_gen_brcc (t, b, offset)
77
78 #define UJUMP(offset) \
79 bfin_gen_ujump (offset)
80
81 #define PROGCTRL(prgfunc, poprnd) \
82 bfin_gen_progctrl (prgfunc, poprnd)
83
84 #define PUSHPOPMULTIPLE(dr, pr, d, p, w) \
85 bfin_gen_pushpopmultiple (dr, pr, d, p, w)
86
87 #define PUSHPOPREG(reg, w) \
88 bfin_gen_pushpopreg (reg, w)
89
90 #define CALLA(addr, s) \
91 bfin_gen_calla (addr, s)
92
93 #define LINKAGE(r, framesize) \
94 bfin_gen_linkage (r, framesize)
95
96 #define COMPI2OPD(dst, src, op) \
97 bfin_gen_compi2opd (dst, src, op)
98
99 #define COMPI2OPP(dst, src, op) \
100 bfin_gen_compi2opp (dst, src, op)
101
102 #define DAGMODIK(i, op) \
103 bfin_gen_dagmodik (i, op)
104
105 #define DAGMODIM(i, m, op, br) \
106 bfin_gen_dagmodim (i, m, op, br)
107
108 #define COMP3OP(dst, src0, src1, opc) \
109 bfin_gen_comp3op (src0, src1, dst, opc)
110
111 #define PTR2OP(dst, src, opc) \
112 bfin_gen_ptr2op (dst, src, opc)
113
114 #define CCFLAG(x, y, opc, i, g) \
115 bfin_gen_ccflag (x, y, opc, i, g)
116
117 #define CCMV(src, dst, t) \
118 bfin_gen_ccmv (src, dst, t)
119
120 #define CACTRL(reg, a, op) \
121 bfin_gen_cactrl (reg, a, op)
122
123 #define LOOPSETUP(soffset, c, rop, eoffset, reg) \
124 bfin_gen_loopsetup (soffset, c, rop, eoffset, reg)
125
126 #define HL2(r1, r0) (IS_H (r1) << 1 | IS_H (r0))
127 #define IS_RANGE(bits, expr, sign, mul) \
128 value_match(expr, bits, sign, mul, 1)
129 #define IS_URANGE(bits, expr, sign, mul) \
130 value_match(expr, bits, sign, mul, 0)
131 #define IS_CONST(expr) (expr->type == Expr_Node_Constant)
132 #define IS_RELOC(expr) (expr->type != Expr_Node_Constant)
133 #define IS_IMM(expr, bits) value_match (expr, bits, 0, 1, 1)
134 #define IS_UIMM(expr, bits) value_match (expr, bits, 0, 1, 0)
135
136 #define IS_PCREL4(expr) \
137 (value_match (expr, 4, 0, 2, 0))
138
139 #define IS_LPPCREL10(expr) \
140 (value_match (expr, 10, 0, 2, 0))
141
142 #define IS_PCREL10(expr) \
143 (value_match (expr, 10, 0, 2, 1))
144
145 #define IS_PCREL12(expr) \
146 (value_match (expr, 12, 0, 2, 1))
147
148 #define IS_PCREL24(expr) \
149 (value_match (expr, 24, 0, 2, 1))
150
151
152 static int value_match (Expr_Node *expr, int sz, int sign, int mul, int issigned);
153
154 extern FILE *errorf;
155 extern INSTR_T insn;
156
157 static Expr_Node *binary (Expr_Op_Type, Expr_Node *, Expr_Node *);
158 static Expr_Node *unary (Expr_Op_Type, Expr_Node *);
159
160 static void notethat (char *format, ...);
161
162 char *current_inputline;
163 extern char *yytext;
164 int yyerror (char *msg);
165
166 void error (char *format, ...)
167 {
168 va_list ap;
169 char buffer[2000];
170
171 va_start (ap, format);
172 vsprintf (buffer, format, ap);
173 va_end (ap);
174
175 as_bad (buffer);
176 }
177
178 int
179 yyerror (char *msg)
180 {
181 if (msg[0] == '\0')
182 error ("%s", msg);
183
184 else if (yytext[0] != ';')
185 error ("%s. Input text was %s.", msg, yytext);
186 else
187 error ("%s.", msg);
188
189 return -1;
190 }
191
192 static int
193 in_range_p (Expr_Node *expr, int from, int to, unsigned int mask)
194 {
195 int val = EXPR_VALUE (expr);
196 if (expr->type != Expr_Node_Constant)
197 return 0;
198 if (val < from || val > to)
199 return 0;
200 return (val & mask) == 0;
201 }
202
203 extern int yylex (void);
204
205 #define imm3(x) EXPR_VALUE (x)
206 #define imm4(x) EXPR_VALUE (x)
207 #define uimm4(x) EXPR_VALUE (x)
208 #define imm5(x) EXPR_VALUE (x)
209 #define uimm5(x) EXPR_VALUE (x)
210 #define imm6(x) EXPR_VALUE (x)
211 #define imm7(x) EXPR_VALUE (x)
212 #define imm16(x) EXPR_VALUE (x)
213 #define uimm16s4(x) ((EXPR_VALUE (x)) >> 2)
214 #define uimm16(x) EXPR_VALUE (x)
215
216 /* Return true if a value is inside a range. */
217 #define IN_RANGE(x, low, high) \
218 (((EXPR_VALUE(x)) >= (low)) && (EXPR_VALUE(x)) <= ((high)))
219
220 /* Auxiliary functions. */
221
222 static void
223 neg_value (Expr_Node *expr)
224 {
225 expr->value.i_value = -expr->value.i_value;
226 }
227
228 static int
229 valid_dreg_pair (Register *reg1, Expr_Node *reg2)
230 {
231 if (!IS_DREG (*reg1))
232 {
233 yyerror ("Dregs expected");
234 return 0;
235 }
236
237 if (reg1->regno != 1 && reg1->regno != 3)
238 {
239 yyerror ("Bad register pair");
240 return 0;
241 }
242
243 if (imm7 (reg2) != reg1->regno - 1)
244 {
245 yyerror ("Bad register pair");
246 return 0;
247 }
248
249 reg1->regno--;
250 return 1;
251 }
252
253 static int
254 check_multiply_halfregs (Macfunc *aa, Macfunc *ab)
255 {
256 if ((!REG_EQUAL (aa->s0, ab->s0) && !REG_EQUAL (aa->s0, ab->s1))
257 || (!REG_EQUAL (aa->s1, ab->s1) && !REG_EQUAL (aa->s1, ab->s0)))
258 return yyerror ("Source multiplication register mismatch");
259
260 return 0;
261 }
262
263
264 /* Check (vector) mac funcs and ops. */
265
266 static int
267 check_macfuncs (Macfunc *aa, Opt_mode *opa,
268 Macfunc *ab, Opt_mode *opb)
269 {
270 /* Variables for swapping. */
271 Macfunc mtmp;
272 Opt_mode otmp;
273
274 /* If a0macfunc comes before a1macfunc, swap them. */
275
276 if (aa->n == 0)
277 {
278 /* (M) is not allowed here. */
279 if (opa->MM != 0)
280 return yyerror ("(M) not allowed with A0MAC");
281 if (ab->n != 1)
282 return yyerror ("Vector AxMACs can't be same");
283
284 mtmp = *aa; *aa = *ab; *ab = mtmp;
285 otmp = *opa; *opa = *opb; *opb = otmp;
286 }
287 else
288 {
289 if (opb->MM != 0)
290 return yyerror ("(M) not allowed with A0MAC");
291 if (opa->mod != 0)
292 return yyerror ("Bad opt mode");
293 if (ab->n != 0)
294 return yyerror ("Vector AxMACs can't be same");
295 }
296
297 /* If both ops are != 3, we have multiply_halfregs in both
298 assignment_or_macfuncs. */
299 if (aa->op == ab->op && aa->op != 3)
300 {
301 if (check_multiply_halfregs (aa, ab) < 0)
302 return -1;
303 }
304 else
305 {
306 /* Only one of the assign_macfuncs has a half reg multiply
307 Evil trick: Just 'OR' their source register codes:
308 We can do that, because we know they were initialized to 0
309 in the rules that don't use multiply_halfregs. */
310 aa->s0.regno |= (ab->s0.regno & CODE_MASK);
311 aa->s1.regno |= (ab->s1.regno & CODE_MASK);
312 }
313
314 if (aa->w == ab->w && aa->P != ab->P)
315 {
316 return yyerror ("macfuncs must differ");
317 if (aa->w && (aa->dst.regno - ab->dst.regno != 1))
318 return yyerror ("Destination Dregs must differ by one");
319 }
320 /* We assign to full regs, thus obey even/odd rules. */
321 else if ((aa->w && aa->P && IS_EVEN (aa->dst))
322 || (ab->w && ab->P && !IS_EVEN (ab->dst)))
323 return yyerror ("Even/Odd register assignment mismatch");
324 /* We assign to half regs, thus obey hi/low rules. */
325 else if ( (aa->w && !aa->P && !IS_H (aa->dst))
326 || (ab->w && !aa->P && IS_H (ab->dst)))
327 return yyerror ("High/Low register assignment mismatch");
328
329 /* Make sure first macfunc has got both P flags ORed. */
330 aa->P |= ab->P;
331
332 /* Make sure mod flags get ORed, too. */
333 opb->mod |= opa->mod;
334 return 0;
335 }
336
337
338 static int
339 is_group1 (INSTR_T x)
340 {
341 /* Group1 is dpsLDST, LDSTpmod, LDST, LDSTiiFP, LDSTii. */
342 if ((x->value & 0xc000) == 0x8000 || (x->value == 0x0000))
343 return 1;
344
345 return 0;
346 }
347
348 static int
349 is_group2 (INSTR_T x)
350 {
351 if ((((x->value & 0xfc00) == 0x9c00) /* dspLDST. */
352 && !((x->value & 0xfde0) == 0x9c60) /* dagMODim. */
353 && !((x->value & 0xfde0) == 0x9ce0) /* dagMODim with bit rev. */
354 && !((x->value & 0xfde0) == 0x9d60)) /* pick dagMODik. */
355 || (x->value == 0x0000))
356 return 1;
357 return 0;
358 }
359
360 %}
361
362 %union {
363 INSTR_T instr;
364 Expr_Node *expr;
365 SYMBOL_T symbol;
366 long value;
367 Register reg;
368 Macfunc macfunc;
369 struct { int r0; int s0; int x0; int aop; } modcodes;
370 struct { int r0; } r0;
371 Opt_mode mod;
372 }
373
374
375 /* Tokens. */
376
377 /* Vector Specific. */
378 %token BYTEOP16P BYTEOP16M
379 %token BYTEOP1P BYTEOP2P BYTEOP2M BYTEOP3P
380 %token BYTEUNPACK BYTEPACK
381 %token PACK
382 %token SAA
383 %token ALIGN8 ALIGN16 ALIGN24
384 %token VIT_MAX
385 %token EXTRACT DEPOSIT EXPADJ SEARCH
386 %token ONES SIGN SIGNBITS
387
388 /* Stack. */
389 %token LINK UNLINK
390
391 /* Registers. */
392 %token REG
393 %token PC
394 %token CCREG BYTE_DREG
395 %token REG_A_DOUBLE_ZERO REG_A_DOUBLE_ONE
396 %token A_ZERO_DOT_L A_ZERO_DOT_H A_ONE_DOT_L A_ONE_DOT_H
397 %token HALF_REG
398
399 /* Progctrl. */
400 %token NOP
401 %token RTI RTS RTX RTN RTE
402 %token HLT IDLE
403 %token STI CLI
404 %token CSYNC SSYNC
405 %token EMUEXCPT
406 %token RAISE EXCPT
407 %token LSETUP
408 %token LOOP
409 %token LOOP_BEGIN
410 %token LOOP_END
411 %token DISALGNEXCPT
412 %token JUMP JUMP_DOT_S JUMP_DOT_L
413 %token CALL
414
415 /* Emulator only. */
416 %token ABORT
417
418 /* Operators. */
419 %token NOT TILDA BANG
420 %token AMPERSAND BAR
421 %token PERCENT
422 %token CARET
423 %token BXOR
424
425 %token MINUS PLUS STAR SLASH
426 %token NEG
427 %token MIN MAX ABS
428 %token DOUBLE_BAR
429 %token _PLUS_BAR_PLUS _PLUS_BAR_MINUS _MINUS_BAR_PLUS _MINUS_BAR_MINUS
430 %token _MINUS_MINUS _PLUS_PLUS
431
432 /* Shift/rotate ops. */
433 %token SHIFT LSHIFT ASHIFT BXORSHIFT
434 %token _GREATER_GREATER_GREATER_THAN_ASSIGN
435 %token ROT
436 %token LESS_LESS GREATER_GREATER
437 %token _GREATER_GREATER_GREATER
438 %token _LESS_LESS_ASSIGN _GREATER_GREATER_ASSIGN
439 %token DIVS DIVQ
440
441 /* In place operators. */
442 %token ASSIGN _STAR_ASSIGN
443 %token _BAR_ASSIGN _CARET_ASSIGN _AMPERSAND_ASSIGN
444 %token _MINUS_ASSIGN _PLUS_ASSIGN
445
446 /* Assignments, comparisons. */
447 %token _ASSIGN_BANG _LESS_THAN_ASSIGN _ASSIGN_ASSIGN
448 %token GE LT LE GT
449 %token LESS_THAN
450
451 /* Cache. */
452 %token FLUSHINV FLUSH
453 %token IFLUSH PREFETCH
454
455 /* Misc. */
456 %token PRNT
457 %token OUTC
458 %token WHATREG
459 %token TESTSET
460
461 /* Modifiers. */
462 %token ASL ASR
463 %token B W
464 %token NS S CO SCO
465 %token TH TL
466 %token BP
467 %token BREV
468 %token X Z
469 %token M MMOD
470 %token R RND RNDL RNDH RND12 RND20
471 %token V
472 %token LO HI
473
474 /* Bit ops. */
475 %token BITTGL BITCLR BITSET BITTST BITMUX
476
477 /* Debug. */
478 %token DBGAL DBGAH DBGHALT DBG DBGA DBGCMPLX
479
480 /* Semantic auxiliaries. */
481
482 %token IF COMMA BY
483 %token COLON SEMICOLON
484 %token RPAREN LPAREN LBRACK RBRACK
485 %token STATUS_REG
486 %token MNOP
487 %token SYMBOL NUMBER
488 %token GOT AT PLTPC
489
490 /* Types. */
491 %type <instr> asm
492 %type <value> MMOD
493 %type <mod> opt_mode
494
495 %type <value> NUMBER
496 %type <r0> aligndir
497 %type <modcodes> byteop_mod
498 %type <reg> a_assign
499 %type <reg> a_plusassign
500 %type <reg> a_minusassign
501 %type <macfunc> multiply_halfregs
502 %type <macfunc> assign_macfunc
503 %type <macfunc> a_macfunc
504 %type <expr> expr_1
505 %type <instr> asm_1
506 %type <r0> vmod
507 %type <modcodes> vsmod
508 %type <modcodes> ccstat
509 %type <r0> cc_op
510 %type <reg> CCREG
511 %type <reg> reg_with_postinc
512 %type <reg> reg_with_predec
513
514 %type <r0> searchmod
515 %type <expr> symbol
516 %type <symbol> SYMBOL
517 %type <expr> eterm
518 %type <reg> REG
519 %type <reg> BYTE_DREG
520 %type <reg> REG_A_DOUBLE_ZERO
521 %type <reg> REG_A_DOUBLE_ONE
522 %type <reg> REG_A
523 %type <reg> STATUS_REG
524 %type <expr> expr
525 %type <r0> xpmod
526 %type <r0> xpmod1
527 %type <modcodes> smod
528 %type <modcodes> b3_op
529 %type <modcodes> rnd_op
530 %type <modcodes> post_op
531 %type <reg> HALF_REG
532 %type <r0> iu_or_nothing
533 %type <r0> plus_minus
534 %type <r0> asr_asl
535 %type <r0> asr_asl_0
536 %type <modcodes> sco
537 %type <modcodes> amod0
538 %type <modcodes> amod1
539 %type <modcodes> amod2
540 %type <r0> op_bar_op
541 %type <r0> w32_or_nothing
542 %type <r0> c_align
543 %type <r0> min_max
544 %type <expr> got
545 %type <expr> got_or_expr
546 %type <expr> pltpc
547
548
549 /* Precedence rules. */
550 %left BAR
551 %left CARET
552 %left AMPERSAND
553 %left LESS_LESS GREATER_GREATER
554 %left PLUS MINUS
555 %left STAR SLASH PERCENT
556
557 %right ASSIGN
558
559 %right TILDA BANG
560 %start statement
561 %%
562 statement:
563 | asm
564 {
565 insn = $1;
566 if (insn == (INSTR_T) 0)
567 return NO_INSN_GENERATED;
568 else if (insn == (INSTR_T) - 1)
569 return SEMANTIC_ERROR;
570 else
571 return INSN_GENERATED;
572 }
573 ;
574
575 asm: asm_1 SEMICOLON
576 /* Parallel instructions. */
577 | asm_1 DOUBLE_BAR asm_1 DOUBLE_BAR asm_1 SEMICOLON
578 {
579 if (($1->value & 0xf800) == 0xc000)
580 {
581 if (is_group1 ($3) && is_group2 ($5))
582 $$ = bfin_gen_multi_instr ($1, $3, $5);
583 else if (is_group2 ($3) && is_group1 ($5))
584 $$ = bfin_gen_multi_instr ($1, $5, $3);
585 else
586 return yyerror ("Wrong 16 bit instructions groups, slot 2 and slot 3 must be 16-bit instrution group");
587 }
588 else if (($3->value & 0xf800) == 0xc000)
589 {
590 if (is_group1 ($1) && is_group2 ($5))
591 $$ = bfin_gen_multi_instr ($3, $1, $5);
592 else if (is_group2 ($1) && is_group1 ($5))
593 $$ = bfin_gen_multi_instr ($3, $5, $1);
594 else
595 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 3 must be 16-bit instrution group");
596 }
597 else if (($5->value & 0xf800) == 0xc000)
598 {
599 if (is_group1 ($1) && is_group2 ($3))
600 $$ = bfin_gen_multi_instr ($5, $1, $3);
601 else if (is_group2 ($1) && is_group1 ($3))
602 $$ = bfin_gen_multi_instr ($5, $3, $1);
603 else
604 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be 16-bit instrution group");
605 }
606 else
607 error ("\nIllegal Multi Issue Construct, at least any one of the slot must be DSP32 instruction group\n");
608 }
609
610 | asm_1 DOUBLE_BAR asm_1 SEMICOLON
611 {
612 if (($1->value & 0xf800) == 0xc000)
613 {
614 if (is_group1 ($3))
615 $$ = bfin_gen_multi_instr ($1, $3, 0);
616 else if (is_group2 ($3))
617 $$ = bfin_gen_multi_instr ($1, 0, $3);
618 else
619 return yyerror ("Wrong 16 bit instructions groups, slot 2 must be the 16-bit instruction group");
620 }
621 else if (($3->value & 0xf800) == 0xc000)
622 {
623 if (is_group1 ($1))
624 $$ = bfin_gen_multi_instr ($3, $1, 0);
625 else if (is_group2 ($1))
626 $$ = bfin_gen_multi_instr ($3, 0, $1);
627 else
628 return yyerror ("Wrong 16 bit instructions groups, slot 1 must be the 16-bit instruction group");
629 }
630 else if (is_group1 ($1) && is_group2 ($3))
631 $$ = bfin_gen_multi_instr (0, $1, $3);
632 else if (is_group2 ($1) && is_group1 ($3))
633 $$ = bfin_gen_multi_instr (0, $3, $1);
634 else
635 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be the 16-bit instruction group");
636 }
637 | error
638 {
639 $$ = 0;
640 yyerror ("");
641 yyerrok;
642 }
643 ;
644
645 /* DSPMAC. */
646
647 asm_1:
648 MNOP
649 {
650 $$ = DSP32MAC (3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0);
651 }
652 | assign_macfunc opt_mode
653 {
654 int op0, op1;
655 int w0 = 0, w1 = 0;
656 int h00, h10, h01, h11;
657
658 if ($1.n == 0)
659 {
660 if ($2.MM)
661 return yyerror ("(m) not allowed with a0 unit");
662 op1 = 3;
663 op0 = $1.op;
664 w1 = 0;
665 w0 = $1.w;
666 h00 = IS_H ($1.s0);
667 h10 = IS_H ($1.s1);
668 h01 = h11 = 0;
669 }
670 else
671 {
672 op1 = $1.op;
673 op0 = 3;
674 w1 = $1.w;
675 w0 = 0;
676 h00 = h10 = 0;
677 h01 = IS_H ($1.s0);
678 h11 = IS_H ($1.s1);
679 }
680 $$ = DSP32MAC (op1, $2.MM, $2.mod, w1, $1.P, h01, h11, h00, h10,
681 &$1.dst, op0, &$1.s0, &$1.s1, w0);
682 }
683
684
685 /* VECTOR MACs. */
686
687 | assign_macfunc opt_mode COMMA assign_macfunc opt_mode
688 {
689 Register *dst;
690
691 if (check_macfuncs (&$1, &$2, &$4, &$5) < 0)
692 return -1;
693 notethat ("assign_macfunc (.), assign_macfunc (.)\n");
694
695 if ($1.w)
696 dst = &$1.dst;
697 else
698 dst = &$4.dst;
699
700 $$ = DSP32MAC ($1.op, $2.MM, $5.mod, $1.w, $1.P,
701 IS_H ($1.s0), IS_H ($1.s1), IS_H ($4.s0), IS_H ($4.s1),
702 dst, $4.op, &$1.s0, &$1.s1, $4.w);
703 }
704
705 /* DSPALU. */
706
707 | DISALGNEXCPT
708 {
709 notethat ("dsp32alu: DISALGNEXCPT\n");
710 $$ = DSP32ALU (18, 0, 0, 0, 0, 0, 0, 0, 3);
711 }
712 | REG ASSIGN LPAREN a_plusassign REG_A RPAREN
713 {
714 if (IS_DREG ($1) && !IS_A1 ($4) && IS_A1 ($5))
715 {
716 notethat ("dsp32alu: dregs = ( A0 += A1 )\n");
717 $$ = DSP32ALU (11, 0, 0, &$1, 0, 0, 0, 0, 0);
718 }
719 else
720 return yyerror ("Register mismatch");
721 }
722 | HALF_REG ASSIGN LPAREN a_plusassign REG_A RPAREN
723 {
724 if (!IS_A1 ($4) && IS_A1 ($5))
725 {
726 notethat ("dsp32alu: dregs_half = ( A0 += A1 )\n");
727 $$ = DSP32ALU (11, IS_H ($1), 0, &$1, 0, 0, 0, 0, 1);
728 }
729 else
730 return yyerror ("Register mismatch");
731 }
732 | A_ZERO_DOT_H ASSIGN HALF_REG
733 {
734 notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
735 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
736 }
737 | A_ONE_DOT_H ASSIGN HALF_REG
738 {
739 notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
740 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
741 }
742 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16P LPAREN REG
743 COLON expr COMMA REG COLON expr RPAREN aligndir
744 {
745 if (!IS_DREG ($2) || !IS_DREG ($4))
746 return yyerror ("Dregs expected");
747 else if (!valid_dreg_pair (&$9, $11))
748 return yyerror ("Bad dreg pair");
749 else if (!valid_dreg_pair (&$13, $15))
750 return yyerror ("Bad dreg pair");
751 else
752 {
753 notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16P (dregs_pair , dregs_pair ) (half)\n");
754 $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 0);
755 }
756 }
757
758 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16M LPAREN REG COLON expr COMMA
759 REG COLON expr RPAREN aligndir
760 {
761 if (!IS_DREG ($2) || !IS_DREG($4))
762 return yyerror ("Dregs expected");
763 else if (!valid_dreg_pair (&$9, $11))
764 return yyerror ("Bad dreg pair");
765 else if (!valid_dreg_pair (&$13, $15))
766 return yyerror ("Bad dreg pair");
767 else
768 {
769 notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16M (dregs_pair , dregs_pair ) (aligndir)\n");
770 $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 1);
771 }
772 }
773
774 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEUNPACK REG COLON expr aligndir
775 {
776 if (!IS_DREG ($2) || !IS_DREG ($4))
777 return yyerror ("Dregs expected");
778 else if (!valid_dreg_pair (&$8, $10))
779 return yyerror ("Bad dreg pair");
780 else
781 {
782 notethat ("dsp32alu: (dregs , dregs ) = BYTEUNPACK dregs_pair (aligndir)\n");
783 $$ = DSP32ALU (24, 0, &$2, &$4, &$8, 0, $11.r0, 0, 1);
784 }
785 }
786 | LPAREN REG COMMA REG RPAREN ASSIGN SEARCH REG LPAREN searchmod RPAREN
787 {
788 if (IS_DREG ($2) && IS_DREG ($4) && IS_DREG ($8))
789 {
790 notethat ("dsp32alu: (dregs , dregs ) = SEARCH dregs (searchmod)\n");
791 $$ = DSP32ALU (13, 0, &$2, &$4, &$8, 0, 0, 0, $10.r0);
792 }
793 else
794 return yyerror ("Register mismatch");
795 }
796 | REG ASSIGN A_ONE_DOT_L PLUS A_ONE_DOT_H COMMA
797 REG ASSIGN A_ZERO_DOT_L PLUS A_ZERO_DOT_H
798 {
799 if (IS_DREG ($1) && IS_DREG ($7))
800 {
801 notethat ("dsp32alu: dregs = A1.l + A1.h, dregs = A0.l + A0.h \n");
802 $$ = DSP32ALU (12, 0, &$1, &$7, 0, 0, 0, 0, 1);
803 }
804 else
805 return yyerror ("Register mismatch");
806 }
807
808
809 | REG ASSIGN REG_A PLUS REG_A COMMA REG ASSIGN REG_A MINUS REG_A amod1
810 {
811 if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
812 && IS_A1 ($9) && !IS_A1 ($11))
813 {
814 notethat ("dsp32alu: dregs = A1 + A0 , dregs = A1 - A0 (amod1)\n");
815 $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 0);
816
817 }
818 else if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
819 && !IS_A1 ($9) && IS_A1 ($11))
820 {
821 notethat ("dsp32alu: dregs = A0 + A1 , dregs = A0 - A1 (amod1)\n");
822 $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 1);
823 }
824 else
825 return yyerror ("Register mismatch");
826 }
827
828 | REG ASSIGN REG plus_minus REG COMMA REG ASSIGN REG plus_minus REG amod1
829 {
830 if ($4.r0 == $10.r0)
831 return yyerror ("Operators must differ");
832
833 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5)
834 && REG_SAME ($3, $9) && REG_SAME ($5, $11))
835 {
836 notethat ("dsp32alu: dregs = dregs + dregs,"
837 "dregs = dregs - dregs (amod1)\n");
838 $$ = DSP32ALU (4, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, 2);
839 }
840 else
841 return yyerror ("Register mismatch");
842 }
843
844 /* Bar Operations. */
845
846 | REG ASSIGN REG op_bar_op REG COMMA REG ASSIGN REG op_bar_op REG amod2
847 {
848 if (!REG_SAME ($3, $9) || !REG_SAME ($5, $11))
849 return yyerror ("Differing source registers");
850
851 if (!IS_DREG ($1) || !IS_DREG ($3) || !IS_DREG ($5) || !IS_DREG ($7))
852 return yyerror ("Dregs expected");
853
854
855 if ($4.r0 == 1 && $10.r0 == 2)
856 {
857 notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
858 $$ = DSP32ALU (1, 1, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
859 }
860 else if ($4.r0 == 0 && $10.r0 == 3)
861 {
862 notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
863 $$ = DSP32ALU (1, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
864 }
865 else
866 return yyerror ("Bar operand mismatch");
867 }
868
869 | REG ASSIGN ABS REG vmod
870 {
871 int op;
872
873 if (IS_DREG ($1) && IS_DREG ($4))
874 {
875 if ($5.r0)
876 {
877 notethat ("dsp32alu: dregs = ABS dregs (v)\n");
878 op = 6;
879 }
880 else
881 {
882 /* Vector version of ABS. */
883 notethat ("dsp32alu: dregs = ABS dregs\n");
884 op = 7;
885 }
886 $$ = DSP32ALU (op, 0, 0, &$1, &$4, 0, 0, 0, 2);
887 }
888 else
889 return yyerror ("Dregs expected");
890 }
891 | a_assign ABS REG_A
892 {
893 notethat ("dsp32alu: Ax = ABS Ax\n");
894 $$ = DSP32ALU (16, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
895 }
896 | A_ZERO_DOT_L ASSIGN HALF_REG
897 {
898 if (IS_DREG_L ($3))
899 {
900 notethat ("dsp32alu: A0.l = reg_half\n");
901 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
902 }
903 else
904 return yyerror ("A0.l = Rx.l expected");
905 }
906 | A_ONE_DOT_L ASSIGN HALF_REG
907 {
908 if (IS_DREG_L ($3))
909 {
910 notethat ("dsp32alu: A1.l = reg_half\n");
911 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
912 }
913 else
914 return yyerror ("A1.l = Rx.l expected");
915 }
916
917 | REG ASSIGN c_align LPAREN REG COMMA REG RPAREN
918 {
919 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
920 {
921 notethat ("dsp32shift: dregs = ALIGN8 (dregs , dregs )\n");
922 $$ = DSP32SHIFT (13, &$1, &$7, &$5, $3.r0, 0);
923 }
924 else
925 return yyerror ("Dregs expected");
926 }
927
928 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN byteop_mod
929 {
930 if (!IS_DREG ($1))
931 return yyerror ("Dregs expected");
932 else if (!valid_dreg_pair (&$5, $7))
933 return yyerror ("Bad dreg pair");
934 else if (!valid_dreg_pair (&$9, $11))
935 return yyerror ("Bad dreg pair");
936 else
937 {
938 notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
939 $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, $13.s0, 0, $13.r0);
940 }
941 }
942 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
943 {
944 if (!IS_DREG ($1))
945 return yyerror ("Dregs expected");
946 else if (!valid_dreg_pair (&$5, $7))
947 return yyerror ("Bad dreg pair");
948 else if (!valid_dreg_pair (&$9, $11))
949 return yyerror ("Bad dreg pair");
950 else
951 {
952 notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
953 $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, 0, 0, 0);
954 }
955 }
956
957 | REG ASSIGN BYTEOP2P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
958 rnd_op
959 {
960 if (!IS_DREG ($1))
961 return yyerror ("Dregs expected");
962 else if (!valid_dreg_pair (&$5, $7))
963 return yyerror ("Bad dreg pair");
964 else if (!valid_dreg_pair (&$9, $11))
965 return yyerror ("Bad dreg pair");
966 else
967 {
968 notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
969 $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, $13.x0, $13.aop);
970 }
971 }
972
973 | REG ASSIGN BYTEOP2M LPAREN REG COLON expr COMMA REG COLON expr RPAREN
974 rnd_op
975 {
976 if (!IS_DREG ($1))
977 return yyerror ("Dregs expected");
978 else if (!valid_dreg_pair (&$5, $7))
979 return yyerror ("Bad dreg pair");
980 else if (!valid_dreg_pair (&$9, $11))
981 return yyerror ("Bad dreg pair");
982 else
983 {
984 notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
985 $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, 0, $13.x0);
986 }
987 }
988
989 | REG ASSIGN BYTEOP3P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
990 b3_op
991 {
992 if (!IS_DREG ($1))
993 return yyerror ("Dregs expected");
994 else if (!valid_dreg_pair (&$5, $7))
995 return yyerror ("Bad dreg pair");
996 else if (!valid_dreg_pair (&$9, $11))
997 return yyerror ("Bad dreg pair");
998 else
999 {
1000 notethat ("dsp32alu: dregs = BYTEOP3P (dregs_pair , dregs_pair ) (b3_op)\n");
1001 $$ = DSP32ALU (23, $13.x0, 0, &$1, &$5, &$9, $13.s0, 0, 0);
1002 }
1003 }
1004
1005 | REG ASSIGN BYTEPACK LPAREN REG COMMA REG RPAREN
1006 {
1007 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1008 {
1009 notethat ("dsp32alu: dregs = BYTEPACK (dregs , dregs )\n");
1010 $$ = DSP32ALU (24, 0, 0, &$1, &$5, &$7, 0, 0, 0);
1011 }
1012 else
1013 return yyerror ("Dregs expected");
1014 }
1015
1016 | HALF_REG ASSIGN HALF_REG ASSIGN SIGN LPAREN HALF_REG RPAREN STAR
1017 HALF_REG PLUS SIGN LPAREN HALF_REG RPAREN STAR HALF_REG
1018 {
1019 if (IS_HCOMPL ($1, $3) && IS_HCOMPL ($7, $14) && IS_HCOMPL ($10, $17))
1020 {
1021 notethat ("dsp32alu: dregs_hi = dregs_lo ="
1022 "SIGN (dregs_hi) * dregs_hi + "
1023 "SIGN (dregs_lo) * dregs_lo \n");
1024
1025 $$ = DSP32ALU (12, 0, 0, &$1, &$7, &$10, 0, 0, 0);
1026 }
1027 else
1028 return yyerror ("Dregs expected");
1029 }
1030 | REG ASSIGN REG plus_minus REG amod1
1031 {
1032 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1033 {
1034 if ($6.aop == 0)
1035 {
1036 /* No saturation flag specified, generate the 16 bit variant. */
1037 notethat ("COMP3op: dregs = dregs +- dregs\n");
1038 $$ = COMP3OP (&$1, &$3, &$5, $4.r0);
1039 }
1040 else
1041 {
1042 /* Saturation flag specified, generate the 32 bit variant. */
1043 notethat ("dsp32alu: dregs = dregs +- dregs (amod1)\n");
1044 $$ = DSP32ALU (4, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1045 }
1046 }
1047 else
1048 if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($5) && $4.r0 == 0)
1049 {
1050 notethat ("COMP3op: pregs = pregs + pregs\n");
1051 $$ = COMP3OP (&$1, &$3, &$5, 5);
1052 }
1053 else
1054 return yyerror ("Dregs expected");
1055 }
1056 | REG ASSIGN min_max LPAREN REG COMMA REG RPAREN vmod
1057 {
1058 int op;
1059
1060 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1061 {
1062 if ($9.r0)
1063 op = 6;
1064 else
1065 op = 7;
1066
1067 notethat ("dsp32alu: dregs = {MIN|MAX} (dregs, dregs)\n");
1068 $$ = DSP32ALU (op, 0, 0, &$1, &$5, &$7, 0, 0, $3.r0);
1069 }
1070 else
1071 return yyerror ("Dregs expected");
1072 }
1073
1074 | a_assign MINUS REG_A
1075 {
1076 notethat ("dsp32alu: Ax = - Ax\n");
1077 $$ = DSP32ALU (14, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
1078 }
1079 | HALF_REG ASSIGN HALF_REG plus_minus HALF_REG amod1
1080 {
1081 notethat ("dsp32alu: dregs_lo = dregs_lo +- dregs_lo (amod1)\n");
1082 $$ = DSP32ALU (2 | $4.r0, IS_H ($1), 0, &$1, &$3, &$5,
1083 $6.s0, $6.x0, HL2 ($3, $5));
1084 }
1085 | a_assign a_assign expr
1086 {
1087 if (EXPR_VALUE ($3) == 0 && !REG_SAME ($1, $2))
1088 {
1089 notethat ("dsp32alu: A1 = A0 = 0\n");
1090 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, 2);
1091 }
1092 else
1093 return yyerror ("Bad value, 0 expected");
1094 }
1095
1096 /* Saturating. */
1097 | a_assign REG_A LPAREN S RPAREN
1098 {
1099 if (REG_SAME ($1, $2))
1100 {
1101 notethat ("dsp32alu: Ax = Ax (S)\n");
1102 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, IS_A1 ($1));
1103 }
1104 else
1105 return yyerror ("Registers must be equal");
1106 }
1107
1108 | HALF_REG ASSIGN REG LPAREN RND RPAREN
1109 {
1110 if (IS_DREG ($3))
1111 {
1112 notethat ("dsp32alu: dregs_half = dregs (RND)\n");
1113 $$ = DSP32ALU (12, IS_H ($1), 0, &$1, &$3, 0, 0, 0, 3);
1114 }
1115 else
1116 return yyerror ("Dregs expected");
1117 }
1118
1119 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND12 RPAREN
1120 {
1121 if (IS_DREG ($3) && IS_DREG ($5))
1122 {
1123 notethat ("dsp32alu: dregs_half = dregs (+-) dregs (RND12)\n");
1124 $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 0, $4.r0);
1125 }
1126 else
1127 return yyerror ("Dregs expected");
1128 }
1129
1130 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND20 RPAREN
1131 {
1132 if (IS_DREG ($3) && IS_DREG ($5))
1133 {
1134 notethat ("dsp32alu: dregs_half = dregs -+ dregs (RND20)\n");
1135 $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 1, $4.r0 | 2);
1136 }
1137 else
1138 return yyerror ("Dregs expected");
1139 }
1140
1141 | a_assign REG_A
1142 {
1143 if (!REG_SAME ($1, $2))
1144 {
1145 notethat ("dsp32alu: An = Am\n");
1146 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, IS_A1 ($1), 0, 3);
1147 }
1148 else
1149 return yyerror ("Accu reg arguments must differ");
1150 }
1151
1152 | a_assign REG
1153 {
1154 if (IS_DREG ($2))
1155 {
1156 notethat ("dsp32alu: An = dregs\n");
1157 $$ = DSP32ALU (9, 0, 0, 0, &$2, 0, 1, 0, IS_A1 ($1) << 1);
1158 }
1159 else
1160 return yyerror ("Dregs expected");
1161 }
1162
1163 | REG ASSIGN HALF_REG xpmod
1164 {
1165 if (!IS_H ($3))
1166 {
1167 if ($1.regno == REG_A0x && IS_DREG ($3))
1168 {
1169 notethat ("dsp32alu: A0.x = dregs_lo\n");
1170 $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 1);
1171 }
1172 else if ($1.regno == REG_A1x && IS_DREG ($3))
1173 {
1174 notethat ("dsp32alu: A1.x = dregs_lo\n");
1175 $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 3);
1176 }
1177 else if (IS_DREG ($1) && IS_DREG ($3))
1178 {
1179 notethat ("ALU2op: dregs = dregs_lo\n");
1180 $$ = ALU2OP (&$1, &$3, 10 | ($4.r0 ? 0: 1));
1181 }
1182 else
1183 return yyerror ("Register mismatch");
1184 }
1185 else
1186 return yyerror ("Low reg expected");
1187 }
1188
1189 | HALF_REG ASSIGN expr
1190 {
1191 notethat ("LDIMMhalf: pregs_half = imm16\n");
1192 if (!IS_IMM ($3, 16) && !IS_UIMM ($3, 16))
1193 return yyerror ("Constant out of range");
1194 $$ = LDIMMHALF_R (&$1, IS_H ($1), 0, 0, $3);
1195 }
1196
1197 | a_assign expr
1198 {
1199 notethat ("dsp32alu: An = 0\n");
1200
1201 if (imm7 ($2) != 0)
1202 return yyerror ("0 expected");
1203
1204 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, IS_A1 ($1));
1205 }
1206
1207 | REG ASSIGN expr xpmod1
1208 {
1209 if ($4.r0 == 0)
1210 {
1211 /* 7 bit immediate value if possible.
1212 We will check for that constant value for efficiency
1213 If it goes to reloc, it will be 16 bit. */
1214 if (IS_CONST ($3) && IS_IMM ($3, 7) && (IS_DREG ($1) || IS_PREG ($1)))
1215 {
1216 /* if the expr is a relocation, generate it. */
1217 if (IS_DREG ($1) && IS_IMM ($3, 7))
1218 {
1219 notethat ("COMPI2opD: dregs = imm7 (x) \n");
1220 $$ = COMPI2OPD (&$1, imm7 ($3), 0);
1221 }
1222 else if (IS_PREG ($1) && IS_IMM ($3, 7))
1223 {
1224 notethat ("COMPI2opP: pregs = imm7 (x)\n");
1225 $$ = COMPI2OPP (&$1, imm7 ($3), 0);
1226 }
1227 else
1228 return yyerror ("Bad register or value for assigment");
1229 }
1230 else
1231 {
1232 notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1233 /* reg, H, S, Z. */
1234 $$ = LDIMMHALF_R5 (&$1, 0, 1, 0, $3);
1235 }
1236 }
1237 else
1238 {
1239 /* (z) There is no 7 bit zero extended instruction.
1240 If the expr is a relocation, generate it. */
1241 notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1242 /* reg, H, S, Z. */
1243 $$ = LDIMMHALF_R5 (&$1, 0, 0, 1, $3);
1244 }
1245 }
1246
1247 | HALF_REG ASSIGN REG
1248 {
1249 if (IS_H ($1))
1250 return yyerror ("Low reg expected");
1251
1252 if (IS_DREG ($1) && $3.regno == REG_A0x)
1253 {
1254 notethat ("dsp32alu: dregs_lo = A0.x\n");
1255 $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 0);
1256 }
1257 else if (IS_DREG ($1) && $3.regno == REG_A1x)
1258 {
1259 notethat ("dsp32alu: dregs_lo = A1.x\n");
1260 $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 1);
1261 }
1262 else
1263 return yyerror ("Register mismatch");
1264 }
1265
1266 | REG ASSIGN REG op_bar_op REG amod0
1267 {
1268 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1269 {
1270 notethat ("dsp32alu: dregs = dregs .|. dregs (amod0)\n");
1271 $$ = DSP32ALU (0, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1272 }
1273 else
1274 return yyerror ("Register mismatch");
1275 }
1276
1277 | REG ASSIGN BYTE_DREG xpmod
1278 {
1279 if (IS_DREG ($1) && IS_DREG ($3))
1280 {
1281 notethat ("ALU2op: dregs = dregs_byte\n");
1282 $$ = ALU2OP (&$1, &$3, 12 | ($4.r0 ? 0: 1));
1283 }
1284 else
1285 return yyerror ("Register mismatch");
1286 }
1287
1288 | a_assign ABS REG_A COMMA a_assign ABS REG_A
1289 {
1290 if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1291 {
1292 notethat ("dsp32alu: A1 = ABS A1 , A0 = ABS A0\n");
1293 $$ = DSP32ALU (16, 0, 0, 0, 0, 0, 0, 0, 3);
1294 }
1295 else
1296 return yyerror ("Register mismatch");
1297 }
1298
1299 | a_assign MINUS REG_A COMMA a_assign MINUS REG_A
1300 {
1301 if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1302 {
1303 notethat ("dsp32alu: A1 = - A1 , A0 = - A0\n");
1304 $$ = DSP32ALU (14, 0, 0, 0, 0, 0, 0, 0, 3);
1305 }
1306 else
1307 return yyerror ("Register mismatch");
1308 }
1309
1310 | a_minusassign REG_A w32_or_nothing
1311 {
1312 if (!IS_A1 ($1) && IS_A1 ($2))
1313 {
1314 notethat ("dsp32alu: A0 -= A1\n");
1315 $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $3.r0, 0, 3);
1316 }
1317 else
1318 return yyerror ("Register mismatch");
1319 }
1320
1321 | REG _MINUS_ASSIGN expr
1322 {
1323 if (IS_IREG ($1) && EXPR_VALUE ($3) == 4)
1324 {
1325 notethat ("dagMODik: iregs -= 4\n");
1326 $$ = DAGMODIK (&$1, 3);
1327 }
1328 else if (IS_IREG ($1) && EXPR_VALUE ($3) == 2)
1329 {
1330 notethat ("dagMODik: iregs -= 2\n");
1331 $$ = DAGMODIK (&$1, 1);
1332 }
1333 else
1334 return yyerror ("Register or value mismatch");
1335 }
1336
1337 | REG _PLUS_ASSIGN REG LPAREN BREV RPAREN
1338 {
1339 if (IS_IREG ($1) && IS_MREG ($3))
1340 {
1341 notethat ("dagMODim: iregs += mregs (opt_brev)\n");
1342 /* i, m, op, br. */
1343 $$ = DAGMODIM (&$1, &$3, 0, 1);
1344 }
1345 else if (IS_PREG ($1) && IS_PREG ($3))
1346 {
1347 notethat ("PTR2op: pregs += pregs (BREV )\n");
1348 $$ = PTR2OP (&$1, &$3, 5);
1349 }
1350 else
1351 return yyerror ("Register mismatch");
1352 }
1353
1354 | REG _MINUS_ASSIGN REG
1355 {
1356 if (IS_IREG ($1) && IS_MREG ($3))
1357 {
1358 notethat ("dagMODim: iregs -= mregs\n");
1359 $$ = DAGMODIM (&$1, &$3, 1, 0);
1360 }
1361 else if (IS_PREG ($1) && IS_PREG ($3))
1362 {
1363 notethat ("PTR2op: pregs -= pregs\n");
1364 $$ = PTR2OP (&$1, &$3, 0);
1365 }
1366 else
1367 return yyerror ("Register mismatch");
1368 }
1369
1370 | REG_A _PLUS_ASSIGN REG_A w32_or_nothing
1371 {
1372 if (!IS_A1 ($1) && IS_A1 ($3))
1373 {
1374 notethat ("dsp32alu: A0 += A1 (W32)\n");
1375 $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $4.r0, 0, 2);
1376 }
1377 else
1378 return yyerror ("Register mismatch");
1379 }
1380
1381 | REG _PLUS_ASSIGN REG
1382 {
1383 if (IS_IREG ($1) && IS_MREG ($3))
1384 {
1385 notethat ("dagMODim: iregs += mregs\n");
1386 $$ = DAGMODIM (&$1, &$3, 0, 0);
1387 }
1388 else
1389 return yyerror ("iregs += mregs expected");
1390 }
1391
1392 | REG _PLUS_ASSIGN expr
1393 {
1394 if (IS_IREG ($1))
1395 {
1396 if (EXPR_VALUE ($3) == 4)
1397 {
1398 notethat ("dagMODik: iregs += 4\n");
1399 $$ = DAGMODIK (&$1, 2);
1400 }
1401 else if (EXPR_VALUE ($3) == 2)
1402 {
1403 notethat ("dagMODik: iregs += 2\n");
1404 $$ = DAGMODIK (&$1, 0);
1405 }
1406 else
1407 return yyerror ("iregs += [ 2 | 4 ");
1408 }
1409 else if (IS_PREG ($1) && IS_IMM ($3, 7))
1410 {
1411 notethat ("COMPI2opP: pregs += imm7\n");
1412 $$ = COMPI2OPP (&$1, imm7 ($3), 1);
1413 }
1414 else if (IS_DREG ($1) && IS_IMM ($3, 7))
1415 {
1416 notethat ("COMPI2opD: dregs += imm7\n");
1417 $$ = COMPI2OPD (&$1, imm7 ($3), 1);
1418 }
1419 else
1420 return yyerror ("Register mismatch");
1421 }
1422
1423 | REG _STAR_ASSIGN REG
1424 {
1425 if (IS_DREG ($1) && IS_DREG ($3))
1426 {
1427 notethat ("ALU2op: dregs *= dregs\n");
1428 $$ = ALU2OP (&$1, &$3, 3);
1429 }
1430 else
1431 return yyerror ("Register mismatch");
1432 }
1433
1434 | SAA LPAREN REG COLON expr COMMA REG COLON expr RPAREN aligndir
1435 {
1436 if (!valid_dreg_pair (&$3, $5))
1437 return yyerror ("Bad dreg pair");
1438 else if (!valid_dreg_pair (&$7, $9))
1439 return yyerror ("Bad dreg pair");
1440 else
1441 {
1442 notethat ("dsp32alu: SAA (dregs_pair , dregs_pair ) (aligndir)\n");
1443 $$ = DSP32ALU (18, 0, 0, 0, &$3, &$7, $11.r0, 0, 0);
1444 }
1445 }
1446
1447 | a_assign REG_A LPAREN S RPAREN COMMA a_assign REG_A LPAREN S RPAREN
1448 {
1449 if (REG_SAME ($1, $2) && REG_SAME ($7, $8) && !REG_SAME ($1, $7))
1450 {
1451 notethat ("dsp32alu: A1 = A1 (S) , A0 = A0 (S)\n");
1452 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, 2);
1453 }
1454 else
1455 return yyerror ("Register mismatch");
1456 }
1457
1458 | REG ASSIGN LPAREN REG PLUS REG RPAREN LESS_LESS expr
1459 {
1460 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6)
1461 && REG_SAME ($1, $4))
1462 {
1463 if (EXPR_VALUE ($9) == 1)
1464 {
1465 notethat ("ALU2op: dregs = (dregs + dregs) << 1\n");
1466 $$ = ALU2OP (&$1, &$6, 4);
1467 }
1468 else if (EXPR_VALUE ($9) == 2)
1469 {
1470 notethat ("ALU2op: dregs = (dregs + dregs) << 2\n");
1471 $$ = ALU2OP (&$1, &$6, 5);
1472 }
1473 else
1474 return yyerror ("Bad shift value");
1475 }
1476 else if (IS_PREG ($1) && IS_PREG ($4) && IS_PREG ($6)
1477 && REG_SAME ($1, $4))
1478 {
1479 if (EXPR_VALUE ($9) == 1)
1480 {
1481 notethat ("PTR2op: pregs = (pregs + pregs) << 1\n");
1482 $$ = PTR2OP (&$1, &$6, 6);
1483 }
1484 else if (EXPR_VALUE ($9) == 2)
1485 {
1486 notethat ("PTR2op: pregs = (pregs + pregs) << 2\n");
1487 $$ = PTR2OP (&$1, &$6, 7);
1488 }
1489 else
1490 return yyerror ("Bad shift value");
1491 }
1492 else
1493 return yyerror ("Register mismatch");
1494 }
1495
1496 /* COMP3 CCFLAG. */
1497 | REG ASSIGN REG BAR REG
1498 {
1499 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1500 {
1501 notethat ("COMP3op: dregs = dregs | dregs\n");
1502 $$ = COMP3OP (&$1, &$3, &$5, 3);
1503 }
1504 else
1505 return yyerror ("Dregs expected");
1506 }
1507 | REG ASSIGN REG CARET REG
1508 {
1509 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1510 {
1511 notethat ("COMP3op: dregs = dregs ^ dregs\n");
1512 $$ = COMP3OP (&$1, &$3, &$5, 4);
1513 }
1514 else
1515 return yyerror ("Dregs expected");
1516 }
1517 | REG ASSIGN REG PLUS LPAREN REG LESS_LESS expr RPAREN
1518 {
1519 if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($6))
1520 {
1521 if (EXPR_VALUE ($8) == 1)
1522 {
1523 notethat ("COMP3op: pregs = pregs + (pregs << 1)\n");
1524 $$ = COMP3OP (&$1, &$3, &$6, 6);
1525 }
1526 else if (EXPR_VALUE ($8) == 2)
1527 {
1528 notethat ("COMP3op: pregs = pregs + (pregs << 2)\n");
1529 $$ = COMP3OP (&$1, &$3, &$6, 7);
1530 }
1531 else
1532 return yyerror ("Bad shift value");
1533 }
1534 else
1535 return yyerror ("Dregs expected");
1536 }
1537 | CCREG ASSIGN REG_A _ASSIGN_ASSIGN REG_A
1538 {
1539 if (!REG_SAME ($3, $5))
1540 {
1541 notethat ("CCflag: CC = A0 == A1\n");
1542 $$ = CCFLAG (0, 0, 5, 0, 0);
1543 }
1544 else
1545 return yyerror ("CC register expected");
1546 }
1547 | CCREG ASSIGN REG_A LESS_THAN REG_A
1548 {
1549 if (!REG_SAME ($3, $5))
1550 {
1551 notethat ("CCflag: CC = A0 < A1\n");
1552 $$ = CCFLAG (0, 0, 6, 0, 0);
1553 }
1554 else
1555 return yyerror ("Register mismatch");
1556 }
1557 | CCREG ASSIGN REG LESS_THAN REG iu_or_nothing
1558 {
1559 if (REG_CLASS($3) == REG_CLASS($5))
1560 {
1561 notethat ("CCflag: CC = dpregs < dpregs\n");
1562 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1563 }
1564 else
1565 return yyerror ("Compare only of same register class");
1566 }
1567 | CCREG ASSIGN REG LESS_THAN expr iu_or_nothing
1568 {
1569 if (($6.r0 == 1 && IS_IMM ($5, 3))
1570 || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1571 {
1572 notethat ("CCflag: CC = dpregs < (u)imm3\n");
1573 $$ = CCFLAG (&$3, imm3 ($5), $6.r0, 1, IS_PREG ($3) ? 1 : 0);
1574 }
1575 else
1576 return yyerror ("Bad constant value");
1577 }
1578 | CCREG ASSIGN REG _ASSIGN_ASSIGN REG
1579 {
1580 if (REG_CLASS($3) == REG_CLASS($5))
1581 {
1582 notethat ("CCflag: CC = dpregs == dpregs\n");
1583 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, 0, 0, IS_PREG ($3) ? 1 : 0);
1584 }
1585 }
1586 | CCREG ASSIGN REG _ASSIGN_ASSIGN expr
1587 {
1588 if (IS_IMM ($5, 3))
1589 {
1590 notethat ("CCflag: CC = dpregs == imm3\n");
1591 $$ = CCFLAG (&$3, imm3 ($5), 0, 1, IS_PREG ($3) ? 1 : 0);
1592 }
1593 else
1594 return yyerror ("Bad constant range");
1595 }
1596 | CCREG ASSIGN REG_A _LESS_THAN_ASSIGN REG_A
1597 {
1598 if (!REG_SAME ($3, $5))
1599 {
1600 notethat ("CCflag: CC = A0 <= A1\n");
1601 $$ = CCFLAG (0, 0, 7, 0, 0);
1602 }
1603 else
1604 return yyerror ("CC register expected");
1605 }
1606 | CCREG ASSIGN REG _LESS_THAN_ASSIGN REG iu_or_nothing
1607 {
1608 if (REG_CLASS($3) == REG_CLASS($5))
1609 {
1610 notethat ("CCflag: CC = pregs <= pregs (..)\n");
1611 $$ = CCFLAG (&$3, $5.regno & CODE_MASK,
1612 1 + $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1613 }
1614 else
1615 return yyerror ("Compare only of same register class");
1616 }
1617 | CCREG ASSIGN REG _LESS_THAN_ASSIGN expr iu_or_nothing
1618 {
1619 if (($6.r0 == 1 && IS_IMM ($5, 3))
1620 || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1621 {
1622 if (IS_DREG ($3))
1623 {
1624 notethat ("CCflag: CC = dregs <= (u)imm3\n");
1625 /* x y opc I G */
1626 $$ = CCFLAG (&$3, imm3 ($5), 1 + $6.r0, 1, 0);
1627 }
1628 else if (IS_PREG ($3))
1629 {
1630 notethat ("CCflag: CC = pregs <= (u)imm3\n");
1631 /* x y opc I G */
1632 $$ = CCFLAG (&$3, imm3 ($5), 1 + $6.r0, 1, 1);
1633 }
1634 else
1635 return yyerror ("Dreg or Preg expected");
1636 }
1637 else
1638 return yyerror ("Bad constant value");
1639 }
1640
1641 | REG ASSIGN REG AMPERSAND REG
1642 {
1643 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1644 {
1645 notethat ("COMP3op: dregs = dregs & dregs\n");
1646 $$ = COMP3OP (&$1, &$3, &$5, 2);
1647 }
1648 else
1649 return yyerror ("Dregs expected");
1650 }
1651
1652 | ccstat
1653 {
1654 notethat ("CC2stat operation\n");
1655 $$ = bfin_gen_cc2stat ($1.r0, $1.x0, $1.s0);
1656 }
1657
1658 | REG ASSIGN REG
1659 {
1660 if (IS_ALLREG ($1) && IS_ALLREG ($3))
1661 {
1662 notethat ("REGMV: allregs = allregs\n");
1663 $$ = bfin_gen_regmv (&$3, &$1);
1664 }
1665 else
1666 return yyerror ("Register mismatch");
1667 }
1668
1669 | CCREG ASSIGN REG
1670 {
1671 if (IS_DREG ($3))
1672 {
1673 notethat ("CC2dreg: CC = dregs\n");
1674 $$ = bfin_gen_cc2dreg (1, &$3);
1675 }
1676 else
1677 return yyerror ("Register mismatch");
1678 }
1679
1680 | REG ASSIGN CCREG
1681 {
1682 if (IS_DREG ($1))
1683 {
1684 notethat ("CC2dreg: dregs = CC\n");
1685 $$ = bfin_gen_cc2dreg (0, &$1);
1686 }
1687 else
1688 return yyerror ("Register mismatch");
1689 }
1690
1691 | CCREG _ASSIGN_BANG CCREG
1692 {
1693 notethat ("CC2dreg: CC =! CC\n");
1694 $$ = bfin_gen_cc2dreg (3, 0);
1695 }
1696
1697 /* DSPMULT. */
1698
1699 | HALF_REG ASSIGN multiply_halfregs opt_mode
1700 {
1701 notethat ("dsp32mult: dregs_half = multiply_halfregs (opt_mode)\n");
1702
1703 if (!IS_H ($1) && $4.MM)
1704 return yyerror ("(M) not allowed with MAC0");
1705
1706 if (IS_H ($1))
1707 {
1708 $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 0,
1709 IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1710 &$1, 0, &$3.s0, &$3.s1, 0);
1711 }
1712 else
1713 {
1714 $$ = DSP32MULT (0, 0, $4.mod, 0, 0,
1715 0, 0, IS_H ($3.s0), IS_H ($3.s1),
1716 &$1, 0, &$3.s0, &$3.s1, 1);
1717 }
1718 }
1719
1720 | REG ASSIGN multiply_halfregs opt_mode
1721 {
1722 /* Odd registers can use (M). */
1723 if (!IS_DREG ($1))
1724 return yyerror ("Dreg expected");
1725
1726 if (!IS_EVEN ($1))
1727 {
1728 notethat ("dsp32mult: dregs = multiply_halfregs (opt_mode)\n");
1729
1730 $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 1,
1731 IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1732 &$1, 0, &$3.s0, &$3.s1, 0);
1733 }
1734 else if ($4.MM == 0)
1735 {
1736 notethat ("dsp32mult: dregs = multiply_halfregs opt_mode\n");
1737 $$ = DSP32MULT (0, 0, $4.mod, 0, 1,
1738 0, 0, IS_H ($3.s0), IS_H ($3.s1),
1739 &$1, 0, &$3.s0, &$3.s1, 1);
1740 }
1741 else
1742 return yyerror ("Register or mode mismatch");
1743 }
1744
1745 | HALF_REG ASSIGN multiply_halfregs opt_mode COMMA
1746 HALF_REG ASSIGN multiply_halfregs opt_mode
1747 {
1748 if (!IS_DREG ($1) || !IS_DREG ($6))
1749 return yyerror ("Dregs expected");
1750
1751 if (check_multiply_halfregs (&$3, &$8) < 0)
1752 return -1;
1753
1754 if (IS_H ($1) && !IS_H ($6))
1755 {
1756 notethat ("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, "
1757 "dregs_lo = multiply_halfregs opt_mode\n");
1758 $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 0,
1759 IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1760 &$1, 0, &$3.s0, &$3.s1, 1);
1761 }
1762 else if (!IS_H ($1) && IS_H ($6) && $4.MM == 0)
1763 {
1764 $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 0,
1765 IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1766 &$1, 0, &$3.s0, &$3.s1, 1);
1767 }
1768 else
1769 return yyerror ("Multfunc Register or mode mismatch");
1770 }
1771
1772 | REG ASSIGN multiply_halfregs opt_mode COMMA REG ASSIGN multiply_halfregs opt_mode
1773 {
1774 if (!IS_DREG ($1) || !IS_DREG ($6))
1775 return yyerror ("Dregs expected");
1776
1777 if (check_multiply_halfregs (&$3, &$8) < 0)
1778 return -1;
1779
1780 notethat ("dsp32mult: dregs = multiply_halfregs mxd_mod, "
1781 "dregs = multiply_halfregs opt_mode\n");
1782 if (IS_EVEN ($1))
1783 {
1784 if ($6.regno - $1.regno != 1 || $4.MM != 0)
1785 return yyerror ("Dest registers or mode mismatch");
1786
1787 /* op1 MM mmod */
1788 $$ = DSP32MULT (0, 0, $9.mod, 1, 1,
1789 IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1790 &$1, 0, &$3.s0, &$3.s1, 1);
1791
1792 }
1793 else
1794 {
1795 if ($1.regno - $6.regno != 1)
1796 return yyerror ("Dest registers mismatch");
1797
1798 $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 1,
1799 IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1800 &$1, 0, &$3.s0, &$3.s1, 1);
1801 }
1802 }
1803
1804 \f
1805 /* SHIFTs. */
1806 | a_assign ASHIFT REG_A BY HALF_REG
1807 {
1808 if (!REG_SAME ($1, $3))
1809 return yyerror ("Aregs must be same");
1810
1811 if (IS_DREG ($5) && !IS_H ($5))
1812 {
1813 notethat ("dsp32shift: A0 = ASHIFT A0 BY dregs_lo\n");
1814 $$ = DSP32SHIFT (3, 0, &$5, 0, 0, IS_A1 ($1));
1815 }
1816 else
1817 return yyerror ("Dregs expected");
1818 }
1819
1820 | HALF_REG ASSIGN ASHIFT HALF_REG BY HALF_REG smod
1821 {
1822 if (IS_DREG ($6) && !IS_H ($6))
1823 {
1824 notethat ("dsp32shift: dregs_half = ASHIFT dregs_half BY dregs_lo\n");
1825 $$ = DSP32SHIFT (0, &$1, &$6, &$4, $7.s0, HL2 ($1, $4));
1826 }
1827 else
1828 return yyerror ("Dregs expected");
1829 }
1830
1831 | a_assign REG_A LESS_LESS expr
1832 {
1833 if (!REG_SAME ($1, $2))
1834 return yyerror ("Aregs must be same");
1835
1836 if (IS_UIMM ($4, 5))
1837 {
1838 notethat ("dsp32shiftimm: A0 = A0 << uimm5\n");
1839 $$ = DSP32SHIFTIMM (3, 0, imm5 ($4), 0, 0, IS_A1 ($1));
1840 }
1841 else
1842 return yyerror ("Bad shift value");
1843 }
1844
1845 | REG ASSIGN REG LESS_LESS expr vsmod
1846 {
1847 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
1848 {
1849 if ($6.r0)
1850 {
1851 /* Vector? */
1852 notethat ("dsp32shiftimm: dregs = dregs << expr (V, .)\n");
1853 $$ = DSP32SHIFTIMM (1, &$1, imm4 ($5), &$3, $6.s0 ? 1 : 2, 0);
1854 }
1855 else
1856 {
1857 notethat ("dsp32shiftimm: dregs = dregs << uimm5 (.)\n");
1858 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($5), &$3, $6.s0 ? 1 : 2, 0);
1859 }
1860 }
1861 else if ($6.s0 == 0 && IS_PREG ($1) && IS_PREG ($3))
1862 {
1863 if (EXPR_VALUE ($5) == 2)
1864 {
1865 notethat ("PTR2op: pregs = pregs << 2\n");
1866 $$ = PTR2OP (&$1, &$3, 1);
1867 }
1868 else if (EXPR_VALUE ($5) == 1)
1869 {
1870 notethat ("COMP3op: pregs = pregs << 1\n");
1871 $$ = COMP3OP (&$1, &$3, &$3, 5);
1872 }
1873 else
1874 return yyerror ("Bad shift value");
1875 }
1876 else
1877 return yyerror ("Bad shift value or register");
1878 }
1879 | HALF_REG ASSIGN HALF_REG LESS_LESS expr
1880 {
1881 if (IS_UIMM ($5, 4))
1882 {
1883 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
1884 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3));
1885 }
1886 else
1887 return yyerror ("Bad shift value");
1888 }
1889 | HALF_REG ASSIGN HALF_REG LESS_LESS expr smod
1890 {
1891 if (IS_UIMM ($5, 4))
1892 {
1893 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
1894 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3));
1895 }
1896 else
1897 return yyerror ("Bad shift value");
1898 }
1899 | REG ASSIGN ASHIFT REG BY HALF_REG vsmod
1900 {
1901 int op;
1902
1903 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6) && !IS_H ($6))
1904 {
1905 if ($7.r0)
1906 {
1907 op = 1;
1908 notethat ("dsp32shift: dregs = ASHIFT dregs BY "
1909 "dregs_lo (V, .)\n");
1910 }
1911 else
1912 {
1913
1914 op = 2;
1915 notethat ("dsp32shift: dregs = ASHIFT dregs BY dregs_lo (.)\n");
1916 }
1917 $$ = DSP32SHIFT (op, &$1, &$6, &$4, $7.s0, 0);
1918 }
1919 else
1920 return yyerror ("Dregs expected");
1921 }
1922
1923 /* EXPADJ. */
1924 | HALF_REG ASSIGN EXPADJ LPAREN REG COMMA HALF_REG RPAREN vmod
1925 {
1926 if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
1927 {
1928 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs , dregs_lo )\n");
1929 $$ = DSP32SHIFT (7, &$1, &$7, &$5, $9.r0, 0);
1930 }
1931 else
1932 return yyerror ("Bad shift value or register");
1933 }
1934
1935
1936 | HALF_REG ASSIGN EXPADJ LPAREN HALF_REG COMMA HALF_REG RPAREN
1937 {
1938 if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
1939 {
1940 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_lo, dregs_lo)\n");
1941 $$ = DSP32SHIFT (7, &$1, &$7, &$5, 2, 0);
1942 }
1943 else if (IS_DREG_L ($1) && IS_DREG_H ($5) && IS_DREG_L ($7))
1944 {
1945 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_hi, dregs_lo)\n");
1946 $$ = DSP32SHIFT (7, &$1, &$7, &$5, 3, 0);
1947 }
1948 else
1949 return yyerror ("Bad shift value or register");
1950 }
1951
1952 /* DEPOSIT. */
1953
1954 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN
1955 {
1956 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1957 {
1958 notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs )\n");
1959 $$ = DSP32SHIFT (10, &$1, &$7, &$5, 2, 0);
1960 }
1961 else
1962 return yyerror ("Register mismatch");
1963 }
1964
1965 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN LPAREN X RPAREN
1966 {
1967 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1968 {
1969 notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs ) (X)\n");
1970 $$ = DSP32SHIFT (10, &$1, &$7, &$5, 3, 0);
1971 }
1972 else
1973 return yyerror ("Register mismatch");
1974 }
1975
1976 | REG ASSIGN EXTRACT LPAREN REG COMMA HALF_REG RPAREN xpmod
1977 {
1978 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG_L ($7))
1979 {
1980 notethat ("dsp32shift: dregs = EXTRACT (dregs, dregs_lo ) (.)\n");
1981 $$ = DSP32SHIFT (10, &$1, &$7, &$5, $9.r0, 0);
1982 }
1983 else
1984 return yyerror ("Register mismatch");
1985 }
1986
1987 | a_assign REG_A _GREATER_GREATER_GREATER expr
1988 {
1989 if (!REG_SAME ($1, $2))
1990 return yyerror ("Aregs must be same");
1991
1992 if (IS_UIMM ($4, 5))
1993 {
1994 notethat ("dsp32shiftimm: Ax = Ax >>> uimm5\n");
1995 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 0, IS_A1 ($1));
1996 }
1997 else
1998 return yyerror ("Shift value range error");
1999 }
2000 | a_assign LSHIFT REG_A BY HALF_REG
2001 {
2002 if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2003 {
2004 notethat ("dsp32shift: Ax = LSHIFT Ax BY dregs_lo\n");
2005 $$ = DSP32SHIFT (3, 0, &$5, 0, 1, IS_A1 ($1));
2006 }
2007 else
2008 return yyerror ("Register mismatch");
2009 }
2010
2011 | HALF_REG ASSIGN LSHIFT HALF_REG BY HALF_REG
2012 {
2013 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2014 {
2015 notethat ("dsp32shift: dregs_lo = LSHIFT dregs_hi BY dregs_lo\n");
2016 $$ = DSP32SHIFT (0, &$1, &$6, &$4, 2, HL2 ($1, $4));
2017 }
2018 else
2019 return yyerror ("Register mismatch");
2020 }
2021
2022 | REG ASSIGN LSHIFT REG BY HALF_REG vmod
2023 {
2024 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2025 {
2026 notethat ("dsp32shift: dregs = LSHIFT dregs BY dregs_lo (V )\n");
2027 $$ = DSP32SHIFT ($7.r0 ? 1: 2, &$1, &$6, &$4, 2, 0);
2028 }
2029 else
2030 return yyerror ("Register mismatch");
2031 }
2032
2033 | REG ASSIGN SHIFT REG BY HALF_REG
2034 {
2035 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2036 {
2037 notethat ("dsp32shift: dregs = SHIFT dregs BY dregs_lo\n");
2038 $$ = DSP32SHIFT (2, &$1, &$6, &$4, 2, 0);
2039 }
2040 else
2041 return yyerror ("Register mismatch");
2042 }
2043
2044 | a_assign REG_A GREATER_GREATER expr
2045 {
2046 if (REG_SAME ($1, $2) && IS_IMM ($4, 6) >= 0)
2047 {
2048 notethat ("dsp32shiftimm: Ax = Ax >> imm6\n");
2049 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 1, IS_A1 ($1));
2050 }
2051 else
2052 return yyerror ("Accu register expected");
2053 }
2054
2055 | REG ASSIGN REG GREATER_GREATER expr vmod
2056 {
2057 if ($6.r0 == 1)
2058 {
2059 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2060 {
2061 notethat ("dsp32shiftimm: dregs = dregs >> uimm5 (V)\n");
2062 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, 2, 0);
2063 }
2064 else
2065 return yyerror ("Register mismatch");
2066 }
2067 else
2068 {
2069 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2070 {
2071 notethat ("dsp32shiftimm: dregs = dregs >> uimm5\n");
2072 $$ = DSP32SHIFTIMM (2, &$1, -imm6 ($5), &$3, 2, 0);
2073 }
2074 else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 2)
2075 {
2076 notethat ("PTR2op: pregs = pregs >> 2\n");
2077 $$ = PTR2OP (&$1, &$3, 3);
2078 }
2079 else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 1)
2080 {
2081 notethat ("PTR2op: pregs = pregs >> 1\n");
2082 $$ = PTR2OP (&$1, &$3, 4);
2083 }
2084 else
2085 return yyerror ("Register mismatch");
2086 }
2087 }
2088 | HALF_REG ASSIGN HALF_REG GREATER_GREATER expr
2089 {
2090 if (IS_UIMM ($5, 5))
2091 {
2092 notethat ("dsp32shiftimm: dregs_half = dregs_half >> uimm5\n");
2093 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3, 2, HL2 ($1, $3));
2094 }
2095 else
2096 return yyerror ("Register mismatch");
2097 }
2098 | HALF_REG ASSIGN HALF_REG _GREATER_GREATER_GREATER expr smod
2099 {
2100 if (IS_UIMM ($5, 5))
2101 {
2102 notethat ("dsp32shiftimm: dregs_half = dregs_half >>> uimm5\n");
2103 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3,
2104 $6.s0, HL2 ($1, $3));
2105 }
2106 else
2107 return yyerror ("Register or modifier mismatch");
2108 }
2109
2110
2111 | REG ASSIGN REG _GREATER_GREATER_GREATER expr vsmod
2112 {
2113 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2114 {
2115 if ($6.r0)
2116 {
2117 /* Vector? */
2118 notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (V, .)\n");
2119 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2120 }
2121 else
2122 {
2123 notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (.)\n");
2124 $$ = DSP32SHIFTIMM (2, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2125 }
2126 }
2127 else
2128 return yyerror ("Register mismatch");
2129 }
2130
2131 | HALF_REG ASSIGN ONES REG
2132 {
2133 if (IS_DREG_L ($1) && IS_DREG ($4))
2134 {
2135 notethat ("dsp32shift: dregs_lo = ONES dregs\n");
2136 $$ = DSP32SHIFT (6, &$1, 0, &$4, 3, 0);
2137 }
2138 else
2139 return yyerror ("Register mismatch");
2140 }
2141
2142 | REG ASSIGN PACK LPAREN HALF_REG COMMA HALF_REG RPAREN
2143 {
2144 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2145 {
2146 notethat ("dsp32shift: dregs = PACK (dregs_hi , dregs_hi )\n");
2147 $$ = DSP32SHIFT (4, &$1, &$7, &$5, HL2 ($5, $7), 0);
2148 }
2149 else
2150 return yyerror ("Register mismatch");
2151 }
2152
2153 | HALF_REG ASSIGN CCREG ASSIGN BXORSHIFT LPAREN REG_A COMMA REG RPAREN
2154 {
2155 if (IS_DREG ($1)
2156 && $7.regno == REG_A0
2157 && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2158 {
2159 notethat ("dsp32shift: dregs_lo = CC = BXORSHIFT (A0 , dregs )\n");
2160 $$ = DSP32SHIFT (11, &$1, &$9, 0, 0, 0);
2161 }
2162 else
2163 return yyerror ("Register mismatch");
2164 }
2165
2166 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG RPAREN
2167 {
2168 if (IS_DREG ($1)
2169 && $7.regno == REG_A0
2170 && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2171 {
2172 notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , dregs)\n");
2173 $$ = DSP32SHIFT (11, &$1, &$9, 0, 1, 0);
2174 }
2175 else
2176 return yyerror ("Register mismatch");
2177 }
2178
2179 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2180 {
2181 if (IS_DREG ($1) && !IS_H ($1) && !REG_SAME ($7, $9))
2182 {
2183 notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , A1 , CC)\n");
2184 $$ = DSP32SHIFT (12, &$1, 0, 0, 1, 0);
2185 }
2186 else
2187 return yyerror ("Register mismatch");
2188 }
2189
2190 | a_assign ROT REG_A BY HALF_REG
2191 {
2192 if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2193 {
2194 notethat ("dsp32shift: Ax = ROT Ax BY dregs_lo\n");
2195 $$ = DSP32SHIFT (3, 0, &$5, 0, 2, IS_A1 ($1));
2196 }
2197 else
2198 return yyerror ("Register mismatch");
2199 }
2200
2201 | REG ASSIGN ROT REG BY HALF_REG
2202 {
2203 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2204 {
2205 notethat ("dsp32shift: dregs = ROT dregs BY dregs_lo\n");
2206 $$ = DSP32SHIFT (2, &$1, &$6, &$4, 3, 0);
2207 }
2208 else
2209 return yyerror ("Register mismatch");
2210 }
2211
2212 | a_assign ROT REG_A BY expr
2213 {
2214 if (IS_IMM ($5, 6))
2215 {
2216 notethat ("dsp32shiftimm: An = ROT An BY imm6\n");
2217 $$ = DSP32SHIFTIMM (3, 0, imm6 ($5), 0, 2, IS_A1 ($1));
2218 }
2219 else
2220 return yyerror ("Register mismatch");
2221 }
2222
2223 | REG ASSIGN ROT REG BY expr
2224 {
2225 if (IS_DREG ($1) && IS_DREG ($4) && IS_IMM ($6, 6))
2226 {
2227 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($6), &$4, 3, IS_A1 ($1));
2228 }
2229 else
2230 return yyerror ("Register mismatch");
2231 }
2232
2233 | HALF_REG ASSIGN SIGNBITS REG_A
2234 {
2235 if (IS_DREG_L ($1))
2236 {
2237 notethat ("dsp32shift: dregs_lo = SIGNBITS An\n");
2238 $$ = DSP32SHIFT (6, &$1, 0, 0, IS_A1 ($4), 0);
2239 }
2240 else
2241 return yyerror ("Register mismatch");
2242 }
2243
2244 | HALF_REG ASSIGN SIGNBITS REG
2245 {
2246 if (IS_DREG_L ($1) && IS_DREG ($4))
2247 {
2248 notethat ("dsp32shift: dregs_lo = SIGNBITS dregs\n");
2249 $$ = DSP32SHIFT (5, &$1, 0, &$4, 0, 0);
2250 }
2251 else
2252 return yyerror ("Register mismatch");
2253 }
2254
2255 | HALF_REG ASSIGN SIGNBITS HALF_REG
2256 {
2257 if (IS_DREG_L ($1))
2258 {
2259 notethat ("dsp32shift: dregs_lo = SIGNBITS dregs_lo\n");
2260 $$ = DSP32SHIFT (5, &$1, 0, &$4, 1 + IS_H ($4), 0);
2261 }
2262 else
2263 return yyerror ("Register mismatch");
2264 }
2265
2266 /* The ASR bit is just inverted here. */
2267 | HALF_REG ASSIGN VIT_MAX LPAREN REG RPAREN asr_asl
2268 {
2269 if (IS_DREG_L ($1) && IS_DREG ($5))
2270 {
2271 notethat ("dsp32shift: dregs_lo = VIT_MAX (dregs) (..)\n");
2272 $$ = DSP32SHIFT (9, &$1, 0, &$5, ($7.r0 ? 0 : 1), 0);
2273 }
2274 else
2275 return yyerror ("Register mismatch");
2276 }
2277
2278 | REG ASSIGN VIT_MAX LPAREN REG COMMA REG RPAREN asr_asl
2279 {
2280 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2281 {
2282 notethat ("dsp32shift: dregs = VIT_MAX (dregs, dregs) (ASR)\n");
2283 $$ = DSP32SHIFT (9, &$1, &$7, &$5, 2 | ($9.r0 ? 0 : 1), 0);
2284 }
2285 else
2286 return yyerror ("Register mismatch");
2287 }
2288
2289 | BITMUX LPAREN REG COMMA REG COMMA REG_A RPAREN asr_asl
2290 {
2291 if (IS_DREG ($3) && IS_DREG ($5) && !IS_A1 ($7))
2292 {
2293 notethat ("dsp32shift: BITMUX (dregs , dregs , A0) (ASR)\n");
2294 $$ = DSP32SHIFT (8, 0, &$3, &$5, $9.r0, 0);
2295 }
2296 else
2297 return yyerror ("Register mismatch");
2298 }
2299
2300 | a_assign BXORSHIFT LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2301 {
2302 if (!IS_A1 ($1) && !IS_A1 ($4) && IS_A1 ($6))
2303 {
2304 notethat ("dsp32shift: A0 = BXORSHIFT (A0 , A1 , CC )\n");
2305 $$ = DSP32SHIFT (12, 0, 0, 0, 0, 0);
2306 }
2307 else
2308 return yyerror ("Dregs expected");
2309 }
2310
2311
2312 /* LOGI2op: BITCLR (dregs, uimm5). */
2313 | BITCLR LPAREN REG COMMA expr RPAREN
2314 {
2315 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2316 {
2317 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2318 $$ = LOGI2OP ($3, uimm5 ($5), 4);
2319 }
2320 else
2321 return yyerror ("Register mismatch");
2322 }
2323
2324 /* LOGI2op: BITSET (dregs, uimm5). */
2325 | BITSET LPAREN REG COMMA expr RPAREN
2326 {
2327 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2328 {
2329 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2330 $$ = LOGI2OP ($3, uimm5 ($5), 2);
2331 }
2332 else
2333 return yyerror ("Register mismatch");
2334 }
2335
2336 /* LOGI2op: BITTGL (dregs, uimm5). */
2337 | BITTGL LPAREN REG COMMA expr RPAREN
2338 {
2339 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2340 {
2341 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2342 $$ = LOGI2OP ($3, uimm5 ($5), 3);
2343 }
2344 else
2345 return yyerror ("Register mismatch");
2346 }
2347
2348 | CCREG _ASSIGN_BANG BITTST LPAREN REG COMMA expr RPAREN
2349 {
2350 if (IS_DREG ($5) && IS_UIMM ($7, 5))
2351 {
2352 notethat ("LOGI2op: CC =! BITTST (dregs , uimm5 )\n");
2353 $$ = LOGI2OP ($5, uimm5 ($7), 0);
2354 }
2355 else
2356 return yyerror ("Register mismatch or value error");
2357 }
2358
2359 | CCREG ASSIGN BITTST LPAREN REG COMMA expr RPAREN
2360 {
2361 if (IS_DREG ($5) && IS_UIMM ($7, 5))
2362 {
2363 notethat ("LOGI2op: CC = BITTST (dregs , uimm5 )\n");
2364 $$ = LOGI2OP ($5, uimm5 ($7), 1);
2365 }
2366 else
2367 return yyerror ("Register mismatch or value error");
2368 }
2369
2370 | IF BANG CCREG REG ASSIGN REG
2371 {
2372 if ((IS_DREG ($4) || IS_PREG ($4))
2373 && (IS_DREG ($6) || IS_PREG ($6)))
2374 {
2375 notethat ("ccMV: IF ! CC gregs = gregs\n");
2376 $$ = CCMV (&$6, &$4, 0);
2377 }
2378 else
2379 return yyerror ("Register mismatch");
2380 }
2381
2382 | IF CCREG REG ASSIGN REG
2383 {
2384 if ((IS_DREG ($5) || IS_PREG ($5))
2385 && (IS_DREG ($3) || IS_PREG ($3)))
2386 {
2387 notethat ("ccMV: IF CC gregs = gregs\n");
2388 $$ = CCMV (&$5, &$3, 1);
2389 }
2390 else
2391 return yyerror ("Register mismatch");
2392 }
2393
2394 | IF BANG CCREG JUMP expr
2395 {
2396 if (IS_PCREL10 ($5))
2397 {
2398 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2399 $$ = BRCC (0, 0, $5);
2400 }
2401 else
2402 return yyerror ("Bad jump offset");
2403 }
2404
2405 | IF BANG CCREG JUMP expr LPAREN BP RPAREN
2406 {
2407 if (IS_PCREL10 ($5))
2408 {
2409 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2410 $$ = BRCC (0, 1, $5);
2411 }
2412 else
2413 return yyerror ("Bad jump offset");
2414 }
2415
2416 | IF CCREG JUMP expr
2417 {
2418 if (IS_PCREL10 ($4))
2419 {
2420 notethat ("BRCC: IF CC JUMP pcrel11m2\n");
2421 $$ = BRCC (1, 0, $4);
2422 }
2423 else
2424 return yyerror ("Bad jump offset");
2425 }
2426
2427 | IF CCREG JUMP expr LPAREN BP RPAREN
2428 {
2429 if (IS_PCREL10 ($4))
2430 {
2431 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2432 $$ = BRCC (1, 1, $4);
2433 }
2434 else
2435 return yyerror ("Bad jump offset");
2436 }
2437 | NOP
2438 {
2439 notethat ("ProgCtrl: NOP\n");
2440 $$ = PROGCTRL (0, 0);
2441 }
2442
2443 | RTS
2444 {
2445 notethat ("ProgCtrl: RTS\n");
2446 $$ = PROGCTRL (1, 0);
2447 }
2448
2449 | RTI
2450 {
2451 notethat ("ProgCtrl: RTI\n");
2452 $$ = PROGCTRL (1, 1);
2453 }
2454
2455 | RTX
2456 {
2457 notethat ("ProgCtrl: RTX\n");
2458 $$ = PROGCTRL (1, 2);
2459 }
2460
2461 | RTN
2462 {
2463 notethat ("ProgCtrl: RTN\n");
2464 $$ = PROGCTRL (1, 3);
2465 }
2466
2467 | RTE
2468 {
2469 notethat ("ProgCtrl: RTE\n");
2470 $$ = PROGCTRL (1, 4);
2471 }
2472
2473 | IDLE
2474 {
2475 notethat ("ProgCtrl: IDLE\n");
2476 $$ = PROGCTRL (2, 0);
2477 }
2478
2479 | CSYNC
2480 {
2481 notethat ("ProgCtrl: CSYNC\n");
2482 $$ = PROGCTRL (2, 3);
2483 }
2484
2485 | SSYNC
2486 {
2487 notethat ("ProgCtrl: SSYNC\n");
2488 $$ = PROGCTRL (2, 4);
2489 }
2490
2491 | EMUEXCPT
2492 {
2493 notethat ("ProgCtrl: EMUEXCPT\n");
2494 $$ = PROGCTRL (2, 5);
2495 }
2496
2497 | CLI REG
2498 {
2499 if (IS_DREG ($2))
2500 {
2501 notethat ("ProgCtrl: CLI dregs\n");
2502 $$ = PROGCTRL (3, $2.regno & CODE_MASK);
2503 }
2504 else
2505 return yyerror ("Dreg expected for CLI");
2506 }
2507
2508 | STI REG
2509 {
2510 if (IS_DREG ($2))
2511 {
2512 notethat ("ProgCtrl: STI dregs\n");
2513 $$ = PROGCTRL (4, $2.regno & CODE_MASK);
2514 }
2515 else
2516 return yyerror ("Dreg expected for STI");
2517 }
2518
2519 | JUMP LPAREN REG RPAREN
2520 {
2521 if (IS_PREG ($3))
2522 {
2523 notethat ("ProgCtrl: JUMP (pregs )\n");
2524 $$ = PROGCTRL (5, $3.regno & CODE_MASK);
2525 }
2526 else
2527 return yyerror ("Bad register for indirect jump");
2528 }
2529
2530 | CALL LPAREN REG RPAREN
2531 {
2532 if (IS_PREG ($3))
2533 {
2534 notethat ("ProgCtrl: CALL (pregs )\n");
2535 $$ = PROGCTRL (6, $3.regno & CODE_MASK);
2536 }
2537 else
2538 return yyerror ("Bad register for indirect call");
2539 }
2540
2541 | CALL LPAREN PC PLUS REG RPAREN
2542 {
2543 if (IS_PREG ($5))
2544 {
2545 notethat ("ProgCtrl: CALL (PC + pregs )\n");
2546 $$ = PROGCTRL (7, $5.regno & CODE_MASK);
2547 }
2548 else
2549 return yyerror ("Bad register for indirect call");
2550 }
2551
2552 | JUMP LPAREN PC PLUS REG RPAREN
2553 {
2554 if (IS_PREG ($5))
2555 {
2556 notethat ("ProgCtrl: JUMP (PC + pregs )\n");
2557 $$ = PROGCTRL (8, $5.regno & CODE_MASK);
2558 }
2559 else
2560 return yyerror ("Bad register for indirect jump");
2561 }
2562
2563 | RAISE expr
2564 {
2565 if (IS_UIMM ($2, 4))
2566 {
2567 notethat ("ProgCtrl: RAISE uimm4\n");
2568 $$ = PROGCTRL (9, uimm4 ($2));
2569 }
2570 else
2571 return yyerror ("Bad value for RAISE");
2572 }
2573
2574 | EXCPT expr
2575 {
2576 notethat ("ProgCtrl: EMUEXCPT\n");
2577 $$ = PROGCTRL (10, uimm4 ($2));
2578 }
2579
2580 | TESTSET LPAREN REG RPAREN
2581 {
2582 if (IS_PREG ($3))
2583 {
2584 notethat ("ProgCtrl: TESTSET (pregs )\n");
2585 $$ = PROGCTRL (11, $3.regno & CODE_MASK);
2586 }
2587 else
2588 return yyerror ("Preg expected");
2589 }
2590
2591 | JUMP expr
2592 {
2593 if (IS_PCREL12 ($2))
2594 {
2595 notethat ("UJUMP: JUMP pcrel12\n");
2596 $$ = UJUMP ($2);
2597 }
2598 else
2599 return yyerror ("Bad value for relative jump");
2600 }
2601
2602 | JUMP_DOT_S expr
2603 {
2604 if (IS_PCREL12 ($2))
2605 {
2606 notethat ("UJUMP: JUMP_DOT_S pcrel12\n");
2607 $$ = UJUMP($2);
2608 }
2609 else
2610 return yyerror ("Bad value for relative jump");
2611 }
2612
2613 | JUMP_DOT_L expr
2614 {
2615 if (IS_PCREL24 ($2))
2616 {
2617 notethat ("CALLa: jump.l pcrel24\n");
2618 $$ = CALLA ($2, 0);
2619 }
2620 else
2621 return yyerror ("Bad value for long jump");
2622 }
2623
2624 | JUMP_DOT_L pltpc
2625 {
2626 if (IS_PCREL24 ($2))
2627 {
2628 notethat ("CALLa: jump.l pcrel24\n");
2629 $$ = CALLA ($2, 2);
2630 }
2631 else
2632 return yyerror ("Bad value for long jump");
2633 }
2634
2635 | CALL expr
2636 {
2637 if (IS_PCREL24 ($2))
2638 {
2639 notethat ("CALLa: CALL pcrel25m2\n");
2640 $$ = CALLA ($2, 1);
2641 }
2642 else
2643 return yyerror ("Bad call address");
2644 }
2645 | CALL pltpc
2646 {
2647 if (IS_PCREL24 ($2))
2648 {
2649 notethat ("CALLa: CALL pcrel25m2\n");
2650 $$ = CALLA ($2, 2);
2651 }
2652 else
2653 return yyerror ("Bad call address");
2654 }
2655
2656 /* ALU2ops. */
2657 /* ALU2op: DIVQ (dregs, dregs). */
2658 | DIVQ LPAREN REG COMMA REG RPAREN
2659 {
2660 if (IS_DREG ($3) && IS_DREG ($5))
2661 $$ = ALU2OP (&$3, &$5, 8);
2662 else
2663 return yyerror ("Bad registers for DIVQ");
2664 }
2665
2666 | DIVS LPAREN REG COMMA REG RPAREN
2667 {
2668 if (IS_DREG ($3) && IS_DREG ($5))
2669 $$ = ALU2OP (&$3, &$5, 9);
2670 else
2671 return yyerror ("Bad registers for DIVS");
2672 }
2673
2674 | REG ASSIGN MINUS REG vsmod
2675 {
2676 if (IS_DREG ($1) && IS_DREG ($4))
2677 {
2678 if ($5.r0 == 0 && $5.s0 == 0 && $5.aop == 0)
2679 {
2680 notethat ("ALU2op: dregs = - dregs\n");
2681 $$ = ALU2OP (&$1, &$4, 14);
2682 }
2683 else if ($5.r0 == 1 && $5.s0 == 0 && $5.aop == 3)
2684 {
2685 notethat ("dsp32alu: dregs = - dregs (.)\n");
2686 $$ = DSP32ALU (15, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2687 }
2688 else
2689 {
2690 notethat ("dsp32alu: dregs = - dregs (.)\n");
2691 $$ = DSP32ALU (7, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2692 }
2693 }
2694 else
2695 return yyerror ("Dregs expected");
2696 }
2697
2698 | REG ASSIGN TILDA REG
2699 {
2700 if (IS_DREG ($1) && IS_DREG ($4))
2701 {
2702 notethat ("ALU2op: dregs = ~dregs\n");
2703 $$ = ALU2OP (&$1, &$4, 15);
2704 }
2705 else
2706 return yyerror ("Dregs expected");
2707 }
2708
2709 | REG _GREATER_GREATER_ASSIGN REG
2710 {
2711 if (IS_DREG ($1) && IS_DREG ($3))
2712 {
2713 notethat ("ALU2op: dregs >>= dregs\n");
2714 $$ = ALU2OP (&$1, &$3, 1);
2715 }
2716 else
2717 return yyerror ("Dregs expected");
2718 }
2719
2720 | REG _GREATER_GREATER_ASSIGN expr
2721 {
2722 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2723 {
2724 notethat ("LOGI2op: dregs >>= uimm5\n");
2725 $$ = LOGI2OP ($1, uimm5 ($3), 6);
2726 }
2727 else
2728 return yyerror ("Dregs expected or value error");
2729 }
2730
2731 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN REG
2732 {
2733 if (IS_DREG ($1) && IS_DREG ($3))
2734 {
2735 notethat ("ALU2op: dregs >>>= dregs\n");
2736 $$ = ALU2OP (&$1, &$3, 0);
2737 }
2738 else
2739 return yyerror ("Dregs expected");
2740 }
2741
2742 | REG _LESS_LESS_ASSIGN REG
2743 {
2744 if (IS_DREG ($1) && IS_DREG ($3))
2745 {
2746 notethat ("ALU2op: dregs <<= dregs\n");
2747 $$ = ALU2OP (&$1, &$3, 2);
2748 }
2749 else
2750 return yyerror ("Dregs expected");
2751 }
2752
2753 | REG _LESS_LESS_ASSIGN expr
2754 {
2755 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2756 {
2757 notethat ("LOGI2op: dregs <<= uimm5\n");
2758 $$ = LOGI2OP ($1, uimm5 ($3), 7);
2759 }
2760 else
2761 return yyerror ("Dregs expected or const value error");
2762 }
2763
2764
2765 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN expr
2766 {
2767 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2768 {
2769 notethat ("LOGI2op: dregs >>>= uimm5\n");
2770 $$ = LOGI2OP ($1, uimm5 ($3), 5);
2771 }
2772 else
2773 return yyerror ("Dregs expected");
2774 }
2775
2776 /* Cache Control. */
2777
2778 | FLUSH LBRACK REG RBRACK
2779 {
2780 notethat ("CaCTRL: FLUSH [ pregs ]\n");
2781 if (IS_PREG ($3))
2782 $$ = CACTRL (&$3, 0, 2);
2783 else
2784 return yyerror ("Bad register(s) for FLUSH");
2785 }
2786
2787 | FLUSH reg_with_postinc
2788 {
2789 if (IS_PREG ($2))
2790 {
2791 notethat ("CaCTRL: FLUSH [ pregs ++ ]\n");
2792 $$ = CACTRL (&$2, 1, 2);
2793 }
2794 else
2795 return yyerror ("Bad register(s) for FLUSH");
2796 }
2797
2798 | FLUSHINV LBRACK REG RBRACK
2799 {
2800 if (IS_PREG ($3))
2801 {
2802 notethat ("CaCTRL: FLUSHINV [ pregs ]\n");
2803 $$ = CACTRL (&$3, 0, 1);
2804 }
2805 else
2806 return yyerror ("Bad register(s) for FLUSH");
2807 }
2808
2809 | FLUSHINV reg_with_postinc
2810 {
2811 if (IS_PREG ($2))
2812 {
2813 notethat ("CaCTRL: FLUSHINV [ pregs ++ ]\n");
2814 $$ = CACTRL (&$2, 1, 1);
2815 }
2816 else
2817 return yyerror ("Bad register(s) for FLUSH");
2818 }
2819
2820 /* CaCTRL: IFLUSH [pregs]. */
2821 | IFLUSH LBRACK REG RBRACK
2822 {
2823 if (IS_PREG ($3))
2824 {
2825 notethat ("CaCTRL: IFLUSH [ pregs ]\n");
2826 $$ = CACTRL (&$3, 0, 3);
2827 }
2828 else
2829 return yyerror ("Bad register(s) for FLUSH");
2830 }
2831
2832 | IFLUSH reg_with_postinc
2833 {
2834 if (IS_PREG ($2))
2835 {
2836 notethat ("CaCTRL: IFLUSH [ pregs ++ ]\n");
2837 $$ = CACTRL (&$2, 1, 3);
2838 }
2839 else
2840 return yyerror ("Bad register(s) for FLUSH");
2841 }
2842
2843 | PREFETCH LBRACK REG RBRACK
2844 {
2845 if (IS_PREG ($3))
2846 {
2847 notethat ("CaCTRL: PREFETCH [ pregs ]\n");
2848 $$ = CACTRL (&$3, 0, 0);
2849 }
2850 else
2851 return yyerror ("Bad register(s) for PREFETCH");
2852 }
2853
2854 | PREFETCH reg_with_postinc
2855 {
2856 if (IS_PREG ($2))
2857 {
2858 notethat ("CaCTRL: PREFETCH [ pregs ++ ]\n");
2859 $$ = CACTRL (&$2, 1, 0);
2860 }
2861 else
2862 return yyerror ("Bad register(s) for PREFETCH");
2863 }
2864
2865 /* LOAD/STORE. */
2866 /* LDST: B [ pregs <post_op> ] = dregs. */
2867
2868 | B LBRACK REG post_op RBRACK ASSIGN REG
2869 {
2870 if (IS_PREG ($3) && IS_DREG ($7))
2871 {
2872 notethat ("LDST: B [ pregs <post_op> ] = dregs\n");
2873 $$ = LDST (&$3, &$7, $4.x0, 2, 0, 1);
2874 }
2875 else
2876 return yyerror ("Register mismatch");
2877 }
2878
2879 /* LDSTidxI: B [ pregs + imm16 ] = dregs. */
2880 | B LBRACK REG plus_minus expr RBRACK ASSIGN REG
2881 {
2882 if (IS_PREG ($3) && IS_RANGE(16, $5, $4.r0, 1) && IS_DREG ($8))
2883 {
2884 notethat ("LDST: B [ pregs + imm16 ] = dregs\n");
2885 if ($4.r0)
2886 neg_value ($5);
2887 $$ = LDSTIDXI (&$3, &$8, 1, 2, 0, $5);
2888 }
2889 else
2890 return yyerror ("Register mismatch or const size wrong");
2891 }
2892
2893
2894 /* LDSTii: W [ pregs + uimm4s2 ] = dregs. */
2895 | W LBRACK REG plus_minus expr RBRACK ASSIGN REG
2896 {
2897 if (IS_PREG ($3) && IS_URANGE (4, $5, $4.r0, 2) && IS_DREG ($8))
2898 {
2899 notethat ("LDSTii: W [ pregs +- uimm5m2 ] = dregs\n");
2900 $$ = LDSTII (&$3, &$8, $5, 1, 1);
2901 }
2902 else if (IS_PREG ($3) && IS_RANGE(16, $5, $4.r0, 2) && IS_DREG ($8))
2903 {
2904 notethat ("LDSTidxI: W [ pregs + imm17m2 ] = dregs\n");
2905 if ($4.r0)
2906 neg_value ($5);
2907 $$ = LDSTIDXI (&$3, &$8, 1, 1, 0, $5);
2908 }
2909 else
2910 return yyerror ("Bad register(s) or wrong constant size");
2911 }
2912
2913 /* LDST: W [ pregs <post_op> ] = dregs. */
2914 | W LBRACK REG post_op RBRACK ASSIGN REG
2915 {
2916 if (IS_PREG ($3) && IS_DREG ($7))
2917 {
2918 notethat ("LDST: W [ pregs <post_op> ] = dregs\n");
2919 $$ = LDST (&$3, &$7, $4.x0, 1, 0, 1);
2920 }
2921 else
2922 return yyerror ("Bad register(s) for STORE");
2923 }
2924
2925 | W LBRACK REG post_op RBRACK ASSIGN HALF_REG
2926 {
2927 if (IS_IREG ($3))
2928 {
2929 notethat ("dspLDST: W [ iregs <post_op> ] = dregs_half\n");
2930 $$ = DSPLDST (&$3, 1 + IS_H ($7), &$7, $4.x0, 1);
2931 }
2932 else if ($4.x0 == 2 && IS_PREG ($3) && IS_DREG ($7))
2933 {
2934 notethat ("LDSTpmod: W [ pregs <post_op>] = dregs_half\n");
2935 $$ = LDSTPMOD (&$3, &$7, &$3, 1 + IS_H ($7), 1);
2936
2937 }
2938 else
2939 return yyerror ("Bad register(s) for STORE");
2940 }
2941
2942 /* LDSTiiFP: [ FP - const ] = dpregs. */
2943 | LBRACK REG plus_minus expr RBRACK ASSIGN REG
2944 {
2945 Expr_Node *tmp = $4;
2946 int ispreg = IS_PREG ($7);
2947
2948 if (!IS_PREG ($2))
2949 return yyerror ("Preg expected for indirect");
2950
2951 if (!IS_DREG ($7) && !ispreg)
2952 return yyerror ("Bad source register for STORE");
2953
2954 if ($3.r0)
2955 tmp = unary (Expr_Op_Type_NEG, tmp);
2956
2957 if (in_range_p (tmp, 0, 63, 3))
2958 {
2959 notethat ("LDSTii: dpregs = [ pregs + uimm6m4 ]\n");
2960 $$ = LDSTII (&$2, &$7, tmp, 1, ispreg ? 3 : 0);
2961 }
2962 else if ($2.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
2963 {
2964 notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
2965 tmp = unary (Expr_Op_Type_NEG, tmp);
2966 $$ = LDSTIIFP (tmp, &$7, 1);
2967 }
2968 else if (in_range_p (tmp, -131072, 131071, 3))
2969 {
2970 notethat ("LDSTidxI: [ pregs + imm18m4 ] = dpregs\n");
2971 $$ = LDSTIDXI (&$2, &$7, 1, 0, ispreg ? 1: 0, tmp);
2972 }
2973 else
2974 return yyerror ("Displacement out of range for store");
2975 }
2976
2977 | REG ASSIGN W LBRACK REG plus_minus expr RBRACK xpmod
2978 {
2979 if (IS_DREG ($1) && IS_PREG ($5) && IS_URANGE (4, $7, $6.r0, 2))
2980 {
2981 notethat ("LDSTii: dregs = W [ pregs + uimm4s2 ] (.)\n");
2982 $$ = LDSTII (&$5, &$1, $7, 0, 1 << $9.r0);
2983 }
2984 else if (IS_DREG ($1) && IS_PREG ($5) && IS_RANGE(16, $7, $6.r0, 2))
2985 {
2986 notethat ("LDSTidxI: dregs = W [ pregs + imm17m2 ] (.)\n");
2987 if ($6.r0)
2988 neg_value ($7);
2989 $$ = LDSTIDXI (&$5, &$1, 0, 1, $9.r0, $7);
2990 }
2991 else
2992 return yyerror ("Bad register or constant for LOAD");
2993 }
2994
2995 | HALF_REG ASSIGN W LBRACK REG post_op RBRACK
2996 {
2997 if (IS_IREG ($5))
2998 {
2999 notethat ("dspLDST: dregs_half = W [ iregs ]\n");
3000 $$ = DSPLDST(&$5, 1 + IS_H ($1), &$1, $6.x0, 0);
3001 }
3002 else if ($6.x0 == 2 && IS_DREG ($1) && IS_PREG ($5))
3003 {
3004 notethat ("LDSTpmod: dregs_half = W [ pregs ]\n");
3005 $$ = LDSTPMOD (&$5, &$1, &$5, 1 + IS_H ($1), 0);
3006 }
3007 else
3008 return yyerror ("Bad register or post_op for LOAD");
3009 }
3010
3011
3012 | REG ASSIGN W LBRACK REG post_op RBRACK xpmod
3013 {
3014 if (IS_DREG ($1) && IS_PREG ($5))
3015 {
3016 notethat ("LDST: dregs = W [ pregs <post_op> ] (.)\n");
3017 $$ = LDST (&$5, &$1, $6.x0, 1, $8.r0, 0);
3018 }
3019 else
3020 return yyerror ("Bad register for LOAD");
3021 }
3022
3023 | REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK xpmod
3024 {
3025 if (IS_DREG ($1) && IS_PREG ($5) && IS_PREG ($7))
3026 {
3027 notethat ("LDSTpmod: dregs = W [ pregs ++ pregs ] (.)\n");
3028 $$ = LDSTPMOD (&$5, &$1, &$7, 3, $9.r0);
3029 }
3030 else
3031 return yyerror ("Bad register for LOAD");
3032 }
3033
3034 | HALF_REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK
3035 {
3036 if (IS_DREG ($1) && IS_PREG ($5) && IS_PREG ($7))
3037 {
3038 notethat ("LDSTpmod: dregs_half = W [ pregs ++ pregs ]\n");
3039 $$ = LDSTPMOD (&$5, &$1, &$7, 1 + IS_H ($1), 0);
3040 }
3041 else
3042 return yyerror ("Bad register for LOAD");
3043 }
3044
3045 | LBRACK REG post_op RBRACK ASSIGN REG
3046 {
3047 if (IS_IREG ($2) && IS_DREG ($6))
3048 {
3049 notethat ("dspLDST: [ iregs <post_op> ] = dregs\n");
3050 $$ = DSPLDST(&$2, 0, &$6, $3.x0, 1);
3051 }
3052 else if (IS_PREG ($2) && IS_DREG ($6))
3053 {
3054 notethat ("LDST: [ pregs <post_op> ] = dregs\n");
3055 $$ = LDST (&$2, &$6, $3.x0, 0, 0, 1);
3056 }
3057 else if (IS_PREG ($2) && IS_PREG ($6))
3058 {
3059 notethat ("LDST: [ pregs <post_op> ] = pregs\n");
3060 $$ = LDST (&$2, &$6, $3.x0, 0, 1, 1);
3061 }
3062 else
3063 return yyerror ("Bad register for STORE");
3064 }
3065
3066 | LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN REG
3067 {
3068 if (! IS_DREG ($7))
3069 return yyerror ("Expected Dreg for last argument");
3070
3071 if (IS_IREG ($2) && IS_MREG ($4))
3072 {
3073 notethat ("dspLDST: [ iregs ++ mregs ] = dregs\n");
3074 $$ = DSPLDST(&$2, $4.regno & CODE_MASK, &$7, 3, 1);
3075 }
3076 else if (IS_PREG ($2) && IS_PREG ($4))
3077 {
3078 notethat ("LDSTpmod: [ pregs ++ pregs ] = dregs\n");
3079 $$ = LDSTPMOD (&$2, &$7, &$4, 0, 1);
3080 }
3081 else
3082 return yyerror ("Bad register for STORE");
3083 }
3084
3085 | W LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN HALF_REG
3086 {
3087 if (!IS_DREG ($8))
3088 return yyerror ("Expect Dreg as last argument");
3089 if (IS_PREG ($3) && IS_PREG ($5))
3090 {
3091 notethat ("LDSTpmod: W [ pregs ++ pregs ] = dregs_half\n");
3092 $$ = LDSTPMOD (&$3, &$8, &$5, 1 + IS_H ($8), 1);
3093 }
3094 else
3095 return yyerror ("Bad register for STORE");
3096 }
3097
3098 | REG ASSIGN B LBRACK REG plus_minus expr RBRACK xpmod
3099 {
3100 if (IS_DREG ($1) && IS_PREG ($5) && IS_RANGE(16, $7, $6.r0, 1))
3101 {
3102 notethat ("LDSTidxI: dregs = B [ pregs + imm16 ] (%c)\n",
3103 $9.r0 ? 'X' : 'Z');
3104 if ($6.r0)
3105 neg_value ($7);
3106 $$ = LDSTIDXI (&$5, &$1, 0, 2, $9.r0, $7);
3107 }
3108 else
3109 return yyerror ("Bad register or value for LOAD");
3110 }
3111
3112 | REG ASSIGN B LBRACK REG post_op RBRACK xpmod
3113 {
3114 if (IS_DREG ($1) && IS_PREG ($5))
3115 {
3116 notethat ("LDST: dregs = B [ pregs <post_op> ] (%c)\n",
3117 $8.r0 ? 'X' : 'Z');
3118 $$ = LDST (&$5, &$1, $6.x0, 2, $8.r0, 0);
3119 }
3120 else
3121 return yyerror ("Bad register for LOAD");
3122 }
3123
3124 | REG ASSIGN LBRACK REG _PLUS_PLUS REG RBRACK
3125 {
3126 if (IS_DREG ($1) && IS_IREG ($4) && IS_MREG ($6))
3127 {
3128 notethat ("dspLDST: dregs = [ iregs ++ mregs ]\n");
3129 $$ = DSPLDST(&$4, $6.regno & CODE_MASK, &$1, 3, 0);
3130 }
3131 else if (IS_DREG ($1) && IS_PREG ($4) && IS_PREG ($6))
3132 {
3133 notethat ("LDSTpmod: dregs = [ pregs ++ pregs ]\n");
3134 $$ = LDSTPMOD (&$4, &$1, &$6, 0, 0);
3135 }
3136 else
3137 return yyerror ("Bad register for LOAD");
3138 }
3139
3140 | REG ASSIGN LBRACK REG plus_minus got_or_expr RBRACK
3141 {
3142 Expr_Node *tmp = $6;
3143 int ispreg = IS_PREG ($1);
3144 int isgot = IS_RELOC($6);
3145
3146 if (!IS_PREG ($4))
3147 return yyerror ("Preg expected for indirect");
3148
3149 if (!IS_DREG ($1) && !ispreg)
3150 return yyerror ("Bad destination register for LOAD");
3151
3152 if ($5.r0)
3153 tmp = unary (Expr_Op_Type_NEG, tmp);
3154
3155 if(isgot){
3156 notethat ("LDSTidxI: dpregs = [ pregs + sym@got ]\n");
3157 $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1: 0, tmp);
3158 }
3159 else if (in_range_p (tmp, 0, 63, 3))
3160 {
3161 notethat ("LDSTii: dpregs = [ pregs + uimm7m4 ]\n");
3162 $$ = LDSTII (&$4, &$1, tmp, 0, ispreg ? 3 : 0);
3163 }
3164 else if ($4.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3165 {
3166 notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3167 tmp = unary (Expr_Op_Type_NEG, tmp);
3168 $$ = LDSTIIFP (tmp, &$1, 0);
3169 }
3170 else if (in_range_p (tmp, -131072, 131071, 3))
3171 {
3172 notethat ("LDSTidxI: dpregs = [ pregs + imm18m4 ]\n");
3173 $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1: 0, tmp);
3174
3175 }
3176 else
3177 return yyerror ("Displacement out of range for load");
3178 }
3179
3180 | REG ASSIGN LBRACK REG post_op RBRACK
3181 {
3182 if (IS_DREG ($1) && IS_IREG ($4))
3183 {
3184 notethat ("dspLDST: dregs = [ iregs <post_op> ]\n");
3185 $$ = DSPLDST (&$4, 0, &$1, $5.x0, 0);
3186 }
3187 else if (IS_DREG ($1) && IS_PREG ($4))
3188 {
3189 notethat ("LDST: dregs = [ pregs <post_op> ]\n");
3190 $$ = LDST (&$4, &$1, $5.x0, 0, 0, 0);
3191 }
3192 else if (IS_PREG ($1) && IS_PREG ($4))
3193 {
3194 if (REG_SAME ($1, $4) && $5.x0 != 2)
3195 return yyerror ("Pregs can't be same");
3196
3197 notethat ("LDST: pregs = [ pregs <post_op> ]\n");
3198 $$ = LDST (&$4, &$1, $5.x0, 0, 1, 0);
3199 }
3200 else if ($4.regno == REG_SP && IS_ALLREG ($1) && $5.x0 == 0)
3201 {
3202 notethat ("PushPopReg: allregs = [ SP ++ ]\n");
3203 $$ = PUSHPOPREG (&$1, 0);
3204 }
3205 else
3206 return yyerror ("Bad register or value");
3207 }
3208
3209
3210
3211 /* Expression Assignment. */
3212
3213 | expr ASSIGN expr
3214 {
3215 bfin_equals ($1);
3216 $$ = 0;
3217 }
3218
3219
3220 /* PushPopMultiple. */
3221 | reg_with_predec ASSIGN LPAREN REG COLON expr COMMA REG COLON expr RPAREN
3222 {
3223 if ($1.regno != REG_SP)
3224 yyerror ("Stack Pointer expected");
3225 if ($4.regno == REG_R7
3226 && IN_RANGE ($6, 0, 7)
3227 && $8.regno == REG_P5
3228 && IN_RANGE ($10, 0, 5))
3229 {
3230 notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim , P5 : reglim )\n");
3231 $$ = PUSHPOPMULTIPLE (imm5 ($6), imm5 ($10), 1, 1, 1);
3232 }
3233 else
3234 return yyerror ("Bad register for PushPopMultiple");
3235 }
3236
3237 | reg_with_predec ASSIGN LPAREN REG COLON expr RPAREN
3238 {
3239 if ($1.regno != REG_SP)
3240 yyerror ("Stack Pointer expected");
3241
3242 if ($4.regno == REG_R7 && IN_RANGE ($6, 0, 7))
3243 {
3244 notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim )\n");
3245 $$ = PUSHPOPMULTIPLE (imm5 ($6), 0, 1, 0, 1);
3246 }
3247 else if ($4.regno == REG_P5 && IN_RANGE ($6, 0, 6))
3248 {
3249 notethat ("PushPopMultiple: [ -- SP ] = (P5 : reglim )\n");
3250 $$ = PUSHPOPMULTIPLE (0, imm5 ($6), 0, 1, 1);
3251 }
3252 else
3253 return yyerror ("Bad register for PushPopMultiple");
3254 }
3255
3256 | LPAREN REG COLON expr COMMA REG COLON expr RPAREN ASSIGN reg_with_postinc
3257 {
3258 if ($11.regno != REG_SP)
3259 yyerror ("Stack Pointer expected");
3260 if ($2.regno == REG_R7 && (IN_RANGE ($4, 0, 7))
3261 && $6.regno == REG_P5 && (IN_RANGE ($8, 0, 6)))
3262 {
3263 notethat ("PushPopMultiple: (R7 : reglim , P5 : reglim ) = [ SP ++ ]\n");
3264 $$ = PUSHPOPMULTIPLE (imm5 ($4), imm5 ($8), 1, 1, 0);
3265 }
3266 else
3267 return yyerror ("Bad register range for PushPopMultiple");
3268 }
3269
3270 | LPAREN REG COLON expr RPAREN ASSIGN reg_with_postinc
3271 {
3272 if ($7.regno != REG_SP)
3273 yyerror ("Stack Pointer expected");
3274
3275 if ($2.regno == REG_R7 && IN_RANGE ($4, 0, 7))
3276 {
3277 notethat ("PushPopMultiple: (R7 : reglim ) = [ SP ++ ]\n");
3278 $$ = PUSHPOPMULTIPLE (imm5 ($4), 0, 1, 0, 0);
3279 }
3280 else if ($2.regno == REG_P5 && IN_RANGE ($4, 0, 6))
3281 {
3282 notethat ("PushPopMultiple: (P5 : reglim ) = [ SP ++ ]\n");
3283 $$ = PUSHPOPMULTIPLE (0, imm5 ($4), 0, 1, 0);
3284 }
3285 else
3286 return yyerror ("Bad register range for PushPopMultiple");
3287 }
3288
3289 | reg_with_predec ASSIGN REG
3290 {
3291 if ($1.regno != REG_SP)
3292 yyerror ("Stack Pointer expected");
3293
3294 if (IS_ALLREG ($3))
3295 {
3296 notethat ("PushPopReg: [ -- SP ] = allregs\n");
3297 $$ = PUSHPOPREG (&$3, 1);
3298 }
3299 else
3300 return yyerror ("Bad register for PushPopReg");
3301 }
3302
3303 /* Linkage. */
3304
3305 | LINK expr
3306 {
3307 if (IS_URANGE (16, $2, 0, 4))
3308 $$ = LINKAGE (0, uimm16s4 ($2));
3309 else
3310 return yyerror ("Bad constant for LINK");
3311 }
3312
3313 | UNLINK
3314 {
3315 notethat ("linkage: UNLINK\n");
3316 $$ = LINKAGE (1, 0);
3317 }
3318
3319
3320 /* LSETUP. */
3321
3322 | LSETUP LPAREN expr COMMA expr RPAREN REG
3323 {
3324 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5) && IS_CREG ($7))
3325 {
3326 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters\n");
3327 $$ = LOOPSETUP ($3, &$7, 0, $5, 0);
3328 }
3329 else
3330 return yyerror ("Bad register or values for LSETUP");
3331
3332 }
3333 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG
3334 {
3335 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3336 && IS_PREG ($9) && IS_CREG ($7))
3337 {
3338 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs\n");
3339 $$ = LOOPSETUP ($3, &$7, 1, $5, &$9);
3340 }
3341 else
3342 return yyerror ("Bad register or values for LSETUP");
3343 }
3344
3345 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG GREATER_GREATER expr
3346 {
3347 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3348 && IS_PREG ($9) && IS_CREG ($7)
3349 && EXPR_VALUE ($11) == 1)
3350 {
3351 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs >> 1\n");
3352 $$ = LOOPSETUP ($3, &$7, 3, $5, &$9);
3353 }
3354 else
3355 return yyerror ("Bad register or values for LSETUP");
3356 }
3357
3358 /* LOOP. */
3359 | LOOP expr REG
3360 {
3361 if (!IS_RELOC ($2))
3362 return yyerror ("Invalid expression in loop statement");
3363 if (!IS_CREG ($3))
3364 return yyerror ("Invalid loop counter register");
3365 $$ = bfin_gen_loop ($2, &$3, 0, 0);
3366 }
3367 | LOOP expr REG ASSIGN REG
3368 {
3369 if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3))
3370 {
3371 notethat ("Loop: LOOP expr counters = pregs\n");
3372 $$ = bfin_gen_loop ($2, &$3, 1, &$5);
3373 }
3374 else
3375 return yyerror ("Bad register or values for LOOP");
3376 }
3377 | LOOP expr REG ASSIGN REG GREATER_GREATER expr
3378 {
3379 if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3) && EXPR_VALUE ($7) == 1)
3380 {
3381 notethat ("Loop: LOOP expr counters = pregs >> 1\n");
3382 $$ = bfin_gen_loop ($2, &$3, 3, &$5);
3383 }
3384 else
3385 return yyerror ("Bad register or values for LOOP");
3386 }
3387 /* pseudoDEBUG. */
3388
3389 | DBG
3390 {
3391 notethat ("pseudoDEBUG: DBG\n");
3392 $$ = bfin_gen_pseudodbg (3, 7, 0);
3393 }
3394 | DBG REG_A
3395 {
3396 notethat ("pseudoDEBUG: DBG REG_A\n");
3397 $$ = bfin_gen_pseudodbg (3, IS_A1 ($2), 0);
3398 }
3399 | DBG REG
3400 {
3401 notethat ("pseudoDEBUG: DBG allregs\n");
3402 $$ = bfin_gen_pseudodbg (0, $2.regno & CODE_MASK, $2.regno & CLASS_MASK);
3403 }
3404
3405 | DBGCMPLX LPAREN REG RPAREN
3406 {
3407 if (!IS_DREG ($3))
3408 return yyerror ("Dregs expected");
3409 notethat ("pseudoDEBUG: DBGCMPLX (dregs )\n");
3410 $$ = bfin_gen_pseudodbg (3, 6, $3.regno & CODE_MASK);
3411 }
3412
3413 | DBGHALT
3414 {
3415 notethat ("psedoDEBUG: DBGHALT\n");
3416 $$ = bfin_gen_pseudodbg (3, 5, 0);
3417 }
3418
3419 | DBGA LPAREN HALF_REG COMMA expr RPAREN
3420 {
3421 notethat ("pseudodbg_assert: DBGA (dregs_lo , uimm16 )\n");
3422 $$ = bfin_gen_pseudodbg_assert (IS_H ($3), &$3, uimm16 ($5));
3423 }
3424
3425 | DBGAH LPAREN REG COMMA expr RPAREN
3426 {
3427 notethat ("pseudodbg_assert: DBGAH (dregs , uimm16 )\n");
3428 $$ = bfin_gen_pseudodbg_assert (3, &$3, uimm16 ($5));
3429 }
3430
3431 | DBGAL LPAREN REG COMMA expr RPAREN
3432 {
3433 notethat ("psedodbg_assert: DBGAL (dregs , uimm16 )\n");
3434 $$ = bfin_gen_pseudodbg_assert (2, &$3, uimm16 ($5));
3435 }
3436
3437
3438 ;
3439
3440 /* AUX RULES. */
3441
3442 /* Register rules. */
3443
3444 REG_A: REG_A_DOUBLE_ZERO
3445 {
3446 $$ = $1;
3447 }
3448 | REG_A_DOUBLE_ONE
3449 {
3450 $$ = $1;
3451 }
3452 ;
3453
3454
3455 /* Modifiers. */
3456
3457 opt_mode:
3458 {
3459 $$.MM = 0;
3460 $$.mod = 0;
3461 }
3462 | LPAREN M COMMA MMOD RPAREN
3463 {
3464 $$.MM = 1;
3465 $$.mod = $4;
3466 }
3467 | LPAREN MMOD COMMA M RPAREN
3468 {
3469 $$.MM = 1;
3470 $$.mod = $2;
3471 }
3472 | LPAREN MMOD RPAREN
3473 {
3474 $$.MM = 0;
3475 $$.mod = $2;
3476 }
3477 | LPAREN M RPAREN
3478 {
3479 $$.MM = 1;
3480 $$.mod = 0;
3481 }
3482 ;
3483
3484 asr_asl: LPAREN ASL RPAREN
3485 {
3486 $$.r0 = 1;
3487 }
3488 | LPAREN ASR RPAREN
3489 {
3490 $$.r0 = 0;
3491 }
3492 ;
3493
3494 sco:
3495 {
3496 $$.s0 = 0;
3497 $$.x0 = 0;
3498 }
3499 | S
3500 {
3501 $$.s0 = 1;
3502 $$.x0 = 0;
3503 }
3504 | CO
3505 {
3506 $$.s0 = 0;
3507 $$.x0 = 1;
3508 }
3509 | SCO
3510 {
3511 $$.s0 = 1;
3512 $$.x0 = 1;
3513 }
3514 ;
3515
3516 asr_asl_0:
3517 ASL
3518 {
3519 $$.r0 = 1;
3520 }
3521 | ASR
3522 {
3523 $$.r0 = 0;
3524 }
3525 ;
3526
3527 amod0:
3528 {
3529 $$.s0 = 0;
3530 $$.x0 = 0;
3531 }
3532 | LPAREN sco RPAREN
3533 {
3534 $$.s0 = $2.s0;
3535 $$.x0 = $2.x0;
3536 }
3537 ;
3538
3539 amod1:
3540 {
3541 $$.s0 = 0;
3542 $$.x0 = 0;
3543 $$.aop = 0;
3544 }
3545 | LPAREN NS RPAREN
3546 {
3547 $$.s0 = 0;
3548 $$.x0 = 0;
3549 $$.aop = 1;
3550 }
3551 | LPAREN S RPAREN
3552 {
3553 $$.s0 = 1;
3554 $$.x0 = 0;
3555 $$.aop = 1;
3556 }
3557 ;
3558
3559 amod2:
3560 {
3561 $$.r0 = 0;
3562 $$.s0 = 0;
3563 $$.x0 = 0;
3564 }
3565 | LPAREN asr_asl_0 RPAREN
3566 {
3567 $$.r0 = 2 + $2.r0;
3568 $$.s0 = 0;
3569 $$.x0 = 0;
3570 }
3571 | LPAREN sco RPAREN
3572 {
3573 $$.r0 = 0;
3574 $$.s0 = $2.s0;
3575 $$.x0 = $2.x0;
3576 }
3577 | LPAREN asr_asl_0 COMMA sco RPAREN
3578 {
3579 $$.r0 = 2 + $2.r0;
3580 $$.s0 = $4.s0;
3581 $$.x0 = $4.x0;
3582 }
3583 | LPAREN sco COMMA asr_asl_0 RPAREN
3584 {
3585 $$.r0 = 2 + $4.r0;
3586 $$.s0 = $2.s0;
3587 $$.x0 = $2.x0;
3588 }
3589 ;
3590
3591 xpmod:
3592 {
3593 $$.r0 = 0;
3594 }
3595 | LPAREN Z RPAREN
3596 {
3597 $$.r0 = 0;
3598 }
3599 | LPAREN X RPAREN
3600 {
3601 $$.r0 = 1;
3602 }
3603 ;
3604
3605 xpmod1:
3606 {
3607 $$.r0 = 0;
3608 }
3609 | LPAREN X RPAREN
3610 {
3611 $$.r0 = 0;
3612 }
3613 | LPAREN Z RPAREN
3614 {
3615 $$.r0 = 1;
3616 }
3617 ;
3618
3619 vsmod:
3620 {
3621 $$.r0 = 0;
3622 $$.s0 = 0;
3623 $$.aop = 0;
3624 }
3625 | LPAREN NS RPAREN
3626 {
3627 $$.r0 = 0;
3628 $$.s0 = 0;
3629 $$.aop = 3;
3630 }
3631 | LPAREN S RPAREN
3632 {
3633 $$.r0 = 0;
3634 $$.s0 = 1;
3635 $$.aop = 3;
3636 }
3637 | LPAREN V RPAREN
3638 {
3639 $$.r0 = 1;
3640 $$.s0 = 0;
3641 $$.aop = 3;
3642 }
3643 | LPAREN V COMMA S RPAREN
3644 {
3645 $$.r0 = 1;
3646 $$.s0 = 1;
3647 }
3648 | LPAREN S COMMA V RPAREN
3649 {
3650 $$.r0 = 1;
3651 $$.s0 = 1;
3652 }
3653 ;
3654
3655 vmod:
3656 {
3657 $$.r0 = 0;
3658 }
3659 | LPAREN V RPAREN
3660 {
3661 $$.r0 = 1;
3662 }
3663 ;
3664
3665 smod:
3666 {
3667 $$.s0 = 0;
3668 }
3669 | LPAREN S RPAREN
3670 {
3671 $$.s0 = 1;
3672 }
3673 ;
3674
3675 searchmod:
3676 GE
3677 {
3678 $$.r0 = 1;
3679 }
3680 | GT
3681 {
3682 $$.r0 = 0;
3683 }
3684 | LE
3685 {
3686 $$.r0 = 3;
3687 }
3688 | LT
3689 {
3690 $$.r0 = 2;
3691 }
3692 ;
3693
3694 aligndir:
3695 {
3696 $$.r0 = 0;
3697 }
3698 | LPAREN R RPAREN
3699 {
3700 $$.r0 = 1;
3701 }
3702 ;
3703
3704 byteop_mod:
3705 LPAREN R RPAREN
3706 {
3707 $$.r0 = 0;
3708 $$.s0 = 1;
3709 }
3710 | LPAREN MMOD RPAREN
3711 {
3712 if ($2 != M_T)
3713 return yyerror ("Bad modifier");
3714 $$.r0 = 1;
3715 $$.s0 = 0;
3716 }
3717 | LPAREN MMOD COMMA R RPAREN
3718 {
3719 if ($2 != M_T)
3720 return yyerror ("Bad modifier");
3721 $$.r0 = 1;
3722 $$.s0 = 1;
3723 }
3724 | LPAREN R COMMA MMOD RPAREN
3725 {
3726 if ($4 != M_T)
3727 return yyerror ("Bad modifier");
3728 $$.r0 = 1;
3729 $$.s0 = 1;
3730 }
3731 ;
3732
3733
3734
3735 c_align:
3736 ALIGN8
3737 {
3738 $$.r0 = 0;
3739 }
3740 | ALIGN16
3741 {
3742 $$.r0 = 1;
3743 }
3744 | ALIGN24
3745 {
3746 $$.r0 = 2;
3747 }
3748 ;
3749
3750 w32_or_nothing:
3751 {
3752 $$.r0 = 0;
3753 }
3754 | LPAREN MMOD RPAREN
3755 {
3756 if ($2 == M_W32)
3757 $$.r0 = 1;
3758 else
3759 return yyerror ("Only (W32) allowed");
3760 }
3761 ;
3762
3763 iu_or_nothing:
3764 {
3765 $$.r0 = 1;
3766 }
3767 | LPAREN MMOD RPAREN
3768 {
3769 if ($2 == M_IU)
3770 $$.r0 = 3;
3771 else
3772 return yyerror ("(IU) expected");
3773 }
3774 ;
3775
3776 reg_with_predec: LBRACK _MINUS_MINUS REG RBRACK
3777 {
3778 $$ = $3;
3779 }
3780 ;
3781
3782 reg_with_postinc: LBRACK REG _PLUS_PLUS RBRACK
3783 {
3784 $$ = $2;
3785 }
3786 ;
3787
3788 /* Operators. */
3789
3790 min_max:
3791 MIN
3792 {
3793 $$.r0 = 1;
3794 }
3795 | MAX
3796 {
3797 $$.r0 = 0;
3798 }
3799 ;
3800
3801 op_bar_op:
3802 _PLUS_BAR_PLUS
3803 {
3804 $$.r0 = 0;
3805 }
3806 | _PLUS_BAR_MINUS
3807 {
3808 $$.r0 = 1;
3809 }
3810 | _MINUS_BAR_PLUS
3811 {
3812 $$.r0 = 2;
3813 }
3814 | _MINUS_BAR_MINUS
3815 {
3816 $$.r0 = 3;
3817 }
3818 ;
3819
3820 plus_minus:
3821 PLUS
3822 {
3823 $$.r0 = 0;
3824 }
3825 | MINUS
3826 {
3827 $$.r0 = 1;
3828 }
3829 ;
3830
3831 rnd_op:
3832 LPAREN RNDH RPAREN
3833 {
3834 $$.r0 = 1; /* HL. */
3835 $$.s0 = 0; /* s. */
3836 $$.x0 = 0; /* x. */
3837 $$.aop = 0; /* aop. */
3838 }
3839
3840 | LPAREN TH RPAREN
3841 {
3842 $$.r0 = 1; /* HL. */
3843 $$.s0 = 0; /* s. */
3844 $$.x0 = 0; /* x. */
3845 $$.aop = 1; /* aop. */
3846 }
3847
3848 | LPAREN RNDL RPAREN
3849 {
3850 $$.r0 = 0; /* HL. */
3851 $$.s0 = 0; /* s. */
3852 $$.x0 = 0; /* x. */
3853 $$.aop = 0; /* aop. */
3854 }
3855
3856 | LPAREN TL RPAREN
3857 {
3858 $$.r0 = 0; /* HL. */
3859 $$.s0 = 0; /* s. */
3860 $$.x0 = 0; /* x. */
3861 $$.aop = 1;
3862 }
3863
3864 | LPAREN RNDH COMMA R RPAREN
3865 {
3866 $$.r0 = 1; /* HL. */
3867 $$.s0 = 1; /* s. */
3868 $$.x0 = 0; /* x. */
3869 $$.aop = 0; /* aop. */
3870 }
3871 | LPAREN TH COMMA R RPAREN
3872 {
3873 $$.r0 = 1; /* HL. */
3874 $$.s0 = 1; /* s. */
3875 $$.x0 = 0; /* x. */
3876 $$.aop = 1; /* aop. */
3877 }
3878 | LPAREN RNDL COMMA R RPAREN
3879 {
3880 $$.r0 = 0; /* HL. */
3881 $$.s0 = 1; /* s. */
3882 $$.x0 = 0; /* x. */
3883 $$.aop = 0; /* aop. */
3884 }
3885
3886 | LPAREN TL COMMA R RPAREN
3887 {
3888 $$.r0 = 0; /* HL. */
3889 $$.s0 = 1; /* s. */
3890 $$.x0 = 0; /* x. */
3891 $$.aop = 1; /* aop. */
3892 }
3893 ;
3894
3895 b3_op:
3896 LPAREN LO RPAREN
3897 {
3898 $$.s0 = 0; /* s. */
3899 $$.x0 = 0; /* HL. */
3900 }
3901 | LPAREN HI RPAREN
3902 {
3903 $$.s0 = 0; /* s. */
3904 $$.x0 = 1; /* HL. */
3905 }
3906 | LPAREN LO COMMA R RPAREN
3907 {
3908 $$.s0 = 1; /* s. */
3909 $$.x0 = 0; /* HL. */
3910 }
3911 | LPAREN HI COMMA R RPAREN
3912 {
3913 $$.s0 = 1; /* s. */
3914 $$.x0 = 1; /* HL. */
3915 }
3916 ;
3917
3918 post_op:
3919 {
3920 $$.x0 = 2;
3921 }
3922 | _PLUS_PLUS
3923 {
3924 $$.x0 = 0;
3925 }
3926 | _MINUS_MINUS
3927 {
3928 $$.x0 = 1;
3929 }
3930 ;
3931
3932 /* Assignments, Macfuncs. */
3933
3934 a_assign:
3935 REG_A ASSIGN
3936 {
3937 $$ = $1;
3938 }
3939 ;
3940
3941 a_minusassign:
3942 REG_A _MINUS_ASSIGN
3943 {
3944 $$ = $1;
3945 }
3946 ;
3947
3948 a_plusassign:
3949 REG_A _PLUS_ASSIGN
3950 {
3951 $$ = $1;
3952 }
3953 ;
3954
3955 assign_macfunc:
3956 REG ASSIGN REG_A
3957 {
3958 $$.w = 1;
3959 $$.P = 1;
3960 $$.n = IS_A1 ($3);
3961 $$.op = 3;
3962 $$.dst = $1;
3963 $$.s0.regno = 0;
3964 $$.s1.regno = 0;
3965
3966 if (IS_A1 ($3) && IS_EVEN ($1))
3967 return yyerror ("Cannot move A1 to even register");
3968 else if (!IS_A1 ($3) && !IS_EVEN ($1))
3969 return yyerror ("Cannot move A0 to odd register");
3970 }
3971 | a_macfunc
3972 {
3973 $$ = $1;
3974 $$.w = 0; $$.P = 0;
3975 $$.dst.regno = 0;
3976 }
3977 | REG ASSIGN LPAREN a_macfunc RPAREN
3978 {
3979 $$ = $4;
3980 $$.w = 1;
3981 $$.P = 1;
3982 $$.dst = $1;
3983 }
3984
3985 | HALF_REG ASSIGN LPAREN a_macfunc RPAREN
3986 {
3987 $$ = $4;
3988 $$.w = 1;
3989 $$.P = 0;
3990 $$.dst = $1;
3991 }
3992
3993 | HALF_REG ASSIGN REG_A
3994 {
3995 $$.w = 1;
3996 $$.P = 0;
3997 $$.n = IS_A1 ($3);
3998 $$.op = 3;
3999 $$.dst = $1;
4000 $$.s0.regno = 0;
4001 $$.s1.regno = 0;
4002
4003 if (IS_A1 ($3) && !IS_H ($1))
4004 return yyerror ("Cannot move A1 to low half of register");
4005 else if (!IS_A1 ($3) && IS_H ($1))
4006 return yyerror ("Cannot move A0 to high half of register");
4007 }
4008 ;
4009
4010 a_macfunc:
4011 a_assign multiply_halfregs
4012 {
4013 $$.n = IS_A1 ($1);
4014 $$.op = 0;
4015 $$.s0 = $2.s0;
4016 $$.s1 = $2.s1;
4017 }
4018 | a_plusassign multiply_halfregs
4019 {
4020 $$.n = IS_A1 ($1);
4021 $$.op = 1;
4022 $$.s0 = $2.s0;
4023 $$.s1 = $2.s1;
4024 }
4025 | a_minusassign multiply_halfregs
4026 {
4027 $$.n = IS_A1 ($1);
4028 $$.op = 2;
4029 $$.s0 = $2.s0;
4030 $$.s1 = $2.s1;
4031 }
4032 ;
4033
4034 multiply_halfregs:
4035 HALF_REG STAR HALF_REG
4036 {
4037 if (IS_DREG ($1) && IS_DREG ($3))
4038 {
4039 $$.s0 = $1;
4040 $$.s1 = $3;
4041 }
4042 else
4043 return yyerror ("Dregs expected");
4044 }
4045 ;
4046
4047 cc_op:
4048 ASSIGN
4049 {
4050 $$.r0 = 0;
4051 }
4052 | _BAR_ASSIGN
4053 {
4054 $$.r0 = 1;
4055 }
4056 | _AMPERSAND_ASSIGN
4057 {
4058 $$.r0 = 2;
4059 }
4060 | _CARET_ASSIGN
4061 {
4062 $$.r0 = 3;
4063 }
4064 ;
4065
4066 ccstat:
4067 CCREG cc_op STATUS_REG
4068 {
4069 $$.r0 = $3.regno;
4070 $$.x0 = $2.r0;
4071 $$.s0 = 0;
4072 }
4073 | CCREG cc_op V
4074 {
4075 $$.r0 = 0x18;
4076 $$.x0 = $2.r0;
4077 $$.s0 = 0;
4078 }
4079 | STATUS_REG cc_op CCREG
4080 {
4081 $$.r0 = $1.regno;
4082 $$.x0 = $2.r0;
4083 $$.s0 = 1;
4084 }
4085 | V cc_op CCREG
4086 {
4087 $$.r0 = 0x18;
4088 $$.x0 = $2.r0;
4089 $$.s0 = 1;
4090 }
4091 ;
4092
4093 /* Expressions and Symbols. */
4094
4095 symbol: SYMBOL
4096 {
4097 Expr_Node_Value val;
4098 val.s_value = S_GET_NAME($1);
4099 $$ = Expr_Node_Create (Expr_Node_Reloc, val, NULL, NULL);
4100 }
4101 ;
4102
4103 got: symbol AT GOT
4104 {
4105 $$ = $1;
4106 }
4107 ;
4108
4109 got_or_expr: got
4110 {
4111 $$ = $1;
4112 }
4113 | expr
4114 {
4115 $$ = $1;
4116 }
4117 ;
4118
4119 pltpc :
4120 symbol AT PLTPC
4121 {
4122 $$ = $1;
4123 }
4124 ;
4125
4126 eterm: NUMBER
4127 {
4128 Expr_Node_Value val;
4129 val.i_value = $1;
4130 $$ = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
4131 }
4132 | symbol
4133 {
4134 $$ = $1;
4135 }
4136 | LPAREN expr_1 RPAREN
4137 {
4138 $$ = $2;
4139 }
4140 | TILDA expr_1
4141 {
4142 $$ = unary (Expr_Op_Type_COMP, $2);
4143 }
4144 | MINUS expr_1 %prec TILDA
4145 {
4146 $$ = unary (Expr_Op_Type_NEG, $2);
4147 }
4148 ;
4149
4150 expr: expr_1
4151 {
4152 $$ = $1;
4153 }
4154 ;
4155
4156 expr_1: expr_1 STAR expr_1
4157 {
4158 $$ = binary (Expr_Op_Type_Mult, $1, $3);
4159 }
4160 | expr_1 SLASH expr_1
4161 {
4162 $$ = binary (Expr_Op_Type_Div, $1, $3);
4163 }
4164 | expr_1 PERCENT expr_1
4165 {
4166 $$ = binary (Expr_Op_Type_Mod, $1, $3);
4167 }
4168 | expr_1 PLUS expr_1
4169 {
4170 $$ = binary (Expr_Op_Type_Add, $1, $3);
4171 }
4172 | expr_1 MINUS expr_1
4173 {
4174 $$ = binary (Expr_Op_Type_Sub, $1, $3);
4175 }
4176 | expr_1 LESS_LESS expr_1
4177 {
4178 $$ = binary (Expr_Op_Type_Lshift, $1, $3);
4179 }
4180 | expr_1 GREATER_GREATER expr_1
4181 {
4182 $$ = binary (Expr_Op_Type_Rshift, $1, $3);
4183 }
4184 | expr_1 AMPERSAND expr_1
4185 {
4186 $$ = binary (Expr_Op_Type_BAND, $1, $3);
4187 }
4188 | expr_1 CARET expr_1
4189 {
4190 $$ = binary (Expr_Op_Type_LOR, $1, $3);
4191 }
4192 | expr_1 BAR expr_1
4193 {
4194 $$ = binary (Expr_Op_Type_BOR, $1, $3);
4195 }
4196 | eterm
4197 {
4198 $$ = $1;
4199 }
4200 ;
4201
4202
4203 %%
4204
4205 EXPR_T
4206 mkexpr (int x, SYMBOL_T s)
4207 {
4208 EXPR_T e = (EXPR_T) ALLOCATE (sizeof (struct expression_cell));
4209 e->value = x;
4210 EXPR_SYMBOL(e) = s;
4211 return e;
4212 }
4213
4214 static int
4215 value_match (Expr_Node *expr, int sz, int sign, int mul, int issigned)
4216 {
4217 long umax = (1L << sz) - 1;
4218 long min = -1L << (sz - 1);
4219 long max = (1L << (sz - 1)) - 1;
4220
4221 long v = EXPR_VALUE (expr);
4222
4223 if ((v % mul) != 0)
4224 {
4225 error ("%s:%d: Value Error -- Must align to %d\n", __LINE__, __FILE__, mul);
4226 return 0;
4227 }
4228
4229 v /= mul;
4230
4231 if (sign)
4232 v = -v;
4233
4234 if (issigned)
4235 {
4236 if (v >= min && v <= max) return 1;
4237
4238 #ifdef DEBUG
4239 fprintf(stderr, "signed value %lx out of range\n", v * mul);
4240 #endif
4241 return 0;
4242 }
4243 if (v <= umax && v >= 0)
4244 return 1;
4245 #ifdef DEBUG
4246 fprintf(stderr, "unsigned value %lx out of range\n", v * mul);
4247 #endif
4248 return 0;
4249 }
4250
4251 /* Return the expression structure that allows symbol operations.
4252 If the left and right children are constants, do the operation. */
4253 static Expr_Node *
4254 binary (Expr_Op_Type op, Expr_Node *x, Expr_Node *y)
4255 {
4256 if (x->type == Expr_Node_Constant && y->type == Expr_Node_Constant)
4257 {
4258 switch (op)
4259 {
4260 case Expr_Op_Type_Add:
4261 x->value.i_value += y->value.i_value;
4262 break;
4263 case Expr_Op_Type_Sub:
4264 x->value.i_value -= y->value.i_value;
4265 break;
4266 case Expr_Op_Type_Mult:
4267 x->value.i_value *= y->value.i_value;
4268 break;
4269 case Expr_Op_Type_Div:
4270 if (y->value.i_value == 0)
4271 error ("Illegal Expression: Division by zero.");
4272 else
4273 x->value.i_value /= y->value.i_value;
4274 break;
4275 case Expr_Op_Type_Mod:
4276 x->value.i_value %= y->value.i_value;
4277 break;
4278 case Expr_Op_Type_Lshift:
4279 x->value.i_value <<= y->value.i_value;
4280 break;
4281 case Expr_Op_Type_Rshift:
4282 x->value.i_value >>= y->value.i_value;
4283 break;
4284 case Expr_Op_Type_BAND:
4285 x->value.i_value &= y->value.i_value;
4286 break;
4287 case Expr_Op_Type_BOR:
4288 x->value.i_value |= y->value.i_value;
4289 break;
4290 case Expr_Op_Type_BXOR:
4291 x->value.i_value ^= y->value.i_value;
4292 break;
4293 case Expr_Op_Type_LAND:
4294 x->value.i_value = x->value.i_value && y->value.i_value;
4295 break;
4296 case Expr_Op_Type_LOR:
4297 x->value.i_value = x->value.i_value || y->value.i_value;
4298 break;
4299
4300 default:
4301 error ("%s:%d: Internal compiler error\n", __LINE__, __FILE__);
4302 }
4303 return x;
4304 }
4305 else
4306 {
4307 /* Create a new expression structure. */
4308 Expr_Node_Value val;
4309 val.op_value = op;
4310 return Expr_Node_Create (Expr_Node_Binop, val, x, y);
4311 }
4312 }
4313
4314 static Expr_Node *
4315 unary (Expr_Op_Type op, Expr_Node *x)
4316 {
4317 if (x->type == Expr_Node_Constant)
4318 {
4319 switch (op)
4320 {
4321 case Expr_Op_Type_NEG:
4322 x->value.i_value = -x->value.i_value;
4323 break;
4324 case Expr_Op_Type_COMP:
4325 x->value.i_value = ~x->value.i_value;
4326 break;
4327 default:
4328 error ("%s:%d: Internal compiler error\n", __LINE__, __FILE__);
4329 }
4330 return x;
4331 }
4332 else
4333 {
4334 /* Create a new expression structure. */
4335 Expr_Node_Value val;
4336 val.op_value = op;
4337 return Expr_Node_Create (Expr_Node_Unop, val, x, NULL);
4338 }
4339 }
4340
4341 int debug_codeselection = 0;
4342 static void
4343 notethat (char *format, ...)
4344 {
4345 va_list ap;
4346 va_start (ap, format);
4347 if (debug_codeselection)
4348 {
4349 vfprintf (errorf, format, ap);
4350 }
4351 va_end (ap);
4352 }
4353
4354 #ifdef TEST
4355 main (int argc, char **argv)
4356 {
4357 yyparse();
4358 }
4359 #endif
4360
git-cvsimport of binutils cvsroot