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gas/
[binutils.git] / gas / config / tc-m68k.c
blobff9539e01113c19d2b1a713fba599eeb2922dc06
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
21
22 #include "as.h"
23 #include "safe-ctype.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
31
32 #if defined (OBJ_ELF)
33 #include "elf/m68k.h"
34 #endif
35
36 #ifdef M68KCOFF
37 #include "obj-coff.h"
38 #endif
39
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars = "|#";
46 #else
47 const char *m68k_comment_chars = "|";
48 #endif
49
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars[] = "#*";
58
59 const char line_separator_chars[] = ";";
60
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS[] = "eE";
63
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
66
67 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
68
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
72
73 /* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
75 references. Not implemented. For ELF there are other means
76 to denote pic relocations. */
77 int flag_want_pic;
78
79 static int flag_short_refs; /* -l option. */
80 static int flag_long_jumps; /* -S option. */
81 static int flag_keep_pcrel; /* --pcrel option. */
82
83 #ifdef REGISTER_PREFIX_OPTIONAL
84 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
85 #else
86 int flag_reg_prefix_optional;
87 #endif
88
89 /* Whether --register-prefix-optional was used on the command line. */
90 static int reg_prefix_optional_seen;
91
92 /* The floating point coprocessor to use by default. */
93 static enum m68k_register m68k_float_copnum = COP1;
94
95 /* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97 static int m68k_abspcadd;
98
99 /* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101 static int m68k_quick = 1;
102
103 /* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
105 be 32 bits. */
106 static int m68k_rel32 = 1;
107
108 /* This is non-zero if m68k_rel32 was set from the command line. */
109 static int m68k_rel32_from_cmdline;
110
111 /* The default width to use for an index register when using a base
112 displacement. */
113 static enum m68k_size m68k_index_width_default = SIZE_LONG;
114
115 /* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
117 label. */
118 struct label_line
119 {
120 struct label_line *next;
121 symbolS *label;
122 char *file;
123 unsigned int line;
124 int text;
125 };
126
127 /* The list of labels. */
128
129 static struct label_line *labels;
130
131 /* The current label. */
132
133 static struct label_line *current_label;
134
135 /* Pointer to list holding the opcodes sorted by name. */
136 static struct m68k_opcode const ** m68k_sorted_opcodes;
137
138 /* Its an arbitrary name: This means I don't approve of it.
139 See flames below. */
140 static struct obstack robyn;
141
142 struct m68k_incant
143 {
144 const char *m_operands;
145 unsigned long m_opcode;
146 short m_opnum;
147 short m_codenum;
148 int m_arch;
149 struct m68k_incant *m_next;
150 };
151
152 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153 #define gettwo(x) (((x)->m_opcode)&0xffff)
154
155 static const enum m68k_register m68000_ctrl[] = { 0 };
156 static const enum m68k_register m68010_ctrl[] = {
157 SFC, DFC, USP, VBR,
158 0
159 };
160 static const enum m68k_register m68020_ctrl[] = {
161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
162 0
163 };
164 static const enum m68k_register m68040_ctrl[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
167 0
168 };
169 static const enum m68k_register m68060_ctrl[] = {
170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
172 0
173 };
174 static const enum m68k_register mcf_ctrl[] = {
175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
176 RAMBAR0, RAMBAR1, MBAR,
177 0
178 };
179 static const enum m68k_register mcf5208_ctrl[] = {
180 CACR, ACR0, ACR1, VBR, RAMBAR1,
181 0
182 };
183 static const enum m68k_register mcf5210a_ctrl[] = {
184 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, MBAR,
185 0
186 };
187 static const enum m68k_register mcf5213_ctrl[] = {
188 VBR, RAMBAR, FLASHBAR,
189 0
190 };
191 static const enum m68k_register mcf5216_ctrl[] = {
192 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR,
193 0
194 };
195 static const enum m68k_register mcf52235_ctrl[] = {
196 VBR, FLASHBAR, RAMBAR,
197 0
198 };
199 static const enum m68k_register mcf5225_ctrl[] = {
200 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR,
201 0
202 };
203 static const enum m68k_register mcf5235_ctrl[] = {
204 VBR, CACR, ACR0, ACR1, RAMBAR,
205 0
206 };
207 static const enum m68k_register mcf5249_ctrl[] = {
208 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, MBAR, MBAR2,
209 0
210 };
211 static const enum m68k_register mcf5250_ctrl[] = {
212 VBR,
213 0
214 };
215 static const enum m68k_register mcf5271_ctrl[] = {
216 VBR, CACR, ACR0, ACR1, RAMBAR,
217 0
218 };
219 static const enum m68k_register mcf5272_ctrl[] = {
220 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, MBAR,
221 0
222 };
223 static const enum m68k_register mcf5275_ctrl[] = {
224 VBR, CACR, ACR0, ACR1, RAMBAR,
225 0
226 };
227 static const enum m68k_register mcf5282_ctrl[] = {
228 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR,
229 0
230 };
231 static const enum m68k_register mcf5329_ctrl[] = {
232 VBR, CACR, ACR0, ACR1, RAMBAR,
233 0
234 };
235 static const enum m68k_register mcf5373_ctrl[] = {
236 VBR, CACR, ACR0, ACR1, RAMBAR,
237 0
238 };
239 static const enum m68k_register mcfv4e_ctrl[] = {
240 CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, VBR, PC, ROMBAR,
241 ROMBAR1, RAMBAR0, RAMBAR1, MPCR, EDRAMBAR, SECMBAR, MBAR, MBAR0, MBAR1,
242 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
243 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
244 0
245 };
246 #define cpu32_ctrl m68010_ctrl
247
248 static const enum m68k_register *control_regs;
249
250 /* Internal form of a 68020 instruction. */
251 struct m68k_it
252 {
253 const char *error;
254 const char *args; /* List of opcode info. */
255 int numargs;
256
257 int numo; /* Number of shorts in opcode. */
258 short opcode[11];
259
260 struct m68k_op operands[6];
261
262 int nexp; /* Number of exprs in use. */
263 struct m68k_exp exprs[4];
264
265 int nfrag; /* Number of frags we have to produce. */
266 struct
267 {
268 int fragoff; /* Where in the current opcode the frag ends. */
269 symbolS *fadd;
270 offsetT foff;
271 int fragty;
272 }
273 fragb[4];
274
275 int nrel; /* Num of reloc strucs in use. */
276 struct
277 {
278 int n;
279 expressionS exp;
280 char wid;
281 char pcrel;
282 /* In a pc relative address the difference between the address
283 of the offset and the address that the offset is relative
284 to. This depends on the addressing mode. Basically this
285 is the value to put in the offset field to address the
286 first byte of the offset, without regarding the special
287 significance of some values (in the branch instruction, for
288 example). */
289 int pcrel_fix;
290 #ifdef OBJ_ELF
291 /* Whether this expression needs special pic relocation, and if
292 so, which. */
293 enum pic_relocation pic_reloc;
294 #endif
295 }
296 reloc[5]; /* Five is enough??? */
297 };
298
299 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a))
300 #define float_of_arch(x) ((x) & mfloat)
301 #define mmu_of_arch(x) ((x) & mmmu)
302 #define arch_coldfire_p(x) ((x) & mcfisa_a)
303 #define arch_coldfire_fpu(x) ((x) & cfloat)
304
305 /* Macros for determining if cpu supports a specific addressing mode. */
306 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b))
307
308 static struct m68k_it the_ins; /* The instruction being assembled. */
309
310 #define op(ex) ((ex)->exp.X_op)
311 #define adds(ex) ((ex)->exp.X_add_symbol)
312 #define subs(ex) ((ex)->exp.X_op_symbol)
313 #define offs(ex) ((ex)->exp.X_add_number)
314
315 /* Macros for adding things to the m68k_it struct. */
316 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
317
318 /* Like addword, but goes BEFORE general operands. */
319
320 static void
321 insop (int w, const struct m68k_incant *opcode)
322 {
323 int z;
324 for (z = the_ins.numo; z > opcode->m_codenum; --z)
325 the_ins.opcode[z] = the_ins.opcode[z - 1];
326 for (z = 0; z < the_ins.nrel; z++)
327 the_ins.reloc[z].n += 2;
328 for (z = 0; z < the_ins.nfrag; z++)
329 the_ins.fragb[z].fragoff++;
330 the_ins.opcode[opcode->m_codenum] = w;
331 the_ins.numo++;
332 }
333
334 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
335 Blecch. */
336 static void
337 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
338 {
339 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
340 ? the_ins.numo * 2 - 1
341 : (width == 'b'
342 ? the_ins.numo * 2 + 1
343 : the_ins.numo * 2));
344 the_ins.reloc[the_ins.nrel].exp = exp->exp;
345 the_ins.reloc[the_ins.nrel].wid = width;
346 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
347 #ifdef OBJ_ELF
348 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
349 #endif
350 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
351 }
352
353 /* Cause an extra frag to be generated here, inserting up to 10 bytes
354 (that value is chosen in the frag_var call in md_assemble). TYPE
355 is the subtype of the frag to be generated; its primary type is
356 rs_machine_dependent.
357
358 The TYPE parameter is also used by md_convert_frag_1 and
359 md_estimate_size_before_relax. The appropriate type of fixup will
360 be emitted by md_convert_frag_1.
361
362 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
363 static void
364 add_frag (symbolS *add, offsetT off, int type)
365 {
366 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
367 the_ins.fragb[the_ins.nfrag].fadd = add;
368 the_ins.fragb[the_ins.nfrag].foff = off;
369 the_ins.fragb[the_ins.nfrag++].fragty = type;
370 }
371
372 #define isvar(ex) \
373 (op (ex) != O_constant && op (ex) != O_big)
374
375 static char *crack_operand (char *str, struct m68k_op *opP);
376 static int get_num (struct m68k_exp *exp, int ok);
377 static int reverse_16_bits (int in);
378 static int reverse_8_bits (int in);
379 static void install_gen_operand (int mode, int val);
380 static void install_operand (int mode, int val);
381 static void s_bss (int);
382 static void s_data1 (int);
383 static void s_data2 (int);
384 static void s_even (int);
385 static void s_proc (int);
386 static void s_chip (int);
387 static void s_fopt (int);
388 static void s_opt (int);
389 static void s_reg (int);
390 static void s_restore (int);
391 static void s_save (int);
392 static void s_mri_if (int);
393 static void s_mri_else (int);
394 static void s_mri_endi (int);
395 static void s_mri_break (int);
396 static void s_mri_next (int);
397 static void s_mri_for (int);
398 static void s_mri_endf (int);
399 static void s_mri_repeat (int);
400 static void s_mri_until (int);
401 static void s_mri_while (int);
402 static void s_mri_endw (int);
403 static void s_m68k_cpu (int);
404 static void s_m68k_arch (int);
405
406 struct m68k_cpu
407 {
408 unsigned long arch; /* Architecture features. */
409 const enum m68k_register *control_regs; /* Control regs on chip */
410 const char *name; /* Name */
411 int alias; /* Alias for a cannonical name. If 1, then
412 succeeds canonical name, if -1 then
413 succeeds canonical name, if <-1 ||>1 this is a
414 deprecated name, and the next/previous name
415 should be used. */
416 };
417
418 /* We hold flags for features explicitly enabled and explicitly
419 disabled. */
420 static int current_architecture;
421 static int not_current_architecture;
422 static const struct m68k_cpu *selected_arch;
423 static const struct m68k_cpu *selected_cpu;
424 static int initialized;
425
426 /* Architecture models. */
427 static const struct m68k_cpu m68k_archs[] =
428 {
429 {m68000, m68000_ctrl, "68000", 0},
430 {m68010, m68010_ctrl, "68010", 0},
431 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
432 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
433 {m68040, m68040_ctrl, "68040", 0},
434 {m68060, m68060_ctrl, "68060", 0},
435 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
436 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
437 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
438 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
439 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
440 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
441 {0,0,NULL, 0}
442 };
443
444 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
445 for either. */
446 static const struct m68k_cpu m68k_extensions[] =
447 {
448 {m68851, NULL, "68851", -1},
449 {m68881, NULL, "68881", -1},
450 {m68881, NULL, "68882", -1},
451
452 {cfloat|m68881, NULL, "float", 0},
453
454 {mcfhwdiv, NULL, "div", 1},
455 {mcfusp, NULL, "usp", 1},
456 {mcfmac, NULL, "mac", 1},
457 {mcfemac, NULL, "emac", 1},
458
459 {0,NULL,NULL, 0}
460 };
461
462 /* Processor list */
463 static const struct m68k_cpu m68k_cpus[] =
464 {
465 {m68000, m68000_ctrl, "68000", 0},
466 {m68000, m68000_ctrl, "68ec000", 1},
467 {m68000, m68000_ctrl, "68hc000", 1},
468 {m68000, m68000_ctrl, "68hc001", 1},
469 {m68000, m68000_ctrl, "68008", 1},
470 {m68000, m68000_ctrl, "68302", 1},
471 {m68000, m68000_ctrl, "68306", 1},
472 {m68000, m68000_ctrl, "68307", 1},
473 {m68000, m68000_ctrl, "68322", 1},
474 {m68000, m68000_ctrl, "68356", 1},
475 {m68010, m68010_ctrl, "68010", 0},
476 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
477 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
478 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
479 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
480 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
481 {m68040, m68040_ctrl, "68040", 0},
482 {m68040, m68040_ctrl, "68ec040", 1},
483 {m68060, m68060_ctrl, "68060", 0},
484 {m68060, m68060_ctrl, "68ec060", 1},
485
486 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
487 {cpu32|m68881, cpu32_ctrl, "68330", 1},
488 {cpu32|m68881, cpu32_ctrl, "68331", 1},
489 {cpu32|m68881, cpu32_ctrl, "68332", 1},
490 {cpu32|m68881, cpu32_ctrl, "68333", 1},
491 {cpu32|m68881, cpu32_ctrl, "68334", 1},
492 {cpu32|m68881, cpu32_ctrl, "68336", 1},
493 {cpu32|m68881, cpu32_ctrl, "68340", 1},
494 {cpu32|m68881, cpu32_ctrl, "68341", 1},
495 {cpu32|m68881, cpu32_ctrl, "68349", 1},
496 {cpu32|m68881, cpu32_ctrl, "68360", 1},
497
498 {mcfisa_a, mcf_ctrl, "5200", 0},
499 {mcfisa_a, mcf_ctrl, "5202", 1},
500 {mcfisa_a, mcf_ctrl, "5204", 1},
501 {mcfisa_a, mcf_ctrl, "5206", 1},
502
503 {mcfisa_a|mcfhwdiv|mcfmac, mcf_ctrl, "5206e", 0},
504
505 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
506 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
507
508 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
509 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
510
511 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
512 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
513 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
514
515 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
516 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
517 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
518
519 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
520 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
521 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
522 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
523
524 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
525 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
526
527 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
528 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
529 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
530 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
531 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
532
533 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
534 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
535
536 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
537 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
538
539 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
540
541 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
542 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
543
544 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
545 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
546 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
547 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
548
549 {mcfisa_a|mcfhwdiv|mcfmac, mcf_ctrl, "5307", 0},
550
551 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
552 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
553 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
554 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
555
556 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
557 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
558 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
559
560 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf_ctrl, "5407",0},
561
562 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5470", -1},
563 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5471", -1},
564 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5472", -1},
565 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5473", -1},
566 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5474", -1},
567 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5475", -1},
568 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "547x", 0},
569
570 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5480", -1},
571 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5481", -1},
572 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5482", -1},
573 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5483", -1},
574 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5484", -1},
575 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5485", -1},
576 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "548x", 0},
577
578 {0,NULL,NULL, 0}
579 };
580
581 static const struct m68k_cpu *m68k_lookup_cpu
582 (const char *, const struct m68k_cpu *, int, int *);
583 static int m68k_set_arch (const char *, int, int);
584 static int m68k_set_cpu (const char *, int, int);
585 static int m68k_set_extension (const char *, int, int);
586 static void m68k_init_arch (void);
587
588 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
589 architecture and we have a lot of relaxation modes. */
590
591 /* Macros used in the relaxation code. */
592 #define TAB(x,y) (((x) << 2) + (y))
593 #define TABTYPE(x) ((x) >> 2)
594
595 /* Relaxation states. */
596 #define BYTE 0
597 #define SHORT 1
598 #define LONG 2
599 #define SZ_UNDEF 3
600
601 /* Here are all the relaxation modes we support. First we can relax ordinary
602 branches. On 68020 and higher and on CPU32 all branch instructions take
603 three forms, so on these CPUs all branches always remain as such. When we
604 have to expand to the LONG form on a 68000, though, we substitute an
605 absolute jump instead. This is a direct replacement for unconditional
606 branches and a branch over a jump for conditional branches. However, if the
607 user requires PIC and disables this with --pcrel, we can only relax between
608 BYTE and SHORT forms, punting if that isn't enough. This gives us four
609 different relaxation modes for branches: */
610
611 #define BRANCHBWL 0 /* Branch byte, word, or long. */
612 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
613 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
614 #define BRANCHBW 3 /* Branch byte or word. */
615
616 /* We also relax coprocessor branches and DBcc's. All CPUs that support
617 coprocessor branches support them in word and long forms, so we have only
618 one relaxation mode for them. DBcc's are word only on all CPUs. We can
619 relax them to the LONG form with a branch-around sequence. This sequence
620 can use a long branch (if available) or an absolute jump (if acceptable).
621 This gives us two relaxation modes. If long branches are not available and
622 absolute jumps are not acceptable, we don't relax DBcc's. */
623
624 #define FBRANCH 4 /* Coprocessor branch. */
625 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
626 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
627
628 /* That's all for instruction relaxation. However, we also relax PC-relative
629 operands. Specifically, we have three operand relaxation modes. On the
630 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
631 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
632 two. Also PC+displacement+index operands in their simple form (with a non-
633 suppressed index without memory indirection) are supported on all CPUs, but
634 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
635 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
636 form of the PC+displacement+index operand. Finally, some absolute operands
637 can be relaxed down to 16-bit PC-relative. */
638
639 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
640 #define PCINDEX 8 /* PC + displacement + index. */
641 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
642
643 /* Note that calls to frag_var need to specify the maximum expansion
644 needed; this is currently 10 bytes for DBCC. */
645
646 /* The fields are:
647 How far Forward this mode will reach:
648 How far Backward this mode will reach:
649 How many bytes this mode will add to the size of the frag
650 Which mode to go to if the offset won't fit in this one
651
652 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
653 relax_typeS md_relax_table[] =
654 {
655 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
656 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
657 { 0, 0, 4, 0 },
658 { 1, 1, 0, 0 },
659
660 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
661 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
662 { 0, 0, 4, 0 },
663 { 1, 1, 0, 0 },
664
665 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
666 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
667 { 0, 0, 6, 0 },
668 { 1, 1, 0, 0 },
669
670 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
671 { 0, 0, 2, 0 },
672 { 1, 1, 0, 0 },
673 { 1, 1, 0, 0 },
674
675 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
676 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
677 { 0, 0, 4, 0 },
678 { 1, 1, 0, 0 },
679
680 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
681 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
682 { 0, 0, 10, 0 },
683 { 1, 1, 0, 0 },
684
685 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
686 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
687 { 0, 0, 10, 0 },
688 { 1, 1, 0, 0 },
689
690 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
691 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
692 { 0, 0, 6, 0 },
693 { 1, 1, 0, 0 },
694
695 { 125, -130, 0, TAB (PCINDEX, SHORT) },
696 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
697 { 0, 0, 4, 0 },
698 { 1, 1, 0, 0 },
699
700 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
701 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
702 { 0, 0, 4, 0 },
703 { 1, 1, 0, 0 },
704 };
705
706 /* These are the machine dependent pseudo-ops. These are included so
707 the assembler can work on the output from the SUN C compiler, which
708 generates these. */
709
710 /* This table describes all the machine specific pseudo-ops the assembler
711 has to support. The fields are:
712 pseudo-op name without dot
713 function to call to execute this pseudo-op
714 Integer arg to pass to the function. */
715 const pseudo_typeS md_pseudo_table[] =
716 {
717 {"data1", s_data1, 0},
718 {"data2", s_data2, 0},
719 {"bss", s_bss, 0},
720 {"even", s_even, 0},
721 {"skip", s_space, 0},
722 {"proc", s_proc, 0},
723 #if defined (TE_SUN3) || defined (OBJ_ELF)
724 {"align", s_align_bytes, 0},
725 #endif
726 #ifdef OBJ_ELF
727 {"swbeg", s_ignore, 0},
728 #endif
729 {"extend", float_cons, 'x'},
730 {"ldouble", float_cons, 'x'},
731
732 {"arch", s_m68k_arch, 0},
733 {"cpu", s_m68k_cpu, 0},
734
735 /* The following pseudo-ops are supported for MRI compatibility. */
736 {"chip", s_chip, 0},
737 {"comline", s_space, 1},
738 {"fopt", s_fopt, 0},
739 {"mask2", s_ignore, 0},
740 {"opt", s_opt, 0},
741 {"reg", s_reg, 0},
742 {"restore", s_restore, 0},
743 {"save", s_save, 0},
744
745 {"if", s_mri_if, 0},
746 {"if.b", s_mri_if, 'b'},
747 {"if.w", s_mri_if, 'w'},
748 {"if.l", s_mri_if, 'l'},
749 {"else", s_mri_else, 0},
750 {"else.s", s_mri_else, 's'},
751 {"else.l", s_mri_else, 'l'},
752 {"endi", s_mri_endi, 0},
753 {"break", s_mri_break, 0},
754 {"break.s", s_mri_break, 's'},
755 {"break.l", s_mri_break, 'l'},
756 {"next", s_mri_next, 0},
757 {"next.s", s_mri_next, 's'},
758 {"next.l", s_mri_next, 'l'},
759 {"for", s_mri_for, 0},
760 {"for.b", s_mri_for, 'b'},
761 {"for.w", s_mri_for, 'w'},
762 {"for.l", s_mri_for, 'l'},
763 {"endf", s_mri_endf, 0},
764 {"repeat", s_mri_repeat, 0},
765 {"until", s_mri_until, 0},
766 {"until.b", s_mri_until, 'b'},
767 {"until.w", s_mri_until, 'w'},
768 {"until.l", s_mri_until, 'l'},
769 {"while", s_mri_while, 0},
770 {"while.b", s_mri_while, 'b'},
771 {"while.w", s_mri_while, 'w'},
772 {"while.l", s_mri_while, 'l'},
773 {"endw", s_mri_endw, 0},
774
775 {0, 0, 0}
776 };
777
778 /* The mote pseudo ops are put into the opcode table, since they
779 don't start with a . they look like opcodes to gas. */
780
781 const pseudo_typeS mote_pseudo_table[] =
782 {
783
784 {"dcl", cons, 4},
785 {"dc", cons, 2},
786 {"dcw", cons, 2},
787 {"dcb", cons, 1},
788
789 {"dsl", s_space, 4},
790 {"ds", s_space, 2},
791 {"dsw", s_space, 2},
792 {"dsb", s_space, 1},
793
794 {"xdef", s_globl, 0},
795 #ifdef OBJ_ELF
796 {"align", s_align_bytes, 0},
797 #else
798 {"align", s_align_ptwo, 0},
799 #endif
800 #ifdef M68KCOFF
801 {"sect", obj_coff_section, 0},
802 {"section", obj_coff_section, 0},
803 #endif
804 {0, 0, 0}
805 };
806
807 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
808 gives identical results to a 32-bit host. */
809 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
810 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
811
812 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
813 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
814 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
815 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
816
817 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
818 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
819 #define islong(x) (1)
820
821 static char notend_table[256];
822 static char alt_notend_table[256];
823 #define notend(s) \
824 (! (notend_table[(unsigned char) *s] \
825 || (*s == ':' \
826 && alt_notend_table[(unsigned char) s[1]])))
827
828 #ifdef OBJ_ELF
829
830 /* Return zero if the reference to SYMBOL from within the same segment may
831 be relaxed. */
832
833 /* On an ELF system, we can't relax an externally visible symbol,
834 because it may be overridden by a shared library. However, if
835 TARGET_OS is "elf", then we presume that we are assembling for an
836 embedded system, in which case we don't have to worry about shared
837 libraries, and we can relax any external sym. */
838
839 #define relaxable_symbol(symbol) \
840 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
841 || S_IS_WEAK (symbol)))
842
843 /* Compute the relocation code for a fixup of SIZE bytes, using pc
844 relative relocation if PCREL is non-zero. PIC says whether a special
845 pic relocation was requested. */
846
847 static bfd_reloc_code_real_type
848 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
849 {
850 switch (pic)
851 {
852 case pic_got_pcrel:
853 switch (size)
854 {
855 case 1:
856 return BFD_RELOC_8_GOT_PCREL;
857 case 2:
858 return BFD_RELOC_16_GOT_PCREL;
859 case 4:
860 return BFD_RELOC_32_GOT_PCREL;
861 }
862 break;
863
864 case pic_got_off:
865 switch (size)
866 {
867 case 1:
868 return BFD_RELOC_8_GOTOFF;
869 case 2:
870 return BFD_RELOC_16_GOTOFF;
871 case 4:
872 return BFD_RELOC_32_GOTOFF;
873 }
874 break;
875
876 case pic_plt_pcrel:
877 switch (size)
878 {
879 case 1:
880 return BFD_RELOC_8_PLT_PCREL;
881 case 2:
882 return BFD_RELOC_16_PLT_PCREL;
883 case 4:
884 return BFD_RELOC_32_PLT_PCREL;
885 }
886 break;
887
888 case pic_plt_off:
889 switch (size)
890 {
891 case 1:
892 return BFD_RELOC_8_PLTOFF;
893 case 2:
894 return BFD_RELOC_16_PLTOFF;
895 case 4:
896 return BFD_RELOC_32_PLTOFF;
897 }
898 break;
899
900 case pic_none:
901 if (pcrel)
902 {
903 switch (size)
904 {
905 case 1:
906 return BFD_RELOC_8_PCREL;
907 case 2:
908 return BFD_RELOC_16_PCREL;
909 case 4:
910 return BFD_RELOC_32_PCREL;
911 }
912 }
913 else
914 {
915 switch (size)
916 {
917 case 1:
918 return BFD_RELOC_8;
919 case 2:
920 return BFD_RELOC_16;
921 case 4:
922 return BFD_RELOC_32;
923 }
924 }
925 }
926
927 if (pcrel)
928 {
929 if (pic == pic_none)
930 as_bad (_("Can not do %d byte pc-relative relocation"), size);
931 else
932 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
933 }
934 else
935 {
936 if (pic == pic_none)
937 as_bad (_("Can not do %d byte relocation"), size);
938 else
939 as_bad (_("Can not do %d byte pic relocation"), size);
940 }
941
942 return BFD_RELOC_NONE;
943 }
944
945 /* Here we decide which fixups can be adjusted to make them relative
946 to the beginning of the section instead of the symbol. Basically
947 we need to make sure that the dynamic relocations are done
948 correctly, so in some cases we force the original symbol to be
949 used. */
950 int
951 tc_m68k_fix_adjustable (fixS *fixP)
952 {
953 /* Adjust_reloc_syms doesn't know about the GOT. */
954 switch (fixP->fx_r_type)
955 {
956 case BFD_RELOC_8_GOT_PCREL:
957 case BFD_RELOC_16_GOT_PCREL:
958 case BFD_RELOC_32_GOT_PCREL:
959 case BFD_RELOC_8_GOTOFF:
960 case BFD_RELOC_16_GOTOFF:
961 case BFD_RELOC_32_GOTOFF:
962 case BFD_RELOC_8_PLT_PCREL:
963 case BFD_RELOC_16_PLT_PCREL:
964 case BFD_RELOC_32_PLT_PCREL:
965 case BFD_RELOC_8_PLTOFF:
966 case BFD_RELOC_16_PLTOFF:
967 case BFD_RELOC_32_PLTOFF:
968 return 0;
969
970 case BFD_RELOC_VTABLE_INHERIT:
971 case BFD_RELOC_VTABLE_ENTRY:
972 return 0;
973
974 default:
975 return 1;
976 }
977 }
978
979 #else /* !OBJ_ELF */
980
981 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
982
983 #define relaxable_symbol(symbol) 1
984
985 #endif /* OBJ_ELF */
986
987 arelent *
988 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
989 {
990 arelent *reloc;
991 bfd_reloc_code_real_type code;
992
993 /* If the tcbit is set, then this was a fixup of a negative value
994 that was never resolved. We do not have a reloc to handle this,
995 so just return. We assume that other code will have detected this
996 situation and produced a helpful error message, so we just tell the
997 user that the reloc cannot be produced. */
998 if (fixp->fx_tcbit)
999 {
1000 if (fixp->fx_addsy)
1001 as_bad_where (fixp->fx_file, fixp->fx_line,
1002 _("Unable to produce reloc against symbol '%s'"),
1003 S_GET_NAME (fixp->fx_addsy));
1004 return NULL;
1005 }
1006
1007 if (fixp->fx_r_type != BFD_RELOC_NONE)
1008 {
1009 code = fixp->fx_r_type;
1010
1011 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1012 that fixup_segment converted a non-PC relative reloc into a
1013 PC relative reloc. In such a case, we need to convert the
1014 reloc code. */
1015 if (fixp->fx_pcrel)
1016 {
1017 switch (code)
1018 {
1019 case BFD_RELOC_8:
1020 code = BFD_RELOC_8_PCREL;
1021 break;
1022 case BFD_RELOC_16:
1023 code = BFD_RELOC_16_PCREL;
1024 break;
1025 case BFD_RELOC_32:
1026 code = BFD_RELOC_32_PCREL;
1027 break;
1028 case BFD_RELOC_8_PCREL:
1029 case BFD_RELOC_16_PCREL:
1030 case BFD_RELOC_32_PCREL:
1031 case BFD_RELOC_8_GOT_PCREL:
1032 case BFD_RELOC_16_GOT_PCREL:
1033 case BFD_RELOC_32_GOT_PCREL:
1034 case BFD_RELOC_8_GOTOFF:
1035 case BFD_RELOC_16_GOTOFF:
1036 case BFD_RELOC_32_GOTOFF:
1037 case BFD_RELOC_8_PLT_PCREL:
1038 case BFD_RELOC_16_PLT_PCREL:
1039 case BFD_RELOC_32_PLT_PCREL:
1040 case BFD_RELOC_8_PLTOFF:
1041 case BFD_RELOC_16_PLTOFF:
1042 case BFD_RELOC_32_PLTOFF:
1043 break;
1044 default:
1045 as_bad_where (fixp->fx_file, fixp->fx_line,
1046 _("Cannot make %s relocation PC relative"),
1047 bfd_get_reloc_code_name (code));
1048 }
1049 }
1050 }
1051 else
1052 {
1053 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1054 switch (F (fixp->fx_size, fixp->fx_pcrel))
1055 {
1056 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1057 MAP (1, 0, BFD_RELOC_8);
1058 MAP (2, 0, BFD_RELOC_16);
1059 MAP (4, 0, BFD_RELOC_32);
1060 MAP (1, 1, BFD_RELOC_8_PCREL);
1061 MAP (2, 1, BFD_RELOC_16_PCREL);
1062 MAP (4, 1, BFD_RELOC_32_PCREL);
1063 default:
1064 abort ();
1065 }
1066 }
1067 #undef F
1068 #undef MAP
1069
1070 reloc = (arelent *) xmalloc (sizeof (arelent));
1071 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1072 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1073 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1074 #ifndef OBJ_ELF
1075 if (fixp->fx_pcrel)
1076 reloc->addend = fixp->fx_addnumber;
1077 else
1078 reloc->addend = 0;
1079 #else
1080 if (!fixp->fx_pcrel)
1081 reloc->addend = fixp->fx_addnumber;
1082 else
1083 reloc->addend = (section->vma
1084 /* Explicit sign extension in case char is
1085 unsigned. */
1086 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1087 + fixp->fx_addnumber
1088 + md_pcrel_from (fixp));
1089 #endif
1090
1091 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1092 assert (reloc->howto != 0);
1093
1094 return reloc;
1095 }
1096
1097 /* Handle of the OPCODE hash table. NULL means any use before
1098 m68k_ip_begin() will crash. */
1099 static struct hash_control *op_hash;
1100 \f
1101 /* Assemble an m68k instruction. */
1102
1103 static void
1104 m68k_ip (char *instring)
1105 {
1106 register char *p;
1107 register struct m68k_op *opP;
1108 register const struct m68k_incant *opcode;
1109 register const char *s;
1110 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1111 char *pdot, *pdotmove;
1112 enum m68k_size siz1, siz2;
1113 char c;
1114 int losing;
1115 int opsfound;
1116 struct m68k_op operands_backup[6];
1117 LITTLENUM_TYPE words[6];
1118 LITTLENUM_TYPE *wordp;
1119 unsigned long ok_arch = 0;
1120
1121 if (*instring == ' ')
1122 instring++; /* Skip leading whitespace. */
1123
1124 /* Scan up to end of operation-code, which MUST end in end-of-string
1125 or exactly 1 space. */
1126 pdot = 0;
1127 for (p = instring; *p != '\0'; p++)
1128 {
1129 if (*p == ' ')
1130 break;
1131 if (*p == '.')
1132 pdot = p;
1133 }
1134
1135 if (p == instring)
1136 {
1137 the_ins.error = _("No operator");
1138 return;
1139 }
1140
1141 /* p now points to the end of the opcode name, probably whitespace.
1142 Make sure the name is null terminated by clobbering the
1143 whitespace, look it up in the hash table, then fix it back.
1144 Remove a dot, first, since the opcode tables have none. */
1145 if (pdot != NULL)
1146 {
1147 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1148 *pdotmove = pdotmove[1];
1149 p--;
1150 }
1151
1152 c = *p;
1153 *p = '\0';
1154 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1155 *p = c;
1156
1157 if (pdot != NULL)
1158 {
1159 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1160 *pdotmove = pdotmove[-1];
1161 *pdot = '.';
1162 ++p;
1163 }
1164
1165 if (opcode == NULL)
1166 {
1167 the_ins.error = _("Unknown operator");
1168 return;
1169 }
1170
1171 /* Found a legitimate opcode, start matching operands. */
1172 while (*p == ' ')
1173 ++p;
1174
1175 if (opcode->m_operands == 0)
1176 {
1177 char *old = input_line_pointer;
1178 *old = '\n';
1179 input_line_pointer = p;
1180 /* Ahh - it's a motorola style psuedo op. */
1181 mote_pseudo_table[opcode->m_opnum].poc_handler
1182 (mote_pseudo_table[opcode->m_opnum].poc_val);
1183 input_line_pointer = old;
1184 *old = 0;
1185
1186 return;
1187 }
1188
1189 if (flag_mri && opcode->m_opnum == 0)
1190 {
1191 /* In MRI mode, random garbage is allowed after an instruction
1192 which accepts no operands. */
1193 the_ins.args = opcode->m_operands;
1194 the_ins.numargs = opcode->m_opnum;
1195 the_ins.numo = opcode->m_codenum;
1196 the_ins.opcode[0] = getone (opcode);
1197 the_ins.opcode[1] = gettwo (opcode);
1198 return;
1199 }
1200
1201 for (opP = &the_ins.operands[0]; *p; opP++)
1202 {
1203 p = crack_operand (p, opP);
1204
1205 if (opP->error)
1206 {
1207 the_ins.error = opP->error;
1208 return;
1209 }
1210 }
1211
1212 opsfound = opP - &the_ins.operands[0];
1213
1214 /* This ugly hack is to support the floating pt opcodes in their
1215 standard form. Essentially, we fake a first enty of type COP#1 */
1216 if (opcode->m_operands[0] == 'I')
1217 {
1218 int n;
1219
1220 for (n = opsfound; n > 0; --n)
1221 the_ins.operands[n] = the_ins.operands[n - 1];
1222
1223 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1224 the_ins.operands[0].mode = CONTROL;
1225 the_ins.operands[0].reg = m68k_float_copnum;
1226 opsfound++;
1227 }
1228
1229 /* We've got the operands. Find an opcode that'll accept them. */
1230 for (losing = 0;;)
1231 {
1232 /* If we didn't get the right number of ops, or we have no
1233 common model with this pattern then reject this pattern. */
1234
1235 ok_arch |= opcode->m_arch;
1236 if (opsfound != opcode->m_opnum
1237 || ((opcode->m_arch & current_architecture) == 0))
1238 ++losing;
1239 else
1240 {
1241 int i;
1242
1243 /* Make a copy of the operands of this insn so that
1244 we can modify them safely, should we want to. */
1245 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1246 for (i = 0; i < opsfound; i++)
1247 operands_backup[i] = the_ins.operands[i];
1248
1249 for (s = opcode->m_operands, opP = &operands_backup[0];
1250 *s && !losing;
1251 s += 2, opP++)
1252 {
1253 /* Warning: this switch is huge! */
1254 /* I've tried to organize the cases into this order:
1255 non-alpha first, then alpha by letter. Lower-case
1256 goes directly before uppercase counterpart. */
1257 /* Code with multiple case ...: gets sorted by the lowest
1258 case ... it belongs to. I hope this makes sense. */
1259 switch (*s)
1260 {
1261 case '!':
1262 switch (opP->mode)
1263 {
1264 case IMMED:
1265 case DREG:
1266 case AREG:
1267 case FPREG:
1268 case CONTROL:
1269 case AINC:
1270 case ADEC:
1271 case REGLST:
1272 losing++;
1273 break;
1274 default:
1275 break;
1276 }
1277 break;
1278
1279 case '<':
1280 switch (opP->mode)
1281 {
1282 case DREG:
1283 case AREG:
1284 case FPREG:
1285 case CONTROL:
1286 case IMMED:
1287 case ADEC:
1288 case REGLST:
1289 losing++;
1290 break;
1291 default:
1292 break;
1293 }
1294 break;
1295
1296 case '>':
1297 switch (opP->mode)
1298 {
1299 case DREG:
1300 case AREG:
1301 case FPREG:
1302 case CONTROL:
1303 case IMMED:
1304 case AINC:
1305 case REGLST:
1306 losing++;
1307 break;
1308 case ABSL:
1309 break;
1310 default:
1311 if (opP->reg == PC
1312 || opP->reg == ZPC)
1313 losing++;
1314 break;
1315 }
1316 break;
1317
1318 case 'm':
1319 switch (opP->mode)
1320 {
1321 case DREG:
1322 case AREG:
1323 case AINDR:
1324 case AINC:
1325 case ADEC:
1326 break;
1327 default:
1328 losing++;
1329 }
1330 break;
1331
1332 case 'n':
1333 switch (opP->mode)
1334 {
1335 case DISP:
1336 break;
1337 default:
1338 losing++;
1339 }
1340 break;
1341
1342 case 'o':
1343 switch (opP->mode)
1344 {
1345 case BASE:
1346 case ABSL:
1347 case IMMED:
1348 break;
1349 default:
1350 losing++;
1351 }
1352 break;
1353
1354 case 'p':
1355 switch (opP->mode)
1356 {
1357 case DREG:
1358 case AREG:
1359 case AINDR:
1360 case AINC:
1361 case ADEC:
1362 break;
1363 case DISP:
1364 if (opP->reg == PC || opP->reg == ZPC)
1365 losing++;
1366 break;
1367 default:
1368 losing++;
1369 }
1370 break;
1371
1372 case 'q':
1373 switch (opP->mode)
1374 {
1375 case DREG:
1376 case AINDR:
1377 case AINC:
1378 case ADEC:
1379 break;
1380 case DISP:
1381 if (opP->reg == PC || opP->reg == ZPC)
1382 losing++;
1383 break;
1384 default:
1385 losing++;
1386 break;
1387 }
1388 break;
1389
1390 case 'v':
1391 switch (opP->mode)
1392 {
1393 case DREG:
1394 case AINDR:
1395 case AINC:
1396 case ADEC:
1397 case ABSL:
1398 break;
1399 case DISP:
1400 if (opP->reg == PC || opP->reg == ZPC)
1401 losing++;
1402 break;
1403 default:
1404 losing++;
1405 break;
1406 }
1407 break;
1408
1409 case '#':
1410 if (opP->mode != IMMED)
1411 losing++;
1412 else if (s[1] == 'b'
1413 && ! isvar (&opP->disp)
1414 && (opP->disp.exp.X_op != O_constant
1415 || ! isbyte (opP->disp.exp.X_add_number)))
1416 losing++;
1417 else if (s[1] == 'B'
1418 && ! isvar (&opP->disp)
1419 && (opP->disp.exp.X_op != O_constant
1420 || ! issbyte (opP->disp.exp.X_add_number)))
1421 losing++;
1422 else if (s[1] == 'w'
1423 && ! isvar (&opP->disp)
1424 && (opP->disp.exp.X_op != O_constant
1425 || ! isword (opP->disp.exp.X_add_number)))
1426 losing++;
1427 else if (s[1] == 'W'
1428 && ! isvar (&opP->disp)
1429 && (opP->disp.exp.X_op != O_constant
1430 || ! issword (opP->disp.exp.X_add_number)))
1431 losing++;
1432 break;
1433
1434 case '^':
1435 case 'T':
1436 if (opP->mode != IMMED)
1437 losing++;
1438 break;
1439
1440 case '$':
1441 if (opP->mode == AREG
1442 || opP->mode == CONTROL
1443 || opP->mode == FPREG
1444 || opP->mode == IMMED
1445 || opP->mode == REGLST
1446 || (opP->mode != ABSL
1447 && (opP->reg == PC
1448 || opP->reg == ZPC)))
1449 losing++;
1450 break;
1451
1452 case '%':
1453 if (opP->mode == CONTROL
1454 || opP->mode == FPREG
1455 || opP->mode == REGLST
1456 || opP->mode == IMMED
1457 || (opP->mode != ABSL
1458 && (opP->reg == PC
1459 || opP->reg == ZPC)))
1460 losing++;
1461 break;
1462
1463 case '&':
1464 switch (opP->mode)
1465 {
1466 case DREG:
1467 case AREG:
1468 case FPREG:
1469 case CONTROL:
1470 case IMMED:
1471 case AINC:
1472 case ADEC:
1473 case REGLST:
1474 losing++;
1475 break;
1476 case ABSL:
1477 break;
1478 default:
1479 if (opP->reg == PC
1480 || opP->reg == ZPC)
1481 losing++;
1482 break;
1483 }
1484 break;
1485
1486 case '*':
1487 if (opP->mode == CONTROL
1488 || opP->mode == FPREG
1489 || opP->mode == REGLST)
1490 losing++;
1491 break;
1492
1493 case '+':
1494 if (opP->mode != AINC)
1495 losing++;
1496 break;
1497
1498 case '-':
1499 if (opP->mode != ADEC)
1500 losing++;
1501 break;
1502
1503 case '/':
1504 switch (opP->mode)
1505 {
1506 case AREG:
1507 case CONTROL:
1508 case FPREG:
1509 case AINC:
1510 case ADEC:
1511 case IMMED:
1512 case REGLST:
1513 losing++;
1514 break;
1515 default:
1516 break;
1517 }
1518 break;
1519
1520 case ';':
1521 switch (opP->mode)
1522 {
1523 case AREG:
1524 case CONTROL:
1525 case FPREG:
1526 case REGLST:
1527 losing++;
1528 break;
1529 default:
1530 break;
1531 }
1532 break;
1533
1534 case '?':
1535 switch (opP->mode)
1536 {
1537 case AREG:
1538 case CONTROL:
1539 case FPREG:
1540 case AINC:
1541 case ADEC:
1542 case IMMED:
1543 case REGLST:
1544 losing++;
1545 break;
1546 case ABSL:
1547 break;
1548 default:
1549 if (opP->reg == PC || opP->reg == ZPC)
1550 losing++;
1551 break;
1552 }
1553 break;
1554
1555 case '@':
1556 switch (opP->mode)
1557 {
1558 case AREG:
1559 case CONTROL:
1560 case FPREG:
1561 case IMMED:
1562 case REGLST:
1563 losing++;
1564 break;
1565 default:
1566 break;
1567 }
1568 break;
1569
1570 case '~': /* For now! (JF FOO is this right?) */
1571 switch (opP->mode)
1572 {
1573 case DREG:
1574 case AREG:
1575 case CONTROL:
1576 case FPREG:
1577 case IMMED:
1578 case REGLST:
1579 losing++;
1580 break;
1581 case ABSL:
1582 break;
1583 default:
1584 if (opP->reg == PC
1585 || opP->reg == ZPC)
1586 losing++;
1587 break;
1588 }
1589 break;
1590
1591 case '3':
1592 if (opP->mode != CONTROL
1593 || (opP->reg != TT0 && opP->reg != TT1))
1594 losing++;
1595 break;
1596
1597 case 'A':
1598 if (opP->mode != AREG)
1599 losing++;
1600 break;
1601
1602 case 'a':
1603 if (opP->mode != AINDR)
1604 ++losing;
1605 break;
1606
1607 case '4':
1608 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1609 && (opP->mode != DISP
1610 || opP->reg < ADDR0
1611 || opP->reg > ADDR7))
1612 ++losing;
1613 break;
1614
1615 case 'B': /* FOO */
1616 if (opP->mode != ABSL
1617 || (flag_long_jumps
1618 && strncmp (instring, "jbsr", 4) == 0))
1619 losing++;
1620 break;
1621
1622 case 'b':
1623 switch (opP->mode)
1624 {
1625 case IMMED:
1626 case ABSL:
1627 case AREG:
1628 case FPREG:
1629 case CONTROL:
1630 case POST:
1631 case PRE:
1632 case REGLST:
1633 losing++;
1634 break;
1635 default:
1636 break;
1637 }
1638 break;
1639
1640 case 'C':
1641 if (opP->mode != CONTROL || opP->reg != CCR)
1642 losing++;
1643 break;
1644
1645 case 'd':
1646 if (opP->mode != DISP
1647 || opP->reg < ADDR0
1648 || opP->reg > ADDR7)
1649 losing++;
1650 break;
1651
1652 case 'D':
1653 if (opP->mode != DREG)
1654 losing++;
1655 break;
1656
1657 case 'E':
1658 if (opP->reg != ACC)
1659 losing++;
1660 break;
1661
1662 case 'e':
1663 if (opP->reg != ACC && opP->reg != ACC1
1664 && opP->reg != ACC2 && opP->reg != ACC3)
1665 losing++;
1666 break;
1667
1668 case 'F':
1669 if (opP->mode != FPREG)
1670 losing++;
1671 break;
1672
1673 case 'G':
1674 if (opP->reg != MACSR)
1675 losing++;
1676 break;
1677
1678 case 'g':
1679 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1680 losing++;
1681 break;
1682
1683 case 'H':
1684 if (opP->reg != MASK)
1685 losing++;
1686 break;
1687
1688 case 'I':
1689 if (opP->mode != CONTROL
1690 || opP->reg < COP0
1691 || opP->reg > COP7)
1692 losing++;
1693 break;
1694
1695 case 'i':
1696 if (opP->mode != LSH && opP->mode != RSH)
1697 losing++;
1698 break;
1699
1700 case 'J':
1701 if (opP->mode != CONTROL
1702 || opP->reg < USP
1703 || opP->reg > last_movec_reg
1704 || !control_regs)
1705 losing++;
1706 else
1707 {
1708 const enum m68k_register *rp;
1709
1710 for (rp = control_regs; *rp; rp++)
1711 if (*rp == opP->reg)
1712 break;
1713 if (*rp == 0)
1714 losing++;
1715 }
1716 break;
1717
1718 case 'k':
1719 if (opP->mode != IMMED)
1720 losing++;
1721 break;
1722
1723 case 'l':
1724 case 'L':
1725 if (opP->mode == DREG
1726 || opP->mode == AREG
1727 || opP->mode == FPREG)
1728 {
1729 if (s[1] == '8')
1730 losing++;
1731 else
1732 {
1733 switch (opP->mode)
1734 {
1735 case DREG:
1736 opP->mask = 1 << (opP->reg - DATA0);
1737 break;
1738 case AREG:
1739 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1740 break;
1741 case FPREG:
1742 opP->mask = 1 << (opP->reg - FP0 + 16);
1743 break;
1744 default:
1745 abort ();
1746 }
1747 opP->mode = REGLST;
1748 }
1749 }
1750 else if (opP->mode == CONTROL)
1751 {
1752 if (s[1] != '8')
1753 losing++;
1754 else
1755 {
1756 switch (opP->reg)
1757 {
1758 case FPI:
1759 opP->mask = 1 << 24;
1760 break;
1761 case FPS:
1762 opP->mask = 1 << 25;
1763 break;
1764 case FPC:
1765 opP->mask = 1 << 26;
1766 break;
1767 default:
1768 losing++;
1769 break;
1770 }
1771 opP->mode = REGLST;
1772 }
1773 }
1774 else if (opP->mode != REGLST)
1775 losing++;
1776 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1777 losing++;
1778 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1779 losing++;
1780 break;
1781
1782 case 'M':
1783 if (opP->mode != IMMED)
1784 losing++;
1785 else if (opP->disp.exp.X_op != O_constant
1786 || ! issbyte (opP->disp.exp.X_add_number))
1787 losing++;
1788 else if (! m68k_quick
1789 && instring[3] != 'q'
1790 && instring[4] != 'q')
1791 losing++;
1792 break;
1793
1794 case 'O':
1795 if (opP->mode != DREG
1796 && opP->mode != IMMED
1797 && opP->mode != ABSL)
1798 losing++;
1799 break;
1800
1801 case 'Q':
1802 if (opP->mode != IMMED)
1803 losing++;
1804 else if (opP->disp.exp.X_op != O_constant
1805 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1806 losing++;
1807 else if (! m68k_quick
1808 && (strncmp (instring, "add", 3) == 0
1809 || strncmp (instring, "sub", 3) == 0)
1810 && instring[3] != 'q')
1811 losing++;
1812 break;
1813
1814 case 'R':
1815 if (opP->mode != DREG && opP->mode != AREG)
1816 losing++;
1817 break;
1818
1819 case 'r':
1820 if (opP->mode != AINDR
1821 && (opP->mode != BASE
1822 || (opP->reg != 0
1823 && opP->reg != ZADDR0)
1824 || opP->disp.exp.X_op != O_absent
1825 || ((opP->index.reg < DATA0
1826 || opP->index.reg > DATA7)
1827 && (opP->index.reg < ADDR0
1828 || opP->index.reg > ADDR7))
1829 || opP->index.size != SIZE_UNSPEC
1830 || opP->index.scale != 1))
1831 losing++;
1832 break;
1833
1834 case 's':
1835 if (opP->mode != CONTROL
1836 || ! (opP->reg == FPI
1837 || opP->reg == FPS
1838 || opP->reg == FPC))
1839 losing++;
1840 break;
1841
1842 case 'S':
1843 if (opP->mode != CONTROL || opP->reg != SR)
1844 losing++;
1845 break;
1846
1847 case 't':
1848 if (opP->mode != IMMED)
1849 losing++;
1850 else if (opP->disp.exp.X_op != O_constant
1851 || TRUNC (opP->disp.exp.X_add_number) > 7)
1852 losing++;
1853 break;
1854
1855 case 'U':
1856 if (opP->mode != CONTROL || opP->reg != USP)
1857 losing++;
1858 break;
1859
1860 case 'x':
1861 if (opP->mode != IMMED)
1862 losing++;
1863 else if (opP->disp.exp.X_op != O_constant
1864 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1865 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
1866 losing++;
1867 break;
1868
1869 /* JF these are out of order. We could put them
1870 in order if we were willing to put up with
1871 bunches of #ifdef m68851s in the code.
1872
1873 Don't forget that you need these operands
1874 to use 68030 MMU instructions. */
1875 #ifndef NO_68851
1876 /* Memory addressing mode used by pflushr. */
1877 case '|':
1878 if (opP->mode == CONTROL
1879 || opP->mode == FPREG
1880 || opP->mode == DREG
1881 || opP->mode == AREG
1882 || opP->mode == REGLST)
1883 losing++;
1884 /* We should accept immediate operands, but they
1885 supposedly have to be quad word, and we don't
1886 handle that. I would like to see what a Motorola
1887 assembler does before doing something here. */
1888 if (opP->mode == IMMED)
1889 losing++;
1890 break;
1891
1892 case 'f':
1893 if (opP->mode != CONTROL
1894 || (opP->reg != SFC && opP->reg != DFC))
1895 losing++;
1896 break;
1897
1898 case '0':
1899 if (opP->mode != CONTROL || opP->reg != TC)
1900 losing++;
1901 break;
1902
1903 case '1':
1904 if (opP->mode != CONTROL || opP->reg != AC)
1905 losing++;
1906 break;
1907
1908 case '2':
1909 if (opP->mode != CONTROL
1910 || (opP->reg != CAL
1911 && opP->reg != VAL
1912 && opP->reg != SCC))
1913 losing++;
1914 break;
1915
1916 case 'V':
1917 if (opP->mode != CONTROL
1918 || opP->reg != VAL)
1919 losing++;
1920 break;
1921
1922 case 'W':
1923 if (opP->mode != CONTROL
1924 || (opP->reg != DRP
1925 && opP->reg != SRP
1926 && opP->reg != CRP))
1927 losing++;
1928 break;
1929
1930 case 'w':
1931 switch (opP->mode)
1932 {
1933 case IMMED:
1934 case ABSL:
1935 case AREG:
1936 case DREG:
1937 case FPREG:
1938 case CONTROL:
1939 case POST:
1940 case PRE:
1941 case REGLST:
1942 losing++;
1943 break;
1944 default:
1945 break;
1946 }
1947 break;
1948
1949 case 'X':
1950 if (opP->mode != CONTROL
1951 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1952 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1953 losing++;
1954 break;
1955
1956 case 'Y':
1957 if (opP->mode != CONTROL || opP->reg != PSR)
1958 losing++;
1959 break;
1960
1961 case 'Z':
1962 if (opP->mode != CONTROL || opP->reg != PCSR)
1963 losing++;
1964 break;
1965 #endif
1966 case 'c':
1967 if (opP->mode != CONTROL
1968 || (opP->reg != NC
1969 && opP->reg != IC
1970 && opP->reg != DC
1971 && opP->reg != BC))
1972 losing++;
1973 break;
1974
1975 case '_':
1976 if (opP->mode != ABSL)
1977 ++losing;
1978 break;
1979
1980 case 'u':
1981 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1982 losing++;
1983 /* FIXME: kludge instead of fixing parser:
1984 upper/lower registers are *not* CONTROL
1985 registers, but ordinary ones. */
1986 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1987 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1988 opP->mode = DREG;
1989 else
1990 opP->mode = AREG;
1991 break;
1992
1993 case 'y':
1994 if (!(opP->mode == AINDR
1995 || (opP->mode == DISP
1996 && !(opP->reg == PC || opP->reg == ZPC))))
1997 losing++;
1998 break;
1999
2000 case 'z':
2001 if (!(opP->mode == AINDR || opP->mode == DISP))
2002 losing++;
2003 break;
2004
2005 default:
2006 abort ();
2007 }
2008
2009 if (losing)
2010 break;
2011 }
2012
2013 /* Since we have found the correct instruction, copy
2014 in the modifications that we may have made. */
2015 if (!losing)
2016 for (i = 0; i < opsfound; i++)
2017 the_ins.operands[i] = operands_backup[i];
2018 }
2019
2020 if (!losing)
2021 break;
2022
2023 opcode = opcode->m_next;
2024
2025 if (!opcode)
2026 {
2027 if (ok_arch
2028 && !(ok_arch & current_architecture))
2029 {
2030 const struct m68k_cpu *cpu;
2031 int any = 0;
2032 size_t space = 400;
2033 char *buf = xmalloc (space + 1);
2034 size_t len;
2035 int paren = 1;
2036
2037 the_ins.error = buf;
2038 /* Make sure there's a NUL at the end of the buffer -- strncpy
2039 won't write one when it runs out of buffer */
2040 buf[space] = 0;
2041 #define APPEND(STRING) \
2042 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2043
2044 APPEND (_("invalid instruction for this architecture; needs "));
2045 switch (ok_arch)
2046 {
2047 case mcfisa_a:
2048 APPEND (_("ColdFire ISA_A"));
2049 break;
2050 case mcfhwdiv:
2051 APPEND (_("ColdFire hardware divide"));
2052 break;
2053 case mcfisa_aa:
2054 APPEND (_("ColdFire ISA_A+"));
2055 break;
2056 case mcfisa_b:
2057 APPEND (_("ColdFire ISA_B"));
2058 break;
2059 case cfloat:
2060 APPEND (_("ColdFire fpu"));
2061 break;
2062 case mfloat:
2063 APPEND (_("M68K fpu"));
2064 break;
2065 case mmmu:
2066 APPEND (_("M68K mmu"));
2067 break;
2068 case m68020up:
2069 APPEND (_("68020 or higher"));
2070 break;
2071 case m68000up:
2072 APPEND (_("68000 or higher"));
2073 break;
2074 case m68010up:
2075 APPEND (_("68010 or higher"));
2076 break;
2077 default:
2078 paren = 0;
2079 }
2080 if (paren)
2081 APPEND (" (");
2082
2083 for (cpu = m68k_cpus; cpu->name; cpu++)
2084 if (!cpu->alias && (cpu->arch & ok_arch))
2085 {
2086 const struct m68k_cpu *alias;
2087
2088 if (any)
2089 APPEND (", ");
2090 any = 0;
2091 APPEND (cpu->name);
2092 APPEND (" [");
2093 if (cpu != m68k_cpus)
2094 for (alias = cpu - 1; alias->alias; alias--)
2095 {
2096 if (any)
2097 APPEND (", ");
2098 APPEND (alias->name);
2099 any = 1;
2100 }
2101 for (alias = cpu + 1; alias->alias; alias++)
2102 {
2103 if (any)
2104 APPEND (", ");
2105 APPEND (alias->name);
2106 any = 1;
2107 }
2108
2109 APPEND ("]");
2110 any = 1;
2111 }
2112 if (paren)
2113 APPEND (")");
2114 #undef APPEND
2115 if (!space)
2116 {
2117 /* we ran out of space, so replace the end of the list
2118 with ellipsis. */
2119 buf -= 4;
2120 while (*buf != ' ')
2121 buf--;
2122 strcpy (buf, " ...");
2123 }
2124 }
2125 else
2126 the_ins.error = _("operands mismatch");
2127 return;
2128 }
2129
2130 losing = 0;
2131 }
2132
2133 /* Now assemble it. */
2134 the_ins.args = opcode->m_operands;
2135 the_ins.numargs = opcode->m_opnum;
2136 the_ins.numo = opcode->m_codenum;
2137 the_ins.opcode[0] = getone (opcode);
2138 the_ins.opcode[1] = gettwo (opcode);
2139
2140 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2141 {
2142 /* This switch is a doozy.
2143 Watch the first step; its a big one! */
2144 switch (s[0])
2145 {
2146
2147 case '*':
2148 case '~':
2149 case '%':
2150 case ';':
2151 case '@':
2152 case '!':
2153 case '&':
2154 case '$':
2155 case '?':
2156 case '/':
2157 case '<':
2158 case '>':
2159 case 'b':
2160 case 'm':
2161 case 'n':
2162 case 'o':
2163 case 'p':
2164 case 'q':
2165 case 'v':
2166 case 'w':
2167 case 'y':
2168 case 'z':
2169 case '4':
2170 #ifndef NO_68851
2171 case '|':
2172 #endif
2173 switch (opP->mode)
2174 {
2175 case IMMED:
2176 tmpreg = 0x3c; /* 7.4 */
2177 if (strchr ("bwl", s[1]))
2178 nextword = get_num (&opP->disp, 90);
2179 else
2180 nextword = get_num (&opP->disp, 0);
2181 if (isvar (&opP->disp))
2182 add_fix (s[1], &opP->disp, 0, 0);
2183 switch (s[1])
2184 {
2185 case 'b':
2186 if (!isbyte (nextword))
2187 opP->error = _("operand out of range");
2188 addword (nextword);
2189 baseo = 0;
2190 break;
2191 case 'w':
2192 if (!isword (nextword))
2193 opP->error = _("operand out of range");
2194 addword (nextword);
2195 baseo = 0;
2196 break;
2197 case 'W':
2198 if (!issword (nextword))
2199 opP->error = _("operand out of range");
2200 addword (nextword);
2201 baseo = 0;
2202 break;
2203 case 'l':
2204 addword (nextword >> 16);
2205 addword (nextword);
2206 baseo = 0;
2207 break;
2208
2209 case 'f':
2210 baseo = 2;
2211 outro = 8;
2212 break;
2213 case 'F':
2214 baseo = 4;
2215 outro = 11;
2216 break;
2217 case 'x':
2218 baseo = 6;
2219 outro = 15;
2220 break;
2221 case 'p':
2222 baseo = 6;
2223 outro = -1;
2224 break;
2225 default:
2226 abort ();
2227 }
2228 if (!baseo)
2229 break;
2230
2231 /* We gotta put out some float. */
2232 if (op (&opP->disp) != O_big)
2233 {
2234 valueT val;
2235 int gencnt;
2236
2237 /* Can other cases happen here? */
2238 if (op (&opP->disp) != O_constant)
2239 abort ();
2240
2241 val = (valueT) offs (&opP->disp);
2242 gencnt = 0;
2243 do
2244 {
2245 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2246 val >>= LITTLENUM_NUMBER_OF_BITS;
2247 ++gencnt;
2248 }
2249 while (val != 0);
2250 offs (&opP->disp) = gencnt;
2251 }
2252 if (offs (&opP->disp) > 0)
2253 {
2254 if (offs (&opP->disp) > baseo)
2255 {
2256 as_warn (_("Bignum too big for %c format; truncated"),
2257 s[1]);
2258 offs (&opP->disp) = baseo;
2259 }
2260 baseo -= offs (&opP->disp);
2261 while (baseo--)
2262 addword (0);
2263 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2264 offs (&opP->disp)--;
2265 --wordp)
2266 addword (*wordp);
2267 break;
2268 }
2269 gen_to_words (words, baseo, (long) outro);
2270 for (wordp = words; baseo--; wordp++)
2271 addword (*wordp);
2272 break;
2273 case DREG:
2274 tmpreg = opP->reg - DATA; /* 0.dreg */
2275 break;
2276 case AREG:
2277 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2278 break;
2279 case AINDR:
2280 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2281 break;
2282 case ADEC:
2283 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2284 break;
2285 case AINC:
2286 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2287 break;
2288 case DISP:
2289
2290 nextword = get_num (&opP->disp, 90);
2291
2292 /* Convert mode 5 addressing with a zero offset into
2293 mode 2 addressing to reduce the instruction size by a
2294 word. */
2295 if (! isvar (&opP->disp)
2296 && (nextword == 0)
2297 && (opP->disp.size == SIZE_UNSPEC)
2298 && (opP->reg >= ADDR0)
2299 && (opP->reg <= ADDR7))
2300 {
2301 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2302 break;
2303 }
2304
2305 if (opP->reg == PC
2306 && ! isvar (&opP->disp)
2307 && m68k_abspcadd)
2308 {
2309 opP->disp.exp.X_op = O_symbol;
2310 opP->disp.exp.X_add_symbol =
2311 section_symbol (absolute_section);
2312 }
2313
2314 /* Force into index mode. Hope this works. */
2315
2316 /* We do the first bit for 32-bit displacements, and the
2317 second bit for 16 bit ones. It is possible that we
2318 should make the default be WORD instead of LONG, but
2319 I think that'd break GCC, so we put up with a little
2320 inefficiency for the sake of working output. */
2321
2322 if (!issword (nextword)
2323 || (isvar (&opP->disp)
2324 && ((opP->disp.size == SIZE_UNSPEC
2325 && flag_short_refs == 0
2326 && cpu_of_arch (current_architecture) >= m68020
2327 && ! arch_coldfire_p (current_architecture))
2328 || opP->disp.size == SIZE_LONG)))
2329 {
2330 if (cpu_of_arch (current_architecture) < m68020
2331 || arch_coldfire_p (current_architecture))
2332 opP->error =
2333 _("displacement too large for this architecture; needs 68020 or higher");
2334 if (opP->reg == PC)
2335 tmpreg = 0x3B; /* 7.3 */
2336 else
2337 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2338 if (isvar (&opP->disp))
2339 {
2340 if (opP->reg == PC)
2341 {
2342 if (opP->disp.size == SIZE_LONG
2343 #ifdef OBJ_ELF
2344 /* If the displacement needs pic
2345 relocation it cannot be relaxed. */
2346 || opP->disp.pic_reloc != pic_none
2347 #endif
2348 )
2349 {
2350 addword (0x0170);
2351 add_fix ('l', &opP->disp, 1, 2);
2352 }
2353 else
2354 {
2355 add_frag (adds (&opP->disp),
2356 SEXT (offs (&opP->disp)),
2357 TAB (PCREL1632, SZ_UNDEF));
2358 break;
2359 }
2360 }
2361 else
2362 {
2363 addword (0x0170);
2364 add_fix ('l', &opP->disp, 0, 0);
2365 }
2366 }
2367 else
2368 addword (0x0170);
2369 addword (nextword >> 16);
2370 }
2371 else
2372 {
2373 if (opP->reg == PC)
2374 tmpreg = 0x3A; /* 7.2 */
2375 else
2376 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2377
2378 if (isvar (&opP->disp))
2379 {
2380 if (opP->reg == PC)
2381 {
2382 add_fix ('w', &opP->disp, 1, 0);
2383 }
2384 else
2385 add_fix ('w', &opP->disp, 0, 0);
2386 }
2387 }
2388 addword (nextword);
2389 break;
2390
2391 case POST:
2392 case PRE:
2393 case BASE:
2394 nextword = 0;
2395 baseo = get_num (&opP->disp, 90);
2396 if (opP->mode == POST || opP->mode == PRE)
2397 outro = get_num (&opP->odisp, 90);
2398 /* Figure out the `addressing mode'.
2399 Also turn on the BASE_DISABLE bit, if needed. */
2400 if (opP->reg == PC || opP->reg == ZPC)
2401 {
2402 tmpreg = 0x3b; /* 7.3 */
2403 if (opP->reg == ZPC)
2404 nextword |= 0x80;
2405 }
2406 else if (opP->reg == 0)
2407 {
2408 nextword |= 0x80;
2409 tmpreg = 0x30; /* 6.garbage */
2410 }
2411 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2412 {
2413 nextword |= 0x80;
2414 tmpreg = 0x30 + opP->reg - ZADDR0;
2415 }
2416 else
2417 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2418
2419 siz1 = opP->disp.size;
2420 if (opP->mode == POST || opP->mode == PRE)
2421 siz2 = opP->odisp.size;
2422 else
2423 siz2 = SIZE_UNSPEC;
2424
2425 /* Index register stuff. */
2426 if (opP->index.reg != 0
2427 && opP->index.reg >= DATA
2428 && opP->index.reg <= ADDR7)
2429 {
2430 nextword |= (opP->index.reg - DATA) << 12;
2431
2432 if (opP->index.size == SIZE_LONG
2433 || (opP->index.size == SIZE_UNSPEC
2434 && m68k_index_width_default == SIZE_LONG))
2435 nextword |= 0x800;
2436
2437 if ((opP->index.scale != 1
2438 && cpu_of_arch (current_architecture) < m68020)
2439 || (opP->index.scale == 8
2440 && (arch_coldfire_p (current_architecture)
2441 && !arch_coldfire_fpu (current_architecture))))
2442 {
2443 opP->error =
2444 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2445 }
2446
2447 if (arch_coldfire_p (current_architecture)
2448 && opP->index.size == SIZE_WORD)
2449 opP->error = _("invalid index size for coldfire");
2450
2451 switch (opP->index.scale)
2452 {
2453 case 1:
2454 break;
2455 case 2:
2456 nextword |= 0x200;
2457 break;
2458 case 4:
2459 nextword |= 0x400;
2460 break;
2461 case 8:
2462 nextword |= 0x600;
2463 break;
2464 default:
2465 abort ();
2466 }
2467 /* IF its simple,
2468 GET US OUT OF HERE! */
2469
2470 /* Must be INDEX, with an index register. Address
2471 register cannot be ZERO-PC, and either :b was
2472 forced, or we know it will fit. For a 68000 or
2473 68010, force this mode anyways, because the
2474 larger modes aren't supported. */
2475 if (opP->mode == BASE
2476 && ((opP->reg >= ADDR0
2477 && opP->reg <= ADDR7)
2478 || opP->reg == PC))
2479 {
2480 if (siz1 == SIZE_BYTE
2481 || cpu_of_arch (current_architecture) < m68020
2482 || arch_coldfire_p (current_architecture)
2483 || (siz1 == SIZE_UNSPEC
2484 && ! isvar (&opP->disp)
2485 && issbyte (baseo)))
2486 {
2487 nextword += baseo & 0xff;
2488 addword (nextword);
2489 if (isvar (&opP->disp))
2490 {
2491 /* Do a byte relocation. If it doesn't
2492 fit (possible on m68000) let the
2493 fixup processing complain later. */
2494 if (opP->reg == PC)
2495 add_fix ('B', &opP->disp, 1, 1);
2496 else
2497 add_fix ('B', &opP->disp, 0, 0);
2498 }
2499 else if (siz1 != SIZE_BYTE)
2500 {
2501 if (siz1 != SIZE_UNSPEC)
2502 as_warn (_("Forcing byte displacement"));
2503 if (! issbyte (baseo))
2504 opP->error = _("byte displacement out of range");
2505 }
2506
2507 break;
2508 }
2509 else if (siz1 == SIZE_UNSPEC
2510 && opP->reg == PC
2511 && isvar (&opP->disp)
2512 && subs (&opP->disp) == NULL
2513 #ifdef OBJ_ELF
2514 /* If the displacement needs pic
2515 relocation it cannot be relaxed. */
2516 && opP->disp.pic_reloc == pic_none
2517 #endif
2518 )
2519 {
2520 /* The code in md_convert_frag_1 needs to be
2521 able to adjust nextword. Call frag_grow
2522 to ensure that we have enough space in
2523 the frag obstack to make all the bytes
2524 contiguous. */
2525 frag_grow (14);
2526 nextword += baseo & 0xff;
2527 addword (nextword);
2528 add_frag (adds (&opP->disp),
2529 SEXT (offs (&opP->disp)),
2530 TAB (PCINDEX, SZ_UNDEF));
2531
2532 break;
2533 }
2534 }
2535 }
2536 else
2537 {
2538 nextword |= 0x40; /* No index reg. */
2539 if (opP->index.reg >= ZDATA0
2540 && opP->index.reg <= ZDATA7)
2541 nextword |= (opP->index.reg - ZDATA0) << 12;
2542 else if (opP->index.reg >= ZADDR0
2543 || opP->index.reg <= ZADDR7)
2544 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2545 }
2546
2547 /* It isn't simple. */
2548
2549 if (cpu_of_arch (current_architecture) < m68020
2550 || arch_coldfire_p (current_architecture))
2551 opP->error =
2552 _("invalid operand mode for this architecture; needs 68020 or higher");
2553
2554 nextword |= 0x100;
2555 /* If the guy specified a width, we assume that it is
2556 wide enough. Maybe it isn't. If so, we lose. */
2557 switch (siz1)
2558 {
2559 case SIZE_UNSPEC:
2560 if (isvar (&opP->disp)
2561 ? m68k_rel32
2562 : ! issword (baseo))
2563 {
2564 siz1 = SIZE_LONG;
2565 nextword |= 0x30;
2566 }
2567 else if (! isvar (&opP->disp) && baseo == 0)
2568 nextword |= 0x10;
2569 else
2570 {
2571 nextword |= 0x20;
2572 siz1 = SIZE_WORD;
2573 }
2574 break;
2575 case SIZE_BYTE:
2576 as_warn (_(":b not permitted; defaulting to :w"));
2577 /* Fall through. */
2578 case SIZE_WORD:
2579 nextword |= 0x20;
2580 break;
2581 case SIZE_LONG:
2582 nextword |= 0x30;
2583 break;
2584 }
2585
2586 /* Figure out inner displacement stuff. */
2587 if (opP->mode == POST || opP->mode == PRE)
2588 {
2589 if (cpu_of_arch (current_architecture) & cpu32)
2590 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2591 switch (siz2)
2592 {
2593 case SIZE_UNSPEC:
2594 if (isvar (&opP->odisp)
2595 ? m68k_rel32
2596 : ! issword (outro))
2597 {
2598 siz2 = SIZE_LONG;
2599 nextword |= 0x3;
2600 }
2601 else if (! isvar (&opP->odisp) && outro == 0)
2602 nextword |= 0x1;
2603 else
2604 {
2605 nextword |= 0x2;
2606 siz2 = SIZE_WORD;
2607 }
2608 break;
2609 case 1:
2610 as_warn (_(":b not permitted; defaulting to :w"));
2611 /* Fall through. */
2612 case 2:
2613 nextword |= 0x2;
2614 break;
2615 case 3:
2616 nextword |= 0x3;
2617 break;
2618 }
2619 if (opP->mode == POST
2620 && (nextword & 0x40) == 0)
2621 nextword |= 0x04;
2622 }
2623 addword (nextword);
2624
2625 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2626 {
2627 if (opP->reg == PC || opP->reg == ZPC)
2628 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2629 else
2630 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2631 }
2632 if (siz1 == SIZE_LONG)
2633 addword (baseo >> 16);
2634 if (siz1 != SIZE_UNSPEC)
2635 addword (baseo);
2636
2637 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2638 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2639 if (siz2 == SIZE_LONG)
2640 addword (outro >> 16);
2641 if (siz2 != SIZE_UNSPEC)
2642 addword (outro);
2643
2644 break;
2645
2646 case ABSL:
2647 nextword = get_num (&opP->disp, 90);
2648 switch (opP->disp.size)
2649 {
2650 default:
2651 abort ();
2652 case SIZE_UNSPEC:
2653 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2654 {
2655 tmpreg = 0x38; /* 7.0 */
2656 addword (nextword);
2657 break;
2658 }
2659 if (isvar (&opP->disp)
2660 && !subs (&opP->disp)
2661 && adds (&opP->disp)
2662 #ifdef OBJ_ELF
2663 /* If the displacement needs pic relocation it
2664 cannot be relaxed. */
2665 && opP->disp.pic_reloc == pic_none
2666 #endif
2667 && !flag_long_jumps
2668 && !strchr ("~%&$?", s[0]))
2669 {
2670 tmpreg = 0x3A; /* 7.2 */
2671 add_frag (adds (&opP->disp),
2672 SEXT (offs (&opP->disp)),
2673 TAB (ABSTOPCREL, SZ_UNDEF));
2674 break;
2675 }
2676 /* Fall through into long. */
2677 case SIZE_LONG:
2678 if (isvar (&opP->disp))
2679 add_fix ('l', &opP->disp, 0, 0);
2680
2681 tmpreg = 0x39;/* 7.1 mode */
2682 addword (nextword >> 16);
2683 addword (nextword);
2684 break;
2685
2686 case SIZE_BYTE:
2687 as_bad (_("unsupported byte value; use a different suffix"));
2688 /* Fall through. */
2689
2690 case SIZE_WORD:
2691 if (isvar (&opP->disp))
2692 add_fix ('w', &opP->disp, 0, 0);
2693
2694 tmpreg = 0x38;/* 7.0 mode */
2695 addword (nextword);
2696 break;
2697 }
2698 break;
2699 case CONTROL:
2700 case FPREG:
2701 default:
2702 as_bad (_("unknown/incorrect operand"));
2703 /* abort (); */
2704 }
2705
2706 /* If s[0] is '4', then this is for the mac instructions
2707 that can have a trailing_ampersand set. If so, set 0x100
2708 bit on tmpreg so install_gen_operand can check for it and
2709 set the appropriate bit (word2, bit 5). */
2710 if (s[0] == '4')
2711 {
2712 if (opP->trailing_ampersand)
2713 tmpreg |= 0x100;
2714 }
2715 install_gen_operand (s[1], tmpreg);
2716 break;
2717
2718 case '#':
2719 case '^':
2720 switch (s[1])
2721 { /* JF: I hate floating point! */
2722 case 'j':
2723 tmpreg = 70;
2724 break;
2725 case '8':
2726 tmpreg = 20;
2727 break;
2728 case 'C':
2729 tmpreg = 50;
2730 break;
2731 case '3':
2732 default:
2733 tmpreg = 90;
2734 break;
2735 }
2736 tmpreg = get_num (&opP->disp, tmpreg);
2737 if (isvar (&opP->disp))
2738 add_fix (s[1], &opP->disp, 0, 0);
2739 switch (s[1])
2740 {
2741 case 'b': /* Danger: These do no check for
2742 certain types of overflow.
2743 user beware! */
2744 if (!isbyte (tmpreg))
2745 opP->error = _("out of range");
2746 insop (tmpreg, opcode);
2747 if (isvar (&opP->disp))
2748 the_ins.reloc[the_ins.nrel - 1].n =
2749 (opcode->m_codenum) * 2 + 1;
2750 break;
2751 case 'B':
2752 if (!issbyte (tmpreg))
2753 opP->error = _("out of range");
2754 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2755 if (isvar (&opP->disp))
2756 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2757 break;
2758 case 'w':
2759 if (!isword (tmpreg))
2760 opP->error = _("out of range");
2761 insop (tmpreg, opcode);
2762 if (isvar (&opP->disp))
2763 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2764 break;
2765 case 'W':
2766 if (!issword (tmpreg))
2767 opP->error = _("out of range");
2768 insop (tmpreg, opcode);
2769 if (isvar (&opP->disp))
2770 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2771 break;
2772 case 'l':
2773 /* Because of the way insop works, we put these two out
2774 backwards. */
2775 insop (tmpreg, opcode);
2776 insop (tmpreg >> 16, opcode);
2777 if (isvar (&opP->disp))
2778 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2779 break;
2780 case '3':
2781 tmpreg &= 0xFF;
2782 case '8':
2783 case 'C':
2784 case 'j':
2785 install_operand (s[1], tmpreg);
2786 break;
2787 default:
2788 abort ();
2789 }
2790 break;
2791
2792 case '+':
2793 case '-':
2794 case 'A':
2795 case 'a':
2796 install_operand (s[1], opP->reg - ADDR);
2797 break;
2798
2799 case 'B':
2800 tmpreg = get_num (&opP->disp, 90);
2801 switch (s[1])
2802 {
2803 case 'B':
2804 add_fix ('B', &opP->disp, 1, -1);
2805 break;
2806 case 'W':
2807 add_fix ('w', &opP->disp, 1, 0);
2808 addword (0);
2809 break;
2810 case 'L':
2811 long_branch:
2812 if (! HAVE_LONG_BRANCH (current_architecture))
2813 as_warn (_("Can't use long branches on 68000/68010/5200"));
2814 the_ins.opcode[0] |= 0xff;
2815 add_fix ('l', &opP->disp, 1, 0);
2816 addword (0);
2817 addword (0);
2818 break;
2819 case 'g':
2820 if (subs (&opP->disp)) /* We can't relax it. */
2821 goto long_branch;
2822
2823 #ifdef OBJ_ELF
2824 /* If the displacement needs pic relocation it cannot be
2825 relaxed. */
2826 if (opP->disp.pic_reloc != pic_none)
2827 goto long_branch;
2828 #endif
2829 /* This could either be a symbol, or an absolute
2830 address. If it's an absolute address, turn it into
2831 an absolute jump right here and keep it out of the
2832 relaxer. */
2833 if (adds (&opP->disp) == 0)
2834 {
2835 if (the_ins.opcode[0] == 0x6000) /* jbra */
2836 the_ins.opcode[0] = 0x4EF9;
2837 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2838 the_ins.opcode[0] = 0x4EB9;
2839 else /* jCC */
2840 {
2841 the_ins.opcode[0] ^= 0x0100;
2842 the_ins.opcode[0] |= 0x0006;
2843 addword (0x4EF9);
2844 }
2845 add_fix ('l', &opP->disp, 0, 0);
2846 addword (0);
2847 addword (0);
2848 break;
2849 }
2850
2851 /* Now we know it's going into the relaxer. Now figure
2852 out which mode. We try in this order of preference:
2853 long branch, absolute jump, byte/word branches only. */
2854 if (HAVE_LONG_BRANCH (current_architecture))
2855 add_frag (adds (&opP->disp),
2856 SEXT (offs (&opP->disp)),
2857 TAB (BRANCHBWL, SZ_UNDEF));
2858 else if (! flag_keep_pcrel)
2859 {
2860 if ((the_ins.opcode[0] == 0x6000)
2861 || (the_ins.opcode[0] == 0x6100))
2862 add_frag (adds (&opP->disp),
2863 SEXT (offs (&opP->disp)),
2864 TAB (BRABSJUNC, SZ_UNDEF));
2865 else
2866 add_frag (adds (&opP->disp),
2867 SEXT (offs (&opP->disp)),
2868 TAB (BRABSJCOND, SZ_UNDEF));
2869 }
2870 else
2871 add_frag (adds (&opP->disp),
2872 SEXT (offs (&opP->disp)),
2873 TAB (BRANCHBW, SZ_UNDEF));
2874 break;
2875 case 'w':
2876 if (isvar (&opP->disp))
2877 {
2878 /* Check for DBcc instructions. We can relax them,
2879 but only if we have long branches and/or absolute
2880 jumps. */
2881 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2882 && (HAVE_LONG_BRANCH (current_architecture)
2883 || (! flag_keep_pcrel)))
2884 {
2885 if (HAVE_LONG_BRANCH (current_architecture))
2886 add_frag (adds (&opP->disp),
2887 SEXT (offs (&opP->disp)),
2888 TAB (DBCCLBR, SZ_UNDEF));
2889 else
2890 add_frag (adds (&opP->disp),
2891 SEXT (offs (&opP->disp)),
2892 TAB (DBCCABSJ, SZ_UNDEF));
2893 break;
2894 }
2895 add_fix ('w', &opP->disp, 1, 0);
2896 }
2897 addword (0);
2898 break;
2899 case 'C': /* Fixed size LONG coproc branches. */
2900 add_fix ('l', &opP->disp, 1, 0);
2901 addword (0);
2902 addword (0);
2903 break;
2904 case 'c': /* Var size Coprocesssor branches. */
2905 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
2906 {
2907 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2908 add_fix ('l', &opP->disp, 1, 0);
2909 addword (0);
2910 addword (0);
2911 }
2912 else
2913 add_frag (adds (&opP->disp),
2914 SEXT (offs (&opP->disp)),
2915 TAB (FBRANCH, SZ_UNDEF));
2916 break;
2917 default:
2918 abort ();
2919 }
2920 break;
2921
2922 case 'C': /* Ignore it. */
2923 break;
2924
2925 case 'd': /* JF this is a kludge. */
2926 install_operand ('s', opP->reg - ADDR);
2927 tmpreg = get_num (&opP->disp, 90);
2928 if (!issword (tmpreg))
2929 {
2930 as_warn (_("Expression out of range, using 0"));
2931 tmpreg = 0;
2932 }
2933 addword (tmpreg);
2934 break;
2935
2936 case 'D':
2937 install_operand (s[1], opP->reg - DATA);
2938 break;
2939
2940 case 'e': /* EMAC ACCx, reg/reg. */
2941 install_operand (s[1], opP->reg - ACC);
2942 break;
2943
2944 case 'E': /* Ignore it. */
2945 break;
2946
2947 case 'F':
2948 install_operand (s[1], opP->reg - FP0);
2949 break;
2950
2951 case 'g': /* EMAC ACCEXTx. */
2952 install_operand (s[1], opP->reg - ACCEXT01);
2953 break;
2954
2955 case 'G': /* Ignore it. */
2956 case 'H':
2957 break;
2958
2959 case 'I':
2960 tmpreg = opP->reg - COP0;
2961 install_operand (s[1], tmpreg);
2962 break;
2963
2964 case 'i': /* MAC/EMAC scale factor. */
2965 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
2966 break;
2967
2968 case 'J': /* JF foo. */
2969 switch (opP->reg)
2970 {
2971 case SFC:
2972 tmpreg = 0x000;
2973 break;
2974 case DFC:
2975 tmpreg = 0x001;
2976 break;
2977 case CACR:
2978 tmpreg = 0x002;
2979 break;
2980 case TC:
2981 tmpreg = 0x003;
2982 break;
2983 case ACR0:
2984 case ITT0:
2985 tmpreg = 0x004;
2986 break;
2987 case ACR1:
2988 case ITT1:
2989 tmpreg = 0x005;
2990 break;
2991 case ACR2:
2992 case DTT0:
2993 tmpreg = 0x006;
2994 break;
2995 case ACR3:
2996 case DTT1:
2997 tmpreg = 0x007;
2998 break;
2999 case BUSCR:
3000 tmpreg = 0x008;
3001 break;
3002
3003 case USP:
3004 tmpreg = 0x800;
3005 break;
3006 case VBR:
3007 tmpreg = 0x801;
3008 break;
3009 case CAAR:
3010 tmpreg = 0x802;
3011 break;
3012 case MSP:
3013 tmpreg = 0x803;
3014 break;
3015 case ISP:
3016 tmpreg = 0x804;
3017 break;
3018 case MMUSR:
3019 tmpreg = 0x805;
3020 break;
3021 case URP:
3022 tmpreg = 0x806;
3023 break;
3024 case SRP:
3025 tmpreg = 0x807;
3026 break;
3027 case PCR:
3028 tmpreg = 0x808;
3029 break;
3030 case ROMBAR:
3031 tmpreg = 0xC00;
3032 break;
3033 case ROMBAR1:
3034 tmpreg = 0xC01;
3035 break;
3036 case FLASHBAR:
3037 case RAMBAR0:
3038 tmpreg = 0xC04;
3039 break;
3040 case RAMBAR:
3041 case RAMBAR1:
3042 tmpreg = 0xC05;
3043 break;
3044 case MPCR:
3045 tmpreg = 0xC0C;
3046 break;
3047 case EDRAMBAR:
3048 tmpreg = 0xC0D;
3049 break;
3050 case MBAR0:
3051 case MBAR2:
3052 case SECMBAR:
3053 tmpreg = 0xC0E;
3054 break;
3055 case MBAR1:
3056 case MBAR:
3057 tmpreg = 0xC0F;
3058 break;
3059 case PCR1U0:
3060 tmpreg = 0xD02;
3061 break;
3062 case PCR1L0:
3063 tmpreg = 0xD03;
3064 break;
3065 case PCR2U0:
3066 tmpreg = 0xD04;
3067 break;
3068 case PCR2L0:
3069 tmpreg = 0xD05;
3070 break;
3071 case PCR3U0:
3072 tmpreg = 0xD06;
3073 break;
3074 case PCR3L0:
3075 tmpreg = 0xD07;
3076 break;
3077 case PCR1L1:
3078 tmpreg = 0xD0A;
3079 break;
3080 case PCR1U1:
3081 tmpreg = 0xD0B;
3082 break;
3083 case PCR2L1:
3084 tmpreg = 0xD0C;
3085 break;
3086 case PCR2U1:
3087 tmpreg = 0xD0D;
3088 break;
3089 case PCR3L1:
3090 tmpreg = 0xD0E;
3091 break;
3092 case PCR3U1:
3093 tmpreg = 0xD0F;
3094 break;
3095 default:
3096 abort ();
3097 }
3098 install_operand (s[1], tmpreg);
3099 break;
3100
3101 case 'k':
3102 tmpreg = get_num (&opP->disp, 55);
3103 install_operand (s[1], tmpreg & 0x7f);
3104 break;
3105
3106 case 'l':
3107 tmpreg = opP->mask;
3108 if (s[1] == 'w')
3109 {
3110 if (tmpreg & 0x7FF0000)
3111 as_bad (_("Floating point register in register list"));
3112 insop (reverse_16_bits (tmpreg), opcode);
3113 }
3114 else
3115 {
3116 if (tmpreg & 0x700FFFF)
3117 as_bad (_("Wrong register in floating-point reglist"));
3118 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3119 }
3120 break;
3121
3122 case 'L':
3123 tmpreg = opP->mask;
3124 if (s[1] == 'w')
3125 {
3126 if (tmpreg & 0x7FF0000)
3127 as_bad (_("Floating point register in register list"));
3128 insop (tmpreg, opcode);
3129 }
3130 else if (s[1] == '8')
3131 {
3132 if (tmpreg & 0x0FFFFFF)
3133 as_bad (_("incorrect register in reglist"));
3134 install_operand (s[1], tmpreg >> 24);
3135 }
3136 else
3137 {
3138 if (tmpreg & 0x700FFFF)
3139 as_bad (_("wrong register in floating-point reglist"));
3140 else
3141 install_operand (s[1], tmpreg >> 16);
3142 }
3143 break;
3144
3145 case 'M':
3146 install_operand (s[1], get_num (&opP->disp, 60));
3147 break;
3148
3149 case 'O':
3150 tmpreg = ((opP->mode == DREG)
3151 ? 0x20 + (int) (opP->reg - DATA)
3152 : (get_num (&opP->disp, 40) & 0x1F));
3153 install_operand (s[1], tmpreg);
3154 break;
3155
3156 case 'Q':
3157 tmpreg = get_num (&opP->disp, 10);
3158 if (tmpreg == 8)
3159 tmpreg = 0;
3160 install_operand (s[1], tmpreg);
3161 break;
3162
3163 case 'R':
3164 /* This depends on the fact that ADDR registers are eight
3165 more than their corresponding DATA regs, so the result
3166 will have the ADDR_REG bit set. */
3167 install_operand (s[1], opP->reg - DATA);
3168 break;
3169
3170 case 'r':
3171 if (opP->mode == AINDR)
3172 install_operand (s[1], opP->reg - DATA);
3173 else
3174 install_operand (s[1], opP->index.reg - DATA);
3175 break;
3176
3177 case 's':
3178 if (opP->reg == FPI)
3179 tmpreg = 0x1;
3180 else if (opP->reg == FPS)
3181 tmpreg = 0x2;
3182 else if (opP->reg == FPC)
3183 tmpreg = 0x4;
3184 else
3185 abort ();
3186 install_operand (s[1], tmpreg);
3187 break;
3188
3189 case 'S': /* Ignore it. */
3190 break;
3191
3192 case 'T':
3193 install_operand (s[1], get_num (&opP->disp, 30));
3194 break;
3195
3196 case 'U': /* Ignore it. */
3197 break;
3198
3199 case 'c':
3200 switch (opP->reg)
3201 {
3202 case NC:
3203 tmpreg = 0;
3204 break;
3205 case DC:
3206 tmpreg = 1;
3207 break;
3208 case IC:
3209 tmpreg = 2;
3210 break;
3211 case BC:
3212 tmpreg = 3;
3213 break;
3214 default:
3215 as_fatal (_("failed sanity check"));
3216 } /* switch on cache token. */
3217 install_operand (s[1], tmpreg);
3218 break;
3219 #ifndef NO_68851
3220 /* JF: These are out of order, I fear. */
3221 case 'f':
3222 switch (opP->reg)
3223 {
3224 case SFC:
3225 tmpreg = 0;
3226 break;
3227 case DFC:
3228 tmpreg = 1;
3229 break;
3230 default:
3231 abort ();
3232 }
3233 install_operand (s[1], tmpreg);
3234 break;
3235
3236 case '0':
3237 case '1':
3238 case '2':
3239 switch (opP->reg)
3240 {
3241 case TC:
3242 tmpreg = 0;
3243 break;
3244 case CAL:
3245 tmpreg = 4;
3246 break;
3247 case VAL:
3248 tmpreg = 5;
3249 break;
3250 case SCC:
3251 tmpreg = 6;
3252 break;
3253 case AC:
3254 tmpreg = 7;
3255 break;
3256 default:
3257 abort ();
3258 }
3259 install_operand (s[1], tmpreg);
3260 break;
3261
3262 case 'V':
3263 if (opP->reg == VAL)
3264 break;
3265 abort ();
3266
3267 case 'W':
3268 switch (opP->reg)
3269 {
3270 case DRP:
3271 tmpreg = 1;
3272 break;
3273 case SRP:
3274 tmpreg = 2;
3275 break;
3276 case CRP:
3277 tmpreg = 3;
3278 break;
3279 default:
3280 abort ();
3281 }
3282 install_operand (s[1], tmpreg);
3283 break;
3284
3285 case 'X':
3286 switch (opP->reg)
3287 {
3288 case BAD:
3289 case BAD + 1:
3290 case BAD + 2:
3291 case BAD + 3:
3292 case BAD + 4:
3293 case BAD + 5:
3294 case BAD + 6:
3295 case BAD + 7:
3296 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3297 break;
3298
3299 case BAC:
3300 case BAC + 1:
3301 case BAC + 2:
3302 case BAC + 3:
3303 case BAC + 4:
3304 case BAC + 5:
3305 case BAC + 6:
3306 case BAC + 7:
3307 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3308 break;
3309
3310 default:
3311 abort ();
3312 }
3313 install_operand (s[1], tmpreg);
3314 break;
3315 case 'Y':
3316 know (opP->reg == PSR);
3317 break;
3318 case 'Z':
3319 know (opP->reg == PCSR);
3320 break;
3321 #endif /* m68851 */
3322 case '3':
3323 switch (opP->reg)
3324 {
3325 case TT0:
3326 tmpreg = 2;
3327 break;
3328 case TT1:
3329 tmpreg = 3;
3330 break;
3331 default:
3332 abort ();
3333 }
3334 install_operand (s[1], tmpreg);
3335 break;
3336 case 't':
3337 tmpreg = get_num (&opP->disp, 20);
3338 install_operand (s[1], tmpreg);
3339 break;
3340 case '_': /* used only for move16 absolute 32-bit address. */
3341 if (isvar (&opP->disp))
3342 add_fix ('l', &opP->disp, 0, 0);
3343 tmpreg = get_num (&opP->disp, 90);
3344 addword (tmpreg >> 16);
3345 addword (tmpreg & 0xFFFF);
3346 break;
3347 case 'u':
3348 install_operand (s[1], opP->reg - DATA0L);
3349 opP->reg -= (DATA0L);
3350 opP->reg &= 0x0F; /* remove upper/lower bit. */
3351 break;
3352 case 'x':
3353 tmpreg = get_num (&opP->disp, 80);
3354 if (tmpreg == -1)
3355 tmpreg = 0;
3356 install_operand (s[1], tmpreg);
3357 break;
3358 default:
3359 abort ();
3360 }
3361 }
3362
3363 /* By the time whe get here (FINALLY) the_ins contains the complete
3364 instruction, ready to be emitted. . . */
3365 }
3366
3367 static int
3368 reverse_16_bits (int in)
3369 {
3370 int out = 0;
3371 int n;
3372
3373 static int mask[16] =
3374 {
3375 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3376 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3377 };
3378 for (n = 0; n < 16; n++)
3379 {
3380 if (in & mask[n])
3381 out |= mask[15 - n];
3382 }
3383 return out;
3384 } /* reverse_16_bits() */
3385
3386 static int
3387 reverse_8_bits (int in)
3388 {
3389 int out = 0;
3390 int n;
3391
3392 static int mask[8] =
3393 {
3394 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3395 };
3396
3397 for (n = 0; n < 8; n++)
3398 {
3399 if (in & mask[n])
3400 out |= mask[7 - n];
3401 }
3402 return out;
3403 } /* reverse_8_bits() */
3404
3405 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3406 (that value is chosen in the frag_var call in md_assemble). TYPE
3407 is the subtype of the frag to be generated; its primary type is
3408 rs_machine_dependent.
3409
3410 The TYPE parameter is also used by md_convert_frag_1 and
3411 md_estimate_size_before_relax. The appropriate type of fixup will
3412 be emitted by md_convert_frag_1.
3413
3414 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3415 static void
3416 install_operand (int mode, int val)
3417 {
3418 switch (mode)
3419 {
3420 case 's':
3421 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3422 break;
3423 case 'd':
3424 the_ins.opcode[0] |= val << 9;
3425 break;
3426 case '1':
3427 the_ins.opcode[1] |= val << 12;
3428 break;
3429 case '2':
3430 the_ins.opcode[1] |= val << 6;
3431 break;
3432 case '3':
3433 the_ins.opcode[1] |= val;
3434 break;
3435 case '4':
3436 the_ins.opcode[2] |= val << 12;
3437 break;
3438 case '5':
3439 the_ins.opcode[2] |= val << 6;
3440 break;
3441 case '6':
3442 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3443 three words long! */
3444 the_ins.numo++;
3445 the_ins.opcode[2] |= val;
3446 break;
3447 case '7':
3448 the_ins.opcode[1] |= val << 7;
3449 break;
3450 case '8':
3451 the_ins.opcode[1] |= val << 10;
3452 break;
3453 #ifndef NO_68851
3454 case '9':
3455 the_ins.opcode[1] |= val << 5;
3456 break;
3457 #endif
3458
3459 case 't':
3460 the_ins.opcode[1] |= (val << 10) | (val << 7);
3461 break;
3462 case 'D':
3463 the_ins.opcode[1] |= (val << 12) | val;
3464 break;
3465 case 'g':
3466 the_ins.opcode[0] |= val = 0xff;
3467 break;
3468 case 'i':
3469 the_ins.opcode[0] |= val << 9;
3470 break;
3471 case 'C':
3472 the_ins.opcode[1] |= val;
3473 break;
3474 case 'j':
3475 the_ins.opcode[1] |= val;
3476 the_ins.numo++; /* What a hack. */
3477 break;
3478 case 'k':
3479 the_ins.opcode[1] |= val << 4;
3480 break;
3481 case 'b':
3482 case 'w':
3483 case 'W':
3484 case 'l':
3485 break;
3486 case 'e':
3487 the_ins.opcode[0] |= (val << 6);
3488 break;
3489 case 'L':
3490 the_ins.opcode[1] = (val >> 16);
3491 the_ins.opcode[2] = val & 0xffff;
3492 break;
3493 case 'm':
3494 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3495 the_ins.opcode[0] |= ((val & 0x7) << 9);
3496 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3497 break;
3498 case 'n': /* MAC/EMAC Rx on !load. */
3499 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3500 the_ins.opcode[0] |= ((val & 0x7) << 9);
3501 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3502 break;
3503 case 'o': /* MAC/EMAC Rx on load. */
3504 the_ins.opcode[1] |= val << 12;
3505 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3506 break;
3507 case 'M': /* MAC/EMAC Ry on !load. */
3508 the_ins.opcode[0] |= (val & 0xF);
3509 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3510 break;
3511 case 'N': /* MAC/EMAC Ry on load. */
3512 the_ins.opcode[1] |= (val & 0xF);
3513 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3514 break;
3515 case 'h':
3516 the_ins.opcode[1] |= ((val != 1) << 10);
3517 break;
3518 case 'F':
3519 the_ins.opcode[0] |= ((val & 0x3) << 9);
3520 break;
3521 case 'f':
3522 the_ins.opcode[0] |= ((val & 0x3) << 0);
3523 break;
3524 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3525 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3526 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3527 break;
3528 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3529 the_ins.opcode[0] |= ((val & 0x1) << 7);
3530 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3531 break;
3532 case 'I':
3533 the_ins.opcode[1] |= ((val & 0x3) << 9);
3534 break;
3535 case ']':
3536 the_ins.opcode[0] |= (val & 0x1) <<10;
3537 break;
3538 case 'c':
3539 default:
3540 as_fatal (_("failed sanity check."));
3541 }
3542 }
3543
3544 static void
3545 install_gen_operand (int mode, int val)
3546 {
3547 switch (mode)
3548 {
3549 case '/': /* Special for mask loads for mac/msac insns with
3550 possible mask; trailing_ampersend set in bit 8. */
3551 the_ins.opcode[0] |= (val & 0x3f);
3552 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3553 break;
3554 case 's':
3555 the_ins.opcode[0] |= val;
3556 break;
3557 case 'd':
3558 /* This is a kludge!!! */
3559 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3560 break;
3561 case 'b':
3562 case 'w':
3563 case 'l':
3564 case 'f':
3565 case 'F':
3566 case 'x':
3567 case 'p':
3568 the_ins.opcode[0] |= val;
3569 break;
3570 /* more stuff goes here. */
3571 default:
3572 as_fatal (_("failed sanity check."));
3573 }
3574 }
3575
3576 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3577 then deal with the bitfield hack. */
3578
3579 static char *
3580 crack_operand (char *str, struct m68k_op *opP)
3581 {
3582 register int parens;
3583 register int c;
3584 register char *beg_str;
3585 int inquote = 0;
3586
3587 if (!str)
3588 {
3589 return str;
3590 }
3591 beg_str = str;
3592 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3593 {
3594 if (! inquote)
3595 {
3596 if (*str == '(')
3597 parens++;
3598 else if (*str == ')')
3599 {
3600 if (!parens)
3601 { /* ERROR. */
3602 opP->error = _("Extra )");
3603 return str;
3604 }
3605 --parens;
3606 }
3607 }
3608 if (flag_mri && *str == '\'')
3609 inquote = ! inquote;
3610 }
3611 if (!*str && parens)
3612 { /* ERROR. */
3613 opP->error = _("Missing )");
3614 return str;
3615 }
3616 c = *str;
3617 *str = '\0';
3618 if (m68k_ip_op (beg_str, opP) != 0)
3619 {
3620 *str = c;
3621 return str;
3622 }
3623 *str = c;
3624 if (c == '}')
3625 c = *++str; /* JF bitfield hack. */
3626 if (c)
3627 {
3628 c = *++str;
3629 if (!c)
3630 as_bad (_("Missing operand"));
3631 }
3632
3633 /* Detect MRI REG symbols and convert them to REGLSTs. */
3634 if (opP->mode == CONTROL && (int)opP->reg < 0)
3635 {
3636 opP->mode = REGLST;
3637 opP->mask = ~(int)opP->reg;
3638 opP->reg = 0;
3639 }
3640
3641 return str;
3642 }
3643
3644 /* This is the guts of the machine-dependent assembler. STR points to a
3645 machine dependent instruction. This function is supposed to emit
3646 the frags/bytes it assembles to.
3647 */
3648
3649 static void
3650 insert_reg (const char *regname, int regnum)
3651 {
3652 char buf[100];
3653 int i;
3654
3655 #ifdef REGISTER_PREFIX
3656 if (!flag_reg_prefix_optional)
3657 {
3658 buf[0] = REGISTER_PREFIX;
3659 strcpy (buf + 1, regname);
3660 regname = buf;
3661 }
3662 #endif
3663
3664 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3665 &zero_address_frag));
3666
3667 for (i = 0; regname[i]; i++)
3668 buf[i] = TOUPPER (regname[i]);
3669 buf[i] = '\0';
3670
3671 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3672 &zero_address_frag));
3673 }
3674
3675 struct init_entry
3676 {
3677 const char *name;
3678 int number;
3679 };
3680
3681 static const struct init_entry init_table[] =
3682 {
3683 { "d0", DATA0 },
3684 { "d1", DATA1 },
3685 { "d2", DATA2 },
3686 { "d3", DATA3 },
3687 { "d4", DATA4 },
3688 { "d5", DATA5 },
3689 { "d6", DATA6 },
3690 { "d7", DATA7 },
3691 { "a0", ADDR0 },
3692 { "a1", ADDR1 },
3693 { "a2", ADDR2 },
3694 { "a3", ADDR3 },
3695 { "a4", ADDR4 },
3696 { "a5", ADDR5 },
3697 { "a6", ADDR6 },
3698 { "fp", ADDR6 },
3699 { "a7", ADDR7 },
3700 { "sp", ADDR7 },
3701 { "ssp", ADDR7 },
3702 { "fp0", FP0 },
3703 { "fp1", FP1 },
3704 { "fp2", FP2 },
3705 { "fp3", FP3 },
3706 { "fp4", FP4 },
3707 { "fp5", FP5 },
3708 { "fp6", FP6 },
3709 { "fp7", FP7 },
3710 { "fpi", FPI },
3711 { "fpiar", FPI },
3712 { "fpc", FPI },
3713 { "fps", FPS },
3714 { "fpsr", FPS },
3715 { "fpc", FPC },
3716 { "fpcr", FPC },
3717 { "control", FPC },
3718 { "status", FPS },
3719 { "iaddr", FPI },
3720
3721 { "cop0", COP0 },
3722 { "cop1", COP1 },
3723 { "cop2", COP2 },
3724 { "cop3", COP3 },
3725 { "cop4", COP4 },
3726 { "cop5", COP5 },
3727 { "cop6", COP6 },
3728 { "cop7", COP7 },
3729 { "pc", PC },
3730 { "zpc", ZPC },
3731 { "sr", SR },
3732
3733 { "ccr", CCR },
3734 { "cc", CCR },
3735
3736 { "acc", ACC },
3737 { "acc0", ACC },
3738 { "acc1", ACC1 },
3739 { "acc2", ACC2 },
3740 { "acc3", ACC3 },
3741 { "accext01", ACCEXT01 },
3742 { "accext23", ACCEXT23 },
3743 { "macsr", MACSR },
3744 { "mask", MASK },
3745
3746 /* Control registers. */
3747 { "sfc", SFC }, /* Source Function Code. */
3748 { "sfcr", SFC },
3749 { "dfc", DFC }, /* Destination Function Code. */
3750 { "dfcr", DFC },
3751 { "cacr", CACR }, /* Cache Control Register. */
3752 { "caar", CAAR }, /* Cache Address Register. */
3753
3754 { "usp", USP }, /* User Stack Pointer. */
3755 { "vbr", VBR }, /* Vector Base Register. */
3756 { "msp", MSP }, /* Master Stack Pointer. */
3757 { "isp", ISP }, /* Interrupt Stack Pointer. */
3758
3759 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3760 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3761 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3762 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
3763
3764 /* 68ec040 versions of same */
3765 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3766 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3767 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3768 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
3769
3770 /* mcf5200 versions of same. The ColdFire programmer's reference
3771 manual indicated that the order is 2,3,0,1, but Ken Rose
3772 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3773 { "acr0", ACR0 }, /* Access Control Unit 0. */
3774 { "acr1", ACR1 }, /* Access Control Unit 1. */
3775 { "acr2", ACR2 }, /* Access Control Unit 2. */
3776 { "acr3", ACR3 }, /* Access Control Unit 3. */
3777
3778 { "tc", TC }, /* MMU Translation Control Register. */
3779 { "tcr", TC },
3780
3781 { "mmusr", MMUSR }, /* MMU Status Register. */
3782 { "srp", SRP }, /* User Root Pointer. */
3783 { "urp", URP }, /* Supervisor Root Pointer. */
3784
3785 { "buscr", BUSCR },
3786 { "pcr", PCR },
3787
3788 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3789 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3790 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3791 { "mbar", MBAR }, /* Module Base Address Register. */
3792
3793 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3794 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3795 { "rombar0", ROMBAR }, /* mcfv4e registers. */
3796 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3797 { "mpcr", MPCR }, /* mcfv4e registers. */
3798 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3799 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3800 { "asid", TC }, /* mcfv4e registers. */
3801 { "mmubar", BUSCR }, /* mcfv4e registers. */
3802 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3803 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3804 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3805 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3806 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3807 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3808 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3809 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3810 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3811 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3812 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3813 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3814
3815 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3816 { "rambar", RAMBAR }, /* mcf528x registers. */
3817
3818 { "mbar2", MBAR2 }, /* mcf5249 registers. */
3819 /* End of control registers. */
3820
3821 { "ac", AC },
3822 { "bc", BC },
3823 { "cal", CAL },
3824 { "crp", CRP },
3825 { "drp", DRP },
3826 { "pcsr", PCSR },
3827 { "psr", PSR },
3828 { "scc", SCC },
3829 { "val", VAL },
3830 { "bad0", BAD0 },
3831 { "bad1", BAD1 },
3832 { "bad2", BAD2 },
3833 { "bad3", BAD3 },
3834 { "bad4", BAD4 },
3835 { "bad5", BAD5 },
3836 { "bad6", BAD6 },
3837 { "bad7", BAD7 },
3838 { "bac0", BAC0 },
3839 { "bac1", BAC1 },
3840 { "bac2", BAC2 },
3841 { "bac3", BAC3 },
3842 { "bac4", BAC4 },
3843 { "bac5", BAC5 },
3844 { "bac6", BAC6 },
3845 { "bac7", BAC7 },
3846
3847 { "ic", IC },
3848 { "dc", DC },
3849 { "nc", NC },
3850
3851 { "tt0", TT0 },
3852 { "tt1", TT1 },
3853 /* 68ec030 versions of same. */
3854 { "ac0", TT0 },
3855 { "ac1", TT1 },
3856 /* 68ec030 access control unit, identical to 030 MMU status reg. */
3857 { "acusr", PSR },
3858
3859 /* Suppressed data and address registers. */
3860 { "zd0", ZDATA0 },
3861 { "zd1", ZDATA1 },
3862 { "zd2", ZDATA2 },
3863 { "zd3", ZDATA3 },
3864 { "zd4", ZDATA4 },
3865 { "zd5", ZDATA5 },
3866 { "zd6", ZDATA6 },
3867 { "zd7", ZDATA7 },
3868 { "za0", ZADDR0 },
3869 { "za1", ZADDR1 },
3870 { "za2", ZADDR2 },
3871 { "za3", ZADDR3 },
3872 { "za4", ZADDR4 },
3873 { "za5", ZADDR5 },
3874 { "za6", ZADDR6 },
3875 { "za7", ZADDR7 },
3876
3877 /* Upper and lower data and address registers, used by macw and msacw. */
3878 { "d0l", DATA0L },
3879 { "d1l", DATA1L },
3880 { "d2l", DATA2L },
3881 { "d3l", DATA3L },
3882 { "d4l", DATA4L },
3883 { "d5l", DATA5L },
3884 { "d6l", DATA6L },
3885 { "d7l", DATA7L },
3886
3887 { "a0l", ADDR0L },
3888 { "a1l", ADDR1L },
3889 { "a2l", ADDR2L },
3890 { "a3l", ADDR3L },
3891 { "a4l", ADDR4L },
3892 { "a5l", ADDR5L },
3893 { "a6l", ADDR6L },
3894 { "a7l", ADDR7L },
3895
3896 { "d0u", DATA0U },
3897 { "d1u", DATA1U },
3898 { "d2u", DATA2U },
3899 { "d3u", DATA3U },
3900 { "d4u", DATA4U },
3901 { "d5u", DATA5U },
3902 { "d6u", DATA6U },
3903 { "d7u", DATA7U },
3904
3905 { "a0u", ADDR0U },
3906 { "a1u", ADDR1U },
3907 { "a2u", ADDR2U },
3908 { "a3u", ADDR3U },
3909 { "a4u", ADDR4U },
3910 { "a5u", ADDR5U },
3911 { "a6u", ADDR6U },
3912 { "a7u", ADDR7U },
3913
3914 { 0, 0 }
3915 };
3916
3917 static void
3918 init_regtable (void)
3919 {
3920 int i;
3921 for (i = 0; init_table[i].name; i++)
3922 insert_reg (init_table[i].name, init_table[i].number);
3923 }
3924
3925 void
3926 md_assemble (char *str)
3927 {
3928 const char *er;
3929 short *fromP;
3930 char *toP = NULL;
3931 int m, n = 0;
3932 char *to_beg_P;
3933 int shorts_this_frag;
3934 fixS *fixP;
3935
3936 if (!selected_cpu && !selected_arch)
3937 {
3938 /* We've not selected an architecture yet. Set the default
3939 now. We do this lazily so that an initial .cpu or .arch directive
3940 can specify. */
3941 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
3942 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
3943 }
3944 if (!initialized)
3945 m68k_init_arch ();
3946
3947 /* In MRI mode, the instruction and operands are separated by a
3948 space. Anything following the operands is a comment. The label
3949 has already been removed. */
3950 if (flag_mri)
3951 {
3952 char *s;
3953 int fields = 0;
3954 int infield = 0;
3955 int inquote = 0;
3956
3957 for (s = str; *s != '\0'; s++)
3958 {
3959 if ((*s == ' ' || *s == '\t') && ! inquote)
3960 {
3961 if (infield)
3962 {
3963 ++fields;
3964 if (fields >= 2)
3965 {
3966 *s = '\0';
3967 break;
3968 }
3969 infield = 0;
3970 }
3971 }
3972 else
3973 {
3974 if (! infield)
3975 infield = 1;
3976 if (*s == '\'')
3977 inquote = ! inquote;
3978 }
3979 }
3980 }
3981
3982 memset (&the_ins, '\0', sizeof (the_ins));
3983 m68k_ip (str);
3984 er = the_ins.error;
3985 if (!er)
3986 {
3987 for (n = 0; n < the_ins.numargs; n++)
3988 if (the_ins.operands[n].error)
3989 {
3990 er = the_ins.operands[n].error;
3991 break;
3992 }
3993 }
3994 if (er)
3995 {
3996 as_bad (_("%s -- statement `%s' ignored"), er, str);
3997 return;
3998 }
3999
4000 /* If there is a current label, record that it marks an instruction. */
4001 if (current_label != NULL)
4002 {
4003 current_label->text = 1;
4004 current_label = NULL;
4005 }
4006
4007 #ifdef OBJ_ELF
4008 /* Tie dwarf2 debug info to the address at the start of the insn. */
4009 dwarf2_emit_insn (0);
4010 #endif
4011
4012 if (the_ins.nfrag == 0)
4013 {
4014 /* No frag hacking involved; just put it out. */
4015 toP = frag_more (2 * the_ins.numo);
4016 fromP = &the_ins.opcode[0];
4017 for (m = the_ins.numo; m; --m)
4018 {
4019 md_number_to_chars (toP, (long) (*fromP), 2);
4020 toP += 2;
4021 fromP++;
4022 }
4023 /* Put out symbol-dependent info. */
4024 for (m = 0; m < the_ins.nrel; m++)
4025 {
4026 switch (the_ins.reloc[m].wid)
4027 {
4028 case 'B':
4029 n = 1;
4030 break;
4031 case 'b':
4032 n = 1;
4033 break;
4034 case '3':
4035 n = 1;
4036 break;
4037 case 'w':
4038 case 'W':
4039 n = 2;
4040 break;
4041 case 'l':
4042 n = 4;
4043 break;
4044 default:
4045 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4046 the_ins.reloc[m].wid);
4047 }
4048
4049 fixP = fix_new_exp (frag_now,
4050 ((toP - frag_now->fr_literal)
4051 - the_ins.numo * 2 + the_ins.reloc[m].n),
4052 n,
4053 &the_ins.reloc[m].exp,
4054 the_ins.reloc[m].pcrel,
4055 get_reloc_code (n, the_ins.reloc[m].pcrel,
4056 the_ins.reloc[m].pic_reloc));
4057 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4058 if (the_ins.reloc[m].wid == 'B')
4059 fixP->fx_signed = 1;
4060 }
4061 return;
4062 }
4063
4064 /* There's some frag hacking. */
4065 {
4066 /* Calculate the max frag size. */
4067 int wid;
4068
4069 wid = 2 * the_ins.fragb[0].fragoff;
4070 for (n = 1; n < the_ins.nfrag; n++)
4071 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4072 /* frag_var part. */
4073 wid += 10;
4074 /* Make sure the whole insn fits in one chunk, in particular that
4075 the var part is attached, as we access one byte before the
4076 variable frag for byte branches. */
4077 frag_grow (wid);
4078 }
4079
4080 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4081 {
4082 int wid;
4083
4084 if (n == 0)
4085 wid = 2 * the_ins.fragb[n].fragoff;
4086 else
4087 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4088 toP = frag_more (wid);
4089 to_beg_P = toP;
4090 shorts_this_frag = 0;
4091 for (m = wid / 2; m; --m)
4092 {
4093 md_number_to_chars (toP, (long) (*fromP), 2);
4094 toP += 2;
4095 fromP++;
4096 shorts_this_frag++;
4097 }
4098 for (m = 0; m < the_ins.nrel; m++)
4099 {
4100 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4101 {
4102 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4103 break;
4104 }
4105 wid = the_ins.reloc[m].wid;
4106 if (wid == 0)
4107 continue;
4108 the_ins.reloc[m].wid = 0;
4109 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4110
4111 fixP = fix_new_exp (frag_now,
4112 ((toP - frag_now->fr_literal)
4113 - the_ins.numo * 2 + the_ins.reloc[m].n),
4114 wid,
4115 &the_ins.reloc[m].exp,
4116 the_ins.reloc[m].pcrel,
4117 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4118 the_ins.reloc[m].pic_reloc));
4119 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4120 }
4121 (void) frag_var (rs_machine_dependent, 10, 0,
4122 (relax_substateT) (the_ins.fragb[n].fragty),
4123 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4124 }
4125 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4126 shorts_this_frag = 0;
4127 if (n)
4128 {
4129 toP = frag_more (n * 2);
4130 while (n--)
4131 {
4132 md_number_to_chars (toP, (long) (*fromP), 2);
4133 toP += 2;
4134 fromP++;
4135 shorts_this_frag++;
4136 }
4137 }
4138 for (m = 0; m < the_ins.nrel; m++)
4139 {
4140 int wid;
4141
4142 wid = the_ins.reloc[m].wid;
4143 if (wid == 0)
4144 continue;
4145 the_ins.reloc[m].wid = 0;
4146 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4147
4148 fixP = fix_new_exp (frag_now,
4149 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4150 - shorts_this_frag * 2),
4151 wid,
4152 &the_ins.reloc[m].exp,
4153 the_ins.reloc[m].pcrel,
4154 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4155 the_ins.reloc[m].pic_reloc));
4156 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4157 }
4158 }
4159
4160 /* Comparison function used by qsort to rank the opcode entries by name. */
4161
4162 static int
4163 m68k_compare_opcode (const void * v1, const void * v2)
4164 {
4165 struct m68k_opcode * op1, * op2;
4166 int ret;
4167
4168 if (v1 == v2)
4169 return 0;
4170
4171 op1 = *(struct m68k_opcode **) v1;
4172 op2 = *(struct m68k_opcode **) v2;
4173
4174 /* Compare the two names. If different, return the comparison.
4175 If the same, return the order they are in the opcode table. */
4176 ret = strcmp (op1->name, op2->name);
4177 if (ret)
4178 return ret;
4179 if (op1 < op2)
4180 return -1;
4181 return 1;
4182 }
4183
4184 void
4185 md_begin (void)
4186 {
4187 const struct m68k_opcode *ins;
4188 struct m68k_incant *hack, *slak;
4189 const char *retval = 0; /* Empty string, or error msg text. */
4190 int i;
4191
4192 /* Set up hash tables with 68000 instructions.
4193 similar to what the vax assembler does. */
4194 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4195 a copy of it at runtime, adding in the information we want but isn't
4196 there. I think it'd be better to have an awk script hack the table
4197 at compile time. Or even just xstr the table and use it as-is. But
4198 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4199 names. */
4200
4201 if (flag_mri)
4202 {
4203 flag_reg_prefix_optional = 1;
4204 m68k_abspcadd = 1;
4205 if (! m68k_rel32_from_cmdline)
4206 m68k_rel32 = 0;
4207 }
4208
4209 /* First sort the opcode table into alphabetical order to seperate
4210 the order that the assembler wants to see the opcodes from the
4211 order that the disassembler wants to see them. */
4212 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4213 if (!m68k_sorted_opcodes)
4214 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4215 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
4216
4217 for (i = m68k_numopcodes; i--;)
4218 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4219
4220 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4221 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4222
4223 op_hash = hash_new ();
4224
4225 obstack_begin (&robyn, 4000);
4226 for (i = 0; i < m68k_numopcodes; i++)
4227 {
4228 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4229 do
4230 {
4231 ins = m68k_sorted_opcodes[i];
4232
4233 /* We *could* ignore insns that don't match our
4234 arch here by just leaving them out of the hash. */
4235 slak->m_operands = ins->args;
4236 slak->m_opnum = strlen (slak->m_operands) / 2;
4237 slak->m_arch = ins->arch;
4238 slak->m_opcode = ins->opcode;
4239 /* This is kludgey. */
4240 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4241 if (i + 1 != m68k_numopcodes
4242 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4243 {
4244 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4245 i++;
4246 }
4247 else
4248 slak->m_next = 0;
4249 slak = slak->m_next;
4250 }
4251 while (slak);
4252
4253 retval = hash_insert (op_hash, ins->name, (char *) hack);
4254 if (retval)
4255 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4256 }
4257
4258 for (i = 0; i < m68k_numaliases; i++)
4259 {
4260 const char *name = m68k_opcode_aliases[i].primary;
4261 const char *alias = m68k_opcode_aliases[i].alias;
4262 PTR val = hash_find (op_hash, name);
4263
4264 if (!val)
4265 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4266 retval = hash_insert (op_hash, alias, val);
4267 if (retval)
4268 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4269 }
4270
4271 /* In MRI mode, all unsized branches are variable sized. Normally,
4272 they are word sized. */
4273 if (flag_mri)
4274 {
4275 static struct m68k_opcode_alias mri_aliases[] =
4276 {
4277 { "bhi", "jhi", },
4278 { "bls", "jls", },
4279 { "bcc", "jcc", },
4280 { "bcs", "jcs", },
4281 { "bne", "jne", },
4282 { "beq", "jeq", },
4283 { "bvc", "jvc", },
4284 { "bvs", "jvs", },
4285 { "bpl", "jpl", },
4286 { "bmi", "jmi", },
4287 { "bge", "jge", },
4288 { "blt", "jlt", },
4289 { "bgt", "jgt", },
4290 { "ble", "jle", },
4291 { "bra", "jra", },
4292 { "bsr", "jbsr", },
4293 };
4294
4295 for (i = 0;
4296 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4297 i++)
4298 {
4299 const char *name = mri_aliases[i].primary;
4300 const char *alias = mri_aliases[i].alias;
4301 PTR val = hash_find (op_hash, name);
4302
4303 if (!val)
4304 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4305 retval = hash_jam (op_hash, alias, val);
4306 if (retval)
4307 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4308 }
4309 }
4310
4311 for (i = 0; i < (int) sizeof (notend_table); i++)
4312 {
4313 notend_table[i] = 0;
4314 alt_notend_table[i] = 0;
4315 }
4316
4317 notend_table[','] = 1;
4318 notend_table['{'] = 1;
4319 notend_table['}'] = 1;
4320 alt_notend_table['a'] = 1;
4321 alt_notend_table['A'] = 1;
4322 alt_notend_table['d'] = 1;
4323 alt_notend_table['D'] = 1;
4324 alt_notend_table['#'] = 1;
4325 alt_notend_table['&'] = 1;
4326 alt_notend_table['f'] = 1;
4327 alt_notend_table['F'] = 1;
4328 #ifdef REGISTER_PREFIX
4329 alt_notend_table[REGISTER_PREFIX] = 1;
4330 #endif
4331
4332 /* We need to put '(' in alt_notend_table to handle
4333 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4334 alt_notend_table['('] = 1;
4335
4336 /* We need to put '@' in alt_notend_table to handle
4337 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4338 alt_notend_table['@'] = 1;
4339
4340 /* We need to put digits in alt_notend_table to handle
4341 bfextu %d0{24:1},%d0 */
4342 alt_notend_table['0'] = 1;
4343 alt_notend_table['1'] = 1;
4344 alt_notend_table['2'] = 1;
4345 alt_notend_table['3'] = 1;
4346 alt_notend_table['4'] = 1;
4347 alt_notend_table['5'] = 1;
4348 alt_notend_table['6'] = 1;
4349 alt_notend_table['7'] = 1;
4350 alt_notend_table['8'] = 1;
4351 alt_notend_table['9'] = 1;
4352
4353 #ifndef MIT_SYNTAX_ONLY
4354 /* Insert pseudo ops, these have to go into the opcode table since
4355 gas expects pseudo ops to start with a dot. */
4356 {
4357 int n = 0;
4358
4359 while (mote_pseudo_table[n].poc_name)
4360 {
4361 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4362 hash_insert (op_hash,
4363 mote_pseudo_table[n].poc_name, (char *) hack);
4364 hack->m_operands = 0;
4365 hack->m_opnum = n;
4366 n++;
4367 }
4368 }
4369 #endif
4370
4371 init_regtable ();
4372
4373 #ifdef OBJ_ELF
4374 record_alignment (text_section, 2);
4375 record_alignment (data_section, 2);
4376 record_alignment (bss_section, 2);
4377 #endif
4378 }
4379
4380 \f
4381 /* This is called when a label is defined. */
4382
4383 void
4384 m68k_frob_label (symbolS *sym)
4385 {
4386 struct label_line *n;
4387
4388 n = (struct label_line *) xmalloc (sizeof *n);
4389 n->next = labels;
4390 n->label = sym;
4391 as_where (&n->file, &n->line);
4392 n->text = 0;
4393 labels = n;
4394 current_label = n;
4395
4396 #ifdef OBJ_ELF
4397 dwarf2_emit_label (sym);
4398 #endif
4399 }
4400
4401 /* This is called when a value that is not an instruction is emitted. */
4402
4403 void
4404 m68k_flush_pending_output (void)
4405 {
4406 current_label = NULL;
4407 }
4408
4409 /* This is called at the end of the assembly, when the final value of
4410 the label is known. We warn if this is a text symbol aligned at an
4411 odd location. */
4412
4413 void
4414 m68k_frob_symbol (symbolS *sym)
4415 {
4416 if (S_GET_SEGMENT (sym) == reg_section
4417 && (int) S_GET_VALUE (sym) < 0)
4418 {
4419 S_SET_SEGMENT (sym, absolute_section);
4420 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4421 }
4422 else if ((S_GET_VALUE (sym) & 1) != 0)
4423 {
4424 struct label_line *l;
4425
4426 for (l = labels; l != NULL; l = l->next)
4427 {
4428 if (l->label == sym)
4429 {
4430 if (l->text)
4431 as_warn_where (l->file, l->line,
4432 _("text label `%s' aligned to odd boundary"),
4433 S_GET_NAME (sym));
4434 break;
4435 }
4436 }
4437 }
4438 }
4439 \f
4440 /* This is called if we go in or out of MRI mode because of the .mri
4441 pseudo-op. */
4442
4443 void
4444 m68k_mri_mode_change (int on)
4445 {
4446 if (on)
4447 {
4448 if (! flag_reg_prefix_optional)
4449 {
4450 flag_reg_prefix_optional = 1;
4451 #ifdef REGISTER_PREFIX
4452 init_regtable ();
4453 #endif
4454 }
4455 m68k_abspcadd = 1;
4456 if (! m68k_rel32_from_cmdline)
4457 m68k_rel32 = 0;
4458 }
4459 else
4460 {
4461 if (! reg_prefix_optional_seen)
4462 {
4463 #ifdef REGISTER_PREFIX_OPTIONAL
4464 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4465 #else
4466 flag_reg_prefix_optional = 0;
4467 #endif
4468 #ifdef REGISTER_PREFIX
4469 init_regtable ();
4470 #endif
4471 }
4472 m68k_abspcadd = 0;
4473 if (! m68k_rel32_from_cmdline)
4474 m68k_rel32 = 1;
4475 }
4476 }
4477
4478 /* Equal to MAX_PRECISION in atof-ieee.c. */
4479 #define MAX_LITTLENUMS 6
4480
4481 /* Turn a string in input_line_pointer into a floating point constant
4482 of type TYPE, and store the appropriate bytes in *LITP. The number
4483 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4484 returned, or NULL on OK. */
4485
4486 char *
4487 md_atof (int type, char *litP, int *sizeP)
4488 {
4489 int prec;
4490 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4491 LITTLENUM_TYPE *wordP;
4492 char *t;
4493
4494 switch (type)
4495 {
4496 case 'f':
4497 case 'F':
4498 case 's':
4499 case 'S':
4500 prec = 2;
4501 break;
4502
4503 case 'd':
4504 case 'D':
4505 case 'r':
4506 case 'R':
4507 prec = 4;
4508 break;
4509
4510 case 'x':
4511 case 'X':
4512 prec = 6;
4513 break;
4514
4515 case 'p':
4516 case 'P':
4517 prec = 6;
4518 break;
4519
4520 default:
4521 *sizeP = 0;
4522 return _("Bad call to MD_ATOF()");
4523 }
4524 t = atof_ieee (input_line_pointer, type, words);
4525 if (t)
4526 input_line_pointer = t;
4527
4528 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4529 for (wordP = words; prec--;)
4530 {
4531 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4532 litP += sizeof (LITTLENUM_TYPE);
4533 }
4534 return 0;
4535 }
4536
4537 void
4538 md_number_to_chars (char *buf, valueT val, int n)
4539 {
4540 number_to_chars_bigendian (buf, val, n);
4541 }
4542
4543 void
4544 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4545 {
4546 offsetT val = *valP;
4547 addressT upper_limit;
4548 offsetT lower_limit;
4549
4550 /* This is unnecessary but it convinces the native rs6000 compiler
4551 to generate the code we want. */
4552 char *buf = fixP->fx_frag->fr_literal;
4553 buf += fixP->fx_where;
4554 /* End ibm compiler workaround. */
4555
4556 val = SEXT (val);
4557
4558 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4559 fixP->fx_done = 1;
4560
4561 #ifdef OBJ_ELF
4562 if (fixP->fx_addsy)
4563 {
4564 memset (buf, 0, fixP->fx_size);
4565 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4566
4567 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4568 && !S_IS_DEFINED (fixP->fx_addsy)
4569 && !S_IS_WEAK (fixP->fx_addsy))
4570 S_SET_WEAK (fixP->fx_addsy);
4571 return;
4572 }
4573 #endif
4574
4575 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4576 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4577 return;
4578
4579 switch (fixP->fx_size)
4580 {
4581 /* The cast to offsetT below are necessary to make code
4582 correct for machines where ints are smaller than offsetT. */
4583 case 1:
4584 *buf++ = val;
4585 upper_limit = 0x7f;
4586 lower_limit = - (offsetT) 0x80;
4587 break;
4588 case 2:
4589 *buf++ = (val >> 8);
4590 *buf++ = val;
4591 upper_limit = 0x7fff;
4592 lower_limit = - (offsetT) 0x8000;
4593 break;
4594 case 4:
4595 *buf++ = (val >> 24);
4596 *buf++ = (val >> 16);
4597 *buf++ = (val >> 8);
4598 *buf++ = val;
4599 upper_limit = 0x7fffffff;
4600 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4601 break;
4602 default:
4603 BAD_CASE (fixP->fx_size);
4604 }
4605
4606 /* Fix up a negative reloc. */
4607 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4608 {
4609 fixP->fx_addsy = fixP->fx_subsy;
4610 fixP->fx_subsy = NULL;
4611 fixP->fx_tcbit = 1;
4612 }
4613
4614 /* For non-pc-relative values, it's conceivable we might get something
4615 like "0xff" for a byte field. So extend the upper part of the range
4616 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4617 so that we can do any range checking at all. */
4618 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4619 upper_limit = upper_limit * 2 + 1;
4620
4621 if ((addressT) val > upper_limit
4622 && (val > 0 || val < lower_limit))
4623 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4624
4625 /* A one byte PC-relative reloc means a short branch. We can't use
4626 a short branch with a value of 0 or -1, because those indicate
4627 different opcodes (branches with longer offsets). fixup_segment
4628 in write.c may have clobbered fx_pcrel, so we need to examine the
4629 reloc type. */
4630 if ((fixP->fx_pcrel
4631 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4632 && fixP->fx_size == 1
4633 && (fixP->fx_addsy == NULL
4634 || S_IS_DEFINED (fixP->fx_addsy))
4635 && (val == 0 || val == -1))
4636 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4637 }
4638
4639 /* *fragP has been relaxed to its final size, and now needs to have
4640 the bytes inside it modified to conform to the new size There is UGLY
4641 MAGIC here. ..
4642 */
4643 static void
4644 md_convert_frag_1 (fragS *fragP)
4645 {
4646 long disp;
4647 fixS *fixP;
4648
4649 /* Address in object code of the displacement. */
4650 register int object_address = fragP->fr_fix + fragP->fr_address;
4651
4652 /* Address in gas core of the place to store the displacement. */
4653 /* This convinces the native rs6000 compiler to generate the code we
4654 want. */
4655 register char *buffer_address = fragP->fr_literal;
4656 buffer_address += fragP->fr_fix;
4657 /* End ibm compiler workaround. */
4658
4659 /* The displacement of the address, from current location. */
4660 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4661 disp = (disp + fragP->fr_offset) - object_address;
4662
4663 switch (fragP->fr_subtype)
4664 {
4665 case TAB (BRANCHBWL, BYTE):
4666 case TAB (BRABSJUNC, BYTE):
4667 case TAB (BRABSJCOND, BYTE):
4668 case TAB (BRANCHBW, BYTE):
4669 know (issbyte (disp));
4670 if (disp == 0)
4671 as_bad_where (fragP->fr_file, fragP->fr_line,
4672 _("short branch with zero offset: use :w"));
4673 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4674 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4675 fixP->fx_pcrel_adjust = -1;
4676 break;
4677 case TAB (BRANCHBWL, SHORT):
4678 case TAB (BRABSJUNC, SHORT):
4679 case TAB (BRABSJCOND, SHORT):
4680 case TAB (BRANCHBW, SHORT):
4681 fragP->fr_opcode[1] = 0x00;
4682 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4683 1, RELAX_RELOC_PC16);
4684 fragP->fr_fix += 2;
4685 break;
4686 case TAB (BRANCHBWL, LONG):
4687 fragP->fr_opcode[1] = (char) 0xFF;
4688 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4689 1, RELAX_RELOC_PC32);
4690 fragP->fr_fix += 4;
4691 break;
4692 case TAB (BRABSJUNC, LONG):
4693 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4694 {
4695 if (flag_keep_pcrel)
4696 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
4697 fragP->fr_opcode[0] = 0x4E;
4698 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4699 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4700 0, RELAX_RELOC_ABS32);
4701 fragP->fr_fix += 4;
4702 }
4703 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4704 {
4705 if (flag_keep_pcrel)
4706 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
4707 fragP->fr_opcode[0] = 0x4E;
4708 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4709 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4710 0, RELAX_RELOC_ABS32);
4711 fragP->fr_fix += 4;
4712 }
4713 else
4714 {
4715 /* This cannot happen, because jbsr and jbra are the only two
4716 unconditional branches. */
4717 abort ();
4718 }
4719 break;
4720 case TAB (BRABSJCOND, LONG):
4721 if (flag_keep_pcrel)
4722 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4723
4724 /* Only Bcc 68000 instructions can come here
4725 Change bcc into b!cc/jmp absl long. */
4726 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4727 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
4728
4729 /* JF: these used to be fr_opcode[2,3], but they may be in a
4730 different frag, in which case referring to them is a no-no.
4731 Only fr_opcode[0,1] are guaranteed to work. */
4732 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4733 *buffer_address++ = (char) 0xf9;
4734 fragP->fr_fix += 2; /* Account for jmp instruction. */
4735 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4736 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4737 fragP->fr_fix += 4;
4738 break;
4739 case TAB (FBRANCH, SHORT):
4740 know ((fragP->fr_opcode[1] & 0x40) == 0);
4741 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4742 1, RELAX_RELOC_PC16);
4743 fragP->fr_fix += 2;
4744 break;
4745 case TAB (FBRANCH, LONG):
4746 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
4747 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4748 1, RELAX_RELOC_PC32);
4749 fragP->fr_fix += 4;
4750 break;
4751 case TAB (DBCCLBR, SHORT):
4752 case TAB (DBCCABSJ, SHORT):
4753 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4754 1, RELAX_RELOC_PC16);
4755 fragP->fr_fix += 2;
4756 break;
4757 case TAB (DBCCLBR, LONG):
4758 /* Only DBcc instructions can come here.
4759 Change dbcc into dbcc/bral.
4760 JF: these used to be fr_opcode[2-7], but that's wrong. */
4761 if (flag_keep_pcrel)
4762 as_fatal (_("Tried to convert DBcc to absolute jump"));
4763
4764 *buffer_address++ = 0x00; /* Branch offset = 4. */
4765 *buffer_address++ = 0x04;
4766 *buffer_address++ = 0x60; /* Put in bra pc+6. */
4767 *buffer_address++ = 0x06;
4768 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4769 *buffer_address++ = (char) 0xff;
4770
4771 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4772 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
4773 RELAX_RELOC_PC32);
4774 fragP->fr_fix += 4;
4775 break;
4776 case TAB (DBCCABSJ, LONG):
4777 /* Only DBcc instructions can come here.
4778 Change dbcc into dbcc/jmp.
4779 JF: these used to be fr_opcode[2-7], but that's wrong. */
4780 if (flag_keep_pcrel)
4781 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4782
4783 *buffer_address++ = 0x00; /* Branch offset = 4. */
4784 *buffer_address++ = 0x04;
4785 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
4786 *buffer_address++ = 0x06;
4787 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4788 *buffer_address++ = (char) 0xf9;
4789
4790 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4791 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
4792 RELAX_RELOC_ABS32);
4793 fragP->fr_fix += 4;
4794 break;
4795 case TAB (PCREL1632, SHORT):
4796 fragP->fr_opcode[1] &= ~0x3F;
4797 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4798 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4799 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4800 fragP->fr_fix += 2;
4801 break;
4802 case TAB (PCREL1632, LONG):
4803 /* Already set to mode 7.3; this indicates: PC indirect with
4804 suppressed index, 32-bit displacement. */
4805 *buffer_address++ = 0x01;
4806 *buffer_address++ = 0x70;
4807 fragP->fr_fix += 2;
4808 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4809 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4810 fixP->fx_pcrel_adjust = 2;
4811 fragP->fr_fix += 4;
4812 break;
4813 case TAB (PCINDEX, BYTE):
4814 assert (fragP->fr_fix >= 2);
4815 buffer_address[-2] &= ~1;
4816 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4817 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4818 fixP->fx_pcrel_adjust = 1;
4819 break;
4820 case TAB (PCINDEX, SHORT):
4821 assert (fragP->fr_fix >= 2);
4822 buffer_address[-2] |= 0x1;
4823 buffer_address[-1] = 0x20;
4824 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4825 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4826 fixP->fx_pcrel_adjust = 2;
4827 fragP->fr_fix += 2;
4828 break;
4829 case TAB (PCINDEX, LONG):
4830 assert (fragP->fr_fix >= 2);
4831 buffer_address[-2] |= 0x1;
4832 buffer_address[-1] = 0x30;
4833 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4834 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4835 fixP->fx_pcrel_adjust = 2;
4836 fragP->fr_fix += 4;
4837 break;
4838 case TAB (ABSTOPCREL, SHORT):
4839 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4840 1, RELAX_RELOC_PC16);
4841 fragP->fr_fix += 2;
4842 break;
4843 case TAB (ABSTOPCREL, LONG):
4844 if (flag_keep_pcrel)
4845 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4846 /* The thing to do here is force it to ABSOLUTE LONG, since
4847 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
4848 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4849 abort ();
4850 fragP->fr_opcode[1] &= ~0x3F;
4851 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4852 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4853 0, RELAX_RELOC_ABS32);
4854 fragP->fr_fix += 4;
4855 break;
4856 }
4857 }
4858
4859 void
4860 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
4861 segT sec ATTRIBUTE_UNUSED,
4862 fragS *fragP)
4863 {
4864 md_convert_frag_1 (fragP);
4865 }
4866
4867 /* Force truly undefined symbols to their maximum size, and generally set up
4868 the frag list to be relaxed
4869 */
4870 int
4871 md_estimate_size_before_relax (fragS *fragP, segT segment)
4872 {
4873 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4874 switch (fragP->fr_subtype)
4875 {
4876 case TAB (BRANCHBWL, SZ_UNDEF):
4877 case TAB (BRABSJUNC, SZ_UNDEF):
4878 case TAB (BRABSJCOND, SZ_UNDEF):
4879 {
4880 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4881 && relaxable_symbol (fragP->fr_symbol))
4882 {
4883 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4884 }
4885 else if (flag_short_refs)
4886 {
4887 /* Symbol is undefined and we want short ref. */
4888 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4889 }
4890 else
4891 {
4892 /* Symbol is still undefined. Make it LONG. */
4893 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4894 }
4895 break;
4896 }
4897
4898 case TAB (BRANCHBW, SZ_UNDEF):
4899 {
4900 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4901 && relaxable_symbol (fragP->fr_symbol))
4902 {
4903 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4904 }
4905 else
4906 {
4907 /* Symbol is undefined and we don't have long branches. */
4908 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4909 }
4910 break;
4911 }
4912
4913 case TAB (FBRANCH, SZ_UNDEF):
4914 case TAB (DBCCLBR, SZ_UNDEF):
4915 case TAB (DBCCABSJ, SZ_UNDEF):
4916 case TAB (PCREL1632, SZ_UNDEF):
4917 {
4918 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4919 && relaxable_symbol (fragP->fr_symbol))
4920 || flag_short_refs)
4921 {
4922 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4923 }
4924 else
4925 {
4926 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4927 }
4928 break;
4929 }
4930
4931 case TAB (PCINDEX, SZ_UNDEF):
4932 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4933 && relaxable_symbol (fragP->fr_symbol)))
4934 {
4935 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4936 }
4937 else
4938 {
4939 fragP->fr_subtype = TAB (PCINDEX, LONG);
4940 }
4941 break;
4942
4943 case TAB (ABSTOPCREL, SZ_UNDEF):
4944 {
4945 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4946 && relaxable_symbol (fragP->fr_symbol)))
4947 {
4948 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
4949 }
4950 else
4951 {
4952 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
4953 }
4954 break;
4955 }
4956
4957 default:
4958 break;
4959 }
4960
4961 /* Now that SZ_UNDEF are taken care of, check others. */
4962 switch (fragP->fr_subtype)
4963 {
4964 case TAB (BRANCHBWL, BYTE):
4965 case TAB (BRABSJUNC, BYTE):
4966 case TAB (BRABSJCOND, BYTE):
4967 case TAB (BRANCHBW, BYTE):
4968 /* We can't do a short jump to the next instruction, so in that
4969 case we force word mode. If the symbol is at the start of a
4970 frag, and it is the next frag with any data in it (usually
4971 this is just the next frag, but assembler listings may
4972 introduce empty frags), we must use word mode. */
4973 if (fragP->fr_symbol)
4974 {
4975 fragS *sym_frag;
4976
4977 sym_frag = symbol_get_frag (fragP->fr_symbol);
4978 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
4979 {
4980 fragS *l;
4981
4982 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
4983 if (l->fr_fix != 0)
4984 break;
4985 if (l == sym_frag)
4986 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4987 }
4988 }
4989 break;
4990 default:
4991 break;
4992 }
4993 return md_relax_table[fragP->fr_subtype].rlx_length;
4994 }
4995
4996 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4997 /* the bit-field entries in the relocation_info struct plays hell
4998 with the byte-order problems of cross-assembly. So as a hack,
4999 I added this mach. dependent ri twiddler. Ugly, but it gets
5000 you there. -KWK */
5001 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5002 are symbolnum, most sig. byte first. Last byte is broken up with
5003 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5004 nibble as nuthin. (on Sun 3 at least) */
5005 /* Translate the internal relocation information into target-specific
5006 format. */
5007 #ifdef comment
5008 void
5009 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
5010 {
5011 /* This is easy. */
5012 md_number_to_chars (the_bytes, ri->r_address, 4);
5013 /* Now the fun stuff. */
5014 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5015 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5016 the_bytes[6] = ri->r_symbolnum & 0x0ff;
5017 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5018 | ((ri->r_length << 5) & 0x60)
5019 | ((ri->r_extern << 4) & 0x10));
5020 }
5021
5022 #endif
5023
5024 #endif /* OBJ_AOUT or OBJ_BOUT */
5025
5026 #ifndef WORKING_DOT_WORD
5027 int md_short_jump_size = 4;
5028 int md_long_jump_size = 6;
5029
5030 void
5031 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5032 fragS *frag ATTRIBUTE_UNUSED,
5033 symbolS *to_symbol ATTRIBUTE_UNUSED)
5034 {
5035 valueT offset;
5036
5037 offset = to_addr - (from_addr + 2);
5038
5039 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5040 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5041 }
5042
5043 void
5044 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5045 fragS *frag, symbolS *to_symbol)
5046 {
5047 valueT offset;
5048
5049 if (!HAVE_LONG_BRANCH (current_architecture))
5050 {
5051 if (flag_keep_pcrel)
5052 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5053 offset = to_addr - S_GET_VALUE (to_symbol);
5054 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5055 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5056 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5057 0, NO_RELOC);
5058 }
5059 else
5060 {
5061 offset = to_addr - (from_addr + 2);
5062 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5063 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5064 }
5065 }
5066
5067 #endif
5068
5069 /* Different values of OK tell what its OK to return. Things that
5070 aren't OK are an error (what a shock, no?)
5071
5072 0: Everything is OK
5073 10: Absolute 1:8 only
5074 20: Absolute 0:7 only
5075 30: absolute 0:15 only
5076 40: Absolute 0:31 only
5077 50: absolute 0:127 only
5078 55: absolute -64:63 only
5079 60: absolute -128:127 only
5080 70: absolute 0:4095 only
5081 80: absolute -1, 1:7 only
5082 90: No bignums. */
5083
5084 static int
5085 get_num (struct m68k_exp *exp, int ok)
5086 {
5087 if (exp->exp.X_op == O_absent)
5088 {
5089 /* Do the same thing the VAX asm does. */
5090 op (exp) = O_constant;
5091 adds (exp) = 0;
5092 subs (exp) = 0;
5093 offs (exp) = 0;
5094 if (ok == 10)
5095 {
5096 as_warn (_("expression out of range: defaulting to 1"));
5097 offs (exp) = 1;
5098 }
5099 }
5100 else if (exp->exp.X_op == O_constant)
5101 {
5102 switch (ok)
5103 {
5104 case 10:
5105 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5106 {
5107 as_warn (_("expression out of range: defaulting to 1"));
5108 offs (exp) = 1;
5109 }
5110 break;
5111 case 20:
5112 if ((valueT) TRUNC (offs (exp)) > 7)
5113 goto outrange;
5114 break;
5115 case 30:
5116 if ((valueT) TRUNC (offs (exp)) > 15)
5117 goto outrange;
5118 break;
5119 case 40:
5120 if ((valueT) TRUNC (offs (exp)) > 32)
5121 goto outrange;
5122 break;
5123 case 50:
5124 if ((valueT) TRUNC (offs (exp)) > 127)
5125 goto outrange;
5126 break;
5127 case 55:
5128 if ((valueT) SEXT (offs (exp)) + 64 > 127)
5129 goto outrange;
5130 break;
5131 case 60:
5132 if ((valueT) SEXT (offs (exp)) + 128 > 255)
5133 goto outrange;
5134 break;
5135 case 70:
5136 if ((valueT) TRUNC (offs (exp)) > 4095)
5137 {
5138 outrange:
5139 as_warn (_("expression out of range: defaulting to 0"));
5140 offs (exp) = 0;
5141 }
5142 break;
5143 case 80:
5144 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5145 && (valueT) TRUNC (offs (exp)) - 1 > 6)
5146 {
5147 as_warn (_("expression out of range: defaulting to 1"));
5148 offs (exp) = 1;
5149 }
5150 break;
5151 default:
5152 break;
5153 }
5154 }
5155 else if (exp->exp.X_op == O_big)
5156 {
5157 if (offs (exp) <= 0 /* flonum. */
5158 && (ok == 90 /* no bignums */
5159 || (ok > 10 /* Small-int ranges including 0 ok. */
5160 /* If we have a flonum zero, a zero integer should
5161 do as well (e.g., in moveq). */
5162 && generic_floating_point_number.exponent == 0
5163 && generic_floating_point_number.low[0] == 0)))
5164 {
5165 /* HACK! Turn it into a long. */
5166 LITTLENUM_TYPE words[6];
5167
5168 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5169 op (exp) = O_constant;
5170 adds (exp) = 0;
5171 subs (exp) = 0;
5172 offs (exp) = words[1] | (words[0] << 16);
5173 }
5174 else if (ok != 0)
5175 {
5176 op (exp) = O_constant;
5177 adds (exp) = 0;
5178 subs (exp) = 0;
5179 offs (exp) = (ok == 10) ? 1 : 0;
5180 as_warn (_("Can't deal with expression; defaulting to %ld"),
5181 (long) offs (exp));
5182 }
5183 }
5184 else
5185 {
5186 if (ok >= 10 && ok <= 80)
5187 {
5188 op (exp) = O_constant;
5189 adds (exp) = 0;
5190 subs (exp) = 0;
5191 offs (exp) = (ok == 10) ? 1 : 0;
5192 as_warn (_("Can't deal with expression; defaulting to %ld"),
5193 (long) offs (exp));
5194 }
5195 }
5196
5197 if (exp->size != SIZE_UNSPEC)
5198 {
5199 switch (exp->size)
5200 {
5201 case SIZE_UNSPEC:
5202 case SIZE_LONG:
5203 break;
5204 case SIZE_BYTE:
5205 if (!isbyte (offs (exp)))
5206 as_warn (_("expression doesn't fit in BYTE"));
5207 break;
5208 case SIZE_WORD:
5209 if (!isword (offs (exp)))
5210 as_warn (_("expression doesn't fit in WORD"));
5211 break;
5212 }
5213 }
5214
5215 return offs (exp);
5216 }
5217
5218 /* These are the back-ends for the various machine dependent pseudo-ops. */
5219
5220 static void
5221 s_data1 (int ignore ATTRIBUTE_UNUSED)
5222 {
5223 subseg_set (data_section, 1);
5224 demand_empty_rest_of_line ();
5225 }
5226
5227 static void
5228 s_data2 (int ignore ATTRIBUTE_UNUSED)
5229 {
5230 subseg_set (data_section, 2);
5231 demand_empty_rest_of_line ();
5232 }
5233
5234 static void
5235 s_bss (int ignore ATTRIBUTE_UNUSED)
5236 {
5237 /* We don't support putting frags in the BSS segment, we fake it
5238 by marking in_bss, then looking at s_skip for clues. */
5239
5240 subseg_set (bss_section, 0);
5241 demand_empty_rest_of_line ();
5242 }
5243
5244 static void
5245 s_even (int ignore ATTRIBUTE_UNUSED)
5246 {
5247 register int temp;
5248 register long temp_fill;
5249
5250 temp = 1; /* JF should be 2? */
5251 temp_fill = get_absolute_expression ();
5252 if (!need_pass_2) /* Never make frag if expect extra pass. */
5253 frag_align (temp, (int) temp_fill, 0);
5254 demand_empty_rest_of_line ();
5255 record_alignment (now_seg, temp);
5256 }
5257
5258 static void
5259 s_proc (int ignore ATTRIBUTE_UNUSED)
5260 {
5261 demand_empty_rest_of_line ();
5262 }
5263 \f
5264 /* Pseudo-ops handled for MRI compatibility. */
5265
5266 /* This function returns non-zero if the argument is a conditional
5267 pseudo-op. This is called when checking whether a pending
5268 alignment is needed. */
5269
5270 int
5271 m68k_conditional_pseudoop (pseudo_typeS *pop)
5272 {
5273 return (pop->poc_handler == s_mri_if
5274 || pop->poc_handler == s_mri_else);
5275 }
5276
5277 /* Handle an MRI style chip specification. */
5278
5279 static void
5280 mri_chip (void)
5281 {
5282 char *s;
5283 char c;
5284 int i;
5285
5286 s = input_line_pointer;
5287 /* We can't use get_symbol_end since the processor names are not proper
5288 symbols. */
5289 while (is_part_of_name (c = *input_line_pointer++))
5290 ;
5291 *--input_line_pointer = 0;
5292 for (i = 0; m68k_cpus[i].name; i++)
5293 if (strcasecmp (s, m68k_cpus[i].name) == 0)
5294 break;
5295 if (!m68k_cpus[i].name)
5296 {
5297 as_bad (_("%s: unrecognized processor name"), s);
5298 *input_line_pointer = c;
5299 ignore_rest_of_line ();
5300 return;
5301 }
5302 *input_line_pointer = c;
5303
5304 if (*input_line_pointer == '/')
5305 current_architecture = 0;
5306 else
5307 current_architecture &= m68881 | m68851;
5308 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5309 control_regs = m68k_cpus[i].control_regs;
5310
5311 while (*input_line_pointer == '/')
5312 {
5313 ++input_line_pointer;
5314 s = input_line_pointer;
5315 /* We can't use get_symbol_end since the processor names are not
5316 proper symbols. */
5317 while (is_part_of_name (c = *input_line_pointer++))
5318 ;
5319 *--input_line_pointer = 0;
5320 if (strcmp (s, "68881") == 0)
5321 current_architecture |= m68881;
5322 else if (strcmp (s, "68851") == 0)
5323 current_architecture |= m68851;
5324 *input_line_pointer = c;
5325 }
5326 }
5327
5328 /* The MRI CHIP pseudo-op. */
5329
5330 static void
5331 s_chip (int ignore ATTRIBUTE_UNUSED)
5332 {
5333 char *stop = NULL;
5334 char stopc;
5335
5336 if (flag_mri)
5337 stop = mri_comment_field (&stopc);
5338 mri_chip ();
5339 if (flag_mri)
5340 mri_comment_end (stop, stopc);
5341 demand_empty_rest_of_line ();
5342 }
5343
5344 /* The MRI FOPT pseudo-op. */
5345
5346 static void
5347 s_fopt (int ignore ATTRIBUTE_UNUSED)
5348 {
5349 SKIP_WHITESPACE ();
5350
5351 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5352 {
5353 int temp;
5354
5355 input_line_pointer += 3;
5356 temp = get_absolute_expression ();
5357 if (temp < 0 || temp > 7)
5358 as_bad (_("bad coprocessor id"));
5359 else
5360 m68k_float_copnum = COP0 + temp;
5361 }
5362 else
5363 {
5364 as_bad (_("unrecognized fopt option"));
5365 ignore_rest_of_line ();
5366 return;
5367 }
5368
5369 demand_empty_rest_of_line ();
5370 }
5371
5372 /* The structure used to handle the MRI OPT pseudo-op. */
5373
5374 struct opt_action
5375 {
5376 /* The name of the option. */
5377 const char *name;
5378
5379 /* If this is not NULL, just call this function. The first argument
5380 is the ARG field of this structure, the second argument is
5381 whether the option was negated. */
5382 void (*pfn) (int arg, int on);
5383
5384 /* If this is not NULL, and the PFN field is NULL, set the variable
5385 this points to. Set it to the ARG field if the option was not
5386 negated, and the NOTARG field otherwise. */
5387 int *pvar;
5388
5389 /* The value to pass to PFN or to assign to *PVAR. */
5390 int arg;
5391
5392 /* The value to assign to *PVAR if the option is negated. If PFN is
5393 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5394 the option may not be negated. */
5395 int notarg;
5396 };
5397
5398 /* The table used to handle the MRI OPT pseudo-op. */
5399
5400 static void skip_to_comma (int, int);
5401 static void opt_nest (int, int);
5402 static void opt_chip (int, int);
5403 static void opt_list (int, int);
5404 static void opt_list_symbols (int, int);
5405
5406 static const struct opt_action opt_table[] =
5407 {
5408 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5409
5410 /* We do relaxing, so there is little use for these options. */
5411 { "b", 0, 0, 0, 0 },
5412 { "brs", 0, 0, 0, 0 },
5413 { "brb", 0, 0, 0, 0 },
5414 { "brl", 0, 0, 0, 0 },
5415 { "brw", 0, 0, 0, 0 },
5416
5417 { "c", 0, 0, 0, 0 },
5418 { "cex", 0, 0, 0, 0 },
5419 { "case", 0, &symbols_case_sensitive, 1, 0 },
5420 { "cl", 0, 0, 0, 0 },
5421 { "cre", 0, 0, 0, 0 },
5422 { "d", 0, &flag_keep_locals, 1, 0 },
5423 { "e", 0, 0, 0, 0 },
5424 { "f", 0, &flag_short_refs, 1, 0 },
5425 { "frs", 0, &flag_short_refs, 1, 0 },
5426 { "frl", 0, &flag_short_refs, 0, 1 },
5427 { "g", 0, 0, 0, 0 },
5428 { "i", 0, 0, 0, 0 },
5429 { "m", 0, 0, 0, 0 },
5430 { "mex", 0, 0, 0, 0 },
5431 { "mc", 0, 0, 0, 0 },
5432 { "md", 0, 0, 0, 0 },
5433 { "nest", opt_nest, 0, 0, 0 },
5434 { "next", skip_to_comma, 0, 0, 0 },
5435 { "o", 0, 0, 0, 0 },
5436 { "old", 0, 0, 0, 0 },
5437 { "op", skip_to_comma, 0, 0, 0 },
5438 { "pco", 0, 0, 0, 0 },
5439 { "p", opt_chip, 0, 0, 0 },
5440 { "pcr", 0, 0, 0, 0 },
5441 { "pcs", 0, 0, 0, 0 },
5442 { "r", 0, 0, 0, 0 },
5443 { "quick", 0, &m68k_quick, 1, 0 },
5444 { "rel32", 0, &m68k_rel32, 1, 0 },
5445 { "s", opt_list, 0, 0, 0 },
5446 { "t", opt_list_symbols, 0, 0, 0 },
5447 { "w", 0, &flag_no_warnings, 0, 1 },
5448 { "x", 0, 0, 0, 0 }
5449 };
5450
5451 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5452
5453 /* The MRI OPT pseudo-op. */
5454
5455 static void
5456 s_opt (int ignore ATTRIBUTE_UNUSED)
5457 {
5458 do
5459 {
5460 int t;
5461 char *s;
5462 char c;
5463 int i;
5464 const struct opt_action *o;
5465
5466 SKIP_WHITESPACE ();
5467
5468 t = 1;
5469 if (*input_line_pointer == '-')
5470 {
5471 ++input_line_pointer;
5472 t = 0;
5473 }
5474 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5475 {
5476 input_line_pointer += 2;
5477 t = 0;
5478 }
5479
5480 s = input_line_pointer;
5481 c = get_symbol_end ();
5482
5483 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5484 {
5485 if (strcasecmp (s, o->name) == 0)
5486 {
5487 if (o->pfn)
5488 {
5489 /* Restore input_line_pointer now in case the option
5490 takes arguments. */
5491 *input_line_pointer = c;
5492 (*o->pfn) (o->arg, t);
5493 }
5494 else if (o->pvar != NULL)
5495 {
5496 if (! t && o->arg == o->notarg)
5497 as_bad (_("option `%s' may not be negated"), s);
5498 *input_line_pointer = c;
5499 *o->pvar = t ? o->arg : o->notarg;
5500 }
5501 else
5502 *input_line_pointer = c;
5503 break;
5504 }
5505 }
5506 if (i >= OPTCOUNT)
5507 {
5508 as_bad (_("option `%s' not recognized"), s);
5509 *input_line_pointer = c;
5510 }
5511 }
5512 while (*input_line_pointer++ == ',');
5513
5514 /* Move back to terminating character. */
5515 --input_line_pointer;
5516 demand_empty_rest_of_line ();
5517 }
5518
5519 /* Skip ahead to a comma. This is used for OPT options which we do
5520 not support and which take arguments. */
5521
5522 static void
5523 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5524 {
5525 while (*input_line_pointer != ','
5526 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5527 ++input_line_pointer;
5528 }
5529
5530 /* Handle the OPT NEST=depth option. */
5531
5532 static void
5533 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5534 {
5535 if (*input_line_pointer != '=')
5536 {
5537 as_bad (_("bad format of OPT NEST=depth"));
5538 return;
5539 }
5540
5541 ++input_line_pointer;
5542 max_macro_nest = get_absolute_expression ();
5543 }
5544
5545 /* Handle the OPT P=chip option. */
5546
5547 static void
5548 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5549 {
5550 if (*input_line_pointer != '=')
5551 {
5552 /* This is just OPT P, which we do not support. */
5553 return;
5554 }
5555
5556 ++input_line_pointer;
5557 mri_chip ();
5558 }
5559
5560 /* Handle the OPT S option. */
5561
5562 static void
5563 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5564 {
5565 listing_list (on);
5566 }
5567
5568 /* Handle the OPT T option. */
5569
5570 static void
5571 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5572 {
5573 if (on)
5574 listing |= LISTING_SYMBOLS;
5575 else
5576 listing &= ~LISTING_SYMBOLS;
5577 }
5578
5579 /* Handle the MRI REG pseudo-op. */
5580
5581 static void
5582 s_reg (int ignore ATTRIBUTE_UNUSED)
5583 {
5584 char *s;
5585 int c;
5586 struct m68k_op rop;
5587 int mask;
5588 char *stop = NULL;
5589 char stopc;
5590
5591 if (line_label == NULL)
5592 {
5593 as_bad (_("missing label"));
5594 ignore_rest_of_line ();
5595 return;
5596 }
5597
5598 if (flag_mri)
5599 stop = mri_comment_field (&stopc);
5600
5601 SKIP_WHITESPACE ();
5602
5603 s = input_line_pointer;
5604 while (ISALNUM (*input_line_pointer)
5605 #ifdef REGISTER_PREFIX
5606 || *input_line_pointer == REGISTER_PREFIX
5607 #endif
5608 || *input_line_pointer == '/'
5609 || *input_line_pointer == '-')
5610 ++input_line_pointer;
5611 c = *input_line_pointer;
5612 *input_line_pointer = '\0';
5613
5614 if (m68k_ip_op (s, &rop) != 0)
5615 {
5616 if (rop.error == NULL)
5617 as_bad (_("bad register list"));
5618 else
5619 as_bad (_("bad register list: %s"), rop.error);
5620 *input_line_pointer = c;
5621 ignore_rest_of_line ();
5622 return;
5623 }
5624
5625 *input_line_pointer = c;
5626
5627 if (rop.mode == REGLST)
5628 mask = rop.mask;
5629 else if (rop.mode == DREG)
5630 mask = 1 << (rop.reg - DATA0);
5631 else if (rop.mode == AREG)
5632 mask = 1 << (rop.reg - ADDR0 + 8);
5633 else if (rop.mode == FPREG)
5634 mask = 1 << (rop.reg - FP0 + 16);
5635 else if (rop.mode == CONTROL
5636 && rop.reg == FPI)
5637 mask = 1 << 24;
5638 else if (rop.mode == CONTROL
5639 && rop.reg == FPS)
5640 mask = 1 << 25;
5641 else if (rop.mode == CONTROL
5642 && rop.reg == FPC)
5643 mask = 1 << 26;
5644 else
5645 {
5646 as_bad (_("bad register list"));
5647 ignore_rest_of_line ();
5648 return;
5649 }
5650
5651 S_SET_SEGMENT (line_label, reg_section);
5652 S_SET_VALUE (line_label, ~mask);
5653 symbol_set_frag (line_label, &zero_address_frag);
5654
5655 if (flag_mri)
5656 mri_comment_end (stop, stopc);
5657
5658 demand_empty_rest_of_line ();
5659 }
5660
5661 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5662
5663 struct save_opts
5664 {
5665 struct save_opts *next;
5666 int abspcadd;
5667 int symbols_case_sensitive;
5668 int keep_locals;
5669 int short_refs;
5670 int architecture;
5671 const enum m68k_register *control_regs;
5672 int quick;
5673 int rel32;
5674 int listing;
5675 int no_warnings;
5676 /* FIXME: We don't save OPT S. */
5677 };
5678
5679 /* This variable holds the stack of saved options. */
5680
5681 static struct save_opts *save_stack;
5682
5683 /* The MRI SAVE pseudo-op. */
5684
5685 static void
5686 s_save (int ignore ATTRIBUTE_UNUSED)
5687 {
5688 struct save_opts *s;
5689
5690 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5691 s->abspcadd = m68k_abspcadd;
5692 s->symbols_case_sensitive = symbols_case_sensitive;
5693 s->keep_locals = flag_keep_locals;
5694 s->short_refs = flag_short_refs;
5695 s->architecture = current_architecture;
5696 s->control_regs = control_regs;
5697 s->quick = m68k_quick;
5698 s->rel32 = m68k_rel32;
5699 s->listing = listing;
5700 s->no_warnings = flag_no_warnings;
5701
5702 s->next = save_stack;
5703 save_stack = s;
5704
5705 demand_empty_rest_of_line ();
5706 }
5707
5708 /* The MRI RESTORE pseudo-op. */
5709
5710 static void
5711 s_restore (int ignore ATTRIBUTE_UNUSED)
5712 {
5713 struct save_opts *s;
5714
5715 if (save_stack == NULL)
5716 {
5717 as_bad (_("restore without save"));
5718 ignore_rest_of_line ();
5719 return;
5720 }
5721
5722 s = save_stack;
5723 save_stack = s->next;
5724
5725 m68k_abspcadd = s->abspcadd;
5726 symbols_case_sensitive = s->symbols_case_sensitive;
5727 flag_keep_locals = s->keep_locals;
5728 flag_short_refs = s->short_refs;
5729 current_architecture = s->architecture;
5730 control_regs = s->control_regs;
5731 m68k_quick = s->quick;
5732 m68k_rel32 = s->rel32;
5733 listing = s->listing;
5734 flag_no_warnings = s->no_warnings;
5735
5736 free (s);
5737
5738 demand_empty_rest_of_line ();
5739 }
5740
5741 /* Types of MRI structured control directives. */
5742
5743 enum mri_control_type
5744 {
5745 mri_for,
5746 mri_if,
5747 mri_repeat,
5748 mri_while
5749 };
5750
5751 /* This structure is used to stack the MRI structured control
5752 directives. */
5753
5754 struct mri_control_info
5755 {
5756 /* The directive within which this one is enclosed. */
5757 struct mri_control_info *outer;
5758
5759 /* The type of directive. */
5760 enum mri_control_type type;
5761
5762 /* Whether an ELSE has been in an IF. */
5763 int else_seen;
5764
5765 /* The add or sub statement at the end of a FOR. */
5766 char *incr;
5767
5768 /* The label of the top of a FOR or REPEAT loop. */
5769 char *top;
5770
5771 /* The label to jump to for the next iteration, or the else
5772 expression of a conditional. */
5773 char *next;
5774
5775 /* The label to jump to to break out of the loop, or the label past
5776 the end of a conditional. */
5777 char *bottom;
5778 };
5779
5780 /* The stack of MRI structured control directives. */
5781
5782 static struct mri_control_info *mri_control_stack;
5783
5784 /* The current MRI structured control directive index number, used to
5785 generate label names. */
5786
5787 static int mri_control_index;
5788
5789 /* Assemble an instruction for an MRI structured control directive. */
5790
5791 static void
5792 mri_assemble (char *str)
5793 {
5794 char *s;
5795
5796 /* md_assemble expects the opcode to be in lower case. */
5797 for (s = str; *s != ' ' && *s != '\0'; s++)
5798 *s = TOLOWER (*s);
5799
5800 md_assemble (str);
5801 }
5802
5803 /* Generate a new MRI label structured control directive label name. */
5804
5805 static char *
5806 mri_control_label (void)
5807 {
5808 char *n;
5809
5810 n = (char *) xmalloc (20);
5811 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5812 ++mri_control_index;
5813 return n;
5814 }
5815
5816 /* Create a new MRI structured control directive. */
5817
5818 static struct mri_control_info *
5819 push_mri_control (enum mri_control_type type)
5820 {
5821 struct mri_control_info *n;
5822
5823 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5824
5825 n->type = type;
5826 n->else_seen = 0;
5827 if (type == mri_if || type == mri_while)
5828 n->top = NULL;
5829 else
5830 n->top = mri_control_label ();
5831 n->next = mri_control_label ();
5832 n->bottom = mri_control_label ();
5833
5834 n->outer = mri_control_stack;
5835 mri_control_stack = n;
5836
5837 return n;
5838 }
5839
5840 /* Pop off the stack of MRI structured control directives. */
5841
5842 static void
5843 pop_mri_control (void)
5844 {
5845 struct mri_control_info *n;
5846
5847 n = mri_control_stack;
5848 mri_control_stack = n->outer;
5849 if (n->top != NULL)
5850 free (n->top);
5851 free (n->next);
5852 free (n->bottom);
5853 free (n);
5854 }
5855
5856 /* Recognize a condition code in an MRI structured control expression. */
5857
5858 static int
5859 parse_mri_condition (int *pcc)
5860 {
5861 char c1, c2;
5862
5863 know (*input_line_pointer == '<');
5864
5865 ++input_line_pointer;
5866 c1 = *input_line_pointer++;
5867 c2 = *input_line_pointer++;
5868
5869 if (*input_line_pointer != '>')
5870 {
5871 as_bad (_("syntax error in structured control directive"));
5872 return 0;
5873 }
5874
5875 ++input_line_pointer;
5876 SKIP_WHITESPACE ();
5877
5878 c1 = TOLOWER (c1);
5879 c2 = TOLOWER (c2);
5880
5881 *pcc = (c1 << 8) | c2;
5882
5883 return 1;
5884 }
5885
5886 /* Parse a single operand in an MRI structured control expression. */
5887
5888 static int
5889 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
5890 char **rightstart, char **rightstop)
5891 {
5892 char *s;
5893
5894 SKIP_WHITESPACE ();
5895
5896 *pcc = -1;
5897 *leftstart = NULL;
5898 *leftstop = NULL;
5899 *rightstart = NULL;
5900 *rightstop = NULL;
5901
5902 if (*input_line_pointer == '<')
5903 {
5904 /* It's just a condition code. */
5905 return parse_mri_condition (pcc);
5906 }
5907
5908 /* Look ahead for the condition code. */
5909 for (s = input_line_pointer; *s != '\0'; ++s)
5910 {
5911 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5912 break;
5913 }
5914 if (*s == '\0')
5915 {
5916 as_bad (_("missing condition code in structured control directive"));
5917 return 0;
5918 }
5919
5920 *leftstart = input_line_pointer;
5921 *leftstop = s;
5922 if (*leftstop > *leftstart
5923 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5924 --*leftstop;
5925
5926 input_line_pointer = s;
5927 if (! parse_mri_condition (pcc))
5928 return 0;
5929
5930 /* Look ahead for AND or OR or end of line. */
5931 for (s = input_line_pointer; *s != '\0'; ++s)
5932 {
5933 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5934 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5935 ^^^ ^^ */
5936 if ((s == input_line_pointer
5937 || *(s-1) == ' '
5938 || *(s-1) == '\t')
5939 && ((strncasecmp (s, "AND", 3) == 0
5940 && (s[3] == '.' || ! is_part_of_name (s[3])))
5941 || (strncasecmp (s, "OR", 2) == 0
5942 && (s[2] == '.' || ! is_part_of_name (s[2])))))
5943 break;
5944 }
5945
5946 *rightstart = input_line_pointer;
5947 *rightstop = s;
5948 if (*rightstop > *rightstart
5949 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5950 --*rightstop;
5951
5952 input_line_pointer = s;
5953
5954 return 1;
5955 }
5956
5957 #define MCC(b1, b2) (((b1) << 8) | (b2))
5958
5959 /* Swap the sense of a condition. This changes the condition so that
5960 it generates the same result when the operands are swapped. */
5961
5962 static int
5963 swap_mri_condition (int cc)
5964 {
5965 switch (cc)
5966 {
5967 case MCC ('h', 'i'): return MCC ('c', 's');
5968 case MCC ('l', 's'): return MCC ('c', 'c');
5969 /* <HS> is an alias for <CC>. */
5970 case MCC ('h', 's'):
5971 case MCC ('c', 'c'): return MCC ('l', 's');
5972 /* <LO> is an alias for <CS>. */
5973 case MCC ('l', 'o'):
5974 case MCC ('c', 's'): return MCC ('h', 'i');
5975 case MCC ('p', 'l'): return MCC ('m', 'i');
5976 case MCC ('m', 'i'): return MCC ('p', 'l');
5977 case MCC ('g', 'e'): return MCC ('l', 'e');
5978 case MCC ('l', 't'): return MCC ('g', 't');
5979 case MCC ('g', 't'): return MCC ('l', 't');
5980 case MCC ('l', 'e'): return MCC ('g', 'e');
5981 /* Issue a warning for conditions we can not swap. */
5982 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
5983 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
5984 case MCC ('v', 'c'):
5985 case MCC ('v', 's'):
5986 default :
5987 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
5988 (char) (cc >> 8), (char) (cc));
5989 break;
5990 }
5991 return cc;
5992 }
5993
5994 /* Reverse the sense of a condition. */
5995
5996 static int
5997 reverse_mri_condition (int cc)
5998 {
5999 switch (cc)
6000 {
6001 case MCC ('h', 'i'): return MCC ('l', 's');
6002 case MCC ('l', 's'): return MCC ('h', 'i');
6003 /* <HS> is an alias for <CC> */
6004 case MCC ('h', 's'): return MCC ('l', 'o');
6005 case MCC ('c', 'c'): return MCC ('c', 's');
6006 /* <LO> is an alias for <CS> */
6007 case MCC ('l', 'o'): return MCC ('h', 's');
6008 case MCC ('c', 's'): return MCC ('c', 'c');
6009 case MCC ('n', 'e'): return MCC ('e', 'q');
6010 case MCC ('e', 'q'): return MCC ('n', 'e');
6011 case MCC ('v', 'c'): return MCC ('v', 's');
6012 case MCC ('v', 's'): return MCC ('v', 'c');
6013 case MCC ('p', 'l'): return MCC ('m', 'i');
6014 case MCC ('m', 'i'): return MCC ('p', 'l');
6015 case MCC ('g', 'e'): return MCC ('l', 't');
6016 case MCC ('l', 't'): return MCC ('g', 'e');
6017 case MCC ('g', 't'): return MCC ('l', 'e');
6018 case MCC ('l', 'e'): return MCC ('g', 't');
6019 }
6020 return cc;
6021 }
6022
6023 /* Build an MRI structured control expression. This generates test
6024 and branch instructions. It goes to TRUELAB if the condition is
6025 true, and to FALSELAB if the condition is false. Exactly one of
6026 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6027 is the size qualifier for the expression. EXTENT is the size to
6028 use for the branch. */
6029
6030 static void
6031 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6032 char *rightstart, char *rightstop,
6033 const char *truelab, const char *falselab,
6034 int extent)
6035 {
6036 char *buf;
6037 char *s;
6038
6039 if (leftstart != NULL)
6040 {
6041 struct m68k_op leftop, rightop;
6042 char c;
6043
6044 /* Swap the compare operands, if necessary, to produce a legal
6045 m68k compare instruction. Comparing a register operand with
6046 a non-register operand requires the register to be on the
6047 right (cmp, cmpa). Comparing an immediate value with
6048 anything requires the immediate value to be on the left
6049 (cmpi). */
6050
6051 c = *leftstop;
6052 *leftstop = '\0';
6053 (void) m68k_ip_op (leftstart, &leftop);
6054 *leftstop = c;
6055
6056 c = *rightstop;
6057 *rightstop = '\0';
6058 (void) m68k_ip_op (rightstart, &rightop);
6059 *rightstop = c;
6060
6061 if (rightop.mode == IMMED
6062 || ((leftop.mode == DREG || leftop.mode == AREG)
6063 && (rightop.mode != DREG && rightop.mode != AREG)))
6064 {
6065 char *temp;
6066
6067 /* Correct conditional handling:
6068 if #1 <lt> d0 then ;means if (1 < d0)
6069 ...
6070 endi
6071
6072 should assemble to:
6073
6074 cmp #1,d0 if we do *not* swap the operands
6075 bgt true we need the swapped condition!
6076 ble false
6077 true:
6078 ...
6079 false:
6080 */
6081 temp = leftstart;
6082 leftstart = rightstart;
6083 rightstart = temp;
6084 temp = leftstop;
6085 leftstop = rightstop;
6086 rightstop = temp;
6087 }
6088 else
6089 {
6090 cc = swap_mri_condition (cc);
6091 }
6092 }
6093
6094 if (truelab == NULL)
6095 {
6096 cc = reverse_mri_condition (cc);
6097 truelab = falselab;
6098 }
6099
6100 if (leftstart != NULL)
6101 {
6102 buf = (char *) xmalloc (20
6103 + (leftstop - leftstart)
6104 + (rightstop - rightstart));
6105 s = buf;
6106 *s++ = 'c';
6107 *s++ = 'm';
6108 *s++ = 'p';
6109 if (qual != '\0')
6110 *s++ = TOLOWER (qual);
6111 *s++ = ' ';
6112 memcpy (s, leftstart, leftstop - leftstart);
6113 s += leftstop - leftstart;
6114 *s++ = ',';
6115 memcpy (s, rightstart, rightstop - rightstart);
6116 s += rightstop - rightstart;
6117 *s = '\0';
6118 mri_assemble (buf);
6119 free (buf);
6120 }
6121
6122 buf = (char *) xmalloc (20 + strlen (truelab));
6123 s = buf;
6124 *s++ = 'b';
6125 *s++ = cc >> 8;
6126 *s++ = cc & 0xff;
6127 if (extent != '\0')
6128 *s++ = TOLOWER (extent);
6129 *s++ = ' ';
6130 strcpy (s, truelab);
6131 mri_assemble (buf);
6132 free (buf);
6133 }
6134
6135 /* Parse an MRI structured control expression. This generates test
6136 and branch instructions. STOP is where the expression ends. It
6137 goes to TRUELAB if the condition is true, and to FALSELAB if the
6138 condition is false. Exactly one of TRUELAB and FALSELAB will be
6139 NULL, meaning to fall through. QUAL is the size qualifier for the
6140 expression. EXTENT is the size to use for the branch. */
6141
6142 static void
6143 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6144 const char *falselab, int extent)
6145 {
6146 int c;
6147 int cc;
6148 char *leftstart;
6149 char *leftstop;
6150 char *rightstart;
6151 char *rightstop;
6152
6153 c = *stop;
6154 *stop = '\0';
6155
6156 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6157 &rightstart, &rightstop))
6158 {
6159 *stop = c;
6160 return;
6161 }
6162
6163 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6164 {
6165 const char *flab;
6166
6167 if (falselab != NULL)
6168 flab = falselab;
6169 else
6170 flab = mri_control_label ();
6171
6172 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6173 rightstop, (const char *) NULL, flab, extent);
6174
6175 input_line_pointer += 3;
6176 if (*input_line_pointer != '.'
6177 || input_line_pointer[1] == '\0')
6178 qual = '\0';
6179 else
6180 {
6181 qual = input_line_pointer[1];
6182 input_line_pointer += 2;
6183 }
6184
6185 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6186 &rightstart, &rightstop))
6187 {
6188 *stop = c;
6189 return;
6190 }
6191
6192 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6193 rightstop, truelab, falselab, extent);
6194
6195 if (falselab == NULL)
6196 colon (flab);
6197 }
6198 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6199 {
6200 const char *tlab;
6201
6202 if (truelab != NULL)
6203 tlab = truelab;
6204 else
6205 tlab = mri_control_label ();
6206
6207 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6208 rightstop, tlab, (const char *) NULL, extent);
6209
6210 input_line_pointer += 2;
6211 if (*input_line_pointer != '.'
6212 || input_line_pointer[1] == '\0')
6213 qual = '\0';
6214 else
6215 {
6216 qual = input_line_pointer[1];
6217 input_line_pointer += 2;
6218 }
6219
6220 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6221 &rightstart, &rightstop))
6222 {
6223 *stop = c;
6224 return;
6225 }
6226
6227 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6228 rightstop, truelab, falselab, extent);
6229
6230 if (truelab == NULL)
6231 colon (tlab);
6232 }
6233 else
6234 {
6235 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6236 rightstop, truelab, falselab, extent);
6237 }
6238
6239 *stop = c;
6240 if (input_line_pointer != stop)
6241 as_bad (_("syntax error in structured control directive"));
6242 }
6243
6244 /* Handle the MRI IF pseudo-op. This may be a structured control
6245 directive, or it may be a regular assembler conditional, depending
6246 on its operands. */
6247
6248 static void
6249 s_mri_if (int qual)
6250 {
6251 char *s;
6252 int c;
6253 struct mri_control_info *n;
6254
6255 /* A structured control directive must end with THEN with an
6256 optional qualifier. */
6257 s = input_line_pointer;
6258 /* We only accept '*' as introduction of comments if preceded by white space
6259 or at first column of a line (I think this can't actually happen here?)
6260 This is important when assembling:
6261 if d0 <ne> 12(a0,d0*2) then
6262 if d0 <ne> #CONST*20 then. */
6263 while (! (is_end_of_line[(unsigned char) *s]
6264 || (flag_mri
6265 && *s == '*'
6266 && (s == input_line_pointer
6267 || *(s-1) == ' '
6268 || *(s-1) == '\t'))))
6269 ++s;
6270 --s;
6271 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6272 --s;
6273
6274 if (s - input_line_pointer > 1
6275 && s[-1] == '.')
6276 s -= 2;
6277
6278 if (s - input_line_pointer < 3
6279 || strncasecmp (s - 3, "THEN", 4) != 0)
6280 {
6281 if (qual != '\0')
6282 {
6283 as_bad (_("missing then"));
6284 ignore_rest_of_line ();
6285 return;
6286 }
6287
6288 /* It's a conditional. */
6289 s_if (O_ne);
6290 return;
6291 }
6292
6293 /* Since this might be a conditional if, this pseudo-op will be
6294 called even if we are supported to be ignoring input. Double
6295 check now. Clobber *input_line_pointer so that ignore_input
6296 thinks that this is not a special pseudo-op. */
6297 c = *input_line_pointer;
6298 *input_line_pointer = 0;
6299 if (ignore_input ())
6300 {
6301 *input_line_pointer = c;
6302 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6303 ++input_line_pointer;
6304 demand_empty_rest_of_line ();
6305 return;
6306 }
6307 *input_line_pointer = c;
6308
6309 n = push_mri_control (mri_if);
6310
6311 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6312 n->next, s[1] == '.' ? s[2] : '\0');
6313
6314 if (s[1] == '.')
6315 input_line_pointer = s + 3;
6316 else
6317 input_line_pointer = s + 1;
6318
6319 if (flag_mri)
6320 {
6321 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6322 ++input_line_pointer;
6323 }
6324
6325 demand_empty_rest_of_line ();
6326 }
6327
6328 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6329 structured IF, associate the ELSE with the IF. Otherwise, assume
6330 it is a conditional else. */
6331
6332 static void
6333 s_mri_else (int qual)
6334 {
6335 int c;
6336 char *buf;
6337 char q[2];
6338
6339 if (qual == '\0'
6340 && (mri_control_stack == NULL
6341 || mri_control_stack->type != mri_if
6342 || mri_control_stack->else_seen))
6343 {
6344 s_else (0);
6345 return;
6346 }
6347
6348 c = *input_line_pointer;
6349 *input_line_pointer = 0;
6350 if (ignore_input ())
6351 {
6352 *input_line_pointer = c;
6353 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6354 ++input_line_pointer;
6355 demand_empty_rest_of_line ();
6356 return;
6357 }
6358 *input_line_pointer = c;
6359
6360 if (mri_control_stack == NULL
6361 || mri_control_stack->type != mri_if
6362 || mri_control_stack->else_seen)
6363 {
6364 as_bad (_("else without matching if"));
6365 ignore_rest_of_line ();
6366 return;
6367 }
6368
6369 mri_control_stack->else_seen = 1;
6370
6371 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6372 q[0] = TOLOWER (qual);
6373 q[1] = '\0';
6374 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6375 mri_assemble (buf);
6376 free (buf);
6377
6378 colon (mri_control_stack->next);
6379
6380 if (flag_mri)
6381 {
6382 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6383 ++input_line_pointer;
6384 }
6385
6386 demand_empty_rest_of_line ();
6387 }
6388
6389 /* Handle the MRI ENDI pseudo-op. */
6390
6391 static void
6392 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6393 {
6394 if (mri_control_stack == NULL
6395 || mri_control_stack->type != mri_if)
6396 {
6397 as_bad (_("endi without matching if"));
6398 ignore_rest_of_line ();
6399 return;
6400 }
6401
6402 /* ignore_input will not return true for ENDI, so we don't need to
6403 worry about checking it again here. */
6404
6405 if (! mri_control_stack->else_seen)
6406 colon (mri_control_stack->next);
6407 colon (mri_control_stack->bottom);
6408
6409 pop_mri_control ();
6410
6411 if (flag_mri)
6412 {
6413 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6414 ++input_line_pointer;
6415 }
6416
6417 demand_empty_rest_of_line ();
6418 }
6419
6420 /* Handle the MRI BREAK pseudo-op. */
6421
6422 static void
6423 s_mri_break (int extent)
6424 {
6425 struct mri_control_info *n;
6426 char *buf;
6427 char ex[2];
6428
6429 n = mri_control_stack;
6430 while (n != NULL
6431 && n->type != mri_for
6432 && n->type != mri_repeat
6433 && n->type != mri_while)
6434 n = n->outer;
6435 if (n == NULL)
6436 {
6437 as_bad (_("break outside of structured loop"));
6438 ignore_rest_of_line ();
6439 return;
6440 }
6441
6442 buf = (char *) xmalloc (20 + strlen (n->bottom));
6443 ex[0] = TOLOWER (extent);
6444 ex[1] = '\0';
6445 sprintf (buf, "bra%s %s", ex, n->bottom);
6446 mri_assemble (buf);
6447 free (buf);
6448
6449 if (flag_mri)
6450 {
6451 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6452 ++input_line_pointer;
6453 }
6454
6455 demand_empty_rest_of_line ();
6456 }
6457
6458 /* Handle the MRI NEXT pseudo-op. */
6459
6460 static void
6461 s_mri_next (int extent)
6462 {
6463 struct mri_control_info *n;
6464 char *buf;
6465 char ex[2];
6466
6467 n = mri_control_stack;
6468 while (n != NULL
6469 && n->type != mri_for
6470 && n->type != mri_repeat
6471 && n->type != mri_while)
6472 n = n->outer;
6473 if (n == NULL)
6474 {
6475 as_bad (_("next outside of structured loop"));
6476 ignore_rest_of_line ();
6477 return;
6478 }
6479
6480 buf = (char *) xmalloc (20 + strlen (n->next));
6481 ex[0] = TOLOWER (extent);
6482 ex[1] = '\0';
6483 sprintf (buf, "bra%s %s", ex, n->next);
6484 mri_assemble (buf);
6485 free (buf);
6486
6487 if (flag_mri)
6488 {
6489 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6490 ++input_line_pointer;
6491 }
6492
6493 demand_empty_rest_of_line ();
6494 }
6495
6496 /* Handle the MRI FOR pseudo-op. */
6497
6498 static void
6499 s_mri_for (int qual)
6500 {
6501 const char *varstart, *varstop;
6502 const char *initstart, *initstop;
6503 const char *endstart, *endstop;
6504 const char *bystart, *bystop;
6505 int up;
6506 int by;
6507 int extent;
6508 struct mri_control_info *n;
6509 char *buf;
6510 char *s;
6511 char ex[2];
6512
6513 /* The syntax is
6514 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6515 */
6516
6517 SKIP_WHITESPACE ();
6518 varstart = input_line_pointer;
6519
6520 /* Look for the '='. */
6521 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6522 && *input_line_pointer != '=')
6523 ++input_line_pointer;
6524 if (*input_line_pointer != '=')
6525 {
6526 as_bad (_("missing ="));
6527 ignore_rest_of_line ();
6528 return;
6529 }
6530
6531 varstop = input_line_pointer;
6532 if (varstop > varstart
6533 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6534 --varstop;
6535
6536 ++input_line_pointer;
6537
6538 initstart = input_line_pointer;
6539
6540 /* Look for TO or DOWNTO. */
6541 up = 1;
6542 initstop = NULL;
6543 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6544 {
6545 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6546 && ! is_part_of_name (input_line_pointer[2]))
6547 {
6548 initstop = input_line_pointer;
6549 input_line_pointer += 2;
6550 break;
6551 }
6552 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6553 && ! is_part_of_name (input_line_pointer[6]))
6554 {
6555 initstop = input_line_pointer;
6556 up = 0;
6557 input_line_pointer += 6;
6558 break;
6559 }
6560 ++input_line_pointer;
6561 }
6562 if (initstop == NULL)
6563 {
6564 as_bad (_("missing to or downto"));
6565 ignore_rest_of_line ();
6566 return;
6567 }
6568 if (initstop > initstart
6569 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6570 --initstop;
6571
6572 SKIP_WHITESPACE ();
6573 endstart = input_line_pointer;
6574
6575 /* Look for BY or DO. */
6576 by = 0;
6577 endstop = NULL;
6578 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6579 {
6580 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6581 && ! is_part_of_name (input_line_pointer[2]))
6582 {
6583 endstop = input_line_pointer;
6584 by = 1;
6585 input_line_pointer += 2;
6586 break;
6587 }
6588 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6589 && (input_line_pointer[2] == '.'
6590 || ! is_part_of_name (input_line_pointer[2])))
6591 {
6592 endstop = input_line_pointer;
6593 input_line_pointer += 2;
6594 break;
6595 }
6596 ++input_line_pointer;
6597 }
6598 if (endstop == NULL)
6599 {
6600 as_bad (_("missing do"));
6601 ignore_rest_of_line ();
6602 return;
6603 }
6604 if (endstop > endstart
6605 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6606 --endstop;
6607
6608 if (! by)
6609 {
6610 bystart = "#1";
6611 bystop = bystart + 2;
6612 }
6613 else
6614 {
6615 SKIP_WHITESPACE ();
6616 bystart = input_line_pointer;
6617
6618 /* Look for DO. */
6619 bystop = NULL;
6620 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6621 {
6622 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6623 && (input_line_pointer[2] == '.'
6624 || ! is_part_of_name (input_line_pointer[2])))
6625 {
6626 bystop = input_line_pointer;
6627 input_line_pointer += 2;
6628 break;
6629 }
6630 ++input_line_pointer;
6631 }
6632 if (bystop == NULL)
6633 {
6634 as_bad (_("missing do"));
6635 ignore_rest_of_line ();
6636 return;
6637 }
6638 if (bystop > bystart
6639 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6640 --bystop;
6641 }
6642
6643 if (*input_line_pointer != '.')
6644 extent = '\0';
6645 else
6646 {
6647 extent = input_line_pointer[1];
6648 input_line_pointer += 2;
6649 }
6650
6651 /* We have fully parsed the FOR operands. Now build the loop. */
6652 n = push_mri_control (mri_for);
6653
6654 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6655
6656 /* Move init,var. */
6657 s = buf;
6658 *s++ = 'm';
6659 *s++ = 'o';
6660 *s++ = 'v';
6661 *s++ = 'e';
6662 if (qual != '\0')
6663 *s++ = TOLOWER (qual);
6664 *s++ = ' ';
6665 memcpy (s, initstart, initstop - initstart);
6666 s += initstop - initstart;
6667 *s++ = ',';
6668 memcpy (s, varstart, varstop - varstart);
6669 s += varstop - varstart;
6670 *s = '\0';
6671 mri_assemble (buf);
6672
6673 colon (n->top);
6674
6675 /* cmp end,var. */
6676 s = buf;
6677 *s++ = 'c';
6678 *s++ = 'm';
6679 *s++ = 'p';
6680 if (qual != '\0')
6681 *s++ = TOLOWER (qual);
6682 *s++ = ' ';
6683 memcpy (s, endstart, endstop - endstart);
6684 s += endstop - endstart;
6685 *s++ = ',';
6686 memcpy (s, varstart, varstop - varstart);
6687 s += varstop - varstart;
6688 *s = '\0';
6689 mri_assemble (buf);
6690
6691 /* bcc bottom. */
6692 ex[0] = TOLOWER (extent);
6693 ex[1] = '\0';
6694 if (up)
6695 sprintf (buf, "blt%s %s", ex, n->bottom);
6696 else
6697 sprintf (buf, "bgt%s %s", ex, n->bottom);
6698 mri_assemble (buf);
6699
6700 /* Put together the add or sub instruction used by ENDF. */
6701 s = buf;
6702 if (up)
6703 strcpy (s, "add");
6704 else
6705 strcpy (s, "sub");
6706 s += 3;
6707 if (qual != '\0')
6708 *s++ = TOLOWER (qual);
6709 *s++ = ' ';
6710 memcpy (s, bystart, bystop - bystart);
6711 s += bystop - bystart;
6712 *s++ = ',';
6713 memcpy (s, varstart, varstop - varstart);
6714 s += varstop - varstart;
6715 *s = '\0';
6716 n->incr = buf;
6717
6718 if (flag_mri)
6719 {
6720 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6721 ++input_line_pointer;
6722 }
6723
6724 demand_empty_rest_of_line ();
6725 }
6726
6727 /* Handle the MRI ENDF pseudo-op. */
6728
6729 static void
6730 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
6731 {
6732 if (mri_control_stack == NULL
6733 || mri_control_stack->type != mri_for)
6734 {
6735 as_bad (_("endf without for"));
6736 ignore_rest_of_line ();
6737 return;
6738 }
6739
6740 colon (mri_control_stack->next);
6741
6742 mri_assemble (mri_control_stack->incr);
6743
6744 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6745 mri_assemble (mri_control_stack->incr);
6746
6747 free (mri_control_stack->incr);
6748
6749 colon (mri_control_stack->bottom);
6750
6751 pop_mri_control ();
6752
6753 if (flag_mri)
6754 {
6755 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6756 ++input_line_pointer;
6757 }
6758
6759 demand_empty_rest_of_line ();
6760 }
6761
6762 /* Handle the MRI REPEAT pseudo-op. */
6763
6764 static void
6765 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
6766 {
6767 struct mri_control_info *n;
6768
6769 n = push_mri_control (mri_repeat);
6770 colon (n->top);
6771 if (flag_mri)
6772 {
6773 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6774 ++input_line_pointer;
6775 }
6776 demand_empty_rest_of_line ();
6777 }
6778
6779 /* Handle the MRI UNTIL pseudo-op. */
6780
6781 static void
6782 s_mri_until (int qual)
6783 {
6784 char *s;
6785
6786 if (mri_control_stack == NULL
6787 || mri_control_stack->type != mri_repeat)
6788 {
6789 as_bad (_("until without repeat"));
6790 ignore_rest_of_line ();
6791 return;
6792 }
6793
6794 colon (mri_control_stack->next);
6795
6796 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6797 ;
6798
6799 parse_mri_control_expression (s, qual, (const char *) NULL,
6800 mri_control_stack->top, '\0');
6801
6802 colon (mri_control_stack->bottom);
6803
6804 input_line_pointer = s;
6805
6806 pop_mri_control ();
6807
6808 if (flag_mri)
6809 {
6810 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6811 ++input_line_pointer;
6812 }
6813
6814 demand_empty_rest_of_line ();
6815 }
6816
6817 /* Handle the MRI WHILE pseudo-op. */
6818
6819 static void
6820 s_mri_while (int qual)
6821 {
6822 char *s;
6823
6824 struct mri_control_info *n;
6825
6826 s = input_line_pointer;
6827 /* We only accept '*' as introduction of comments if preceded by white space
6828 or at first column of a line (I think this can't actually happen here?)
6829 This is important when assembling:
6830 while d0 <ne> 12(a0,d0*2) do
6831 while d0 <ne> #CONST*20 do. */
6832 while (! (is_end_of_line[(unsigned char) *s]
6833 || (flag_mri
6834 && *s == '*'
6835 && (s == input_line_pointer
6836 || *(s-1) == ' '
6837 || *(s-1) == '\t'))))
6838 s++;
6839 --s;
6840 while (*s == ' ' || *s == '\t')
6841 --s;
6842 if (s - input_line_pointer > 1
6843 && s[-1] == '.')
6844 s -= 2;
6845 if (s - input_line_pointer < 2
6846 || strncasecmp (s - 1, "DO", 2) != 0)
6847 {
6848 as_bad (_("missing do"));
6849 ignore_rest_of_line ();
6850 return;
6851 }
6852
6853 n = push_mri_control (mri_while);
6854
6855 colon (n->next);
6856
6857 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6858 s[1] == '.' ? s[2] : '\0');
6859
6860 input_line_pointer = s + 1;
6861 if (*input_line_pointer == '.')
6862 input_line_pointer += 2;
6863
6864 if (flag_mri)
6865 {
6866 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6867 ++input_line_pointer;
6868 }
6869
6870 demand_empty_rest_of_line ();
6871 }
6872
6873 /* Handle the MRI ENDW pseudo-op. */
6874
6875 static void
6876 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
6877 {
6878 char *buf;
6879
6880 if (mri_control_stack == NULL
6881 || mri_control_stack->type != mri_while)
6882 {
6883 as_bad (_("endw without while"));
6884 ignore_rest_of_line ();
6885 return;
6886 }
6887
6888 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6889 sprintf (buf, "bra %s", mri_control_stack->next);
6890 mri_assemble (buf);
6891 free (buf);
6892
6893 colon (mri_control_stack->bottom);
6894
6895 pop_mri_control ();
6896
6897 if (flag_mri)
6898 {
6899 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6900 ++input_line_pointer;
6901 }
6902
6903 demand_empty_rest_of_line ();
6904 }
6905 \f
6906 /* Parse a .cpu directive. */
6907
6908 static void
6909 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
6910 {
6911 char saved_char;
6912 char *name;
6913
6914 if (initialized)
6915 {
6916 as_bad (_("already assembled instructions"));
6917 ignore_rest_of_line ();
6918 return;
6919 }
6920
6921 name = input_line_pointer;
6922 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
6923 input_line_pointer++;
6924 saved_char = *input_line_pointer;
6925 *input_line_pointer = 0;
6926
6927 m68k_set_cpu (name, 1, 0);
6928
6929 *input_line_pointer = saved_char;
6930 demand_empty_rest_of_line ();
6931 return;
6932 }
6933
6934 /* Parse a .arch directive. */
6935
6936 static void
6937 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
6938 {
6939 char saved_char;
6940 char *name;
6941
6942 if (initialized)
6943 {
6944 as_bad (_("already assembled instructions"));
6945 ignore_rest_of_line ();
6946 return;
6947 }
6948
6949 name = input_line_pointer;
6950 while (*input_line_pointer && *input_line_pointer != ','
6951 && !ISSPACE (*input_line_pointer))
6952 input_line_pointer++;
6953 saved_char = *input_line_pointer;
6954 *input_line_pointer = 0;
6955
6956 if (m68k_set_arch (name, 1, 0))
6957 {
6958 /* Scan extensions. */
6959 do
6960 {
6961 *input_line_pointer++ = saved_char;
6962 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
6963 break;
6964 name = input_line_pointer;
6965 while (*input_line_pointer && *input_line_pointer != ','
6966 && !ISSPACE (*input_line_pointer))
6967 input_line_pointer++;
6968 saved_char = *input_line_pointer;
6969 *input_line_pointer = 0;
6970 }
6971 while (m68k_set_extension (name, 1, 0));
6972 }
6973
6974 *input_line_pointer = saved_char;
6975 demand_empty_rest_of_line ();
6976 return;
6977 }
6978 \f
6979 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
6980 if none is found, the caller is responsible for emitting an error
6981 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
6982 cpu name, if it begins with a '6' (possibly skipping an intervening
6983 'c'. We also allow a 'c' in the same place. if NEGATED is
6984 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
6985 the option is indeed negated. */
6986
6987 static const struct m68k_cpu *
6988 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
6989 int allow_m, int *negated)
6990 {
6991 /* allow negated value? */
6992 if (negated)
6993 {
6994 *negated = 0;
6995
6996 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6997 {
6998 arg += 3;
6999 *negated = 1;
7000 }
7001 }
7002
7003 /* Remove 'm' or 'mc' prefix from 68k variants. */
7004 if (allow_m)
7005 {
7006 if (arg[0] == 'm')
7007 {
7008 if (arg[1] == '6')
7009 arg += 1;
7010 else if (arg[1] == 'c' && arg[2] == '6')
7011 arg += 2;
7012 }
7013 }
7014 else if (arg[0] == 'c' && arg[1] == '6')
7015 arg += 1;
7016
7017 for (; table->name; table++)
7018 if (!strcmp (arg, table->name))
7019 {
7020 if (table->alias < -1 || table->alias > 1)
7021 as_bad (_("`%s' is deprecated, use `%s'"),
7022 table->name, table[table->alias < 0 ? 1 : -1].name);
7023 return table;
7024 }
7025 return 0;
7026 }
7027
7028 /* Set the cpu, issuing errors if it is unrecognized, or invalid */
7029
7030 static int
7031 m68k_set_cpu (char const *name, int allow_m, int silent)
7032 {
7033 const struct m68k_cpu *cpu;
7034
7035 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7036
7037 if (!cpu)
7038 {
7039 if (!silent)
7040 as_bad (_("cpu `%s' unrecognized"), name);
7041 return 0;
7042 }
7043
7044 if (selected_cpu && selected_cpu != cpu)
7045 {
7046 as_bad (_("already selected `%s' processor"),
7047 selected_cpu->name);
7048 return 0;
7049 }
7050 selected_cpu = cpu;
7051 return 1;
7052 }
7053
7054 /* Set the architecture, issuing errors if it is unrecognized, or invalid */
7055
7056 static int
7057 m68k_set_arch (char const *name, int allow_m, int silent)
7058 {
7059 const struct m68k_cpu *arch;
7060
7061 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7062
7063 if (!arch)
7064 {
7065 if (!silent)
7066 as_bad (_("architecture `%s' unrecognized"), name);
7067 return 0;
7068 }
7069
7070 if (selected_arch && selected_arch != arch)
7071 {
7072 as_bad (_("already selected `%s' architecture"),
7073 selected_arch->name);
7074 return 0;
7075 }
7076
7077 selected_arch = arch;
7078 return 1;
7079 }
7080
7081 /* Set the architecture extension, issuing errors if it is
7082 unrecognized, or invalid */
7083
7084 static int
7085 m68k_set_extension (char const *name, int allow_m, int silent)
7086 {
7087 int negated;
7088 const struct m68k_cpu *ext;
7089
7090 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7091
7092 if (!ext)
7093 {
7094 if (!silent)
7095 as_bad (_("extension `%s' unrecognized"), name);
7096 return 0;
7097 }
7098
7099 if (negated)
7100 not_current_architecture |= ext->arch;
7101 else
7102 current_architecture |= ext->arch;
7103 return 1;
7104 }
7105
7106 /* md_parse_option
7107 Invocation line includes a switch not recognized by the base assembler.
7108 */
7109
7110 #ifdef OBJ_ELF
7111 const char *md_shortopts = "lSA:m:kQ:V";
7112 #else
7113 const char *md_shortopts = "lSA:m:k";
7114 #endif
7115
7116 struct option md_longopts[] = {
7117 #define OPTION_PIC (OPTION_MD_BASE)
7118 {"pic", no_argument, NULL, OPTION_PIC},
7119 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7120 {"register-prefix-optional", no_argument, NULL,
7121 OPTION_REGISTER_PREFIX_OPTIONAL},
7122 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7123 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7124 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7125 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7126 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7127 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7128 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7129 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7130 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7131 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7132 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7133 {"pcrel", no_argument, NULL, OPTION_PCREL},
7134 {NULL, no_argument, NULL, 0}
7135 };
7136 size_t md_longopts_size = sizeof (md_longopts);
7137
7138 int
7139 md_parse_option (int c, char *arg)
7140 {
7141 switch (c)
7142 {
7143 case 'l': /* -l means keep external to 2 bit offset
7144 rather than 16 bit one. */
7145 flag_short_refs = 1;
7146 break;
7147
7148 case 'S': /* -S means that jbsr's always turn into
7149 jsr's. */
7150 flag_long_jumps = 1;
7151 break;
7152
7153 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7154 branches into absolute jumps. */
7155 flag_keep_pcrel = 1;
7156 break;
7157
7158 case OPTION_PIC:
7159 case 'k':
7160 flag_want_pic = 1;
7161 break; /* -pic, Position Independent Code. */
7162
7163 case OPTION_REGISTER_PREFIX_OPTIONAL:
7164 flag_reg_prefix_optional = 1;
7165 reg_prefix_optional_seen = 1;
7166 break;
7167
7168 /* -V: SVR4 argument to print version ID. */
7169 case 'V':
7170 print_version_id ();
7171 break;
7172
7173 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7174 should be emitted or not. FIXME: Not implemented. */
7175 case 'Q':
7176 break;
7177
7178 case OPTION_BITWISE_OR:
7179 {
7180 char *n, *t;
7181 const char *s;
7182
7183 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7184 t = n;
7185 for (s = m68k_comment_chars; *s != '\0'; s++)
7186 if (*s != '|')
7187 *t++ = *s;
7188 *t = '\0';
7189 m68k_comment_chars = n;
7190 }
7191 break;
7192
7193 case OPTION_BASE_SIZE_DEFAULT_16:
7194 m68k_index_width_default = SIZE_WORD;
7195 break;
7196
7197 case OPTION_BASE_SIZE_DEFAULT_32:
7198 m68k_index_width_default = SIZE_LONG;
7199 break;
7200
7201 case OPTION_DISP_SIZE_DEFAULT_16:
7202 m68k_rel32 = 0;
7203 m68k_rel32_from_cmdline = 1;
7204 break;
7205
7206 case OPTION_DISP_SIZE_DEFAULT_32:
7207 m68k_rel32 = 1;
7208 m68k_rel32_from_cmdline = 1;
7209 break;
7210
7211 case 'A':
7212 #if WARN_DEPRECATED
7213 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7214 arg, arg));
7215 #endif
7216 /* Intentional fall-through. */
7217 case 'm':
7218 if (!strncmp (arg, "arch=", 5))
7219 m68k_set_arch (arg + 5, 1, 0);
7220 else if (!strncmp (arg, "cpu=", 4))
7221 m68k_set_cpu (arg + 4, 1, 0);
7222 else if (m68k_set_extension (arg, 0, 1))
7223 ;
7224 else if (m68k_set_arch (arg, 0, 1))
7225 ;
7226 else if (m68k_set_cpu (arg, 0, 1))
7227 ;
7228 else
7229 return 0;
7230 break;
7231
7232 default:
7233 return 0;
7234 }
7235
7236 return 1;
7237 }
7238
7239 /* Setup tables from the selected arch and/or cpu */
7240
7241 static void
7242 m68k_init_arch (void)
7243 {
7244 if (not_current_architecture & current_architecture)
7245 {
7246 as_bad (_("architecture features both enabled and disabled"));
7247 not_current_architecture &= ~current_architecture;
7248 }
7249 if (selected_arch)
7250 {
7251 current_architecture |= selected_arch->arch;
7252 control_regs = selected_arch->control_regs;
7253 }
7254 else
7255 current_architecture |= selected_cpu->arch;
7256
7257 current_architecture &= ~not_current_architecture;
7258
7259 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7260 {
7261 /* Determine which float is really meant. */
7262 if (current_architecture & (m68k_mask & ~m68881))
7263 current_architecture ^= cfloat;
7264 else
7265 current_architecture ^= m68881;
7266 }
7267
7268 if (selected_cpu)
7269 {
7270 control_regs = selected_cpu->control_regs;
7271 if (current_architecture & ~selected_cpu->arch)
7272 {
7273 as_bad (_("selected processor does not have all features of selected architecture"));
7274 current_architecture
7275 = selected_cpu->arch & ~not_current_architecture;
7276 }
7277 }
7278
7279 if ((current_architecture & m68k_mask)
7280 && (current_architecture & ~m68k_mask))
7281 {
7282 as_bad (_ ("m68k and cf features both selected"));
7283 if (current_architecture & m68k_mask)
7284 current_architecture &= m68k_mask;
7285 else
7286 current_architecture &= ~m68k_mask;
7287 }
7288
7289 /* Permit m68881 specification with all cpus; those that can't work
7290 with a coprocessor could be doing emulation. */
7291 if (current_architecture & m68851)
7292 {
7293 if (current_architecture & m68040)
7294 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7295 }
7296 /* What other incompatibilities could we check for? */
7297
7298 if (cpu_of_arch (current_architecture) < m68020
7299 || arch_coldfire_p (current_architecture))
7300 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7301
7302 initialized = 1;
7303 }
7304
7305 void
7306 md_show_usage (FILE *stream)
7307 {
7308 const char *default_cpu = TARGET_CPU;
7309 int i;
7310 unsigned int default_arch;
7311
7312 /* Get the canonical name for the default target CPU. */
7313 if (*default_cpu == 'm')
7314 default_cpu++;
7315 for (i = 0; m68k_cpus[i].name; i++)
7316 {
7317 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7318 {
7319 default_arch = m68k_cpus[i].arch;
7320 while (m68k_cpus[i].alias > 0)
7321 i--;
7322 while (m68k_cpus[i].alias < 0)
7323 i++;
7324 default_cpu = m68k_cpus[i].name;
7325 }
7326 }
7327
7328 fprintf (stream, _("\
7329 -march=<arch> set architecture\n\
7330 -mcpu=<cpu> set cpu [default %s]\n\
7331 "), default_cpu);
7332 for (i = 0; m68k_extensions[i].name; i++)
7333 fprintf (stream, _("\
7334 -m[no-]%-16s enable/disable%s architecture extension\n\
7335 "), m68k_extensions[i].name,
7336 m68k_extensions[i].alias > 0 ? " ColdFire"
7337 : m68k_extensions[i].alias < 0 ? " m68k" : "");
7338
7339 fprintf (stream, _("\
7340 -l use 1 word for refs to undefined symbols [default 2]\n\
7341 -pic, -k generate position independent code\n\
7342 -S turn jbsr into jsr\n\
7343 --pcrel never turn PC-relative branches into absolute jumps\n\
7344 --register-prefix-optional\n\
7345 recognize register names without prefix character\n\
7346 --bitwise-or do not treat `|' as a comment character\n\
7347 --base-size-default-16 base reg without size is 16 bits\n\
7348 --base-size-default-32 base reg without size is 32 bits (default)\n\
7349 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7350 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7351 "));
7352
7353 fprintf (stream, _("Architecture variants are: "));
7354 for (i = 0; m68k_archs[i].name; i++)
7355 {
7356 if (i)
7357 fprintf (stream, " | ");
7358 fprintf (stream, m68k_archs[i].name);
7359 }
7360 fprintf (stream, "\n");
7361
7362 fprintf (stream, _("Processor variants are: "));
7363 for (i = 0; m68k_cpus[i].name; i++)
7364 {
7365 if (i)
7366 fprintf (stream, " | ");
7367 fprintf (stream, m68k_cpus[i].name);
7368 }
7369 fprintf (stream, _("\n"));
7370 }
7371 \f
7372 #ifdef TEST2
7373
7374 /* TEST2: Test md_assemble() */
7375 /* Warning, this routine probably doesn't work anymore. */
7376 int
7377 main (void)
7378 {
7379 struct m68k_it the_ins;
7380 char buf[120];
7381 char *cp;
7382 int n;
7383
7384 m68k_ip_begin ();
7385 for (;;)
7386 {
7387 if (!gets (buf) || !*buf)
7388 break;
7389 if (buf[0] == '|' || buf[1] == '.')
7390 continue;
7391 for (cp = buf; *cp; cp++)
7392 if (*cp == '\t')
7393 *cp = ' ';
7394 if (is_label (buf))
7395 continue;
7396 memset (&the_ins, '\0', sizeof (the_ins));
7397 m68k_ip (&the_ins, buf);
7398 if (the_ins.error)
7399 {
7400 printf (_("Error %s in %s\n"), the_ins.error, buf);
7401 }
7402 else
7403 {
7404 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7405 for (n = 0; n < the_ins.numo; n++)
7406 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7407 printf (" ");
7408 print_the_insn (&the_ins.opcode[0], stdout);
7409 (void) putchar ('\n');
7410 }
7411 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7412 {
7413 if (the_ins.operands[n].error)
7414 {
7415 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7416 continue;
7417 }
7418 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7419 the_ins.operands[n].reg);
7420 if (the_ins.operands[n].b_const)
7421 printf ("Constant: '%.*s', ",
7422 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7423 the_ins.operands[n].b_const);
7424 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7425 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7426 if (the_ins.operands[n].b_iadd)
7427 printf ("Iadd: '%.*s',",
7428 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7429 the_ins.operands[n].b_iadd);
7430 putchar ('\n');
7431 }
7432 }
7433 m68k_ip_end ();
7434 return 0;
7435 }
7436
7437 int
7438 is_label (char *str)
7439 {
7440 while (*str == ' ')
7441 str++;
7442 while (*str && *str != ' ')
7443 str++;
7444 if (str[-1] == ':' || str[1] == '=')
7445 return 1;
7446 return 0;
7447 }
7448
7449 #endif
7450
7451 /* Possible states for relaxation:
7452
7453 0 0 branch offset byte (bra, etc)
7454 0 1 word
7455 0 2 long
7456
7457 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7458 1 1 word
7459 1 2 long
7460
7461 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7462 2 1 word-long
7463 2 2 long-word
7464 2 3 long-long
7465
7466 */
7467
7468 /* We have no need to default values of symbols. */
7469
7470 symbolS *
7471 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7472 {
7473 return 0;
7474 }
7475
7476 /* Round up a section size to the appropriate boundary. */
7477 valueT
7478 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7479 {
7480 #ifdef OBJ_AOUT
7481 /* For a.out, force the section size to be aligned. If we don't do
7482 this, BFD will align it for us, but it will not write out the
7483 final bytes of the section. This may be a bug in BFD, but it is
7484 easier to fix it here since that is how the other a.out targets
7485 work. */
7486 int align;
7487
7488 align = bfd_get_section_alignment (stdoutput, segment);
7489 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7490 #endif
7491
7492 return size;
7493 }
7494
7495 /* Exactly what point is a PC-relative offset relative TO?
7496 On the 68k, it is relative to the address of the first extension
7497 word. The difference between the addresses of the offset and the
7498 first extension word is stored in fx_pcrel_adjust. */
7499 long
7500 md_pcrel_from (fixS *fixP)
7501 {
7502 int adjust;
7503
7504 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7505 sign extend the value here. */
7506 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7507 if (adjust == 64)
7508 adjust = -1;
7509 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7510 }
7511
7512 #ifdef OBJ_ELF
7513 void
7514 m68k_elf_final_processing (void)
7515 {
7516 unsigned flags = 0;
7517
7518 if (arch_coldfire_fpu (current_architecture))
7519 flags |= EF_M68K_CFV4E;
7520 /* Set file-specific flags if this is a cpu32 processor. */
7521 if (cpu_of_arch (current_architecture) & cpu32)
7522 flags |= EF_M68K_CPU32;
7523 else if ((cpu_of_arch (current_architecture) & m68000up)
7524 && !(cpu_of_arch (current_architecture) & m68020up))
7525 flags |= EF_M68K_M68000;
7526
7527 if (current_architecture & mcfisa_a)
7528 {
7529 static const unsigned isa_features[][2] =
7530 {
7531 {EF_M68K_ISA_A_NODIV, mcfisa_a},
7532 {EF_M68K_ISA_A, mcfisa_a|mcfhwdiv},
7533 {EF_M68K_ISA_A_PLUS,mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7534 {EF_M68K_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7535 {EF_M68K_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7536 {0,0},
7537 };
7538 static const unsigned mac_features[][2] =
7539 {
7540 {EF_M68K_MAC, mcfmac},
7541 {EF_M68K_EMAC, mcfemac},
7542 {0,0},
7543 };
7544 unsigned ix;
7545 unsigned pattern;
7546
7547 pattern = (current_architecture
7548 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfhwdiv|mcfusp));
7549 for (ix = 0; isa_features[ix][1]; ix++)
7550 {
7551 if (pattern == isa_features[ix][1])
7552 {
7553 flags |= isa_features[ix][0];
7554 break;
7555 }
7556 }
7557 if (!isa_features[ix][1])
7558 {
7559 cf_bad:
7560 as_warn (_("Not a defined coldfire architecture"));
7561 }
7562 else
7563 {
7564 if (current_architecture & cfloat)
7565 flags |= EF_M68K_FLOAT | EF_M68K_CFV4E;
7566
7567 pattern = current_architecture & (mcfmac|mcfemac);
7568 if (pattern)
7569 {
7570 for (ix = 0; mac_features[ix][1]; ix++)
7571 {
7572 if (pattern == mac_features[ix][1])
7573 {
7574 flags |= mac_features[ix][0];
7575 break;
7576 }
7577 }
7578 if (!mac_features[ix][1])
7579 goto cf_bad;
7580 }
7581 }
7582 }
7583 elf_elfheader (stdoutput)->e_flags |= flags;
7584 }
7585 #endif
7586
7587 int
7588 tc_m68k_regname_to_dw2regnum (const char *regname)
7589 {
7590 unsigned int regnum;
7591 static const char *const regnames[] =
7592 {
7593 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7594 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7595 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7596 "pc"
7597 };
7598
7599 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7600 if (strcmp (regname, regnames[regnum]) == 0)
7601 return regnum;
7602
7603 return -1;
7604 }
7605
7606 void
7607 tc_m68k_frame_initial_instructions (void)
7608 {
7609 static int sp_regno = -1;
7610
7611 if (sp_regno < 0)
7612 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7613
7614 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7615 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7616 }
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