opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright 2007, 2008, 2009, 2010
   3    Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "opcode/i386.h"
  23 #ifdef HAVE_LIMITS_H
  24 #include <limits.h>
  25 #endif
  26
  27 #ifndef CHAR_BIT
  28 #define CHAR_BIT 8
  29 #endif
  30
  31 /* Position of cpu flags bitfiled.  */
  32
  33 enum
  34 {
  35   /* i186 or better required */
  36   Cpu186 = 0,
  37   /* i286 or better required */
  38   Cpu286,
  39   /* i386 or better required */
  40   Cpu386,
  41   /* i486 or better required */
  42   Cpu486,
  43   /* i585 or better required */
  44   Cpu586,
  45   /* i686 or better required */
  46   Cpu686,
  47   /* CLFLUSH Instruction support required */
  48   CpuClflush,
  49   /* NOP Instruction support required */
  50   CpuNop,
  51   /* SYSCALL Instructions support required */
  52   CpuSYSCALL,
  53   /* Floating point support required */
  54   Cpu8087,
  55   /* i287 support required */
  56   Cpu287,
  57   /* i387 support required */
  58   Cpu387,
  59   /* i686 and floating point support required */
  60   Cpu687,
  61   /* SSE3 and floating point support required */
  62   CpuFISTTP,
  63   /* MMX support required */
  64   CpuMMX,
  65   /* SSE support required */
  66   CpuSSE,
  67   /* SSE2 support required */
  68   CpuSSE2,
  69   /* 3dnow! support required */
  70   Cpu3dnow,
  71   /* 3dnow! Extensions support required */
  72   Cpu3dnowA,
  73   /* SSE3 support required */
  74   CpuSSE3,
  75   /* VIA PadLock required */
  76   CpuPadLock,
  77   /* AMD Secure Virtual Machine Ext-s required */
  78   CpuSVME,
  79   /* VMX Instructions required */
  80   CpuVMX,
  81   /* SMX Instructions required */
  82   CpuSMX,
  83   /* SSSE3 support required */
  84   CpuSSSE3,
  85   /* SSE4a support required */
  86   CpuSSE4a,
  87   /* ABM New Instructions required */
  88   CpuABM,
  89   /* SSE4.1 support required */
  90   CpuSSE4_1,
  91   /* SSE4.2 support required */
  92   CpuSSE4_2,
  93   /* AVX support required */
  94   CpuAVX,
  95   /* AVX2 support required */
  96   CpuAVX2,
  97   /* Intel L1OM support required */
  98   CpuL1OM,
  99   /* Intel K1OM support required */
 100   CpuK1OM,
 101   /* Xsave/xrstor New Instructions support required */
 102   CpuXsave,
 103   /* Xsaveopt New Instructions support required */
 104   CpuXsaveopt,
 105   /* AES support required */
 106   CpuAES,
 107   /* PCLMUL support required */
 108   CpuPCLMUL,
 109   /* FMA support required */
 110   CpuFMA,
 111   /* FMA4 support required */
 112   CpuFMA4,
 113   /* XOP support required */
 114   CpuXOP,
 115   /* LWP support required */
 116   CpuLWP,
 117   /* BMI support required */
 118   CpuBMI,
 119   /* TBM support required */
 120   CpuTBM,
 121   /* MOVBE Instruction support required */
 122   CpuMovbe,
 123   /* EPT Instructions required */
 124   CpuEPT,
 125   /* RDTSCP Instruction support required */
 126   CpuRdtscp,
 127   /* FSGSBASE Instructions required */
 128   CpuFSGSBase,
 129   /* RDRND Instructions required */
 130   CpuRdRnd,
 131   /* F16C Instructions required */
 132   CpuF16C,
 133   /* Intel BMI2 support required */
 134   CpuBMI2,
 135   /* LZCNT support required */
 136   CpuLZCNT,
 137   /* HLE support required */
 138   CpuHLE,
 139   /* RTM support required */
 140   CpuRTM,
 141   /* INVPCID Instructions required */
 142   CpuINVPCID,
 143   /* VMFUNC Instruction required */
 144   CpuVMFUNC,
 145   /* 64bit support available, used by -march= in assembler.  */
 146   CpuLM,
 147   /* 64bit support required  */
 148   Cpu64,
 149   /* Not supported in the 64bit mode  */
 150   CpuNo64,
 151   /* The last bitfield in i386_cpu_flags.  */
 152   CpuMax = CpuNo64
 153 };
 154
 155 #define CpuNumOfUints \
 156   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 157 #define CpuNumOfBits \
 158   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 159
 160 /* If you get a compiler error for zero width of the unused field,
 161    comment it out.  */
 162 #define CpuUnused       (CpuMax + 1)
 163
 164 /* We can check if an instruction is available with array instead
 165    of bitfield. */
 166 typedef union i386_cpu_flags
 167 {
 168   struct
 169     {
 170       unsigned int cpui186:1;
 171       unsigned int cpui286:1;
 172       unsigned int cpui386:1;
 173       unsigned int cpui486:1;
 174       unsigned int cpui586:1;
 175       unsigned int cpui686:1;
 176       unsigned int cpuclflush:1;
 177       unsigned int cpunop:1;
 178       unsigned int cpusyscall:1;
 179       unsigned int cpu8087:1;
 180       unsigned int cpu287:1;
 181       unsigned int cpu387:1;
 182       unsigned int cpu687:1;
 183       unsigned int cpufisttp:1;
 184       unsigned int cpummx:1;
 185       unsigned int cpusse:1;
 186       unsigned int cpusse2:1;
 187       unsigned int cpua3dnow:1;
 188       unsigned int cpua3dnowa:1;
 189       unsigned int cpusse3:1;
 190       unsigned int cpupadlock:1;
 191       unsigned int cpusvme:1;
 192       unsigned int cpuvmx:1;
 193       unsigned int cpusmx:1;
 194       unsigned int cpussse3:1;
 195       unsigned int cpusse4a:1;
 196       unsigned int cpuabm:1;
 197       unsigned int cpusse4_1:1;
 198       unsigned int cpusse4_2:1;
 199       unsigned int cpuavx:1;
 200       unsigned int cpuavx2:1;
 201       unsigned int cpul1om:1;
 202       unsigned int cpuk1om:1;
 203       unsigned int cpuxsave:1;
 204       unsigned int cpuxsaveopt:1;
 205       unsigned int cpuaes:1;
 206       unsigned int cpupclmul:1;
 207       unsigned int cpufma:1;
 208       unsigned int cpufma4:1;
 209       unsigned int cpuxop:1;
 210       unsigned int cpulwp:1;
 211       unsigned int cpubmi:1;
 212       unsigned int cputbm:1;
 213       unsigned int cpumovbe:1;
 214       unsigned int cpuept:1;
 215       unsigned int cpurdtscp:1;
 216       unsigned int cpufsgsbase:1;
 217       unsigned int cpurdrnd:1;
 218       unsigned int cpuf16c:1;
 219       unsigned int cpubmi2:1;
 220       unsigned int cpulzcnt:1;
 221       unsigned int cpuhle:1;
 222       unsigned int cpurtm:1;
 223       unsigned int cpuinvpcid:1;
 224       unsigned int cpuvmfunc:1;
 225       unsigned int cpulm:1;
 226       unsigned int cpu64:1;
 227       unsigned int cpuno64:1;
 228 #ifdef CpuUnused
 229       unsigned int unused:(CpuNumOfBits - CpuUnused);
 230 #endif
 231     } bitfield;
 232   unsigned int array[CpuNumOfUints];
 233 } i386_cpu_flags;
 234
 235 /* Position of opcode_modifier bits.  */
 236
 237 enum
 238 {
 239   /* has direction bit. */
 240   D = 0,
 241   /* set if operands can be words or dwords encoded the canonical way */
 242   W,
 243   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 244      operand in encoding.  */
 245   S,
 246   /* insn has a modrm byte. */
 247   Modrm,
 248   /* register is in low 3 bits of opcode */
 249   ShortForm,
 250   /* special case for jump insns.  */
 251   Jump,
 252   /* call and jump */
 253   JumpDword,
 254   /* loop and jecxz */
 255   JumpByte,
 256   /* special case for intersegment leaps/calls */
 257   JumpInterSegment,
 258   /* FP insn memory format bit, sized by 0x4 */
 259   FloatMF,
 260   /* src/dest swap for floats. */
 261   FloatR,
 262   /* has float insn direction bit. */
 263   FloatD,
 264   /* needs size prefix if in 32-bit mode */
 265   Size16,
 266   /* needs size prefix if in 16-bit mode */
 267   Size32,
 268   /* needs size prefix if in 64-bit mode */
 269   Size64,
 270   /* check register size.  */
 271   CheckRegSize,
 272   /* instruction ignores operand size prefix and in Intel mode ignores
 273      mnemonic size suffix check.  */
 274   IgnoreSize,
 275   /* default insn size depends on mode */
 276   DefaultSize,
 277   /* b suffix on instruction illegal */
 278   No_bSuf,
 279   /* w suffix on instruction illegal */
 280   No_wSuf,
 281   /* l suffix on instruction illegal */
 282   No_lSuf,
 283   /* s suffix on instruction illegal */
 284   No_sSuf,
 285   /* q suffix on instruction illegal */
 286   No_qSuf,
 287   /* long double suffix on instruction illegal */
 288   No_ldSuf,
 289   /* instruction needs FWAIT */
 290   FWait,
 291   /* quick test for string instructions */
 292   IsString,
 293   /* quick test for lockable instructions */
 294   IsLockable,
 295   /* fake an extra reg operand for clr, imul and special register
 296      processing for some instructions.  */
 297   RegKludge,
 298   /* The first operand must be xmm0 */
 299   FirstXmm0,
 300   /* An implicit xmm0 as the first operand */
 301   Implicit1stXmm0,
 302   /* The HLE prefix is OK:
 303      1. With a LOCK prefix.
 304      2. With or without a LOCK prefix.
 305      3. With a RELEASE (0xf3) prefix.
 306    */
 307   HLEPrefixOk,
 308   /* Convert to DWORD */
 309   ToDword,
 310   /* Convert to QWORD */
 311   ToQword,
 312   /* Address prefix changes operand 0 */
 313   AddrPrefixOp0,
 314   /* opcode is a prefix */
 315   IsPrefix,
 316   /* instruction has extension in 8 bit imm */
 317   ImmExt,
 318   /* instruction don't need Rex64 prefix.  */
 319   NoRex64,
 320   /* instruction require Rex64 prefix.  */
 321   Rex64,
 322   /* deprecated fp insn, gets a warning */
 323   Ugh,
 324   /* insn has VEX prefix:
 325         1: 128bit VEX prefix.
 326         2: 256bit VEX prefix.
 327         3: Scalar VEX prefix.
 328    */
 329 #define VEX128          1
 330 #define VEX256          2
 331 #define VEXScalar       3
 332   Vex,
 333   /* How to encode VEX.vvvv:
 334      0: VEX.vvvv must be 1111b.
 335      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 336         the content of source registers will be preserved.
 337         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 338         where the content of first source register will be overwritten
 339         by the result.
 340         VEX.NDD2.  The second destination register operand is encoded in
 341         VEX.vvvv for instructions with 2 destination register operands.
 342         For assembler, there are no difference between VEX.NDS, VEX.DDS
 343         and VEX.NDD2.
 344      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 345      instructions with 1 destination register operand.
 346      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 347         of the operands can access a memory location.
 348    */
 349 #define VEXXDS  1
 350 #define VEXNDD  2
 351 #define VEXLWP  3
 352   VexVVVV,
 353   /* How the VEX.W bit is used:
 354      0: Set by the REX.W bit.
 355      1: VEX.W0.  Should always be 0.
 356      2: VEX.W1.  Should always be 1.
 357    */
 358 #define VEXW0   1
 359 #define VEXW1   2
 360   VexW,
 361   /* VEX opcode prefix:
 362      0: VEX 0x0F opcode prefix.
 363      1: VEX 0x0F38 opcode prefix.
 364      2: VEX 0x0F3A opcode prefix
 365      3: XOP 0x08 opcode prefix.
 366      4: XOP 0x09 opcode prefix
 367      5: XOP 0x0A opcode prefix.
 368    */
 369 #define VEX0F           0
 370 #define VEX0F38         1
 371 #define VEX0F3A         2
 372 #define XOP08           3
 373 #define XOP09           4
 374 #define XOP0A           5
 375   VexOpcode,
 376   /* number of VEX source operands:
 377      0: <= 2 source operands.
 378      1: 2 XOP source operands.
 379      2: 3 source operands.
 380    */
 381 #define XOP2SOURCES     1
 382 #define VEX3SOURCES     2
 383   VexSources,
 384   /* instruction has VEX 8 bit imm */
 385   VexImmExt,
 386   /* Instruction with vector SIB byte:
 387         1: 128bit vector register.
 388         2: 256bit vector register.
 389    */
 390 #define VecSIB128       1
 391 #define VecSIB256       2
 392   VecSIB,
 393   /* SSE to AVX support required */
 394   SSE2AVX,
 395   /* No AVX equivalent */
 396   NoAVX,
 397   /* Compatible with old (<= 2.8.1) versions of gcc  */
 398   OldGcc,
 399   /* AT&T mnemonic.  */
 400   ATTMnemonic,
 401   /* AT&T syntax.  */
 402   ATTSyntax,
 403   /* Intel syntax.  */
 404   IntelSyntax,
 405   /* The last bitfield in i386_opcode_modifier.  */
 406   Opcode_Modifier_Max
 407 };
 408
 409 typedef struct i386_opcode_modifier
 410 {
 411   unsigned int d:1;
 412   unsigned int w:1;
 413   unsigned int s:1;
 414   unsigned int modrm:1;
 415   unsigned int shortform:1;
 416   unsigned int jump:1;
 417   unsigned int jumpdword:1;
 418   unsigned int jumpbyte:1;
 419   unsigned int jumpintersegment:1;
 420   unsigned int floatmf:1;
 421   unsigned int floatr:1;
 422   unsigned int floatd:1;
 423   unsigned int size16:1;
 424   unsigned int size32:1;
 425   unsigned int size64:1;
 426   unsigned int checkregsize:1;
 427   unsigned int ignoresize:1;
 428   unsigned int defaultsize:1;
 429   unsigned int no_bsuf:1;
 430   unsigned int no_wsuf:1;
 431   unsigned int no_lsuf:1;
 432   unsigned int no_ssuf:1;
 433   unsigned int no_qsuf:1;
 434   unsigned int no_ldsuf:1;
 435   unsigned int fwait:1;
 436   unsigned int isstring:1;
 437   unsigned int islockable:1;
 438   unsigned int regkludge:1;
 439   unsigned int firstxmm0:1;
 440   unsigned int implicit1stxmm0:1;
 441   unsigned int hleprefixok:2;
 442   unsigned int todword:1;
 443   unsigned int toqword:1;
 444   unsigned int addrprefixop0:1;
 445   unsigned int isprefix:1;
 446   unsigned int immext:1;
 447   unsigned int norex64:1;
 448   unsigned int rex64:1;
 449   unsigned int ugh:1;
 450   unsigned int vex:2;
 451   unsigned int vexvvvv:2;
 452   unsigned int vexw:2;
 453   unsigned int vexopcode:3;
 454   unsigned int vexsources:2;
 455   unsigned int veximmext:1;
 456   unsigned int vecsib:2;
 457   unsigned int sse2avx:1;
 458   unsigned int noavx:1;
 459   unsigned int oldgcc:1;
 460   unsigned int attmnemonic:1;
 461   unsigned int attsyntax:1;
 462   unsigned int intelsyntax:1;
 463 } i386_opcode_modifier;
 464
 465 /* Position of operand_type bits.  */
 466
 467 enum
 468 {
 469   /* 8bit register */
 470   Reg8 = 0,
 471   /* 16bit register */
 472   Reg16,
 473   /* 32bit register */
 474   Reg32,
 475   /* 64bit register */
 476   Reg64,
 477   /* Floating pointer stack register */
 478   FloatReg,
 479   /* MMX register */
 480   RegMMX,
 481   /* SSE register */
 482   RegXMM,
 483   /* AVX registers */
 484   RegYMM,
 485   /* Control register */
 486   Control,
 487   /* Debug register */
 488   Debug,
 489   /* Test register */
 490   Test,
 491   /* 2 bit segment register */
 492   SReg2,
 493   /* 3 bit segment register */
 494   SReg3,
 495   /* 1 bit immediate */
 496   Imm1,
 497   /* 8 bit immediate */
 498   Imm8,
 499   /* 8 bit immediate sign extended */
 500   Imm8S,
 501   /* 16 bit immediate */
 502   Imm16,
 503   /* 32 bit immediate */
 504   Imm32,
 505   /* 32 bit immediate sign extended */
 506   Imm32S,
 507   /* 64 bit immediate */
 508   Imm64,
 509   /* 8bit/16bit/32bit displacements are used in different ways,
 510      depending on the instruction.  For jumps, they specify the
 511      size of the PC relative displacement, for instructions with
 512      memory operand, they specify the size of the offset relative
 513      to the base register, and for instructions with memory offset
 514      such as `mov 1234,%al' they specify the size of the offset
 515      relative to the segment base.  */
 516   /* 8 bit displacement */
 517   Disp8,
 518   /* 16 bit displacement */
 519   Disp16,
 520   /* 32 bit displacement */
 521   Disp32,
 522   /* 32 bit signed displacement */
 523   Disp32S,
 524   /* 64 bit displacement */
 525   Disp64,
 526   /* Accumulator %al/%ax/%eax/%rax */
 527   Acc,
 528   /* Floating pointer top stack register %st(0) */
 529   FloatAcc,
 530   /* Register which can be used for base or index in memory operand.  */
 531   BaseIndex,
 532   /* Register to hold in/out port addr = dx */
 533   InOutPortReg,
 534   /* Register to hold shift count = cl */
 535   ShiftCount,
 536   /* Absolute address for jump.  */
 537   JumpAbsolute,
 538   /* String insn operand with fixed es segment */
 539   EsSeg,
 540   /* RegMem is for instructions with a modrm byte where the register
 541      destination operand should be encoded in the mod and regmem fields.
 542      Normally, it will be encoded in the reg field. We add a RegMem
 543      flag to the destination register operand to indicate that it should
 544      be encoded in the regmem field.  */
 545   RegMem,
 546   /* Memory.  */
 547   Mem,
 548   /* BYTE memory. */
 549   Byte,
 550   /* WORD memory. 2 byte */
 551   Word,
 552   /* DWORD memory. 4 byte */
 553   Dword,
 554   /* FWORD memory. 6 byte */
 555   Fword,
 556   /* QWORD memory. 8 byte */
 557   Qword,
 558   /* TBYTE memory. 10 byte */
 559   Tbyte,
 560   /* XMMWORD memory. */
 561   Xmmword,
 562   /* YMMWORD memory. */
 563   Ymmword,
 564   /* Unspecified memory size.  */
 565   Unspecified,
 566   /* Any memory size.  */
 567   Anysize,
 568
 569   /* Vector 4 bit immediate.  */
 570   Vec_Imm4,
 571
 572   /* The last bitfield in i386_operand_type.  */
 573   OTMax
 574 };
 575
 576 #define OTNumOfUints \
 577   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 578 #define OTNumOfBits \
 579   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 580
 581 /* If you get a compiler error for zero width of the unused field,
 582    comment it out.  */
 583 #define OTUnused                (OTMax + 1)
 584
 585 typedef union i386_operand_type
 586 {
 587   struct
 588     {
 589       unsigned int reg8:1;
 590       unsigned int reg16:1;
 591       unsigned int reg32:1;
 592       unsigned int reg64:1;
 593       unsigned int floatreg:1;
 594       unsigned int regmmx:1;
 595       unsigned int regxmm:1;
 596       unsigned int regymm:1;
 597       unsigned int control:1;
 598       unsigned int debug:1;
 599       unsigned int test:1;
 600       unsigned int sreg2:1;
 601       unsigned int sreg3:1;
 602       unsigned int imm1:1;
 603       unsigned int imm8:1;
 604       unsigned int imm8s:1;
 605       unsigned int imm16:1;
 606       unsigned int imm32:1;
 607       unsigned int imm32s:1;
 608       unsigned int imm64:1;
 609       unsigned int disp8:1;
 610       unsigned int disp16:1;
 611       unsigned int disp32:1;
 612       unsigned int disp32s:1;
 613       unsigned int disp64:1;
 614       unsigned int acc:1;
 615       unsigned int floatacc:1;
 616       unsigned int baseindex:1;
 617       unsigned int inoutportreg:1;
 618       unsigned int shiftcount:1;
 619       unsigned int jumpabsolute:1;
 620       unsigned int esseg:1;
 621       unsigned int regmem:1;
 622       unsigned int mem:1;
 623       unsigned int byte:1;
 624       unsigned int word:1;
 625       unsigned int dword:1;
 626       unsigned int fword:1;
 627       unsigned int qword:1;
 628       unsigned int tbyte:1;
 629       unsigned int xmmword:1;
 630       unsigned int ymmword:1;
 631       unsigned int unspecified:1;
 632       unsigned int anysize:1;
 633       unsigned int vec_imm4:1;
 634 #ifdef OTUnused
 635       unsigned int unused:(OTNumOfBits - OTUnused);
 636 #endif
 637     } bitfield;
 638   unsigned int array[OTNumOfUints];
 639 } i386_operand_type;
 640
 641 typedef struct insn_template
 642 {
 643   /* instruction name sans width suffix ("mov" for movl insns) */
 644   char *name;
 645
 646   /* how many operands */
 647   unsigned int operands;
 648
 649   /* base_opcode is the fundamental opcode byte without optional
 650      prefix(es).  */
 651   unsigned int base_opcode;
 652 #define Opcode_D        0x2 /* Direction bit:
 653                                set if Reg --> Regmem;
 654                                unset if Regmem --> Reg. */
 655 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 656 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 657
 658   /* extension_opcode is the 3 bit extension for group <n> insns.
 659      This field is also used to store the 8-bit opcode suffix for the
 660      AMD 3DNow! instructions.
 661      If this template has no extension opcode (the usual case) use None
 662      Instructions */
 663   unsigned int extension_opcode;
 664 #define None 0xffff             /* If no extension_opcode is possible.  */
 665
 666   /* Opcode length.  */
 667   unsigned char opcode_length;
 668
 669   /* cpu feature flags */
 670   i386_cpu_flags cpu_flags;
 671
 672   /* the bits in opcode_modifier are used to generate the final opcode from
 673      the base_opcode.  These bits also are used to detect alternate forms of
 674      the same instruction */
 675   i386_opcode_modifier opcode_modifier;
 676
 677   /* operand_types[i] describes the type of operand i.  This is made
 678      by OR'ing together all of the possible type masks.  (e.g.
 679      'operand_types[i] = Reg|Imm' specifies that operand i can be
 680      either a register or an immediate operand.  */
 681   i386_operand_type operand_types[MAX_OPERANDS];
 682 }
 683 insn_template;
 684
 685 extern const insn_template i386_optab[];
 686
 687 /* these are for register name --> number & type hash lookup */
 688 typedef struct
 689 {
 690   char *reg_name;
 691   i386_operand_type reg_type;
 692   unsigned char reg_flags;
 693 #define RegRex      0x1  /* Extended register.  */
 694 #define RegRex64    0x2  /* Extended 8 bit register.  */
 695   unsigned char reg_num;
 696 #define RegRip  ((unsigned char ) ~0)
 697 #define RegEip  (RegRip - 1)
 698 /* EIZ and RIZ are fake index registers.  */
 699 #define RegEiz  (RegEip - 1)
 700 #define RegRiz  (RegEiz - 1)
 701 /* FLAT is a fake segment register (Intel mode).  */
 702 #define RegFlat     ((unsigned char) ~0)
 703   signed char dw2_regnum[2];
 704 #define Dw2Inval (-1)
 705 }
 706 reg_entry;
 707
 708 /* Entries in i386_regtab.  */
 709 #define REGNAM_AL 1
 710 #define REGNAM_AX 25
 711 #define REGNAM_EAX 41
 712
 713 extern const reg_entry i386_regtab[];
 714 extern const unsigned int i386_regtab_size;
 715
 716 typedef struct
 717 {
 718   char *seg_name;
 719   unsigned int seg_prefix;
 720 }
 721 seg_entry;
 722
 723 extern const seg_entry cs;
 724 extern const seg_entry ds;
 725 extern const seg_entry ss;
 726 extern const seg_entry es;
 727 extern const seg_entry fs;
 728 extern const seg_entry gs;