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2004-08-31 Robert Bowdidge <bowdidge@apple.com>
[binutils.git] / opcodes / or32-opc.c
blob8ccdfb1e5e667de9817aa38c51fa30efee3d11b8
1 /* Table of opcodes for the OpenRISC 1000 ISA.
2 Copyright 2002 Free Software Foundation, Inc.
3 Contributed by Damjan Lampret (lampret@opencores.org).
4
5 This file is part of gen_or1k_isa, or1k, GDB and GAS.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21 /* We treat all letters the same in encode/decode routines so
22 we need to assign some characteristics to them like signess etc. */
23 #include <string.h>
24 #include <stdio.h>
25 #include <stdlib.h>
26 #include "safe-ctype.h"
27 #include "ansidecl.h"
28 #ifdef HAVE_CONFIG_H
29 # include "config.h"
30 #endif
31 #include "opcode/or32.h"
32
33 static unsigned long insn_extract PARAMS ((char, char *));
34 static unsigned long * cover_insn PARAMS ((unsigned long *, int, unsigned int));
35 static int num_ones PARAMS ((unsigned long));
36 static struct insn_op_struct * parse_params PARAMS ((const struct or32_opcode *, struct insn_op_struct *));
37 static unsigned long or32_extract PARAMS ((char, char *, unsigned long));
38 static void or32_print_register PARAMS ((char, char *, unsigned long));
39 static void or32_print_immediate PARAMS ((char, char *, unsigned long));
40 static unsigned long extend_imm PARAMS ((unsigned long, char));
41
42 const struct or32_letter or32_letters[] =
43 {
44 { 'A', NUM_UNSIGNED },
45 { 'B', NUM_UNSIGNED },
46 { 'D', NUM_UNSIGNED },
47 { 'I', NUM_SIGNED },
48 { 'K', NUM_UNSIGNED },
49 { 'L', NUM_UNSIGNED },
50 { 'N', NUM_SIGNED },
51 { '0', NUM_UNSIGNED },
52 { '\0', 0 } /* Dummy entry. */
53 };
54
55 /* Opcode encoding:
56 machine[31:30]: first two bits of opcode
57 00 - neither of source operands is GPR
58 01 - second source operand is GPR (rB)
59 10 - first source operand is GPR (rA)
60 11 - both source operands are GPRs (rA and rB)
61 machine[29:26]: next four bits of opcode
62 machine[25:00]: instruction operands (specific to individual instruction)
63
64 Recommendation: irrelevant instruction bits should be set with a value of
65 bits in same positions of instruction preceding current instruction in the
66 code (when assembling). */
67
68 #define EFN &l_none
69
70 #ifdef HAS_EXECUTION
71 #define EF(func) &(func)
72 #define EFI &l_invalid
73 #else /* HAS_EXECUTION */
74 #define EF(func) EFN
75 #define EFI EFN
76 #endif /* HAS_EXECUTION */
77
78 const struct or32_opcode or32_opcodes[] =
79 {
80 { "l.j", "N", "00 0x0 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_j), OR32_IF_DELAY },
81 { "l.jal", "N", "00 0x1 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_jal), OR32_IF_DELAY },
82 { "l.bnf", "N", "00 0x3 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bnf), OR32_IF_DELAY | OR32_R_FLAG},
83 { "l.bf", "N", "00 0x4 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bf), OR32_IF_DELAY | OR32_R_FLAG },
84 { "l.nop", "K", "00 0x5 01--- ----- KKKK KKKK KKKK KKKK", EF(l_nop), 0 },
85 { "l.movhi", "rD,K", "00 0x6 DDDDD ----0 KKKK KKKK KKKK KKKK", EF(l_movhi), 0 }, /*MM*/
86 { "l.macrc", "rD", "00 0x6 DDDDD ----1 0000 0000 0000 0000", EF(l_macrc), 0 }, /*MM*/
87
88 { "l.sys", "K", "00 0x8 00000 00000 KKKK KKKK KKKK KKKK", EF(l_sys), 0 },
89 { "l.trap", "K", "00 0x8 01000 00000 KKKK KKKK KKKK KKKK", EF(l_trap), 0 }, /* CZ 21/06/01 */
90 { "l.msync", "", "00 0x8 10000 00000 0000 0000 0000 0000", EFN, 0 },
91 { "l.psync", "", "00 0x8 10100 00000 0000 0000 0000 0000", EFN, 0 },
92 { "l.csync", "", "00 0x8 11000 00000 0000 0000 0000 0000", EFN, 0 },
93 { "l.rfe", "", "00 0x9 ----- ----- ---- ---- ---- ----", EF(l_rfe), OR32_IF_DELAY },
94
95 { "lv.all_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
96 { "lv.all_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
97 { "lv.all_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 },
98 { "lv.all_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 },
99 { "lv.all_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
100 { "lv.all_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },
101 { "lv.all_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 },
102 { "lv.all_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 },
103 { "lv.all_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x8", EFI, 0 },
104 { "lv.all_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x9", EFI, 0 },
105 { "lv.all_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xA", EFI, 0 },
106 { "lv.all_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xB", EFI, 0 },
107 { "lv.any_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x0", EFI, 0 },
108 { "lv.any_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x1", EFI, 0 },
109 { "lv.any_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x2", EFI, 0 },
110 { "lv.any_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x3", EFI, 0 },
111 { "lv.any_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x4", EFI, 0 },
112 { "lv.any_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x5", EFI, 0 },
113 { "lv.any_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x6", EFI, 0 },
114 { "lv.any_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x7", EFI, 0 },
115 { "lv.any_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x8", EFI, 0 },
116 { "lv.any_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x9", EFI, 0 },
117 { "lv.any_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xA", EFI, 0 },
118 { "lv.any_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xB", EFI, 0 },
119 { "lv.add.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x0", EFI, 0 },
120 { "lv.add.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x1", EFI, 0 },
121 { "lv.adds.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x2", EFI, 0 },
122 { "lv.adds.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x3", EFI, 0 },
123 { "lv.addu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x4", EFI, 0 },
124 { "lv.addu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x5", EFI, 0 },
125 { "lv.addus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x6", EFI, 0 },
126 { "lv.addus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x7", EFI, 0 },
127 { "lv.and", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x8", EFI, 0 },
128 { "lv.avg.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x9", EFI, 0 },
129 { "lv.avg.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0xA", EFI, 0 },
130 { "lv.cmp_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x0", EFI, 0 },
131 { "lv.cmp_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x1", EFI, 0 },
132 { "lv.cmp_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x2", EFI, 0 },
133 { "lv.cmp_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x3", EFI, 0 },
134 { "lv.cmp_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x4", EFI, 0 },
135 { "lv.cmp_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x5", EFI, 0 },
136 { "lv.cmp_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x6", EFI, 0 },
137 { "lv.cmp_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x7", EFI, 0 },
138 { "lv.cmp_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x8", EFI, 0 },
139 { "lv.cmp_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x9", EFI, 0 },
140 { "lv.cmp_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xA", EFI, 0 },
141 { "lv.cmp_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xB", EFI, 0 },
142 { "lv.madds.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x4", EFI, 0 },
143 { "lv.max.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x5", EFI, 0 },
144 { "lv.max.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x6", EFI, 0 },
145 { "lv.merge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x7", EFI, 0 },
146 { "lv.merge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x8", EFI, 0 },
147 { "lv.min.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x9", EFI, 0 },
148 { "lv.min.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xA", EFI, 0 },
149 { "lv.msubs.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xB", EFI, 0 },
150 { "lv.muls.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xC", EFI, 0 },
151 { "lv.nand", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xD", EFI, 0 },
152 { "lv.nor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xE", EFI, 0 },
153 { "lv.or", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xF", EFI, 0 },
154 { "lv.pack.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x0", EFI, 0 },
155 { "lv.pack.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x1", EFI, 0 },
156 { "lv.packs.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x2", EFI, 0 },
157 { "lv.packs.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x3", EFI, 0 },
158 { "lv.packus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x4", EFI, 0 },
159 { "lv.packus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x5", EFI, 0 },
160 { "lv.perm.n", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x6", EFI, 0 },
161 { "lv.rl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x7", EFI, 0 },
162 { "lv.rl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x8", EFI, 0 },
163 { "lv.sll.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x9", EFI, 0 },
164 { "lv.sll.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xA", EFI, 0 },
165 { "lv.sll", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xB", EFI, 0 },
166 { "lv.srl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xC", EFI, 0 },
167 { "lv.srl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xD", EFI, 0 },
168 { "lv.sra.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xE", EFI, 0 },
169 { "lv.sra.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xF", EFI, 0 },
170 { "lv.srl", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x0", EFI, 0 },
171 { "lv.sub.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x1", EFI, 0 },
172 { "lv.sub.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x2", EFI, 0 },
173 { "lv.subs.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x3", EFI, 0 },
174 { "lv.subs.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x4", EFI, 0 },
175 { "lv.subu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x5", EFI, 0 },
176 { "lv.subu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x6", EFI, 0 },
177 { "lv.subus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x7", EFI, 0 },
178 { "lv.subus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x8", EFI, 0 },
179 { "lv.unpack.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x9", EFI, 0 },
180 { "lv.unpack.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xA", EFI, 0 },
181 { "lv.xor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xB", EFI, 0 },
182 { "lv.cust1", "", "00 0xA ----- ----- ---- ---- 0xC ----", EFI, 0 },
183 { "lv.cust2", "", "00 0xA ----- ----- ---- ---- 0xD ----", EFI, 0 },
184 { "lv.cust3", "", "00 0xA ----- ----- ---- ---- 0xE ----", EFI, 0 },
185 { "lv.cust4", "", "00 0xA ----- ----- ---- ---- 0xF ----", EFI, 0 },
186
187 { "lf.add.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
188 { "lf.sub.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
189 { "lf.mul.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 },
190 { "lf.div.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 },
191 { "lf.itof.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
192 { "lf.ftoi.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },
193 { "lf.rem.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 },
194 { "lf.madd.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 },
195 { "lf.sfeq.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 },
196 { "lf.sfne.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0 },
197 { "lf.sfgt.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0 },
198 { "lf.sfge.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0 },
199 { "lf.sflt.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0 },
200 { "lf.sfle.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0 },
201 { "lf.cust1.s", "", "00 0xB ----- ----- ---- ---- 0xE ----", EFI, 0 },
202
203 { "lf.add.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
204 { "lf.sub.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
205 { "lf.mul.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 },
206 { "lf.div.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 },
207 { "lf.itof.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
208 { "lf.ftoi.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },
209 { "lf.rem.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 },
210 { "lf.madd.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 },
211 { "lf.sfeq.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 },
212 { "lf.sfne.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0 },
213 { "lf.sfgt.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0 },
214 { "lf.sfge.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0 },
215 { "lf.sflt.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0 },
216 { "lf.sfle.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0 },
217 { "lf.cust1.d", "", "00 0xC ----- ----- ---- ---- 0xE ----", EFI, 0 },
218
219 { "lvf.ld", "rD,0(rA)", "00 0xD DDDDD AAAAA ---- ---- 0x0 0x0", EFI, 0 },
220 { "lvf.lw", "rD,0(rA)", "00 0xD DDDDD AAAAA ---- ---- 0x0 0x1", EFI, 0 },
221 { "lvf.sd", "0(rA),rB", "00 0xD ----- AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
222 { "lvf.sw", "0(rA),rB", "00 0xD ----- AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
223
224 { "l.jr", "rB", "01 0x1 ----- ----- BBBB B--- ---- ----", EF(l_jr), OR32_IF_DELAY },
225 { "l.jalr", "rB", "01 0x2 ----- ----- BBBB B--- ---- ----", EF(l_jalr), OR32_IF_DELAY },
226 { "l.maci", "rB,I", "01 0x3 IIIII ----- BBBB BIII IIII IIII", EF(l_mac), 0 },
227 { "l.cust1", "", "01 0xC ----- ----- ---- ---- ---- ----", EF(l_cust1), 0 },
228 { "l.cust2", "", "01 0xD ----- ----- ---- ---- ---- ----", EF(l_cust2), 0 },
229 { "l.cust3", "", "01 0xE ----- ----- ---- ---- ---- ----", EF(l_cust3), 0 },
230 { "l.cust4", "", "01 0xF ----- ----- ---- ---- ---- ----", EF(l_cust4), 0 },
231
232 { "l.ld", "rD,I(rA)", "10 0x0 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
233 { "l.lwz", "rD,I(rA)", "10 0x1 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lwz), 0 },
234 { "l.lws", "rD,I(rA)", "10 0x2 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
235 { "l.lbz", "rD,I(rA)", "10 0x3 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbz), 0 },
236 { "l.lbs", "rD,I(rA)", "10 0x4 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbs), 0 },
237 { "l.lhz", "rD,I(rA)", "10 0x5 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhz), 0 },
238 { "l.lhs", "rD,I(rA)", "10 0x6 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhs), 0 },
239
240 { "l.addi", "rD,rA,I", "10 0x7 DDDDD AAAAA IIII IIII IIII IIII", EF(l_add), 0 },
241 { "l.addic", "rD,rA,I", "10 0x8 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
242 { "l.andi", "rD,rA,K", "10 0x9 DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_and), 0 },
243 { "l.ori", "rD,rA,K", "10 0xA DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_or), 0 },
244 { "l.xori", "rD,rA,I", "10 0xB DDDDD AAAAA IIII IIII IIII IIII", EF(l_xor), 0 },
245 { "l.muli", "rD,rA,I", "10 0xC DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
246 { "l.mfspr", "rD,rA,K", "10 0xD DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_mfspr), 0 },
247 { "l.slli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 00LL LLLL", EF(l_sll), 0 },
248 { "l.srli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 01LL LLLL", EF(l_srl), 0 },
249 { "l.srai", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 10LL LLLL", EF(l_sra), 0 },
250 { "l.rori", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 11LL LLLL", EFI, 0 },
251
252 { "l.sfeqi", "rA,I", "10 0xF 00000 AAAAA IIII IIII IIII IIII", EF(l_sfeq), OR32_W_FLAG },
253 { "l.sfnei", "rA,I", "10 0xF 00001 AAAAA IIII IIII IIII IIII", EF(l_sfne), OR32_W_FLAG },
254 { "l.sfgtui", "rA,I", "10 0xF 00010 AAAAA IIII IIII IIII IIII", EF(l_sfgtu), OR32_W_FLAG },
255 { "l.sfgeui", "rA,I", "10 0xF 00011 AAAAA IIII IIII IIII IIII", EF(l_sfgeu), OR32_W_FLAG },
256 { "l.sfltui", "rA,I", "10 0xF 00100 AAAAA IIII IIII IIII IIII", EF(l_sfltu), OR32_W_FLAG },
257 { "l.sfleui", "rA,I", "10 0xF 00101 AAAAA IIII IIII IIII IIII", EF(l_sfleu), OR32_W_FLAG },
258 { "l.sfgtsi", "rA,I", "10 0xF 01010 AAAAA IIII IIII IIII IIII", EF(l_sfgts), OR32_W_FLAG },
259 { "l.sfgesi", "rA,I", "10 0xF 01011 AAAAA IIII IIII IIII IIII", EF(l_sfges), OR32_W_FLAG },
260 { "l.sfltsi", "rA,I", "10 0xF 01100 AAAAA IIII IIII IIII IIII", EF(l_sflts), OR32_W_FLAG },
261 { "l.sflesi", "rA,I", "10 0xF 01101 AAAAA IIII IIII IIII IIII", EF(l_sfles), OR32_W_FLAG },
262
263 { "l.mtspr", "rA,rB,K", "11 0x0 KKKKK AAAAA BBBB BKKK KKKK KKKK", EF(l_mtspr), 0 },
264 { "l.mac", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x1", EF(l_mac), 0 }, /*MM*/
265 { "l.msb", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x2", EF(l_msb), 0 }, /*MM*/
266
267 { "l.sd", "I(rA),rB", "11 0x4 IIIII AAAAA BBBB BIII IIII IIII", EFI, 0 },
268 { "l.sw", "I(rA),rB", "11 0x5 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sw), 0 },
269 { "l.sb", "I(rA),rB", "11 0x6 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sb), 0 },
270 { "l.sh", "I(rA),rB", "11 0x7 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sh), 0 },
271
272 { "l.add", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x0", EF(l_add), 0 },
273 { "l.addc", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x1", EFI, 0 },
274 { "l.sub", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x2", EF(l_sub), 0 },
275 { "l.and", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x3", EF(l_and), 0 },
276 { "l.or", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x4", EF(l_or), 0 },
277 { "l.xor", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x5", EF(l_xor), 0 },
278 { "l.mul", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0x6", EF(l_mul), 0 },
279
280 { "l.sll", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0x8", EF(l_sll), 0 },
281 { "l.srl", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0x8", EF(l_srl), 0 },
282 { "l.sra", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0x8", EF(l_sra), 0 },
283 { "l.ror", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0x8", EFI, 0 },
284 { "l.div", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x9", EF(l_div), 0 },
285 { "l.divu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xA", EF(l_divu), 0 },
286 { "l.mulu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0xB", EFI, 0 },
287 { "l.exths", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0xC", EFI, 0 },
288 { "l.extbs", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0xC", EFI, 0 },
289 { "l.exthz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0xC", EFI, 0 },
290 { "l.extbz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0xC", EFI, 0 },
291 { "l.extws", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0xD", EFI, 0 },
292 { "l.extwz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0xD", EFI, 0 },
293 { "l.cmov", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xE", EFI, 0 },
294 { "l.ff1", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xF", EFI, 0 },
295
296 { "l.sfeq", "rA,rB", "11 0x9 00000 AAAAA BBBB B--- ---- ----", EF(l_sfeq), OR32_W_FLAG },
297 { "l.sfne", "rA,rB", "11 0x9 00001 AAAAA BBBB B--- ---- ----", EF(l_sfne), OR32_W_FLAG },
298 { "l.sfgtu", "rA,rB", "11 0x9 00010 AAAAA BBBB B--- ---- ----", EF(l_sfgtu), OR32_W_FLAG },
299 { "l.sfgeu", "rA,rB", "11 0x9 00011 AAAAA BBBB B--- ---- ----", EF(l_sfgeu), OR32_W_FLAG },
300 { "l.sfltu", "rA,rB", "11 0x9 00100 AAAAA BBBB B--- ---- ----", EF(l_sfltu), OR32_W_FLAG },
301 { "l.sfleu", "rA,rB", "11 0x9 00101 AAAAA BBBB B--- ---- ----", EF(l_sfleu), OR32_W_FLAG },
302 { "l.sfgts", "rA,rB", "11 0x9 01010 AAAAA BBBB B--- ---- ----", EF(l_sfgts), OR32_W_FLAG },
303 { "l.sfges", "rA,rB", "11 0x9 01011 AAAAA BBBB B--- ---- ----", EF(l_sfges), OR32_W_FLAG },
304 { "l.sflts", "rA,rB", "11 0x9 01100 AAAAA BBBB B--- ---- ----", EF(l_sflts), OR32_W_FLAG },
305 { "l.sfles", "rA,rB", "11 0x9 01101 AAAAA BBBB B--- ---- ----", EF(l_sfles), OR32_W_FLAG },
306
307 { "l.cust5", "", "11 0xC ----- ----- ---- ---- ---- ----", EFI, 0 },
308 { "l.cust6", "", "11 0xD ----- ----- ---- ---- ---- ----", EFI, 0 },
309 { "l.cust7", "", "11 0xE ----- ----- ---- ---- ---- ----", EFI, 0 },
310 { "l.cust8", "", "11 0xF ----- ----- ---- ---- ---- ----", EFI, 0 },
311
312 /* This section should not be defined in or1ksim, since it contains duplicates,
313 which would cause machine builder to complain. */
314 #ifdef HAS_CUST
315 { "l.cust5_1", "rD", "11 0xC DDDDD ----- ---- ---- ---- ----", EFI, 0 },
316 { "l.cust5_2", "rD,rA" , "11 0xC DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
317 { "l.cust5_3", "rD,rA,rB", "11 0xC DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
318
319 { "l.cust6_1", "rD", "11 0xD DDDDD ----- ---- ---- ---- ----", EFI, 0 },
320 { "l.cust6_2", "rD,rA" , "11 0xD DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
321 { "l.cust6_3", "rD,rA,rB", "11 0xD DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
322
323 { "l.cust7_1", "rD", "11 0xE DDDDD ----- ---- ---- ---- ----", EFI, 0 },
324 { "l.cust7_2", "rD,rA" , "11 0xE DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
325 { "l.cust7_3", "rD,rA,rB", "11 0xE DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
326
327 { "l.cust8_1", "rD", "11 0xF DDDDD ----- ---- ---- ---- ----", EFI, 0 },
328 { "l.cust8_2", "rD,rA" , "11 0xF DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
329 { "l.cust8_3", "rD,rA,rB", "11 0xF DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
330 #endif
331
332 /* Dummy entry, not included in num_opcodes. This
333 lets code examine entry i+1 without checking
334 if we've run off the end of the table. */
335 { "", "", "", EFI, 0 }
336 };
337
338 #undef EFI
339 #undef EFN
340 #undef EF
341
342 /* Define dummy, if debug is not defined. */
343
344 #if !defined HAS_DEBUG
345 static void debug PARAMS ((int, const char *, ...));
346
347 static void
348 debug (int level, const char *format, ...)
349 {
350 /* Just to get rid of warnings. */
351 format = (char *) level = 0;
352 }
353 #endif
354
355 const unsigned int or32_num_opcodes = ((sizeof(or32_opcodes)) / (sizeof(struct or32_opcode))) - 1;
356
357 /* Calculates instruction length in bytes. Always 4 for OR32. */
358
359 int
360 insn_len (insn_index)
361 int insn_index ATTRIBUTE_UNUSED;
362 {
363 return 4;
364 }
365
366 /* Is individual insn's operand signed or unsigned? */
367
368 int
369 letter_signed (l)
370 char l;
371 {
372 const struct or32_letter *pletter;
373
374 for (pletter = or32_letters; pletter->letter != '\0'; pletter++)
375 if (pletter->letter == l)
376 return pletter->sign;
377
378 printf ("letter_signed(%c): Unknown letter.\n", l);
379 return 0;
380 }
381
382 /* Number of letters in the individual lettered operand. */
383
384 int
385 letter_range (l)
386 char l;
387 {
388 const struct or32_opcode *pinsn;
389 char *enc;
390 int range = 0;
391
392 for (pinsn = or32_opcodes; strlen(pinsn->name); pinsn++)
393 {
394 if (strchr (pinsn->encoding,l))
395 {
396 for (enc = pinsn->encoding; *enc != '\0'; enc++)
397 if ((*enc == '0') && (*(enc+1) == 'x'))
398 enc += 2;
399 else if (*enc == l)
400 range++;
401 return range;
402 }
403 }
404
405 printf ("\nABORT: letter_range(%c): Never used letter.\n", l);
406 exit (1);
407 }
408
409 /* MM: Returns index of given instruction name. */
410
411 int
412 insn_index (char *insn)
413 {
414 unsigned int i;
415 int found = -1;
416
417 for (i = 0; i < or32_num_opcodes; i++)
418 if (!strcmp (or32_opcodes[i].name, insn))
419 {
420 found = i;
421 break;
422 }
423 return found;
424 }
425
426 const char *
427 insn_name (index)
428 int index;
429 {
430 if (index >= 0 && index < (int) or32_num_opcodes)
431 return or32_opcodes[index].name;
432 else
433 return "???";
434 }
435
436 void
437 l_none ()
438 {
439 }
440
441 /* Finite automata for instruction decoding building code. */
442
443 /* Find simbols in encoding. */
444 static unsigned long
445 insn_extract (param_ch, enc_initial)
446 char param_ch;
447 char *enc_initial;
448 {
449 char *enc;
450 unsigned long ret = 0;
451 unsigned opc_pos = 32;
452
453 for (enc = enc_initial; *enc != '\0'; )
454 if ((*enc == '0') && (*(enc + 1) == 'x'))
455 {
456 unsigned long tmp = strtol (enc+2, NULL, 16);
457
458 opc_pos -= 4;
459 if (param_ch == '0' || param_ch == '1')
460 {
461 if (param_ch == '0')
462 tmp = 15 - tmp;
463 ret |= tmp << opc_pos;
464 }
465 enc += 3;
466 }
467 else
468 {
469 if (*enc == '0' || *enc == '1' || *enc == '-' || ISALPHA (*enc))
470 {
471 opc_pos--;
472 if (param_ch == *enc)
473 ret |= 1 << opc_pos;
474 }
475 enc++;
476 }
477 return ret;
478 }
479
480 #define MAX_AUTOMATA_SIZE (1200)
481 #define MAX_OP_TABLE_SIZE (1200)
482 #define LEAF_FLAG (0x80000000)
483 #define MAX_LEN (8)
484
485 #ifndef MIN
486 # define MIN(x,y) ((x) < (y) ? (x) : (y))
487 #endif
488
489 unsigned long *automata;
490 int nuncovered;
491 int curpass = 0;
492
493 /* MM: Struct that hold runtime build information about instructions. */
494 struct temp_insn_struct
495 {
496 unsigned long insn;
497 unsigned long insn_mask;
498 int in_pass;
499 } *ti;
500
501 struct insn_op_struct *op_data, **op_start;
502
503 /* Recursive utility function used to find best match and to build automata. */
504
505 static unsigned long *
506 cover_insn (cur, pass, mask)
507 unsigned long * cur;
508 int pass;
509 unsigned int mask;
510 {
511 int best_first = 0, last_match = -1, ninstr = 0;
512 unsigned int best_len = 0;
513 unsigned int i;
514 unsigned long cur_mask = mask;
515 unsigned long *next;
516
517 for (i = 0; i < or32_num_opcodes; i++)
518 if (ti[i].in_pass == pass)
519 {
520 cur_mask &= ti[i].insn_mask;
521 ninstr++;
522 last_match = i;
523 }
524
525 debug (8, "%08X %08X\n", mask, cur_mask);
526
527 if (ninstr == 0)
528 return 0;
529
530 if (ninstr == 1)
531 {
532 /* Leaf holds instruction index. */
533 debug (8, "%i>I%i %s\n",
534 cur - automata, last_match, or32_opcodes[last_match].name);
535
536 *cur = LEAF_FLAG | last_match;
537 cur++;
538 nuncovered--;
539 }
540 else
541 {
542 /* Find longest match. */
543 for (i = 0; i < 32; i++)
544 {
545 unsigned int len;
546
547 for (len = best_len + 1; len < MIN (MAX_LEN, 33 - i); len++)
548 {
549 unsigned long m = (1UL << ((unsigned long)len)) - 1;
550
551 debug (9, " (%i(%08X & %08X>>%i = %08X, %08X)",
552 len,m, cur_mask, i, (cur_mask >> (unsigned)i),
553 (cur_mask >> (unsigned)i) & m);
554
555 if ((m & (cur_mask >> (unsigned)i)) == m)
556 {
557 best_len = len;
558 best_first = i;
559 debug (9, "!");
560 }
561 else
562 break;
563 }
564 }
565
566 debug (9, "\n");
567
568 if (!best_len)
569 {
570 fprintf (stderr, "%i instructions match mask 0x%08X:\n", ninstr, mask);
571
572 for (i = 0; i < or32_num_opcodes; i++)
573 if (ti[i].in_pass == pass)
574 fprintf (stderr, "%s ", or32_opcodes[i].name);
575
576 fprintf (stderr, "\n");
577 exit (1);
578 }
579
580 debug (8, "%i> #### %i << %i (%i) ####\n",
581 cur - automata, best_len, best_first, ninstr);
582
583 *cur = best_first;
584 cur++;
585 *cur = (1 << best_len) - 1;
586 cur++;
587 next = cur;
588
589 /* Allocate space for pointers. */
590 cur += 1 << best_len;
591 cur_mask = (1 << (unsigned long)best_len) - 1;
592
593 for (i = 0; i < ((unsigned) 1 << best_len); i++)
594 {
595 unsigned int j;
596 unsigned long *c;
597
598 curpass++;
599 for (j = 0; j < or32_num_opcodes; j++)
600 if (ti[j].in_pass == pass
601 && ((ti[j].insn >> best_first) & cur_mask) == (unsigned long) i
602 && ((ti[j].insn_mask >> best_first) & cur_mask) == cur_mask)
603 ti[j].in_pass = curpass;
604
605 debug (9, "%08X %08X %i\n", mask, cur_mask, best_first);
606 c = cover_insn (cur, curpass, mask & (~(cur_mask << best_first)));
607 if (c)
608 {
609 debug (8, "%i> #%X -> %u\n", next - automata, i, cur - automata);
610 *next = cur - automata;
611 cur = c;
612 }
613 else
614 {
615 debug (8, "%i> N/A\n", next - automata);
616 *next = 0;
617 }
618 next++;
619 }
620 }
621 return cur;
622 }
623
624 /* Returns number of nonzero bits. */
625
626 static int
627 num_ones (value)
628 unsigned long value;
629 {
630 int c = 0;
631
632 while (value)
633 {
634 if (value & 1)
635 c++;
636 value >>= 1;
637 }
638 return c;
639 }
640
641 /* Utility function, which converts parameters from or32_opcode format to more binary form.
642 Parameters are stored in ti struct. */
643
644 static struct insn_op_struct *
645 parse_params (opcode, cur)
646 const struct or32_opcode * opcode;
647 struct insn_op_struct * cur;
648 {
649 char *args = opcode->args;
650 int i, type;
651
652 i = 0;
653 type = 0;
654 /* In case we don't have any parameters, we add dummy read from r0. */
655
656 if (!(*args))
657 {
658 cur->type = OPTYPE_REG | OPTYPE_OP | OPTYPE_LAST;
659 cur->data = 0;
660 debug (9, "#%08X %08X\n", cur->type, cur->data);
661 cur++;
662 return cur;
663 }
664
665 while (*args != '\0')
666 {
667 if (*args == 'r')
668 {
669 args++;
670 type |= OPTYPE_REG;
671 }
672 else if (ISALPHA (*args))
673 {
674 unsigned long arg;
675
676 arg = insn_extract (*args, opcode->encoding);
677 debug (9, "%s : %08X ------\n", opcode->name, arg);
678 if (letter_signed (*args))
679 {
680 type |= OPTYPE_SIG;
681 type |= ((num_ones (arg) - 1) << OPTYPE_SBIT_SHR) & OPTYPE_SBIT;
682 }
683
684 /* Split argument to sequences of consecutive ones. */
685 while (arg)
686 {
687 int shr = 0;
688 unsigned long tmp = arg, mask = 0;
689
690 while ((tmp & 1) == 0)
691 {
692 shr++;
693 tmp >>= 1;
694 }
695 while (tmp & 1)
696 {
697 mask++;
698 tmp >>= 1;
699 }
700 cur->type = type | shr;
701 cur->data = mask;
702 arg &= ~(((1 << mask) - 1) << shr);
703 debug (6, "|%08X %08X\n", cur->type, cur->data);
704 cur++;
705 }
706 args++;
707 }
708 else if (*args == '(')
709 {
710 /* Next param is displacement. Later we will treat them as one operand. */
711 cur--;
712 cur->type = type | cur->type | OPTYPE_DIS | OPTYPE_OP;
713 debug (9, ">%08X %08X\n", cur->type, cur->data);
714 cur++;
715 type = 0;
716 i++;
717 args++;
718 }
719 else if (*args == OPERAND_DELIM)
720 {
721 cur--;
722 cur->type = type | cur->type | OPTYPE_OP;
723 debug (9, ">%08X %08X\n", cur->type, cur->data);
724 cur++;
725 type = 0;
726 i++;
727 args++;
728 }
729 else if (*args == '0')
730 {
731 cur->type = type;
732 cur->data = 0;
733 debug (9, ">%08X %08X\n", cur->type, cur->data);
734 cur++;
735 type = 0;
736 i++;
737 args++;
738 }
739 else if (*args == ')')
740 args++;
741 else
742 {
743 fprintf (stderr, "%s : parse error in args.\n", opcode->name);
744 exit (1);
745 }
746 }
747
748 cur--;
749 cur->type = type | cur->type | OPTYPE_OP | OPTYPE_LAST;
750 debug (9, "#%08X %08X\n", cur->type, cur->data);
751 cur++;
752
753 return cur;
754 }
755
756 /* Constructs new automata based on or32_opcodes array. */
757
758 void
759 build_automata ()
760 {
761 unsigned int i;
762 unsigned long *end;
763 struct insn_op_struct *cur;
764
765 automata = (unsigned long *) malloc (MAX_AUTOMATA_SIZE * sizeof (unsigned long));
766 ti = (struct temp_insn_struct *) malloc (sizeof (struct temp_insn_struct) * or32_num_opcodes);
767
768 nuncovered = or32_num_opcodes;
769 printf ("Building automata... ");
770 /* Build temporary information about instructions. */
771 for (i = 0; i < or32_num_opcodes; i++)
772 {
773 unsigned long ones, zeros;
774 char *encoding = or32_opcodes[i].encoding;
775
776 ones = insn_extract('1', encoding);
777 zeros = insn_extract('0', encoding);
778
779 ti[i].insn_mask = ones | zeros;
780 ti[i].insn = ones;
781 ti[i].in_pass = curpass = 0;
782
783 /*debug(9, "%s: %s %08X %08X\n", or32_opcodes[i].name,
784 or32_opcodes[i].encoding, ti[i].insn_mask, ti[i].insn);*/
785 }
786
787 /* Until all are covered search for best criteria to separate them. */
788 end = cover_insn (automata, curpass, 0xFFFFFFFF);
789
790 if (end - automata > MAX_AUTOMATA_SIZE)
791 {
792 fprintf (stderr, "Automata too large. Increase MAX_AUTOMATA_SIZE.");
793 exit (1);
794 }
795
796 printf ("done, num uncovered: %i/%i.\n", nuncovered, or32_num_opcodes);
797 printf ("Parsing operands data... ");
798
799 op_data = (struct insn_op_struct *) malloc (MAX_OP_TABLE_SIZE * sizeof (struct insn_op_struct));
800 op_start = (struct insn_op_struct **) malloc (or32_num_opcodes * sizeof (struct insn_op_struct *));
801 cur = op_data;
802
803 for (i = 0; i < or32_num_opcodes; i++)
804 {
805 op_start[i] = cur;
806 cur = parse_params (&or32_opcodes[i], cur);
807
808 if (cur - op_data > MAX_OP_TABLE_SIZE)
809 {
810 fprintf (stderr, "Operands table too small, increase MAX_OP_TABLE_SIZE.\n");
811 exit (1);
812 }
813 }
814 printf ("done.\n");
815 }
816
817 void
818 destruct_automata ()
819 {
820 free (ti);
821 free (automata);
822 free (op_data);
823 free (op_start);
824 }
825
826 /* Decodes instruction and returns instruction index. */
827
828 int
829 insn_decode (insn)
830 unsigned int insn;
831 {
832 unsigned long *a = automata;
833 int i;
834
835 while (!(*a & LEAF_FLAG))
836 {
837 unsigned int first = *a;
838
839 debug (9, "%i ", a - automata);
840
841 a++;
842 i = (insn >> first) & *a;
843 a++;
844 if (!*(a + i))
845 {
846 /* Invalid instruction found? */
847 debug (9, "XXX\n", i);
848 return -1;
849 }
850 a = automata + *(a + i);
851 }
852
853 i = *a & ~LEAF_FLAG;
854
855 debug (9, "%i\n", i);
856
857 /* Final check - do we have direct match?
858 (based on or32_opcodes this should be the only possibility,
859 but in case of invalid/missing instruction we must perform a check) */
860 if ((ti[i].insn_mask & insn) == ti[i].insn)
861 return i;
862 else
863 return -1;
864 }
865
866 static char disassembled_str[50];
867 char *disassembled = &disassembled_str[0];
868
869 /* Automagically does zero- or sign- extension and also finds correct
870 sign bit position if sign extension is correct extension. Which extension
871 is proper is figured out from letter description. */
872
873 static unsigned long
874 extend_imm (imm, l)
875 unsigned long imm;
876 char l;
877 {
878 unsigned long mask;
879 int letter_bits;
880
881 /* First truncate all bits above valid range for this letter
882 in case it is zero extend. */
883 letter_bits = letter_range (l);
884 mask = (1 << letter_bits) - 1;
885 imm &= mask;
886
887 /* Do sign extend if this is the right one. */
888 if (letter_signed(l) && (imm >> (letter_bits - 1)))
889 imm |= (~mask);
890
891 return imm;
892 }
893
894 static unsigned long
895 or32_extract (param_ch, enc_initial, insn)
896 char param_ch;
897 char *enc_initial;
898 unsigned long insn;
899 {
900 char *enc;
901 unsigned long ret = 0;
902 int opc_pos = 0;
903 int param_pos = 0;
904
905 for (enc = enc_initial; *enc != '\0'; enc++)
906 if (*enc == param_ch)
907 {
908 if (enc - 2 >= enc_initial && (*(enc - 2) == '0') && (*(enc - 1) == 'x'))
909 continue;
910 else
911 param_pos++;
912 }
913
914 #if DEBUG
915 printf ("or32_extract: %x ", param_pos);
916 #endif
917 opc_pos = 32;
918
919 for (enc = enc_initial; *enc != '\0'; )
920 if ((*enc == '0') && (*(enc + 1) == 'x'))
921 {
922 opc_pos -= 4;
923 if ((param_ch == '0') || (param_ch == '1'))
924 {
925 unsigned long tmp = strtol (enc, NULL, 16);
926 #if DEBUG
927 printf (" enc=%s, tmp=%x ", enc, tmp);
928 #endif
929 if (param_ch == '0')
930 tmp = 15 - tmp;
931 ret |= tmp << opc_pos;
932 }
933 enc += 3;
934 }
935 else if ((*enc == '0') || (*enc == '1'))
936 {
937 opc_pos--;
938 if (param_ch == *enc)
939 ret |= 1 << opc_pos;
940 enc++;
941 }
942 else if (*enc == param_ch)
943 {
944 opc_pos--;
945 param_pos--;
946 #if DEBUG
947 printf ("\n ret=%x opc_pos=%x, param_pos=%x\n", ret, opc_pos, param_pos);
948 #endif
949 if (ISLOWER (param_ch))
950 ret -= ((insn >> opc_pos) & 0x1) << param_pos;
951 else
952 ret += ((insn >> opc_pos) & 0x1) << param_pos;
953 enc++;
954 }
955 else if (ISALPHA (*enc))
956 {
957 opc_pos--;
958 enc++;
959 }
960 else if (*enc == '-')
961 {
962 opc_pos--;
963 enc++;
964 }
965 else
966 enc++;
967
968 #if DEBUG
969 printf ("ret=%x\n", ret);
970 #endif
971 return ret;
972 }
973
974 /* Print register. Used only by print_insn. */
975
976 static void
977 or32_print_register (param_ch, encoding, insn)
978 char param_ch;
979 char *encoding;
980 unsigned long insn;
981 {
982 int regnum = or32_extract(param_ch, encoding, insn);
983
984 sprintf (disassembled, "%sr%d", disassembled, regnum);
985 }
986
987 /* Print immediate. Used only by print_insn. */
988
989 static void
990 or32_print_immediate (param_ch, encoding, insn)
991 char param_ch;
992 char *encoding;
993 unsigned long insn;
994 {
995 int imm = or32_extract (param_ch, encoding, insn);
996
997 imm = extend_imm (imm, param_ch);
998
999 if (letter_signed (param_ch))
1000 {
1001 if (imm < 0)
1002 sprintf (disassembled, "%s%d", disassembled, imm);
1003 else
1004 sprintf (disassembled, "%s0x%x", disassembled, imm);
1005 }
1006 else
1007 sprintf (disassembled, "%s%#x", disassembled, imm);
1008 }
1009
1010 /* Disassemble one instruction from insn to disassemble.
1011 Return the size of the instruction. */
1012
1013 int
1014 disassemble_insn (insn)
1015 unsigned long insn;
1016 {
1017 int index;
1018 index = insn_decode (insn);
1019
1020 if (index >= 0)
1021 {
1022 struct or32_opcode const *opcode = &or32_opcodes[index];
1023 char *s;
1024
1025 sprintf (disassembled, "%s ", opcode->name);
1026 for (s = opcode->args; *s != '\0'; ++s)
1027 {
1028 switch (*s)
1029 {
1030 case '\0':
1031 return 4;
1032
1033 case 'r':
1034 or32_print_register (*++s, opcode->encoding, insn);
1035 break;
1036
1037 default:
1038 if (strchr (opcode->encoding, *s))
1039 or32_print_immediate (*s, opcode->encoding, insn);
1040 else
1041 sprintf (disassembled, "%s%c", disassembled, *s);
1042 }
1043 }
1044 }
1045 else
1046 {
1047 /* This used to be %8x for binutils. */
1048 sprintf (disassembled, "%s.word 0x%08lx", disassembled, insn);
1049 }
1050
1051 return insn_len (insn);
1052 }
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