| blob | 3208b77f4f00cdef9a7fb2d04c0853745ded08b5 |
1 /* Opcode table header for m680[01234]0/m6888[12]/m68851.
2 Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 1999 Free Software Foundation.
4 This file is part of GDB, GAS, and the GNU binutils.
6 GDB, GAS, and the GNU binutils are free software; you can redistribute
7 them and/or modify them under the terms of the GNU General Public
8 License as published by the Free Software Foundation; either version
9 1, or (at your option) any later version.
11 GDB, GAS, and the GNU binutils are distributed in the hope that they
12 will be useful, but WITHOUT ANY WARRANTY; without even the implied
13 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
14 the GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this file; see the file COPYING. If not, write to the Free
18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
19 02111-1307, USA. */
21 /* These are used as bit flags for the arch field in the m68k_opcode
22 structure. */
23 #define _m68k_undef 0
24 #define m68000 0x001
26 #define m68010 0x002
27 #define m68020 0x004
28 #define m68030 0x008
30 gas will deal with the few differences. */
31 #define m68040 0x010
32 /* there is no 68050 */
33 #define m68060 0x020
34 #define m68881 0x040
36 #define m68851 0x080
38 #define mcf5200 0x200
39 #define mcf5206e 0x400
40 #define mcf5307 0x800
42 /* handy aliases */
43 #define m68040up (m68040 | m68060)
44 #define m68030up (m68030 | m68040up)
45 #define m68020up (m68020 | m68030up)
46 #define m68010up (m68010 | cpu32 | m68020up)
47 #define m68000up (m68000 | m68010up)
48 #define mcf (mcf5200 | mcf5206e | mcf5307)
50 #define mfloat (m68881 | m68882 | m68040 | m68060)
51 #define mmmu (m68851 | m68030 | m68040 | m68060)
53 /* The structure used to hold information for an opcode. */
55 struct m68k_opcode
56 {
57 /* The opcode name. */
59 /* The opcode itself. */
61 /* The mask used by the disassembler. */
63 /* The arguments. */
65 /* The architectures which support this opcode. */
67 };
69 /* The structure used to hold information for an opcode alias. */
71 struct m68k_opcode_alias
72 {
73 /* The alias name. */
75 /* The instruction for which this is an alias. */
77 };
79 /* We store four bytes of opcode for all opcodes because that is the
80 most any of them need. The actual length of an instruction is
81 always at least 2 bytes, and is as much longer as necessary to hold
82 the operands it has.
84 The match field is a mask saying which bits must match particular
85 opcode in order for an instruction to be an instance of that
86 opcode.
88 The args field is a string containing two characters for each
89 operand of the instruction. The first specifies the kind of
90 operand; the second, the place it is stored. */
92 /* Kinds of operands:
93 Characters used: AaBCcDdEFfGHIJkLlMmnOopQqRrSsTtU VvWXYZ0123|*~%;@!&$?/<>#^+-
95 D data register only. Stored as 3 bits.
96 A address register only. Stored as 3 bits.
97 a address register indirect only. Stored as 3 bits.
98 R either kind of register. Stored as 4 bits.
99 r either kind of register indirect only. Stored as 4 bits.
100 At the moment, used only for cas2 instruction.
101 F floating point coprocessor register only. Stored as 3 bits.
102 O an offset (or width): immediate data 0-31 or data register.
103 Stored as 6 bits in special format for BF... insns.
104 + autoincrement only. Stored as 3 bits (number of the address register).
105 - autodecrement only. Stored as 3 bits (number of the address register).
106 Q quick immediate data. Stored as 3 bits.
107 This matches an immediate operand only when value is in range 1 .. 8.
108 M moveq immediate data. Stored as 8 bits.
109 This matches an immediate operand only when value is in range -128..127
110 T trap vector immediate data. Stored as 4 bits.
112 k K-factor for fmove.p instruction. Stored as a 7-bit constant or
113 a three bit register offset, depending on the field type.
115 # immediate data. Stored in special places (b, w or l)
116 which say how many bits to store.
117 ^ immediate data for floating point instructions. Special places
118 are offset by 2 bytes from '#'...
119 B pc-relative address, converted to an offset
120 that is treated as immediate data.
121 d displacement and register. Stores the register as 3 bits
122 and stores the displacement in the entire second word.
124 C the CCR. No need to store it; this is just for filtering validity.
125 S the SR. No need to store, just as with CCR.
126 U the USP. No need to store, just as with CCR.
127 E the ACC. No need to store, just as with CCR.
128 G the MACSR. No need to store, just as with CCR.
129 H the MASK. No need to store, just as with CCR.
131 I Coprocessor ID. Not printed if 1. The Coprocessor ID is always
132 extracted from the 'd' field of word one, which means that an extended
133 coprocessor opcode can be skipped using the 'i' place, if needed.
135 s System Control register for the floating point coprocessor.
137 J Misc register for movec instruction, stored in 'j' format.
138 Possible values:
139 0x000 SFC Source Function Code reg [60, 40, 30, 20, 10]
140 0x001 DFC Data Function Code reg [60, 40, 30, 20, 10]
141 0x002 CACR Cache Control Register [60, 40, 30, 20]
142 0x003 TC MMU Translation Control [60, 40]
143 0x004 ITT0 Instruction Transparent
144 Translation reg 0 [60, 40]
145 0x005 ITT1 Instruction Transparent
146 Translation reg 1 [60, 40]
147 0x006 DTT0 Data Transparent
148 Translation reg 0 [60, 40]
149 0x007 DTT1 Data Transparent
150 Translation reg 1 [60, 40]
151 0x008 BUSCR Bus Control Register [60]
152 0x800 USP User Stack Pointer [60, 40, 30, 20, 10]
153 0x801 VBR Vector Base reg [60, 40, 30, 20, 10]
154 0x802 CAAR Cache Address Register [ 30, 20]
155 0x803 MSP Master Stack Pointer [ 40, 30, 20]
156 0x804 ISP Interrupt Stack Pointer [ 40, 30, 20]
157 0x805 MMUSR MMU Status reg [ 40]
158 0x806 URP User Root Pointer [60, 40]
159 0x807 SRP Supervisor Root Pointer [60, 40]
160 0x808 PCR Processor Configuration reg [60]
161 0xC00 ROMBAR ROM Base Address Register [520X]
162 0xC04 RAMBAR0 RAM Base Address Register 0 [520X]
163 0xC05 RAMBAR1 RAM Base Address Register 0 [520X]
164 0xC0F MBAR0 RAM Base Address Register 0 [520X]
166 L Register list of the type d0-d7/a0-a7 etc.
167 (New! Improved! Can also hold fp0-fp7, as well!)
168 The assembler tries to see if the registers match the insn by
169 looking at where the insn wants them stored.
171 l Register list like L, but with all the bits reversed.
172 Used for going the other way. . .
174 c cache identifier which may be "nc" for no cache, "ic"
175 for instruction cache, "dc" for data cache, or "bc"
176 for both caches. Used in cinv and cpush. Always
177 stored in position "d".
179 u Any register, with ``upper'' or ``lower'' specification. Used
180 in the mac instructions with size word.
182 The remainder are all stored as 6 bits using an address mode and a
183 register number; they differ in which addressing modes they match.
185 * all (modes 0-6,7.0-4)
186 ~ alterable memory (modes 2-6,7.0,7.1)
187 (not 0,1,7.2-4)
188 % alterable (modes 0-6,7.0,7.1)
189 (not 7.2-4)
190 ; data (modes 0,2-6,7.0-4)
191 (not 1)
192 @ data, but not immediate (modes 0,2-6,7.0-3)
193 (not 1,7.4)
194 ! control (modes 2,5,6,7.0-3)
195 (not 0,1,3,4,7.4)
196 & alterable control (modes 2,5,6,7.0,7.1)
197 (not 0,1,7.2-4)
198 $ alterable data (modes 0,2-6,7.0,7.1)
199 (not 1,7.2-4)
200 ? alterable control, or data register (modes 0,2,5,6,7.0,7.1)
201 (not 1,3,4,7.2-4)
202 / control, or data register (modes 0,2,5,6,7.0-3)
203 (not 1,3,4,7.4)
204 > *save operands (modes 2,4,5,6,7.0,7.1)
205 (not 0,1,3,7.2-4)
206 < *restore operands (modes 2,3,5,6,7.0-3)
207 (not 0,1,4,7.4)
209 coldfire move operands:
210 m (modes 0-4)
211 n (modes 5,7.2)
212 o (modes 6,7.0,7.1,7.3,7.4)
213 p (modes 0-5)
215 coldfire bset/bclr/btst/mulsl/mulul operands:
216 q (modes 0,2-5)
217 v (modes 0,2-5,7.0,7.1)
218 */
220 /* For the 68851: */
221 /*
222 I didn't use much imagination in choosing the
223 following codes, so many of them aren't very
224 mnemonic. -rab
226 0 32 bit pmmu register
227 Possible values:
228 000 TC Translation Control Register (68030, 68851)
230 1 16 bit pmmu register
231 111 AC Access Control (68851)
233 2 8 bit pmmu register
234 100 CAL Current Access Level (68851)
235 101 VAL Validate Access Level (68851)
236 110 SCC Stack Change Control (68851)
238 3 68030-only pmmu registers (32 bit)
239 010 TT0 Transparent Translation reg 0
240 (aka Access Control reg 0 -- AC0 -- on 68ec030)
241 011 TT1 Transparent Translation reg 1
242 (aka Access Control reg 1 -- AC1 -- on 68ec030)
244 W wide pmmu registers
245 Possible values:
246 001 DRP Dma Root Pointer (68851)
247 010 SRP Supervisor Root Pointer (68030, 68851)
248 011 CRP Cpu Root Pointer (68030, 68851)
250 f function code register (68030, 68851)
251 0 SFC
252 1 DFC
254 V VAL register only (68851)
256 X BADx, BACx (16 bit)
257 100 BAD Breakpoint Acknowledge Data (68851)
258 101 BAC Breakpoint Acknowledge Control (68851)
260 Y PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030)
261 Z PCSR (68851)
263 | memory (modes 2-6, 7.*)
265 t address test level (68030 only)
266 Stored as 3 bits, range 0-7.
267 Also used for breakpoint instruction now.
269 */
271 /* Places to put an operand, for non-general operands:
272 Characters used: BbCcDdghijkLlMmNnostWw123456789
274 s source, low bits of first word.
275 d dest, shifted 9 in first word
276 1 second word, shifted 12
277 2 second word, shifted 6
278 3 second word, shifted 0
279 4 third word, shifted 12
280 5 third word, shifted 6
281 6 third word, shifted 0
282 7 second word, shifted 7
283 8 second word, shifted 10
284 9 second word, shifted 5
285 D store in both place 1 and place 3; for divul and divsl.
286 B first word, low byte, for branch displacements
287 W second word (entire), for branch displacements
288 L second and third words (entire), for branch displacements
289 (also overloaded for move16)
290 b second word, low byte
291 w second word (entire) [variable word/long branch offset for dbra]
292 W second word (entire) (must be signed 16 bit value)
293 l second and third word (entire)
294 g variable branch offset for bra and similar instructions.
295 The place to store depends on the magnitude of offset.
296 t store in both place 7 and place 8; for floating point operations
297 c branch offset for cpBcc operations.
298 The place to store is word two if bit six of word one is zero,
299 and words two and three if bit six of word one is one.
300 i Increment by two, to skip over coprocessor extended operands. Only
301 works with the 'I' format.
302 k Dynamic K-factor field. Bits 6-4 of word 2, used as a register number.
303 Also used for dynamic fmovem instruction.
304 C floating point coprocessor constant - 7 bits. Also used for static
305 K-factors...
306 j Movec register #, stored in 12 low bits of second word.
307 m For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word
308 and remaining 3 bits of register shifted 9 bits in first word.
309 Indicate upper/lower in 1 bit shifted 7 bits in second word.
310 Use with `R' or `u' format.
311 n `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split
312 with MSB shifted 6 bits in first word and remaining 3 bits of
313 register shifted 9 bits in first word. No upper/lower
314 indication is done.) Use with `R' or `u' format.
315 o For M[S]ACw; 4 bits shifted 12 in second word (like `1').
316 Indicate upper/lower in 1 bit shifted 7 bits in second word.
317 Use with `R' or `u' format.
318 M For M[S]ACw; 4 bits in low bits of first word. Indicate
319 upper/lower in 1 bit shifted 6 bits in second word. Use with
320 `R' or `u' format.
321 N For M[S]ACw; 4 bits in low bits of second word. Indicate
322 upper/lower in 1 bit shifted 6 bits in second word. Use with
323 `R' or `u' format.
324 h shift indicator (scale factor), 1 bit shifted 10 in second word
326 Places to put operand, for general operands:
327 d destination, shifted 6 bits in first word
328 b source, at low bit of first word, and immediate uses one byte
329 w source, at low bit of first word, and immediate uses two bytes
330 l source, at low bit of first word, and immediate uses four bytes
331 s source, at low bit of first word.
332 Used sometimes in contexts where immediate is not allowed anyway.
333 f single precision float, low bit of 1st word, immediate uses 4 bytes
334 F double precision float, low bit of 1st word, immediate uses 8 bytes
335 x extended precision float, low bit of 1st word, immediate uses 12 bytes
336 p packed float, low bit of 1st word, immediate uses 12 bytes
337 */
344 /* end of m68k-opcode.h */