opcodes/ppc-opc.c

   1 /* ppc-opc.c -- PowerPC opcode list
   2    Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
   3    2005, 2006, 2007, 2008 Free Software Foundation, Inc.
   4    Written by Ian Lance Taylor, Cygnus Support
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this file; see the file COPYING.  If not, write to the
  20    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23 #include <stdio.h>
  24 #include "sysdep.h"
  25 #include "opcode/ppc.h"
  26 #include "opintl.h"
  27
  28 /* This file holds the PowerPC opcode table.  The opcode table
  29    includes almost all of the extended instruction mnemonics.  This
  30    permits the disassembler to use them, and simplifies the assembler
  31    logic, at the cost of increasing the table size.  The table is
  32    strictly constant data, so the compiler should be able to put it in
  33    the .text section.
  34
  35    This file also holds the operand table.  All knowledge about
  36    inserting operands into instructions and vice-versa is kept in this
  37    file.  */
  38 \f
  39 /* Local insertion and extraction functions.  */
  40
  41 static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **);
  42 static long extract_bat (unsigned long, ppc_cpu_t, int *);
  43 static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **);
  44 static long extract_bba (unsigned long, ppc_cpu_t, int *);
  45 static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **);
  46 static long extract_bdm (unsigned long, ppc_cpu_t, int *);
  47 static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **);
  48 static long extract_bdp (unsigned long, ppc_cpu_t, int *);
  49 static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **);
  50 static long extract_bo (unsigned long, ppc_cpu_t, int *);
  51 static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **);
  52 static long extract_boe (unsigned long, ppc_cpu_t, int *);
  53 static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
  54 static long extract_fxm (unsigned long, ppc_cpu_t, int *);
  55 static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
  56 static long extract_mbe (unsigned long, ppc_cpu_t, int *);
  57 static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
  58 static long extract_mb6 (unsigned long, ppc_cpu_t, int *);
  59 static long extract_nb (unsigned long, ppc_cpu_t, int *);
  60 static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **);
  61 static long extract_nsi (unsigned long, ppc_cpu_t, int *);
  62 static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **);
  63 static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **);
  64 static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **);
  65 static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **);
  66 static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **);
  67 static long extract_rbs (unsigned long, ppc_cpu_t, int *);
  68 static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **);
  69 static long extract_sh6 (unsigned long, ppc_cpu_t, int *);
  70 static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **);
  71 static long extract_spr (unsigned long, ppc_cpu_t, int *);
  72 static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **);
  73 static long extract_sprg (unsigned long, ppc_cpu_t, int *);
  74 static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
  75 static long extract_tbr (unsigned long, ppc_cpu_t, int *);
  76 static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
  77 static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
  78 static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
  79 static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
  80 static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
  81 static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
  82 static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
  83 static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
  84 \f
  85 /* The operands table.
  86
  87    The fields are bitm, shift, insert, extract, flags.
  88
  89    We used to put parens around the various additions, like the one
  90    for BA just below.  However, that caused trouble with feeble
  91    compilers with a limit on depth of a parenthesized expression, like
  92    (reportedly) the compiler in Microsoft Developer Studio 5.  So we
  93    omit the parens, since the macros are never used in a context where
  94    the addition will be ambiguous.  */
  95
  96 const struct powerpc_operand powerpc_operands[] =
  97 {
  98   /* The zero index is used to indicate the end of the list of
  99      operands.  */
 100 #define UNUSED 0
 101   { 0, 0, NULL, NULL, 0 },
 102
 103   /* The BA field in an XL form instruction.  */
 104 #define BA UNUSED + 1
 105   /* The BI field in a B form or XL form instruction.  */
 106 #define BI BA
 107 #define BI_MASK (0x1f << 16)
 108   { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
 109
 110   /* The BA field in an XL form instruction when it must be the same
 111      as the BT field in the same instruction.  */
 112 #define BAT BA + 1
 113   { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
 114
 115   /* The BB field in an XL form instruction.  */
 116 #define BB BAT + 1
 117 #define BB_MASK (0x1f << 11)
 118   { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR },
 119
 120   /* The BB field in an XL form instruction when it must be the same
 121      as the BA field in the same instruction.  */
 122 #define BBA BB + 1
 123   { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
 124
 125   /* The BD field in a B form instruction.  The lower two bits are
 126      forced to zero.  */
 127 #define BD BBA + 1
 128   { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 129
 130   /* The BD field in a B form instruction when absolute addressing is
 131      used.  */
 132 #define BDA BD + 1
 133   { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 134
 135   /* The BD field in a B form instruction when the - modifier is used.
 136      This sets the y bit of the BO field appropriately.  */
 137 #define BDM BDA + 1
 138   { 0xfffc, 0, insert_bdm, extract_bdm,
 139       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 140
 141   /* The BD field in a B form instruction when the - modifier is used
 142      and absolute address is used.  */
 143 #define BDMA BDM + 1
 144   { 0xfffc, 0, insert_bdm, extract_bdm,
 145       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 146
 147   /* The BD field in a B form instruction when the + modifier is used.
 148      This sets the y bit of the BO field appropriately.  */
 149 #define BDP BDMA + 1
 150   { 0xfffc, 0, insert_bdp, extract_bdp,
 151       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 152
 153   /* The BD field in a B form instruction when the + modifier is used
 154      and absolute addressing is used.  */
 155 #define BDPA BDP + 1
 156   { 0xfffc, 0, insert_bdp, extract_bdp,
 157       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 158
 159   /* The BF field in an X or XL form instruction.  */
 160 #define BF BDPA + 1
 161   /* The CRFD field in an X form instruction.  */
 162 #define CRFD BF
 163   { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
 164
 165   /* The BF field in an X or XL form instruction.  */
 166 #define BFF BF + 1
 167   { 0x7, 23, NULL, NULL, 0 },
 168
 169   /* An optional BF field.  This is used for comparison instructions,
 170      in which an omitted BF field is taken as zero.  */
 171 #define OBF BFF + 1
 172   { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 173
 174   /* The BFA field in an X or XL form instruction.  */
 175 #define BFA OBF + 1
 176   { 0x7, 18, NULL, NULL, PPC_OPERAND_CR },
 177
 178   /* The BO field in a B form instruction.  Certain values are
 179      illegal.  */
 180 #define BO BFA + 1
 181 #define BO_MASK (0x1f << 21)
 182   { 0x1f, 21, insert_bo, extract_bo, 0 },
 183
 184   /* The BO field in a B form instruction when the + or - modifier is
 185      used.  This is like the BO field, but it must be even.  */
 186 #define BOE BO + 1
 187   { 0x1e, 21, insert_boe, extract_boe, 0 },
 188
 189 #define BH BOE + 1
 190   { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
 191
 192   /* The BT field in an X or XL form instruction.  */
 193 #define BT BH + 1
 194   { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR },
 195
 196   /* The condition register number portion of the BI field in a B form
 197      or XL form instruction.  This is used for the extended
 198      conditional branch mnemonics, which set the lower two bits of the
 199      BI field.  This field is optional.  */
 200 #define CR BT + 1
 201   { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 202
 203   /* The CRB field in an X form instruction.  */
 204 #define CRB CR + 1
 205   /* The MB field in an M form instruction.  */
 206 #define MB CRB
 207 #define MB_MASK (0x1f << 6)
 208   { 0x1f, 6, NULL, NULL, 0 },
 209
 210   /* The CRFS field in an X form instruction.  */
 211 #define CRFS CRB + 1
 212   { 0x7, 0, NULL, NULL, PPC_OPERAND_CR },
 213
 214   /* The CT field in an X form instruction.  */
 215 #define CT CRFS + 1
 216   /* The MO field in an mbar instruction.  */
 217 #define MO CT
 218   { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 219
 220   /* The D field in a D form instruction.  This is a displacement off
 221      a register, and implies that the next operand is a register in
 222      parentheses.  */
 223 #define D CT + 1
 224   { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 225
 226   /* The DE field in a DE form instruction.  This is like D, but is 12
 227      bits only.  */
 228 #define DE D + 1
 229   { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 230
 231   /* The DES field in a DES form instruction.  This is like DS, but is 14
 232      bits only (12 stored.)  */
 233 #define DES DE + 1
 234   { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 235
 236   /* The DQ field in a DQ form instruction.  This is like D, but the
 237      lower four bits are forced to zero. */
 238 #define DQ DES + 1
 239   { 0xfff0, 0, NULL, NULL,
 240     PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
 241
 242   /* The DS field in a DS form instruction.  This is like D, but the
 243      lower two bits are forced to zero.  */
 244 #define DS DQ + 1
 245   { 0xfffc, 0, NULL, NULL,
 246     PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
 247
 248   /* The DUIS field in a XFX form instruction, 10 bits unsigned imediate */
 249 #define DUIS DS + 1
 250   { 0x3ff, 11, NULL, NULL, 0 },
 251
 252   /* The E field in a wrteei instruction.  */
 253   /* And the W bit in the pair singles instructions.  */
 254 #define E DUIS + 1
 255 #define PSW E
 256   { 0x1, 15, NULL, NULL, 0 },
 257
 258   /* The FL1 field in a POWER SC form instruction.  */
 259 #define FL1 E + 1
 260   /* The U field in an X form instruction.  */
 261 #define U FL1
 262   { 0xf, 12, NULL, NULL, 0 },
 263
 264   /* The FL2 field in a POWER SC form instruction.  */
 265 #define FL2 FL1 + 1
 266   { 0x7, 2, NULL, NULL, 0 },
 267
 268   /* The FLM field in an XFL form instruction.  */
 269 #define FLM FL2 + 1
 270   { 0xff, 17, NULL, NULL, 0 },
 271
 272   /* The FRA field in an X or A form instruction.  */
 273 #define FRA FLM + 1
 274 #define FRA_MASK (0x1f << 16)
 275   { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
 276
 277   /* The FRB field in an X or A form instruction.  */
 278 #define FRB FRA + 1
 279 #define FRB_MASK (0x1f << 11)
 280   { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
 281
 282   /* The FRC field in an A form instruction.  */
 283 #define FRC FRB + 1
 284 #define FRC_MASK (0x1f << 6)
 285   { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
 286
 287   /* The FRS field in an X form instruction or the FRT field in a D, X
 288      or A form instruction.  */
 289 #define FRS FRC + 1
 290 #define FRT FRS
 291   { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
 292
 293   /* The FXM field in an XFX instruction.  */
 294 #define FXM FRS + 1
 295   { 0xff, 12, insert_fxm, extract_fxm, 0 },
 296
 297   /* Power4 version for mfcr.  */
 298 #define FXM4 FXM + 1
 299   { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
 300
 301   /* The L field in a D or X form instruction.  */
 302 #define L FXM4 + 1
 303   { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 304
 305   /* The LEV field in a POWER SVC form instruction.  */
 306 #define SVC_LEV L + 1
 307   { 0x7f, 5, NULL, NULL, 0 },
 308
 309   /* The LEV field in an SC form instruction.  */
 310 #define LEV SVC_LEV + 1
 311   { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
 312
 313   /* The LI field in an I form instruction.  The lower two bits are
 314      forced to zero.  */
 315 #define LI LEV + 1
 316   { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 317
 318   /* The LI field in an I form instruction when used as an absolute
 319      address.  */
 320 #define LIA LI + 1
 321   { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 322
 323   /* The LS field in an X (sync) form instruction.  */
 324 #define LS LIA + 1
 325   { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 326
 327   /* The ME field in an M form instruction.  */
 328 #define ME LS + 1
 329 #define ME_MASK (0x1f << 1)
 330   { 0x1f, 1, NULL, NULL, 0 },
 331
 332   /* The MB and ME fields in an M form instruction expressed a single
 333      operand which is a bitmask indicating which bits to select.  This
 334      is a two operand form using PPC_OPERAND_NEXT.  See the
 335      description in opcode/ppc.h for what this means.  */
 336 #define MBE ME + 1
 337   { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
 338   { -1, 0, insert_mbe, extract_mbe, 0 },
 339
 340   /* The MB or ME field in an MD or MDS form instruction.  The high
 341      bit is wrapped to the low end.  */
 342 #define MB6 MBE + 2
 343 #define ME6 MB6
 344 #define MB6_MASK (0x3f << 5)
 345   { 0x3f, 5, insert_mb6, extract_mb6, 0 },
 346
 347   /* The NB field in an X form instruction.  The value 32 is stored as
 348      0.  */
 349 #define NB MB6 + 1
 350   { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
 351
 352   /* The NSI field in a D form instruction.  This is the same as the
 353      SI field, only negated.  */
 354 #define NSI NB + 1
 355   { 0xffff, 0, insert_nsi, extract_nsi,
 356       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 357
 358   /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */
 359 #define RA NSI + 1
 360 #define RA_MASK (0x1f << 16)
 361   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
 362
 363   /* As above, but 0 in the RA field means zero, not r0.  */
 364 #define RA0 RA + 1
 365   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
 366
 367   /* The RA field in the DQ form lq instruction, which has special
 368      value restrictions.  */
 369 #define RAQ RA0 + 1
 370   { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
 371
 372   /* The RA field in a D or X form instruction which is an updating
 373      load, which means that the RA field may not be zero and may not
 374      equal the RT field.  */
 375 #define RAL RAQ + 1
 376   { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
 377
 378   /* The RA field in an lmw instruction, which has special value
 379      restrictions.  */
 380 #define RAM RAL + 1
 381   { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
 382
 383   /* The RA field in a D or X form instruction which is an updating
 384      store or an updating floating point load, which means that the RA
 385      field may not be zero.  */
 386 #define RAS RAM + 1
 387   { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
 388
 389   /* The RA field of the tlbwe instruction, which is optional.  */
 390 #define RAOPT RAS + 1
 391   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 392
 393   /* The RB field in an X, XO, M, or MDS form instruction.  */
 394 #define RB RAOPT + 1
 395 #define RB_MASK (0x1f << 11)
 396   { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
 397
 398   /* The RB field in an X form instruction when it must be the same as
 399      the RS field in the instruction.  This is used for extended
 400      mnemonics like mr.  */
 401 #define RBS RB + 1
 402   { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
 403
 404   /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
 405      instruction or the RT field in a D, DS, X, XFX or XO form
 406      instruction.  */
 407 #define RS RBS + 1
 408 #define RT RS
 409 #define RT_MASK (0x1f << 21)
 410   { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
 411
 412   /* The RS and RT fields of the DS form stq instruction, which have
 413      special value restrictions.  */
 414 #define RSQ RS + 1
 415 #define RTQ RSQ
 416   { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
 417
 418   /* The RS field of the tlbwe instruction, which is optional.  */
 419 #define RSO RSQ + 1
 420 #define RTO RSO
 421   { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 422
 423   /* The SH field in an X or M form instruction.  */
 424 #define SH RSO + 1
 425 #define SH_MASK (0x1f << 11)
 426   /* The other UIMM field in a EVX form instruction.  */
 427 #define EVUIMM SH
 428   { 0x1f, 11, NULL, NULL, 0 },
 429
 430   /* The SH field in an MD form instruction.  This is split.  */
 431 #define SH6 SH + 1
 432 #define SH6_MASK ((0x1f << 11) | (1 << 1))
 433   { 0x3f, -1, insert_sh6, extract_sh6, 0 },
 434
 435   /* The SH field of the tlbwe instruction, which is optional.  */
 436 #define SHO SH6 + 1
 437   { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
 438
 439   /* The SI field in a D form instruction.  */
 440 #define SI SHO + 1
 441   { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
 442
 443   /* The SI field in a D form instruction when we accept a wide range
 444      of positive values.  */
 445 #define SISIGNOPT SI + 1
 446   { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 447
 448   /* The SPR field in an XFX form instruction.  This is flipped--the
 449      lower 5 bits are stored in the upper 5 and vice- versa.  */
 450 #define SPR SISIGNOPT + 1
 451 #define PMR SPR
 452 #define SPR_MASK (0x3ff << 11)
 453   { 0x3ff, 11, insert_spr, extract_spr, 0 },
 454
 455   /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
 456 #define SPRBAT SPR + 1
 457 #define SPRBAT_MASK (0x3 << 17)
 458   { 0x3, 17, NULL, NULL, 0 },
 459
 460   /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
 461 #define SPRG SPRBAT + 1
 462   { 0x1f, 16, insert_sprg, extract_sprg, 0 },
 463
 464   /* The SR field in an X form instruction.  */
 465 #define SR SPRG + 1
 466   { 0xf, 16, NULL, NULL, 0 },
 467
 468   /* The STRM field in an X AltiVec form instruction.  */
 469 #define STRM SR + 1
 470   /* The T field in a tlbilx form instruction.  */
 471 #define T STRM
 472   { 0x3, 21, NULL, NULL, 0 },
 473
 474   /* The SV field in a POWER SC form instruction.  */
 475 #define SV STRM + 1
 476   { 0x3fff, 2, NULL, NULL, 0 },
 477
 478   /* The TBR field in an XFX form instruction.  This is like the SPR
 479      field, but it is optional.  */
 480 #define TBR SV + 1
 481   { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
 482
 483   /* The TO field in a D or X form instruction.  */
 484 #define TO TBR + 1
 485 #define DUI TO
 486 #define TO_MASK (0x1f << 21)
 487   { 0x1f, 21, NULL, NULL, 0 },
 488
 489   /* The UI field in a D form instruction.  */
 490 #define UI TO + 1
 491   { 0xffff, 0, NULL, NULL, 0 },
 492
 493   /* The VA field in a VA, VX or VXR form instruction.  */
 494 #define VA UI + 1
 495   { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
 496
 497   /* The VB field in a VA, VX or VXR form instruction.  */
 498 #define VB VA + 1
 499   { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
 500
 501   /* The VC field in a VA form instruction.  */
 502 #define VC VB + 1
 503   { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
 504
 505   /* The VD or VS field in a VA, VX, VXR or X form instruction.  */
 506 #define VD VC + 1
 507 #define VS VD
 508   { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
 509
 510   /* The SIMM field in a VX form instruction, and TE in Z form.  */
 511 #define SIMM VD + 1
 512 #define TE SIMM
 513   { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
 514
 515   /* The UIMM field in a VX form instruction.  */
 516 #define UIMM SIMM + 1
 517   { 0x1f, 16, NULL, NULL, 0 },
 518
 519   /* The SHB field in a VA form instruction.  */
 520 #define SHB UIMM + 1
 521   { 0xf, 6, NULL, NULL, 0 },
 522
 523   /* The other UIMM field in a half word EVX form instruction.  */
 524 #define EVUIMM_2 SHB + 1
 525   { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
 526
 527   /* The other UIMM field in a word EVX form instruction.  */
 528 #define EVUIMM_4 EVUIMM_2 + 1
 529   { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
 530
 531   /* The other UIMM field in a double EVX form instruction.  */
 532 #define EVUIMM_8 EVUIMM_4 + 1
 533   { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
 534
 535   /* The WS field.  */
 536 #define WS EVUIMM_8 + 1
 537   { 0x7, 11, NULL, NULL, 0 },
 538
 539   /* PowerPC paired singles extensions.  */
 540   /* W bit in the pair singles instructions for x type instructions.  */
 541 #define PSWM WS + 1
 542   {  0x1, 10, 0, 0, 0 },
 543
 544   /* IDX bits for quantization in the pair singles instructions.  */
 545 #define PSQ PSWM + 1
 546   {  0x7, 12, 0, 0, 0 },
 547
 548   /* IDX bits for quantization in the pair singles x-type instructions.  */
 549 #define PSQM PSQ + 1
 550   {  0x7, 7, 0, 0, 0 },
 551
 552   /* Smaller D field for quantization in the pair singles instructions.  */
 553 #define PSD PSQM + 1
 554   {  0xfff, 0, 0, 0,  PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 555
 556 #define A_L PSD + 1
 557 #define W A_L
 558 #define MTMSRD_L W
 559   { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
 560
 561 #define RMC MTMSRD_L + 1
 562   { 0x3, 9, NULL, NULL, 0 },
 563
 564 #define R RMC + 1
 565   { 0x1, 16, NULL, NULL, 0 },
 566
 567 #define SP R + 1
 568   { 0x3, 19, NULL, NULL, 0 },
 569
 570 #define S SP + 1
 571   { 0x1, 20, NULL, NULL, 0 },
 572
 573   /* SH field starting at bit position 16.  */
 574 #define SH16 S + 1
 575   /* The DCM and DGM fields in a Z form instruction.  */
 576 #define DCM SH16
 577 #define DGM DCM
 578   { 0x3f, 10, NULL, NULL, 0 },
 579
 580   /* The EH field in larx instruction.  */
 581 #define EH SH16 + 1
 582   { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
 583
 584   /* The L field in an mtfsf or XFL form instruction.  */
 585 #define XFL_L EH + 1
 586   { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
 587
 588   /* Xilinx APU related masks and macros */
 589 #define FCRT XFL_L + 1
 590 #define FCRT_MASK (0x1f << 21)
 591   { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
 592
 593   /* Xilinx FSL related masks and macros */
 594 #define FSL FCRT + 1
 595 #define FSL_MASK (0x1f << 11)
 596   { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
 597
 598   /* Xilinx UDI related masks and macros */
 599 #define URT FSL + 1
 600   { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
 601
 602 #define URA URT + 1
 603   { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
 604
 605 #define URB URA + 1
 606   { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
 607
 608 #define URC URB + 1
 609   { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
 610
 611   /* The XT and XS fields in an XX1 or XX3 form instruction.  This is split.  */
 612 #define XS6 URC + 1
 613 #define XT6 XS6
 614   { 0x3f, -1, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
 615
 616   /* The XA field in an XX3 form instruction.  This is split.  */
 617 #define XA6 XT6 + 1
 618   { 0x3f, -1, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
 619
 620   /* The XB field in an XX3 form instruction.  This is split.  */
 621 #define XB6 XA6 + 1
 622   { 0x3f, -1, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
 623
 624   /* The XB field in an XX3 form instruction when it must be the same as
 625      the XA field in the instruction.  This is used in extended mnemonics
 626      like xvmovdp.  This is split.  */
 627 #define XB6S XB6 + 1
 628   { 0x3f, -1, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
 629
 630   /* The DM field in an XX3 form instruction.  */
 631 #define DM XB6S + 1
 632   { 0x3, 8, NULL, NULL, 0 },
 633 };
 634
 635 const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
 636                                            / sizeof (powerpc_operands[0]));
 637
 638 /* The functions used to insert and extract complicated operands.  */
 639
 640 /* The BA field in an XL form instruction when it must be the same as
 641    the BT field in the same instruction.  This operand is marked FAKE.
 642    The insertion function just copies the BT field into the BA field,
 643    and the extraction function just checks that the fields are the
 644    same.  */
 645
 646 static unsigned long
 647 insert_bat (unsigned long insn,
 648             long value ATTRIBUTE_UNUSED,
 649             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 650             const char **errmsg ATTRIBUTE_UNUSED)
 651 {
 652   return insn | (((insn >> 21) & 0x1f) << 16);
 653 }
 654
 655 static long
 656 extract_bat (unsigned long insn,
 657              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 658              int *invalid)
 659 {
 660   if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
 661     *invalid = 1;
 662   return 0;
 663 }
 664
 665 /* The BB field in an XL form instruction when it must be the same as
 666    the BA field in the same instruction.  This operand is marked FAKE.
 667    The insertion function just copies the BA field into the BB field,
 668    and the extraction function just checks that the fields are the
 669    same.  */
 670
 671 static unsigned long
 672 insert_bba (unsigned long insn,
 673             long value ATTRIBUTE_UNUSED,
 674             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 675             const char **errmsg ATTRIBUTE_UNUSED)
 676 {
 677   return insn | (((insn >> 16) & 0x1f) << 11);
 678 }
 679
 680 static long
 681 extract_bba (unsigned long insn,
 682              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 683              int *invalid)
 684 {
 685   if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
 686     *invalid = 1;
 687   return 0;
 688 }
 689
 690 /* The BD field in a B form instruction when the - modifier is used.
 691    This modifier means that the branch is not expected to be taken.
 692    For chips built to versions of the architecture prior to version 2
 693    (ie. not Power4 compatible), we set the y bit of the BO field to 1
 694    if the offset is negative.  When extracting, we require that the y
 695    bit be 1 and that the offset be positive, since if the y bit is 0
 696    we just want to print the normal form of the instruction.
 697    Power4 compatible targets use two bits, "a", and "t", instead of
 698    the "y" bit.  "at" == 00 => no hint, "at" == 01 => unpredictable,
 699    "at" == 10 => not taken, "at" == 11 => taken.  The "t" bit is 00001
 700    in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
 701    for branch on CTR.  We only handle the taken/not-taken hint here.
 702    Note that we don't relax the conditions tested here when
 703    disassembling with -Many because insns using extract_bdm and
 704    extract_bdp always occur in pairs.  One or the other will always
 705    be valid.  */
 706
 707 static unsigned long
 708 insert_bdm (unsigned long insn,
 709             long value,
 710             ppc_cpu_t dialect,
 711             const char **errmsg ATTRIBUTE_UNUSED)
 712 {
 713   if ((dialect & PPC_OPCODE_POWER4) == 0)
 714     {
 715       if ((value & 0x8000) != 0)
 716         insn |= 1 << 21;
 717     }
 718   else
 719     {
 720       if ((insn & (0x14 << 21)) == (0x04 << 21))
 721         insn |= 0x02 << 21;
 722       else if ((insn & (0x14 << 21)) == (0x10 << 21))
 723         insn |= 0x08 << 21;
 724     }
 725   return insn | (value & 0xfffc);
 726 }
 727
 728 static long
 729 extract_bdm (unsigned long insn,
 730              ppc_cpu_t dialect,
 731              int *invalid)
 732 {
 733   if ((dialect & PPC_OPCODE_POWER4) == 0)
 734     {
 735       if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
 736         *invalid = 1;
 737     }
 738   else
 739     {
 740       if ((insn & (0x17 << 21)) != (0x06 << 21)
 741           && (insn & (0x1d << 21)) != (0x18 << 21))
 742         *invalid = 1;
 743     }
 744
 745   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 746 }
 747
 748 /* The BD field in a B form instruction when the + modifier is used.
 749    This is like BDM, above, except that the branch is expected to be
 750    taken.  */
 751
 752 static unsigned long
 753 insert_bdp (unsigned long insn,
 754             long value,
 755             ppc_cpu_t dialect,
 756             const char **errmsg ATTRIBUTE_UNUSED)
 757 {
 758   if ((dialect & PPC_OPCODE_POWER4) == 0)
 759     {
 760       if ((value & 0x8000) == 0)
 761         insn |= 1 << 21;
 762     }
 763   else
 764     {
 765       if ((insn & (0x14 << 21)) == (0x04 << 21))
 766         insn |= 0x03 << 21;
 767       else if ((insn & (0x14 << 21)) == (0x10 << 21))
 768         insn |= 0x09 << 21;
 769     }
 770   return insn | (value & 0xfffc);
 771 }
 772
 773 static long
 774 extract_bdp (unsigned long insn,
 775              ppc_cpu_t dialect,
 776              int *invalid)
 777 {
 778   if ((dialect & PPC_OPCODE_POWER4) == 0)
 779     {
 780       if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
 781         *invalid = 1;
 782     }
 783   else
 784     {
 785       if ((insn & (0x17 << 21)) != (0x07 << 21)
 786           && (insn & (0x1d << 21)) != (0x19 << 21))
 787         *invalid = 1;
 788     }
 789
 790   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 791 }
 792
 793 /* Check for legal values of a BO field.  */
 794
 795 static int
 796 valid_bo (long value, ppc_cpu_t dialect, int extract)
 797 {
 798   if ((dialect & PPC_OPCODE_POWER4) == 0)
 799     {
 800       int valid;
 801       /* Certain encodings have bits that are required to be zero.
 802          These are (z must be zero, y may be anything):
 803              001zy
 804              011zy
 805              1z00y
 806              1z01y
 807              1z1zz
 808       */
 809       switch (value & 0x14)
 810         {
 811         default:
 812         case 0:
 813           valid = 1;
 814           break;
 815         case 0x4:
 816           valid = (value & 0x2) == 0;
 817           break;
 818         case 0x10:
 819           valid = (value & 0x8) == 0;
 820           break;
 821         case 0x14:
 822           valid = value == 0x14;
 823           break;
 824         }
 825       /* When disassembling with -Many, accept power4 encodings too.  */
 826       if (valid
 827           || (dialect & PPC_OPCODE_ANY) == 0
 828           || !extract)
 829         return valid;
 830     }
 831
 832   /* Certain encodings have bits that are required to be zero.
 833      These are (z must be zero, a & t may be anything):
 834          0000z
 835          0001z
 836          0100z
 837          0101z
 838          001at
 839          011at
 840          1a00t
 841          1a01t
 842          1z1zz
 843   */
 844   if ((value & 0x14) == 0)
 845     return (value & 0x1) == 0;
 846   else if ((value & 0x14) == 0x14)
 847     return value == 0x14;
 848   else
 849     return 1;
 850 }
 851
 852 /* The BO field in a B form instruction.  Warn about attempts to set
 853    the field to an illegal value.  */
 854
 855 static unsigned long
 856 insert_bo (unsigned long insn,
 857            long value,
 858            ppc_cpu_t dialect,
 859            const char **errmsg)
 860 {
 861   if (!valid_bo (value, dialect, 0))
 862     *errmsg = _("invalid conditional option");
 863   return insn | ((value & 0x1f) << 21);
 864 }
 865
 866 static long
 867 extract_bo (unsigned long insn,
 868             ppc_cpu_t dialect,
 869             int *invalid)
 870 {
 871   long value;
 872
 873   value = (insn >> 21) & 0x1f;
 874   if (!valid_bo (value, dialect, 1))
 875     *invalid = 1;
 876   return value;
 877 }
 878
 879 /* The BO field in a B form instruction when the + or - modifier is
 880    used.  This is like the BO field, but it must be even.  When
 881    extracting it, we force it to be even.  */
 882
 883 static unsigned long
 884 insert_boe (unsigned long insn,
 885             long value,
 886             ppc_cpu_t dialect,
 887             const char **errmsg)
 888 {
 889   if (!valid_bo (value, dialect, 0))
 890     *errmsg = _("invalid conditional option");
 891   else if ((value & 1) != 0)
 892     *errmsg = _("attempt to set y bit when using + or - modifier");
 893
 894   return insn | ((value & 0x1f) << 21);
 895 }
 896
 897 static long
 898 extract_boe (unsigned long insn,
 899              ppc_cpu_t dialect,
 900              int *invalid)
 901 {
 902   long value;
 903
 904   value = (insn >> 21) & 0x1f;
 905   if (!valid_bo (value, dialect, 1))
 906     *invalid = 1;
 907   return value & 0x1e;
 908 }
 909
 910 /* FXM mask in mfcr and mtcrf instructions.  */
 911
 912 static unsigned long
 913 insert_fxm (unsigned long insn,
 914             long value,
 915             ppc_cpu_t dialect,
 916             const char **errmsg)
 917 {
 918   /* If we're handling the mfocrf and mtocrf insns ensure that exactly
 919      one bit of the mask field is set.  */
 920   if ((insn & (1 << 20)) != 0)
 921     {
 922       if (value == 0 || (value & -value) != value)
 923         {
 924           *errmsg = _("invalid mask field");
 925           value = 0;
 926         }
 927     }
 928
 929   /* If the optional field on mfcr is missing that means we want to use
 930      the old form of the instruction that moves the whole cr.  In that
 931      case we'll have VALUE zero.  There doesn't seem to be a way to
 932      distinguish this from the case where someone writes mfcr %r3,0.  */
 933   else if (value == 0)
 934     ;
 935
 936   /* If only one bit of the FXM field is set, we can use the new form
 937      of the instruction, which is faster.  Unlike the Power4 branch hint
 938      encoding, this is not backward compatible.  Do not generate the
 939      new form unless -mpower4 has been given, or -many and the two
 940      operand form of mfcr was used.  */
 941   else if ((value & -value) == value
 942            && ((dialect & PPC_OPCODE_POWER4) != 0
 943                || ((dialect & PPC_OPCODE_ANY) != 0
 944                    && (insn & (0x3ff << 1)) == 19 << 1)))
 945     insn |= 1 << 20;
 946
 947   /* Any other value on mfcr is an error.  */
 948   else if ((insn & (0x3ff << 1)) == 19 << 1)
 949     {
 950       *errmsg = _("ignoring invalid mfcr mask");
 951       value = 0;
 952     }
 953
 954   return insn | ((value & 0xff) << 12);
 955 }
 956
 957 static long
 958 extract_fxm (unsigned long insn,
 959              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 960              int *invalid)
 961 {
 962   long mask = (insn >> 12) & 0xff;
 963
 964   /* Is this a Power4 insn?  */
 965   if ((insn & (1 << 20)) != 0)
 966     {
 967       /* Exactly one bit of MASK should be set.  */
 968       if (mask == 0 || (mask & -mask) != mask)
 969         *invalid = 1;
 970     }
 971
 972   /* Check that non-power4 form of mfcr has a zero MASK.  */
 973   else if ((insn & (0x3ff << 1)) == 19 << 1)
 974     {
 975       if (mask != 0)
 976         *invalid = 1;
 977     }
 978
 979   return mask;
 980 }
 981
 982 /* The MB and ME fields in an M form instruction expressed as a single
 983    operand which is itself a bitmask.  The extraction function always
 984    marks it as invalid, since we never want to recognize an
 985    instruction which uses a field of this type.  */
 986
 987 static unsigned long
 988 insert_mbe (unsigned long insn,
 989             long value,
 990             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 991             const char **errmsg)
 992 {
 993   unsigned long uval, mask;
 994   int mb, me, mx, count, last;
 995
 996   uval = value;
 997
 998   if (uval == 0)
 999     {
1000       *errmsg = _("illegal bitmask");
1001       return insn;
1002     }
1003
1004   mb = 0;
1005   me = 32;
1006   if ((uval & 1) != 0)
1007     last = 1;
1008   else
1009     last = 0;
1010   count = 0;
1011
1012   /* mb: location of last 0->1 transition */
1013   /* me: location of last 1->0 transition */
1014   /* count: # transitions */
1015
1016   for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1017     {
1018       if ((uval & mask) && !last)
1019         {
1020           ++count;
1021           mb = mx;
1022           last = 1;
1023         }
1024       else if (!(uval & mask) && last)
1025         {
1026           ++count;
1027           me = mx;
1028           last = 0;
1029         }
1030     }
1031   if (me == 0)
1032     me = 32;
1033
1034   if (count != 2 && (count != 0 || ! last))
1035     *errmsg = _("illegal bitmask");
1036
1037   return insn | (mb << 6) | ((me - 1) << 1);
1038 }
1039
1040 static long
1041 extract_mbe (unsigned long insn,
1042              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1043              int *invalid)
1044 {
1045   long ret;
1046   int mb, me;
1047   int i;
1048
1049   *invalid = 1;
1050
1051   mb = (insn >> 6) & 0x1f;
1052   me = (insn >> 1) & 0x1f;
1053   if (mb < me + 1)
1054     {
1055       ret = 0;
1056       for (i = mb; i <= me; i++)
1057         ret |= 1L << (31 - i);
1058     }
1059   else if (mb == me + 1)
1060     ret = ~0;
1061   else /* (mb > me + 1) */
1062     {
1063       ret = ~0;
1064       for (i = me + 1; i < mb; i++)
1065         ret &= ~(1L << (31 - i));
1066     }
1067   return ret;
1068 }
1069
1070 /* The MB or ME field in an MD or MDS form instruction.  The high bit
1071    is wrapped to the low end.  */
1072
1073 static unsigned long
1074 insert_mb6 (unsigned long insn,
1075             long value,
1076             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1077             const char **errmsg ATTRIBUTE_UNUSED)
1078 {
1079   return insn | ((value & 0x1f) << 6) | (value & 0x20);
1080 }
1081
1082 static long
1083 extract_mb6 (unsigned long insn,
1084              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1085              int *invalid ATTRIBUTE_UNUSED)
1086 {
1087   return ((insn >> 6) & 0x1f) | (insn & 0x20);
1088 }
1089
1090 /* The NB field in an X form instruction.  The value 32 is stored as
1091    0.  */
1092
1093 static long
1094 extract_nb (unsigned long insn,
1095             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1096             int *invalid ATTRIBUTE_UNUSED)
1097 {
1098   long ret;
1099
1100   ret = (insn >> 11) & 0x1f;
1101   if (ret == 0)
1102     ret = 32;
1103   return ret;
1104 }
1105
1106 /* The NSI field in a D form instruction.  This is the same as the SI
1107    field, only negated.  The extraction function always marks it as
1108    invalid, since we never want to recognize an instruction which uses
1109    a field of this type.  */
1110
1111 static unsigned long
1112 insert_nsi (unsigned long insn,
1113             long value,
1114             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1115             const char **errmsg ATTRIBUTE_UNUSED)
1116 {
1117   return insn | (-value & 0xffff);
1118 }
1119
1120 static long
1121 extract_nsi (unsigned long insn,
1122              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1123              int *invalid)
1124 {
1125   *invalid = 1;
1126   return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1127 }
1128
1129 /* The RA field in a D or X form instruction which is an updating
1130    load, which means that the RA field may not be zero and may not
1131    equal the RT field.  */
1132
1133 static unsigned long
1134 insert_ral (unsigned long insn,
1135             long value,
1136             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1137             const char **errmsg)
1138 {
1139   if (value == 0
1140       || (unsigned long) value == ((insn >> 21) & 0x1f))
1141     *errmsg = "invalid register operand when updating";
1142   return insn | ((value & 0x1f) << 16);
1143 }
1144
1145 /* The RA field in an lmw instruction, which has special value
1146    restrictions.  */
1147
1148 static unsigned long
1149 insert_ram (unsigned long insn,
1150             long value,
1151             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1152             const char **errmsg)
1153 {
1154   if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1155     *errmsg = _("index register in load range");
1156   return insn | ((value & 0x1f) << 16);
1157 }
1158
1159 /* The RA field in the DQ form lq instruction, which has special
1160    value restrictions.  */
1161
1162 static unsigned long
1163 insert_raq (unsigned long insn,
1164             long value,
1165             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1166             const char **errmsg)
1167 {
1168   long rtvalue = (insn & RT_MASK) >> 21;
1169
1170   if (value == rtvalue)
1171     *errmsg = _("source and target register operands must be different");
1172   return insn | ((value & 0x1f) << 16);
1173 }
1174
1175 /* The RA field in a D or X form instruction which is an updating
1176    store or an updating floating point load, which means that the RA
1177    field may not be zero.  */
1178
1179 static unsigned long
1180 insert_ras (unsigned long insn,
1181             long value,
1182             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1183             const char **errmsg)
1184 {
1185   if (value == 0)
1186     *errmsg = _("invalid register operand when updating");
1187   return insn | ((value & 0x1f) << 16);
1188 }
1189
1190 /* The RB field in an X form instruction when it must be the same as
1191    the RS field in the instruction.  This is used for extended
1192    mnemonics like mr.  This operand is marked FAKE.  The insertion
1193    function just copies the BT field into the BA field, and the
1194    extraction function just checks that the fields are the same.  */
1195
1196 static unsigned long
1197 insert_rbs (unsigned long insn,
1198             long value ATTRIBUTE_UNUSED,
1199             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1200             const char **errmsg ATTRIBUTE_UNUSED)
1201 {
1202   return insn | (((insn >> 21) & 0x1f) << 11);
1203 }
1204
1205 static long
1206 extract_rbs (unsigned long insn,
1207              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1208              int *invalid)
1209 {
1210   if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1211     *invalid = 1;
1212   return 0;
1213 }
1214
1215 /* The SH field in an MD form instruction.  This is split.  */
1216
1217 static unsigned long
1218 insert_sh6 (unsigned long insn,
1219             long value,
1220             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1221             const char **errmsg ATTRIBUTE_UNUSED)
1222 {
1223   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1224 }
1225
1226 static long
1227 extract_sh6 (unsigned long insn,
1228              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1229              int *invalid ATTRIBUTE_UNUSED)
1230 {
1231   return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1232 }
1233
1234 /* The SPR field in an XFX form instruction.  This is flipped--the
1235    lower 5 bits are stored in the upper 5 and vice- versa.  */
1236
1237 static unsigned long
1238 insert_spr (unsigned long insn,
1239             long value,
1240             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1241             const char **errmsg ATTRIBUTE_UNUSED)
1242 {
1243   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1244 }
1245
1246 static long
1247 extract_spr (unsigned long insn,
1248              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1249              int *invalid ATTRIBUTE_UNUSED)
1250 {
1251   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1252 }
1253
1254 /* Some dialects have 8 SPRG registers instead of the standard 4.  */
1255
1256 static unsigned long
1257 insert_sprg (unsigned long insn,
1258              long value,
1259              ppc_cpu_t dialect,
1260              const char **errmsg)
1261 {
1262   if (value > 7
1263       || (value > 3
1264           && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0))
1265     *errmsg = _("invalid sprg number");
1266
1267   /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1268      user mode.  Anything else must use spr 272..279.  */
1269   if (value <= 3 || (insn & 0x100) != 0)
1270     value |= 0x10;
1271
1272   return insn | ((value & 0x17) << 16);
1273 }
1274
1275 static long
1276 extract_sprg (unsigned long insn,
1277               ppc_cpu_t dialect,
1278               int *invalid)
1279 {
1280   unsigned long val = (insn >> 16) & 0x1f;
1281
1282   /* mfsprg can use 260..263 and 272..279.  mtsprg only uses spr 272..279
1283      If not BOOKE or 405, then both use only 272..275.  */
1284   if ((val - 0x10 > 3 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0)
1285       || (val - 0x10 > 7 && (insn & 0x100) != 0)
1286       || val <= 3
1287       || (val & 8) != 0)
1288     *invalid = 1;
1289   return val & 7;
1290 }
1291
1292 /* The TBR field in an XFX instruction.  This is just like SPR, but it
1293    is optional.  When TBR is omitted, it must be inserted as 268 (the
1294    magic number of the TB register).  These functions treat 0
1295    (indicating an omitted optional operand) as 268.  This means that
1296    ``mftb 4,0'' is not handled correctly.  This does not matter very
1297    much, since the architecture manual does not define mftb as
1298    accepting any values other than 268 or 269.  */
1299
1300 #define TB (268)
1301
1302 static unsigned long
1303 insert_tbr (unsigned long insn,
1304             long value,
1305             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1306             const char **errmsg ATTRIBUTE_UNUSED)
1307 {
1308   if (value == 0)
1309     value = TB;
1310   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1311 }
1312
1313 static long
1314 extract_tbr (unsigned long insn,
1315              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1316              int *invalid ATTRIBUTE_UNUSED)
1317 {
1318   long ret;
1319
1320   ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1321   if (ret == TB)
1322     ret = 0;
1323   return ret;
1324 }
1325
1326 /* The XT and XS fields in an XX1 or XX3 form instruction.  This is split.  */
1327
1328 static unsigned long
1329 insert_xt6 (unsigned long insn,
1330             long value,
1331             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1332             const char **errmsg ATTRIBUTE_UNUSED)
1333 {
1334   return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
1335 }
1336
1337 static long
1338 extract_xt6 (unsigned long insn,
1339              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1340              int *invalid ATTRIBUTE_UNUSED)
1341 {
1342   return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
1343 }
1344
1345 /* The XA field in an XX3 form instruction.  This is split.  */
1346
1347 static unsigned long
1348 insert_xa6 (unsigned long insn,
1349             long value,
1350             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1351             const char **errmsg ATTRIBUTE_UNUSED)
1352 {
1353   return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
1354 }
1355
1356 static long
1357 extract_xa6 (unsigned long insn,
1358              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1359              int *invalid ATTRIBUTE_UNUSED)
1360 {
1361   return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
1362 }
1363
1364 /* The XB field in an XX3 form instruction.  This is split.  */
1365
1366 static unsigned long
1367 insert_xb6 (unsigned long insn,
1368             long value,
1369             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1370             const char **errmsg ATTRIBUTE_UNUSED)
1371 {
1372   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1373 }
1374
1375 static long
1376 extract_xb6 (unsigned long insn,
1377              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1378              int *invalid ATTRIBUTE_UNUSED)
1379 {
1380   return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
1381 }
1382
1383 /* The XB field in an XX3 form instruction when it must be the same as
1384    the XA field in the instruction.  This is used for extended
1385    mnemonics like xvmovdp.  This operand is marked FAKE.  The insertion
1386    function just copies the XA field into the XB field, and the
1387    extraction function just checks that the fields are the same.  */
1388
1389 static unsigned long
1390 insert_xb6s (unsigned long insn,
1391             long value ATTRIBUTE_UNUSED,
1392             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1393             const char **errmsg ATTRIBUTE_UNUSED)
1394 {
1395   return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
1396 }
1397
1398 static long
1399 extract_xb6s (unsigned long insn,
1400              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1401              int *invalid)
1402 {
1403   if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
1404       || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
1405     *invalid = 1;
1406   return 0;
1407 }
1408 \f
1409 /* Macros used to form opcodes.  */
1410
1411 /* The main opcode.  */
1412 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1413 #define OP_MASK OP (0x3f)
1414
1415 /* The main opcode combined with a trap code in the TO field of a D
1416    form instruction.  Used for extended mnemonics for the trap
1417    instructions.  */
1418 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1419 #define OPTO_MASK (OP_MASK | TO_MASK)
1420
1421 /* The main opcode combined with a comparison size bit in the L field
1422    of a D form or X form instruction.  Used for extended mnemonics for
1423    the comparison instructions.  */
1424 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1425 #define OPL_MASK OPL (0x3f,1)
1426
1427 /* An A form instruction.  */
1428 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1429 #define A_MASK A (0x3f, 0x1f, 1)
1430
1431 /* An A_MASK with the FRB field fixed.  */
1432 #define AFRB_MASK (A_MASK | FRB_MASK)
1433
1434 /* An A_MASK with the FRC field fixed.  */
1435 #define AFRC_MASK (A_MASK | FRC_MASK)
1436
1437 /* An A_MASK with the FRA and FRC fields fixed.  */
1438 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1439
1440 /* An AFRAFRC_MASK, but with L bit clear.  */
1441 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
1442
1443 /* A B form instruction.  */
1444 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1445 #define B_MASK B (0x3f, 1, 1)
1446
1447 /* A B form instruction setting the BO field.  */
1448 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1449 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1450
1451 /* A BBO_MASK with the y bit of the BO field removed.  This permits
1452    matching a conditional branch regardless of the setting of the y
1453    bit.  Similarly for the 'at' bits used for power4 branch hints.  */
1454 #define Y_MASK   (((unsigned long) 1) << 21)
1455 #define AT1_MASK (((unsigned long) 3) << 21)
1456 #define AT2_MASK (((unsigned long) 9) << 21)
1457 #define BBOY_MASK  (BBO_MASK &~ Y_MASK)
1458 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1459
1460 /* A B form instruction setting the BO field and the condition bits of
1461    the BI field.  */
1462 #define BBOCB(op, bo, cb, aa, lk) \
1463   (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1464 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1465
1466 /* A BBOCB_MASK with the y bit of the BO field removed.  */
1467 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1468 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1469 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1470
1471 /* A BBOYCB_MASK in which the BI field is fixed.  */
1472 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1473 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1474
1475 /* An Context form instruction.  */
1476 #define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
1477 #define CTX_MASK CTX(0x3f, 0x7)
1478
1479 /* An User Context form instruction.  */
1480 #define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1481 #define UCTX_MASK UCTX(0x3f, 0x1f)
1482
1483 /* The main opcode mask with the RA field clear.  */
1484 #define DRA_MASK (OP_MASK | RA_MASK)
1485
1486 /* A DS form instruction.  */
1487 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1488 #define DS_MASK DSO (0x3f, 3)
1489
1490 /* A DE form instruction.  */
1491 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1492 #define DE_MASK DEO (0x3e, 0xf)
1493
1494 /* An EVSEL form instruction.  */
1495 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1496 #define EVSEL_MASK EVSEL(0x3f, 0xff)
1497
1498 /* An M form instruction.  */
1499 #define M(op, rc) (OP (op) | ((rc) & 1))
1500 #define M_MASK M (0x3f, 1)
1501
1502 /* An M form instruction with the ME field specified.  */
1503 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1504
1505 /* An M_MASK with the MB and ME fields fixed.  */
1506 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1507
1508 /* An M_MASK with the SH and ME fields fixed.  */
1509 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1510
1511 /* An MD form instruction.  */
1512 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1513 #define MD_MASK MD (0x3f, 0x7, 1)
1514
1515 /* An MD_MASK with the MB field fixed.  */
1516 #define MDMB_MASK (MD_MASK | MB6_MASK)
1517
1518 /* An MD_MASK with the SH field fixed.  */
1519 #define MDSH_MASK (MD_MASK | SH6_MASK)
1520
1521 /* An MDS form instruction.  */
1522 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1523 #define MDS_MASK MDS (0x3f, 0xf, 1)
1524
1525 /* An MDS_MASK with the MB field fixed.  */
1526 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1527
1528 /* An SC form instruction.  */
1529 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1530 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1531
1532 /* An VX form instruction.  */
1533 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1534
1535 /* The mask for an VX form instruction.  */
1536 #define VX_MASK VX(0x3f, 0x7ff)
1537
1538 /* An VA form instruction.  */
1539 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1540
1541 /* The mask for an VA form instruction.  */
1542 #define VXA_MASK VXA(0x3f, 0x3f)
1543
1544 /* An VXR form instruction.  */
1545 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1546
1547 /* The mask for a VXR form instruction.  */
1548 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1549
1550 /* An X form instruction.  */
1551 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1552
1553 /* An XX3 form instruction.  */
1554 #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
1555
1556 #define XX3DM(op, xop, dm) (XX3 (op, ((unsigned long)(xop) & 0x1f)) \
1557   | ((((unsigned long)(dm)) & 0x3) << 8))
1558
1559 /* A Z form instruction.  */
1560 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1561
1562 /* An X form instruction with the RC bit specified.  */
1563 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1564
1565 /* A Z form instruction with the RC bit specified.  */
1566 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1567
1568 /* The mask for an X form instruction.  */
1569 #define X_MASK XRC (0x3f, 0x3ff, 1)
1570
1571 /* The mask for an XX1 form instruction.  */
1572 #define XX1_MASK X (0x3f, 0x3ff)
1573
1574 /* The mask for an XX3 form instruction.  */
1575 #define XX3_MASK XX3 (0x3f, 0xff)
1576
1577 /* The mask for an XX3 form instruction with the DM bits specified.  */
1578 #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
1579
1580 /* The mask for a Z form instruction.  */
1581 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
1582 #define Z2_MASK ZRC (0x3f, 0xff, 1)
1583
1584 /* An X_MASK with the RA field fixed.  */
1585 #define XRA_MASK (X_MASK | RA_MASK)
1586
1587 /* An XRA_MASK with the W field clear.  */
1588 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
1589
1590 /* An X_MASK with the RB field fixed.  */
1591 #define XRB_MASK (X_MASK | RB_MASK)
1592
1593 /* An X_MASK with the RT field fixed.  */
1594 #define XRT_MASK (X_MASK | RT_MASK)
1595
1596 /* An XRT_MASK mask with the L bits clear.  */
1597 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
1598
1599 /* An X_MASK with the RA and RB fields fixed.  */
1600 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1601
1602 /* An XRARB_MASK, but with the L bit clear.  */
1603 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1604
1605 /* An X_MASK with the RT and RA fields fixed.  */
1606 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1607
1608 /* An XRTRA_MASK, but with L bit clear.  */
1609 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1610
1611 /* An X form instruction with the L bit specified.  */
1612 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1613
1614 /* An X form instruction with RT fields specified */
1615 #define XRT(op, xop, rt) (X ((op), (xop)) \
1616         | ((((unsigned long)(rt)) & 0x1f) << 21))
1617
1618 /* An X form instruction with RT and RA fields specified */
1619 #define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
1620         | ((((unsigned long)(rt)) & 0x1f) << 21) \
1621         | ((((unsigned long)(ra)) & 0x1f) << 16))
1622
1623 /* The mask for an X form comparison instruction.  */
1624 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1625
1626 /* The mask for an X form comparison instruction with the L field
1627    fixed.  */
1628 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1629
1630 /* An X form trap instruction with the TO field specified.  */
1631 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1632 #define XTO_MASK (X_MASK | TO_MASK)
1633
1634 /* An X form tlb instruction with the SH field specified.  */
1635 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1636 #define XTLB_MASK (X_MASK | SH_MASK)
1637
1638 /* An X form sync instruction.  */
1639 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1640
1641 /* An X form sync instruction with everything filled in except the LS field.  */
1642 #define XSYNC_MASK (0xff9fffff)
1643
1644 /* An X_MASK, but with the EH bit clear.  */
1645 #define XEH_MASK (X_MASK & ~((unsigned long )1))
1646
1647 /* An X form AltiVec dss instruction.  */
1648 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1649 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1650
1651 /* An XFL form instruction.  */
1652 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1653 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
1654
1655 /* An X form isel instruction.  */
1656 #define XISEL(op, xop)  (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1657 #define XISEL_MASK      XISEL(0x3f, 0x1f)
1658
1659 /* An XL form instruction with the LK field set to 0.  */
1660 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1661
1662 /* An XL form instruction which uses the LK field.  */
1663 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1664
1665 /* The mask for an XL form instruction.  */
1666 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1667
1668 /* An XL form instruction which explicitly sets the BO field.  */
1669 #define XLO(op, bo, xop, lk) \
1670   (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1671 #define XLO_MASK (XL_MASK | BO_MASK)
1672
1673 /* An XL form instruction which explicitly sets the y bit of the BO
1674    field.  */
1675 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1676 #define XLYLK_MASK (XL_MASK | Y_MASK)
1677
1678 /* An XL form instruction which sets the BO field and the condition
1679    bits of the BI field.  */
1680 #define XLOCB(op, bo, cb, xop, lk) \
1681   (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1682 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1683
1684 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
1685 #define XLBB_MASK (XL_MASK | BB_MASK)
1686 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1687 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1688
1689 /* A mask for branch instructions using the BH field.  */
1690 #define XLBH_MASK (XL_MASK | (0x1c << 11))
1691
1692 /* An XL_MASK with the BO and BB fields fixed.  */
1693 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1694
1695 /* An XL_MASK with the BO, BI and BB fields fixed.  */
1696 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1697
1698 /* An XO form instruction.  */
1699 #define XO(op, xop, oe, rc) \
1700   (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1701 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1702
1703 /* An XO_MASK with the RB field fixed.  */
1704 #define XORB_MASK (XO_MASK | RB_MASK)
1705
1706 /* An XOPS form instruction for paired singles.  */
1707 #define XOPS(op, xop, rc) \
1708   (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1709 #define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
1710
1711
1712 /* An XS form instruction.  */
1713 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1714 #define XS_MASK XS (0x3f, 0x1ff, 1)
1715
1716 /* A mask for the FXM version of an XFX form instruction.  */
1717 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
1718
1719 /* An XFX form instruction with the FXM field filled in.  */
1720 #define XFXM(op, xop, fxm, p4) \
1721   (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1722    | ((unsigned long)(p4) << 20))
1723
1724 /* An XFX form instruction with the SPR field filled in.  */
1725 #define XSPR(op, xop, spr) \
1726   (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1727 #define XSPR_MASK (X_MASK | SPR_MASK)
1728
1729 /* An XFX form instruction with the SPR field filled in except for the
1730    SPRBAT field.  */
1731 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1732
1733 /* An XFX form instruction with the SPR field filled in except for the
1734    SPRG field.  */
1735 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
1736
1737 /* An X form instruction with everything filled in except the E field.  */
1738 #define XE_MASK (0xffff7fff)
1739
1740 /* An X form user context instruction.  */
1741 #define XUC(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1742 #define XUC_MASK      XUC(0x3f, 0x1f)
1743
1744 /* An XW form instruction.  */
1745 #define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
1746 /* The mask for a G form instruction. rc not supported at present.  */
1747 #define XW_MASK XW (0x3f, 0x3f, 0)
1748
1749 /* An APU form instruction.  */
1750 #define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
1751
1752 /* The mask for an APU form instruction.  */
1753 #define APU_MASK APU (0x3f, 0x3ff, 1)
1754 #define APU_RT_MASK (APU_MASK | RT_MASK)
1755 #define APU_RA_MASK (APU_MASK | RA_MASK)
1756
1757 /* The BO encodings used in extended conditional branch mnemonics.  */
1758 #define BODNZF  (0x0)
1759 #define BODNZFP (0x1)
1760 #define BODZF   (0x2)
1761 #define BODZFP  (0x3)
1762 #define BODNZT  (0x8)
1763 #define BODNZTP (0x9)
1764 #define BODZT   (0xa)
1765 #define BODZTP  (0xb)
1766
1767 #define BOF     (0x4)
1768 #define BOFP    (0x5)
1769 #define BOFM4   (0x6)
1770 #define BOFP4   (0x7)
1771 #define BOT     (0xc)
1772 #define BOTP    (0xd)
1773 #define BOTM4   (0xe)
1774 #define BOTP4   (0xf)
1775
1776 #define BODNZ   (0x10)
1777 #define BODNZP  (0x11)
1778 #define BODZ    (0x12)
1779 #define BODZP   (0x13)
1780 #define BODNZM4 (0x18)
1781 #define BODNZP4 (0x19)
1782 #define BODZM4  (0x1a)
1783 #define BODZP4  (0x1b)
1784
1785 #define BOU     (0x14)
1786
1787 /* The BI condition bit encodings used in extended conditional branch
1788    mnemonics.  */
1789 #define CBLT    (0)
1790 #define CBGT    (1)
1791 #define CBEQ    (2)
1792 #define CBSO    (3)
1793
1794 /* The TO encodings used in extended trap mnemonics.  */
1795 #define TOLGT   (0x1)
1796 #define TOLLT   (0x2)
1797 #define TOEQ    (0x4)
1798 #define TOLGE   (0x5)
1799 #define TOLNL   (0x5)
1800 #define TOLLE   (0x6)
1801 #define TOLNG   (0x6)
1802 #define TOGT    (0x8)
1803 #define TOGE    (0xc)
1804 #define TONL    (0xc)
1805 #define TOLT    (0x10)
1806 #define TOLE    (0x14)
1807 #define TONG    (0x14)
1808 #define TONE    (0x18)
1809 #define TOU     (0x1f)
1810 \f
1811 /* Smaller names for the flags so each entry in the opcodes table will
1812    fit on a single line.  */
1813 #undef  PPC
1814 #define PPC     PPC_OPCODE_PPC
1815 #define PPCCOM  PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1816 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1817 #define POWER4  PPC_OPCODE_POWER4
1818 #define POWER5  PPC_OPCODE_POWER5
1819 #define POWER6  PPC_OPCODE_POWER6
1820 #define CELL    PPC_OPCODE_CELL
1821 #define PPC32   PPC_OPCODE_32 | PPC_OPCODE_PPC
1822 #define PPC64   PPC_OPCODE_64 | PPC_OPCODE_PPC
1823 #define PPC403  PPC_OPCODE_403
1824 #define PPC405  PPC_OPCODE_405
1825 #define PPC440  PPC_OPCODE_440
1826 #define PPC464  PPC440
1827 #define PPC750  PPC
1828 #define PPC7450 PPC
1829 #define PPC860  PPC
1830 #define PPCPS   PPC_OPCODE_PPCPS
1831 #define PPCVEC  PPC_OPCODE_ALTIVEC
1832 #define PPCVSX  PPC_OPCODE_VSX
1833 #define POWER   PPC_OPCODE_POWER
1834 #define POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1835 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1836 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1837 #define COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1838 #define COM32   PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1839 #define M601    PPC_OPCODE_POWER | PPC_OPCODE_601
1840 #define PWRCOM  PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1841 #define MFDEC1  PPC_OPCODE_POWER
1842 #define MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1843 #define BOOKE   PPC_OPCODE_BOOKE
1844 #define BOOKE64 PPC_OPCODE_BOOKE64
1845 #define CLASSIC PPC_OPCODE_CLASSIC
1846 #define PPCE300 PPC_OPCODE_E300
1847 #define PPCSPE  PPC_OPCODE_SPE
1848 #define PPCISEL PPC_OPCODE_ISEL
1849 #define PPCEFS  PPC_OPCODE_EFS
1850 #define PPCBRLK PPC_OPCODE_BRLOCK
1851 #define PPCPMR  PPC_OPCODE_PMR
1852 #define PPCCHLK PPC_OPCODE_CACHELCK
1853 #define PPCCHLK64       PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1854 #define PPCRFMCI        PPC_OPCODE_RFMCI
1855 #define E500MC  PPC_OPCODE_E500MC
1856 \f
1857 /* The opcode table.
1858
1859    The format of the opcode table is:
1860
1861    NAME         OPCODE          MASK         FLAGS      {OPERANDS}
1862
1863    NAME is the name of the instruction.
1864    OPCODE is the instruction opcode.
1865    MASK is the opcode mask; this is used to tell the disassembler
1866      which bits in the actual opcode must match OPCODE.
1867    FLAGS are flags indicated what processors support the instruction.
1868    OPERANDS is the list of operands.
1869
1870    The disassembler reads the table in order and prints the first
1871    instruction which matches, so this table is sorted to put more
1872    specific instructions before more general instructions.
1873
1874    This table must be sorted by major opcode.  Please try to keep it
1875    vaguely sorted within major opcode too, except of course where
1876    constrained otherwise by disassembler operation.  */
1877
1878 const struct powerpc_opcode powerpc_opcodes[] = {
1879 {"attn",        X(0,256),       X_MASK,      POWER4,    {0}},
1880 {"tdlgti",      OPTO(2,TOLGT),  OPTO_MASK,   PPC64,     {RA, SI}},
1881 {"tdllti",      OPTO(2,TOLLT),  OPTO_MASK,   PPC64,     {RA, SI}},
1882 {"tdeqi",       OPTO(2,TOEQ),   OPTO_MASK,   PPC64,     {RA, SI}},
1883 {"tdlgei",      OPTO(2,TOLGE),  OPTO_MASK,   PPC64,     {RA, SI}},
1884 {"tdlnli",      OPTO(2,TOLNL),  OPTO_MASK,   PPC64,     {RA, SI}},
1885 {"tdllei",      OPTO(2,TOLLE),  OPTO_MASK,   PPC64,     {RA, SI}},
1886 {"tdlngi",      OPTO(2,TOLNG),  OPTO_MASK,   PPC64,     {RA, SI}},
1887 {"tdgti",       OPTO(2,TOGT),   OPTO_MASK,   PPC64,     {RA, SI}},
1888 {"tdgei",       OPTO(2,TOGE),   OPTO_MASK,   PPC64,     {RA, SI}},
1889 {"tdnli",       OPTO(2,TONL),   OPTO_MASK,   PPC64,     {RA, SI}},
1890 {"tdlti",       OPTO(2,TOLT),   OPTO_MASK,   PPC64,     {RA, SI}},
1891 {"tdlei",       OPTO(2,TOLE),   OPTO_MASK,   PPC64,     {RA, SI}},
1892 {"tdngi",       OPTO(2,TONG),   OPTO_MASK,   PPC64,     {RA, SI}},
1893 {"tdnei",       OPTO(2,TONE),   OPTO_MASK,   PPC64,     {RA, SI}},
1894 {"tdi",         OP(2),          OP_MASK,     PPC64,     {TO, RA, SI}},
1895
1896 {"twlgti",      OPTO(3,TOLGT),  OPTO_MASK,   PPCCOM,    {RA, SI}},
1897 {"tlgti",       OPTO(3,TOLGT),  OPTO_MASK,   PWRCOM,    {RA, SI}},
1898 {"twllti",      OPTO(3,TOLLT),  OPTO_MASK,   PPCCOM,    {RA, SI}},
1899 {"tllti",       OPTO(3,TOLLT),  OPTO_MASK,   PWRCOM,    {RA, SI}},
1900 {"tweqi",       OPTO(3,TOEQ),   OPTO_MASK,   PPCCOM,    {RA, SI}},
1901 {"teqi",        OPTO(3,TOEQ),   OPTO_MASK,   PWRCOM,    {RA, SI}},
1902 {"twlgei",      OPTO(3,TOLGE),  OPTO_MASK,   PPCCOM,    {RA, SI}},
1903 {"tlgei",       OPTO(3,TOLGE),  OPTO_MASK,   PWRCOM,    {RA, SI}},
1904 {"twlnli",      OPTO(3,TOLNL),  OPTO_MASK,   PPCCOM,    {RA, SI}},
1905 {"tlnli",       OPTO(3,TOLNL),  OPTO_MASK,   PWRCOM,    {RA, SI}},
1906 {"twllei",      OPTO(3,TOLLE),  OPTO_MASK,   PPCCOM,    {RA, SI}},
1907 {"tllei",       OPTO(3,TOLLE),  OPTO_MASK,   PWRCOM,    {RA, SI}},
1908 {"twlngi",      OPTO(3,TOLNG),  OPTO_MASK,   PPCCOM,    {RA, SI}},
1909 {"tlngi",       OPTO(3,TOLNG),  OPTO_MASK,   PWRCOM,    {RA, SI}},
1910 {"twgti",       OPTO(3,TOGT),   OPTO_MASK,   PPCCOM,    {RA, SI}},
1911 {"tgti",        OPTO(3,TOGT),   OPTO_MASK,   PWRCOM,    {RA, SI}},
1912 {"twgei",       OPTO(3,TOGE),   OPTO_MASK,   PPCCOM,    {RA, SI}},
1913 {"tgei",        OPTO(3,TOGE),   OPTO_MASK,   PWRCOM,    {RA, SI}},
1914 {"twnli",       OPTO(3,TONL),   OPTO_MASK,   PPCCOM,    {RA, SI}},
1915 {"tnli",        OPTO(3,TONL),   OPTO_MASK,   PWRCOM,    {RA, SI}},
1916 {"twlti",       OPTO(3,TOLT),   OPTO_MASK,   PPCCOM,    {RA, SI}},
1917 {"tlti",        OPTO(3,TOLT),   OPTO_MASK,   PWRCOM,    {RA, SI}},
1918 {"twlei",       OPTO(3,TOLE),   OPTO_MASK,   PPCCOM,    {RA, SI}},
1919 {"tlei",        OPTO(3,TOLE),   OPTO_MASK,   PWRCOM,    {RA, SI}},
1920 {"twngi",       OPTO(3,TONG),   OPTO_MASK,   PPCCOM,    {RA, SI}},
1921 {"tngi",        OPTO(3,TONG),   OPTO_MASK,   PWRCOM,    {RA, SI}},
1922 {"twnei",       OPTO(3,TONE),   OPTO_MASK,   PPCCOM,    {RA, SI}},
1923 {"tnei",        OPTO(3,TONE),   OPTO_MASK,   PWRCOM,    {RA, SI}},
1924 {"twi",         OP(3),          OP_MASK,     PPCCOM,    {TO, RA, SI}},
1925 {"ti",          OP(3),          OP_MASK,     PWRCOM,    {TO, RA, SI}},
1926
1927 {"ps_cmpu0",    X  (4,   0), X_MASK|(3<<21), PPCPS,     {BF, FRA, FRB}},
1928 {"vaddubm",     VX (4,   0),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
1929 {"vmaxub",      VX (4,   2),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
1930 {"vrlb",        VX (4,   4),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
1931 {"vcmpequb",    VXR(4,   6,0),  VXR_MASK,    PPCVEC,    {VD, VA, VB}},
1932 {"vmuloub",     VX (4,   8),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
1933 {"vaddfp",      VX (4,  10),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
1934 {"psq_lx",      XW (4,   6,0),  XW_MASK,     PPCPS,     {FRT,RA,RB,PSWM,PSQM}},
1935 {"vmrghb",      VX (4,  12),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
1936 {"psq_stx",     XW (4,   7,0),  XW_MASK,     PPCPS,     {FRS,RA,RB,PSWM,PSQM}},
1937 {"vpkuhum",     VX (4,  14),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
1938 {"mulhhwu",     XRC(4,   8,0),  X_MASK,  PPC405|PPC440, {RT, RA, RB}},
1939 {"mulhhwu.",    XRC(4,   8,1),  X_MASK,  PPC405|PPC440, {RT, RA, RB}},
1940 {"ps_sum0",     A  (4,  10,0),  A_MASK,      PPCPS,     {FRT, FRA, FRC, FRB}},
1941 {"ps_sum0.",    A  (4,  10,1),  A_MASK,      PPCPS,     {FRT, FRA, FRC, FRB}},
1942 {"ps_sum1",     A  (4,  11,0),  A_MASK,      PPCPS,     {FRT, FRA, FRC, FRB}},
1943 {"ps_sum1.",    A  (4,  11,1),  A_MASK,      PPCPS,     {FRT, FRA, FRC, FRB}},
1944 {"ps_muls0",    A  (4,  12,0),  AFRB_MASK,   PPCPS,     {FRT, FRA, FRC}},
1945 {"machhwu",     XO (4,  12,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1946 {"ps_muls0.",   A  (4,  12,1),  AFRB_MASK,   PPCPS,     {FRT, FRA, FRC}},
1947 {"machhwu.",    XO (4,  12,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1948 {"ps_muls1",    A  (4,  13,0),  AFRB_MASK,   PPCPS,     {FRT, FRA, FRC}},
1949 {"ps_muls1.",   A  (4,  13,1),  AFRB_MASK,   PPCPS,     {FRT, FRA, FRC}},
1950 {"ps_madds0",   A  (4,  14,0),  A_MASK,      PPCPS,     {FRT, FRA, FRC, FRB}},
1951 {"ps_madds0.",  A  (4,  14,1),  A_MASK,      PPCPS,     {FRT, FRA, FRC, FRB}},
1952 {"ps_madds1",   A  (4,  15,0),  A_MASK,      PPCPS,     {FRT, FRA, FRC, FRB}},
1953 {"ps_madds1.",  A  (4,  15,1),  A_MASK,      PPCPS,     {FRT, FRA, FRC, FRB}},
1954 {"vmhaddshs",   VXA(4,  32),    VXA_MASK,    PPCVEC,    {VD, VA, VB, VC}},
1955 {"vmhraddshs",  VXA(4,  33),    VXA_MASK,    PPCVEC,    {VD, VA, VB, VC}},
1956 {"vmladduhm",   VXA(4,  34),    VXA_MASK,    PPCVEC,    {VD, VA, VB, VC}},
1957 {"ps_div",      A  (4,  18,0),  AFRC_MASK,   PPCPS,     {FRT, FRA, FRB}},
1958 {"vmsumubm",    VXA(4,  36),    VXA_MASK,    PPCVEC,    {VD, VA, VB, VC}},
1959 {"ps_div.",     A  (4,  18,1),  AFRC_MASK,   PPCPS,     {FRT, FRA, FRB}},
1960 {"vmsummbm",    VXA(4,  37),    VXA_MASK,    PPCVEC,    {VD, VA, VB, VC}},
1961 {"vmsumuhm",    VXA(4,  38),    VXA_MASK,    PPCVEC,    {VD, VA, VB, VC}},
1962 {"vmsumuhs",    VXA(4,  39),    VXA_MASK,    PPCVEC,    {VD, VA, VB, VC}},
1963 {"ps_sub",      A  (4,  20,0),  AFRC_MASK,   PPCPS,     {FRT, FRA, FRB}},
1964 {"vmsumshm",    VXA(4,  40),    VXA_MASK,    PPCVEC,    {VD, VA, VB, VC}},
1965 {"ps_sub.",     A  (4,  20,1),  AFRC_MASK,   PPCPS,     {FRT, FRA, FRB}},
1966 {"vmsumshs",    VXA(4,  41),    VXA_MASK,    PPCVEC,    {VD, VA, VB, VC}},
1967 {"ps_add",      A  (4,  21,0),  AFRC_MASK,   PPCPS,     {FRT, FRA, FRB}},
1968 {"vsel",        VXA(4,  42),    VXA_MASK,    PPCVEC,    {VD, VA, VB, VC}},
1969 {"ps_add.",     A  (4,  21,1),  AFRC_MASK,   PPCPS,     {FRT, FRA, FRB}},
1970 {"vperm",       VXA(4,  43),    VXA_MASK,    PPCVEC,    {VD, VA, VB, VC}},
1971 {"vsldoi",      VXA(4,  44),    VXA_MASK,    PPCVEC,    {VD, VA, VB, SHB}},
1972 {"ps_sel",      A  (4,  23,0),  A_MASK,      PPCPS,     {FRT, FRA, FRC, FRB}},
1973 {"vmaddfp",     VXA(4,  46),    VXA_MASK,    PPCVEC,    {VD, VA, VC, VB}},
1974 {"ps_sel.",     A  (4,  23,1),  A_MASK,      PPCPS,     {FRT, FRA, FRC, FRB}},
1975 {"vnmsubfp",    VXA(4,  47),    VXA_MASK,    PPCVEC,    {VD, VA, VC, VB}},
1976 {"ps_res",      A  (4,  24,0), AFRAFRC_MASK, PPCPS,     {FRT, FRB}},
1977 {"ps_res.",     A  (4,  24,1), AFRAFRC_MASK, PPCPS,     {FRT, FRB}},
1978 {"ps_mul",      A  (4,  25,0), AFRB_MASK,    PPCPS,     {FRT, FRA, FRC}},
1979 {"ps_mul.",     A  (4,  25,1),  AFRB_MASK,   PPCPS,     {FRT, FRA, FRC}},
1980 {"ps_rsqrte",   A  (4,  26,0), AFRAFRC_MASK, PPCPS,     {FRT, FRB}},
1981 {"ps_rsqrte.",  A  (4,  26,1), AFRAFRC_MASK, PPCPS,     {FRT, FRB}},
1982 {"ps_msub",     A  (4,  28,0),  A_MASK,      PPCPS,     {FRT, FRA, FRC, FRB}},
1983 {"ps_msub.",    A  (4,  28,1),  A_MASK,      PPCPS,     {FRT, FRA, FRC, FRB}},
1984 {"ps_madd",     A  (4,  29,0),  A_MASK,      PPCPS,     {FRT, FRA, FRC, FRB}},
1985 {"ps_madd.",    A  (4,  29,1),  A_MASK,      PPCPS,     {FRT, FRA, FRC, FRB}},
1986 {"ps_nmsub",    A  (4,  30,0),  A_MASK,      PPCPS,     {FRT, FRA, FRC, FRB}},
1987 {"ps_nmsub.",   A  (4,  30,1),  A_MASK,      PPCPS,     {FRT, FRA, FRC, FRB}},
1988 {"ps_nmadd",    A  (4,  31,0),  A_MASK,      PPCPS,     {FRT, FRA, FRC, FRB}},
1989 {"ps_nmadd.",   A  (4,  31,1),  A_MASK,      PPCPS,     {FRT, FRA, FRC, FRB}},
1990 {"ps_cmpo0",    X  (4,  32), X_MASK|(3<<21), PPCPS,     {BF, FRA, FRB}},
1991 {"vadduhm",     VX (4,  64),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
1992 {"vmaxuh",      VX (4,  66),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
1993 {"vrlh",        VX (4,  68),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
1994 {"vcmpequh",    VXR(4,  70,0),  VXR_MASK,    PPCVEC,    {VD, VA, VB}},
1995 {"vmulouh",     VX (4,  72),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
1996 {"vsubfp",      VX (4,  74),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
1997 {"psq_lux",     XW (4,  38,0),  XW_MASK,     PPCPS,     {FRT,RA,RB,PSWM,PSQM}},
1998 {"vmrghh",      VX (4,  76),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
1999 {"psq_stux",    XW (4,  39,0),  XW_MASK,     PPCPS,     {FRS,RA,RB,PSWM,PSQM}},
2000 {"vpkuwum",     VX (4,  78),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2001 {"ps_neg",      XRC(4,  40,0),  XRA_MASK,    PPCPS,     {FRT, FRB}},
2002 {"mulhhw",      XRC(4,  40,0),  X_MASK,  PPC405|PPC440, {RT, RA, RB}},
2003 {"ps_neg.",     XRC(4,  40,1),  XRA_MASK,    PPCPS,     {FRT, FRB}},
2004 {"mulhhw.",     XRC(4,  40,1),  X_MASK,  PPC405|PPC440, {RT, RA, RB}},
2005 {"machhw",      XO (4,  44,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2006 {"machhw.",     XO (4,  44,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2007 {"nmachhw",     XO (4,  46,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2008 {"nmachhw.",    XO (4,  46,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2009 {"ps_cmpu1",    X  (4,  64), X_MASK|(3<<21), PPCPS,     {BF, FRA, FRB}},
2010 {"vadduwm",     VX (4,  128),   VX_MASK,     PPCVEC,    {VD, VA, VB}},
2011 {"vmaxuw",      VX (4,  130),   VX_MASK,     PPCVEC,    {VD, VA, VB}},
2012 {"vrlw",        VX (4,  132),   VX_MASK,     PPCVEC,    {VD, VA, VB}},
2013 {"vcmpequw",    VXR(4,  134,0), VXR_MASK,    PPCVEC,    {VD, VA, VB}},
2014 {"vmrghw",      VX (4,  140),   VX_MASK,     PPCVEC,    {VD, VA, VB}},
2015 {"vpkuhus",     VX (4,  142),   VX_MASK,     PPCVEC,    {VD, VA, VB}},
2016 {"ps_mr",       XRC(4,  72,0),  XRA_MASK,    PPCPS,     {FRT, FRB}},
2017 {"ps_mr.",      XRC(4,  72,1),  XRA_MASK,    PPCPS,     {FRT, FRB}},
2018 {"machhwsu",    XO (4,  76,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2019 {"machhwsu.",   XO (4,  76,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2020 {"ps_cmpo1",    X  (4,  96), X_MASK|(3<<21), PPCPS,     {BF, FRA, FRB}},
2021 {"vcmpeqfp",    VXR(4, 198,0),  VXR_MASK,    PPCVEC,    {VD, VA, VB}},
2022 {"vpkuwus",     VX (4, 206),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2023 {"machhws",     XO (4, 108,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2024 {"machhws.",    XO (4, 108,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2025 {"nmachhws",    XO (4, 110,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2026 {"nmachhws.",   XO (4, 110,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2027 {"vmaxsb",      VX (4, 258),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2028 {"vslb",        VX (4, 260),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2029 {"vmulosb",     VX (4, 264),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2030 {"vrefp",       VX (4, 266),    VX_MASK,     PPCVEC,    {VD, VB}},
2031 {"vmrglb",      VX (4, 268),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2032 {"vpkshus",     VX (4, 270),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2033 {"ps_nabs",     XRC(4, 136,0),  XRA_MASK,    PPCPS,     {FRT, FRB}},
2034 {"mulchwu",     XRC(4, 136,0),  X_MASK,  PPC405|PPC440, {RT, RA, RB}},
2035 {"ps_nabs.",    XRC(4, 136,1),  XRA_MASK,    PPCPS,     {FRT, FRB}},
2036 {"mulchwu.",    XRC(4, 136,1),  X_MASK,  PPC405|PPC440, {RT, RA, RB}},
2037 {"macchwu",     XO (4, 140,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2038 {"macchwu.",    XO (4, 140,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2039 {"vmaxsh",      VX (4, 322),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2040 {"vslh",        VX (4, 324),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2041 {"vmulosh",     VX (4, 328),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2042 {"vrsqrtefp",   VX (4, 330),    VX_MASK,     PPCVEC,    {VD, VB}},
2043 {"vmrglh",      VX (4, 332),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2044 {"vpkswus",     VX (4, 334),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2045 {"mulchw",      XRC(4, 168,0),  X_MASK,  PPC405|PPC440, {RT, RA, RB}},
2046 {"mulchw.",     XRC(4, 168,1),  X_MASK,  PPC405|PPC440, {RT, RA, RB}},
2047 {"macchw",      XO (4, 172,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2048 {"macchw.",     XO (4, 172,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2049 {"nmacchw",     XO (4, 174,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2050 {"nmacchw.",    XO (4, 174,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2051 {"vaddcuw",     VX (4, 384),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2052 {"vmaxsw",      VX (4, 386),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2053 {"vslw",        VX (4, 388),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2054 {"vexptefp",    VX (4, 394),    VX_MASK,     PPCVEC,    {VD, VB}},
2055 {"vmrglw",      VX (4, 396),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2056 {"vpkshss",     VX (4, 398),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2057 {"macchwsu",    XO (4, 204,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2058 {"macchwsu.",   XO (4, 204,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2059 {"vsl",         VX (4, 452),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2060 {"vcmpgefp",    VXR(4, 454,0),  VXR_MASK,    PPCVEC,    {VD, VA, VB}},
2061 {"vlogefp",     VX (4, 458),    VX_MASK,     PPCVEC,    {VD, VB}},
2062 {"vpkswss",     VX (4, 462),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2063 {"macchws",     XO (4, 236,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2064 {"macchws.",    XO (4, 236,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2065 {"nmacchws",    XO (4, 238,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2066 {"nmacchws.",   XO (4, 238,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2067 {"evaddw",      VX (4, 512),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2068 {"vaddubs",     VX (4, 512),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2069 {"evaddiw",     VX (4, 514),    VX_MASK,     PPCSPE,    {RS, RB, UIMM}},
2070 {"vminub",      VX (4, 514),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2071 {"evsubfw",     VX (4, 516),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2072 {"evsubw",      VX (4, 516),    VX_MASK,     PPCSPE,    {RS, RB, RA}},
2073 {"vsrb",        VX (4, 516),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2074 {"evsubifw",    VX (4, 518),    VX_MASK,     PPCSPE,    {RS, UIMM, RB}},
2075 {"evsubiw",     VX (4, 518),    VX_MASK,     PPCSPE,    {RS, RB, UIMM}},
2076 {"vcmpgtub",    VXR(4, 518,0),  VXR_MASK,    PPCVEC,    {VD, VA, VB}},
2077 {"evabs",       VX (4, 520),    VX_MASK,     PPCSPE,    {RS, RA}},
2078 {"vmuleub",     VX (4, 520),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2079 {"evneg",       VX (4, 521),    VX_MASK,     PPCSPE,    {RS, RA}},
2080 {"evextsb",     VX (4, 522),    VX_MASK,     PPCSPE,    {RS, RA}},
2081 {"vrfin",       VX (4, 522),    VX_MASK,     PPCVEC,    {VD, VB}},
2082 {"evextsh",     VX (4, 523),    VX_MASK,     PPCSPE,    {RS, RA}},
2083 {"evrndw",      VX (4, 524),    VX_MASK,     PPCSPE,    {RS, RA}},
2084 {"vspltb",      VX (4, 524),    VX_MASK,     PPCVEC,    {VD, VB, UIMM}},
2085 {"evcntlzw",    VX (4, 525),    VX_MASK,     PPCSPE,    {RS, RA}},
2086 {"evcntlsw",    VX (4, 526),    VX_MASK,     PPCSPE,    {RS, RA}},
2087 {"vupkhsb",     VX (4, 526),    VX_MASK,     PPCVEC,    {VD, VB}},
2088 {"brinc",       VX (4, 527),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2089 {"ps_abs",      XRC(4, 264,0),  XRA_MASK,    PPCPS,     {FRT, FRB}},
2090 {"ps_abs.",     XRC(4, 264,1),  XRA_MASK,    PPCPS,     {FRT, FRB}},
2091 {"evand",       VX (4, 529),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2092 {"evandc",      VX (4, 530),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2093 {"evxor",       VX (4, 534),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2094 {"evmr",        VX (4, 535),    VX_MASK,     PPCSPE,    {RS, RA, BBA}},
2095 {"evor",        VX (4, 535),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2096 {"evnor",       VX (4, 536),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2097 {"evnot",       VX (4, 536),    VX_MASK,     PPCSPE,    {RS, RA, BBA}},
2098 {"get",         APU(4, 268,0),  APU_RA_MASK, PPC405,    {RT, FSL}},
2099 {"eveqv",       VX (4, 537),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2100 {"evorc",       VX (4, 539),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2101 {"evnand",      VX (4, 542),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2102 {"evsrwu",      VX (4, 544),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2103 {"evsrws",      VX (4, 545),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2104 {"evsrwiu",     VX (4, 546),    VX_MASK,     PPCSPE,    {RS, RA, EVUIMM}},
2105 {"evsrwis",     VX (4, 547),    VX_MASK,     PPCSPE,    {RS, RA, EVUIMM}},
2106 {"evslw",       VX (4, 548),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2107 {"evslwi",      VX (4, 550),    VX_MASK,     PPCSPE,    {RS, RA, EVUIMM}},
2108 {"evrlw",       VX (4, 552),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2109 {"evsplati",    VX (4, 553),    VX_MASK,     PPCSPE,    {RS, SIMM}},
2110 {"evrlwi",      VX (4, 554),    VX_MASK,     PPCSPE,    {RS, RA, EVUIMM}},
2111 {"evsplatfi",   VX (4, 555),    VX_MASK,     PPCSPE,    {RS, SIMM}},
2112 {"evmergehi",   VX (4, 556),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2113 {"evmergelo",   VX (4, 557),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2114 {"evmergehilo", VX (4, 558),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2115 {"evmergelohi", VX (4, 559),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2116 {"evcmpgtu",    VX (4, 560),    VX_MASK,     PPCSPE,    {CRFD, RA, RB}},
2117 {"evcmpgts",    VX (4, 561),    VX_MASK,     PPCSPE,    {CRFD, RA, RB}},
2118 {"evcmpltu",    VX (4, 562),    VX_MASK,     PPCSPE,    {CRFD, RA, RB}},
2119 {"evcmplts",    VX (4, 563),    VX_MASK,     PPCSPE,    {CRFD, RA, RB}},
2120 {"evcmpeq",     VX (4, 564),    VX_MASK,     PPCSPE,    {CRFD, RA, RB}},
2121 {"cget",        APU(4, 284,0),  APU_RA_MASK, PPC405,    {RT, FSL}},
2122 {"vadduhs",     VX (4, 576),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2123 {"vminuh",      VX (4, 578),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2124 {"vsrh",        VX (4, 580),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2125 {"vcmpgtuh",    VXR(4, 582,0),  VXR_MASK,    PPCVEC,    {VD, VA, VB}},
2126 {"vmuleuh",     VX (4, 584),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2127 {"vrfiz",       VX (4, 586),    VX_MASK,     PPCVEC,    {VD, VB}},
2128 {"vsplth",      VX (4, 588),    VX_MASK,     PPCVEC,    {VD, VB, UIMM}},
2129 {"vupkhsh",     VX (4, 590),    VX_MASK,     PPCVEC,    {VD, VB}},
2130 {"nget",        APU(4, 300,0),  APU_RA_MASK, PPC405,    {RT, FSL}},
2131 {"evsel",       EVSEL(4,79),    EVSEL_MASK,  PPCSPE,    {RS, RA, RB, CRFS}},
2132 {"ncget",       APU(4, 316,0),  APU_RA_MASK, PPC405,    {RT, FSL}},
2133 {"evfsadd",     VX (4, 640),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2134 {"vadduws",     VX (4, 640),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2135 {"evfssub",     VX (4, 641),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2136 {"vminuw",      VX (4, 642),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2137 {"evfsabs",     VX (4, 644),    VX_MASK,     PPCSPE,    {RS, RA}},
2138 {"vsrw",        VX (4, 644),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2139 {"evfsnabs",    VX (4, 645),    VX_MASK,     PPCSPE,    {RS, RA}},
2140 {"evfsneg",     VX (4, 646),    VX_MASK,     PPCSPE,    {RS, RA}},
2141 {"vcmpgtuw",    VXR(4, 646,0),  VXR_MASK,    PPCVEC,    {VD, VA, VB}},
2142 {"evfsmul",     VX (4, 648),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2143 {"evfsdiv",     VX (4, 649),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2144 {"vrfip",       VX (4, 650),    VX_MASK,     PPCVEC,    {VD, VB}},
2145 {"evfscmpgt",   VX (4, 652),    VX_MASK,     PPCSPE,    {CRFD, RA, RB}},
2146 {"vspltw",      VX (4, 652),    VX_MASK,     PPCVEC,    {VD, VB, UIMM}},
2147 {"evfscmplt",   VX (4, 653),    VX_MASK,     PPCSPE,    {CRFD, RA, RB}},
2148 {"evfscmpeq",   VX (4, 654),    VX_MASK,     PPCSPE,    {CRFD, RA, RB}},
2149 {"vupklsb",     VX (4, 654),    VX_MASK,     PPCVEC,    {VD, VB}},
2150 {"evfscfui",    VX (4, 656),    VX_MASK,     PPCSPE,    {RS, RB}},
2151 {"evfscfsi",    VX (4, 657),    VX_MASK,     PPCSPE,    {RS, RB}},
2152 {"evfscfuf",    VX (4, 658),    VX_MASK,     PPCSPE,    {RS, RB}},
2153 {"evfscfsf",    VX (4, 659),    VX_MASK,     PPCSPE,    {RS, RB}},
2154 {"evfsctui",    VX (4, 660),    VX_MASK,     PPCSPE,    {RS, RB}},
2155 {"evfsctsi",    VX (4, 661),    VX_MASK,     PPCSPE,    {RS, RB}},
2156 {"evfsctuf",    VX (4, 662),    VX_MASK,     PPCSPE,    {RS, RB}},
2157 {"evfsctsf",    VX (4, 663),    VX_MASK,     PPCSPE,    {RS, RB}},
2158 {"evfsctuiz",   VX (4, 664),    VX_MASK,     PPCSPE,    {RS, RB}},
2159 {"put",         APU(4, 332,0),  APU_RT_MASK, PPC405,    {RA, FSL}},
2160 {"evfsctsiz",   VX (4, 666),    VX_MASK,     PPCSPE,    {RS, RB}},
2161 {"evfststgt",   VX (4, 668),    VX_MASK,     PPCSPE,    {CRFD, RA, RB}},
2162 {"evfststlt",   VX (4, 669),    VX_MASK,     PPCSPE,    {CRFD, RA, RB}},
2163 {"evfststeq",   VX (4, 670),    VX_MASK,     PPCSPE,    {CRFD, RA, RB}},
2164 {"cput",        APU(4, 348,0),  APU_RT_MASK, PPC405,    {RA, FSL}},
2165 {"efsadd",      VX (4, 704),    VX_MASK,     PPCEFS,    {RS, RA, RB}},
2166 {"efssub",      VX (4, 705),    VX_MASK,     PPCEFS,    {RS, RA, RB}},
2167 {"efsabs",      VX (4, 708),    VX_MASK,     PPCEFS,    {RS, RA}},
2168 {"vsr",         VX (4, 708),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2169 {"efsnabs",     VX (4, 709),    VX_MASK,     PPCEFS,    {RS, RA}},
2170 {"efsneg",      VX (4, 710),    VX_MASK,     PPCEFS,    {RS, RA}},
2171 {"vcmpgtfp",    VXR(4, 710,0),  VXR_MASK,    PPCVEC,    {VD, VA, VB}},
2172 {"efsmul",      VX (4, 712),    VX_MASK,     PPCEFS,    {RS, RA, RB}},
2173 {"efsdiv",      VX (4, 713),    VX_MASK,     PPCEFS,    {RS, RA, RB}},
2174 {"vrfim",       VX (4, 714),    VX_MASK,     PPCVEC,    {VD, VB}},
2175 {"efscmpgt",    VX (4, 716),    VX_MASK,     PPCEFS,    {CRFD, RA, RB}},
2176 {"efscmplt",    VX (4, 717),    VX_MASK,     PPCEFS,    {CRFD, RA, RB}},
2177 {"efscmpeq",    VX (4, 718),    VX_MASK,     PPCEFS,    {CRFD, RA, RB}},
2178 {"vupklsh",     VX (4, 718),    VX_MASK,     PPCVEC,    {VD, VB}},
2179 {"efscfd",      VX (4, 719),    VX_MASK,     PPCEFS,    {RS, RB}},
2180 {"efscfui",     VX (4, 720),    VX_MASK,     PPCEFS,    {RS, RB}},
2181 {"efscfsi",     VX (4, 721),    VX_MASK,     PPCEFS,    {RS, RB}},
2182 {"efscfuf",     VX (4, 722),    VX_MASK,     PPCEFS,    {RS, RB}},
2183 {"efscfsf",     VX (4, 723),    VX_MASK,     PPCEFS,    {RS, RB}},
2184 {"efsctui",     VX (4, 724),    VX_MASK,     PPCEFS,    {RS, RB}},
2185 {"efsctsi",     VX (4, 725),    VX_MASK,     PPCEFS,    {RS, RB}},
2186 {"efsctuf",     VX (4, 726),    VX_MASK,     PPCEFS,    {RS, RB}},
2187 {"efsctsf",     VX (4, 727),    VX_MASK,     PPCEFS,    {RS, RB}},
2188 {"efsctuiz",    VX (4, 728),    VX_MASK,     PPCEFS,    {RS, RB}},
2189 {"nput",        APU(4, 364,0),  APU_RT_MASK, PPC405,    {RA, FSL}},
2190 {"efsctsiz",    VX (4, 730),    VX_MASK,     PPCEFS,    {RS, RB}},
2191 {"efststgt",    VX (4, 732),    VX_MASK,     PPCEFS,    {CRFD, RA, RB}},
2192 {"efststlt",    VX (4, 733),    VX_MASK,     PPCEFS,    {CRFD, RA, RB}},
2193 {"efststeq",    VX (4, 734),    VX_MASK,     PPCEFS,    {CRFD, RA, RB}},
2194 {"efdadd",      VX (4, 736),    VX_MASK,     PPCEFS,    {RS, RA, RB}},
2195 {"efdsub",      VX (4, 737),    VX_MASK,     PPCEFS,    {RS, RA, RB}},
2196 {"efdcfuid",    VX (4, 738),    VX_MASK,     PPCEFS,    {RS, RB}},
2197 {"efdcfsid",    VX (4, 739),    VX_MASK,     PPCEFS,    {RS, RB}},
2198 {"efdabs",      VX (4, 740),    VX_MASK,     PPCEFS,    {RS, RA}},
2199 {"efdnabs",     VX (4, 741),    VX_MASK,     PPCEFS,    {RS, RA}},
2200 {"efdneg",      VX (4, 742),    VX_MASK,     PPCEFS,    {RS, RA}},
2201 {"efdmul",      VX (4, 744),    VX_MASK,     PPCEFS,    {RS, RA, RB}},
2202 {"efddiv",      VX (4, 745),    VX_MASK,     PPCEFS,    {RS, RA, RB}},
2203 {"efdctuidz",   VX (4, 746),    VX_MASK,     PPCEFS,    {RS, RB}},
2204 {"efdctsidz",   VX (4, 747),    VX_MASK,     PPCEFS,    {RS, RB}},
2205 {"efdcmpgt",    VX (4, 748),    VX_MASK,     PPCEFS,    {CRFD, RA, RB}},
2206 {"efdcmplt",    VX (4, 749),    VX_MASK,     PPCEFS,    {CRFD, RA, RB}},
2207 {"efdcmpeq",    VX (4, 750),    VX_MASK,     PPCEFS,    {CRFD, RA, RB}},
2208 {"efdcfs",      VX (4, 751),    VX_MASK,     PPCEFS,    {RS, RB}},
2209 {"efdcfui",     VX (4, 752),    VX_MASK,     PPCEFS,    {RS, RB}},
2210 {"efdcfsi",     VX (4, 753),    VX_MASK,     PPCEFS,    {RS, RB}},
2211 {"efdcfuf",     VX (4, 754),    VX_MASK,     PPCEFS,    {RS, RB}},
2212 {"efdcfsf",     VX (4, 755),    VX_MASK,     PPCEFS,    {RS, RB}},
2213 {"efdctui",     VX (4, 756),    VX_MASK,     PPCEFS,    {RS, RB}},
2214 {"efdctsi",     VX (4, 757),    VX_MASK,     PPCEFS,    {RS, RB}},
2215 {"efdctuf",     VX (4, 758),    VX_MASK,     PPCEFS,    {RS, RB}},
2216 {"efdctsf",     VX (4, 759),    VX_MASK,     PPCEFS,    {RS, RB}},
2217 {"efdctuiz",    VX (4, 760),    VX_MASK,     PPCEFS,    {RS, RB}},
2218 {"ncput",       APU(4, 380,0),  APU_RT_MASK, PPC405,    {RA, FSL}},
2219 {"efdctsiz",    VX (4, 762),    VX_MASK,     PPCEFS,    {RS, RB}},
2220 {"efdtstgt",    VX (4, 764),    VX_MASK,     PPCEFS,    {CRFD, RA, RB}},
2221 {"efdtstlt",    VX (4, 765),    VX_MASK,     PPCEFS,    {CRFD, RA, RB}},
2222 {"efdtsteq",    VX (4, 766),    VX_MASK,     PPCEFS,    {CRFD, RA, RB}},
2223 {"evlddx",      VX (4, 768),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2224 {"vaddsbs",     VX (4, 768),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2225 {"evldd",       VX (4, 769),    VX_MASK,     PPCSPE,    {RS, EVUIMM_8, RA}},
2226 {"evldwx",      VX (4, 770),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2227 {"vminsb",      VX (4, 770),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2228 {"evldw",       VX (4, 771),    VX_MASK,     PPCSPE,    {RS, EVUIMM_8, RA}},
2229 {"evldhx",      VX (4, 772),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2230 {"vsrab",       VX (4, 772),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2231 {"evldh",       VX (4, 773),    VX_MASK,     PPCSPE,    {RS, EVUIMM_8, RA}},
2232 {"vcmpgtsb",    VXR(4, 774,0),  VXR_MASK,    PPCVEC,    {VD, VA, VB}},
2233 {"evlhhesplatx",VX (4, 776),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2234 {"vmulesb",     VX (4, 776),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2235 {"evlhhesplat", VX (4, 777),    VX_MASK,     PPCSPE,    {RS, EVUIMM_2, RA}},
2236 {"vcfux",       VX (4, 778),    VX_MASK,     PPCVEC,    {VD, VB, UIMM}},
2237 {"evlhhousplatx",VX(4, 780),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2238 {"vspltisb",    VX (4, 780),    VX_MASK,     PPCVEC,    {VD, SIMM}},
2239 {"evlhhousplat",VX (4, 781),    VX_MASK,     PPCSPE,    {RS, EVUIMM_2, RA}},
2240 {"evlhhossplatx",VX(4, 782),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2241 {"vpkpx",       VX (4, 782),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2242 {"evlhhossplat",VX (4, 783),    VX_MASK,     PPCSPE,    {RS, EVUIMM_2, RA}},
2243 {"mullhwu",     XRC(4, 392,0),  X_MASK,  PPC405|PPC440, {RT, RA, RB}},
2244 {"evlwhex",     VX (4, 784),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2245 {"mullhwu.",    XRC(4, 392,1),  X_MASK,  PPC405|PPC440, {RT, RA, RB}},
2246 {"evlwhe",      VX (4, 785),    VX_MASK,     PPCSPE,    {RS, EVUIMM_4, RA}},
2247 {"evlwhoux",    VX (4, 788),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2248 {"evlwhou",     VX (4, 789),    VX_MASK,     PPCSPE,    {RS, EVUIMM_4, RA}},
2249 {"evlwhosx",    VX (4, 790),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2250 {"evlwhos",     VX (4, 791),    VX_MASK,     PPCSPE,    {RS, EVUIMM_4, RA}},
2251 {"maclhwu",     XO (4, 396,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2252 {"evlwwsplatx", VX (4, 792),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2253 {"maclhwu.",    XO (4, 396,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2254 {"evlwwsplat",  VX (4, 793),    VX_MASK,     PPCSPE,    {RS, EVUIMM_4, RA}},
2255 {"evlwhsplatx", VX (4, 796),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2256 {"evlwhsplat",  VX (4, 797),    VX_MASK,     PPCSPE,    {RS, EVUIMM_4, RA}},
2257 {"evstddx",     VX (4, 800),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2258 {"evstdd",      VX (4, 801),    VX_MASK,     PPCSPE,    {RS, EVUIMM_8, RA}},
2259 {"evstdwx",     VX (4, 802),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2260 {"evstdw",      VX (4, 803),    VX_MASK,     PPCSPE,    {RS, EVUIMM_8, RA}},
2261 {"evstdhx",     VX (4, 804),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2262 {"evstdh",      VX (4, 805),    VX_MASK,     PPCSPE,    {RS, EVUIMM_8, RA}},
2263 {"evstwhex",    VX (4, 816),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2264 {"evstwhe",     VX (4, 817),    VX_MASK,     PPCSPE,    {RS, EVUIMM_4, RA}},
2265 {"evstwhox",    VX (4, 820),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2266 {"evstwho",     VX (4, 821),    VX_MASK,     PPCSPE,    {RS, EVUIMM_4, RA}},
2267 {"evstwwex",    VX (4, 824),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2268 {"evstwwe",     VX (4, 825),    VX_MASK,     PPCSPE,    {RS, EVUIMM_4, RA}},
2269 {"evstwwox",    VX (4, 828),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2270 {"evstwwo",     VX (4, 829),    VX_MASK,     PPCSPE,    {RS, EVUIMM_4, RA}},
2271 {"vaddshs",     VX (4, 832),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2272 {"vminsh",      VX (4, 834),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2273 {"vsrah",       VX (4, 836),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2274 {"vcmpgtsh",    VXR(4, 838,0),  VXR_MASK,    PPCVEC,    {VD, VA, VB}},
2275 {"vmulesh",     VX (4, 840),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2276 {"vcfsx",       VX (4, 842),    VX_MASK,     PPCVEC,    {VD, VB, UIMM}},
2277 {"vspltish",    VX (4, 844),    VX_MASK,     PPCVEC,    {VD, SIMM}},
2278 {"vupkhpx",     VX (4, 846),    VX_MASK,     PPCVEC,    {VD, VB}},
2279 {"mullhw",      XRC(4, 424,0),  X_MASK,  PPC405|PPC440, {RT, RA, RB}},
2280 {"mullhw.",     XRC(4, 424,1),  X_MASK,  PPC405|PPC440, {RT, RA, RB}},
2281 {"maclhw",      XO (4, 428,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2282 {"maclhw.",     XO (4, 428,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2283 {"nmaclhw",     XO (4, 430,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2284 {"nmaclhw.",    XO (4, 430,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2285 {"vaddsws",     VX (4, 896),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2286 {"vminsw",      VX (4, 898),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2287 {"vsraw",       VX (4, 900),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2288 {"vcmpgtsw",    VXR(4, 902,0),  VXR_MASK,    PPCVEC,    {VD, VA, VB}},
2289 {"vctuxs",      VX (4, 906),    VX_MASK,     PPCVEC,    {VD, VB, UIMM}},
2290 {"vspltisw",    VX (4, 908),    VX_MASK,     PPCVEC,    {VD, SIMM}},
2291 {"maclhwsu",    XO (4, 460,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2292 {"maclhwsu.",   XO (4, 460,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2293 {"vcmpbfp",     VXR(4, 966,0),  VXR_MASK,    PPCVEC,    {VD, VA, VB}},
2294 {"vctsxs",      VX (4, 970),    VX_MASK,     PPCVEC,    {VD, VB, UIMM}},
2295 {"vupklpx",     VX (4, 974),    VX_MASK,     PPCVEC,    {VD, VB}},
2296 {"maclhws",     XO (4, 492,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2297 {"maclhws.",    XO (4, 492,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2298 {"nmaclhws",    XO (4, 494,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2299 {"nmaclhws.",   XO (4, 494,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2300 {"vsububm",     VX (4,1024),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2301 {"vavgub",      VX (4,1026),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2302 {"evmhessf",    VX (4,1027),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2303 {"vand",        VX (4,1028),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2304 {"vcmpequb.",   VXR(4,   6,1),  VXR_MASK,    PPCVEC,    {VD, VA, VB}},
2305 {"udi0fcm.",    APU(4, 515,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
2306 {"udi0fcm",     APU(4, 515,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
2307 {"evmhossf",    VX (4,1031),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2308 {"evmheumi",    VX (4,1032),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2309 {"evmhesmi",    VX (4,1033),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2310 {"vmaxfp",      VX (4,1034),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2311 {"evmhesmf",    VX (4,1035),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2312 {"evmhoumi",    VX (4,1036),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2313 {"vslo",        VX (4,1036),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2314 {"evmhosmi",    VX (4,1037),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2315 {"evmhosmf",    VX (4,1039),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2316 {"machhwuo",    XO (4,  12,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2317 {"machhwuo.",   XO (4,  12,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2318 {"ps_merge00",  XOPS(4,528,0),  XOPS_MASK,   PPCPS,     {FRT, FRA, FRB}},
2319 {"ps_merge00.", XOPS(4,528,1),  XOPS_MASK,   PPCPS,     {FRT, FRA, FRB}},
2320 {"evmhessfa",   VX (4,1059),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2321 {"evmhossfa",   VX (4,1063),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2322 {"evmheumia",   VX (4,1064),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2323 {"evmhesmia",   VX (4,1065),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2324 {"evmhesmfa",   VX (4,1067),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2325 {"evmhoumia",   VX (4,1068),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2326 {"evmhosmia",   VX (4,1069),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2327 {"evmhosmfa",   VX (4,1071),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2328 {"vsubuhm",     VX (4,1088),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2329 {"vavguh",      VX (4,1090),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2330 {"vandc",       VX (4,1092),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2331 {"vcmpequh.",   VXR(4,  70,1),  VXR_MASK,    PPCVEC,    {VD, VA, VB}},
2332 {"udi1fcm.",    APU(4, 547,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
2333 {"udi1fcm",     APU(4, 547,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
2334 {"evmwhssf",    VX (4,1095),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2335 {"evmwlumi",    VX (4,1096),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2336 {"vminfp",      VX (4,1098),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2337 {"evmwhumi",    VX (4,1100),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2338 {"vsro",        VX (4,1100),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2339 {"evmwhsmi",    VX (4,1101),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2340 {"evmwhsmf",    VX (4,1103),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2341 {"evmwssf",     VX (4,1107),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2342 {"machhwo",     XO (4,  44,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2343 {"evmwumi",     VX (4,1112),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2344 {"machhwo.",    XO (4,  44,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2345 {"evmwsmi",     VX (4,1113),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2346 {"evmwsmf",     VX (4,1115),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2347 {"nmachhwo",    XO (4,  46,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2348 {"nmachhwo.",   XO (4,  46,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2349 {"ps_merge01",  XOPS(4,560,0),  XOPS_MASK,   PPCPS,     {FRT, FRA, FRB}},
2350 {"ps_merge01.", XOPS(4,560,1),  XOPS_MASK,   PPCPS,     {FRT, FRA, FRB}},
2351 {"evmwhssfa",   VX (4,1127),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2352 {"evmwlumia",   VX (4,1128),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2353 {"evmwhumia",   VX (4,1132),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2354 {"evmwhsmia",   VX (4,1133),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2355 {"evmwhsmfa",   VX (4,1135),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2356 {"evmwssfa",    VX (4,1139),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2357 {"evmwumia",    VX (4,1144),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2358 {"evmwsmia",    VX (4,1145),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2359 {"evmwsmfa",    VX (4,1147),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2360 {"vsubuwm",     VX (4,1152),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2361 {"vavguw",      VX (4,1154),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2362 {"vor",         VX (4,1156),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2363 {"vcmpequw.",   VXR(4, 134,1),  VXR_MASK,    PPCVEC,    {VD, VA, VB}},
2364 {"udi2fcm.",    APU(4, 579,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
2365 {"udi2fcm",     APU(4, 579,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
2366 {"machhwsuo",   XO (4,  76,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2367 {"machhwsuo.",  XO (4,  76,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2368 {"ps_merge10",  XOPS(4,592,0),  XOPS_MASK,   PPCPS,     {FRT, FRA, FRB}},
2369 {"ps_merge10.", XOPS(4,592,1),  XOPS_MASK,   PPCPS,     {FRT, FRA, FRB}},
2370 {"evaddusiaaw", VX (4,1216),    VX_MASK,     PPCSPE,    {RS, RA}},
2371 {"evaddssiaaw", VX (4,1217),    VX_MASK,     PPCSPE,    {RS, RA}},
2372 {"evsubfusiaaw",VX (4,1218),    VX_MASK,     PPCSPE,    {RS, RA}},
2373 {"evsubfssiaaw",VX (4,1219),    VX_MASK,     PPCSPE,    {RS, RA}},
2374 {"evmra",       VX (4,1220),    VX_MASK,     PPCSPE,    {RS, RA}},
2375 {"vxor",        VX (4,1220),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2376 {"evdivws",     VX (4,1222),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2377 {"vcmpeqfp.",   VXR(4, 198,1),  VXR_MASK,    PPCVEC,    {VD, VA, VB}},
2378 {"udi3fcm.",    APU(4, 611,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
2379 {"udi3fcm",     APU(4, 611,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
2380 {"evdivwu",     VX (4,1223),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2381 {"evaddumiaaw", VX (4,1224),    VX_MASK,     PPCSPE,    {RS, RA}},
2382 {"evaddsmiaaw", VX (4,1225),    VX_MASK,     PPCSPE,    {RS, RA}},
2383 {"evsubfumiaaw",VX (4,1226),    VX_MASK,     PPCSPE,    {RS, RA}},
2384 {"evsubfsmiaaw",VX (4,1227),    VX_MASK,     PPCSPE,    {RS, RA}},
2385 {"machhwso",    XO (4, 108,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2386 {"machhwso.",   XO (4, 108,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2387 {"nmachhwso",   XO (4, 110,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2388 {"nmachhwso.",  XO (4, 110,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2389 {"ps_merge11",  XOPS(4,624,0),  XOPS_MASK,   PPCPS,     {FRT, FRA, FRB}},
2390 {"ps_merge11.", XOPS(4,624,1),  XOPS_MASK,   PPCPS,     {FRT, FRA, FRB}},
2391 {"evmheusiaaw", VX (4,1280),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2392 {"evmhessiaaw", VX (4,1281),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2393 {"vavgsb",      VX (4,1282),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2394 {"evmhessfaaw", VX (4,1283),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2395 {"evmhousiaaw", VX (4,1284),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2396 {"vnor",        VX (4,1284),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2397 {"evmhossiaaw", VX (4,1285),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2398 {"udi4fcm.",    APU(4, 643,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
2399 {"udi4fcm",     APU(4, 643,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
2400 {"evmhossfaaw", VX (4,1287),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2401 {"evmheumiaaw", VX (4,1288),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2402 {"evmhesmiaaw", VX (4,1289),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2403 {"evmhesmfaaw", VX (4,1291),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2404 {"evmhoumiaaw", VX (4,1292),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2405 {"evmhosmiaaw", VX (4,1293),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2406 {"evmhosmfaaw", VX (4,1295),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2407 {"macchwuo",    XO (4, 140,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2408 {"macchwuo.",   XO (4, 140,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2409 {"evmhegumiaa", VX (4,1320),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2410 {"evmhegsmiaa", VX (4,1321),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2411 {"evmhegsmfaa", VX (4,1323),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2412 {"evmhogumiaa", VX (4,1324),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2413 {"evmhogsmiaa", VX (4,1325),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2414 {"evmhogsmfaa", VX (4,1327),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2415 {"evmwlusiaaw", VX (4,1344),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2416 {"evmwlssiaaw", VX (4,1345),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2417 {"vavgsh",      VX (4,1346),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2418 {"udi5fcm.",    APU(4, 675,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
2419 {"udi5fcm",     APU(4, 675,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
2420 {"evmwlumiaaw", VX (4,1352),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2421 {"evmwlsmiaaw", VX (4,1353),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2422 {"evmwssfaa",   VX (4,1363),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2423 {"macchwo",     XO (4, 172,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2424 {"evmwumiaa",   VX (4,1368),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2425 {"macchwo.",    XO (4, 172,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2426 {"evmwsmiaa",   VX (4,1369),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2427 {"evmwsmfaa",   VX (4,1371),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2428 {"nmacchwo",    XO (4, 174,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2429 {"nmacchwo.",   XO (4, 174,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2430 {"evmheusianw", VX (4,1408),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2431 {"vsubcuw",     VX (4,1408),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2432 {"evmhessianw", VX (4,1409),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2433 {"vavgsw",      VX (4,1410),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2434 {"evmhessfanw", VX (4,1411),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2435 {"evmhousianw", VX (4,1412),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2436 {"evmhossianw", VX (4,1413),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2437 {"udi6fcm.",    APU(4, 707,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
2438 {"udi6fcm",     APU(4, 707,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
2439 {"evmhossfanw", VX (4,1415),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2440 {"evmheumianw", VX (4,1416),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2441 {"evmhesmianw", VX (4,1417),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2442 {"evmhesmfanw", VX (4,1419),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2443 {"evmhoumianw", VX (4,1420),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2444 {"evmhosmianw", VX (4,1421),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2445 {"evmhosmfanw", VX (4,1423),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2446 {"macchwsuo",   XO (4, 204,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2447 {"macchwsuo.",  XO (4, 204,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2448 {"evmhegumian", VX (4,1448),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2449 {"evmhegsmian", VX (4,1449),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2450 {"evmhegsmfan", VX (4,1451),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2451 {"evmhogumian", VX (4,1452),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2452 {"evmhogsmian", VX (4,1453),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2453 {"evmhogsmfan", VX (4,1455),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2454 {"evmwlusianw", VX (4,1472),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2455 {"evmwlssianw", VX (4,1473),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2456 {"vcmpgefp.",   VXR(4, 454,1),  VXR_MASK,    PPCVEC,    {VD, VA, VB}},
2457 {"udi7fcm.",    APU(4, 739,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
2458 {"udi7fcm",     APU(4, 739,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}},
2459 {"evmwlumianw", VX (4,1480),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2460 {"evmwlsmianw", VX (4,1481),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2461 {"evmwssfan",   VX (4,1491),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2462 {"macchwso",    XO (4, 236,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2463 {"evmwumian",   VX (4,1496),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2464 {"macchwso.",   XO (4, 236,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2465 {"evmwsmian",   VX (4,1497),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2466 {"evmwsmfan",   VX (4,1499),    VX_MASK,     PPCSPE,    {RS, RA, RB}},
2467 {"nmacchwso",   XO (4, 238,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2468 {"nmacchwso.",  XO (4, 238,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2469 {"vsububs",     VX (4,1536),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2470 {"mfvscr",      VX (4,1540),    VX_MASK,     PPCVEC,    {VD}},
2471 {"vcmpgtub.",   VXR(4, 518,1),  VXR_MASK,    PPCVEC,    {VD, VA, VB}},
2472 {"udi8fcm.",    APU(4, 771,0),  APU_MASK,    PPC440,    {URT, URA, URB}},
2473 {"udi8fcm",     APU(4, 771,1),  APU_MASK,    PPC440,    {URT, URA, URB}},
2474 {"vsum4ubs",    VX (4,1544),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2475 {"vsubuhs",     VX (4,1600),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2476 {"mtvscr",      VX (4,1604),    VX_MASK,     PPCVEC,    {VB}},
2477 {"vcmpgtuh.",   VXR(4, 582,1),  VXR_MASK,    PPCVEC,    {VD, VA, VB}},
2478 {"vsum4shs",    VX (4,1608),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2479 {"udi9fcm.",    APU(4, 804,0),  APU_MASK,    PPC440,    {URT, URA, URB}},
2480 {"udi9fcm",     APU(4, 804,1),  APU_MASK,    PPC440,    {URT, URA, URB}},
2481 {"vsubuws",     VX (4,1664),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2482 {"vcmpgtuw.",   VXR(4, 646,1),  VXR_MASK,    PPCVEC,    {VD, VA, VB}},
2483 {"udi10fcm.",   APU(4, 835,0),  APU_MASK,    PPC440,    {URT, URA, URB}},
2484 {"udi10fcm",    APU(4, 835,1),  APU_MASK,    PPC440,    {URT, URA, URB}},
2485 {"vsum2sws",    VX (4,1672),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2486 {"vcmpgtfp.",   VXR(4, 710,1),  VXR_MASK,    PPCVEC,    {VD, VA, VB}},
2487 {"udi11fcm.",   APU(4, 867,0),  APU_MASK,    PPC440,    {URT, URA, URB}},
2488 {"udi11fcm",    APU(4, 867,1),  APU_MASK,    PPC440,    {URT, URA, URB}},
2489 {"vsubsbs",     VX (4,1792),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2490 {"vcmpgtsb.",   VXR(4, 774,1),  VXR_MASK,    PPCVEC,    {VD, VA, VB}},
2491 {"udi12fcm.",   APU(4, 899,0),  APU_MASK,    PPC440,    {URT, URA, URB}},
2492 {"udi12fcm",    APU(4, 899,1),  APU_MASK,    PPC440,    {URT, URA, URB}},
2493 {"vsum4sbs",    VX (4,1800),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2494 {"maclhwuo",    XO (4, 396,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2495 {"maclhwuo.",   XO (4, 396,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2496 {"vsubshs",     VX (4,1856),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2497 {"vcmpgtsh.",   VXR(4, 838,1),  VXR_MASK,    PPCVEC,    {VD, VA, VB}},
2498 {"udi13fcm.",   APU(4, 931,0),  APU_MASK,    PPC440,    {URT, URA, URB}},
2499 {"udi13fcm",    APU(4, 931,1),  APU_MASK,    PPC440,    {URT, URA, URB}},
2500 {"maclhwo",     XO (4, 428,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2501 {"maclhwo.",    XO (4, 428,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2502 {"nmaclhwo",    XO (4, 430,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2503 {"nmaclhwo.",   XO (4, 430,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2504 {"vsubsws",     VX (4,1920),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2505 {"vcmpgtsw.",   VXR(4, 902,1),  VXR_MASK,    PPCVEC,    {VD, VA, VB}},
2506 {"udi14fcm.",   APU(4, 963,0),  APU_MASK,    PPC440,    {URT, URA, URB}},
2507 {"udi14fcm",    APU(4, 963,1),  APU_MASK,    PPC440,    {URT, URA, URB}},
2508 {"vsumsws",     VX (4,1928),    VX_MASK,     PPCVEC,    {VD, VA, VB}},
2509 {"maclhwsuo",   XO (4, 460,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2510 {"maclhwsuo.",  XO (4, 460,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2511 {"vcmpbfp.",    VXR(4, 966,1),  VXR_MASK,    PPCVEC,    {VD, VA, VB}},
2512 {"udi15fcm.",   APU(4, 995,0),  APU_MASK,    PPC440,    {URT, URA, URB}},
2513 {"udi15fcm",    APU(4, 995,1),  APU_MASK,    PPC440,    {URT, URA, URB}},
2514 {"maclhwso",    XO (4, 492,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2515 {"maclhwso.",   XO (4, 492,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2516 {"nmaclhwso",   XO (4, 494,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2517 {"nmaclhwso.",  XO (4, 494,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2518 {"dcbz_l",      X  (4,1014),    XRT_MASK,    PPCPS,     {RA, RB}},
2519
2520 {"mulli",       OP(7),          OP_MASK,     PPCCOM,    {RT, RA, SI}},
2521 {"muli",        OP(7),          OP_MASK,     PWRCOM,    {RT, RA, SI}},
2522
2523 {"subfic",      OP(8),          OP_MASK,     PPCCOM,    {RT, RA, SI}},
2524 {"sfi",         OP(8),          OP_MASK,     PWRCOM,    {RT, RA, SI}},
2525
2526 {"dozi",        OP(9),          OP_MASK,     M601,      {RT, RA, SI}},
2527
2528 {"bce",         B(9,0,0),       B_MASK,      BOOKE64,   {BO, BI, BD}},
2529 {"bcel",        B(9,0,1),       B_MASK,      BOOKE64,   {BO, BI, BD}},
2530 {"bcea",        B(9,1,0),       B_MASK,      BOOKE64,   {BO, BI, BDA}},
2531 {"bcela",       B(9,1,1),       B_MASK,      BOOKE64,   {BO, BI, BDA}},
2532
2533 {"cmplwi",      OPL(10,0),      OPL_MASK,    PPCCOM,    {OBF, RA, UI}},
2534 {"cmpldi",      OPL(10,1),      OPL_MASK,    PPC64,     {OBF, RA, UI}},
2535 {"cmpli",       OP(10),         OP_MASK,     PPC,       {BF, L, RA, UI}},
2536 {"cmpli",       OP(10),         OP_MASK,     PWRCOM,    {BF, RA, UI}},
2537
2538 {"cmpwi",       OPL(11,0),      OPL_MASK,    PPCCOM,    {OBF, RA, SI}},
2539 {"cmpdi",       OPL(11,1),      OPL_MASK,    PPC64,     {OBF, RA, SI}},
2540 {"cmpi",        OP(11),         OP_MASK,     PPC,       {BF, L, RA, SI}},
2541 {"cmpi",        OP(11),         OP_MASK,     PWRCOM,    {BF, RA, SI}},
2542
2543 {"addic",       OP(12),         OP_MASK,     PPCCOM,    {RT, RA, SI}},
2544 {"ai",          OP(12),         OP_MASK,     PWRCOM,    {RT, RA, SI}},
2545 {"subic",       OP(12),         OP_MASK,     PPCCOM,    {RT, RA, NSI}},
2546
2547 {"addic.",      OP(13),         OP_MASK,     PPCCOM,    {RT, RA, SI}},
2548 {"ai.",         OP(13),         OP_MASK,     PWRCOM,    {RT, RA, SI}},
2549 {"subic.",      OP(13),         OP_MASK,     PPCCOM,    {RT, RA, NSI}},
2550
2551 {"li",          OP(14),         DRA_MASK,    PPCCOM,    {RT, SI}},
2552 {"lil",         OP(14),         DRA_MASK,    PWRCOM,    {RT, SI}},
2553 {"addi",        OP(14),         OP_MASK,     PPCCOM,    {RT, RA0, SI}},
2554 {"cal",         OP(14),         OP_MASK,     PWRCOM,    {RT, D, RA0}},
2555 {"subi",        OP(14),         OP_MASK,     PPCCOM,    {RT, RA0, NSI}},
2556 {"la",          OP(14),         OP_MASK,     PPCCOM,    {RT, D, RA0}},
2557
2558 {"lis",         OP(15),         DRA_MASK,    PPCCOM,    {RT, SISIGNOPT}},
2559 {"liu",         OP(15),         DRA_MASK,    PWRCOM,    {RT, SISIGNOPT}},
2560 {"addis",       OP(15),         OP_MASK,     PPCCOM,    {RT, RA0, SISIGNOPT}},
2561 {"cau",         OP(15),         OP_MASK,     PWRCOM,    {RT, RA0, SISIGNOPT}},
2562 {"subis",       OP(15),         OP_MASK,     PPCCOM,    {RT, RA0, NSI}},
2563
2564 {"bdnz-",    BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PPCCOM,   {BDM}},
2565 {"bdnz+",    BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PPCCOM,   {BDP}},
2566 {"bdnz",     BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PPCCOM,   {BD}},
2567 {"bdn",      BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PWRCOM,   {BD}},
2568 {"bdnzl-",   BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PPCCOM,   {BDM}},
2569 {"bdnzl+",   BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PPCCOM,   {BDP}},
2570 {"bdnzl",    BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PPCCOM,   {BD}},
2571 {"bdnl",     BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PWRCOM,   {BD}},
2572 {"bdnza-",   BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PPCCOM,   {BDMA}},
2573 {"bdnza+",   BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PPCCOM,   {BDPA}},
2574 {"bdnza",    BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PPCCOM,   {BDA}},
2575 {"bdna",     BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PWRCOM,   {BDA}},
2576 {"bdnzla-",  BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   {BDMA}},
2577 {"bdnzla+",  BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   {BDPA}},
2578 {"bdnzla",   BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   {BDA}},
2579 {"bdnla",    BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PWRCOM,   {BDA}},
2580 {"bdz-",     BBO(16,BODZ,0,0),          BBOATBI_MASK,  PPCCOM,   {BDM}},
2581 {"bdz+",     BBO(16,BODZ,0,0),          BBOATBI_MASK,  PPCCOM,   {BDP}},
2582 {"bdz",      BBO(16,BODZ,0,0),          BBOATBI_MASK,  COM,      {BD}},
2583 {"bdzl-",    BBO(16,BODZ,0,1),          BBOATBI_MASK,  PPCCOM,   {BDM}},
2584 {"bdzl+",    BBO(16,BODZ,0,1),          BBOATBI_MASK,  PPCCOM,   {BDP}},
2585 {"bdzl",     BBO(16,BODZ,0,1),          BBOATBI_MASK,  COM,      {BD}},
2586 {"bdza-",    BBO(16,BODZ,1,0),          BBOATBI_MASK,  PPCCOM,   {BDMA}},
2587 {"bdza+",    BBO(16,BODZ,1,0),          BBOATBI_MASK,  PPCCOM,   {BDPA}},
2588 {"bdza",     BBO(16,BODZ,1,0),          BBOATBI_MASK,  COM,      {BDA}},
2589 {"bdzla-",   BBO(16,BODZ,1,1),          BBOATBI_MASK,  PPCCOM,   {BDMA}},
2590 {"bdzla+",   BBO(16,BODZ,1,1),          BBOATBI_MASK,  PPCCOM,   {BDPA}},
2591 {"bdzla",    BBO(16,BODZ,1,1),          BBOATBI_MASK,  COM,      {BDA}},
2592
2593 {"bge-",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDM}},
2594 {"bge+",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDP}},
2595 {"bge",      BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  COM,      {CR, BD}},
2596 {"bnl-",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDM}},
2597 {"bnl+",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDP}},
2598 {"bnl",      BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  COM,      {CR, BD}},
2599 {"bgel-",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDM}},
2600 {"bgel+",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDP}},
2601 {"bgel",     BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  COM,      {CR, BD}},
2602 {"bnll-",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDM}},
2603 {"bnll+",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDP}},
2604 {"bnll",     BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  COM,      {CR, BD}},
2605 {"bgea-",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDMA}},
2606 {"bgea+",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDPA}},
2607 {"bgea",     BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  COM,      {CR, BDA}},
2608 {"bnla-",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDMA}},
2609 {"bnla+",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDPA}},
2610 {"bnla",     BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  COM,      {CR, BDA}},
2611 {"bgela-",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDMA}},
2612 {"bgela+",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDPA}},
2613 {"bgela",    BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  COM,      {CR, BDA}},
2614 {"bnlla-",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDMA}},
2615 {"bnlla+",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDPA}},
2616 {"bnlla",    BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  COM,      {CR, BDA}},
2617 {"ble-",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDM}},
2618 {"ble+",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDP}},
2619 {"ble",      BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  COM,      {CR, BD}},
2620 {"bng-",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDM}},
2621 {"bng+",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDP}},
2622 {"bng",      BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  COM,      {CR, BD}},
2623 {"blel-",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDM}},
2624 {"blel+",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDP}},
2625 {"blel",     BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  COM,      {CR, BD}},
2626 {"bngl-",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDM}},
2627 {"bngl+",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDP}},
2628 {"bngl",     BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  COM,      {CR, BD}},
2629 {"blea-",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDMA}},
2630 {"blea+",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDPA}},
2631 {"blea",     BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  COM,      {CR, BDA}},
2632 {"bnga-",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDMA}},
2633 {"bnga+",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDPA}},
2634 {"bnga",     BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  COM,      {CR, BDA}},
2635 {"blela-",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDMA}},
2636 {"blela+",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDPA}},
2637 {"blela",    BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  COM,      {CR, BDA}},
2638 {"bngla-",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDMA}},
2639 {"bngla+",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDPA}},
2640 {"bngla",    BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  COM,      {CR, BDA}},
2641 {"bne-",     BBOCB(16,BOF,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDM}},
2642 {"bne+",     BBOCB(16,BOF,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDP}},
2643 {"bne",      BBOCB(16,BOF,CBEQ,0,0),    BBOATCB_MASK,  COM,      {CR, BD}},
2644 {"bnel-",    BBOCB(16,BOF,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDM}},
2645 {"bnel+",    BBOCB(16,BOF,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDP}},
2646 {"bnel",     BBOCB(16,BOF,CBEQ,0,1),    BBOATCB_MASK,  COM,      {CR, BD}},
2647 {"bnea-",    BBOCB(16,BOF,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDMA}},
2648 {"bnea+",    BBOCB(16,BOF,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDPA}},
2649 {"bnea",     BBOCB(16,BOF,CBEQ,1,0),    BBOATCB_MASK,  COM,      {CR, BDA}},
2650 {"bnela-",   BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDMA}},
2651 {"bnela+",   BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDPA}},
2652 {"bnela",    BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  COM,      {CR, BDA}},
2653 {"bns-",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDM}},
2654 {"bns+",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDP}},
2655 {"bns",      BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  COM,      {CR, BD}},
2656 {"bnu-",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDM}},
2657 {"bnu+",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDP}},
2658 {"bnu",      BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   {CR, BD}},
2659 {"bnsl-",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDM}},
2660 {"bnsl+",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDP}},
2661 {"bnsl",     BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  COM,      {CR, BD}},
2662 {"bnul-",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDM}},
2663 {"bnul+",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDP}},
2664 {"bnul",     BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   {CR, BD}},
2665 {"bnsa-",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDMA}},
2666 {"bnsa+",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDPA}},
2667 {"bnsa",     BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  COM,      {CR, BDA}},
2668 {"bnua-",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDMA}},
2669 {"bnua+",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDPA}},
2670 {"bnua",     BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDA}},
2671 {"bnsla-",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDMA}},
2672 {"bnsla+",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDPA}},
2673 {"bnsla",    BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  COM,      {CR, BDA}},
2674 {"bnula-",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDMA}},
2675 {"bnula+",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDPA}},
2676 {"bnula",    BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDA}},
2677
2678 {"blt-",     BBOCB(16,BOT,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDM}},
2679 {"blt+",     BBOCB(16,BOT,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDP}},
2680 {"blt",      BBOCB(16,BOT,CBLT,0,0),    BBOATCB_MASK,  COM,      {CR, BD}},
2681 {"bltl-",    BBOCB(16,BOT,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDM}},
2682 {"bltl+",    BBOCB(16,BOT,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDP}},
2683 {"bltl",     BBOCB(16,BOT,CBLT,0,1),    BBOATCB_MASK,  COM,      {CR, BD}},
2684 {"blta-",    BBOCB(16,BOT,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDMA}},
2685 {"blta+",    BBOCB(16,BOT,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDPA}},
2686 {"blta",     BBOCB(16,BOT,CBLT,1,0),    BBOATCB_MASK,  COM,      {CR, BDA}},
2687 {"bltla-",   BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDMA}},
2688 {"bltla+",   BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDPA}},
2689 {"bltla",    BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  COM,      {CR, BDA}},
2690 {"bgt-",     BBOCB(16,BOT,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDM}},
2691 {"bgt+",     BBOCB(16,BOT,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDP}},
2692 {"bgt",      BBOCB(16,BOT,CBGT,0,0),    BBOATCB_MASK,  COM,      {CR, BD}},
2693 {"bgtl-",    BBOCB(16,BOT,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDM}},
2694 {"bgtl+",    BBOCB(16,BOT,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDP}},
2695 {"bgtl",     BBOCB(16,BOT,CBGT,0,1),    BBOATCB_MASK,  COM,      {CR, BD}},
2696 {"bgta-",    BBOCB(16,BOT,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDMA}},
2697 {"bgta+",    BBOCB(16,BOT,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDPA}},
2698 {"bgta",     BBOCB(16,BOT,CBGT,1,0),    BBOATCB_MASK,  COM,      {CR, BDA}},
2699 {"bgtla-",   BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDMA}},
2700 {"bgtla+",   BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDPA}},
2701 {"bgtla",    BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  COM,      {CR, BDA}},
2702 {"beq-",     BBOCB(16,BOT,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDM}},
2703 {"beq+",     BBOCB(16,BOT,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDP}},
2704 {"beq",      BBOCB(16,BOT,CBEQ,0,0),    BBOATCB_MASK,  COM,      {CR, BD}},
2705 {"beql-",    BBOCB(16,BOT,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDM}},
2706 {"beql+",    BBOCB(16,BOT,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDP}},
2707 {"beql",     BBOCB(16,BOT,CBEQ,0,1),    BBOATCB_MASK,  COM,      {CR, BD}},
2708 {"beqa-",    BBOCB(16,BOT,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDMA}},
2709 {"beqa+",    BBOCB(16,BOT,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDPA}},
2710 {"beqa",     BBOCB(16,BOT,CBEQ,1,0),    BBOATCB_MASK,  COM,      {CR, BDA}},
2711 {"beqla-",   BBOCB(16,BOT,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDMA}},
2712 {"beqla+",   BBOCB(16,BOT,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDPA}},
2713 {"beqla",    BBOCB(16,BOT,CBEQ,1,1),    BBOATCB_MASK,  COM,      {CR, BDA}},
2714 {"bso-",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDM}},
2715 {"bso+",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDP}},
2716 {"bso",      BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  COM,      {CR, BD}},
2717 {"bun-",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDM}},
2718 {"bun+",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDP}},
2719 {"bun",      BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   {CR, BD}},
2720 {"bsol-",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDM}},
2721 {"bsol+",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDP}},
2722 {"bsol",     BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  COM,      {CR, BD}},
2723 {"bunl-",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDM}},
2724 {"bunl+",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDP}},
2725 {"bunl",     BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   {CR, BD}},
2726 {"bsoa-",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDMA}},
2727 {"bsoa+",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDPA}},
2728 {"bsoa",     BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  COM,      {CR, BDA}},
2729 {"buna-",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDMA}},
2730 {"buna+",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDPA}},
2731 {"buna",     BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   {CR, BDA}},
2732 {"bsola-",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDMA}},
2733 {"bsola+",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDPA}},
2734 {"bsola",    BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  COM,      {CR, BDA}},
2735 {"bunla-",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDMA}},
2736 {"bunla+",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDPA}},
2737 {"bunla",    BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   {CR, BDA}},
2738
2739 {"bdnzf-",   BBO(16,BODNZF,0,0),        BBOY_MASK,     NOPOWER4, {BI, BDM}},
2740 {"bdnzf+",   BBO(16,BODNZF,0,0),        BBOY_MASK,     NOPOWER4, {BI, BDP}},
2741 {"bdnzf",    BBO(16,BODNZF,0,0),        BBOY_MASK,     PPCCOM,   {BI, BD}},
2742 {"bdnzfl-",  BBO(16,BODNZF,0,1),        BBOY_MASK,     NOPOWER4, {BI, BDM}},
2743 {"bdnzfl+",  BBO(16,BODNZF,0,1),        BBOY_MASK,     NOPOWER4, {BI, BDP}},
2744 {"bdnzfl",   BBO(16,BODNZF,0,1),        BBOY_MASK,     PPCCOM,   {BI, BD}},
2745 {"bdnzfa-",  BBO(16,BODNZF,1,0),        BBOY_MASK,     NOPOWER4, {BI, BDMA}},
2746 {"bdnzfa+",  BBO(16,BODNZF,1,0),        BBOY_MASK,     NOPOWER4, {BI, BDPA}},
2747 {"bdnzfa",   BBO(16,BODNZF,1,0),        BBOY_MASK,     PPCCOM,   {BI, BDA}},
2748 {"bdnzfla-", BBO(16,BODNZF,1,1),        BBOY_MASK,     NOPOWER4, {BI, BDMA}},
2749 {"bdnzfla+", BBO(16,BODNZF,1,1),        BBOY_MASK,     NOPOWER4, {BI, BDPA}},
2750 {"bdnzfla",  BBO(16,BODNZF,1,1),        BBOY_MASK,     PPCCOM,   {BI, BDA}},
2751 {"bdzf-",    BBO(16,BODZF,0,0),         BBOY_MASK,     NOPOWER4, {BI, BDM}},
2752 {"bdzf+",    BBO(16,BODZF,0,0),         BBOY_MASK,     NOPOWER4, {BI, BDP}},
2753 {"bdzf",     BBO(16,BODZF,0,0),         BBOY_MASK,     PPCCOM,   {BI, BD}},
2754 {"bdzfl-",   BBO(16,BODZF,0,1),         BBOY_MASK,     NOPOWER4, {BI, BDM}},
2755 {"bdzfl+",   BBO(16,BODZF,0,1),         BBOY_MASK,     NOPOWER4, {BI, BDP}},
2756 {"bdzfl",    BBO(16,BODZF,0,1),         BBOY_MASK,     PPCCOM,   {BI, BD}},
2757 {"bdzfa-",   BBO(16,BODZF,1,0),         BBOY_MASK,     NOPOWER4, {BI, BDMA}},
2758 {"bdzfa+",   BBO(16,BODZF,1,0),         BBOY_MASK,     NOPOWER4, {BI, BDPA}},
2759 {"bdzfa",    BBO(16,BODZF,1,0),         BBOY_MASK,     PPCCOM,   {BI, BDA}},
2760 {"bdzfla-",  BBO(16,BODZF,1,1),         BBOY_MASK,     NOPOWER4, {BI, BDMA}},
2761 {"bdzfla+",  BBO(16,BODZF,1,1),         BBOY_MASK,     NOPOWER4, {BI, BDPA}},
2762 {"bdzfla",   BBO(16,BODZF,1,1),         BBOY_MASK,     PPCCOM,   {BI, BDA}},
2763
2764 {"bf-",      BBO(16,BOF,0,0),           BBOAT_MASK,    PPCCOM,   {BI, BDM}},
2765 {"bf+",      BBO(16,BOF,0,0),           BBOAT_MASK,    PPCCOM,   {BI, BDP}},
2766 {"bf",       BBO(16,BOF,0,0),           BBOAT_MASK,    PPCCOM,   {BI, BD}},
2767 {"bbf",      BBO(16,BOF,0,0),           BBOAT_MASK,    PWRCOM,   {BI, BD}},
2768 {"bfl-",     BBO(16,BOF,0,1),           BBOAT_MASK,    PPCCOM,   {BI, BDM}},
2769 {"bfl+",     BBO(16,BOF,0,1),           BBOAT_MASK,    PPCCOM,   {BI, BDP}},
2770 {"bfl",      BBO(16,BOF,0,1),           BBOAT_MASK,    PPCCOM,   {BI, BD}},
2771 {"bbfl",     BBO(16,BOF,0,1),           BBOAT_MASK,    PWRCOM,   {BI, BD}},
2772 {"bfa-",     BBO(16,BOF,1,0),           BBOAT_MASK,    PPCCOM,   {BI, BDMA}},
2773 {"bfa+",     BBO(16,BOF,1,0),           BBOAT_MASK,    PPCCOM,   {BI, BDPA}},
2774 {"bfa",      BBO(16,BOF,1,0),           BBOAT_MASK,    PPCCOM,   {BI, BDA}},
2775 {"bbfa",     BBO(16,BOF,1,0),           BBOAT_MASK,    PWRCOM,   {BI, BDA}},
2776 {"bfla-",    BBO(16,BOF,1,1),           BBOAT_MASK,    PPCCOM,   {BI, BDMA}},
2777 {"bfla+",    BBO(16,BOF,1,1),           BBOAT_MASK,    PPCCOM,   {BI, BDPA}},
2778 {"bfla",     BBO(16,BOF,1,1),           BBOAT_MASK,    PPCCOM,   {BI, BDA}},
2779 {"bbfla",    BBO(16,BOF,1,1),           BBOAT_MASK,    PWRCOM,   {BI, BDA}},
2780
2781 {"bdnzt-",   BBO(16,BODNZT,0,0),        BBOY_MASK,     NOPOWER4, {BI, BDM}},
2782 {"bdnzt+",   BBO(16,BODNZT,0,0),        BBOY_MASK,     NOPOWER4, {BI, BDP}},
2783 {"bdnzt",    BBO(16,BODNZT,0,0),        BBOY_MASK,     PPCCOM,   {BI, BD}},
2784 {"bdnztl-",  BBO(16,BODNZT,0,1),        BBOY_MASK,     NOPOWER4, {BI, BDM}},
2785 {"bdnztl+",  BBO(16,BODNZT,0,1),        BBOY_MASK,     NOPOWER4, {BI, BDP}},
2786 {"bdnztl",   BBO(16,BODNZT,0,1),        BBOY_MASK,     PPCCOM,   {BI, BD}},
2787 {"bdnzta-",  BBO(16,BODNZT,1,0),        BBOY_MASK,     NOPOWER4, {BI, BDMA}},
2788 {"bdnzta+",  BBO(16,BODNZT,1,0),        BBOY_MASK,     NOPOWER4, {BI, BDPA}},
2789 {"bdnzta",   BBO(16,BODNZT,1,0),        BBOY_MASK,     PPCCOM,   {BI, BDA}},
2790 {"bdnztla-", BBO(16,BODNZT,1,1),        BBOY_MASK,     NOPOWER4, {BI, BDMA}},
2791 {"bdnztla+", BBO(16,BODNZT,1,1),        BBOY_MASK,     NOPOWER4, {BI, BDPA}},
2792 {"bdnztla",  BBO(16,BODNZT,1,1),        BBOY_MASK,     PPCCOM,   {BI, BDA}},
2793 {"bdzt-",    BBO(16,BODZT,0,0),         BBOY_MASK,     NOPOWER4, {BI, BDM}},
2794 {"bdzt+",    BBO(16,BODZT,0,0),         BBOY_MASK,     NOPOWER4, {BI, BDP}},
2795 {"bdzt",     BBO(16,BODZT,0,0),         BBOY_MASK,     PPCCOM,   {BI, BD}},
2796 {"bdztl-",   BBO(16,BODZT,0,1),         BBOY_MASK,     NOPOWER4, {BI, BDM}},
2797 {"bdztl+",   BBO(16,BODZT,0,1),         BBOY_MASK,     NOPOWER4, {BI, BDP}},
2798 {"bdztl",    BBO(16,BODZT,0,1),         BBOY_MASK,     PPCCOM,   {BI, BD}},
2799 {"bdzta-",   BBO(16,BODZT,1,0),         BBOY_MASK,     NOPOWER4, {BI, BDMA}},
2800 {"bdzta+",   BBO(16,BODZT,1,0),         BBOY_MASK,     NOPOWER4, {BI, BDPA}},
2801 {"bdzta",    BBO(16,BODZT,1,0),         BBOY_MASK,     PPCCOM,   {BI, BDA}},
2802 {"bdztla-",  BBO(16,BODZT,1,1),         BBOY_MASK,     NOPOWER4, {BI, BDMA}},
2803 {"bdztla+",  BBO(16,BODZT,1,1),         BBOY_MASK,     NOPOWER4, {BI, BDPA}},
2804 {"bdztla",   BBO(16,BODZT,1,1),         BBOY_MASK,     PPCCOM,   {BI, BDA}},
2805
2806 {"bt-",      BBO(16,BOT,0,0),           BBOAT_MASK,    PPCCOM,   {BI, BDM}},
2807 {"bt+",      BBO(16,BOT,0,0),           BBOAT_MASK,    PPCCOM,   {BI, BDP}},
2808 {"bt",       BBO(16,BOT,0,0),           BBOAT_MASK,    PPCCOM,   {BI, BD}},
2809 {"bbt",      BBO(16,BOT,0,0),           BBOAT_MASK,    PWRCOM,   {BI, BD}},
2810 {"btl-",     BBO(16,BOT,0,1),           BBOAT_MASK,    PPCCOM,   {BI, BDM}},
2811 {"btl+",     BBO(16,BOT,0,1),           BBOAT_MASK,    PPCCOM,   {BI, BDP}},
2812 {"btl",      BBO(16,BOT,0,1),           BBOAT_MASK,    PPCCOM,   {BI, BD}},
2813 {"bbtl",     BBO(16,BOT,0,1),           BBOAT_MASK,    PWRCOM,   {BI, BD}},
2814 {"bta-",     BBO(16,BOT,1,0),           BBOAT_MASK,    PPCCOM,   {BI, BDMA}},
2815 {"bta+",     BBO(16,BOT,1,0),           BBOAT_MASK,    PPCCOM,   {BI, BDPA}},
2816 {"bta",      BBO(16,BOT,1,0),           BBOAT_MASK,    PPCCOM,   {BI, BDA}},
2817 {"bbta",     BBO(16,BOT,1,0),           BBOAT_MASK,    PWRCOM,   {BI, BDA}},
2818 {"btla-",    BBO(16,BOT,1,1),           BBOAT_MASK,    PPCCOM,   {BI, BDMA}},
2819 {"btla+",    BBO(16,BOT,1,1),           BBOAT_MASK,    PPCCOM,   {BI, BDPA}},
2820 {"btla",     BBO(16,BOT,1,1),           BBOAT_MASK,    PPCCOM,   {BI, BDA}},
2821 {"bbtla",    BBO(16,BOT,1,1),           BBOAT_MASK,    PWRCOM,   {BI, BDA}},
2822
2823 {"bc-",         B(16,0,0),      B_MASK,      PPCCOM,    {BOE, BI, BDM}},
2824 {"bc+",         B(16,0,0),      B_MASK,      PPCCOM,    {BOE, BI, BDP}},
2825 {"bc",          B(16,0,0),      B_MASK,      COM,       {BO, BI, BD}},
2826 {"bcl-",        B(16,0,1),      B_MASK,      PPCCOM,    {BOE, BI, BDM}},
2827 {"bcl+",        B(16,0,1),      B_MASK,      PPCCOM,    {BOE, BI, BDP}},
2828 {"bcl",         B(16,0,1),      B_MASK,      COM,       {BO, BI, BD}},
2829 {"bca-",        B(16,1,0),      B_MASK,      PPCCOM,    {BOE, BI, BDMA}},
2830 {"bca+",        B(16,1,0),      B_MASK,      PPCCOM,    {BOE, BI, BDPA}},
2831 {"bca",         B(16,1,0),      B_MASK,      COM,       {BO, BI, BDA}},
2832 {"bcla-",       B(16,1,1),      B_MASK,      PPCCOM,    {BOE, BI, BDMA}},
2833 {"bcla+",       B(16,1,1),      B_MASK,      PPCCOM,    {BOE, BI, BDPA}},
2834 {"bcla",        B(16,1,1),      B_MASK,      COM,       {BO, BI, BDA}},
2835
2836 {"svc",         SC(17,0,0),     SC_MASK,     POWER,     {SVC_LEV, FL1, FL2}},
2837 {"svcl",        SC(17,0,1),     SC_MASK,     POWER,     {SVC_LEV, FL1, FL2}},
2838 {"sc",          SC(17,1,0),     SC_MASK,     PPC,       {LEV}},
2839 {"svca",        SC(17,1,0),     SC_MASK,     PWRCOM,    {SV}},
2840 {"svcla",       SC(17,1,1),     SC_MASK,     POWER,     {SV}},
2841
2842 {"b",           B(18,0,0),      B_MASK,      COM,       {LI}},
2843 {"bl",          B(18,0,1),      B_MASK,      COM,       {LI}},
2844 {"ba",          B(18,1,0),      B_MASK,      COM,       {LIA}},
2845 {"bla",         B(18,1,1),      B_MASK,      COM,       {LIA}},
2846
2847 {"mcrf",      XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, {BF, BFA}},
2848
2849 {"bdnzlr",   XLO(19,BODNZ,16,0),        XLBOBIBB_MASK, PPCCOM,   {0}},
2850 {"bdnzlr-",  XLO(19,BODNZ,16,0),        XLBOBIBB_MASK, NOPOWER4, {0}},
2851 {"bdnzlrl",  XLO(19,BODNZ,16,1),        XLBOBIBB_MASK, PPCCOM,   {0}},
2852 {"bdnzlrl-", XLO(19,BODNZ,16,1),        XLBOBIBB_MASK, NOPOWER4, {0}},
2853 {"bdnzlr+",  XLO(19,BODNZP,16,0),       XLBOBIBB_MASK, NOPOWER4, {0}},
2854 {"bdnzlrl+", XLO(19,BODNZP,16,1),       XLBOBIBB_MASK, NOPOWER4, {0}},
2855 {"bdzlr",    XLO(19,BODZ,16,0),         XLBOBIBB_MASK, PPCCOM,   {0}},
2856 {"bdzlr-",   XLO(19,BODZ,16,0),         XLBOBIBB_MASK, NOPOWER4, {0}},
2857 {"bdzlrl",   XLO(19,BODZ,16,1),         XLBOBIBB_MASK, PPCCOM,   {0}},
2858 {"bdzlrl-",  XLO(19,BODZ,16,1),         XLBOBIBB_MASK, NOPOWER4, {0}},
2859 {"bdzlr+",   XLO(19,BODZP,16,0),        XLBOBIBB_MASK, NOPOWER4, {0}},
2860 {"bdzlrl+",  XLO(19,BODZP,16,1),        XLBOBIBB_MASK, NOPOWER4, {0}},
2861 {"blr",      XLO(19,BOU,16,0),          XLBOBIBB_MASK, PPCCOM,   {0}},
2862 {"br",       XLO(19,BOU,16,0),          XLBOBIBB_MASK, PWRCOM,   {0}},
2863 {"blrl",     XLO(19,BOU,16,1),          XLBOBIBB_MASK, PPCCOM,   {0}},
2864 {"brl",      XLO(19,BOU,16,1),          XLBOBIBB_MASK, PWRCOM,   {0}},
2865 {"bdnzlr-",  XLO(19,BODNZM4,16,0),      XLBOBIBB_MASK, POWER4,   {0}},
2866 {"bdnzlrl-", XLO(19,BODNZM4,16,1),      XLBOBIBB_MASK, POWER4,   {0}},
2867 {"bdnzlr+",  XLO(19,BODNZP4,16,0),      XLBOBIBB_MASK, POWER4,   {0}},
2868 {"bdnzlrl+", XLO(19,BODNZP4,16,1),      XLBOBIBB_MASK, POWER4,   {0}},
2869 {"bdzlr-",   XLO(19,BODZM4,16,0),       XLBOBIBB_MASK, POWER4,   {0}},
2870 {"bdzlrl-",  XLO(19,BODZM4,16,1),       XLBOBIBB_MASK, POWER4,   {0}},
2871 {"bdzlr+",   XLO(19,BODZP4,16,0),       XLBOBIBB_MASK, POWER4,   {0}},
2872 {"bdzlrl+",  XLO(19,BODZP4,16,1),       XLBOBIBB_MASK, POWER4,   {0}},
2873
2874 {"bgelr",    XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   {CR}},
2875 {"bgelr-",   XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, NOPOWER4, {CR}},
2876 {"bger",     XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PWRCOM,   {CR}},
2877 {"bnllr",    XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   {CR}},
2878 {"bnllr-",   XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, NOPOWER4, {CR}},
2879 {"bnlr",     XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PWRCOM,   {CR}},
2880 {"bgelrl",   XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   {CR}},
2881 {"bgelrl-",  XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, NOPOWER4, {CR}},
2882 {"bgerl",    XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PWRCOM,   {CR}},
2883 {"bnllrl",   XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   {CR}},
2884 {"bnllrl-",  XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, NOPOWER4, {CR}},
2885 {"bnlrl",    XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PWRCOM,   {CR}},
2886 {"blelr",    XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   {CR}},
2887 {"blelr-",   XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, NOPOWER4, {CR}},
2888 {"bler",     XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PWRCOM,   {CR}},
2889 {"bnglr",    XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   {CR}},
2890 {"bnglr-",   XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, NOPOWER4, {CR}},
2891 {"bngr",     XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PWRCOM,   {CR}},
2892 {"blelrl",   XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   {CR}},
2893 {"blelrl-",  XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, NOPOWER4, {CR}},
2894 {"blerl",    XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PWRCOM,   {CR}},
2895 {"bnglrl",   XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   {CR}},
2896 {"bnglrl-",  XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, NOPOWER4, {CR}},
2897 {"bngrl",    XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PWRCOM,   {CR}},
2898 {"bnelr",    XLOCB(19,BOF,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   {CR}},
2899 {"bnelr-",   XLOCB(19,BOF,CBEQ,16,0),   XLBOCBBB_MASK, NOPOWER4, {CR}},
2900 {"bner",     XLOCB(19,BOF,CBEQ,16,0),   XLBOCBBB_MASK, PWRCOM,   {CR}},
2901 {"bnelrl",   XLOCB(19,BOF,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   {CR}},
2902 {"bnelrl-",  XLOCB(19,BOF,CBEQ,16,1),   XLBOCBBB_MASK, NOPOWER4, {CR}},
2903 {"bnerl",    XLOCB(19,BOF,CBEQ,16,1),   XLBOCBBB_MASK, PWRCOM,   {CR}},
2904 {"bnslr",    XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   {CR}},
2905 {"bnslr-",   XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, NOPOWER4, {CR}},
2906 {"bnsr",     XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PWRCOM,   {CR}},
2907 {"bnulr",    XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   {CR}},
2908 {"bnulr-",   XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, NOPOWER4, {CR}},
2909 {"bnslrl",   XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   {CR}},
2910 {"bnslrl-",  XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, NOPOWER4, {CR}},
2911 {"bnsrl",    XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PWRCOM,   {CR}},
2912 {"bnulrl",   XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   {CR}},
2913 {"bnulrl-",  XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, NOPOWER4, {CR}},
2914 {"bgelr+",   XLOCB(19,BOFP,CBLT,16,0),  XLBOCBBB_MASK, NOPOWER4, {CR}},
2915 {"bnllr+",   XLOCB(19,BOFP,CBLT,16,0),  XLBOCBBB_MASK, NOPOWER4, {CR}},
2916 {"bgelrl+",  XLOCB(19,BOFP,CBLT,16,1),  XLBOCBBB_MASK, NOPOWER4, {CR}},
2917 {"bnllrl+",  XLOCB(19,BOFP,CBLT,16,1),  XLBOCBBB_MASK, NOPOWER4, {CR}},
2918 {"blelr+",   XLOCB(19,BOFP,CBGT,16,0),  XLBOCBBB_MASK, NOPOWER4, {CR}},
2919 {"bnglr+",   XLOCB(19,BOFP,CBGT,16,0),  XLBOCBBB_MASK, NOPOWER4, {CR}},
2920 {"blelrl+",  XLOCB(19,BOFP,CBGT,16,1),  XLBOCBBB_MASK, NOPOWER4, {CR}},
2921 {"bnglrl+",  XLOCB(19,BOFP,CBGT,16,1),  XLBOCBBB_MASK, NOPOWER4, {CR}},
2922 {"bnelr+",   XLOCB(19,BOFP,CBEQ,16,0),  XLBOCBBB_MASK, NOPOWER4, {CR}},
2923 {"bnelrl+",  XLOCB(19,BOFP,CBEQ,16,1),  XLBOCBBB_MASK, NOPOWER4, {CR}},
2924 {"bnslr+",   XLOCB(19,BOFP,CBSO,16,0),  XLBOCBBB_MASK, NOPOWER4, {CR}},
2925 {"bnulr+",   XLOCB(19,BOFP,CBSO,16,0),  XLBOCBBB_MASK, NOPOWER4, {CR}},
2926 {"bnslrl+",  XLOCB(19,BOFP,CBSO,16,1),  XLBOCBBB_MASK, NOPOWER4, {CR}},
2927 {"bnulrl+",  XLOCB(19,BOFP,CBSO,16,1),  XLBOCBBB_MASK, NOPOWER4, {CR}},
2928 {"bgelr-",   XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4,   {CR}},
2929 {"bnllr-",   XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4,   {CR}},
2930 {"bgelrl-",  XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   {CR}},
2931 {"bnllrl-",  XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   {CR}},
2932 {"blelr-",   XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4,   {CR}},
2933 {"bnglr-",   XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4,   {CR}},
2934 {"blelrl-",  XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   {CR}},
2935 {"bnglrl-",  XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   {CR}},
2936 {"bnelr-",   XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4,   {CR}},
2937 {"bnelrl-",  XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4,   {CR}},
2938 {"bnslr-",   XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   {CR}},
2939 {"bnulr-",   XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   {CR}},
2940 {"bnslrl-",  XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   {CR}},
2941 {"bnulrl-",  XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   {CR}},
2942 {"bgelr+",   XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4,   {CR}},
2943 {"bnllr+",   XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4,   {CR}},
2944 {"bgelrl+",  XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   {CR}},
2945 {"bnllrl+",  XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   {CR}},
2946 {"blelr+",   XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4,   {CR}},
2947 {"bnglr+",   XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4,   {CR}},
2948 {"blelrl+",  XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   {CR}},
2949 {"bnglrl+",  XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   {CR}},
2950 {"bnelr+",   XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4,   {CR}},
2951 {"bnelrl+",  XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4,   {CR}},
2952 {"bnslr+",   XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   {CR}},
2953 {"bnulr+",   XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   {CR}},
2954 {"bnslrl+",  XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   {CR}},
2955 {"bnulrl+",  XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   {CR}},
2956 {"bltlr",    XLOCB(19,BOT,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   {CR}},
2957 {"bltlr-",   XLOCB(19,BOT,CBLT,16,0),   XLBOCBBB_MASK, NOPOWER4, {CR}},
2958 {"bltr",     XLOCB(19,BOT,CBLT,16,0),   XLBOCBBB_MASK, PWRCOM,   {CR}},
2959 {"bltlrl",   XLOCB(19,BOT,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   {CR}},
2960 {"bltlrl-",  XLOCB(19,BOT,CBLT,16,1),   XLBOCBBB_MASK, NOPOWER4, {CR}},
2961 {"bltrl",    XLOCB(19,BOT,CBLT,16,1),   XLBOCBBB_MASK, PWRCOM,   {CR}},
2962 {"bgtlr",    XLOCB(19,BOT,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   {CR}},
2963 {"bgtlr-",   XLOCB(19,BOT,CBGT,16,0),   XLBOCBBB_MASK, NOPOWER4, {CR}},
2964 {"bgtr",     XLOCB(19,BOT,CBGT,16,0),   XLBOCBBB_MASK, PWRCOM,   {CR}},
2965 {"bgtlrl",   XLOCB(19,BOT,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   {CR}},
2966 {"bgtlrl-",  XLOCB(19,BOT,CBGT,16,1),   XLBOCBBB_MASK, NOPOWER4, {CR}},
2967 {"bgtrl",    XLOCB(19,BOT,CBGT,16,1),   XLBOCBBB_MASK, PWRCOM,   {CR}},
2968 {"beqlr",    XLOCB(19,BOT,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   {CR}},
2969 {"beqlr-",   XLOCB(19,BOT,CBEQ,16,0),   XLBOCBBB_MASK, NOPOWER4, {CR}},
2970 {"beqr",     XLOCB(19,BOT,CBEQ,16,0),   XLBOCBBB_MASK, PWRCOM,   {CR}},
2971 {"beqlrl",   XLOCB(19,BOT,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   {CR}},
2972 {"beqlrl-",  XLOCB(19,BOT,CBEQ,16,1),   XLBOCBBB_MASK, NOPOWER4, {CR}},
2973 {"beqrl",    XLOCB(19,BOT,CBEQ,16,1),   XLBOCBBB_MASK, PWRCOM,   {CR}},
2974 {"bsolr",    XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   {CR}},
2975 {"bsolr-",   XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, NOPOWER4, {CR}},
2976 {"bsor",     XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PWRCOM,   {CR}},
2977 {"bunlr",    XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   {CR}},
2978 {"bunlr-",   XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, NOPOWER4, {CR}},
2979 {"bsolrl",   XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   {CR}},
2980 {"bsolrl-",  XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, NOPOWER4, {CR}},
2981 {"bsorl",    XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PWRCOM,   {CR}},
2982 {"bunlrl",   XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   {CR}},
2983 {"bunlrl-",  XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, NOPOWER4, {CR}},
2984 {"bltlr+",   XLOCB(19,BOTP,CBLT,16,0),  XLBOCBBB_MASK, NOPOWER4, {CR}},
2985 {"bltlrl+",  XLOCB(19,BOTP,CBLT,16,1),  XLBOCBBB_MASK, NOPOWER4, {CR}},
2986 {"bgtlr+",   XLOCB(19,BOTP,CBGT,16,0),  XLBOCBBB_MASK, NOPOWER4, {CR}},
2987 {"bgtlrl+",  XLOCB(19,BOTP,CBGT,16,1),  XLBOCBBB_MASK, NOPOWER4, {CR}},
2988 {"beqlr+",   XLOCB(19,BOTP,CBEQ,16,0),  XLBOCBBB_MASK, NOPOWER4, {CR}},
2989 {"beqlrl+",  XLOCB(19,BOTP,CBEQ,16,1),  XLBOCBBB_MASK, NOPOWER4, {CR}},
2990 {"bsolr+",   XLOCB(19,BOTP,CBSO,16,0),  XLBOCBBB_MASK, NOPOWER4, {CR}},
2991 {"bunlr+",   XLOCB(19,BOTP,CBSO,16,0),  XLBOCBBB_MASK, NOPOWER4, {CR}},
2992 {"bsolrl+",  XLOCB(19,BOTP,CBSO,16,1),  XLBOCBBB_MASK, NOPOWER4, {CR}},
2993 {"bunlrl+",  XLOCB(19,BOTP,CBSO,16,1),  XLBOCBBB_MASK, NOPOWER4, {CR}},
2994 {"bltlr-",   XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4,   {CR}},
2995 {"bltlrl-",  XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   {CR}},
2996 {"bgtlr-",   XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4,   {CR}},
2997 {"bgtlrl-",  XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   {CR}},
2998 {"beqlr-",   XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4,   {CR}},
2999 {"beqlrl-",  XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4,   {CR}},
3000 {"bsolr-",   XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   {CR}},
3001 {"bunlr-",   XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   {CR}},
3002 {"bsolrl-",  XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   {CR}},
3003 {"bunlrl-",  XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   {CR}},
3004 {"bltlr+",   XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4,   {CR}},
3005 {"bltlrl+",  XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   {CR}},
3006 {"bgtlr+",   XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4,   {CR}},
3007 {"bgtlrl+",  XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   {CR}},
3008 {"beqlr+",   XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4,   {CR}},
3009 {"beqlrl+",  XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4,   {CR}},
3010 {"bsolr+",   XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   {CR}},
3011 {"bunlr+",   XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   {CR}},
3012 {"bsolrl+",  XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   {CR}},
3013 {"bunlrl+",  XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   {CR}},
3014
3015 {"bdnzflr",  XLO(19,BODNZF,16,0),       XLBOBB_MASK,   PPCCOM,   {BI}},
3016 {"bdnzflr-", XLO(19,BODNZF,16,0),       XLBOBB_MASK,   NOPOWER4, {BI}},
3017 {"bdnzflrl", XLO(19,BODNZF,16,1),       XLBOBB_MASK,   PPCCOM,   {BI}},
3018 {"bdnzflrl-",XLO(19,BODNZF,16,1),       XLBOBB_MASK,   NOPOWER4, {BI}},
3019 {"bdnzflr+", XLO(19,BODNZFP,16,0),      XLBOBB_MASK,   NOPOWER4, {BI}},
3020 {"bdnzflrl+",XLO(19,BODNZFP,16,1),      XLBOBB_MASK,   NOPOWER4, {BI}},
3021 {"bdzflr",   XLO(19,BODZF,16,0),        XLBOBB_MASK,   PPCCOM,   {BI}},
3022 {"bdzflr-",  XLO(19,BODZF,16,0),        XLBOBB_MASK,   NOPOWER4, {BI}},
3023 {"bdzflrl",  XLO(19,BODZF,16,1),        XLBOBB_MASK,   PPCCOM,   {BI}},
3024 {"bdzflrl-", XLO(19,BODZF,16,1),        XLBOBB_MASK,   NOPOWER4, {BI}},
3025 {"bdzflr+",  XLO(19,BODZFP,16,0),       XLBOBB_MASK,   NOPOWER4, {BI}},
3026 {"bdzflrl+", XLO(19,BODZFP,16,1),       XLBOBB_MASK,   NOPOWER4, {BI}},
3027 {"bflr",     XLO(19,BOF,16,0),          XLBOBB_MASK,   PPCCOM,   {BI}},
3028 {"bflr-",    XLO(19,BOF,16,0),          XLBOBB_MASK,   NOPOWER4, {BI}},
3029 {"bbfr",     XLO(19,BOF,16,0),          XLBOBB_MASK,   PWRCOM,   {BI}},
3030 {"bflrl",    XLO(19,BOF,16,1),          XLBOBB_MASK,   PPCCOM,   {BI}},
3031 {"bflrl-",   XLO(19,BOF,16,1),          XLBOBB_MASK,   NOPOWER4, {BI}},
3032 {"bbfrl",    XLO(19,BOF,16,1),          XLBOBB_MASK,   PWRCOM,   {BI}},
3033 {"bflr+",    XLO(19,BOFP,16,0),         XLBOBB_MASK,   NOPOWER4, {BI}},
3034 {"bflrl+",   XLO(19,BOFP,16,1),         XLBOBB_MASK,   NOPOWER4, {BI}},
3035 {"bflr-",    XLO(19,BOFM4,16,0),        XLBOBB_MASK,   POWER4,   {BI}},
3036 {"bflrl-",   XLO(19,BOFM4,16,1),        XLBOBB_MASK,   POWER4,   {BI}},
3037 {"bflr+",    XLO(19,BOFP4,16,0),        XLBOBB_MASK,   POWER4,   {BI}},
3038 {"bflrl+",   XLO(19,BOFP4,16,1),        XLBOBB_MASK,   POWER4,   {BI}},
3039 {"bdnztlr",  XLO(19,BODNZT,16,0),       XLBOBB_MASK,   PPCCOM,   {BI}},
3040 {"bdnztlr-", XLO(19,BODNZT,16,0),       XLBOBB_MASK,   NOPOWER4, {BI}},
3041 {"bdnztlrl", XLO(19,BODNZT,16,1),       XLBOBB_MASK,   PPCCOM,   {BI}},
3042 {"bdnztlrl-",XLO(19,BODNZT,16,1),       XLBOBB_MASK,   NOPOWER4, {BI}},
3043 {"bdnztlr+", XLO(19,BODNZTP,16,0),      XLBOBB_MASK,   NOPOWER4, {BI}},
3044 {"bdnztlrl+",XLO(19,BODNZTP,16,1),      XLBOBB_MASK,   NOPOWER4, {BI}},
3045 {"bdztlr",   XLO(19,BODZT,16,0),        XLBOBB_MASK,   PPCCOM,   {BI}},
3046 {"bdztlr-",  XLO(19,BODZT,16,0),        XLBOBB_MASK,   NOPOWER4, {BI}},
3047 {"bdztlrl",  XLO(19,BODZT,16,1),        XLBOBB_MASK,   PPCCOM,   {BI}},
3048 {"bdztlrl-", XLO(19,BODZT,16,1),        XLBOBB_MASK,   NOPOWER4, {BI}},
3049 {"bdztlr+",  XLO(19,BODZTP,16,0),       XLBOBB_MASK,   NOPOWER4, {BI}},
3050 {"bdztlrl+", XLO(19,BODZTP,16,1),       XLBOBB_MASK,   NOPOWER4, {BI}},
3051 {"btlr",     XLO(19,BOT,16,0),          XLBOBB_MASK,   PPCCOM,   {BI}},
3052 {"btlr-",    XLO(19,BOT,16,0),          XLBOBB_MASK,   NOPOWER4, {BI}},
3053 {"bbtr",     XLO(19,BOT,16,0),          XLBOBB_MASK,   PWRCOM,   {BI}},
3054 {"btlrl",    XLO(19,BOT,16,1),          XLBOBB_MASK,   PPCCOM,   {BI}},
3055 {"btlrl-",   XLO(19,BOT,16,1),          XLBOBB_MASK,   NOPOWER4, {BI}},
3056 {"bbtrl",    XLO(19,BOT,16,1),          XLBOBB_MASK,   PWRCOM,   {BI}},
3057 {"btlr+",    XLO(19,BOTP,16,0),         XLBOBB_MASK,   NOPOWER4, {BI}},
3058 {"btlrl+",   XLO(19,BOTP,16,1),         XLBOBB_MASK,   NOPOWER4, {BI}},
3059 {"btlr-",    XLO(19,BOTM4,16,0),        XLBOBB_MASK,   POWER4,   {BI}},
3060 {"btlrl-",   XLO(19,BOTM4,16,1),        XLBOBB_MASK,   POWER4,   {BI}},
3061 {"btlr+",    XLO(19,BOTP4,16,0),        XLBOBB_MASK,   POWER4,   {BI}},
3062 {"btlrl+",   XLO(19,BOTP4,16,1),        XLBOBB_MASK,   POWER4,   {BI}},
3063
3064 {"bclr-",    XLYLK(19,16,0,0),          XLYBB_MASK,    PPCCOM,   {BOE, BI}},
3065 {"bclrl-",   XLYLK(19,16,0,1),          XLYBB_MASK,    PPCCOM,   {BOE, BI}},
3066 {"bclr+",    XLYLK(19,16,1,0),          XLYBB_MASK,    PPCCOM,   {BOE, BI}},
3067 {"bclrl+",   XLYLK(19,16,1,1),          XLYBB_MASK,    PPCCOM,   {BOE, BI}},
3068 {"bclr",     XLLK(19,16,0),             XLBH_MASK,     PPCCOM,   {BO, BI, BH}},
3069 {"bcr",      XLLK(19,16,0),             XLBB_MASK,     PWRCOM,   {BO, BI}},
3070 {"bclrl",    XLLK(19,16,1),             XLBH_MASK,     PPCCOM,   {BO, BI, BH}},
3071 {"bcrl",     XLLK(19,16,1),             XLBB_MASK,     PWRCOM,   {BO, BI}},
3072
3073 {"bclre",    XLLK(19,17,0),             XLBB_MASK,     BOOKE64,  {BO, BI}},
3074 {"bclrel",   XLLK(19,17,1),             XLBB_MASK,     BOOKE64,  {BO, BI}},
3075
3076 {"rfid",        XL(19,18),      0xffffffff,  PPC64,     {0}},
3077
3078 {"crnot",       XL(19,33),      XL_MASK,     PPCCOM,    {BT, BA, BBA}},
3079 {"crnor",       XL(19,33),      XL_MASK,     COM,       {BT, BA, BB}},
3080 {"rfmci",       X(19,38),       0xffffffff,  PPCRFMCI,  {0}},
3081
3082 {"rfdi",        XL(19,39),      0xffffffff,  E500MC,    {0}},
3083 {"rfi",         XL(19,50),      0xffffffff,  COM,       {0}},
3084 {"rfci",        XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300, {0}},
3085
3086 {"rfsvc",       XL(19,82),      0xffffffff,  POWER,     {0}},
3087
3088 {"rfgi",        XL(19,102),     0xffffffff,  E500MC,    {0}},
3089
3090 {"crandc",      XL(19,129),     XL_MASK,     COM,       {BT, BA, BB}},
3091
3092 {"isync",       XL(19,150),     0xffffffff,  PPCCOM,    {0}},
3093 {"ics",         XL(19,150),     0xffffffff,  PWRCOM,    {0}},
3094
3095 {"crclr",       XL(19,193),     XL_MASK,     PPCCOM,    {BT, BAT, BBA}},
3096 {"crxor",       XL(19,193),     XL_MASK,     COM,       {BT, BA, BB}},
3097
3098 {"dnh",         X(19,198),      X_MASK,      E500MC,    {DUI, DUIS}},
3099
3100 {"crnand",      XL(19,225),     XL_MASK,     COM,       {BT, BA, BB}},
3101
3102 {"crand",       XL(19,257),     XL_MASK,     COM,       {BT, BA, BB}},
3103
3104 {"hrfid",       XL(19,274),     0xffffffff, POWER5|CELL, {0}},
3105
3106 {"crset",       XL(19,289),     XL_MASK,     PPCCOM,    {BT, BAT, BBA}},
3107 {"creqv",       XL(19,289),     XL_MASK,     COM,       {BT, BA, BB}},
3108
3109 {"doze",        XL(19,402),     0xffffffff,  POWER6,    {0}},
3110
3111 {"crorc",       XL(19,417),     XL_MASK,     COM,       {BT, BA, BB}},
3112
3113 {"nap",         XL(19,434),     0xffffffff,  POWER6,    {0}},
3114
3115 {"crmove",      XL(19,449),     XL_MASK,     PPCCOM,    {BT, BA, BBA}},
3116 {"cror",        XL(19,449),     XL_MASK,     COM,       {BT, BA, BB}},
3117
3118 {"sleep",       XL(19,466),     0xffffffff,  POWER6,    {0}},
3119 {"rvwinkle",    XL(19,498),     0xffffffff,  POWER6,    {0}},
3120
3121 {"bctr",    XLO(19,BOU,528,0),          XLBOBIBB_MASK, COM,      {0}},
3122 {"bctrl",   XLO(19,BOU,528,1),          XLBOBIBB_MASK, COM,      {0}},
3123
3124 {"bgectr",  XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   {CR}},
3125 {"bgectr-", XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, NOPOWER4, {CR}},
3126 {"bnlctr",  XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   {CR}},
3127 {"bnlctr-", XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, NOPOWER4, {CR}},
3128 {"bgectrl", XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   {CR}},
3129 {"bgectrl-",XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, NOPOWER4, {CR}},
3130 {"bnlctrl", XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   {CR}},
3131 {"bnlctrl-",XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, NOPOWER4, {CR}},
3132 {"blectr",  XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   {CR}},
3133 {"blectr-", XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, NOPOWER4, {CR}},
3134 {"bngctr",  XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   {CR}},
3135 {"bngctr-", XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, NOPOWER4, {CR}},
3136 {"blectrl", XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   {CR}},
3137 {"blectrl-",XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, NOPOWER4, {CR}},
3138 {"bngctrl", XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   {CR}},
3139 {"bngctrl-",XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, NOPOWER4, {CR}},
3140 {"bnectr",  XLOCB(19,BOF,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   {CR}},
3141 {"bnectr-", XLOCB(19,BOF,CBEQ,528,0),   XLBOCBBB_MASK, NOPOWER4, {CR}},
3142 {"bnectrl", XLOCB(19,BOF,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   {CR}},
3143 {"bnectrl-",XLOCB(19,BOF,CBEQ,528,1),   XLBOCBBB_MASK, NOPOWER4, {CR}},
3144 {"bnsctr",  XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   {CR}},
3145 {"bnsctr-", XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, NOPOWER4, {CR}},
3146 {"bnuctr",  XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   {CR}},
3147 {"bnuctr-", XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, NOPOWER4, {CR}},
3148 {"bnsctrl", XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   {CR}},
3149 {"bnsctrl-",XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, NOPOWER4, {CR}},
3150 {"bnuctrl", XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   {CR}},
3151 {"bnuctrl-",XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, NOPOWER4, {CR}},
3152 {"bgectr+", XLOCB(19,BOFP,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, {CR}},
3153 {"bnlctr+", XLOCB(19,BOFP,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, {CR}},
3154 {"bgectrl+",XLOCB(19,BOFP,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, {CR}},
3155 {"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, {CR}},
3156 {"blectr+", XLOCB(19,BOFP,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, {CR}},
3157 {"bngctr+", XLOCB(19,BOFP,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, {CR}},
3158 {"blectrl+",XLOCB(19,BOFP,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, {CR}},
3159 {"bngctrl+",XLOCB(19,BOFP,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, {CR}},
3160 {"bnectr+", XLOCB(19,BOFP,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, {CR}},
3161 {"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, {CR}},
3162 {"bnsctr+", XLOCB(19,BOFP,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, {CR}},
3163 {"bnuctr+", XLOCB(19,BOFP,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, {CR}},
3164 {"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, {CR}},
3165 {"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, {CR}},
3166 {"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4,   {CR}},
3167 {"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4,   {CR}},
3168 {"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   {CR}},
3169 {"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   {CR}},
3170 {"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4,   {CR}},
3171 {"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4,   {CR}},
3172 {"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   {CR}},
3173 {"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   {CR}},
3174 {"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4,   {CR}},
3175 {"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4,   {CR}},
3176 {"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   {CR}},
3177 {"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   {CR}},
3178 {"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   {CR}},
3179 {"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   {CR}},
3180 {"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4,   {CR}},
3181 {"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4,   {CR}},
3182 {"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   {CR}},
3183 {"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   {CR}},
3184 {"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4,   {CR}},
3185 {"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4,   {CR}},
3186 {"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   {CR}},
3187 {"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   {CR}},
3188 {"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4,   {CR}},
3189 {"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4,   {CR}},
3190 {"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   {CR}},
3191 {"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   {CR}},
3192 {"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   {CR}},
3193 {"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   {CR}},
3194 {"bltctr",  XLOCB(19,BOT,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   {CR}},
3195 {"bltctr-", XLOCB(19,BOT,CBLT,528,0),   XLBOCBBB_MASK, NOPOWER4, {CR}},
3196 {"bltctrl", XLOCB(19,BOT,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   {CR}},
3197 {"bltctrl-",XLOCB(19,BOT,CBLT,528,1),   XLBOCBBB_MASK, NOPOWER4, {CR}},
3198 {"bgtctr",  XLOCB(19,BOT,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   {CR}},
3199 {"bgtctr-", XLOCB(19,BOT,CBGT,528,0),   XLBOCBBB_MASK, NOPOWER4, {CR}},
3200 {"bgtctrl", XLOCB(19,BOT,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   {CR}},
3201 {"bgtctrl-",XLOCB(19,BOT,CBGT,528,1),   XLBOCBBB_MASK, NOPOWER4, {CR}},
3202 {"beqctr",  XLOCB(19,BOT,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   {CR}},
3203 {"beqctr-", XLOCB(19,BOT,CBEQ,528,0),   XLBOCBBB_MASK, NOPOWER4, {CR}},
3204 {"beqctrl", XLOCB(19,BOT,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   {CR}},
3205 {"beqctrl-",XLOCB(19,BOT,CBEQ,528,1),   XLBOCBBB_MASK, NOPOWER4, {CR}},
3206 {"bsoctr",  XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   {CR}},
3207 {"bsoctr-", XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, NOPOWER4, {CR}},
3208 {"bunctr",  XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   {CR}},
3209 {"bunctr-", XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, NOPOWER4, {CR}},
3210 {"bsoctrl", XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   {CR}},
3211 {"bsoctrl-",XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, NOPOWER4, {CR}},
3212 {"bunctrl", XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   {CR}},
3213 {"bunctrl-",XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, NOPOWER4, {CR}},
3214 {"bltctr+", XLOCB(19,BOTP,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, {CR}},
3215 {"bltctrl+",XLOCB(19,BOTP,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, {CR}},
3216 {"bgtctr+", XLOCB(19,BOTP,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, {CR}},
3217 {"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, {CR}},
3218 {"beqctr+", XLOCB(19,BOTP,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, {CR}},
3219 {"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, {CR}},
3220 {"bsoctr+", XLOCB(19,BOTP,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, {CR}},
3221 {"bunctr+", XLOCB(19,BOTP,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, {CR}},
3222 {"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, {CR}},
3223 {"bunctrl+",XLOCB(19,BOTP,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, {CR}},
3224 {"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4,   {CR}},
3225 {"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   {CR}},
3226 {"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4,   {CR}},
3227 {"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   {CR}},
3228 {"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4,   {CR}},
3229 {"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4,   {CR}},
3230 {"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   {CR}},
3231 {"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   {CR}},
3232 {"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   {CR}},
3233 {"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   {CR}},
3234 {"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4,   {CR}},
3235 {"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   {CR}},
3236 {"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4,   {CR}},
3237 {"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   {CR}},
3238 {"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4,   {CR}},
3239 {"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4,   {CR}},
3240 {"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   {CR}},
3241 {"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   {CR}},
3242 {"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   {CR}},
3243 {"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   {CR}},
3244
3245 {"bfctr",   XLO(19,BOF,528,0),          XLBOBB_MASK,   PPCCOM,   {BI}},
3246 {"bfctr-",  XLO(19,BOF,528,0),          XLBOBB_MASK,   NOPOWER4, {BI}},
3247 {"bfctrl",  XLO(19,BOF,528,1),          XLBOBB_MASK,   PPCCOM,   {BI}},
3248 {"bfctrl-", XLO(19,BOF,528,1),          XLBOBB_MASK,   NOPOWER4, {BI}},
3249 {"bfctr+",  XLO(19,BOFP,528,0),         XLBOBB_MASK,   NOPOWER4, {BI}},
3250 {"bfctrl+", XLO(19,BOFP,528,1),         XLBOBB_MASK,   NOPOWER4, {BI}},
3251 {"bfctr-",  XLO(19,BOFM4,528,0),        XLBOBB_MASK,   POWER4,   {BI}},
3252 {"bfctrl-", XLO(19,BOFM4,528,1),        XLBOBB_MASK,   POWER4,   {BI}},
3253 {"bfctr+",  XLO(19,BOFP4,528,0),        XLBOBB_MASK,   POWER4,   {BI}},
3254 {"bfctrl+", XLO(19,BOFP4,528,1),        XLBOBB_MASK,   POWER4,   {BI}},
3255 {"btctr",   XLO(19,BOT,528,0),          XLBOBB_MASK,   PPCCOM,   {BI}},
3256 {"btctr-",  XLO(19,BOT,528,0),          XLBOBB_MASK,   NOPOWER4, {BI}},
3257 {"btctrl",  XLO(19,BOT,528,1),          XLBOBB_MASK,   PPCCOM,   {BI}},
3258 {"btctrl-", XLO(19,BOT,528,1),          XLBOBB_MASK,   NOPOWER4, {BI}},
3259 {"btctr+",  XLO(19,BOTP,528,0),         XLBOBB_MASK,   NOPOWER4, {BI}},
3260 {"btctrl+", XLO(19,BOTP,528,1),         XLBOBB_MASK,   NOPOWER4, {BI}},
3261 {"btctr-",  XLO(19,BOTM4,528,0),        XLBOBB_MASK,   POWER4,   {BI}},
3262 {"btctrl-", XLO(19,BOTM4,528,1),        XLBOBB_MASK,   POWER4,   {BI}},
3263 {"btctr+",  XLO(19,BOTP4,528,0),        XLBOBB_MASK,   POWER4,   {BI}},
3264 {"btctrl+", XLO(19,BOTP4,528,1),        XLBOBB_MASK,   POWER4,   {BI}},
3265
3266 {"bcctr-",  XLYLK(19,528,0,0),          XLYBB_MASK,    PPCCOM,   {BOE, BI}},
3267 {"bcctrl-", XLYLK(19,528,0,1),          XLYBB_MASK,    PPCCOM,   {BOE, BI}},
3268 {"bcctr+",  XLYLK(19,528,1,0),          XLYBB_MASK,    PPCCOM,   {BOE, BI}},
3269 {"bcctrl+", XLYLK(19,528,1,1),          XLYBB_MASK,    PPCCOM,   {BOE, BI}},
3270 {"bcctr",   XLLK(19,528,0),             XLBH_MASK,     PPCCOM,   {BO, BI, BH}},
3271 {"bcc",     XLLK(19,528,0),             XLBB_MASK,     PWRCOM,   {BO, BI}},
3272 {"bcctrl",  XLLK(19,528,1),             XLBH_MASK,     PPCCOM,   {BO, BI, BH}},
3273 {"bccl",    XLLK(19,528,1),             XLBB_MASK,     PWRCOM,   {BO, BI}},
3274
3275 {"bcctre",  XLLK(19,529,0),             XLBB_MASK,     BOOKE64,  {BO, BI}},
3276 {"bcctrel", XLLK(19,529,1),             XLBB_MASK,     BOOKE64,  {BO, BI}},
3277
3278 {"rlwimi",      M(20,0),        M_MASK,      PPCCOM,    {RA, RS, SH, MBE, ME}},
3279 {"rlimi",       M(20,0),        M_MASK,      PWRCOM,    {RA, RS, SH, MBE, ME}},
3280
3281 {"rlwimi.",     M(20,1),        M_MASK,      PPCCOM,    {RA, RS, SH, MBE, ME}},
3282 {"rlimi.",      M(20,1),        M_MASK,      PWRCOM,    {RA, RS, SH, MBE, ME}},
3283
3284 {"rotlwi",      MME(21,31,0),   MMBME_MASK,  PPCCOM,    {RA, RS, SH}},
3285 {"clrlwi",      MME(21,31,0),   MSHME_MASK,  PPCCOM,    {RA, RS, MB}},
3286 {"rlwinm",      M(21,0),        M_MASK,      PPCCOM,    {RA, RS, SH, MBE, ME}},
3287 {"rlinm",       M(21,0),        M_MASK,      PWRCOM,    {RA, RS, SH, MBE, ME}},
3288 {"rotlwi.",     MME(21,31,1),   MMBME_MASK,  PPCCOM,    {RA, RS, SH}},
3289 {"clrlwi.",     MME(21,31,1),   MSHME_MASK,  PPCCOM,    {RA, RS, MB}},
3290 {"rlwinm.",     M(21,1),        M_MASK,      PPCCOM,    {RA, RS, SH, MBE, ME}},
3291 {"rlinm.",      M(21,1),        M_MASK,      PWRCOM,    {RA, RS, SH, MBE, ME}},
3292
3293 {"rlmi",        M(22,0),        M_MASK,      M601,      {RA, RS, RB, MBE, ME}},
3294 {"be",          B(22,0,0),      B_MASK,      BOOKE64,   {LI}},
3295 {"bel",         B(22,0,1),      B_MASK,      BOOKE64,   {LI}},
3296 {"rlmi.",       M(22,1),        M_MASK,      M601,      {RA, RS, RB, MBE, ME}},
3297 {"bea",         B(22,1,0),      B_MASK,      BOOKE64,   {LIA}},
3298 {"bela",        B(22,1,1),      B_MASK,      BOOKE64,   {LIA}},
3299
3300 {"rotlw",       MME(23,31,0),   MMBME_MASK,  PPCCOM,    {RA, RS, RB}},
3301 {"rlwnm",       M(23,0),        M_MASK,      PPCCOM,    {RA, RS, RB, MBE, ME}},
3302 {"rlnm",        M(23,0),        M_MASK,      PWRCOM,    {RA, RS, RB, MBE, ME}},
3303 {"rotlw.",      MME(23,31,1),   MMBME_MASK,  PPCCOM,    {RA, RS, RB}},
3304 {"rlwnm.",      M(23,1),        M_MASK,      PPCCOM,    {RA, RS, RB, MBE, ME}},
3305 {"rlnm.",       M(23,1),        M_MASK,      PWRCOM,    {RA, RS, RB, MBE, ME}},
3306
3307 {"nop",         OP(24),         0xffffffff,  PPCCOM,    {0}},
3308 {"ori",         OP(24),         OP_MASK,     PPCCOM,    {RA, RS, UI}},
3309 {"oril",        OP(24),         OP_MASK,     PWRCOM,    {RA, RS, UI}},
3310
3311 {"oris",        OP(25),         OP_MASK,     PPCCOM,    {RA, RS, UI}},
3312 {"oriu",        OP(25),         OP_MASK,     PWRCOM,    {RA, RS, UI}},
3313
3314 {"xori",        OP(26),         OP_MASK,     PPCCOM,    {RA, RS, UI}},
3315 {"xoril",       OP(26),         OP_MASK,     PWRCOM,    {RA, RS, UI}},
3316
3317 {"xoris",       OP(27),         OP_MASK,     PPCCOM,    {RA, RS, UI}},
3318 {"xoriu",       OP(27),         OP_MASK,     PWRCOM,    {RA, RS, UI}},
3319
3320 {"andi.",       OP(28),         OP_MASK,     PPCCOM,    {RA, RS, UI}},
3321 {"andil.",      OP(28),         OP_MASK,     PWRCOM,    {RA, RS, UI}},
3322
3323 {"andis.",      OP(29),         OP_MASK,     PPCCOM,    {RA, RS, UI}},
3324 {"andiu.",      OP(29),         OP_MASK,     PWRCOM,    {RA, RS, UI}},
3325
3326 {"rotldi",      MD(30,0,0),     MDMB_MASK,   PPC64,     {RA, RS, SH6}},
3327 {"clrldi",      MD(30,0,0),     MDSH_MASK,   PPC64,     {RA, RS, MB6}},
3328 {"rldicl",      MD(30,0,0),     MD_MASK,     PPC64,     {RA, RS, SH6, MB6}},
3329 {"rotldi.",     MD(30,0,1),     MDMB_MASK,   PPC64,     {RA, RS, SH6}},
3330 {"clrldi.",     MD(30,0,1),     MDSH_MASK,   PPC64,     {RA, RS, MB6}},
3331 {"rldicl.",     MD(30,0,1),     MD_MASK,     PPC64,     {RA, RS, SH6, MB6}},
3332
3333 {"rldicr",      MD(30,1,0),     MD_MASK,     PPC64,     {RA, RS, SH6, ME6}},
3334 {"rldicr.",     MD(30,1,1),     MD_MASK,     PPC64,     {RA, RS, SH6, ME6}},
3335
3336 {"rldic",       MD(30,2,0),     MD_MASK,     PPC64,     {RA, RS, SH6, MB6}},
3337 {"rldic.",      MD(30,2,1),     MD_MASK,     PPC64,     {RA, RS, SH6, MB6}},
3338
3339 {"rldimi",      MD(30,3,0),     MD_MASK,     PPC64,     {RA, RS, SH6, MB6}},
3340 {"rldimi.",     MD(30,3,1),     MD_MASK,     PPC64,     {RA, RS, SH6, MB6}},
3341
3342 {"rotld",       MDS(30,8,0),    MDSMB_MASK,  PPC64,     {RA, RS, RB}},
3343 {"rldcl",       MDS(30,8,0),    MDS_MASK,    PPC64,     {RA, RS, RB, MB6}},
3344 {"rotld.",      MDS(30,8,1),    MDSMB_MASK,  PPC64,     {RA, RS, RB}},
3345 {"rldcl.",      MDS(30,8,1),    MDS_MASK,    PPC64,     {RA, RS, RB, MB6}},
3346
3347 {"rldcr",       MDS(30,9,0),    MDS_MASK,    PPC64,     {RA, RS, RB, ME6}},
3348 {"rldcr.",      MDS(30,9,1),    MDS_MASK,    PPC64,     {RA, RS, RB, ME6}},
3349
3350 {"cmpw",        XOPL(31,0,0),   XCMPL_MASK,  PPCCOM,    {OBF, RA, RB}},
3351 {"cmpd",        XOPL(31,0,1),   XCMPL_MASK,  PPC64,     {OBF, RA, RB}},
3352 {"cmp",         X(31,0),        XCMP_MASK,   PPC,       {BF, L, RA, RB}},
3353 {"cmp",         X(31,0),        XCMPL_MASK,  PWRCOM,    {BF, RA, RB}},
3354
3355 {"twlgt",       XTO(31,4,TOLGT), XTO_MASK,   PPCCOM,    {RA, RB}},
3356 {"tlgt",        XTO(31,4,TOLGT), XTO_MASK,   PWRCOM,    {RA, RB}},
3357 {"twllt",       XTO(31,4,TOLLT), XTO_MASK,   PPCCOM,    {RA, RB}},
3358 {"tllt",        XTO(31,4,TOLLT), XTO_MASK,   PWRCOM,    {RA, RB}},
3359 {"tweq",        XTO(31,4,TOEQ),  XTO_MASK,   PPCCOM,    {RA, RB}},
3360 {"teq",         XTO(31,4,TOEQ),  XTO_MASK,   PWRCOM,    {RA, RB}},
3361 {"twlge",       XTO(31,4,TOLGE), XTO_MASK,   PPCCOM,    {RA, RB}},
3362 {"tlge",        XTO(31,4,TOLGE), XTO_MASK,   PWRCOM,    {RA, RB}},
3363 {"twlnl",       XTO(31,4,TOLNL), XTO_MASK,   PPCCOM,    {RA, RB}},
3364 {"tlnl",        XTO(31,4,TOLNL), XTO_MASK,   PWRCOM,    {RA, RB}},
3365 {"twlle",       XTO(31,4,TOLLE), XTO_MASK,   PPCCOM,    {RA, RB}},
3366 {"tlle",        XTO(31,4,TOLLE), XTO_MASK,   PWRCOM,    {RA, RB}},
3367 {"twlng",       XTO(31,4,TOLNG), XTO_MASK,   PPCCOM,    {RA, RB}},
3368 {"tlng",        XTO(31,4,TOLNG), XTO_MASK,   PWRCOM,    {RA, RB}},
3369 {"twgt",        XTO(31,4,TOGT),  XTO_MASK,   PPCCOM,    {RA, RB}},
3370 {"tgt",         XTO(31,4,TOGT),  XTO_MASK,   PWRCOM,    {RA, RB}},
3371 {"twge",        XTO(31,4,TOGE),  XTO_MASK,   PPCCOM,    {RA, RB}},
3372 {"tge",         XTO(31,4,TOGE),  XTO_MASK,   PWRCOM,    {RA, RB}},
3373 {"twnl",        XTO(31,4,TONL),  XTO_MASK,   PPCCOM,    {RA, RB}},
3374 {"tnl",         XTO(31,4,TONL),  XTO_MASK,   PWRCOM,    {RA, RB}},
3375 {"twlt",        XTO(31,4,TOLT),  XTO_MASK,   PPCCOM,    {RA, RB}},
3376 {"tlt",         XTO(31,4,TOLT),  XTO_MASK,   PWRCOM,    {RA, RB}},
3377 {"twle",        XTO(31,4,TOLE),  XTO_MASK,   PPCCOM,    {RA, RB}},
3378 {"tle",         XTO(31,4,TOLE),  XTO_MASK,   PWRCOM,    {RA, RB}},
3379 {"twng",        XTO(31,4,TONG),  XTO_MASK,   PPCCOM,    {RA, RB}},
3380 {"tng",         XTO(31,4,TONG),  XTO_MASK,   PWRCOM,    {RA, RB}},
3381 {"twne",        XTO(31,4,TONE),  XTO_MASK,   PPCCOM,    {RA, RB}},
3382 {"tne",         XTO(31,4,TONE),  XTO_MASK,   PWRCOM,    {RA, RB}},
3383 {"trap",        XTO(31,4,TOU),   0xffffffff, PPCCOM,    {0}},
3384 {"tw",          X(31,4),         X_MASK,     PPCCOM,    {TO, RA, RB}},
3385 {"t",           X(31,4),         X_MASK,     PWRCOM,    {TO, RA, RB}},
3386
3387 {"lvsl",        X(31,6),        X_MASK,      PPCVEC,    {VD, RA, RB}},
3388 {"lvebx",       X(31,7),        X_MASK,      PPCVEC,    {VD, RA, RB}},
3389 {"lbfcmx",      APU(31,7,0),    APU_MASK,    PPC405,    {FCRT, RA, RB}},
3390
3391 {"subfc",       XO(31,8,0,0),   XO_MASK,     PPCCOM,    {RT, RA, RB}},
3392 {"sf",          XO(31,8,0,0),   XO_MASK,     PWRCOM,    {RT, RA, RB}},
3393 {"subc",        XO(31,8,0,0),   XO_MASK,     PPC,       {RT, RB, RA}},
3394 {"subfc.",      XO(31,8,0,1),   XO_MASK,     PPCCOM,    {RT, RA, RB}},
3395 {"sf.",         XO(31,8,0,1),   XO_MASK,     PWRCOM,    {RT, RA, RB}},
3396 {"subc.",       XO(31,8,0,1),   XO_MASK,     PPCCOM,    {RT, RB, RA}},
3397
3398 {"mulhdu",      XO(31,9,0,0),   XO_MASK,     PPC64,     {RT, RA, RB}},
3399 {"mulhdu.",     XO(31,9,0,1),   XO_MASK,     PPC64,     {RT, RA, RB}},
3400
3401 {"addc",        XO(31,10,0,0),  XO_MASK,     PPCCOM,    {RT, RA, RB}},
3402 {"a",           XO(31,10,0,0),  XO_MASK,     PWRCOM,    {RT, RA, RB}},
3403 {"addc.",       XO(31,10,0,1),  XO_MASK,     PPCCOM,    {RT, RA, RB}},
3404 {"a.",          XO(31,10,0,1),  XO_MASK,     PWRCOM,    {RT, RA, RB}},
3405
3406 {"mulhwu",      XO(31,11,0,0),  XO_MASK,     PPC,       {RT, RA, RB}},
3407 {"mulhwu.",     XO(31,11,0,1),  XO_MASK,     PPC,       {RT, RA, RB}},
3408
3409 {"isellt",      X(31,15),       X_MASK,      PPCISEL,   {RT, RA, RB}},
3410
3411 {"mfcr",        XFXM(31,19,0,0), XRARB_MASK, NOPOWER4|COM, {RT}},
3412 {"mfcr",        XFXM(31,19,0,0), XFXFXM_MASK, POWER4,   {RT, FXM4}},
3413 {"mfocrf",      XFXM(31,19,0,1), XFXFXM_MASK, COM,      {RT, FXM}},
3414
3415 {"lwarx",       X(31,20),       XEH_MASK,    PPC,       {RT, RA0, RB, EH}},
3416
3417 {"ldx",         X(31,21),       X_MASK,      PPC64,     {RT, RA0, RB}},
3418
3419 {"icbt",        X(31,22),       X_MASK,  BOOKE|PPCE300, {CT, RA, RB}},
3420
3421 {"lwzx",        X(31,23),       X_MASK,      PPCCOM,    {RT, RA0, RB}},
3422 {"lx",          X(31,23),       X_MASK,      PWRCOM,    {RT, RA, RB}},
3423
3424 {"slw",         XRC(31,24,0),   X_MASK,      PPCCOM,    {RA, RS, RB}},
3425 {"sl",          XRC(31,24,0),   X_MASK,      PWRCOM,    {RA, RS, RB}},
3426 {"slw.",        XRC(31,24,1),   X_MASK,      PPCCOM,    {RA, RS, RB}},
3427 {"sl.",         XRC(31,24,1),   X_MASK,      PWRCOM,    {RA, RS, RB}},
3428
3429 {"cntlzw",      XRC(31,26,0),   XRB_MASK,    PPCCOM,    {RA, RS}},
3430 {"cntlz",       XRC(31,26,0),   XRB_MASK,    PWRCOM,    {RA, RS}},
3431 {"cntlzw.",     XRC(31,26,1),   XRB_MASK,    PPCCOM,    {RA, RS}},
3432 {"cntlz.",      XRC(31,26,1),   XRB_MASK,    PWRCOM,    {RA, RS}},
3433
3434 {"sld",         XRC(31,27,0),   X_MASK,      PPC64,     {RA, RS, RB}},
3435 {"sld.",        XRC(31,27,1),   X_MASK,      PPC64,     {RA, RS, RB}},
3436
3437 {"and",         XRC(31,28,0),   X_MASK,      COM,       {RA, RS, RB}},
3438 {"and.",        XRC(31,28,1),   X_MASK,      COM,       {RA, RS, RB}},
3439
3440 {"maskg",       XRC(31,29,0),   X_MASK,      M601,      {RA, RS, RB}},
3441 {"maskg.",      XRC(31,29,1),   X_MASK,      M601,      {RA, RS, RB}},
3442
3443 {"ldepx",       X(31,29),       X_MASK,      E500MC,    {RT, RA, RB}},
3444
3445 {"icbte",       X(31,30),       X_MASK,      BOOKE64,   {CT, RA, RB}},
3446
3447 {"lwzxe",       X(31,31),       X_MASK,      BOOKE64,   {RT, RA0, RB}},
3448 {"lwepx",       X(31,31),       X_MASK,      E500MC,    {RT, RA, RB}},
3449
3450 {"cmplw",       XOPL(31,32,0),  XCMPL_MASK,  PPCCOM,    {OBF, RA, RB}},
3451 {"cmpld",       XOPL(31,32,1),  XCMPL_MASK,  PPC64,     {OBF, RA, RB}},
3452 {"cmpl",        X(31,32),       XCMP_MASK,   PPC,       {BF, L, RA, RB}},
3453 {"cmpl",        X(31,32),       XCMPL_MASK,  PWRCOM,    {BF, RA, RB}},
3454
3455 {"lvsr",        X(31,38),       X_MASK,      PPCVEC,    {VD, RA, RB}},
3456 {"lvehx",       X(31,39),       X_MASK,      PPCVEC,    {VD, RA, RB}},
3457 {"lhfcmx",      APU(31,39,0),   APU_MASK,    PPC405,    {FCRT, RA, RB}},
3458
3459 {"iselgt",      X(31,47),       X_MASK,      PPCISEL,   {RT, RA, RB}},
3460
3461 {"lvewx",       X(31,71),       X_MASK,      PPCVEC,    {VD, RA, RB}},
3462
3463 {"iseleq",      X(31,79),       X_MASK,      PPCISEL,   {RT, RA, RB}},
3464
3465 {"isel",        XISEL(31,15),   XISEL_MASK,  PPCISEL,   {RT, RA, RB, CRB}},
3466
3467 {"subf",        XO(31,40,0,0),  XO_MASK,     PPC,       {RT, RA, RB}},
3468 {"sub",         XO(31,40,0,0),  XO_MASK,     PPC,       {RT, RB, RA}},
3469 {"subf.",       XO(31,40,0,1),  XO_MASK,     PPC,       {RT, RA, RB}},
3470 {"sub.",        XO(31,40,0,1),  XO_MASK,     PPC,       {RT, RB, RA}},
3471
3472 {"ldux",        X(31,53),       X_MASK,      PPC64,     {RT, RAL, RB}},
3473
3474 {"dcbst",       X(31,54),       XRT_MASK,    PPC,       {RA, RB}},
3475
3476 {"lwzux",       X(31,55),       X_MASK,      PPCCOM,    {RT, RAL, RB}},
3477 {"lux",         X(31,55),       X_MASK,      PWRCOM,    {RT, RA, RB}},
3478
3479 {"cntlzd",      XRC(31,58,0),   XRB_MASK,    PPC64,     {RA, RS}},
3480 {"cntlzd.",     XRC(31,58,1),   XRB_MASK,    PPC64,     {RA, RS}},
3481
3482 {"andc",        XRC(31,60,0),   X_MASK,      COM,       {RA, RS, RB}},
3483 {"andc.",       XRC(31,60,1),   X_MASK,      COM,       {RA, RS, RB}},
3484
3485 {"dcbste",      X(31,62),       XRT_MASK,    BOOKE64,   {RA, RB}},
3486
3487 {"wait",        X(31,62),       0xffffffff,  E500MC,    {0}},
3488
3489 {"lwzuxe",      X(31,63),       X_MASK,      BOOKE64,   {RT, RAL, RB}},
3490
3491 {"dcbstep",     XRT(31,63,0),   XRT_MASK,    E500MC,    {RA, RB}},
3492
3493 {"tdlgt",       XTO(31,68,TOLGT), XTO_MASK,  PPC64,     {RA, RB}},
3494 {"tdllt",       XTO(31,68,TOLLT), XTO_MASK,  PPC64,     {RA, RB}},
3495 {"tdeq",        XTO(31,68,TOEQ),  XTO_MASK,  PPC64,     {RA, RB}},
3496 {"tdlge",       XTO(31,68,TOLGE), XTO_MASK,  PPC64,     {RA, RB}},
3497 {"tdlnl",       XTO(31,68,TOLNL), XTO_MASK,  PPC64,     {RA, RB}},
3498 {"tdlle",       XTO(31,68,TOLLE), XTO_MASK,  PPC64,     {RA, RB}},
3499 {"tdlng",       XTO(31,68,TOLNG), XTO_MASK,  PPC64,     {RA, RB}},
3500 {"tdgt",        XTO(31,68,TOGT),  XTO_MASK,  PPC64,     {RA, RB}},
3501 {"tdge",        XTO(31,68,TOGE),  XTO_MASK,  PPC64,     {RA, RB}},
3502 {"tdnl",        XTO(31,68,TONL),  XTO_MASK,  PPC64,     {RA, RB}},
3503 {"tdlt",        XTO(31,68,TOLT),  XTO_MASK,  PPC64,     {RA, RB}},
3504 {"tdle",        XTO(31,68,TOLE),  XTO_MASK,  PPC64,     {RA, RB}},
3505 {"tdng",        XTO(31,68,TONG),  XTO_MASK,  PPC64,     {RA, RB}},
3506 {"tdne",        XTO(31,68,TONE),  XTO_MASK,  PPC64,     {RA, RB}},
3507 {"td",          X(31,68),       X_MASK,      PPC64,     {TO, RA, RB}},
3508
3509 {"lwfcmx",      APU(31,71,0),   APU_MASK,    PPC405,    {FCRT, RA, RB}},
3510 {"mulhd",       XO(31,73,0,0),  XO_MASK,     PPC64,     {RT, RA, RB}},
3511 {"mulhd.",      XO(31,73,0,1),  XO_MASK,     PPC64,     {RT, RA, RB}},
3512
3513 {"mulhw",       XO(31,75,0,0),  XO_MASK,     PPC,       {RT, RA, RB}},
3514 {"mulhw.",      XO(31,75,0,1),  XO_MASK,     PPC,       {RT, RA, RB}},
3515
3516 {"dlmzb",       XRC(31,78,0),   X_MASK,  PPC403|PPC440, {RA, RS, RB}},
3517 {"dlmzb.",      XRC(31,78,1),   X_MASK,  PPC403|PPC440, {RA, RS, RB}},
3518
3519 {"mtsrd",       X(31,82),  XRB_MASK|(1<<20), PPC64,     {SR, RS}},
3520
3521 {"mfmsr",       X(31,83),       XRARB_MASK,  COM,       {RT}},
3522
3523 {"ldarx",       X(31,84),       XEH_MASK,    PPC64,     {RT, RA0, RB, EH}},
3524
3525 {"dcbfl",       XOPL(31,86,1),  XRT_MASK,    POWER5,    {RA, RB}},
3526 {"dcbf",        X(31,86),       XLRT_MASK,   PPC,       {RA, RB, L}},
3527
3528 {"lbzx",        X(31,87),       X_MASK,      COM,       {RT, RA0, RB}},
3529
3530 {"dcbfe",       X(31,94),       XRT_MASK,    BOOKE64,   {RA, RB}},
3531
3532 {"lbzxe",       X(31,95),       X_MASK,      BOOKE64,   {RT, RA0, RB}},
3533 {"lbepx",       X(31,95),       X_MASK,      E500MC,    {RT, RA, RB}},
3534
3535 {"lvx",         X(31,103),      X_MASK,      PPCVEC,    {VD, RA, RB}},
3536 {"lqfcmx",      APU(31,103,0),  APU_MASK,    PPC405,    {FCRT, RA, RB}},
3537
3538 {"neg",         XO(31,104,0,0), XORB_MASK,   COM,       {RT, RA}},
3539 {"neg.",        XO(31,104,0,1), XORB_MASK,   COM,       {RT, RA}},
3540
3541 {"mul",         XO(31,107,0,0), XO_MASK,     M601,      {RT, RA, RB}},
3542 {"mul.",        XO(31,107,0,1), XO_MASK,     M601,      {RT, RA, RB}},
3543
3544 {"mtsrdin",     X(31,114),      XRA_MASK,    PPC64,     {RS, RB}},
3545
3546 {"clf",         X(31,118),      XTO_MASK,    POWER,     {RA, RB}},
3547
3548 {"lbzux",       X(31,119),      X_MASK,      COM,       {RT, RAL, RB}},
3549
3550 {"popcntb",     X(31,122),      XRB_MASK,    POWER5,    {RA, RS}},
3551
3552 {"not",         XRC(31,124,0),  X_MASK,      COM,       {RA, RS, RBS}},
3553 {"nor",         XRC(31,124,0),  X_MASK,      COM,       {RA, RS, RB}},
3554 {"not.",        XRC(31,124,1),  X_MASK,      COM,       {RA, RS, RBS}},
3555 {"nor.",        XRC(31,124,1),  X_MASK,      COM,       {RA, RS, RB}},
3556
3557 {"lwarxe",      X(31,126),      X_MASK,      BOOKE64,   {RT, RA0, RB}},
3558
3559 {"lbzuxe",      X(31,127),      X_MASK,      BOOKE64,   {RT, RAL, RB}},
3560
3561 {"dcbfep",      XRT(31,127,0),  XRT_MASK,    E500MC,    {RA, RB}},
3562
3563 {"wrtee",       X(31,131),      XRARB_MASK, PPC403|BOOKE, {RS}},
3564
3565 {"dcbtstls",    X(31,134),      X_MASK,      PPCCHLK,   {CT, RA, RB}},
3566
3567 {"stvebx",      X(31,135),      X_MASK,      PPCVEC,    {VS, RA, RB}},
3568 {"stbfcmx",     APU(31,135,0),  APU_MASK,    PPC405,    {FCRT, RA, RB}},
3569
3570 {"subfe",       XO(31,136,0,0), XO_MASK,     PPCCOM,    {RT, RA, RB}},
3571 {"sfe",         XO(31,136,0,0), XO_MASK,     PWRCOM,    {RT, RA, RB}},
3572 {"subfe.",      XO(31,136,0,1), XO_MASK,     PPCCOM,    {RT, RA, RB}},
3573 {"sfe.",        XO(31,136,0,1), XO_MASK,     PWRCOM,    {RT, RA, RB}},
3574
3575 {"adde",        XO(31,138,0,0), XO_MASK,     PPCCOM,    {RT, RA, RB}},
3576 {"ae",          XO(31,138,0,0), XO_MASK,     PWRCOM,    {RT, RA, RB}},
3577 {"adde.",       XO(31,138,0,1), XO_MASK,     PPCCOM,    {RT, RA, RB}},
3578 {"ae.",         XO(31,138,0,1), XO_MASK,     PWRCOM,    {RT, RA, RB}},
3579
3580 {"dcbtstlse",   X(31,142),      X_MASK,      PPCCHLK64, {CT, RA, RB}},
3581
3582 {"mtcr",        XFXM(31,144,0xff,0), XRARB_MASK, COM,   {RS}},
3583 {"mtcrf",       XFXM(31,144,0,0), XFXFXM_MASK, COM,     {FXM, RS}},
3584 {"mtocrf",      XFXM(31,144,0,1), XFXFXM_MASK, COM,     {FXM, RS}},
3585
3586 {"mtmsr",       X(31,146),      XRLARB_MASK, COM,       {RS, A_L}},
3587
3588 {"stdx",        X(31,149),      X_MASK,      PPC64,     {RS, RA0, RB}},
3589
3590 {"stwcx.",      XRC(31,150,1),  X_MASK,      PPC,       {RS, RA0, RB}},
3591
3592 {"stwx",        X(31,151),      X_MASK,      PPCCOM,    {RS, RA0, RB}},
3593 {"stx",         X(31,151),      X_MASK,      PWRCOM,    {RS, RA, RB}},
3594
3595 {"slq",         XRC(31,152,0),  X_MASK,      M601,      {RA, RS, RB}},
3596 {"slq.",        XRC(31,152,1),  X_MASK,      M601,      {RA, RS, RB}},
3597
3598 {"sle",         XRC(31,153,0),  X_MASK,      M601,      {RA, RS, RB}},
3599 {"sle.",        XRC(31,153,1),  X_MASK,      M601,      {RA, RS, RB}},
3600
3601 {"prtyw",       X(31,154),      XRB_MASK,    POWER6,    {RA, RS}},
3602
3603 {"stdepx",      X(31,157),      X_MASK,      E500MC,    {RS, RA, RB}},
3604
3605 {"stwcxe.",     XRC(31,158,1),  X_MASK,      BOOKE64,   {RS, RA0, RB}},
3606
3607 {"stwxe",       X(31,159),      X_MASK,      BOOKE64,   {RS, RA0, RB}},
3608 {"stwepx",      X(31,159),      X_MASK,      E500MC,    {RS, RA, RB}},
3609
3610 {"wrteei",      X(31,163),      XE_MASK,  PPC403|BOOKE, {E}},
3611
3612 {"dcbtls",      X(31,166),      X_MASK,      PPCCHLK,   {CT, RA, RB}},
3613
3614 {"stvehx",      X(31,167),      X_MASK,      PPCVEC,    {VS, RA, RB}},
3615 {"sthfcmx",     APU(31,167,0),  APU_MASK,    PPC405,    {FCRT, RA, RB}},
3616
3617 {"dcbtlse",     X(31,174),      X_MASK,      PPCCHLK64, {CT, RA, RB}},
3618
3619 {"mtmsrd",      X(31,178),      XRLARB_MASK, PPC64,     {RS, A_L}},
3620
3621 {"stdux",       X(31,181),      X_MASK,      PPC64,     {RS, RAS, RB}},
3622
3623 {"stwux",       X(31,183),      X_MASK,      PPCCOM,    {RS, RAS, RB}},
3624 {"stux",        X(31,183),      X_MASK,      PWRCOM,    {RS, RA0, RB}},
3625
3626 {"sliq",        XRC(31,184,0),  X_MASK,      M601,      {RA, RS, SH}},
3627 {"sliq.",       XRC(31,184,1),  X_MASK,      M601,      {RA, RS, SH}},
3628
3629 {"prtyd",       X(31,186),      XRB_MASK,    POWER6,    {RA, RS}},
3630
3631 {"stwuxe",      X(31,191),      X_MASK,      BOOKE64,   {RS, RAS, RB}},
3632
3633 {"stvewx",      X(31,199),      X_MASK,      PPCVEC,    {VS, RA, RB}},
3634 {"stwfcmx",     APU(31,199,0),  APU_MASK,    PPC405,    {FCRT, RA, RB}},
3635
3636 {"subfze",      XO(31,200,0,0), XORB_MASK,   PPCCOM,    {RT, RA}},
3637 {"sfze",        XO(31,200,0,0), XORB_MASK,   PWRCOM,    {RT, RA}},
3638 {"subfze.",     XO(31,200,0,1), XORB_MASK,   PPCCOM,    {RT, RA}},
3639 {"sfze.",       XO(31,200,0,1), XORB_MASK,   PWRCOM,    {RT, RA}},
3640
3641 {"addze",       XO(31,202,0,0), XORB_MASK,   PPCCOM,    {RT, RA}},
3642 {"aze",         XO(31,202,0,0), XORB_MASK,   PWRCOM,    {RT, RA}},
3643 {"addze.",      XO(31,202,0,1), XORB_MASK,   PPCCOM,    {RT, RA}},
3644 {"aze.",        XO(31,202,0,1), XORB_MASK,   PWRCOM,    {RT, RA}},
3645
3646 {"msgsnd",      XRTRA(31,206,0,0),XRTRA_MASK,E500MC,    {RB}},
3647
3648 {"mtsr",        X(31,210), XRB_MASK|(1<<20), COM32,     {SR, RS}},
3649
3650 {"stdcx.",      XRC(31,214,1),  X_MASK,      PPC64,     {RS, RA0, RB}},
3651
3652 {"stbx",        X(31,215),      X_MASK,      COM,       {RS, RA0, RB}},
3653
3654 {"sllq",        XRC(31,216,0),  X_MASK,      M601,      {RA, RS, RB}},
3655 {"sllq.",       XRC(31,216,1),  X_MASK,      M601,      {RA, RS, RB}},
3656
3657 {"sleq",        XRC(31,217,0),  X_MASK,      M601,      {RA, RS, RB}},
3658 {"sleq.",       XRC(31,217,1),  X_MASK,      M601,      {RA, RS, RB}},
3659
3660 {"stbxe",       X(31,223),      X_MASK,      BOOKE64,   {RS, RA0, RB}},
3661 {"stbepx",      X(31,223),      X_MASK,      E500MC,    {RS, RA, RB}},
3662
3663 {"icblc",       X(31,230),      X_MASK,      PPCCHLK,   {CT, RA, RB}},
3664
3665 {"stvx",        X(31,231),      X_MASK,      PPCVEC,    {VS, RA, RB}},
3666 {"stqfcmx",     APU(31,231,0),  APU_MASK,    PPC405,    {FCRT, RA, RB}},
3667
3668 {"subfme",      XO(31,232,0,0), XORB_MASK,   PPCCOM,    {RT, RA}},
3669 {"sfme",        XO(31,232,0,0), XORB_MASK,   PWRCOM,    {RT, RA}},
3670 {"subfme.",     XO(31,232,0,1), XORB_MASK,   PPCCOM,    {RT, RA}},
3671 {"sfme.",       XO(31,232,0,1), XORB_MASK,   PWRCOM,    {RT, RA}},
3672
3673 {"mulld",       XO(31,233,0,0), XO_MASK,     PPC64,     {RT, RA, RB}},
3674 {"mulld.",      XO(31,233,0,1), XO_MASK,     PPC64,     {RT, RA, RB}},
3675
3676 {"addme",       XO(31,234,0,0), XORB_MASK,   PPCCOM,    {RT, RA}},
3677 {"ame",         XO(31,234,0,0), XORB_MASK,   PWRCOM,    {RT, RA}},
3678 {"addme.",      XO(31,234,0,1), XORB_MASK,   PPCCOM,    {RT, RA}},
3679 {"ame.",        XO(31,234,0,1), XORB_MASK,   PWRCOM,    {RT, RA}},
3680
3681 {"mullw",       XO(31,235,0,0), XO_MASK,     PPCCOM,    {RT, RA, RB}},
3682 {"muls",        XO(31,235,0,0), XO_MASK,     PWRCOM,    {RT, RA, RB}},
3683 {"mullw.",      XO(31,235,0,1), XO_MASK,     PPCCOM,    {RT, RA, RB}},
3684 {"muls.",       XO(31,235,0,1), XO_MASK,     PWRCOM,    {RT, RA, RB}},
3685
3686 {"msgclr",      XRTRA(31,238,0,0),XRTRA_MASK,E500MC,    {RB}},
3687 {"icblce",      X(31,238),      X_MASK,      PPCCHLK64, {CT, RA, RB}},
3688 {"mtsrin",      X(31,242),      XRA_MASK,    PPC32,     {RS, RB}},
3689 {"mtsri",       X(31,242),      XRA_MASK,    POWER32,   {RS, RB}},
3690
3691 {"dcbtst",      X(31,246),      X_MASK,      PPC,       {CT, RA, RB}},
3692
3693 {"stbux",       X(31,247),      X_MASK,      COM,       {RS, RAS, RB}},
3694
3695 {"slliq",       XRC(31,248,0),  X_MASK,      M601,      {RA, RS, SH}},
3696 {"slliq.",      XRC(31,248,1),  X_MASK,      M601,      {RA, RS, SH}},
3697
3698 {"dcbtste",     X(31,253),      X_MASK,      BOOKE64,   {CT, RA, RB}},
3699
3700 {"stbuxe",      X(31,255),      X_MASK,      BOOKE64,   {RS, RAS, RB}},
3701
3702 {"dcbtstep",    XRT(31,255,0),  X_MASK,      E500MC,    {RT, RA, RB}},
3703
3704 {"mfdcrx",      X(31,259),      X_MASK,      BOOKE,     {RS, RA}},
3705
3706 {"icbt",        X(31,262),      XRT_MASK,    PPC403,    {RA, RB}},
3707
3708 {"ldfcmx",      APU(31,263,0),  APU_MASK,    PPC405,    {FCRT, RA, RB}},
3709 {"doz",         XO(31,264,0,0), XO_MASK,     M601,      {RT, RA, RB}},
3710 {"doz.",        XO(31,264,0,1), XO_MASK,     M601,      {RT, RA, RB}},
3711
3712 {"add",         XO(31,266,0,0), XO_MASK,     PPCCOM,    {RT, RA, RB}},
3713 {"cax",         XO(31,266,0,0), XO_MASK,     PWRCOM,    {RT, RA, RB}},
3714 {"add.",        XO(31,266,0,1), XO_MASK,     PPCCOM,    {RT, RA, RB}},
3715 {"cax.",        XO(31,266,0,1), XO_MASK,     PWRCOM,    {RT, RA, RB}},
3716
3717 {"ehpriv",      X(31,270),      0xffffffff,  E500MC,    {0}},
3718
3719 {"tlbiel",      X(31,274),      XRTLRA_MASK, POWER4,    {RB, L}},
3720
3721 {"mfapidi",     X(31,275),      X_MASK,      BOOKE,     {RT, RA}},
3722
3723 {"lscbx",       XRC(31,277,0),  X_MASK,      M601,      {RT, RA, RB}},
3724 {"lscbx.",      XRC(31,277,1),  X_MASK,      M601,      {RT, RA, RB}},
3725
3726 {"dcbt",        X(31,278),      X_MASK,      PPC,       {CT, RA, RB}},
3727
3728 {"lhzx",        X(31,279),      X_MASK,      COM,       {RT, RA0, RB}},
3729
3730 {"eqv",         XRC(31,284,0),  X_MASK,      COM,       {RA, RS, RB}},
3731 {"eqv.",        XRC(31,284,1),  X_MASK,      COM,       {RA, RS, RB}},
3732
3733 {"dcbte",       X(31,286),      X_MASK,      BOOKE64,   {CT, RA, RB}},
3734
3735 {"lhzxe",       X(31,287),      X_MASK,      BOOKE64,   {RT, RA0, RB}},
3736 {"lhepx",       X(31,287),      X_MASK,      E500MC,    {RT, RA, RB}},
3737
3738 {"mfdcrux",     X(31,291),      X_MASK,      PPC464,    {RS, RA}},
3739
3740 {"tlbie",       X(31,306),      XRTLRA_MASK, PPC,       {RB, L}},
3741 {"tlbi",        X(31,306),      XRT_MASK,    POWER,     {RA0, RB}},
3742
3743 {"eciwx",       X(31,310),      X_MASK,      PPC,       {RT, RA, RB}},
3744
3745 {"lhzux",       X(31,311),      X_MASK,      COM,       {RT, RAL, RB}},
3746
3747 {"xor",         XRC(31,316,0),  X_MASK,      COM,       {RA, RS, RB}},
3748 {"xor.",        XRC(31,316,1),  X_MASK,      COM,       {RA, RS, RB}},
3749
3750 {"lhzuxe",      X(31,319),      X_MASK,      BOOKE64,   {RT, RAL, RB}},
3751
3752 {"dcbtep",      XRT(31,319,0),  X_MASK,      E500MC,    {RT, RA, RB}},
3753
3754 {"mfexisr",     XSPR(31,323, 64), XSPR_MASK, PPC403,    {RT}},
3755 {"mfexier",     XSPR(31,323, 66), XSPR_MASK, PPC403,    {RT}},
3756 {"mfbr0",       XSPR(31,323,128), XSPR_MASK, PPC403,    {RT}},
3757 {"mfbr1",       XSPR(31,323,129), XSPR_MASK, PPC403,    {RT}},
3758 {"mfbr2",       XSPR(31,323,130), XSPR_MASK, PPC403,    {RT}},
3759 {"mfbr3",       XSPR(31,323,131), XSPR_MASK, PPC403,    {RT}},
3760 {"mfbr4",       XSPR(31,323,132), XSPR_MASK, PPC403,    {RT}},
3761 {"mfbr5",       XSPR(31,323,133), XSPR_MASK, PPC403,    {RT}},
3762 {"mfbr6",       XSPR(31,323,134), XSPR_MASK, PPC403,    {RT}},
3763 {"mfbr7",       XSPR(31,323,135), XSPR_MASK, PPC403,    {RT}},
3764 {"mfbear",      XSPR(31,323,144), XSPR_MASK, PPC403,    {RT}},
3765 {"mfbesr",      XSPR(31,323,145), XSPR_MASK, PPC403,    {RT}},
3766 {"mfiocr",      XSPR(31,323,160), XSPR_MASK, PPC403,    {RT}},
3767 {"mfdmacr0",    XSPR(31,323,192), XSPR_MASK, PPC403,    {RT}},
3768 {"mfdmact0",    XSPR(31,323,193), XSPR_MASK, PPC403,    {RT}},
3769 {"mfdmada0",    XSPR(31,323,194), XSPR_MASK, PPC403,    {RT}},
3770 {"mfdmasa0",    XSPR(31,323,195), XSPR_MASK, PPC403,    {RT}},
3771 {"mfdmacc0",    XSPR(31,323,196), XSPR_MASK, PPC403,    {RT}},
3772 {"mfdmacr1",    XSPR(31,323,200), XSPR_MASK, PPC403,    {RT}},
3773 {"mfdmact1",    XSPR(31,323,201), XSPR_MASK, PPC403,    {RT}},
3774 {"mfdmada1",    XSPR(31,323,202), XSPR_MASK, PPC403,    {RT}},
3775 {"mfdmasa1",    XSPR(31,323,203), XSPR_MASK, PPC403,    {RT}},
3776 {"mfdmacc1",    XSPR(31,323,204), XSPR_MASK, PPC403,    {RT}},
3777 {"mfdmacr2",    XSPR(31,323,208), XSPR_MASK, PPC403,    {RT}},
3778 {"mfdmact2",    XSPR(31,323,209), XSPR_MASK, PPC403,    {RT}},
3779 {"mfdmada2",    XSPR(31,323,210), XSPR_MASK, PPC403,    {RT}},
3780 {"mfdmasa2",    XSPR(31,323,211), XSPR_MASK, PPC403,    {RT}},
3781 {"mfdmacc2",    XSPR(31,323,212), XSPR_MASK, PPC403,    {RT}},
3782 {"mfdmacr3",    XSPR(31,323,216), XSPR_MASK, PPC403,    {RT}},
3783 {"mfdmact3",    XSPR(31,323,217), XSPR_MASK, PPC403,    {RT}},
3784 {"mfdmada3",    XSPR(31,323,218), XSPR_MASK, PPC403,    {RT}},
3785 {"mfdmasa3",    XSPR(31,323,219), XSPR_MASK, PPC403,    {RT}},
3786 {"mfdmacc3",    XSPR(31,323,220), XSPR_MASK, PPC403,    {RT}},
3787 {"mfdmasr",     XSPR(31,323,224), XSPR_MASK, PPC403,    {RT}},
3788 {"mfdcr",       X(31,323),      X_MASK,   PPC403|BOOKE, {RT, SPR}},
3789
3790 {"div",         XO(31,331,0,0), XO_MASK,     M601,      {RT, RA, RB}},
3791 {"div.",        XO(31,331,0,1), XO_MASK,     M601,      {RT, RA, RB}},
3792
3793 {"mfpmr",       X(31,334),      X_MASK, PPCPMR|PPCE300, {RT, PMR}},
3794
3795 {"mfmq",        XSPR(31,339,  0), XSPR_MASK, M601,      {RT}},
3796 {"mfxer",       XSPR(31,339,  1), XSPR_MASK, COM,       {RT}},
3797 {"mfrtcu",      XSPR(31,339,  4), XSPR_MASK, COM,       {RT}},
3798 {"mfrtcl",      XSPR(31,339,  5), XSPR_MASK, COM,       {RT}},
3799 {"mfdec",       XSPR(31,339,  6), XSPR_MASK, MFDEC1,    {RT}},
3800 {"mflr",        XSPR(31,339,  8), XSPR_MASK, COM,       {RT}},
3801 {"mfctr",       XSPR(31,339,  9), XSPR_MASK, COM,       {RT}},
3802 {"mftid",       XSPR(31,339, 17), XSPR_MASK, POWER,     {RT}},
3803 {"mfdsisr",     XSPR(31,339, 18), XSPR_MASK, COM,       {RT}},
3804 {"mfdar",       XSPR(31,339, 19), XSPR_MASK, COM,       {RT}},
3805 {"mfdec",       XSPR(31,339, 22), XSPR_MASK, MFDEC2,    {RT}},
3806 {"mfsdr0",      XSPR(31,339, 24), XSPR_MASK, POWER,     {RT}},
3807 {"mfsdr1",      XSPR(31,339, 25), XSPR_MASK, COM,       {RT}},
3808 {"mfsrr0",      XSPR(31,339, 26), XSPR_MASK, COM,       {RT}},
3809 {"mfsrr1",      XSPR(31,339, 27), XSPR_MASK, COM,       {RT}},
3810 {"mfcfar",      XSPR(31,339, 28), XSPR_MASK, POWER6,    {RT}},
3811 {"mfpid",       XSPR(31,339, 48), XSPR_MASK, BOOKE,     {RT}},
3812 {"mfcsrr0",     XSPR(31,339, 58), XSPR_MASK, BOOKE,     {RT}},
3813 {"mfcsrr1",     XSPR(31,339, 59), XSPR_MASK, BOOKE,     {RT}},
3814 {"mfdear",      XSPR(31,339, 61), XSPR_MASK, BOOKE,     {RT}},
3815 {"mfesr",       XSPR(31,339, 62), XSPR_MASK, BOOKE,     {RT}},
3816 {"mfivpr",      XSPR(31,339, 63), XSPR_MASK, BOOKE,     {RT}},
3817 {"mfcmpa",      XSPR(31,339,144), XSPR_MASK, PPC860,    {RT}},
3818 {"mfcmpb",      XSPR(31,339,145), XSPR_MASK, PPC860,    {RT}},
3819 {"mfcmpc",      XSPR(31,339,146), XSPR_MASK, PPC860,    {RT}},
3820 {"mfcmpd",      XSPR(31,339,147), XSPR_MASK, PPC860,    {RT}},
3821 {"mficr",       XSPR(31,339,148), XSPR_MASK, PPC860,    {RT}},
3822 {"mfder",       XSPR(31,339,149), XSPR_MASK, PPC860,    {RT}},
3823 {"mfcounta",    XSPR(31,339,150), XSPR_MASK, PPC860,    {RT}},
3824 {"mfcountb",    XSPR(31,339,151), XSPR_MASK, PPC860,    {RT}},
3825 {"mfcmpe",      XSPR(31,339,152), XSPR_MASK, PPC860,    {RT}},
3826 {"mfcmpf",      XSPR(31,339,153), XSPR_MASK, PPC860,    {RT}},
3827 {"mfcmpg",      XSPR(31,339,154), XSPR_MASK, PPC860,    {RT}},
3828 {"mfcmph",      XSPR(31,339,155), XSPR_MASK, PPC860,    {RT}},
3829 {"mflctrl1",    XSPR(31,339,156), XSPR_MASK, PPC860,    {RT}},
3830 {"mflctrl2",    XSPR(31,339,157), XSPR_MASK, PPC860,    {RT}},
3831 {"mfictrl",     XSPR(31,339,158), XSPR_MASK, PPC860,    {RT}},
3832 {"mfbar",       XSPR(31,339,159), XSPR_MASK, PPC860,    {RT}},
3833 {"mfvrsave",    XSPR(31,339,256), XSPR_MASK, PPCVEC,    {RT}},
3834 {"mfusprg0",    XSPR(31,339,256), XSPR_MASK, BOOKE,     {RT}},
3835 {"mfsprg",      XSPR(31,339,256), XSPRG_MASK, PPC,      {RT, SPRG}},
3836 {"mfsprg4",     XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, {RT}},
3837 {"mfsprg5",     XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, {RT}},
3838 {"mfsprg6",     XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, {RT}},
3839 {"mfsprg7",     XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, {RT}},
3840 {"mftb",        XSPR(31,339,268), XSPR_MASK, BOOKE,     {RT}},
3841 {"mftbl",       XSPR(31,339,268), XSPR_MASK, BOOKE,     {RT}},
3842 {"mftbu",       XSPR(31,339,269), XSPR_MASK, BOOKE,     {RT}},
3843 {"mfsprg0",     XSPR(31,339,272), XSPR_MASK, PPC,       {RT}},
3844 {"mfsprg1",     XSPR(31,339,273), XSPR_MASK, PPC,       {RT}},
3845 {"mfsprg2",     XSPR(31,339,274), XSPR_MASK, PPC,       {RT}},
3846 {"mfsprg3",     XSPR(31,339,275), XSPR_MASK, PPC,       {RT}},
3847 {"mfasr",       XSPR(31,339,280), XSPR_MASK, PPC64,     {RT}},
3848 {"mfear",       XSPR(31,339,282), XSPR_MASK, PPC,       {RT}},
3849 {"mfpir",       XSPR(31,339,286), XSPR_MASK, BOOKE,     {RT}},
3850 {"mfpvr",       XSPR(31,339,287), XSPR_MASK, PPC,       {RT}},
3851 {"mfdbsr",      XSPR(31,339,304), XSPR_MASK, BOOKE,     {RT}},
3852 {"mfdbcr0",     XSPR(31,339,308), XSPR_MASK, BOOKE,     {RT}},
3853 {"mfdbcr1",     XSPR(31,339,309), XSPR_MASK, BOOKE,     {RT}},
3854 {"mfdbcr2",     XSPR(31,339,310), XSPR_MASK, BOOKE,     {RT}},
3855 {"mfiac1",      XSPR(31,339,312), XSPR_MASK, BOOKE,     {RT}},
3856 {"mfiac2",      XSPR(31,339,313), XSPR_MASK, BOOKE,     {RT}},
3857 {"mfiac3",      XSPR(31,339,314), XSPR_MASK, BOOKE,     {RT}},
3858 {"mfiac4",      XSPR(31,339,315), XSPR_MASK, BOOKE,     {RT}},
3859 {"mfdac1",      XSPR(31,339,316), XSPR_MASK, BOOKE,     {RT}},
3860 {"mfdac2",      XSPR(31,339,317), XSPR_MASK, BOOKE,     {RT}},
3861 {"mfdvc1",      XSPR(31,339,318), XSPR_MASK, BOOKE,     {RT}},
3862 {"mfdvc2",      XSPR(31,339,319), XSPR_MASK, BOOKE,     {RT}},
3863 {"mftsr",       XSPR(31,339,336), XSPR_MASK, BOOKE,     {RT}},
3864 {"mftcr",       XSPR(31,339,340), XSPR_MASK, BOOKE,     {RT}},
3865 {"mfivor0",     XSPR(31,339,400), XSPR_MASK, BOOKE,     {RT}},
3866 {"mfivor1",     XSPR(31,339,401), XSPR_MASK, BOOKE,     {RT}},
3867 {"mfivor2",     XSPR(31,339,402), XSPR_MASK, BOOKE,     {RT}},
3868 {"mfivor3",     XSPR(31,339,403), XSPR_MASK, BOOKE,     {RT}},
3869 {"mfivor4",     XSPR(31,339,404), XSPR_MASK, BOOKE,     {RT}},
3870 {"mfivor5",     XSPR(31,339,405), XSPR_MASK, BOOKE,     {RT}},
3871 {"mfivor6",     XSPR(31,339,406), XSPR_MASK, BOOKE,     {RT}},
3872 {"mfivor7",     XSPR(31,339,407), XSPR_MASK, BOOKE,     {RT}},
3873 {"mfivor8",     XSPR(31,339,408), XSPR_MASK, BOOKE,     {RT}},
3874 {"mfivor9",     XSPR(31,339,409), XSPR_MASK, BOOKE,     {RT}},
3875 {"mfivor10",    XSPR(31,339,410), XSPR_MASK, BOOKE,     {RT}},
3876 {"mfivor11",    XSPR(31,339,411), XSPR_MASK, BOOKE,     {RT}},
3877 {"mfivor12",    XSPR(31,339,412), XSPR_MASK, BOOKE,     {RT}},
3878 {"mfivor13",    XSPR(31,339,413), XSPR_MASK, BOOKE,     {RT}},
3879 {"mfivor14",    XSPR(31,339,414), XSPR_MASK, BOOKE,     {RT}},
3880 {"mfivor15",    XSPR(31,339,415), XSPR_MASK, BOOKE,     {RT}},
3881 {"mfspefscr",   XSPR(31,339,512), XSPR_MASK, PPCSPE,    {RT}},
3882 {"mfbbear",     XSPR(31,339,513), XSPR_MASK, PPCBRLK,   {RT}},
3883 {"mfbbtar",     XSPR(31,339,514), XSPR_MASK, PPCBRLK,   {RT}},
3884 {"mfivor32",    XSPR(31,339,528), XSPR_MASK, PPCSPE,    {RT}},
3885 {"mfibatu",     XSPR(31,339,528), XSPRBAT_MASK, PPC,    {RT, SPRBAT}},
3886 {"mfivor33",    XSPR(31,339,529), XSPR_MASK, PPCSPE,    {RT}},
3887 {"mfibatl",     XSPR(31,339,529), XSPRBAT_MASK, PPC,    {RT, SPRBAT}},
3888 {"mfivor34",    XSPR(31,339,530), XSPR_MASK, PPCSPE,    {RT}},
3889 {"mfivor35",    XSPR(31,339,531), XSPR_MASK, PPCPMR,    {RT}},
3890 {"mfdbatu",     XSPR(31,339,536), XSPRBAT_MASK, PPC,    {RT, SPRBAT}},
3891 {"mfdbatl",     XSPR(31,339,537), XSPRBAT_MASK, PPC,    {RT, SPRBAT}},
3892 {"mfic_cst",    XSPR(31,339,560), XSPR_MASK, PPC860,    {RT}},
3893 {"mfic_adr",    XSPR(31,339,561), XSPR_MASK, PPC860,    {RT}},
3894 {"mfic_dat",    XSPR(31,339,562), XSPR_MASK, PPC860,    {RT}},
3895 {"mfdc_cst",    XSPR(31,339,568), XSPR_MASK, PPC860,    {RT}},
3896 {"mfdc_adr",    XSPR(31,339,569), XSPR_MASK, PPC860,    {RT}},
3897 {"mfdc_dat",    XSPR(31,339,570), XSPR_MASK, PPC860,    {RT}},
3898 {"mfmcsrr0",    XSPR(31,339,570), XSPR_MASK, PPCRFMCI,  {RT}},
3899 {"mfmcsrr1",    XSPR(31,339,571), XSPR_MASK, PPCRFMCI,  {RT}},
3900 {"mfmcsr",      XSPR(31,339,572), XSPR_MASK, PPCRFMCI,  {RT}},
3901 {"mfmcar",      XSPR(31,339,573), XSPR_MASK, PPCRFMCI,  {RT}},
3902 {"mfdpdr",      XSPR(31,339,630), XSPR_MASK, PPC860,    {RT}},
3903 {"mfdpir",      XSPR(31,339,631), XSPR_MASK, PPC860,    {RT}},
3904 {"mfimmr",      XSPR(31,339,638), XSPR_MASK, PPC860,    {RT}},
3905 {"mfmi_ctr",    XSPR(31,339,784), XSPR_MASK, PPC860,    {RT}},
3906 {"mfmi_ap",     XSPR(31,339,786), XSPR_MASK, PPC860,    {RT}},
3907 {"mfmi_epn",    XSPR(31,339,787), XSPR_MASK, PPC860,    {RT}},
3908 {"mfmi_twc",    XSPR(31,339,789), XSPR_MASK, PPC860,    {RT}},
3909 {"mfmi_rpn",    XSPR(31,339,790), XSPR_MASK, PPC860,    {RT}},
3910 {"mfmd_ctr",    XSPR(31,339,792), XSPR_MASK, PPC860,    {RT}},
3911 {"mfm_casid",   XSPR(31,339,793), XSPR_MASK, PPC860,    {RT}},
3912 {"mfmd_ap",     XSPR(31,339,794), XSPR_MASK, PPC860,    {RT}},
3913 {"mfmd_epn",    XSPR(31,339,795), XSPR_MASK, PPC860,    {RT}},
3914 {"mfmd_twb",    XSPR(31,339,796), XSPR_MASK, PPC860,    {RT}},
3915 {"mfmd_twc",    XSPR(31,339,797), XSPR_MASK, PPC860,    {RT}},
3916 {"mfmd_rpn",    XSPR(31,339,798), XSPR_MASK, PPC860,    {RT}},
3917 {"mfm_tw",      XSPR(31,339,799), XSPR_MASK, PPC860,    {RT}},
3918 {"mfmi_dbcam",  XSPR(31,339,816), XSPR_MASK, PPC860,    {RT}},
3919 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860,    {RT}},
3920 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860,    {RT}},
3921 {"mfmd_dbcam",  XSPR(31,339,824), XSPR_MASK, PPC860,    {RT}},
3922 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860,    {RT}},
3923 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860,    {RT}},
3924 {"mfummcr0",    XSPR(31,339,936), XSPR_MASK, PPC750,    {RT}},
3925 {"mfupmc1",     XSPR(31,339,937), XSPR_MASK, PPC750,    {RT}},
3926 {"mfupmc2",     XSPR(31,339,938), XSPR_MASK, PPC750,    {RT}},
3927 {"mfusia",      XSPR(31,339,939), XSPR_MASK, PPC750,    {RT}},
3928 {"mfummcr1",    XSPR(31,339,940), XSPR_MASK, PPC750,    {RT}},
3929 {"mfupmc3",     XSPR(31,339,941), XSPR_MASK, PPC750,    {RT}},
3930 {"mfupmc4",     XSPR(31,339,942), XSPR_MASK, PPC750,    {RT}},
3931 {"mfzpr",       XSPR(31,339,944), XSPR_MASK, PPC403,    {RT}},
3932 {"mfpid",       XSPR(31,339,945), XSPR_MASK, PPC403,    {RT}},
3933 {"mfccr0",      XSPR(31,339,947), XSPR_MASK, PPC405,    {RT}},
3934 {"mfiac3",      XSPR(31,339,948), XSPR_MASK, PPC405,    {RT}},
3935 {"mfiac4",      XSPR(31,339,949), XSPR_MASK, PPC405,    {RT}},
3936 {"mfdvc1",      XSPR(31,339,950), XSPR_MASK, PPC405,    {RT}},
3937 {"mfdvc2",      XSPR(31,339,951), XSPR_MASK, PPC405,    {RT}},
3938 {"mfmmcr0",     XSPR(31,339,952), XSPR_MASK, PPC750,    {RT}},
3939 {"mfpmc1",      XSPR(31,339,953), XSPR_MASK, PPC750,    {RT}},
3940 {"mfsgr",       XSPR(31,339,953), XSPR_MASK, PPC403,    {RT}},
3941 {"mfdcwr",      XSPR(31,339,954), XSPR_MASK, PPC403,    {RT}},
3942 {"mfpmc2",      XSPR(31,339,954), XSPR_MASK, PPC750,    {RT}},
3943 {"mfsia",       XSPR(31,339,955), XSPR_MASK, PPC750,    {RT}},
3944 {"mfsler",      XSPR(31,339,955), XSPR_MASK, PPC405,    {RT}},
3945 {"mfmmcr1",     XSPR(31,339,956), XSPR_MASK, PPC750,    {RT}},
3946 {"mfsu0r",      XSPR(31,339,956), XSPR_MASK, PPC405,    {RT}},
3947 {"mfdbcr1",     XSPR(31,339,957), XSPR_MASK, PPC405,    {RT}},
3948 {"mfpmc3",      XSPR(31,339,957), XSPR_MASK, PPC750,    {RT}},
3949 {"mfpmc4",      XSPR(31,339,958), XSPR_MASK, PPC750,    {RT}},
3950 {"mficdbdr",    XSPR(31,339,979), XSPR_MASK, PPC403,    {RT}},
3951 {"mfesr",       XSPR(31,339,980), XSPR_MASK, PPC403,    {RT}},
3952 {"mfdear",      XSPR(31,339,981), XSPR_MASK, PPC403,    {RT}},
3953 {"mfevpr",      XSPR(31,339,982), XSPR_MASK, PPC403,    {RT}},
3954 {"mfcdbcr",     XSPR(31,339,983), XSPR_MASK, PPC403,    {RT}},
3955 {"mftsr",       XSPR(31,339,984), XSPR_MASK, PPC403,    {RT}},
3956 {"mftcr",       XSPR(31,339,986), XSPR_MASK, PPC403,    {RT}},
3957 {"mfpit",       XSPR(31,339,987), XSPR_MASK, PPC403,    {RT}},
3958 {"mftbhi",      XSPR(31,339,988), XSPR_MASK, PPC403,    {RT}},
3959 {"mftblo",      XSPR(31,339,989), XSPR_MASK, PPC403,    {RT}},
3960 {"mfsrr2",      XSPR(31,339,990), XSPR_MASK, PPC403,    {RT}},
3961 {"mfsrr3",      XSPR(31,339,991), XSPR_MASK, PPC403,    {RT}},
3962 {"mfdbsr",      XSPR(31,339,1008), XSPR_MASK, PPC403,   {RT}},
3963 {"mfdbcr0",     XSPR(31,339,1010), XSPR_MASK, PPC405,   {RT}},
3964 {"mfiac1",      XSPR(31,339,1012), XSPR_MASK, PPC403,   {RT}},
3965 {"mfiac2",      XSPR(31,339,1013), XSPR_MASK, PPC403,   {RT}},
3966 {"mfdac1",      XSPR(31,339,1014), XSPR_MASK, PPC403,   {RT}},
3967 {"mfdac2",      XSPR(31,339,1015), XSPR_MASK, PPC403,   {RT}},
3968 {"mfl2cr",      XSPR(31,339,1017), XSPR_MASK, PPC750,   {RT}},
3969 {"mfdccr",      XSPR(31,339,1018), XSPR_MASK, PPC403,   {RT}},
3970 {"mficcr",      XSPR(31,339,1019), XSPR_MASK, PPC403,   {RT}},
3971 {"mfictc",      XSPR(31,339,1019), XSPR_MASK, PPC750,   {RT}},
3972 {"mfpbl1",      XSPR(31,339,1020), XSPR_MASK, PPC403,   {RT}},
3973 {"mfthrm1",     XSPR(31,339,1020), XSPR_MASK, PPC750,   {RT}},
3974 {"mfpbu1",      XSPR(31,339,1021), XSPR_MASK, PPC403,   {RT}},
3975 {"mfthrm2",     XSPR(31,339,1021), XSPR_MASK, PPC750,   {RT}},
3976 {"mfpbl2",      XSPR(31,339,1022), XSPR_MASK, PPC403,   {RT}},
3977 {"mfthrm3",     XSPR(31,339,1022), XSPR_MASK, PPC750,   {RT}},
3978 {"mfpbu2",      XSPR(31,339,1023), XSPR_MASK, PPC403,   {RT}},
3979 {"mfspr",       X(31,339),      X_MASK,      COM,       {RT, SPR}},
3980
3981 {"lwax",        X(31,341),      X_MASK,      PPC64,     {RT, RA0, RB}},
3982
3983 {"dst",         XDSS(31,342,0), XDSS_MASK,   PPCVEC,    {RA, RB, STRM}},
3984
3985 {"lhax",        X(31,343),      X_MASK,      COM,       {RT, RA0, RB}},
3986
3987 {"lhaxe",       X(31,351),      X_MASK,      BOOKE64,   {RT, RA0, RB}},
3988
3989 {"lvxl",        X(31,359),      X_MASK,      PPCVEC,    {VD, RA, RB}},
3990
3991 {"abs",         XO(31,360,0,0), XORB_MASK,   M601,      {RT, RA}},
3992 {"abs.",        XO(31,360,0,1), XORB_MASK,   M601,      {RT, RA}},
3993
3994 {"divs",        XO(31,363,0,0), XO_MASK,     M601,      {RT, RA, RB}},
3995 {"divs.",       XO(31,363,0,1), XO_MASK,     M601,      {RT, RA, RB}},
3996
3997 {"tlbia",       X(31,370),      0xffffffff,  PPC,       {0}},
3998
3999 {"mftbl",       XSPR(31,371,268), XSPR_MASK, CLASSIC,   {RT}},
4000 {"mftbu",       XSPR(31,371,269), XSPR_MASK, CLASSIC,   {RT}},
4001 {"mftb",        X(31,371),      X_MASK,      CLASSIC,   {RT, TBR}},
4002
4003 {"lwaux",       X(31,373),      X_MASK,      PPC64,     {RT, RAL, RB}},
4004
4005 {"dstst",       XDSS(31,374,0), XDSS_MASK,   PPCVEC,    {RA, RB, STRM}},
4006
4007 {"lhaux",       X(31,375),      X_MASK,      COM,       {RT, RAL, RB}},
4008
4009 {"lhauxe",      X(31,383),      X_MASK,      BOOKE64,   {RT, RAL, RB}},
4010
4011 {"mtdcrx",      X(31,387),      X_MASK,      BOOKE,     {RA, RS}},
4012
4013 {"dcblc",       X(31,390),      X_MASK,      PPCCHLK,   {CT, RA, RB}},
4014 {"stdfcmx",     APU(31,391,0),  APU_MASK,    PPC405,    {FCRT, RA, RB}},
4015
4016 {"subfe64",     XO(31,392,0,0), XO_MASK,     BOOKE64,   {RT, RA, RB}},
4017
4018 {"adde64",      XO(31,394,0,0), XO_MASK,     BOOKE64,   {RT, RA, RB}},
4019
4020 {"dcblce",      X(31,398),      X_MASK,      PPCCHLK64, {CT, RA, RB}},
4021
4022 {"slbmte",      X(31,402),      XRA_MASK,    PPC64,     {RS, RB}},
4023
4024 {"sthx",        X(31,407),      X_MASK,      COM,       {RS, RA0, RB}},
4025
4026 {"orc",         XRC(31,412,0),  X_MASK,      COM,       {RA, RS, RB}},
4027 {"orc.",        XRC(31,412,1),  X_MASK,      COM,       {RA, RS, RB}},
4028
4029 {"sthxe",       X(31,415),      X_MASK,      BOOKE64,   {RS, RA0, RB}},
4030 {"sthepx",      X(31,415),      X_MASK,      E500MC,    {RS, RA, RB}},
4031
4032 {"mtdcrux",     X(31,419),      X_MASK,      PPC464,    {RA, RS}},
4033
4034 {"slbie",       X(31,434),      XRTRA_MASK,  PPC64,     {RB}},
4035
4036 {"ecowx",       X(31,438),      X_MASK,      PPC,       {RT, RA, RB}},
4037
4038 {"sthux",       X(31,439),      X_MASK,      COM,       {RS, RAS, RB}},
4039
4040 {"mdors",       0x7f9ce378,     0xffffffff,  E500MC,    {0}},
4041
4042 {"mr",          XRC(31,444,0),  X_MASK,      COM,       {RA, RS, RBS}},
4043 {"or",          XRC(31,444,0),  X_MASK,      COM,       {RA, RS, RB}},
4044 {"mr.",         XRC(31,444,1),  X_MASK,      COM,       {RA, RS, RBS}},
4045 {"or.",         XRC(31,444,1),  X_MASK,      COM,       {RA, RS, RB}},
4046
4047 {"sthuxe",      X(31,447),      X_MASK,      BOOKE64,   {RS, RAS, RB}},
4048
4049 {"mtexisr",     XSPR(31,451, 64), XSPR_MASK, PPC403,    {RS}},
4050 {"mtexier",     XSPR(31,451, 66), XSPR_MASK, PPC403,    {RS}},
4051 {"mtbr0",       XSPR(31,451,128), XSPR_MASK, PPC403,    {RS}},
4052 {"mtbr1",       XSPR(31,451,129), XSPR_MASK, PPC403,    {RS}},
4053 {"mtbr2",       XSPR(31,451,130), XSPR_MASK, PPC403,    {RS}},
4054 {"mtbr3",       XSPR(31,451,131), XSPR_MASK, PPC403,    {RS}},
4055 {"mtbr4",       XSPR(31,451,132), XSPR_MASK, PPC403,    {RS}},
4056 {"mtbr5",       XSPR(31,451,133), XSPR_MASK, PPC403,    {RS}},
4057 {"mtbr6",       XSPR(31,451,134), XSPR_MASK, PPC403,    {RS}},
4058 {"mtbr7",       XSPR(31,451,135), XSPR_MASK, PPC403,    {RS}},
4059 {"mtbear",      XSPR(31,451,144), XSPR_MASK, PPC403,    {RS}},
4060 {"mtbesr",      XSPR(31,451,145), XSPR_MASK, PPC403,    {RS}},
4061 {"mtiocr",      XSPR(31,451,160), XSPR_MASK, PPC403,    {RS}},
4062 {"mtdmacr0",    XSPR(31,451,192), XSPR_MASK, PPC403,    {RS}},
4063 {"mtdmact0",    XSPR(31,451,193), XSPR_MASK, PPC403,    {RS}},
4064 {"mtdmada0",    XSPR(31,451,194), XSPR_MASK, PPC403,    {RS}},
4065 {"mtdmasa0",    XSPR(31,451,195), XSPR_MASK, PPC403,    {RS}},
4066 {"mtdmacc0",    XSPR(31,451,196), XSPR_MASK, PPC403,    {RS}},
4067 {"mtdmacr1",    XSPR(31,451,200), XSPR_MASK, PPC403,    {RS}},
4068 {"mtdmact1",    XSPR(31,451,201), XSPR_MASK, PPC403,    {RS}},
4069 {"mtdmada1",    XSPR(31,451,202), XSPR_MASK, PPC403,    {RS}},
4070 {"mtdmasa1",    XSPR(31,451,203), XSPR_MASK, PPC403,    {RS}},
4071 {"mtdmacc1",    XSPR(31,451,204), XSPR_MASK, PPC403,    {RS}},
4072 {"mtdmacr2",    XSPR(31,451,208), XSPR_MASK, PPC403,    {RS}},
4073 {"mtdmact2",    XSPR(31,451,209), XSPR_MASK, PPC403,    {RS}},
4074 {"mtdmada2",    XSPR(31,451,210), XSPR_MASK, PPC403,    {RS}},
4075 {"mtdmasa2",    XSPR(31,451,211), XSPR_MASK, PPC403,    {RS}},
4076 {"mtdmacc2",    XSPR(31,451,212), XSPR_MASK, PPC403,    {RS}},
4077 {"mtdmacr3",    XSPR(31,451,216), XSPR_MASK, PPC403,    {RS}},
4078 {"mtdmact3",    XSPR(31,451,217), XSPR_MASK, PPC403,    {RS}},
4079 {"mtdmada3",    XSPR(31,451,218), XSPR_MASK, PPC403,    {RS}},
4080 {"mtdmasa3",    XSPR(31,451,219), XSPR_MASK, PPC403,    {RS}},
4081 {"mtdmacc3",    XSPR(31,451,220), XSPR_MASK, PPC403,    {RS}},
4082 {"mtdmasr",     XSPR(31,451,224), XSPR_MASK, PPC403,    {RS}},
4083 {"mtdcr",       X(31,451),      X_MASK,   PPC403|BOOKE, {SPR, RS}},
4084
4085 {"dccci",       X(31,454),     XRT_MASK, PPC403|PPC440, {RA, RB}},
4086
4087 {"subfze64",    XO(31,456,0,0), XORB_MASK,   BOOKE64,   {RT, RA}},
4088
4089 {"divdu",       XO(31,457,0,0), XO_MASK,     PPC64,     {RT, RA, RB}},
4090 {"divdu.",      XO(31,457,0,1), XO_MASK,     PPC64,     {RT, RA, RB}},
4091
4092 {"addze64",     XO(31,458,0,0), XORB_MASK,   BOOKE64,   {RT, RA}},
4093
4094 {"divwu",       XO(31,459,0,0), XO_MASK,     PPC,       {RT, RA, RB}},
4095 {"divwu.",      XO(31,459,0,1), XO_MASK,     PPC,       {RT, RA, RB}},
4096
4097 {"mtpmr",       X(31,462),      X_MASK, PPCPMR|PPCE300, {PMR, RS}},
4098
4099 {"mtmq",        XSPR(31,467,  0), XSPR_MASK, M601,      {RS}},
4100 {"mtxer",       XSPR(31,467,  1), XSPR_MASK, COM,       {RS}},
4101 {"mtlr",        XSPR(31,467,  8), XSPR_MASK, COM,       {RS}},
4102 {"mtctr",       XSPR(31,467,  9), XSPR_MASK, COM,       {RS}},
4103 {"mttid",       XSPR(31,467, 17), XSPR_MASK, POWER,     {RS}},
4104 {"mtdsisr",     XSPR(31,467, 18), XSPR_MASK, COM,       {RS}},
4105 {"mtdar",       XSPR(31,467, 19), XSPR_MASK, COM,       {RS}},
4106 {"mtrtcu",      XSPR(31,467, 20), XSPR_MASK, COM,       {RS}},
4107 {"mtrtcl",      XSPR(31,467, 21), XSPR_MASK, COM,       {RS}},
4108 {"mtdec",       XSPR(31,467, 22), XSPR_MASK, COM,       {RS}},
4109 {"mtsdr0",      XSPR(31,467, 24), XSPR_MASK, POWER,     {RS}},
4110 {"mtsdr1",      XSPR(31,467, 25), XSPR_MASK, COM,       {RS}},
4111 {"mtsrr0",      XSPR(31,467, 26), XSPR_MASK, COM,       {RS}},
4112 {"mtsrr1",      XSPR(31,467, 27), XSPR_MASK, COM,       {RS}},
4113 {"mtcfar",      XSPR(31,467, 28), XSPR_MASK, POWER6,    {RS}},
4114 {"mtpid",       XSPR(31,467, 48), XSPR_MASK, BOOKE,     {RS}},
4115 {"mtdecar",     XSPR(31,467, 54), XSPR_MASK, BOOKE,     {RS}},
4116 {"mtcsrr0",     XSPR(31,467, 58), XSPR_MASK, BOOKE,     {RS}},
4117 {"mtcsrr1",     XSPR(31,467, 59), XSPR_MASK, BOOKE,     {RS}},
4118 {"mtdear",      XSPR(31,467, 61), XSPR_MASK, BOOKE,     {RS}},
4119 {"mtesr",       XSPR(31,467, 62), XSPR_MASK, BOOKE,     {RS}},
4120 {"mtivpr",      XSPR(31,467, 63), XSPR_MASK, BOOKE,     {RS}},
4121 {"mtcmpa",      XSPR(31,467,144), XSPR_MASK, PPC860,    {RS}},
4122 {"mtcmpb",      XSPR(31,467,145), XSPR_MASK, PPC860,    {RS}},
4123 {"mtcmpc",      XSPR(31,467,146), XSPR_MASK, PPC860,    {RS}},
4124 {"mtcmpd",      XSPR(31,467,147), XSPR_MASK, PPC860,    {RS}},
4125 {"mticr",       XSPR(31,467,148), XSPR_MASK, PPC860,    {RS}},
4126 {"mtder",       XSPR(31,467,149), XSPR_MASK, PPC860,    {RS}},
4127 {"mtcounta",    XSPR(31,467,150), XSPR_MASK, PPC860,    {RS}},
4128 {"mtcountb",    XSPR(31,467,151), XSPR_MASK, PPC860,    {RS}},
4129 {"mtcmpe",      XSPR(31,467,152), XSPR_MASK, PPC860,    {RS}},
4130 {"mtcmpf",      XSPR(31,467,153), XSPR_MASK, PPC860,    {RS}},
4131 {"mtcmpg",      XSPR(31,467,154), XSPR_MASK, PPC860,    {RS}},
4132 {"mtcmph",      XSPR(31,467,155), XSPR_MASK, PPC860,    {RS}},
4133 {"mtlctrl1",    XSPR(31,467,156), XSPR_MASK, PPC860,    {RS}},
4134 {"mtlctrl2",    XSPR(31,467,157), XSPR_MASK, PPC860,    {RS}},
4135 {"mtictrl",     XSPR(31,467,158), XSPR_MASK, PPC860,    {RS}},
4136 {"mtbar",       XSPR(31,467,159), XSPR_MASK, PPC860,    {RS}},
4137 {"mtvrsave",    XSPR(31,467,256), XSPR_MASK, PPCVEC,    {RS}},
4138 {"mtusprg0",    XSPR(31,467,256), XSPR_MASK, BOOKE,     {RS}},
4139 {"mtsprg",      XSPR(31,467,256), XSPRG_MASK,PPC,       {SPRG, RS}},
4140 {"mtsprg0",     XSPR(31,467,272), XSPR_MASK, PPC,       {RS}},
4141 {"mtsprg1",     XSPR(31,467,273), XSPR_MASK, PPC,       {RS}},
4142 {"mtsprg2",     XSPR(31,467,274), XSPR_MASK, PPC,       {RS}},
4143 {"mtsprg3",     XSPR(31,467,275), XSPR_MASK, PPC,       {RS}},
4144 {"mtsprg4",     XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, {RS}},
4145 {"mtsprg5",     XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, {RS}},
4146 {"mtsprg6",     XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, {RS}},
4147 {"mtsprg7",     XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, {RS}},
4148 {"mtasr",       XSPR(31,467,280), XSPR_MASK, PPC64,     {RS}},
4149 {"mtear",       XSPR(31,467,282), XSPR_MASK, PPC,       {RS}},
4150 {"mttbl",       XSPR(31,467,284), XSPR_MASK, PPC,       {RS}},
4151 {"mttbu",       XSPR(31,467,285), XSPR_MASK, PPC,       {RS}},
4152 {"mtdbsr",      XSPR(31,467,304), XSPR_MASK, BOOKE,     {RS}},
4153 {"mtdbcr0",     XSPR(31,467,308), XSPR_MASK, BOOKE,     {RS}},
4154 {"mtdbcr1",     XSPR(31,467,309), XSPR_MASK, BOOKE,     {RS}},
4155 {"mtdbcr2",     XSPR(31,467,310), XSPR_MASK, BOOKE,     {RS}},
4156 {"mtiac1",      XSPR(31,467,312), XSPR_MASK, BOOKE,     {RS}},
4157 {"mtiac2",      XSPR(31,467,313), XSPR_MASK, BOOKE,     {RS}},
4158 {"mtiac3",      XSPR(31,467,314), XSPR_MASK, BOOKE,     {RS}},
4159 {"mtiac4",      XSPR(31,467,315), XSPR_MASK, BOOKE,     {RS}},
4160 {"mtdac1",      XSPR(31,467,316), XSPR_MASK, BOOKE,     {RS}},
4161 {"mtdac2",      XSPR(31,467,317), XSPR_MASK, BOOKE,     {RS}},
4162 {"mtdvc1",      XSPR(31,467,318), XSPR_MASK, BOOKE,     {RS}},
4163 {"mtdvc2",      XSPR(31,467,319), XSPR_MASK, BOOKE,     {RS}},
4164 {"mttsr",       XSPR(31,467,336), XSPR_MASK, BOOKE,     {RS}},
4165 {"mttcr",       XSPR(31,467,340), XSPR_MASK, BOOKE,     {RS}},
4166 {"mtivor0",     XSPR(31,467,400), XSPR_MASK, BOOKE,     {RS}},
4167 {"mtivor1",     XSPR(31,467,401), XSPR_MASK, BOOKE,     {RS}},
4168 {"mtivor2",     XSPR(31,467,402), XSPR_MASK, BOOKE,     {RS}},
4169 {"mtivor3",     XSPR(31,467,403), XSPR_MASK, BOOKE,     {RS}},
4170 {"mtivor4",     XSPR(31,467,404), XSPR_MASK, BOOKE,     {RS}},
4171 {"mtivor5",     XSPR(31,467,405), XSPR_MASK, BOOKE,     {RS}},
4172 {"mtivor6",     XSPR(31,467,406), XSPR_MASK, BOOKE,     {RS}},
4173 {"mtivor7",     XSPR(31,467,407), XSPR_MASK, BOOKE,     {RS}},
4174 {"mtivor8",     XSPR(31,467,408), XSPR_MASK, BOOKE,     {RS}},
4175 {"mtivor9",     XSPR(31,467,409), XSPR_MASK, BOOKE,     {RS}},
4176 {"mtivor10",    XSPR(31,467,410), XSPR_MASK, BOOKE,     {RS}},
4177 {"mtivor11",    XSPR(31,467,411), XSPR_MASK, BOOKE,     {RS}},
4178 {"mtivor12",    XSPR(31,467,412), XSPR_MASK, BOOKE,     {RS}},
4179 {"mtivor13",    XSPR(31,467,413), XSPR_MASK, BOOKE,     {RS}},
4180 {"mtivor14",    XSPR(31,467,414), XSPR_MASK, BOOKE,     {RS}},
4181 {"mtivor15",    XSPR(31,467,415), XSPR_MASK, BOOKE,     {RS}},
4182 {"mtspefscr",   XSPR(31,467,512), XSPR_MASK, PPCSPE,    {RS}},
4183 {"mtbbear",     XSPR(31,467,513), XSPR_MASK, PPCBRLK,   {RS}},
4184 {"mtbbtar",     XSPR(31,467,514), XSPR_MASK, PPCBRLK,   {RS}},
4185 {"mtivor32",    XSPR(31,467,528), XSPR_MASK, PPCSPE,    {RS}},
4186 {"mtibatu",     XSPR(31,467,528), XSPRBAT_MASK, PPC,    {SPRBAT, RS}},
4187 {"mtivor33",    XSPR(31,467,529), XSPR_MASK, PPCSPE,    {RS}},
4188 {"mtibatl",     XSPR(31,467,529), XSPRBAT_MASK, PPC,    {SPRBAT, RS}},
4189 {"mtivor34",    XSPR(31,467,530), XSPR_MASK, PPCSPE,    {RS}},
4190 {"mtivor35",    XSPR(31,467,531), XSPR_MASK, PPCPMR,    {RS}},
4191 {"mtdbatu",     XSPR(31,467,536), XSPRBAT_MASK, PPC,    {SPRBAT, RS}},
4192 {"mtdbatl",     XSPR(31,467,537), XSPRBAT_MASK, PPC,    {SPRBAT, RS}},
4193 {"mtmcsrr0",    XSPR(31,467,570), XSPR_MASK, PPCRFMCI,  {RS}},
4194 {"mtmcsrr1",    XSPR(31,467,571), XSPR_MASK, PPCRFMCI,  {RS}},
4195 {"mtmcsr",      XSPR(31,467,572), XSPR_MASK, PPCRFMCI,  {RS}},
4196 {"mtummcr0",    XSPR(31,467,936), XSPR_MASK, PPC750,    {RS}},
4197 {"mtupmc1",     XSPR(31,467,937), XSPR_MASK, PPC750,    {RS}},
4198 {"mtupmc2",     XSPR(31,467,938), XSPR_MASK, PPC750,    {RS}},
4199 {"mtusia",      XSPR(31,467,939), XSPR_MASK, PPC750,    {RS}},
4200 {"mtummcr1",    XSPR(31,467,940), XSPR_MASK, PPC750,    {RS}},
4201 {"mtupmc3",     XSPR(31,467,941), XSPR_MASK, PPC750,    {RS}},
4202 {"mtupmc4",     XSPR(31,467,942), XSPR_MASK, PPC750,    {RS}},
4203 {"mtzpr",       XSPR(31,467,944), XSPR_MASK, PPC403,    {RS}},
4204 {"mtpid",       XSPR(31,467,945), XSPR_MASK, PPC403,    {RS}},
4205 {"mtccr0",      XSPR(31,467,947), XSPR_MASK, PPC405,    {RS}},
4206 {"mtiac3",      XSPR(31,467,948), XSPR_MASK, PPC405,    {RS}},
4207 {"mtiac4",      XSPR(31,467,949), XSPR_MASK, PPC405,    {RS}},
4208 {"mtdvc1",      XSPR(31,467,950), XSPR_MASK, PPC405,    {RS}},
4209 {"mtdvc2",      XSPR(31,467,951), XSPR_MASK, PPC405,    {RS}},
4210 {"mtmmcr0",     XSPR(31,467,952), XSPR_MASK, PPC750,    {RS}},
4211 {"mtpmc1",      XSPR(31,467,953), XSPR_MASK, PPC750,    {RS}},
4212 {"mtsgr",       XSPR(31,467,953), XSPR_MASK, PPC403,    {RS}},
4213 {"mtdcwr",      XSPR(31,467,954), XSPR_MASK, PPC403,    {RS}},
4214 {"mtpmc2",      XSPR(31,467,954), XSPR_MASK, PPC750,    {RS}},
4215 {"mtsia",       XSPR(31,467,955), XSPR_MASK, PPC750,    {RS}},
4216 {"mtsler",      XSPR(31,467,955), XSPR_MASK, PPC405,    {RS}},
4217 {"mtmmcr1",     XSPR(31,467,956), XSPR_MASK, PPC750,    {RS}},
4218 {"mtsu0r",      XSPR(31,467,956), XSPR_MASK, PPC405,    {RS}},
4219 {"mtdbcr1",     XSPR(31,467,957), XSPR_MASK, PPC405,    {RS}},
4220 {"mtpmc3",      XSPR(31,467,957), XSPR_MASK, PPC750,    {RS}},
4221 {"mtpmc4",      XSPR(31,467,958), XSPR_MASK, PPC750,    {RS}},
4222 {"mticdbdr",    XSPR(31,467,979), XSPR_MASK, PPC403,    {RS}},
4223 {"mtesr",       XSPR(31,467,980), XSPR_MASK, PPC403,    {RS}},
4224 {"mtdear",      XSPR(31,467,981), XSPR_MASK, PPC403,    {RS}},
4225 {"mtevpr",      XSPR(31,467,982), XSPR_MASK, PPC403,    {RS}},
4226 {"mtcdbcr",     XSPR(31,467,983), XSPR_MASK, PPC403,    {RS}},
4227 {"mttsr",       XSPR(31,467,984), XSPR_MASK, PPC403,    {RS}},
4228 {"mttcr",       XSPR(31,467,986), XSPR_MASK, PPC403,    {RS}},
4229 {"mtpit",       XSPR(31,467,987), XSPR_MASK, PPC403,    {RS}},
4230 {"mttbhi",      XSPR(31,467,988), XSPR_MASK, PPC403,    {RS}},
4231 {"mttblo",      XSPR(31,467,989), XSPR_MASK, PPC403,    {RS}},
4232 {"mtsrr2",      XSPR(31,467,990), XSPR_MASK, PPC403,    {RS}},
4233 {"mtsrr3",      XSPR(31,467,991), XSPR_MASK, PPC403,    {RS}},
4234 {"mtdbsr",      XSPR(31,467,1008), XSPR_MASK, PPC403,   {RS}},
4235 {"mtdbcr0",     XSPR(31,467,1010), XSPR_MASK, PPC405,   {RS}},
4236 {"mtiac1",      XSPR(31,467,1012), XSPR_MASK, PPC403,   {RS}},
4237 {"mtiac2",      XSPR(31,467,1013), XSPR_MASK, PPC403,   {RS}},
4238 {"mtdac1",      XSPR(31,467,1014), XSPR_MASK, PPC403,   {RS}},
4239 {"mtdac2",      XSPR(31,467,1015), XSPR_MASK, PPC403,   {RS}},
4240 {"mtl2cr",      XSPR(31,467,1017), XSPR_MASK, PPC750,   {RS}},
4241 {"mtdccr",      XSPR(31,467,1018), XSPR_MASK, PPC403,   {RS}},
4242 {"mticcr",      XSPR(31,467,1019), XSPR_MASK, PPC403,   {RS}},
4243 {"mtictc",      XSPR(31,467,1019), XSPR_MASK, PPC750,   {RS}},
4244 {"mtpbl1",      XSPR(31,467,1020), XSPR_MASK, PPC403,   {RS}},
4245 {"mtthrm1",     XSPR(31,467,1020), XSPR_MASK, PPC750,   {RS}},
4246 {"mtpbu1",      XSPR(31,467,1021), XSPR_MASK, PPC403,   {RS}},
4247 {"mtthrm2",     XSPR(31,467,1021), XSPR_MASK, PPC750,   {RS}},
4248 {"mtpbl2",      XSPR(31,467,1022), XSPR_MASK, PPC403,   {RS}},
4249 {"mtthrm3",     XSPR(31,467,1022), XSPR_MASK, PPC750,   {RS}},
4250 {"mtpbu2",      XSPR(31,467,1023), XSPR_MASK, PPC403,   {RS}},
4251 {"mtspr",       X(31,467),        X_MASK,    COM,       {SPR, RS}},
4252
4253 {"dcbi",        X(31,470),      XRT_MASK,    PPC,       {RA, RB}},
4254
4255 {"nand",        XRC(31,476,0),  X_MASK,      COM,       {RA, RS, RB}},
4256 {"nand.",       XRC(31,476,1),  X_MASK,      COM,       {RA, RS, RB}},
4257
4258 {"dcbie",       X(31,478),      XRT_MASK,    BOOKE64,   {RA, RB}},
4259
4260 {"dsn",         X(31,483),      XRT_MASK,    E500MC,    {RA, RB}},
4261
4262 {"dcread",      X(31,486),      X_MASK,  PPC403|PPC440, {RT, RA, RB}},
4263
4264 {"icbtls",      X(31,486),      X_MASK,      PPCCHLK,   {CT, RA, RB}},
4265
4266 {"stvxl",       X(31,487),      X_MASK,      PPCVEC,    {VS, RA, RB}},
4267
4268 {"nabs",        XO(31,488,0,0), XORB_MASK,   M601,      {RT, RA}},
4269 {"subfme64",    XO(31,488,0,0), XORB_MASK,   BOOKE64,   {RT, RA}},
4270 {"nabs.",       XO(31,488,0,1), XORB_MASK,   M601,      {RT, RA}},
4271
4272 {"divd",        XO(31,489,0,0), XO_MASK,     PPC64,     {RT, RA, RB}},
4273 {"divd.",       XO(31,489,0,1), XO_MASK,     PPC64,     {RT, RA, RB}},
4274
4275 {"addme64",     XO(31,490,0,0), XORB_MASK,   BOOKE64,   {RT, RA}},
4276
4277 {"divw",        XO(31,491,0,0), XO_MASK,     PPC,       {RT, RA, RB}},
4278 {"divw.",       XO(31,491,0,1), XO_MASK,     PPC,       {RT, RA, RB}},
4279
4280 {"icbtlse",     X(31,494),      X_MASK,      PPCCHLK64, {CT, RA, RB}},
4281
4282 {"slbia",       X(31,498),      0xffffffff,  PPC64,     {0}},
4283
4284 {"cli",         X(31,502),      XRB_MASK,    POWER,     {RT, RA}},
4285
4286 {"cmpb",        X(31,508),      X_MASK,      POWER6,    {RA, RS, RB}},
4287
4288 {"stdcxe.",     XRC(31,511,1),  X_MASK,      BOOKE64,   {RS, RA, RB}},
4289
4290 {"mcrxr",       X(31,512), XRARB_MASK|(3<<21), COM,     {BF}},
4291
4292 {"lbdx",        X(31,515),      X_MASK,      E500MC,    {RT, RA, RB}},
4293
4294 {"bblels",      X(31,518),      X_MASK,      PPCBRLK,   {0}},
4295
4296 {"lvlx",        X(31,519),      X_MASK,      CELL,      {VD, RA0, RB}},
4297 {"lbfcmux",     APU(31,519,0),  APU_MASK,    PPC405,    {FCRT, RA, RB}},
4298
4299 {"subfco",      XO(31,8,1,0),   XO_MASK,     PPCCOM,    {RT, RA, RB}},
4300 {"sfo",         XO(31,8,1,0),   XO_MASK,     PWRCOM,    {RT, RA, RB}},
4301 {"subco",       XO(31,8,1,0),   XO_MASK,     PPC,       {RT, RB, RA}},
4302 {"subfco.",     XO(31,8,1,1),   XO_MASK,     PPCCOM,    {RT, RA, RB}},
4303 {"sfo.",        XO(31,8,1,1),   XO_MASK,     PWRCOM,    {RT, RA, RB}},
4304 {"subco.",      XO(31,8,1,1),   XO_MASK,     PPC,       {RT, RB, RA}},
4305
4306 {"addco",       XO(31,10,1,0),  XO_MASK,     PPCCOM,    {RT, RA, RB}},
4307 {"ao",          XO(31,10,1,0),  XO_MASK,     PWRCOM,    {RT, RA, RB}},
4308 {"addco.",      XO(31,10,1,1),  XO_MASK,     PPCCOM,    {RT, RA, RB}},
4309 {"ao.",         XO(31,10,1,1),  XO_MASK,     PWRCOM,    {RT, RA, RB}},
4310
4311 {"clcs",        X(31,531),      XRB_MASK,    M601,      {RT, RA}},
4312
4313 {"ldbrx",       X(31,532),      X_MASK,      CELL,      {RT, RA0, RB}},
4314
4315 {"lswx",        X(31,533),      X_MASK,      PPCCOM,    {RT, RA0, RB}},
4316 {"lsx",         X(31,533),      X_MASK,      PWRCOM,    {RT, RA, RB}},
4317
4318 {"lwbrx",       X(31,534),      X_MASK,      PPCCOM,    {RT, RA0, RB}},
4319 {"lbrx",        X(31,534),      X_MASK,      PWRCOM,    {RT, RA, RB}},
4320
4321 {"lfsx",        X(31,535),      X_MASK,      COM,       {FRT, RA0, RB}},
4322
4323 {"srw",         XRC(31,536,0),  X_MASK,      PPCCOM,    {RA, RS, RB}},
4324 {"sr",          XRC(31,536,0),  X_MASK,      PWRCOM,    {RA, RS, RB}},
4325 {"srw.",        XRC(31,536,1),  X_MASK,      PPCCOM,    {RA, RS, RB}},
4326 {"sr.",         XRC(31,536,1),  X_MASK,      PWRCOM,    {RA, RS, RB}},
4327
4328 {"rrib",        XRC(31,537,0),  X_MASK,      M601,      {RA, RS, RB}},
4329 {"rrib.",       XRC(31,537,1),  X_MASK,      M601,      {RA, RS, RB}},
4330
4331 {"srd",         XRC(31,539,0),  X_MASK,      PPC64,     {RA, RS, RB}},
4332 {"srd.",        XRC(31,539,1),  X_MASK,      PPC64,     {RA, RS, RB}},
4333
4334 {"maskir",      XRC(31,541,0),  X_MASK,      M601,      {RA, RS, RB}},
4335 {"maskir.",     XRC(31,541,1),  X_MASK,      M601,      {RA, RS, RB}},
4336
4337 {"lwbrxe",      X(31,542),      X_MASK,      BOOKE64,   {RT, RA0, RB}},
4338
4339 {"lfsxe",       X(31,543),      X_MASK,      BOOKE64,   {FRT, RA0, RB}},
4340
4341 {"mcrxr64",     X(31,544), XRARB_MASK|(3<<21), BOOKE64, {BF}},
4342
4343 {"lhdx",        X(31,547),      X_MASK,      E500MC,    {RT, RA, RB}},
4344
4345 {"bbelr",       X(31,550),      X_MASK,      PPCBRLK,   {0}},
4346
4347 {"lvrx",        X(31,551),      X_MASK,      CELL,      {VD, RA0, RB}},
4348 {"lhfcmux",     APU(31,551,0),  APU_MASK,    PPC405,    {FCRT, RA, RB}},
4349
4350 {"subfo",       XO(31,40,1,0),  XO_MASK,     PPC,       {RT, RA, RB}},
4351 {"subo",        XO(31,40,1,0),  XO_MASK,     PPC,       {RT, RB, RA}},
4352 {"subfo.",      XO(31,40,1,1),  XO_MASK,     PPC,       {RT, RA, RB}},
4353 {"subo.",       XO(31,40,1,1),  XO_MASK,     PPC,       {RT, RB, RA}},
4354
4355 {"tlbsync",     X(31,566),      0xffffffff,  PPC,       {0}},
4356
4357 {"lfsux",       X(31,567),      X_MASK,      COM,       {FRT, RAS, RB}},
4358
4359 {"lfsuxe",      X(31,575),      X_MASK,      BOOKE64,   {FRT, RAS, RB}},
4360
4361 {"lwdx",        X(31,579),      X_MASK,      E500MC,    {RT, RA, RB}},
4362
4363 {"lwfcmux",     APU(31,583,0),  APU_MASK,    PPC405,    {FCRT, RA, RB}},
4364
4365 {"mfsr",        X(31,595), XRB_MASK|(1<<20), COM32,     {RT, SR}},
4366
4367 {"lswi",        X(31,597),      X_MASK,      PPCCOM,    {RT, RA0, NB}},
4368 {"lsi",         X(31,597),      X_MASK,      PWRCOM,    {RT, RA0, NB}},
4369
4370 {"msync",       X(31,598),      0xffffffff,  BOOKE,     {0}},
4371 {"lwsync",      XSYNC(31,598,1), 0xffffffff, PPC,       {0}},
4372 {"ptesync",     XSYNC(31,598,2), 0xffffffff, PPC64,     {0}},
4373 {"sync",        X(31,598),      XSYNC_MASK,  PPCCOM,    {LS}},
4374 {"dcs",         X(31,598),      0xffffffff,  PWRCOM,    {0}},
4375
4376 {"lfdx",        X(31,599),      X_MASK,      COM,       {FRT, RA0, RB}},
4377
4378 {"lfdxe",       X(31,607),      X_MASK,      BOOKE64,   {FRT, RA0, RB}},
4379 {"lfdepx",      X(31,607),      X_MASK,      E500MC,    {RT, RA, RB}},
4380 {"mffgpr",      XRC(31,607,0),  XRA_MASK,    POWER6,    {FRT, RB}},
4381
4382 {"lddx",        X(31,611),      X_MASK,      E500MC,    {RT, RA, RB}},
4383
4384 {"lqfcmux",     APU(31,615,0),  APU_MASK,    PPC405,    {FCRT, RA, RB}},
4385
4386 {"nego",        XO(31,104,1,0), XORB_MASK,   COM,       {RT, RA}},
4387 {"nego.",       XO(31,104,1,1), XORB_MASK,   COM,       {RT, RA}},
4388
4389 {"mulo",        XO(31,107,1,0), XO_MASK,     M601,      {RT, RA, RB}},
4390 {"mulo.",       XO(31,107,1,1), XO_MASK,     M601,      {RT, RA, RB}},
4391
4392 {"mfsri",       X(31,627),      X_MASK,      PWRCOM,    {RT, RA, RB}},
4393
4394 {"dclst",       X(31,630),      XRB_MASK,    PWRCOM,    {RS, RA}},
4395
4396 {"lfdux",       X(31,631),      X_MASK,      COM,       {FRT, RAS, RB}},
4397
4398 {"lfduxe",      X(31,639),      X_MASK,      BOOKE64,   {FRT, RAS, RB}},
4399
4400 {"stbdx",       X(31,643),      X_MASK,      E500MC,    {RS, RA, RB}},
4401
4402 {"stvlx",       X(31,647),      X_MASK,      CELL,      {VS, RA0, RB}},
4403 {"stbfcmux",    APU(31,647,0),  APU_MASK,    PPC405,    {FCRT, RA, RB}},
4404
4405 {"subfeo",      XO(31,136,1,0), XO_MASK,     PPCCOM,    {RT, RA, RB}},
4406 {"sfeo",        XO(31,136,1,0), XO_MASK,     PWRCOM,    {RT, RA, RB}},
4407 {"subfeo.",     XO(31,136,1,1), XO_MASK,     PPCCOM,    {RT, RA, RB}},
4408 {"sfeo.",       XO(31,136,1,1), XO_MASK,     PWRCOM,    {RT, RA, RB}},
4409
4410 {"addeo",       XO(31,138,1,0), XO_MASK,     PPCCOM,    {RT, RA, RB}},
4411 {"aeo",         XO(31,138,1,0), XO_MASK,     PWRCOM,    {RT, RA, RB}},
4412 {"addeo.",      XO(31,138,1,1), XO_MASK,     PPCCOM,    {RT, RA, RB}},
4413 {"aeo.",        XO(31,138,1,1), XO_MASK,     PWRCOM,    {RT, RA, RB}},
4414
4415 {"mfsrin",      X(31,659),      XRA_MASK,    PPC32,     {RT, RB}},
4416
4417 {"stdbrx",      X(31,660),      X_MASK,      CELL,      {RS, RA0, RB}},
4418
4419 {"stswx",       X(31,661),      X_MASK,      PPCCOM,    {RS, RA0, RB}},
4420 {"stsx",        X(31,661),      X_MASK,      PWRCOM,    {RS, RA0, RB}},
4421
4422 {"stwbrx",      X(31,662),      X_MASK,      PPCCOM,    {RS, RA0, RB}},
4423 {"stbrx",       X(31,662),      X_MASK,      PWRCOM,    {RS, RA0, RB}},
4424
4425 {"stfsx",       X(31,663),      X_MASK,      COM,       {FRS, RA0, RB}},
4426
4427 {"srq",         XRC(31,664,0),  X_MASK,      M601,      {RA, RS, RB}},
4428 {"srq.",        XRC(31,664,1),  X_MASK,      M601,      {RA, RS, RB}},
4429
4430 {"sre",         XRC(31,665,0),  X_MASK,      M601,      {RA, RS, RB}},
4431 {"sre.",        XRC(31,665,1),  X_MASK,      M601,      {RA, RS, RB}},
4432
4433 {"stwbrxe",     X(31,670),      X_MASK,      BOOKE64,   {RS, RA0, RB}},
4434
4435 {"stfsxe",      X(31,671),      X_MASK,      BOOKE64,   {FRS, RA0, RB}},
4436
4437 {"sthdx",       X(31,675),      X_MASK,      E500MC,    {RS, RA, RB}},
4438
4439 {"stvrx",       X(31,679),      X_MASK,      CELL,      {VS, RA0, RB}},
4440 {"sthfcmux",    APU(31,679,0),  APU_MASK,    PPC405,    {FCRT, RA, RB}},
4441
4442 {"stfsux",      X(31,695),      X_MASK,      COM,       {FRS, RAS, RB}},
4443
4444 {"sriq",        XRC(31,696,0),  X_MASK,      M601,      {RA, RS, SH}},
4445 {"sriq.",       XRC(31,696,1),  X_MASK,      M601,      {RA, RS, SH}},
4446
4447 {"stfsuxe",     X(31,703),      X_MASK,      BOOKE64,   {FRS, RAS, RB}},
4448
4449 {"stwdx",       X(31,707),      X_MASK,      E500MC,    {RS, RA, RB}},
4450
4451 {"stwfcmux",    APU(31,711,0),  APU_MASK,    PPC405,    {FCRT, RA, RB}},
4452
4453 {"subfzeo",     XO(31,200,1,0), XORB_MASK,   PPCCOM,    {RT, RA}},
4454 {"sfzeo",       XO(31,200,1,0), XORB_MASK,   PWRCOM,    {RT, RA}},
4455 {"subfzeo.",    XO(31,200,1,1), XORB_MASK,   PPCCOM,    {RT, RA}},
4456 {"sfzeo.",      XO(31,200,1,1), XORB_MASK,   PWRCOM,    {RT, RA}},
4457
4458 {"addzeo",      XO(31,202,1,0), XORB_MASK,   PPCCOM,    {RT, RA}},
4459 {"azeo",        XO(31,202,1,0), XORB_MASK,   PWRCOM,    {RT, RA}},
4460 {"addzeo.",     XO(31,202,1,1), XORB_MASK,   PPCCOM,    {RT, RA}},
4461 {"azeo.",       XO(31,202,1,1), XORB_MASK,   PWRCOM,    {RT, RA}},
4462
4463 {"stswi",       X(31,725),      X_MASK,      PPCCOM,    {RS, RA0, NB}},
4464 {"stsi",        X(31,725),      X_MASK,      PWRCOM,    {RS, RA0, NB}},
4465
4466 {"stfdx",       X(31,727),      X_MASK,      COM,       {FRS, RA0, RB}},
4467
4468 {"srlq",        XRC(31,728,0),  X_MASK,      M601,      {RA, RS, RB}},
4469 {"srlq.",       XRC(31,728,1),  X_MASK,      M601,      {RA, RS, RB}},
4470
4471 {"sreq",        XRC(31,729,0),  X_MASK,      M601,      {RA, RS, RB}},
4472 {"sreq.",       XRC(31,729,1),  X_MASK,      M601,      {RA, RS, RB}},
4473
4474 {"stfdxe",      X(31,735),      X_MASK,      BOOKE64,   {FRS, RA0, RB}},
4475 {"stfdepx",     X(31,735),      X_MASK,      E500MC,    {RS, RA, RB}},
4476 {"mftgpr",      XRC(31,735,0),  XRA_MASK,    POWER6,    {RT, FRB}},
4477
4478 {"stddx",       X(31,739),      X_MASK,      E500MC,    {RS, RA, RB}},
4479
4480 {"stqfcmux",    APU(31,743,0),  APU_MASK,    PPC405,    {FCRT, RA, RB}},
4481
4482 {"subfmeo",     XO(31,232,1,0), XORB_MASK,   PPCCOM,    {RT, RA}},
4483 {"sfmeo",       XO(31,232,1,0), XORB_MASK,   PWRCOM,    {RT, RA}},
4484 {"subfmeo.",    XO(31,232,1,1), XORB_MASK,   PPCCOM,    {RT, RA}},
4485 {"sfmeo.",      XO(31,232,1,1), XORB_MASK,   PWRCOM,    {RT, RA}},
4486
4487 {"mulldo",      XO(31,233,1,0), XO_MASK,     PPC64,     {RT, RA, RB}},
4488 {"mulldo.",     XO(31,233,1,1), XO_MASK,     PPC64,     {RT, RA, RB}},
4489
4490 {"addmeo",      XO(31,234,1,0), XORB_MASK,   PPCCOM,    {RT, RA}},
4491 {"ameo",        XO(31,234,1,0), XORB_MASK,   PWRCOM,    {RT, RA}},
4492 {"addmeo.",     XO(31,234,1,1), XORB_MASK,   PPCCOM,    {RT, RA}},
4493 {"ameo.",       XO(31,234,1,1), XORB_MASK,   PWRCOM,    {RT, RA}},
4494
4495 {"mullwo",      XO(31,235,1,0), XO_MASK,     PPCCOM,    {RT, RA, RB}},
4496 {"mulso",       XO(31,235,1,0), XO_MASK,     PWRCOM,    {RT, RA, RB}},
4497 {"mullwo.",     XO(31,235,1,1), XO_MASK,     PPCCOM,    {RT, RA, RB}},
4498 {"mulso.",      XO(31,235,1,1), XO_MASK,     PWRCOM,    {RT, RA, RB}},
4499
4500 {"dcba",        X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE, {RA, RB}},
4501 {"dcbal",       XOPL(31,758,1), XRT_MASK,    E500MC,    {RA, RB}},
4502
4503 {"stfdux",      X(31,759),      X_MASK,      COM,       {FRS, RAS, RB}},
4504
4505 {"srliq",       XRC(31,760,0),  X_MASK,      M601,      {RA, RS, SH}},
4506 {"srliq.",      XRC(31,760,1),  X_MASK,      M601,      {RA, RS, SH}},
4507
4508 {"dcbae",       X(31,766),      XRT_MASK,    BOOKE64,   {RA, RB}},
4509
4510 {"stfduxe",     X(31,767),      X_MASK,      BOOKE64,   {FRS, RAS, RB}},
4511
4512 {"lvlxl",       X(31,775),      X_MASK,      CELL,      {VD, RA0, RB}},
4513 {"ldfcmux",     APU(31,775,0),  APU_MASK,    PPC405,    {FCRT, RA, RB}},
4514
4515 {"dozo",        XO(31,264,1,0), XO_MASK,     M601,      {RT, RA, RB}},
4516 {"dozo.",       XO(31,264,1,1), XO_MASK,     M601,      {RT, RA, RB}},
4517
4518 {"addo",        XO(31,266,1,0), XO_MASK,     PPCCOM,    {RT, RA, RB}},
4519 {"caxo",        XO(31,266,1,0), XO_MASK,     PWRCOM,    {RT, RA, RB}},
4520 {"addo.",       XO(31,266,1,1), XO_MASK,     PPCCOM,    {RT, RA, RB}},
4521 {"caxo.",       XO(31,266,1,1), XO_MASK,     PWRCOM,    {RT, RA, RB}},
4522
4523 {"tlbivax",     X(31,786),      XRT_MASK,    BOOKE,     {RA, RB}},
4524 {"tlbivaxe",    X(31,787),      XRT_MASK,    BOOKE64,   {RA, RB}},
4525 {"tlbilx",      X(31,787),      X_MASK,      E500MC,    {T, RA0, RB}},
4526 {"tlbilxlpid",  XTO(31,787,0),  XTO_MASK,    E500MC,    {0}},
4527 {"tlbilxpid",   XTO(31,787,1),  XTO_MASK,    E500MC,    {0}},
4528 {"tlbilxva",    XTO(31,787,3),  XTO_MASK,    E500MC,    {RA0, RB}},
4529
4530 {"lwzcix",      X(31,789),      X_MASK,      POWER6,    {RT, RA0, RB}},
4531
4532 {"lhbrx",       X(31,790),      X_MASK,      COM,       {RT, RA0, RB}},
4533
4534 {"lfqx",        X(31,791),      X_MASK,      POWER2,    {FRT, RA, RB}},
4535 {"lfdpx",       X(31,791),      X_MASK,      POWER6,    {FRT, RA, RB}},
4536
4537 {"sraw",        XRC(31,792,0),  X_MASK,      PPCCOM,    {RA, RS, RB}},
4538 {"sra",         XRC(31,792,0),  X_MASK,      PWRCOM,    {RA, RS, RB}},
4539 {"sraw.",       XRC(31,792,1),  X_MASK,      PPCCOM,    {RA, RS, RB}},
4540 {"sra.",        XRC(31,792,1),  X_MASK,      PWRCOM,    {RA, RS, RB}},
4541
4542 {"srad",        XRC(31,794,0),  X_MASK,      PPC64,     {RA, RS, RB}},
4543 {"srad.",       XRC(31,794,1),  X_MASK,      PPC64,     {RA, RS, RB}},
4544
4545 {"lhbrxe",      X(31,798),      X_MASK,      BOOKE64,   {RT, RA0, RB}},
4546
4547 {"ldxe",        X(31,799),      X_MASK,      BOOKE64,   {RT, RA0, RB}},
4548
4549 {"lfddx",       X(31,803),      X_MASK,      E500MC,    {FRT, RA, RB}},
4550
4551 {"lvrxl",       X(31,807),      X_MASK,      CELL,      {VD, RA0, RB}},
4552
4553 {"rac",         X(31,818),      X_MASK,      PWRCOM,    {RT, RA, RB}},
4554
4555 {"lhzcix",      X(31,821),      X_MASK,      POWER6,    {RT, RA0, RB}},
4556
4557 {"dss",         XDSS(31,822,0), XDSS_MASK,   PPCVEC,    {STRM}},
4558
4559 {"lfqux",       X(31,823),      X_MASK,      POWER2,    {FRT, RA, RB}},
4560
4561 {"srawi",       XRC(31,824,0),  X_MASK,      PPCCOM,    {RA, RS, SH}},
4562 {"srai",        XRC(31,824,0),  X_MASK,      PWRCOM,    {RA, RS, SH}},
4563 {"srawi.",      XRC(31,824,1),  X_MASK,      PPCCOM,    {RA, RS, SH}},
4564 {"srai.",       XRC(31,824,1),  X_MASK,      PWRCOM,    {RA, RS, SH}},
4565
4566 {"sradi",       XS(31,413,0),   XS_MASK,     PPC64,     {RA, RS, SH6}},
4567 {"sradi.",      XS(31,413,1),   XS_MASK,     PPC64,     {RA, RS, SH6}},
4568
4569 {"divo",        XO(31,331,1,0), XO_MASK,     M601,      {RT, RA, RB}},
4570 {"divo.",       XO(31,331,1,1), XO_MASK,     M601,      {RT, RA, RB}},
4571 {"lduxe",       X(31,831),      X_MASK,      BOOKE64,   {RT, RA0, RB}},
4572
4573 {"lxvd2x",      X(31,844),      XX1_MASK,    PPCVSX,    {XT6, RA, RB}},
4574
4575 {"slbmfev",     X(31,851),      XRA_MASK,    PPC64,     {RT, RB}},
4576
4577 {"lbzcix",      X(31,853),      X_MASK,      POWER6,    {RT, RA0, RB}},
4578
4579 {"mbar",        X(31,854),      X_MASK,      BOOKE,     {MO}},
4580 {"eieio",       X(31,854),      0xffffffff,  PPC,       {0}},
4581
4582 {"lfiwax",      X(31,855),      X_MASK,      POWER6,    {FRT, RA0, RB}},
4583
4584 {"abso",        XO(31,360,1,0), XORB_MASK,   M601,      {RT, RA}},
4585 {"abso.",       XO(31,360,1,1), XORB_MASK,   M601,      {RT, RA}},
4586
4587 {"divso",       XO(31,363,1,0), XO_MASK,     M601,      {RT, RA, RB}},
4588 {"divso.",      XO(31,363,1,1), XO_MASK,     M601,      {RT, RA, RB}},
4589
4590 {"lxvd2ux",     X(31,876),      XX1_MASK,    PPCVSX,    {XT6, RA, RB}},
4591
4592 {"ldcix",       X(31,885),      X_MASK,      POWER6,    {RT, RA0, RB}},
4593
4594 {"stvlxl",      X(31,903),      X_MASK,      CELL,      {VS, RA0, RB}},
4595 {"stdfcmux",    APU(31,903,0),  APU_MASK,    PPC405,    {FCRT, RA, RB}},
4596
4597 {"subfe64o",    XO(31,392,1,0), XO_MASK,     BOOKE64,   {RT, RA, RB}},
4598
4599 {"adde64o",     XO(31,394,1,0), XO_MASK,     BOOKE64,   {RT, RA, RB}},
4600
4601 {"tlbsx",       XRC(31,914,0),  X_MASK,   PPC403|BOOKE, {RTO, RA, RB}},
4602 {"tlbsx.",      XRC(31,914,1),  X_MASK,   PPC403|BOOKE, {RTO, RA, RB}},
4603
4604 {"tlbsxe",      XRC(31,915,0),  X_MASK,      BOOKE64,   {RTO, RA, RB}},
4605 {"tlbsxe.",     XRC(31,915,1),  X_MASK,      BOOKE64,   {RTO, RA, RB}},
4606 {"slbmfee",     X(31,915),      XRA_MASK,    PPC64,     {RT, RB}},
4607
4608 {"stwcix",      X(31,917),      X_MASK,      POWER6,    {RS, RA0, RB}},
4609
4610 {"sthbrx",      X(31,918),      X_MASK,      COM,       {RS, RA0, RB}},
4611
4612 {"stfqx",       X(31,919),      X_MASK,      POWER2,    {FRS, RA, RB}},
4613 {"stfdpx",      X(31,919),      X_MASK,      POWER6,    {FRS, RA, RB}},
4614
4615 {"sraq",        XRC(31,920,0),  X_MASK,      M601,      {RA, RS, RB}},
4616 {"sraq.",       XRC(31,920,1),  X_MASK,      M601,      {RA, RS, RB}},
4617
4618 {"srea",        XRC(31,921,0),  X_MASK,      M601,      {RA, RS, RB}},
4619 {"srea.",       XRC(31,921,1),  X_MASK,      M601,      {RA, RS, RB}},
4620
4621 {"extsh",       XRC(31,922,0),  XRB_MASK,    PPCCOM,    {RA, RS}},
4622 {"exts",        XRC(31,922,0),  XRB_MASK,    PWRCOM,    {RA, RS}},
4623 {"extsh.",      XRC(31,922,1),  XRB_MASK,    PPCCOM,    {RA, RS}},
4624 {"exts.",       XRC(31,922,1),  XRB_MASK,    PWRCOM,    {RA, RS}},
4625
4626 {"sthbrxe",     X(31,926),      X_MASK,      BOOKE64,   {RS, RA0, RB}},
4627
4628 {"stdxe",       X(31,927),      X_MASK,      BOOKE64,   {RS, RA0, RB}},
4629
4630 {"stfddx",      X(31,931),      X_MASK,      E500MC,    {FRS, RA, RB}},
4631
4632 {"stvrxl",      X(31,935),      X_MASK,      CELL,      {VS, RA0, RB}},
4633
4634 {"tlbrehi",     XTLB(31,946,0), XTLB_MASK,   PPC403,    {RT, RA}},
4635 {"tlbrelo",     XTLB(31,946,1), XTLB_MASK,   PPC403,    {RT, RA}},
4636 {"tlbre",       X(31,946),      X_MASK,   PPC403|BOOKE, {RSO, RAOPT, SHO}},
4637
4638 {"sthcix",      X(31,949),      X_MASK,      POWER6,    {RS, RA0, RB}},
4639
4640 {"stfqux",      X(31,951),      X_MASK,      POWER2,    {FRS, RA, RB}},
4641
4642 {"sraiq",       XRC(31,952,0),  X_MASK,      M601,      {RA, RS, SH}},
4643 {"sraiq.",      XRC(31,952,1),  X_MASK,      M601,      {RA, RS, SH}},
4644
4645 {"extsb",       XRC(31,954,0),  XRB_MASK,    PPC,       {RA, RS}},
4646 {"extsb.",      XRC(31,954,1),  XRB_MASK,    PPC,       {RA, RS}},
4647
4648 {"stduxe",      X(31,959),      X_MASK,      BOOKE64,   {RS, RAS, RB}},
4649
4650 {"iccci",       X(31,966),     XRT_MASK, PPC403|PPC440, {RA, RB}},
4651
4652 {"subfze64o",   XO(31,456,1,0), XORB_MASK,   BOOKE64,   {RT, RA}},
4653
4654 {"divduo",      XO(31,457,1,0), XO_MASK,     PPC64,     {RT, RA, RB}},
4655 {"divduo.",     XO(31,457,1,1), XO_MASK,     PPC64,     {RT, RA, RB}},
4656
4657 {"addze64o",    XO(31,458,1,0), XORB_MASK,   BOOKE64,   {RT, RA}},
4658
4659 {"divwuo",      XO(31,459,1,0), XO_MASK,     PPC,       {RT, RA, RB}},
4660 {"divwuo.",     XO(31,459,1,1), XO_MASK,     PPC,       {RT, RA, RB}},
4661
4662 {"stxvd2x",     X(31,972),      XX1_MASK,    PPCVSX,    {XS6, RA, RB}},
4663
4664 {"tlbwehi",     XTLB(31,978,0), XTLB_MASK,   PPC403,    {RT, RA}},
4665 {"tlbwelo",     XTLB(31,978,1), XTLB_MASK,   PPC403,    {RT, RA}},
4666 {"tlbwe",       X(31,978),      X_MASK,   PPC403|BOOKE, {RSO, RAOPT, SHO}},
4667 {"tlbld",       X(31,978),      XRTRA_MASK,  PPC,       {RB}},
4668
4669 {"stbcix",      X(31,981),      X_MASK,      POWER6,    {RS, RA0, RB}},
4670
4671 {"icbi",        X(31,982),      XRT_MASK,    PPC,       {RA, RB}},
4672
4673 {"stfiwx",      X(31,983),      X_MASK,      PPC,       {FRS, RA0, RB}},
4674
4675 {"extsw",       XRC(31,986,0), XRB_MASK, PPC64|BOOKE64, {RA, RS}},
4676 {"extsw.",      XRC(31,986,1),  XRB_MASK,    PPC64,     {RA, RS}},
4677
4678 {"icbie",       X(31,990),      XRT_MASK,    BOOKE64,   {RA, RB}},
4679 {"stfiwxe",     X(31,991),      X_MASK,      BOOKE64,   {FRS, RA0, RB}},
4680
4681 {"icbiep",      XRT(31,991,0),  XRT_MASK,    E500MC,    {RA, RB}},
4682
4683 {"icread",      X(31,998),     XRT_MASK, PPC403|PPC440, {RA, RB}},
4684
4685 {"nabso",       XO(31,488,1,0), XORB_MASK,   M601,      {RT, RA}},
4686 {"subfme64o",   XO(31,488,1,0), XORB_MASK,   BOOKE64,   {RT, RA}},
4687 {"nabso.",      XO(31,488,1,1), XORB_MASK,   M601,      {RT, RA}},
4688
4689 {"divdo",       XO(31,489,1,0), XO_MASK,     PPC64,     {RT, RA, RB}},
4690 {"divdo.",      XO(31,489,1,1), XO_MASK,     PPC64,     {RT, RA, RB}},
4691
4692 {"addme64o",    XO(31,490,1,0), XORB_MASK,   BOOKE64,   {RT, RA}},
4693
4694 {"divwo",       XO(31,491,1,0), XO_MASK,     PPC,       {RT, RA, RB}},
4695 {"divwo.",      XO(31,491,1,1), XO_MASK,     PPC,       {RT, RA, RB}},
4696
4697 {"stxvd2ux",    X(31,1004),     XX1_MASK,    PPCVSX,    {XS6, RA, RB}},
4698
4699 {"tlbli",       X(31,1010),     XRTRA_MASK,  PPC,       {RB}},
4700
4701 {"stdcix",      X(31,1013),     X_MASK,      POWER6,    {RS, RA0, RB}},
4702
4703 {"dcbz",        X(31,1014),     XRT_MASK,    PPC,       {RA, RB}},
4704 {"dclz",        X(31,1014),     XRT_MASK,    PPC,       {RA, RB}},
4705
4706 {"dcbze",       X(31,1022),     XRT_MASK,    BOOKE64,   {RA, RB}},
4707 {"dcbzep",      XRT(31,1023,0), XRT_MASK,    E500MC,    {RA, RB}},
4708
4709 {"dcbzl",       XOPL(31,1014,1), XRT_MASK,   POWER4,    {RA, RB}},
4710 {"dcbzl",       XOPL(31,1014,1), XRT_MASK,   NOPOWER4|E500MC,{RA, RB}},
4711
4712 {"cctpl",       0x7c210b78,     0xffffffff,  CELL,      {0}},
4713 {"cctpm",       0x7c421378,     0xffffffff,  CELL,      {0}},
4714 {"cctph",       0x7c631b78,     0xffffffff,  CELL,      {0}},
4715
4716 {"dstt",        XDSS(31,342,1), XDSS_MASK,   PPCVEC,    {RA, RB, STRM}},
4717 {"dststt",      XDSS(31,374,1), XDSS_MASK,   PPCVEC,    {RA, RB, STRM}},
4718 {"dssall",      XDSS(31,822,1), XDSS_MASK,   PPCVEC,    {0}},
4719
4720 {"db8cyc",      0x7f9ce378,     0xffffffff,  CELL,      {0}},
4721 {"db10cyc",     0x7fbdeb78,     0xffffffff,  CELL,      {0}},
4722 {"db12cyc",     0x7fdef378,     0xffffffff,  CELL,      {0}},
4723 {"db16cyc",     0x7ffffb78,     0xffffffff,  CELL,      {0}},
4724
4725 {"lwz",         OP(32),         OP_MASK,     PPCCOM,    {RT, D, RA0}},
4726 {"l",           OP(32),         OP_MASK,     PWRCOM,    {RT, D, RA0}},
4727
4728 {"lwzu",        OP(33),         OP_MASK,     PPCCOM,    {RT, D, RAL}},
4729 {"lu",          OP(33),         OP_MASK,     PWRCOM,    {RT, D, RA0}},
4730
4731 {"lbz",         OP(34),         OP_MASK,     COM,       {RT, D, RA0}},
4732
4733 {"lbzu",        OP(35),         OP_MASK,     COM,       {RT, D, RAL}},
4734
4735 {"stw",         OP(36),         OP_MASK,     PPCCOM,    {RS, D, RA0}},
4736 {"st",          OP(36),         OP_MASK,     PWRCOM,    {RS, D, RA0}},
4737
4738 {"stwu",        OP(37),         OP_MASK,     PPCCOM,    {RS, D, RAS}},
4739 {"stu",         OP(37),         OP_MASK,     PWRCOM,    {RS, D, RA0}},
4740
4741 {"stb",         OP(38),         OP_MASK,     COM,       {RS, D, RA0}},
4742
4743 {"stbu",        OP(39),         OP_MASK,     COM,       {RS, D, RAS}},
4744
4745 {"lhz",         OP(40),         OP_MASK,     COM,       {RT, D, RA0}},
4746
4747 {"lhzu",        OP(41),         OP_MASK,     COM,       {RT, D, RAL}},
4748
4749 {"lha",         OP(42),         OP_MASK,     COM,       {RT, D, RA0}},
4750
4751 {"lhau",        OP(43),         OP_MASK,     COM,       {RT, D, RAL}},
4752
4753 {"sth",         OP(44),         OP_MASK,     COM,       {RS, D, RA0}},
4754
4755 {"sthu",        OP(45),         OP_MASK,     COM,       {RS, D, RAS}},
4756
4757 {"lmw",         OP(46),         OP_MASK,     PPCCOM,    {RT, D, RAM}},
4758 {"lm",          OP(46),         OP_MASK,     PWRCOM,    {RT, D, RA0}},
4759
4760 {"stmw",        OP(47),         OP_MASK,     PPCCOM,    {RS, D, RA0}},
4761 {"stm",         OP(47),         OP_MASK,     PWRCOM,    {RS, D, RA0}},
4762
4763 {"lfs",         OP(48),         OP_MASK,     COM,       {FRT, D, RA0}},
4764
4765 {"lfsu",        OP(49),         OP_MASK,     COM,       {FRT, D, RAS}},
4766
4767 {"lfd",         OP(50),         OP_MASK,     COM,       {FRT, D, RA0}},
4768
4769 {"lfdu",        OP(51),         OP_MASK,     COM,       {FRT, D, RAS}},
4770
4771 {"stfs",        OP(52),         OP_MASK,     COM,       {FRS, D, RA0}},
4772
4773 {"stfsu",       OP(53),         OP_MASK,     COM,       {FRS, D, RAS}},
4774
4775 {"stfd",        OP(54),         OP_MASK,     COM,       {FRS, D, RA0}},
4776
4777 {"stfdu",       OP(55),         OP_MASK,     COM,       {FRS, D, RAS}},
4778
4779 {"lq",          OP(56),         OP_MASK,     POWER4,    {RTQ, DQ, RAQ}},
4780
4781 {"lfq",         OP(56),         OP_MASK,     POWER2,    {FRT, D, RA0}},
4782
4783 {"psq_l",       OP(56),         OP_MASK,     PPCPS,     {FRT,PSD,RA,PSW,PSQ}},
4784
4785 {"lfqu",        OP(57),         OP_MASK,     POWER2,    {FRT, D, RA0}},
4786
4787 {"psq_lu",      OP(57),         OP_MASK,     PPCPS,     {FRT,PSD,RA,PSW,PSQ}},
4788
4789 {"lfdp",        OP(57),         OP_MASK,     POWER6,    {FRT, D, RA0}},
4790
4791 {"lbze",        DEO(58,0),      DE_MASK,     BOOKE64,   {RT, DE, RA0}},
4792 {"lbzue",       DEO(58,1),      DE_MASK,     BOOKE64,   {RT, DE, RAL}},
4793 {"lhze",        DEO(58,2),      DE_MASK,     BOOKE64,   {RT, DE, RA0}},
4794 {"lhzue",       DEO(58,3),      DE_MASK,     BOOKE64,   {RT, DE, RAL}},
4795 {"lhae",        DEO(58,4),      DE_MASK,     BOOKE64,   {RT, DE, RA0}},
4796 {"lhaue",       DEO(58,5),      DE_MASK,     BOOKE64,   {RT, DE, RAL}},
4797 {"lwze",        DEO(58,6),      DE_MASK,     BOOKE64,   {RT, DE, RA0}},
4798 {"lwzue",       DEO(58,7),      DE_MASK,     BOOKE64,   {RT, DE, RAL}},
4799 {"stbe",        DEO(58,8),      DE_MASK,     BOOKE64,   {RS, DE, RA0}},
4800 {"stbue",       DEO(58,9),      DE_MASK,     BOOKE64,   {RS, DE, RAS}},
4801 {"sthe",        DEO(58,10),     DE_MASK,     BOOKE64,   {RS, DE, RA0}},
4802 {"sthue",       DEO(58,11),     DE_MASK,     BOOKE64,   {RS, DE, RAS}},
4803 {"stwe",        DEO(58,14),     DE_MASK,     BOOKE64,   {RS, DE, RA0}},
4804 {"stwue",       DEO(58,15),     DE_MASK,     BOOKE64,   {RS, DE, RAS}},
4805
4806 {"ld",          DSO(58,0),      DS_MASK,     PPC64,     {RT, DS, RA0}},
4807 {"ldu",         DSO(58,1),      DS_MASK,     PPC64,     {RT, DS, RAL}},
4808 {"lwa",         DSO(58,2),      DS_MASK,     PPC64,     {RT, DS, RA0}},
4809
4810 {"dadd",        XRC(59,2,0),    X_MASK,      POWER6,    {FRT, FRA, FRB}},
4811 {"dadd.",       XRC(59,2,1),    X_MASK,      POWER6,    {FRT, FRA, FRB}},
4812
4813 {"dqua",        ZRC(59,3,0),    Z2_MASK,     POWER6,    {FRT,FRA,FRB,RMC}},
4814 {"dqua.",       ZRC(59,3,1),    Z2_MASK,     POWER6,    {FRT,FRA,FRB,RMC}},
4815
4816 {"fdivs",       A(59,18,0),     AFRC_MASK,   PPC,       {FRT, FRA, FRB}},
4817 {"fdivs.",      A(59,18,1),     AFRC_MASK,   PPC,       {FRT, FRA, FRB}},
4818
4819 {"fsubs",       A(59,20,0),     AFRC_MASK,   PPC,       {FRT, FRA, FRB}},
4820 {"fsubs.",      A(59,20,1),     AFRC_MASK,   PPC,       {FRT, FRA, FRB}},
4821
4822 {"fadds",       A(59,21,0),     AFRC_MASK,   PPC,       {FRT, FRA, FRB}},
4823 {"fadds.",      A(59,21,1),     AFRC_MASK,   PPC,       {FRT, FRA, FRB}},
4824
4825 {"fsqrts",      A(59,22,0),    AFRAFRC_MASK, PPC,       {FRT, FRB}},
4826 {"fsqrts.",     A(59,22,1),    AFRAFRC_MASK, PPC,       {FRT, FRB}},
4827
4828 {"fres",        A(59,24,0),   AFRALFRC_MASK, PPC,       {FRT, FRB, A_L}},
4829 {"fres.",       A(59,24,1),   AFRALFRC_MASK, PPC,       {FRT, FRB, A_L}},
4830
4831 {"fmuls",       A(59,25,0),     AFRB_MASK,   PPC,       {FRT, FRA, FRC}},
4832 {"fmuls.",      A(59,25,1),     AFRB_MASK,   PPC,       {FRT, FRA, FRC}},
4833
4834 {"frsqrtes",    A(59,26,0),   AFRALFRC_MASK, POWER5,    {FRT, FRB, A_L}},
4835 {"frsqrtes.",   A(59,26,1),   AFRALFRC_MASK, POWER5,    {FRT, FRB, A_L}},
4836
4837 {"fmsubs",      A(59,28,0),     A_MASK,      PPC,       {FRT, FRA, FRC, FRB}},
4838 {"fmsubs.",     A(59,28,1),     A_MASK,      PPC,       {FRT, FRA, FRC, FRB}},
4839
4840 {"fmadds",      A(59,29,0),     A_MASK,      PPC,       {FRT, FRA, FRC, FRB}},
4841 {"fmadds.",     A(59,29,1),     A_MASK,      PPC,       {FRT, FRA, FRC, FRB}},
4842
4843 {"fnmsubs",     A(59,30,0),     A_MASK,      PPC,       {FRT, FRA, FRC, FRB}},
4844 {"fnmsubs.",    A(59,30,1),     A_MASK,      PPC,       {FRT, FRA, FRC, FRB}},
4845
4846 {"fnmadds",     A(59,31,0),     A_MASK,      PPC,       {FRT, FRA, FRC, FRB}},
4847 {"fnmadds.",    A(59,31,1),     A_MASK,      PPC,       {FRT, FRA, FRC, FRB}},
4848
4849 {"dmul",        XRC(59,34,0),   X_MASK,      POWER6,    {FRT, FRA, FRB}},
4850 {"dmul.",       XRC(59,34,1),   X_MASK,      POWER6,    {FRT, FRA, FRB}},
4851
4852 {"drrnd",       ZRC(59,35,0),   Z2_MASK,     POWER6,    {FRT, FRA, FRB, RMC}},
4853 {"drrnd.",      ZRC(59,35,1),   Z2_MASK,     POWER6,    {FRT, FRA, FRB, RMC}},
4854
4855 {"dscli",       ZRC(59,66,0),   Z_MASK,      POWER6,    {FRT, FRA, SH16}},
4856 {"dscli.",      ZRC(59,66,1),   Z_MASK,      POWER6,    {FRT, FRA, SH16}},
4857
4858 {"dquai",       ZRC(59,67,0),   Z2_MASK,     POWER6,    {TE, FRT,FRB,RMC}},
4859 {"dquai.",      ZRC(59,67,1),   Z2_MASK,     POWER6,    {TE, FRT,FRB,RMC}},
4860
4861 {"dscri",       ZRC(59,98,0),   Z_MASK,      POWER6,    {FRT, FRA, SH16}},
4862 {"dscri.",      ZRC(59,98,1),   Z_MASK,      POWER6,    {FRT, FRA, SH16}},
4863
4864 {"drintx",      ZRC(59,99,0),   Z2_MASK,     POWER6,    {R, FRT, FRB, RMC}},
4865 {"drintx.",     ZRC(59,99,1),   Z2_MASK,     POWER6,    {R, FRT, FRB, RMC}},
4866
4867 {"dcmpo",       X(59,130),      X_MASK,      POWER6,    {BF,  FRA, FRB}},
4868
4869 {"dtstex",      X(59,162),      X_MASK,      POWER6,    {BF,  FRA, FRB}},
4870 {"dtstdc",      Z(59,194),      Z_MASK,      POWER6,    {BF,  FRA, DCM}},
4871 {"dtstdg",      Z(59,226),      Z_MASK,      POWER6,    {BF,  FRA, DGM}},
4872
4873 {"drintn",      ZRC(59,227,0),  Z2_MASK,     POWER6,    {R, FRT, FRB, RMC}},
4874 {"drintn.",     ZRC(59,227,1),  Z2_MASK,     POWER6,    {R, FRT, FRB, RMC}},
4875
4876 {"dctdp",       XRC(59,258,0),  X_MASK,      POWER6,    {FRT, FRB}},
4877 {"dctdp.",      XRC(59,258,1),  X_MASK,      POWER6,    {FRT, FRB}},
4878
4879 {"dctfix",      XRC(59,290,0),  X_MASK,      POWER6,    {FRT, FRB}},
4880 {"dctfix.",     XRC(59,290,1),  X_MASK,      POWER6,    {FRT, FRB}},
4881
4882 {"ddedpd",      XRC(59,322,0),  X_MASK,      POWER6,    {SP, FRT, FRB}},
4883 {"ddedpd.",     XRC(59,322,1),  X_MASK,      POWER6,    {SP, FRT, FRB}},
4884
4885 {"dxex",        XRC(59,354,0),  X_MASK,      POWER6,    {FRT, FRB}},
4886 {"dxex.",       XRC(59,354,1),  X_MASK,      POWER6,    {FRT, FRB}},
4887
4888 {"dsub",        XRC(59,514,0),  X_MASK,      POWER6,    {FRT, FRA, FRB}},
4889 {"dsub.",       XRC(59,514,1),  X_MASK,      POWER6,    {FRT, FRA, FRB}},
4890
4891 {"ddiv",        XRC(59,546,0),  X_MASK,      POWER6,    {FRT, FRA, FRB}},
4892 {"ddiv.",       XRC(59,546,1),  X_MASK,      POWER6,    {FRT, FRA, FRB}},
4893
4894 {"dcmpu",       X(59,642),      X_MASK,      POWER6,    {BF,  FRA, FRB}},
4895
4896 {"dtstsf",      X(59,674),      X_MASK,      POWER6,    {BF,  FRA, FRB}},
4897
4898 {"drsp",        XRC(59,770,0),  X_MASK,      POWER6,    {FRT, FRB}},
4899 {"drsp.",       XRC(59,770,1),  X_MASK,      POWER6,    {FRT, FRB}},
4900
4901 {"denbcd",      XRC(59,834,0),  X_MASK,      POWER6,    {S, FRT, FRB}},
4902 {"denbcd.",     XRC(59,834,1),  X_MASK,      POWER6,    {S, FRT, FRB}},
4903
4904 {"diex",        XRC(59,866,0),  X_MASK,      POWER6,    {FRT, FRA, FRB}},
4905 {"diex.",       XRC(59,866,1),  X_MASK,      POWER6,    {FRT, FRA, FRB}},
4906
4907 {"stfq",        OP(60),         OP_MASK,     POWER2,    {FRS, D, RA}},
4908
4909 {"psq_st",      OP(60),         OP_MASK,     PPCPS,     {FRS,PSD,RA,PSW,PSQ}},
4910
4911 {"xxmrghd",     XX3(60,10),     XX3_MASK,    PPCVSX,    {XT6, XA6, XB6}},
4912 {"xxmrgld",     XX3(60,10)|(3<<8), XX3_MASK, PPCVSX,    {XT6, XA6, XB6}},
4913 {"xxpermdi",    XX3(60,10),     XX3DM_MASK,  PPCVSX,    {XT6, XA6, XB6, DM}},
4914 {"xvmovdp",     XX3(60,240),    XX3_MASK,    PPCVSX,    {XT6, XA6, XB6S}},
4915 {"xvcpsgndp",   XX3(60,240),    XX3_MASK,    PPCVSX,    {XT6, XA6, XB6}},
4916
4917 {"psq_stu",     OP(61),         OP_MASK,     PPCPS,     {FRS,PSD,RA,PSW,PSQ}},
4918
4919 {"stfqu",       OP(61),         OP_MASK,     POWER2,    {FRS, D, RA}},
4920
4921 {"stfdp",       OP(61),         OP_MASK,     POWER6,    {FRT, D, RA0}},
4922
4923 {"lde",         DEO(62,0),      DE_MASK,     BOOKE64,   {RT, DES, RA0}},
4924 {"ldue",        DEO(62,1),      DE_MASK,     BOOKE64,   {RT, DES, RA0}},
4925 {"lfse",        DEO(62,4),      DE_MASK,     BOOKE64,   {FRT, DES, RA0}},
4926 {"lfsue",       DEO(62,5),      DE_MASK,     BOOKE64,   {FRT, DES, RAS}},
4927 {"lfde",        DEO(62,6),      DE_MASK,     BOOKE64,   {FRT, DES, RA0}},
4928 {"lfdue",       DEO(62,7),      DE_MASK,     BOOKE64,   {FRT, DES, RAS}},
4929 {"stde",        DEO(62,8),      DE_MASK,     BOOKE64,   {RS, DES, RA0}},
4930 {"stdue",       DEO(62,9),      DE_MASK,     BOOKE64,   {RS, DES, RAS}},
4931 {"stfse",       DEO(62,12),     DE_MASK,     BOOKE64,   {FRS, DES, RA0}},
4932 {"stfsue",      DEO(62,13),     DE_MASK,     BOOKE64,   {FRS, DES, RAS}},
4933 {"stfde",       DEO(62,14),     DE_MASK,     BOOKE64,   {FRS, DES, RA0}},
4934 {"stfdue",      DEO(62,15),     DE_MASK,     BOOKE64,   {FRS, DES, RAS}},
4935
4936 {"std",         DSO(62,0),      DS_MASK,     PPC64,     {RS, DS, RA0}},
4937 {"stdu",        DSO(62,1),      DS_MASK,     PPC64,     {RS, DS, RAS}},
4938 {"stq",         DSO(62,2),      DS_MASK,     POWER4,    {RSQ, DS, RA0}},
4939
4940 {"fcmpu",       X(63,0),     X_MASK|(3<<21), COM,       {BF, FRA, FRB}},
4941
4942 {"daddq",       XRC(63,2,0),    X_MASK,      POWER6,    {FRT, FRA, FRB}},
4943 {"daddq.",      XRC(63,2,1),    X_MASK,      POWER6,    {FRT, FRA, FRB}},
4944
4945 {"dquaq",       ZRC(63,3,0),    Z2_MASK,     POWER6,    {FRT, FRA, FRB, RMC}},
4946 {"dquaq.",      ZRC(63,3,1),    Z2_MASK,     POWER6,    {FRT, FRA, FRB, RMC}},
4947
4948 {"fcpsgn",      XRC(63,8,0),    X_MASK,      POWER6,    {FRT, FRA, FRB}},
4949 {"fcpsgn.",     XRC(63,8,1),    X_MASK,      POWER6,    {FRT, FRA, FRB}},
4950
4951 {"frsp",        XRC(63,12,0),   XRA_MASK,    COM,       {FRT, FRB}},
4952 {"frsp.",       XRC(63,12,1),   XRA_MASK,    COM,       {FRT, FRB}},
4953
4954 {"fctiw",       XRC(63,14,0),   XRA_MASK,    PPCCOM,    {FRT, FRB}},
4955 {"fcir",        XRC(63,14,0),   XRA_MASK,    POWER2,    {FRT, FRB}},
4956 {"fctiw.",      XRC(63,14,1),   XRA_MASK,    PPCCOM,    {FRT, FRB}},
4957 {"fcir.",       XRC(63,14,1),   XRA_MASK,    POWER2,    {FRT, FRB}},
4958
4959 {"fctiwz",      XRC(63,15,0),   XRA_MASK,    PPCCOM,    {FRT, FRB}},
4960 {"fcirz",       XRC(63,15,0),   XRA_MASK,    POWER2,    {FRT, FRB}},
4961 {"fctiwz.",     XRC(63,15,1),   XRA_MASK,    PPCCOM,    {FRT, FRB}},
4962 {"fcirz.",      XRC(63,15,1),   XRA_MASK,    POWER2,    {FRT, FRB}},
4963
4964 {"fdiv",        A(63,18,0),     AFRC_MASK,   PPCCOM,    {FRT, FRA, FRB}},
4965 {"fd",          A(63,18,0),     AFRC_MASK,   PWRCOM,    {FRT, FRA, FRB}},
4966 {"fdiv.",       A(63,18,1),     AFRC_MASK,   PPCCOM,    {FRT, FRA, FRB}},
4967 {"fd.",         A(63,18,1),     AFRC_MASK,   PWRCOM,    {FRT, FRA, FRB}},
4968
4969 {"fsub",        A(63,20,0),     AFRC_MASK,   PPCCOM,    {FRT, FRA, FRB}},
4970 {"fs",          A(63,20,0),     AFRC_MASK,   PWRCOM,    {FRT, FRA, FRB}},
4971 {"fsub.",       A(63,20,1),     AFRC_MASK,   PPCCOM,    {FRT, FRA, FRB}},
4972 {"fs.",         A(63,20,1),     AFRC_MASK,   PWRCOM,    {FRT, FRA, FRB}},
4973
4974 {"fadd",        A(63,21,0),     AFRC_MASK,   PPCCOM,    {FRT, FRA, FRB}},
4975 {"fa",          A(63,21,0),     AFRC_MASK,   PWRCOM,    {FRT, FRA, FRB}},
4976 {"fadd.",       A(63,21,1),     AFRC_MASK,   PPCCOM,    {FRT, FRA, FRB}},
4977 {"fa.",         A(63,21,1),     AFRC_MASK,   PWRCOM,    {FRT, FRA, FRB}},
4978
4979 {"fsqrt",       A(63,22,0),    AFRAFRC_MASK, PPCPWR2,   {FRT, FRB}},
4980 {"fsqrt.",      A(63,22,1),    AFRAFRC_MASK, PPCPWR2,   {FRT, FRB}},
4981
4982 {"fsel",        A(63,23,0),     A_MASK,      PPC,       {FRT, FRA, FRC, FRB}},
4983 {"fsel.",       A(63,23,1),     A_MASK,      PPC,       {FRT, FRA, FRC, FRB}},
4984
4985 {"fre",         A(63,24,0),   AFRALFRC_MASK, POWER5,    {FRT, FRB, A_L}},
4986 {"fre.",        A(63,24,1),   AFRALFRC_MASK, POWER5,    {FRT, FRB, A_L}},
4987
4988 {"fmul",        A(63,25,0),     AFRB_MASK,   PPCCOM,    {FRT, FRA, FRC}},
4989 {"fm",          A(63,25,0),     AFRB_MASK,   PWRCOM,    {FRT, FRA, FRC}},
4990 {"fmul.",       A(63,25,1),     AFRB_MASK,   PPCCOM,    {FRT, FRA, FRC}},
4991 {"fm.",         A(63,25,1),     AFRB_MASK,   PWRCOM,    {FRT, FRA, FRC}},
4992
4993 {"frsqrte",     A(63,26,0),   AFRALFRC_MASK, PPC,       {FRT, FRB, A_L}},
4994 {"frsqrte.",    A(63,26,1),   AFRALFRC_MASK, PPC,       {FRT, FRB, A_L}},
4995
4996 {"fmsub",       A(63,28,0),     A_MASK,      PPCCOM,    {FRT, FRA, FRC, FRB}},
4997 {"fms",         A(63,28,0),     A_MASK,      PWRCOM,    {FRT, FRA, FRC, FRB}},
4998 {"fmsub.",      A(63,28,1),     A_MASK,      PPCCOM,    {FRT, FRA, FRC, FRB}},
4999 {"fms.",        A(63,28,1),     A_MASK,      PWRCOM,    {FRT, FRA, FRC, FRB}},
5000
5001 {"fmadd",       A(63,29,0),     A_MASK,      PPCCOM,    {FRT, FRA, FRC, FRB}},
5002 {"fma",         A(63,29,0),     A_MASK,      PWRCOM,    {FRT, FRA, FRC, FRB}},
5003 {"fmadd.",      A(63,29,1),     A_MASK,      PPCCOM,    {FRT, FRA, FRC, FRB}},
5004 {"fma.",        A(63,29,1),     A_MASK,      PWRCOM,    {FRT, FRA, FRC, FRB}},
5005
5006 {"fnmsub",      A(63,30,0),     A_MASK,      PPCCOM,    {FRT, FRA, FRC, FRB}},
5007 {"fnms",        A(63,30,0),     A_MASK,      PWRCOM,    {FRT, FRA, FRC, FRB}},
5008 {"fnmsub.",     A(63,30,1),     A_MASK,      PPCCOM,    {FRT, FRA, FRC, FRB}},
5009 {"fnms.",       A(63,30,1),     A_MASK,      PWRCOM,    {FRT, FRA, FRC, FRB}},
5010
5011 {"fnmadd",      A(63,31,0),     A_MASK,      PPCCOM,    {FRT, FRA, FRC, FRB}},
5012 {"fnma",        A(63,31,0),     A_MASK,      PWRCOM,    {FRT, FRA, FRC, FRB}},
5013 {"fnmadd.",     A(63,31,1),     A_MASK,      PPCCOM,    {FRT, FRA, FRC, FRB}},
5014 {"fnma.",       A(63,31,1),     A_MASK,      PWRCOM,    {FRT, FRA, FRC, FRB}},
5015
5016 {"fcmpo",       X(63,32),    X_MASK|(3<<21), COM,       {BF, FRA, FRB}},
5017
5018 {"dmulq",       XRC(63,34,0),   X_MASK,      POWER6,    {FRT, FRA, FRB}},
5019 {"dmulq.",      XRC(63,34,1),   X_MASK,      POWER6,    {FRT, FRA, FRB}},
5020
5021 {"drrndq",      ZRC(63,35,0),   Z2_MASK,     POWER6,    {FRT, FRA, FRB, RMC}},
5022 {"drrndq.",     ZRC(63,35,1),   Z2_MASK,     POWER6,    {FRT, FRA, FRB, RMC}},
5023
5024 {"mtfsb1",      XRC(63,38,0),   XRARB_MASK,  COM,       {BT}},
5025 {"mtfsb1.",     XRC(63,38,1),   XRARB_MASK,  COM,       {BT}},
5026
5027 {"fneg",        XRC(63,40,0),   XRA_MASK,    COM,       {FRT, FRB}},
5028 {"fneg.",       XRC(63,40,1),   XRA_MASK,    COM,       {FRT, FRB}},
5029
5030 {"mcrfs",      X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, {BF, BFA}},
5031
5032 {"dscliq",      ZRC(63,66,0),   Z_MASK,      POWER6,    {FRT, FRA, SH16}},
5033 {"dscliq.",     ZRC(63,66,1),   Z_MASK,      POWER6,    {FRT, FRA, SH16}},
5034
5035 {"dquaiq",      ZRC(63,67,0),   Z2_MASK,     POWER6,    {TE, FRT, FRB, RMC}},
5036 {"dquaiq.",     ZRC(63,67,1),   Z2_MASK,     POWER6,    {TE, FRT, FRB, RMC}},
5037
5038 {"mtfsb0",      XRC(63,70,0),   XRARB_MASK,  COM,       {BT}},
5039 {"mtfsb0.",     XRC(63,70,1),   XRARB_MASK,  COM,       {BT}},
5040
5041 {"fmr",         XRC(63,72,0),   XRA_MASK,    COM,       {FRT, FRB}},
5042 {"fmr.",        XRC(63,72,1),   XRA_MASK,    COM,       {FRT, FRB}},
5043
5044 {"dscriq",      ZRC(63,98,0),   Z_MASK,      POWER6,    {FRT, FRA, SH16}},
5045 {"dscriq.",     ZRC(63,98,1),   Z_MASK,      POWER6,    {FRT, FRA, SH16}},
5046
5047 {"drintxq",     ZRC(63,99,0),   Z2_MASK,     POWER6,    {R, FRT, FRB, RMC}},
5048 {"drintxq.",    ZRC(63,99,1),   Z2_MASK,     POWER6,    {R, FRT, FRB, RMC}},
5049
5050 {"dcmpoq",      X(63,130),      X_MASK,      POWER6,    {BF, FRA, FRB}},
5051
5052 {"mtfsfi",  XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), COM, {BFF, U, W}},
5053 {"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), COM, {BFF, U, W}},
5054
5055 {"fnabs",       XRC(63,136,0),  XRA_MASK,    COM,       {FRT, FRB}},
5056 {"fnabs.",      XRC(63,136,1),  XRA_MASK,    COM,       {FRT, FRB}},
5057
5058 {"dtstexq",     X(63,162),      X_MASK,      POWER6,    {BF, FRA, FRB}},
5059 {"dtstdcq",     Z(63,194),      Z_MASK,      POWER6,    {BF, FRA, DCM}},
5060 {"dtstdgq",     Z(63,226),      Z_MASK,      POWER6,    {BF, FRA, DGM}},
5061
5062 {"drintnq",     ZRC(63,227,0),  Z2_MASK,     POWER6,    {R, FRT, FRB, RMC}},
5063 {"drintnq.",    ZRC(63,227,1),  Z2_MASK,     POWER6,    {R, FRT, FRB, RMC}},
5064
5065 {"dctqpq",      XRC(63,258,0),  X_MASK,      POWER6,    {FRT, FRB}},
5066 {"dctqpq.",     XRC(63,258,1),  X_MASK,      POWER6,    {FRT, FRB}},
5067
5068 {"fabs",        XRC(63,264,0),  XRA_MASK,    COM,       {FRT, FRB}},
5069 {"fabs.",       XRC(63,264,1),  XRA_MASK,    COM,       {FRT, FRB}},
5070
5071 {"dctfixq",     XRC(63,290,0),  X_MASK,      POWER6,    {FRT, FRB}},
5072 {"dctfixq.",    XRC(63,290,1),  X_MASK,      POWER6,    {FRT, FRB}},
5073
5074 {"ddedpdq",     XRC(63,322,0),  X_MASK,      POWER6,    {SP, FRT, FRB}},
5075 {"ddedpdq.",    XRC(63,322,1),  X_MASK,      POWER6,    {SP, FRT, FRB}},
5076
5077 {"dxexq",       XRC(63,354,0),  X_MASK,      POWER6,    {FRT, FRB}},
5078 {"dxexq.",      XRC(63,354,1),  X_MASK,      POWER6,    {FRT, FRB}},
5079
5080 {"frin",        XRC(63,392,0),  XRA_MASK,    POWER5,    {FRT, FRB}},
5081 {"frin.",       XRC(63,392,1),  XRA_MASK,    POWER5,    {FRT, FRB}},
5082 {"friz",        XRC(63,424,0),  XRA_MASK,    POWER5,    {FRT, FRB}},
5083 {"friz.",       XRC(63,424,1),  XRA_MASK,    POWER5,    {FRT, FRB}},
5084 {"frip",        XRC(63,456,0),  XRA_MASK,    POWER5,    {FRT, FRB}},
5085 {"frip.",       XRC(63,456,1),  XRA_MASK,    POWER5,    {FRT, FRB}},
5086 {"frim",        XRC(63,488,0),  XRA_MASK,    POWER5,    {FRT, FRB}},
5087 {"frim.",       XRC(63,488,1),  XRA_MASK,    POWER5,    {FRT, FRB}},
5088
5089 {"dsubq",       XRC(63,514,0),  X_MASK,      POWER6,    {FRT, FRA, FRB}},
5090 {"dsubq.",      XRC(63,514,1),  X_MASK,      POWER6,    {FRT, FRA, FRB}},
5091
5092 {"ddivq",       XRC(63,546,0),  X_MASK,      POWER6,    {FRT, FRA, FRB}},
5093 {"ddivq.",      XRC(63,546,1),  X_MASK,      POWER6,    {FRT, FRA, FRB}},
5094
5095 {"mffs",        XRC(63,583,0),  XRARB_MASK,  COM,       {FRT}},
5096 {"mffs.",       XRC(63,583,1),  XRARB_MASK,  COM,       {FRT}},
5097
5098 {"dcmpuq",      X(63,642),      X_MASK,      POWER6,    {BF, FRA, FRB}},
5099
5100 {"dtstsfq",     X(63,674),      X_MASK,      POWER6,    {BF, FRA, FRB}},
5101
5102 {"mtfsf",       XFL(63,711,0),  XFL_MASK,    COM,       {FLM, FRB, XFL_L, W}},
5103 {"mtfsf.",      XFL(63,711,1),  XFL_MASK,    COM,       {FLM, FRB, XFL_L, W}},
5104
5105 {"drdpq",       XRC(63,770,0),  X_MASK,      POWER6,    {FRT, FRB}},
5106 {"drdpq.",      XRC(63,770,1),  X_MASK,      POWER6,    {FRT, FRB}},
5107
5108 {"dcffixq",     XRC(63,802,0),  X_MASK,      POWER6,    {FRT, FRB}},
5109 {"dcffixq.",    XRC(63,802,1),  X_MASK,      POWER6,    {FRT, FRB}},
5110
5111 {"fctid",       XRC(63,814,0),  XRA_MASK,    PPC64,     {FRT, FRB}},
5112 {"fctid.",      XRC(63,814,1),  XRA_MASK,    PPC64,     {FRT, FRB}},
5113
5114 {"fctidz",      XRC(63,815,0),  XRA_MASK,    PPC64,     {FRT, FRB}},
5115 {"fctidz.",     XRC(63,815,1),  XRA_MASK,    PPC64,     {FRT, FRB}},
5116
5117 {"denbcdq",     XRC(63,834,0),  X_MASK,      POWER6,    {S, FRT, FRB}},
5118 {"denbcdq.",    XRC(63,834,1),  X_MASK,      POWER6,    {S, FRT, FRB}},
5119
5120 {"fcfid",       XRC(63,846,0),  XRA_MASK,    PPC64,     {FRT, FRB}},
5121 {"fcfid.",      XRC(63,846,1),  XRA_MASK,    PPC64,     {FRT, FRB}},
5122
5123 {"diexq",       XRC(63,866,0),  X_MASK,      POWER6,    {FRT, FRA, FRB}},
5124 {"diexq.",      XRC(63,866,1),  X_MASK,      POWER6,    {FRT, FRA, FRB}},
5125
5126 };
5127
5128 const int powerpc_num_opcodes =
5129   sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
5130 \f
5131 /* The macro table.  This is only used by the assembler.  */
5132
5133 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
5134    when x=0; 32-x when x is between 1 and 31; are negative if x is
5135    negative; and are 32 or more otherwise.  This is what you want
5136    when, for instance, you are emulating a right shift by a
5137    rotate-left-and-mask, because the underlying instructions support
5138    shifts of size 0 but not shifts of size 32.  By comparison, when
5139    extracting x bits from some word you want to use just 32-x, because
5140    the underlying instructions don't support extracting 0 bits but do
5141    support extracting the whole word (32 bits in this case).  */
5142
5143 const struct powerpc_macro powerpc_macros[] = {
5144 {"extldi",   4, PPC64,  "rldicr %0,%1,%3,(%2)-1"},
5145 {"extldi.",  4, PPC64,  "rldicr. %0,%1,%3,(%2)-1"},
5146 {"extrdi",   4, PPC64,  "rldicl %0,%1,(%2)+(%3),64-(%2)"},
5147 {"extrdi.",  4, PPC64,  "rldicl. %0,%1,(%2)+(%3),64-(%2)"},
5148 {"insrdi",   4, PPC64,  "rldimi %0,%1,64-((%2)+(%3)),%3"},
5149 {"insrdi.",  4, PPC64,  "rldimi. %0,%1,64-((%2)+(%3)),%3"},
5150 {"rotrdi",   3, PPC64,  "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
5151 {"rotrdi.",  3, PPC64,  "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
5152 {"sldi",     3, PPC64,  "rldicr %0,%1,%2,63-(%2)"},
5153 {"sldi.",    3, PPC64,  "rldicr. %0,%1,%2,63-(%2)"},
5154 {"srdi",     3, PPC64,  "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
5155 {"srdi.",    3, PPC64,  "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
5156 {"clrrdi",   3, PPC64,  "rldicr %0,%1,0,63-(%2)"},
5157 {"clrrdi.",  3, PPC64,  "rldicr. %0,%1,0,63-(%2)"},
5158 {"clrlsldi", 4, PPC64,  "rldic %0,%1,%3,(%2)-(%3)"},
5159 {"clrlsldi.",4, PPC64,  "rldic. %0,%1,%3,(%2)-(%3)"},
5160
5161 {"extlwi",   4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
5162 {"extlwi.",  4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
5163 {"extrwi",   4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
5164 {"extrwi.",  4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
5165 {"inslwi",   4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
5166 {"inslwi.",  4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
5167 {"insrwi",   4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
5168 {"insrwi.",  4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
5169 {"rotrwi",   3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
5170 {"rotrwi.",  3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
5171 {"slwi",     3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
5172 {"sli",      3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
5173 {"slwi.",    3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
5174 {"sli.",     3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
5175 {"srwi",     3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5176 {"sri",      3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5177 {"srwi.",    3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5178 {"sri.",     3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5179 {"clrrwi",   3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
5180 {"clrrwi.",  3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
5181 {"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
5182 {"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
5183 };
5184
5185 const int powerpc_num_macros =
5186   sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);