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1 This is as.info, produced by makeinfo version 4.0 from as.texinfo.
3 START-INFO-DIR-ENTRY
4 * As: (as). The GNU assembler.
5 END-INFO-DIR-ENTRY
7 This file documents the GNU Assembler "as".
9 Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001 Free
10 Software Foundation, Inc.
12 Permission is granted to copy, distribute and/or modify this document
13 under the terms of the GNU Free Documentation License, Version 1.1
14 or any later version published by the Free Software Foundation;
15 with no Invariant Sections, with no Front-Cover Texts, and with no
16 Back-Cover Texts. A copy of the license is included in the
17 section entitled "GNU Free Documentation License".
19 \x1f
20 File: as.info, Node: HPPA Syntax, Next: HPPA Floating Point, Prev: HPPA Options, Up: HPPA-Dependent
22 Syntax
23 ------
25 The assembler syntax closely follows the HPPA instruction set
26 reference manual; assembler directives and general syntax closely
27 follow the HPPA assembly language reference manual, with a few
28 noteworthy differences.
30 First, a colon may immediately follow a label definition. This is
31 simply for compatibility with how most assembly language programmers
32 write code.
34 Some obscure expression parsing problems may affect hand written
35 code which uses the `spop' instructions, or code which makes significant
36 use of the `!' line separator.
38 `as' is much less forgiving about missing arguments and other
39 similar oversights than the HP assembler. `as' notifies you of missing
40 arguments as syntax errors; this is regarded as a feature, not a bug.
42 Finally, `as' allows you to use an external symbol without
43 explicitly importing the symbol. _Warning:_ in the future this will be
44 an error for HPPA targets.
46 Special characters for HPPA targets include:
48 `;' is the line comment character.
50 `!' can be used instead of a newline to separate statements.
52 Since `$' has no special meaning, you may use it in symbol names.
54 \x1f
55 File: as.info, Node: HPPA Floating Point, Next: HPPA Directives, Prev: HPPA Syntax, Up: HPPA-Dependent
57 Floating Point
58 --------------
60 The HPPA family uses IEEE floating-point numbers.
62 \x1f
63 File: as.info, Node: HPPA Directives, Next: HPPA Opcodes, Prev: HPPA Floating Point, Up: HPPA-Dependent
65 HPPA Assembler Directives
66 -------------------------
68 `as' for the HPPA supports many additional directives for
69 compatibility with the native assembler. This section describes them
70 only briefly. For detailed information on HPPA-specific assembler
71 directives, see `HP9000 Series 800 Assembly Language Reference Manual'
72 (HP 92432-90001).
74 `as' does _not_ support the following assembler directives described
75 in the HP manual:
77 .endm .liston
78 .enter .locct
79 .leave .macro
80 .listoff
82 Beyond those implemented for compatibility, `as' supports one
83 additional assembler directive for the HPPA: `.param'. It conveys
84 register argument locations for static functions. Its syntax closely
85 follows the `.export' directive.
87 These are the additional directives in `as' for the HPPA:
89 `.block N'
90 `.blockz N'
91 Reserve N bytes of storage, and initialize them to zero.
93 `.call'
94 Mark the beginning of a procedure call. Only the special case
95 with _no arguments_ is allowed.
97 `.callinfo [ PARAM=VALUE, ... ] [ FLAG, ... ]'
98 Specify a number of parameters and flags that define the
99 environment for a procedure.
101 PARAM may be any of `frame' (frame size), `entry_gr' (end of
102 general register range), `entry_fr' (end of float register range),
103 `entry_sr' (end of space register range).
105 The values for FLAG are `calls' or `caller' (proc has
106 subroutines), `no_calls' (proc does not call subroutines),
107 `save_rp' (preserve return pointer), `save_sp' (proc preserves
108 stack pointer), `no_unwind' (do not unwind this proc), `hpux_int'
109 (proc is interrupt routine).
111 `.code'
112 Assemble into the standard section called `$TEXT$', subsection
113 `$CODE$'.
115 `.copyright "STRING"'
116 In the SOM object format, insert STRING into the object code,
117 marked as a copyright string.
119 `.copyright "STRING"'
120 In the ELF object format, insert STRING into the object code,
121 marked as a version string.
123 `.enter'
124 Not yet supported; the assembler rejects programs containing this
125 directive.
127 `.entry'
128 Mark the beginning of a procedure.
130 `.exit'
131 Mark the end of a procedure.
133 `.export NAME [ ,TYP ] [ ,PARAM=R ]'
134 Make a procedure NAME available to callers. TYP, if present, must
135 be one of `absolute', `code' (ELF only, not SOM), `data', `entry',
136 `data', `entry', `millicode', `plabel', `pri_prog', or `sec_prog'.
138 PARAM, if present, provides either relocation information for the
139 procedure arguments and result, or a privilege level. PARAM may be
140 `argwN' (where N ranges from `0' to `3', and indicates one of four
141 one-word arguments); `rtnval' (the procedure's result); or
142 `priv_lev' (privilege level). For arguments or the result, R
143 specifies how to relocate, and must be one of `no' (not
144 relocatable), `gr' (argument is in general register), `fr' (in
145 floating point register), or `fu' (upper half of float register).
146 For `priv_lev', R is an integer.
148 `.half N'
149 Define a two-byte integer constant N; synonym for the portable
150 `as' directive `.short'.
152 `.import NAME [ ,TYP ]'
153 Converse of `.export'; make a procedure available to call. The
154 arguments use the same conventions as the first two arguments for
155 `.export'.
157 `.label NAME'
158 Define NAME as a label for the current assembly location.
160 `.leave'
161 Not yet supported; the assembler rejects programs containing this
162 directive.
164 `.origin LC'
165 Advance location counter to LC. Synonym for the `{No value for
166 `as'}' portable directive `.org'.
168 `.param NAME [ ,TYP ] [ ,PARAM=R ]'
169 Similar to `.export', but used for static procedures.
171 `.proc'
172 Use preceding the first statement of a procedure.
174 `.procend'
175 Use following the last statement of a procedure.
177 `LABEL .reg EXPR'
178 Synonym for `.equ'; define LABEL with the absolute expression EXPR
179 as its value.
181 `.space SECNAME [ ,PARAMS ]'
182 Switch to section SECNAME, creating a new section by that name if
183 necessary. You may only use PARAMS when creating a new section,
184 not when switching to an existing one. SECNAME may identify a
185 section by number rather than by name.
187 If specified, the list PARAMS declares attributes of the section,
188 identified by keywords. The keywords recognized are `spnum=EXP'
189 (identify this section by the number EXP, an absolute expression),
190 `sort=EXP' (order sections according to this sort key when linking;
191 EXP is an absolute expression), `unloadable' (section contains no
192 loadable data), `notdefined' (this section defined elsewhere), and
193 `private' (data in this section not available to other programs).
195 `.spnum SECNAM'
196 Allocate four bytes of storage, and initialize them with the
197 section number of the section named SECNAM. (You can define the
198 section number with the HPPA `.space' directive.)
200 `.string "STR"'
201 Copy the characters in the string STR to the object file. *Note
202 Strings: Strings, for information on escape sequences you can use
203 in `as' strings.
205 _Warning!_ The HPPA version of `.string' differs from the usual
206 `as' definition: it does _not_ write a zero byte after copying STR.
208 `.stringz "STR"'
209 Like `.string', but appends a zero byte after copying STR to object
210 file.
212 `.subspa NAME [ ,PARAMS ]'
213 `.nsubspa NAME [ ,PARAMS ]'
214 Similar to `.space', but selects a subsection NAME within the
215 current section. You may only specify PARAMS when you create a
216 subsection (in the first instance of `.subspa' for this NAME).
218 If specified, the list PARAMS declares attributes of the
219 subsection, identified by keywords. The keywords recognized are
220 `quad=EXPR' ("quadrant" for this subsection), `align=EXPR'
221 (alignment for beginning of this subsection; a power of two),
222 `access=EXPR' (value for "access rights" field), `sort=EXPR'
223 (sorting order for this subspace in link), `code_only' (subsection
224 contains only code), `unloadable' (subsection cannot be loaded
225 into memory), `common' (subsection is common block), `dup_comm'
226 (initialized data may have duplicate names), or `zero' (subsection
227 is all zeros, do not write in object file).
229 `.nsubspa' always creates a new subspace with the given name, even
230 if one with the same name already exists.
232 `.version "STR"'
233 Write STR as version identifier in object code.
235 \x1f
236 File: as.info, Node: HPPA Opcodes, Prev: HPPA Directives, Up: HPPA-Dependent
238 Opcodes
239 -------
241 For detailed information on the HPPA machine instruction set, see
242 `PA-RISC Architecture and Instruction Set Reference Manual' (HP
243 09740-90039).
245 \x1f
246 File: as.info, Node: ESA/390-Dependent, Next: i386-Dependent, Prev: HPPA-Dependent, Up: Machine Dependencies
248 ESA/390 Dependent Features
249 ==========================
251 * Menu:
253 * ESA/390 Notes:: Notes
254 * ESA/390 Options:: Options
255 * ESA/390 Syntax:: Syntax
256 * ESA/390 Floating Point:: Floating Point
257 * ESA/390 Directives:: ESA/390 Machine Directives
258 * ESA/390 Opcodes:: Opcodes
260 \x1f
261 File: as.info, Node: ESA/390 Notes, Next: ESA/390 Options, Up: ESA/390-Dependent
263 Notes
264 -----
266 The ESA/390 `as' port is currently intended to be a back-end for the
267 GNU CC compiler. It is not HLASM compatible, although it does support
268 a subset of some of the HLASM directives. The only supported binary
269 file format is ELF; none of the usual MVS/VM/OE/USS object file
270 formats, such as ESD or XSD, are supported.
272 When used with the GNU CC compiler, the ESA/390 `as' will produce
273 correct, fully relocated, functional binaries, and has been used to
274 compile and execute large projects. However, many aspects should still
275 be considered experimental; these include shared library support,
276 dynamically loadable objects, and any relocation other than the 31-bit
277 relocation.
279 \x1f
280 File: as.info, Node: ESA/390 Options, Next: ESA/390 Syntax, Prev: ESA/390 Notes, Up: ESA/390-Dependent
282 Options
283 -------
285 `as' has no machine-dependent command-line options for the ESA/390.
287 \x1f
288 File: as.info, Node: ESA/390 Syntax, Next: ESA/390 Floating Point, Prev: ESA/390 Options, Up: ESA/390-Dependent
290 Syntax
291 ------
293 The opcode/operand syntax follows the ESA/390 Principles of Operation
294 manual; assembler directives and general syntax are loosely based on the
295 prevailing AT&T/SVR4/ELF/Solaris style notation. HLASM-style directives
296 are _not_ supported for the most part, with the exception of those
297 described herein.
299 A leading dot in front of directives is optional, and the case of
300 directives is ignored; thus for example, .using and USING have the same
301 effect.
303 A colon may immediately follow a label definition. This is simply
304 for compatibility with how most assembly language programmers write
305 code.
307 `#' is the line comment character.
309 `;' can be used instead of a newline to separate statements.
311 Since `$' has no special meaning, you may use it in symbol names.
313 Registers can be given the symbolic names r0..r15, fp0, fp2, fp4,
314 fp6. By using thesse symbolic names, `as' can detect simple syntax
315 errors. The name rarg or r.arg is a synonym for r11, rtca or r.tca for
316 r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base
317 for r3 and rpgt or r.pgt for r4.
319 `*' is the current location counter. Unlike `.' it is always
320 relative to the last USING directive. Note that this means that
321 expressions cannot use multiplication, as any occurence of `*' will be
322 interpreted as a location counter.
324 All labels are relative to the last USING. Thus, branches to a label
325 always imply the use of base+displacement.
327 Many of the usual forms of address constants / address literals are
328 supported. Thus,
329 .using *,r3
330 L r15,=A(some_routine)
331 LM r6,r7,=V(some_longlong_extern)
332 A r1,=F'12'
333 AH r0,=H'42'
334 ME r6,=E'3.1416'
335 MD r6,=D'3.14159265358979'
336 O r6,=XL4'cacad0d0'
337 .ltorg
338 should all behave as expected: that is, an entry in the literal pool
339 will be created (or reused if it already exists), and the instruction
340 operands will be the displacement into the literal pool using the
341 current base register (as last declared with the `.using' directive).
343 \x1f
344 File: as.info, Node: ESA/390 Floating Point, Next: ESA/390 Directives, Prev: ESA/390 Syntax, Up: ESA/390-Dependent
346 Floating Point
347 --------------
349 The assembler generates only IEEE floating-point numbers. The older
350 floiating point formats are not supported.
352 \x1f
353 File: as.info, Node: ESA/390 Directives, Next: ESA/390 Opcodes, Prev: ESA/390 Floating Point, Up: ESA/390-Dependent
355 ESA/390 Assembler Directives
356 ----------------------------
358 `as' for the ESA/390 supports all of the standard ELF/SVR4 assembler
359 directives that are documented in the main part of this documentation.
360 Several additional directives are supported in order to implement the
361 ESA/390 addressing model. The most important of these are `.using' and
362 `.ltorg'
364 These are the additional directives in `as' for the ESA/390:
366 `.dc'
367 A small subset of the usual DC directive is supported.
369 `.drop REGNO'
370 Stop using REGNO as the base register. The REGNO must have been
371 previously declared with a `.using' directive in the same section
372 as the current section.
374 `.ebcdic STRING'
375 Emit the EBCDIC equivalent of the indicated string. The emitted
376 string will be null terminated. Note that the directives
377 `.string' etc. emit ascii strings by default.
379 `EQU'
380 The standard HLASM-style EQU directive is not supported; however,
381 the standard `as' directive .equ can be used to the same effect.
383 `.ltorg'
384 Dump the literal pool accumulated so far; begin a new literal pool.
385 The literal pool will be written in the current section; in order
386 to generate correct assembly, a `.using' must have been previously
387 specified in the same section.
389 `.using EXPR,REGNO'
390 Use REGNO as the base register for all subsequent RX, RS, and SS
391 form instructions. The EXPR will be evaluated to obtain the base
392 address; usually, EXPR will merely be `*'.
394 This assembler allows two `.using' directives to be simultaneously
395 outstanding, one in the `.text' section, and one in another section
396 (typically, the `.data' section). This feature allows dynamically
397 loaded objects to be implemented in a relatively straightforward
398 way. A `.using' directive must always be specified in the `.text'
399 section; this will specify the base register that will be used for
400 branches in the `.text' section. A second `.using' may be
401 specified in another section; this will specify the base register
402 that is used for non-label address literals. When a second
403 `.using' is specified, then the subsequent `.ltorg' must be put in
404 the same section; otherwise an error will result.
406 Thus, for example, the following code uses `r3' to address branch
407 targets and `r4' to address the literal pool, which has been
408 written to the `.data' section. The is, the constants
409 `=A(some_routine)', `=H'42'' and `=E'3.1416'' will all appear in
410 the `.data' section.
412 .data
413 .using LITPOOL,r4
414 .text
415 BASR r3,0
416 .using *,r3
417 B START
418 .long LITPOOL
419 START:
420 L r4,4(,r3)
421 L r15,=A(some_routine)
422 LTR r15,r15
423 BNE LABEL
424 AH r0,=H'42'
425 LABEL:
426 ME r6,=E'3.1416'
427 .data
428 LITPOOL:
429 .ltorg
431 Note that this dual-`.using' directive semantics extends and is
432 not compatible with HLASM semantics. Note that this assembler
433 directive does not support the full range of HLASM semantics.
435 \x1f
436 File: as.info, Node: ESA/390 Opcodes, Prev: ESA/390 Directives, Up: ESA/390-Dependent
438 Opcodes
439 -------
441 For detailed information on the ESA/390 machine instruction set, see
442 `ESA/390 Principles of Operation' (IBM Publication Number DZ9AR004).
444 \x1f
445 File: as.info, Node: i386-Dependent, Next: i860-Dependent, Prev: ESA/390-Dependent, Up: Machine Dependencies
447 80386 Dependent Features
448 ========================
450 The i386 version `as' supports both the original Intel 386
451 architecture in both 16 and 32-bit mode as well as AMD x86-64
452 architecture extending the Intel architecture to 64-bits.
454 * Menu:
456 * i386-Options:: Options
457 * i386-Syntax:: AT&T Syntax versus Intel Syntax
458 * i386-Mnemonics:: Instruction Naming
459 * i386-Regs:: Register Naming
460 * i386-Prefixes:: Instruction Prefixes
461 * i386-Memory:: Memory References
462 * i386-Jumps:: Handling of Jump Instructions
463 * i386-Float:: Floating Point
464 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
465 * i386-16bit:: Writing 16-bit Code
466 * i386-Arch:: Specifying an x86 CPU architecture
467 * i386-Bugs:: AT&T Syntax bugs
468 * i386-Notes:: Notes
470 \x1f
471 File: as.info, Node: i386-Options, Next: i386-Syntax, Up: i386-Dependent
473 Options
474 -------
476 The i386 version of `as' has a few machine dependent options:
478 `--32 | --64'
479 Select the word size, either 32 bits or 64 bits. Selecting 32-bit
480 implies Intel i386 architecture, while 64-bit implies AMD x86-64
481 architecture.
483 These options are only available with the ELF object file format,
484 and require that the necessary BFD support has been included (on a
485 32-bit platform you have to add -enable-64-bit-bfd to configure
486 enable 64-bit usage and use x86-64 as target platform).
488 \x1f
489 File: as.info, Node: i386-Syntax, Next: i386-Mnemonics, Prev: i386-Options, Up: i386-Dependent
491 AT&T Syntax versus Intel Syntax
492 -------------------------------
494 `as' now supports assembly using Intel assembler syntax.
495 `.intel_syntax' selects Intel mode, and `.att_syntax' switches back to
496 the usual AT&T mode for compatibility with the output of `gcc'. Either
497 of these directives may have an optional argument, `prefix', or
498 `noprefix' specifying whether registers require a `%' prefix. AT&T
499 System V/386 assembler syntax is quite different from Intel syntax. We
500 mention these differences because almost all 80386 documents use Intel
501 syntax. Notable differences between the two syntaxes are:
503 * AT&T immediate operands are preceded by `$'; Intel immediate
504 operands are undelimited (Intel `push 4' is AT&T `pushl $4').
505 AT&T register operands are preceded by `%'; Intel register operands
506 are undelimited. AT&T absolute (as opposed to PC relative)
507 jump/call operands are prefixed by `*'; they are undelimited in
508 Intel syntax.
510 * AT&T and Intel syntax use the opposite order for source and
511 destination operands. Intel `add eax, 4' is `addl $4, %eax'. The
512 `source, dest' convention is maintained for compatibility with
513 previous Unix assemblers. Note that instructions with more than
514 one source operand, such as the `enter' instruction, do _not_ have
515 reversed order. *Note i386-Bugs::.
517 * In AT&T syntax the size of memory operands is determined from the
518 last character of the instruction mnemonic. Mnemonic suffixes of
519 `b', `w', `l' and `q' specify byte (8-bit), word (16-bit), long
520 (32-bit) and quadruple word (64-bit) memory references. Intel
521 syntax accomplishes this by prefixing memory operands (_not_ the
522 instruction mnemonics) with `byte ptr', `word ptr', `dword ptr'
523 and `qword ptr'. Thus, Intel `mov al, byte ptr FOO' is `movb FOO,
524 %al' in AT&T syntax.
526 * Immediate form long jumps and calls are `lcall/ljmp $SECTION,
527 $OFFSET' in AT&T syntax; the Intel syntax is `call/jmp far
528 SECTION:OFFSET'. Also, the far return instruction is `lret
529 $STACK-ADJUST' in AT&T syntax; Intel syntax is `ret far
530 STACK-ADJUST'.
532 * The AT&T assembler does not provide support for multiple section
533 programs. Unix style systems expect all programs to be single
534 sections.
536 \x1f
537 File: as.info, Node: i386-Mnemonics, Next: i386-Regs, Prev: i386-Syntax, Up: i386-Dependent
539 Instruction Naming
540 ------------------
542 Instruction mnemonics are suffixed with one character modifiers which
543 specify the size of operands. The letters `b', `w', `l' and `q'
544 specify byte, word, long and quadruple word operands. If no suffix is
545 specified by an instruction then `as' tries to fill in the missing
546 suffix based on the destination register operand (the last one by
547 convention). Thus, `mov %ax, %bx' is equivalent to `movw %ax, %bx';
548 also, `mov $1, %bx' is equivalent to `movw $1, bx'. Note that this is
549 incompatible with the AT&T Unix assembler which assumes that a missing
550 mnemonic suffix implies long operand size. (This incompatibility does
551 not affect compiler output since compilers always explicitly specify
552 the mnemonic suffix.)
554 Almost all instructions have the same names in AT&T and Intel format.
555 There are a few exceptions. The sign extend and zero extend
556 instructions need two sizes to specify them. They need a size to
557 sign/zero extend _from_ and a size to zero extend _to_. This is
558 accomplished by using two instruction mnemonic suffixes in AT&T syntax.
559 Base names for sign extend and zero extend are `movs...' and `movz...'
560 in AT&T syntax (`movsx' and `movzx' in Intel syntax). The instruction
561 mnemonic suffixes are tacked on to this base name, the _from_ suffix
562 before the _to_ suffix. Thus, `movsbl %al, %edx' is AT&T syntax for
563 "move sign extend _from_ %al _to_ %edx." Possible suffixes, thus, are
564 `bl' (from byte to long), `bw' (from byte to word), `wl' (from word to
565 long), `bq' (from byte to quadruple word), `wq' (from word to quadruple
566 word), and `lq' (from long to quadruple word).
568 The Intel-syntax conversion instructions
570 * `cbw' -- sign-extend byte in `%al' to word in `%ax',
572 * `cwde' -- sign-extend word in `%ax' to long in `%eax',
574 * `cwd' -- sign-extend word in `%ax' to long in `%dx:%ax',
576 * `cdq' -- sign-extend dword in `%eax' to quad in `%edx:%eax',
578 * `cdqe' -- sign-extend dword in `%eax' to quad in `%rax' (x86-64
579 only),
581 * `cdo' -- sign-extend quad in `%rax' to octuple in `%rdx:%rax'
582 (x86-64 only),
584 are called `cbtw', `cwtl', `cwtd', `cltd', `cltq', and `cqto' in AT&T
585 naming. `as' accepts either naming for these instructions.
587 Far call/jump instructions are `lcall' and `ljmp' in AT&T syntax,
588 but are `call far' and `jump far' in Intel convention.
590 \x1f
591 File: as.info, Node: i386-Regs, Next: i386-Prefixes, Prev: i386-Mnemonics, Up: i386-Dependent
593 Register Naming
594 ---------------
596 Register operands are always prefixed with `%'. The 80386 registers
597 consist of
599 * the 8 32-bit registers `%eax' (the accumulator), `%ebx', `%ecx',
600 `%edx', `%edi', `%esi', `%ebp' (the frame pointer), and `%esp'
601 (the stack pointer).
603 * the 8 16-bit low-ends of these: `%ax', `%bx', `%cx', `%dx', `%di',
604 `%si', `%bp', and `%sp'.
606 * the 8 8-bit registers: `%ah', `%al', `%bh', `%bl', `%ch', `%cl',
607 `%dh', and `%dl' (These are the high-bytes and low-bytes of `%ax',
608 `%bx', `%cx', and `%dx')
610 * the 6 section registers `%cs' (code section), `%ds' (data
611 section), `%ss' (stack section), `%es', `%fs', and `%gs'.
613 * the 3 processor control registers `%cr0', `%cr2', and `%cr3'.
615 * the 6 debug registers `%db0', `%db1', `%db2', `%db3', `%db6', and
616 `%db7'.
618 * the 2 test registers `%tr6' and `%tr7'.
620 * the 8 floating point register stack `%st' or equivalently
621 `%st(0)', `%st(1)', `%st(2)', `%st(3)', `%st(4)', `%st(5)',
622 `%st(6)', and `%st(7)'. These registers are overloaded by 8 MMX
623 registers `%mm0', `%mm1', `%mm2', `%mm3', `%mm4', `%mm5', `%mm6'
624 and `%mm7'.
626 * the 8 SSE registers registers `%xmm0', `%xmm1', `%xmm2', `%xmm3',
627 `%xmm4', `%xmm5', `%xmm6' and `%xmm7'.
629 The AMD x86-64 architecture extends the register set by:
631 * enhancing the 8 32-bit registers to 64-bit: `%rax' (the
632 accumulator), `%rbx', `%rcx', `%rdx', `%rdi', `%rsi', `%rbp' (the
633 frame pointer), `%rsp' (the stack pointer)
635 * the 8 extended registers `%r8'-`%r15'.
637 * the 8 32-bit low ends of the extended registers: `%r8d'-`%r15d'
639 * the 8 16-bit low ends of the extended registers: `%r8w'-`%r15w'
641 * the 8 8-bit low ends of the extended registers: `%r8b'-`%r15b'
643 * the 4 8-bit registers: `%sil', `%dil', `%bpl', `%spl'.
645 * the 8 debug registers: `%db8'-`%db15'.
647 * the 8 SSE registers: `%xmm8'-`%xmm15'.
649 \x1f
650 File: as.info, Node: i386-Prefixes, Next: i386-Memory, Prev: i386-Regs, Up: i386-Dependent
652 Instruction Prefixes
653 --------------------
655 Instruction prefixes are used to modify the following instruction.
656 They are used to repeat string instructions, to provide section
657 overrides, to perform bus lock operations, and to change operand and
658 address sizes. (Most instructions that normally operate on 32-bit
659 operands will use 16-bit operands if the instruction has an "operand
660 size" prefix.) Instruction prefixes are best written on the same line
661 as the instruction they act upon. For example, the `scas' (scan string)
662 instruction is repeated with:
664 repne scas %es:(%edi),%al
666 You may also place prefixes on the lines immediately preceding the
667 instruction, but this circumvents checks that `as' does with prefixes,
668 and will not work with all prefixes.
670 Here is a list of instruction prefixes:
672 * Section override prefixes `cs', `ds', `ss', `es', `fs', `gs'.
673 These are automatically added by specifying using the
674 SECTION:MEMORY-OPERAND form for memory references.
676 * Operand/Address size prefixes `data16' and `addr16' change 32-bit
677 operands/addresses into 16-bit operands/addresses, while `data32'
678 and `addr32' change 16-bit ones (in a `.code16' section) into
679 32-bit operands/addresses. These prefixes _must_ appear on the
680 same line of code as the instruction they modify. For example, in
681 a 16-bit `.code16' section, you might write:
683 addr32 jmpl *(%ebx)
685 * The bus lock prefix `lock' inhibits interrupts during execution of
686 the instruction it precedes. (This is only valid with certain
687 instructions; see a 80386 manual for details).
689 * The wait for coprocessor prefix `wait' waits for the coprocessor to
690 complete the current instruction. This should never be needed for
691 the 80386/80387 combination.
693 * The `rep', `repe', and `repne' prefixes are added to string
694 instructions to make them repeat `%ecx' times (`%cx' times if the
695 current address size is 16-bits).
697 * The `rex' family of prefixes is used by x86-64 to encode
698 extensions to i386 instruction set. The `rex' prefix has four
699 bits -- an operand size overwrite (`64') used to change operand
700 size from 32-bit to 64-bit and X, Y and Z extensions bits used to
701 extend the register set.
703 You may write the `rex' prefixes directly. The `rex64xyz'
704 instruction emits `rex' prefix with all the bits set. By omitting
705 the `64', `x', `y' or `z' you may write other prefixes as well.
706 Normally, there is no need to write the prefixes explicitly, since
707 gas will automatically generate them based on the instruction
708 operands.
710 \x1f
711 File: as.info, Node: i386-Memory, Next: i386-Jumps, Prev: i386-Prefixes, Up: i386-Dependent
713 Memory References
714 -----------------
716 An Intel syntax indirect memory reference of the form
718 SECTION:[BASE + INDEX*SCALE + DISP]
720 is translated into the AT&T syntax
722 SECTION:DISP(BASE, INDEX, SCALE)
724 where BASE and INDEX are the optional 32-bit base and index registers,
725 DISP is the optional displacement, and SCALE, taking the values 1, 2,
726 4, and 8, multiplies INDEX to calculate the address of the operand. If
727 no SCALE is specified, SCALE is taken to be 1. SECTION specifies the
728 optional section register for the memory operand, and may override the
729 default section register (see a 80386 manual for section register
730 defaults). Note that section overrides in AT&T syntax _must_ be
731 preceded by a `%'. If you specify a section override which coincides
732 with the default section register, `as' does _not_ output any section
733 register override prefixes to assemble the given instruction. Thus,
734 section overrides can be specified to emphasize which section register
735 is used for a given memory operand.
737 Here are some examples of Intel and AT&T style memory references:
739 AT&T: `-4(%ebp)', Intel: `[ebp - 4]'
740 BASE is `%ebp'; DISP is `-4'. SECTION is missing, and the default
741 section is used (`%ss' for addressing with `%ebp' as the base
742 register). INDEX, SCALE are both missing.
744 AT&T: `foo(,%eax,4)', Intel: `[foo + eax*4]'
745 INDEX is `%eax' (scaled by a SCALE 4); DISP is `foo'. All other
746 fields are missing. The section register here defaults to `%ds'.
748 AT&T: `foo(,1)'; Intel `[foo]'
749 This uses the value pointed to by `foo' as a memory operand. Note
750 that BASE and INDEX are both missing, but there is only _one_ `,'.
751 This is a syntactic exception.
753 AT&T: `%gs:foo'; Intel `gs:foo'
754 This selects the contents of the variable `foo' with section
755 register SECTION being `%gs'.
757 Absolute (as opposed to PC relative) call and jump operands must be
758 prefixed with `*'. If no `*' is specified, `as' always chooses PC
759 relative addressing for jump/call labels.
761 Any instruction that has a memory operand, but no register operand,
762 _must_ specify its size (byte, word, long, or quadruple) with an
763 instruction mnemonic suffix (`b', `w', `l' or `q', respectively).
765 The x86-64 architecture adds an RIP (instruction pointer relative)
766 addressing. This addressing mode is specified by using `rip' as a base
767 register. Only constant offsets are valid. For example:
769 AT&T: `1234(%rip)', Intel: `[rip + 1234]'
770 Points to the address 1234 bytes past the end of the current
771 instruction.
773 AT&T: `symbol(%rip)', Intel: `[rip + symbol]'
774 Points to the `symbol' in RIP relative way, this is shorter than
775 the default absolute addressing.
777 Other addressing modes remain unchanged in x86-64 architecture,
778 except registers used are 64-bit instead of 32-bit.
780 \x1f
781 File: as.info, Node: i386-Jumps, Next: i386-Float, Prev: i386-Memory, Up: i386-Dependent
783 Handling of Jump Instructions
784 -----------------------------
786 Jump instructions are always optimized to use the smallest possible
787 displacements. This is accomplished by using byte (8-bit) displacement
788 jumps whenever the target is sufficiently close. If a byte displacement
789 is insufficient a long displacement is used. We do not support word
790 (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
791 instruction with the `data16' instruction prefix), since the 80386
792 insists upon masking `%eip' to 16 bits after the word displacement is
793 added. (See also *note i386-Arch::)
795 Note that the `jcxz', `jecxz', `loop', `loopz', `loope', `loopnz'
796 and `loopne' instructions only come in byte displacements, so that if
797 you use these instructions (`gcc' does not use them) you may get an
798 error message (and incorrect code). The AT&T 80386 assembler tries to
799 get around this problem by expanding `jcxz foo' to
801 jcxz cx_zero
802 jmp cx_nonzero
803 cx_zero: jmp foo
804 cx_nonzero:
806 \x1f
807 File: as.info, Node: i386-Float, Next: i386-SIMD, Prev: i386-Jumps, Up: i386-Dependent
809 Floating Point
810 --------------
812 All 80387 floating point types except packed BCD are supported.
813 (BCD support may be added without much difficulty). These data types
814 are 16-, 32-, and 64- bit integers, and single (32-bit), double
815 (64-bit), and extended (80-bit) precision floating point. Each
816 supported type has an instruction mnemonic suffix and a constructor
817 associated with it. Instruction mnemonic suffixes specify the operand's
818 data type. Constructors build these data types into memory.
820 * Floating point constructors are `.float' or `.single', `.double',
821 and `.tfloat' for 32-, 64-, and 80-bit formats. These correspond
822 to instruction mnemonic suffixes `s', `l', and `t'. `t' stands for
823 80-bit (ten byte) real. The 80387 only supports this format via
824 the `fldt' (load 80-bit real to stack top) and `fstpt' (store
825 80-bit real and pop stack) instructions.
827 * Integer constructors are `.word', `.long' or `.int', and `.quad'
828 for the 16-, 32-, and 64-bit integer formats. The corresponding
829 instruction mnemonic suffixes are `s' (single), `l' (long), and
830 `q' (quad). As with the 80-bit real format, the 64-bit `q' format
831 is only present in the `fildq' (load quad integer to stack top)
832 and `fistpq' (store quad integer and pop stack) instructions.
834 Register to register operations should not use instruction mnemonic
835 suffixes. `fstl %st, %st(1)' will give a warning, and be assembled as
836 if you wrote `fst %st, %st(1)', since all register to register
837 operations use 80-bit floating point operands. (Contrast this with
838 `fstl %st, mem', which converts `%st' from 80-bit to 64-bit floating
839 point format, then stores the result in the 4 byte location `mem')
841 \x1f
842 File: as.info, Node: i386-SIMD, Next: i386-16bit, Prev: i386-Float, Up: i386-Dependent
844 Intel's MMX and AMD's 3DNow! SIMD Operations
845 --------------------------------------------
847 `as' supports Intel's MMX instruction set (SIMD instructions for
848 integer data), available on Intel's Pentium MMX processors and Pentium
849 II processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and
850 probably others. It also supports AMD's 3DNow! instruction set (SIMD
851 instructions for 32-bit floating point data) available on AMD's K6-2
852 processor and possibly others in the future.
854 Currently, `as' does not support Intel's floating point SIMD, Katmai
855 (KNI).
857 The eight 64-bit MMX operands, also used by 3DNow!, are called
858 `%mm0', `%mm1', ... `%mm7'. They contain eight 8-bit integers, four
859 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
860 floating point values. The MMX registers cannot be used at the same
861 time as the floating point stack.
863 See Intel and AMD documentation, keeping in mind that the operand
864 order in instructions is reversed from the Intel syntax.
866 \x1f
867 File: as.info, Node: i386-16bit, Next: i386-Arch, Prev: i386-SIMD, Up: i386-Dependent
869 Writing 16-bit Code
870 -------------------
872 While `as' normally writes only "pure" 32-bit i386 code or 64-bit
873 x86-64 code depending on the default configuration, it also supports
874 writing code to run in real mode or in 16-bit protected mode code
875 segments. To do this, put a `.code16' or `.code16gcc' directive before
876 the assembly language instructions to be run in 16-bit mode. You can
877 switch `as' back to writing normal 32-bit code with the `.code32'
878 directive.
880 `.code16gcc' provides experimental support for generating 16-bit
881 code from gcc, and differs from `.code16' in that `call', `ret',
882 `enter', `leave', `push', `pop', `pusha', `popa', `pushf', and `popf'
883 instructions default to 32-bit size. This is so that the stack pointer
884 is manipulated in the same way over function calls, allowing access to
885 function parameters at the same stack offsets as in 32-bit mode.
886 `.code16gcc' also automatically adds address size prefixes where
887 necessary to use the 32-bit addressing modes that gcc generates.
889 The code which `as' generates in 16-bit mode will not necessarily
890 run on a 16-bit pre-80386 processor. To write code that runs on such a
891 processor, you must refrain from using _any_ 32-bit constructs which
892 require `as' to output address or operand size prefixes.
894 Note that writing 16-bit code instructions by explicitly specifying a
895 prefix or an instruction mnemonic suffix within a 32-bit code section
896 generates different machine instructions than those generated for a
897 16-bit code segment. In a 32-bit code section, the following code
898 generates the machine opcode bytes `66 6a 04', which pushes the value
899 `4' onto the stack, decrementing `%esp' by 2.
901 pushw $4
903 The same code in a 16-bit code section would generate the machine
904 opcode bytes `6a 04' (ie. without the operand size prefix), which is
905 correct since the processor default operand size is assumed to be 16
906 bits in a 16-bit code section.
908 \x1f
909 File: as.info, Node: i386-Bugs, Next: i386-Notes, Prev: i386-Arch, Up: i386-Dependent
911 AT&T Syntax bugs
912 ----------------
914 The UnixWare assembler, and probably other AT&T derived ix86 Unix
915 assemblers, generate floating point instructions with reversed source
916 and destination registers in certain cases. Unfortunately, gcc and
917 possibly many other programs use this reversed syntax, so we're stuck
918 with it.
920 For example
922 fsub %st,%st(3)
924 results in `%st(3)' being updated to `%st - %st(3)' rather than the
925 expected `%st(3) - %st'. This happens with all the non-commutative
926 arithmetic floating point operations with two register operands where
927 the source register is `%st' and the destination register is `%st(i)'.
929 \x1f
930 File: as.info, Node: i386-Arch, Next: i386-Bugs, Prev: i386-16bit, Up: i386-Dependent
932 Specifying CPU Architecture
933 ---------------------------
935 `as' may be told to assemble for a particular CPU architecture with
936 the `.arch CPU_TYPE' directive. This directive enables a warning when
937 gas detects an instruction that is not supported on the CPU specified.
938 The choices for CPU_TYPE are:
940 `i8086' `i186' `i286' `i386'
941 `i486' `i586' `i686' `pentium'
942 `pentiumpro' `pentium4' `k6' `athlon'
943 `sledgehammer'
945 Apart from the warning, there are only two other effects on `as'
946 operation; Firstly, if you specify a CPU other than `i486', then shift
947 by one instructions such as `sarl $1, %eax' will automatically use a
948 two byte opcode sequence. The larger three byte opcode sequence is
949 used on the 486 (and when no architecture is specified) because it
950 executes faster on the 486. Note that you can explicitly request the
951 two byte opcode by writing `sarl %eax'. Secondly, if you specify
952 `i8086', `i186', or `i286', _and_ `.code16' or `.code16gcc' then byte
953 offset conditional jumps will be promoted when necessary to a two
954 instruction sequence consisting of a conditional jump of the opposite
955 sense around an unconditional jump to the target.
957 Following the CPU architecture, you may specify `jumps' or `nojumps'
958 to control automatic promotion of conditional jumps. `jumps' is the
959 default, and enables jump promotion; All external jumps will be of the
960 long variety, and file-local jumps will be promoted as necessary.
961 (*note i386-Jumps::) `nojumps' leaves external conditional jumps as
962 byte offset jumps, and warns about file-local conditional jumps that
963 `as' promotes. Unconditional jumps are treated as for `jumps'.
965 For example
967 .arch i8086,nojumps
969 \x1f
970 File: as.info, Node: i386-Notes, Prev: i386-Bugs, Up: i386-Dependent
972 Notes
973 -----
975 There is some trickery concerning the `mul' and `imul' instructions
976 that deserves mention. The 16-, 32-, 64- and 128-bit expanding
977 multiplies (base opcode `0xf6'; extension 4 for `mul' and 5 for `imul')
978 can be output only in the one operand form. Thus, `imul %ebx, %eax'
979 does _not_ select the expanding multiply; the expanding multiply would
980 clobber the `%edx' register, and this would confuse `gcc' output. Use
981 `imul %ebx' to get the 64-bit product in `%edx:%eax'.
983 We have added a two operand form of `imul' when the first operand is
984 an immediate mode expression and the second operand is a register.
985 This is just a shorthand, so that, multiplying `%eax' by 69, for
986 example, can be done with `imul $69, %eax' rather than `imul $69, %eax,
987 %eax'.
989 \x1f
990 File: as.info, Node: i860-Dependent, Next: i960-Dependent, Prev: i386-Dependent, Up: Machine Dependencies
992 Intel i860 Dependent Features
993 =============================
995 * Menu:
997 * Notes-i860:: i860 Notes
998 * Options-i860:: i860 Command-line Options
999 * Directives-i860:: i860 Machine Directives
1000 * Opcodes for i860:: i860 Opcodes
1002 \x1f
1003 File: as.info, Node: Notes-i860, Next: Options-i860, Up: i860-Dependent
1005 i860 Notes
1006 ----------
1008 This is a fairly complete i860 assembler which is compatible with the
1009 UNIX System V/860 Release 4 assembler. However, it does not currently
1010 support SVR4 PIC (i.e., `@GOT, @GOTOFF, @PLT').
1012 Like the SVR4/860 assembler, the output object format is ELF32.
1013 Currently, this is the only supported object format. If there is
1014 sufficient interest, other formats such as COFF may be implemented.
1016 \x1f
1017 File: as.info, Node: Options-i860, Next: Directives-i860, Prev: Notes-i860, Up: i860-Dependent
1019 i860 Command-line Options
1020 -------------------------
1022 SVR4 compatibility options
1023 ..........................
1025 `-V'
1026 Print assembler version.
1028 `-Qy'
1029 Ignored.
1031 `-Qn'
1032 Ignored.
1034 Other options
1035 .............
1037 `-EL'
1038 Select little endian output (this is the default).
1040 `-EB'
1041 Select big endian output. Note that the i860 always reads
1042 instructions as little endian data, so this option only effects
1043 data and not instructions.
1045 `-mwarn-expand'
1046 Emit a warning message if any pseudo-instruction expansions
1047 occurred. For example, a `or' instruction with an immediate
1048 larger than 16-bits will be expanded into two instructions. This
1049 is a very undesirable feature to rely on, so this flag can help
1050 detect any code where it happens. One use of it, for instance, has
1051 been to find and eliminate any place where `gcc' may emit these
1052 pseudo-instructions.
1054 \x1f
1055 File: as.info, Node: Directives-i860, Next: Opcodes for i860, Prev: Options-i860, Up: i860-Dependent
1057 i860 Machine Directives
1058 -----------------------
1060 `.dual'
1061 Enter dual instruction mode. While this directive is supported, the
1062 preferred way to use dual instruction mode is to explicitly code
1063 the dual bit with the `d.' prefix.
1065 `.enddual'
1066 Exit dual instruction mode. While this directive is supported, the
1067 preferred way to use dual instruction mode is to explicitly code
1068 the dual bit with the `d.' prefix.
1070 `.atmp'
1071 Change the temporary register used when expanding pseudo
1072 operations. The default register is `r31'.
1074 \x1f
1075 File: as.info, Node: Opcodes for i860, Prev: Directives-i860, Up: i860-Dependent
1077 i860 Opcodes
1078 ------------
1080 All of the Intel i860 machine instructions are supported. Please see
1081 either _i860 Microprocessor Programmer's Reference Manual_ or _i860
1082 Microprocessor Architecture_ for more information.
1084 Other instruction support (pseudo-instructions)
1085 ...............................................
1087 For compatibility with some other i860 assemblers, a number of
1088 pseudo-instructions are supported. While these are supported, they are
1089 a very undesirable feature that should be avoided - in particular, when
1090 they result in an expansion to multiple actual i860 instructions. Below
1091 are the pseudo-instructions that result in expansions.
1092 * Load large immediate into general register:
1094 The pseudo-instruction `mov imm,%rn' (where the immediate does not
1095 fit within a signed 16-bit field) will be expanded into:
1096 orh large_imm@h,%r0,%rn
1097 or large_imm@l,%rn,%rn
1099 * Load/store with relocatable address expression:
1101 For example, the pseudo-instruction `ld.b addr,%rn' will be
1102 expanded into:
1103 orh addr_exp@ha,%r0,%r31
1104 ld.l addr_exp@l(%r31),%rn
1106 The analogous expansions apply to `ld.x, st.x, fld.x, pfld.x,
1107 fst.x', and `pst.x' as well.
1109 * Signed large immediate with add/subtract:
1111 If any of the arithmetic operations `adds, addu, subs, subu' are
1112 used with an immediate larger than 16-bits (signed), then they
1113 will be expanded. For instance, the pseudo-instruction `adds
1114 large_imm,%rx,%rn' expands to:
1115 orh large_imm@h,%r0,%r31
1116 or large_imm@l,%r31,%r31
1117 adds %r31,%rx,%rn
1119 * Unsigned large immediate with logical operations:
1121 Logical operations (`or, andnot, or, xor') also result in
1122 expansions. The pseudo-instruction `or large_imm,%rx,%rn' results
1123 in:
1124 orh large_imm@h,%rx,%r31
1125 or large_imm@l,%r31,%rn
1127 Similarly for the others, except for `and' which expands to:
1128 andnot (-1 - large_imm)@h,%rx,%r31
1129 andnot (-1 - large_imm)@l,%r31,%rn
1131 \x1f
1132 File: as.info, Node: i960-Dependent, Next: M32R-Dependent, Prev: i860-Dependent, Up: Machine Dependencies
1134 Intel 80960 Dependent Features
1135 ==============================
1137 * Menu:
1139 * Options-i960:: i960 Command-line Options
1140 * Floating Point-i960:: Floating Point
1141 * Directives-i960:: i960 Machine Directives
1142 * Opcodes for i960:: i960 Opcodes
1144 \x1f
1145 File: as.info, Node: Options-i960, Next: Floating Point-i960, Up: i960-Dependent
1147 i960 Command-line Options
1148 -------------------------
1150 `-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC'
1151 Select the 80960 architecture. Instructions or features not
1152 supported by the selected architecture cause fatal errors.
1154 `-ACA' is equivalent to `-ACA_A'; `-AKC' is equivalent to `-AMC'.
1155 Synonyms are provided for compatibility with other tools.
1157 If you do not specify any of these options, `as' generates code
1158 for any instruction or feature that is supported by _some_ version
1159 of the 960 (even if this means mixing architectures!). In
1160 principle, `as' attempts to deduce the minimal sufficient
1161 processor type if none is specified; depending on the object code
1162 format, the processor type may be recorded in the object file. If
1163 it is critical that the `as' output match a specific architecture,
1164 specify that architecture explicitly.
1166 `-b'
1167 Add code to collect information about conditional branches taken,
1168 for later optimization using branch prediction bits. (The
1169 conditional branch instructions have branch prediction bits in the
1170 CA, CB, and CC architectures.) If BR represents a conditional
1171 branch instruction, the following represents the code generated by
1172 the assembler when `-b' is specified:
1174 call INCREMENT ROUTINE
1175 .word 0 # pre-counter
1176 Label: BR
1177 call INCREMENT ROUTINE
1178 .word 0 # post-counter
1180 The counter following a branch records the number of times that
1181 branch was _not_ taken; the differenc between the two counters is
1182 the number of times the branch _was_ taken.
1184 A table of every such `Label' is also generated, so that the
1185 external postprocessor `gbr960' (supplied by Intel) can locate all
1186 the counters. This table is always labelled `__BRANCH_TABLE__';
1187 this is a local symbol to permit collecting statistics for many
1188 separate object files. The table is word aligned, and begins with
1189 a two-word header. The first word, initialized to 0, is used in
1190 maintaining linked lists of branch tables. The second word is a
1191 count of the number of entries in the table, which follow
1192 immediately: each is a word, pointing to one of the labels
1193 illustrated above.
1195 +------------+------------+------------+ ... +------------+
1196 | | | | | |
1197 | *NEXT | COUNT: N | *BRLAB 1 | | *BRLAB N |
1198 | | | | | |
1199 +------------+------------+------------+ ... +------------+
1201 __BRANCH_TABLE__ layout
1203 The first word of the header is used to locate multiple branch
1204 tables, since each object file may contain one. Normally the links
1205 are maintained with a call to an initialization routine, placed at
1206 the beginning of each function in the file. The GNU C compiler
1207 generates these calls automatically when you give it a `-b' option.
1208 For further details, see the documentation of `gbr960'.
1210 `-no-relax'
1211 Normally, Compare-and-Branch instructions with targets that require
1212 displacements greater than 13 bits (or that have external targets)
1213 are replaced with the corresponding compare (or `chkbit') and
1214 branch instructions. You can use the `-no-relax' option to
1215 specify that `as' should generate errors instead, if the target
1216 displacement is larger than 13 bits.
1218 This option does not affect the Compare-and-Jump instructions; the
1219 code emitted for them is _always_ adjusted when necessary
1220 (depending on displacement size), regardless of whether you use
1221 `-no-relax'.
1223 \x1f
1224 File: as.info, Node: Floating Point-i960, Next: Directives-i960, Prev: Options-i960, Up: i960-Dependent
1226 Floating Point
1227 --------------
1229 `as' generates IEEE floating-point numbers for the directives
1230 `.float', `.double', `.extended', and `.single'.