1 /* Instruction printing code for the ARM
2 Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
6 This file is part of libopcodes.
8 This program is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2 of the License, or (at your option)
13 This program is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
26 #include "coff/internal.h"
30 /* FIXME: This shouldn't be done here */
32 #include "elf/internal.h"
36 #define streq(a,b) (strcmp ((a), (b)) == 0)
40 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
44 #define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
47 static char * arm_conditional
[] =
48 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
49 "hi", "ls", "ge", "lt", "gt", "le", "", "nv"};
54 const char * description
;
55 const char * reg_names
[16];
59 static arm_regname regnames
[] =
61 { "raw" , "Select raw register names",
62 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
63 { "std", "Select register names used in ARM's ISA documentation",
64 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65 { "apcs", "Select register names used in the APCS",
66 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
67 { "atpcs", "Select register names used in the ATPCS",
68 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
69 { "special-atpcs", "Select special register names used in the ATPCS",
70 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
73 /* Default to standard register name set. */
74 static unsigned int regname_selected
= 1;
76 #define NUM_ARM_REGNAMES NUM_ELEM (regnames)
77 #define arm_regnames regnames[regname_selected].reg_names
79 static boolean force_thumb
= false;
81 static char * arm_fp_const
[] =
82 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
84 static char * arm_shift
[] =
85 {"lsl", "lsr", "asr", "ror"};
87 /* Forward declarations. */
88 static void arm_decode_shift
PARAMS ((long, fprintf_ftype
, void *));
89 static int print_insn_arm
PARAMS ((bfd_vma
, struct disassemble_info
*, long));
90 static int print_insn_thumb
PARAMS ((bfd_vma
, struct disassemble_info
*, long));
91 static void parse_disassembler_options
PARAMS ((char *));
92 static int print_insn
PARAMS ((bfd_vma
, struct disassemble_info
*, boolean
));
93 int get_arm_regname_num_options (void);
94 int set_arm_regname_option (int option
);
95 int get_arm_regnames (int option
, const char **setname
,
96 const char **setdescription
,
97 const char ***register_names
);
101 get_arm_regname_num_options (void)
103 return NUM_ARM_REGNAMES
;
107 set_arm_regname_option (int option
)
109 int old
= regname_selected
;
110 regname_selected
= option
;
115 get_arm_regnames (int option
, const char **setname
,
116 const char **setdescription
,
117 const char ***register_names
)
119 *setname
= regnames
[option
].name
;
120 *setdescription
= regnames
[option
].description
;
121 *register_names
= regnames
[option
].reg_names
;
126 arm_decode_shift (given
, func
, stream
)
131 func (stream
, "%s", arm_regnames
[given
& 0xf]);
133 if ((given
& 0xff0) != 0)
135 if ((given
& 0x10) == 0)
137 int amount
= (given
& 0xf80) >> 7;
138 int shift
= (given
& 0x60) >> 5;
144 func (stream
, ", rrx");
151 func (stream
, ", %s #%d", arm_shift
[shift
], amount
);
154 func (stream
, ", %s %s", arm_shift
[(given
& 0x60) >> 5],
155 arm_regnames
[(given
& 0xf00) >> 8]);
159 /* Print one instruction from PC on INFO->STREAM.
160 Return the size of the instruction (always 4 on ARM). */
162 print_insn_arm (pc
, info
, given
)
164 struct disassemble_info
* info
;
167 struct arm_opcode
* insn
;
168 void * stream
= info
->stream
;
169 fprintf_ftype func
= info
->fprintf_func
;
171 for (insn
= arm_opcodes
; insn
->assembler
; insn
++)
173 if ((given
& insn
->mask
) == insn
->value
)
177 for (c
= insn
->assembler
; *c
; c
++)
188 if (((given
& 0x000f0000) == 0x000f0000)
189 && ((given
& 0x02000000) == 0))
191 int offset
= given
& 0xfff;
193 func (stream
, "[pc");
195 if (given
& 0x01000000)
197 if ((given
& 0x00800000) == 0)
201 func (stream
, ", #%x]", offset
);
205 /* Cope with the possibility of write-back
206 being used. Probably a very dangerous thing
207 for the programmer to do, but who are we to
209 if (given
& 0x00200000)
215 func (stream
, "], #%x", offset
);
217 offset
= pc
+ 8; /* ie ignore the offset. */
220 func (stream
, "\t; ");
221 info
->print_address_func (offset
, info
);
226 arm_regnames
[(given
>> 16) & 0xf]);
227 if ((given
& 0x01000000) != 0)
229 if ((given
& 0x02000000) == 0)
231 int offset
= given
& 0xfff;
233 func (stream
, ", %s#%d",
234 (((given
& 0x00800000) == 0)
235 ? "-" : ""), offset
);
239 func (stream
, ", %s",
240 (((given
& 0x00800000) == 0)
242 arm_decode_shift (given
, func
, stream
);
246 ((given
& 0x00200000) != 0) ? "!" : "");
250 if ((given
& 0x02000000) == 0)
252 int offset
= given
& 0xfff;
254 func (stream
, "], %s#%d",
255 (((given
& 0x00800000) == 0)
256 ? "-" : ""), offset
);
262 func (stream
, "], %s",
263 (((given
& 0x00800000) == 0)
265 arm_decode_shift (given
, func
, stream
);
272 if ((given
& 0x004f0000) == 0x004f0000)
274 /* PC relative with immediate offset. */
275 int offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
277 if ((given
& 0x00800000) == 0)
280 func (stream
, "[pc, #%x]\t; ", offset
);
282 (*info
->print_address_func
)
283 (offset
+ pc
+ 8, info
);
288 arm_regnames
[(given
>> 16) & 0xf]);
289 if ((given
& 0x01000000) != 0)
292 if ((given
& 0x00400000) == 0x00400000)
295 int offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
297 func (stream
, ", %s#%d",
298 (((given
& 0x00800000) == 0)
299 ? "-" : ""), offset
);
304 func (stream
, ", %s%s",
305 (((given
& 0x00800000) == 0)
307 arm_regnames
[given
& 0xf]);
311 ((given
& 0x00200000) != 0) ? "!" : "");
316 if ((given
& 0x00400000) == 0x00400000)
319 int offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
321 func (stream
, "], %s#%d",
322 (((given
& 0x00800000) == 0)
323 ? "-" : ""), offset
);
330 func (stream
, "], %s%s",
331 (((given
& 0x00800000) == 0)
333 arm_regnames
[given
& 0xf]);
340 (*info
->print_address_func
)
341 (BDISP (given
) * 4 + pc
+ 8, info
);
346 arm_conditional
[(given
>> 28) & 0xf]);
355 for (reg
= 0; reg
< 16; reg
++)
356 if ((given
& (1 << reg
)) != 0)
361 func (stream
, "%s", arm_regnames
[reg
]);
368 if ((given
& 0x02000000) != 0)
370 int rotate
= (given
& 0xf00) >> 7;
371 int immed
= (given
& 0xff);
372 immed
= (((immed
<< (32 - rotate
))
373 | (immed
>> rotate
)) & 0xffffffff);
374 func (stream
, "#%d\t; 0x%x", immed
, immed
);
377 arm_decode_shift (given
, func
, stream
);
381 if ((given
& 0x0000f000) == 0x0000f000)
386 if ((given
& 0x01200000) == 0x00200000)
391 if ((given
& 0x00000020) == 0x00000020)
398 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
399 if ((given
& 0x01000000) != 0)
401 int offset
= given
& 0xff;
403 func (stream
, ", %s#%d]%s",
404 ((given
& 0x00800000) == 0 ? "-" : ""),
406 ((given
& 0x00200000) != 0 ? "!" : ""));
412 int offset
= given
& 0xff;
414 func (stream
, "], %s#%d",
415 ((given
& 0x00800000) == 0 ? "-" : ""),
423 switch (given
& 0x000f0000)
426 func (stream
, "_???");
429 func (stream
, "_all");
447 switch (given
& 0x00408000)
464 switch (given
& 0x00080080)
476 func (stream
, _("<illegal precision>"));
481 switch (given
& 0x00408000)
498 switch (given
& 0x60)
514 case '0': case '1': case '2': case '3': case '4':
515 case '5': case '6': case '7': case '8': case '9':
517 int bitstart
= *c
++ - '0';
519 while (*c
>= '0' && *c
<= '9')
520 bitstart
= (bitstart
* 10) + *c
++ - '0';
527 while (*c
>= '0' && *c
<= '9')
528 bitend
= (bitend
* 10) + *c
++ - '0';
539 reg
= given
>> bitstart
;
540 reg
&= (2 << (bitend
- bitstart
)) - 1;
542 func (stream
, "%s", arm_regnames
[reg
]);
549 reg
= given
>> bitstart
;
550 reg
&= (2 << (bitend
- bitstart
)) - 1;
552 func (stream
, "%d", reg
);
559 reg
= given
>> bitstart
;
560 reg
&= (2 << (bitend
- bitstart
)) - 1;
562 func (stream
, "0x%08x", reg
);
564 /* Some SWI instructions have special
566 if ((given
& 0x0fffffff) == 0x0FF00000)
567 func (stream
, "\t; IMB");
568 else if ((given
& 0x0fffffff) == 0x0FF00001)
569 func (stream
, "\t; IMBRange");
576 reg
= given
>> bitstart
;
577 reg
&= (2 << (bitend
- bitstart
)) - 1;
579 func (stream
, "%01x", reg
& 0xf);
586 reg
= given
>> bitstart
;
587 reg
&= (2 << (bitend
- bitstart
)) - 1;
591 arm_fp_const
[reg
& 7]);
593 func (stream
, "f%d", reg
);
603 if ((given
& (1 << bitstart
)) == 0)
604 func (stream
, "%c", *c
);
608 if ((given
& (1 << bitstart
)) != 0)
609 func (stream
, "%c", *c
);
613 if ((given
& (1 << bitstart
)) != 0)
614 func (stream
, "%c", *c
++);
616 func (stream
, "%c", *++c
);
629 func (stream
, "%c", *c
);
637 /* Print one instruction from PC on INFO->STREAM.
638 Return the size of the instruction. */
640 print_insn_thumb (pc
, info
, given
)
642 struct disassemble_info
* info
;
645 struct thumb_opcode
* insn
;
646 void * stream
= info
->stream
;
647 fprintf_ftype func
= info
->fprintf_func
;
649 for (insn
= thumb_opcodes
; insn
->assembler
; insn
++)
651 if ((given
& insn
->mask
) == insn
->value
)
653 char * c
= insn
->assembler
;
655 /* Special processing for Thumb 2 instruction BL sequence: */
656 if (!*c
) /* Check for empty (not NULL) assembler string. */
658 info
->bytes_per_chunk
= 4;
659 info
->bytes_per_line
= 4;
661 func (stream
, "bl\t");
663 info
->print_address_func (BDISP23 (given
) * 2 + pc
+ 4, info
);
668 info
->bytes_per_chunk
= 2;
669 info
->bytes_per_line
= 4;
690 reg
= (given
>> 3) & 0x7;
691 if (given
& (1 << 6))
694 func (stream
, "%s", arm_regnames
[reg
]);
703 if (given
& (1 << 7))
706 func (stream
, "%s", arm_regnames
[reg
]);
712 arm_conditional
[(given
>> 8) & 0xf]);
716 if (given
& (1 << 8))
720 if (*c
== 'O' && (given
& (1 << 8)))
730 /* It would be nice if we could spot
731 ranges, and generate the rS-rE format: */
732 for (reg
= 0; (reg
< 8); reg
++)
733 if ((given
& (1 << reg
)) != 0)
738 func (stream
, "%s", arm_regnames
[reg
]);
746 func (stream
, arm_regnames
[14] /* "lr" */);
753 func (stream
, arm_regnames
[15] /* "pc" */);
761 case '0': case '1': case '2': case '3': case '4':
762 case '5': case '6': case '7': case '8': case '9':
764 int bitstart
= *c
++ - '0';
767 while (*c
>= '0' && *c
<= '9')
768 bitstart
= (bitstart
* 10) + *c
++ - '0';
777 while (*c
>= '0' && *c
<= '9')
778 bitend
= (bitend
* 10) + *c
++ - '0';
781 reg
= given
>> bitstart
;
782 reg
&= (2 << (bitend
- bitstart
)) - 1;
786 func (stream
, "%s", arm_regnames
[reg
]);
790 func (stream
, "%d", reg
);
794 func (stream
, "%d", reg
<< 1);
798 func (stream
, "%d", reg
<< 2);
802 /* PC-relative address -- the bottom two
803 bits of the address are dropped
804 before the calculation. */
805 info
->print_address_func
806 (((pc
+ 4) & ~3) + (reg
<< 2), info
);
810 func (stream
, "0x%04x", reg
);
814 reg
= ((reg
^ (1 << bitend
)) - (1 << bitend
));
815 func (stream
, "%d", reg
);
819 reg
= ((reg
^ (1 << bitend
)) - (1 << bitend
));
820 (*info
->print_address_func
)
821 (reg
* 2 + pc
+ 4, info
);
832 if ((given
& (1 << bitstart
)) != 0)
833 func (stream
, "%c", *c
);
838 if ((given
& (1 << bitstart
)) != 0)
839 func (stream
, "%c", *c
++);
841 func (stream
, "%c", *++c
);
855 func (stream
, "%c", *c
);
866 /* Parse an individual disassembler option. */
868 parse_arm_disassembler_option (option
)
874 if (strneq (option
, "reg-names-", 10))
880 for (i
= NUM_ARM_REGNAMES
; i
--;)
881 if (streq (option
, regnames
[i
].name
))
883 regname_selected
= i
;
888 fprintf (stderr
, _("Unrecognised register name set: %s\n"), option
);
890 else if (streq (option
, "force-thumb"))
892 else if (streq (option
, "no-force-thumb"))
895 fprintf (stderr
, _("Unrecognised disassembler option: %s\n"), option
);
900 /* Parse the string of disassembler options, spliting it at whitespaces. */
902 parse_disassembler_options (options
)
912 space
= strchr (options
, ' ');
917 parse_arm_disassembler_option (options
);
922 parse_arm_disassembler_option (options
);
927 /* NOTE: There are no checks in these routines that
928 the relevant number of data bytes exist. */
930 print_insn (pc
, info
, little
)
932 struct disassemble_info
* info
;
940 if (info
->disassembler_options
)
942 parse_disassembler_options (info
->disassembler_options
);
944 /* To avoid repeated parsing of these options, we remove them here. */
945 info
->disassembler_options
= NULL
;
948 is_thumb
= force_thumb
;
950 if (!is_thumb
&& info
->symbols
!= NULL
)
952 if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_coff_flavour
)
954 coff_symbol_type
* cs
;
956 cs
= coffsymbol (*info
->symbols
);
957 is_thumb
= ( cs
->native
->u
.syment
.n_sclass
== C_THUMBEXT
958 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTAT
959 || cs
->native
->u
.syment
.n_sclass
== C_THUMBLABEL
960 || cs
->native
->u
.syment
.n_sclass
== C_THUMBEXTFUNC
961 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTATFUNC
);
963 else if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_elf_flavour
)
965 elf_symbol_type
* es
;
968 es
= *(elf_symbol_type
**)(info
->symbols
);
969 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
971 is_thumb
= (type
== STT_ARM_TFUNC
) || (type
== STT_ARM_16BIT
);
975 info
->bytes_per_chunk
= 4;
976 info
->display_endian
= little
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
980 status
= info
->read_memory_func (pc
, (bfd_byte
*) &b
[0], 4, info
);
981 if (status
!= 0 && is_thumb
)
983 info
->bytes_per_chunk
= 2;
985 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 2, info
);
991 info
->memory_error_func (status
, pc
, info
);
995 given
= (b
[0]) | (b
[1] << 8) | (b
[2] << 16) | (b
[3] << 24);
999 status
= info
->read_memory_func
1000 (pc
& ~ 0x3, (bfd_byte
*) &b
[0], 4, info
);
1003 info
->memory_error_func (status
, pc
, info
);
1011 given
= (b
[2] << 8) | b
[3];
1013 status
= info
->read_memory_func
1014 ((pc
+ 4) & ~ 0x3, (bfd_byte
*) b
, 4, info
);
1017 info
->memory_error_func (status
, pc
+ 4, info
);
1021 given
|= (b
[0] << 24) | (b
[1] << 16);
1024 given
= (b
[0] << 8) | b
[1] | (b
[2] << 24) | (b
[3] << 16);
1027 given
= (b
[0] << 24) | (b
[1] << 16) | (b
[2] << 8) | (b
[3]);
1031 status
= print_insn_thumb (pc
, info
, given
);
1033 status
= print_insn_arm (pc
, info
, given
);
1039 print_insn_big_arm (pc
, info
)
1041 struct disassemble_info
* info
;
1043 return print_insn (pc
, info
, false);
1047 print_insn_little_arm (pc
, info
)
1049 struct disassemble_info
* info
;
1051 return print_insn (pc
, info
, true);
1055 print_arm_disassembler_options (FILE * stream
)
1059 fprintf (stream
, _("\n\
1060 The following ARM specific disassembler options are supported for use with\n\
1061 the -M switch:\n"));
1063 for (i
= NUM_ARM_REGNAMES
; i
--;)
1064 fprintf (stream
, " reg-names-%s %*c%s\n",
1066 14 - strlen (regnames
[i
].name
), ' ',
1067 regnames
[i
].description
);
1069 fprintf (stream
, " force-thumb Assume all insns are Thumb insns\n");
1070 fprintf (stream
, " no-force-thumb Examine preceeding label to determine an insn's type\n\n");