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* m32c-desc.c: Regenerate.
[binutils.git] / opcodes / m32c-dis.c
blob43f93e2b2b87f879b507f8938471c4d0dc8f79fe
1 /* Disassembler interface for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
3
4 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 - the resultant file is machine generated, cgen-dis.in isn't
6
7 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
8 Free Software Foundation, Inc.
9
10 This file is part of the GNU Binutils and GDB, the GNU debugger.
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2, or (at your option)
15 any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software Foundation, Inc.,
24 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
25
26 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
27 Keep that in mind. */
28
29 #include "sysdep.h"
30 #include <stdio.h>
31 #include "ansidecl.h"
32 #include "dis-asm.h"
33 #include "bfd.h"
34 #include "symcat.h"
35 #include "libiberty.h"
36 #include "m32c-desc.h"
37 #include "m32c-opc.h"
38 #include "opintl.h"
39
40 /* Default text to print if an instruction isn't recognized. */
41 #define UNKNOWN_INSN_MSG _("*unknown*")
42
43 static void print_normal
44 (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
45 static void print_address
46 (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
47 static void print_keyword
48 (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
49 static void print_insn_normal
50 (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
51 static int print_insn
52 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned);
53 static int default_print_insn
54 (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
55 static int read_insn
56 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
57 unsigned long *);
58 \f
59 /* -- disassembler routines inserted here. */
60
61 /* -- dis.c */
62
63 #include "elf/m32c.h"
64 #include "elf-bfd.h"
65
66 /* Always print the short insn format suffix as ':<char>'. */
67
68 static void
69 print_suffix (void * dis_info, char suffix)
70 {
71 disassemble_info *info = dis_info;
72
73 (*info->fprintf_func) (info->stream, ":%c", suffix);
74 }
75
76 static void
77 print_S (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
78 void * dis_info,
79 long value ATTRIBUTE_UNUSED,
80 unsigned int attrs ATTRIBUTE_UNUSED,
81 bfd_vma pc ATTRIBUTE_UNUSED,
82 int length ATTRIBUTE_UNUSED)
83 {
84 print_suffix (dis_info, 's');
85 }
86
87
88 static void
89 print_G (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
90 void * dis_info,
91 long value ATTRIBUTE_UNUSED,
92 unsigned int attrs ATTRIBUTE_UNUSED,
93 bfd_vma pc ATTRIBUTE_UNUSED,
94 int length ATTRIBUTE_UNUSED)
95 {
96 print_suffix (dis_info, 'g');
97 }
98
99 static void
100 print_Q (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
101 void * dis_info,
102 long value ATTRIBUTE_UNUSED,
103 unsigned int attrs ATTRIBUTE_UNUSED,
104 bfd_vma pc ATTRIBUTE_UNUSED,
105 int length ATTRIBUTE_UNUSED)
106 {
107 print_suffix (dis_info, 'q');
108 }
109
110 static void
111 print_Z (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
112 void * dis_info,
113 long value ATTRIBUTE_UNUSED,
114 unsigned int attrs ATTRIBUTE_UNUSED,
115 bfd_vma pc ATTRIBUTE_UNUSED,
116 int length ATTRIBUTE_UNUSED)
117 {
118 print_suffix (dis_info, 'z');
119 }
120
121 /* Print the empty suffix. */
122
123 static void
124 print_X (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
125 void * dis_info ATTRIBUTE_UNUSED,
126 long value ATTRIBUTE_UNUSED,
127 unsigned int attrs ATTRIBUTE_UNUSED,
128 bfd_vma pc ATTRIBUTE_UNUSED,
129 int length ATTRIBUTE_UNUSED)
130 {
131 return;
132 }
133
134 static void
135 print_r0l_r0h (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
136 void * dis_info,
137 long value,
138 unsigned int attrs ATTRIBUTE_UNUSED,
139 bfd_vma pc ATTRIBUTE_UNUSED,
140 int length ATTRIBUTE_UNUSED)
141 {
142 disassemble_info *info = dis_info;
143
144 if (value == 0)
145 (*info->fprintf_func) (info->stream, "r0h,r0l");
146 else
147 (*info->fprintf_func) (info->stream, "r0l,r0h");
148 }
149
150 static void
151 print_unsigned_bitbase (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
152 void * dis_info,
153 unsigned long value,
154 unsigned int attrs ATTRIBUTE_UNUSED,
155 bfd_vma pc ATTRIBUTE_UNUSED,
156 int length ATTRIBUTE_UNUSED)
157 {
158 disassemble_info *info = dis_info;
159
160 (*info->fprintf_func) (info->stream, "%ld,0x%lx", value & 0x7, value >> 3);
161 }
162
163 static void
164 print_signed_bitbase (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
165 void * dis_info,
166 signed long value,
167 unsigned int attrs ATTRIBUTE_UNUSED,
168 bfd_vma pc ATTRIBUTE_UNUSED,
169 int length ATTRIBUTE_UNUSED)
170 {
171 disassemble_info *info = dis_info;
172
173 (*info->fprintf_func) (info->stream, "%ld,%ld", value & 0x7, value >> 3);
174 }
175
176 static void
177 print_size (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
178 void * dis_info,
179 long value ATTRIBUTE_UNUSED,
180 unsigned int attrs ATTRIBUTE_UNUSED,
181 bfd_vma pc ATTRIBUTE_UNUSED,
182 int length ATTRIBUTE_UNUSED)
183 {
184 /* Always print the size as '.w'. */
185 disassemble_info *info = dis_info;
186
187 (*info->fprintf_func) (info->stream, ".w");
188 }
189
190 #define POP 0
191 #define PUSH 1
192
193 static void print_pop_regset (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
194 static void print_push_regset (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
195
196 /* Print a set of registers, R0,R1,A0,A1,SB,FB. */
197
198 static void
199 print_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
200 void * dis_info,
201 long value,
202 unsigned int attrs ATTRIBUTE_UNUSED,
203 bfd_vma pc ATTRIBUTE_UNUSED,
204 int length ATTRIBUTE_UNUSED,
205 int push)
206 {
207 static char * m16c_register_names [] =
208 {
209 "r0", "r1", "r2", "r3", "a0", "a1", "sb", "fb"
210 };
211 disassemble_info *info = dis_info;
212 int mask;
213 int index = 0;
214 char* comma = "";
215
216 if (push)
217 mask = 0x80;
218 else
219 mask = 1;
220
221 if (value & mask)
222 {
223 (*info->fprintf_func) (info->stream, "%s", m16c_register_names [0]);
224 comma = ",";
225 }
226
227 for (index = 1; index <= 7; ++index)
228 {
229 if (push)
230 mask >>= 1;
231 else
232 mask <<= 1;
233
234 if (value & mask)
235 {
236 (*info->fprintf_func) (info->stream, "%s%s", comma,
237 m16c_register_names [index]);
238 comma = ",";
239 }
240 }
241 }
242
243 static void
244 print_pop_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
245 void * dis_info,
246 long value,
247 unsigned int attrs ATTRIBUTE_UNUSED,
248 bfd_vma pc ATTRIBUTE_UNUSED,
249 int length ATTRIBUTE_UNUSED)
250 {
251 print_regset (cd, dis_info, value, attrs, pc, length, POP);
252 }
253
254 static void
255 print_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
256 void * dis_info,
257 long value,
258 unsigned int attrs ATTRIBUTE_UNUSED,
259 bfd_vma pc ATTRIBUTE_UNUSED,
260 int length ATTRIBUTE_UNUSED)
261 {
262 print_regset (cd, dis_info, value, attrs, pc, length, PUSH);
263 }
264
265 static void
266 print_signed4n (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
267 void * dis_info,
268 signed long value,
269 unsigned int attrs ATTRIBUTE_UNUSED,
270 bfd_vma pc ATTRIBUTE_UNUSED,
271 int length ATTRIBUTE_UNUSED)
272 {
273 disassemble_info *info = dis_info;
274
275 (*info->fprintf_func) (info->stream, "%ld", -value);
276 }
277
278 void m32c_cgen_print_operand
279 (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
280
281 /* Main entry point for printing operands.
282 XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
283 of dis-asm.h on cgen.h.
284
285 This function is basically just a big switch statement. Earlier versions
286 used tables to look up the function to use, but
287 - if the table contains both assembler and disassembler functions then
288 the disassembler contains much of the assembler and vice-versa,
289 - there's a lot of inlining possibilities as things grow,
290 - using a switch statement avoids the function call overhead.
291
292 This function could be moved into `print_insn_normal', but keeping it
293 separate makes clear the interface between `print_insn_normal' and each of
294 the handlers. */
295
296 void
297 m32c_cgen_print_operand (CGEN_CPU_DESC cd,
298 int opindex,
299 void * xinfo,
300 CGEN_FIELDS *fields,
301 void const *attrs ATTRIBUTE_UNUSED,
302 bfd_vma pc,
303 int length)
304 {
305 disassemble_info *info = (disassemble_info *) xinfo;
306
307 switch (opindex)
308 {
309 case M32C_OPERAND_A0 :
310 print_keyword (cd, info, & m32c_cgen_opval_h_a0, 0, 0);
311 break;
312 case M32C_OPERAND_A1 :
313 print_keyword (cd, info, & m32c_cgen_opval_h_a1, 0, 0);
314 break;
315 case M32C_OPERAND_AN16_PUSH_S :
316 print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_4_1, 0);
317 break;
318 case M32C_OPERAND_BIT16AN :
319 print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst16_an, 0);
320 break;
321 case M32C_OPERAND_BIT16RN :
322 print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_dst16_rn, 0);
323 break;
324 case M32C_OPERAND_BIT32ANPREFIXED :
325 print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_prefixed, 0);
326 break;
327 case M32C_OPERAND_BIT32ANUNPREFIXED :
328 print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_unprefixed, 0);
329 break;
330 case M32C_OPERAND_BIT32RNPREFIXED :
331 print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_dst32_rn_prefixed_QI, 0);
332 break;
333 case M32C_OPERAND_BIT32RNUNPREFIXED :
334 print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_dst32_rn_unprefixed_QI, 0);
335 break;
336 case M32C_OPERAND_BITBASE16_16_S8 :
337 print_signed_bitbase (cd, info, fields->f_dsp_16_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
338 break;
339 case M32C_OPERAND_BITBASE16_16_U16 :
340 print_unsigned_bitbase (cd, info, fields->f_dsp_16_u16, 0, pc, length);
341 break;
342 case M32C_OPERAND_BITBASE16_16_U8 :
343 print_unsigned_bitbase (cd, info, fields->f_dsp_16_u8, 0, pc, length);
344 break;
345 case M32C_OPERAND_BITBASE16_8_U11_S :
346 print_unsigned_bitbase (cd, info, fields->f_bitbase16_u11_S, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
347 break;
348 case M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED :
349 print_signed_bitbase (cd, info, fields->f_bitbase32_16_s11_unprefixed, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
350 break;
351 case M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED :
352 print_signed_bitbase (cd, info, fields->f_bitbase32_16_s19_unprefixed, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
353 break;
354 case M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED :
355 print_unsigned_bitbase (cd, info, fields->f_bitbase32_16_u11_unprefixed, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
356 break;
357 case M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED :
358 print_unsigned_bitbase (cd, info, fields->f_bitbase32_16_u19_unprefixed, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
359 break;
360 case M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED :
361 print_unsigned_bitbase (cd, info, fields->f_bitbase32_16_u27_unprefixed, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
362 break;
363 case M32C_OPERAND_BITBASE32_24_S11_PREFIXED :
364 print_signed_bitbase (cd, info, fields->f_bitbase32_24_s11_prefixed, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
365 break;
366 case M32C_OPERAND_BITBASE32_24_S19_PREFIXED :
367 print_signed_bitbase (cd, info, fields->f_bitbase32_24_s19_prefixed, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
368 break;
369 case M32C_OPERAND_BITBASE32_24_U11_PREFIXED :
370 print_unsigned_bitbase (cd, info, fields->f_bitbase32_24_u11_prefixed, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
371 break;
372 case M32C_OPERAND_BITBASE32_24_U19_PREFIXED :
373 print_unsigned_bitbase (cd, info, fields->f_bitbase32_24_u19_prefixed, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
374 break;
375 case M32C_OPERAND_BITBASE32_24_U27_PREFIXED :
376 print_unsigned_bitbase (cd, info, fields->f_bitbase32_24_u27_prefixed, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
377 break;
378 case M32C_OPERAND_BITNO16R :
379 print_normal (cd, info, fields->f_dsp_16_u8, 0, pc, length);
380 break;
381 case M32C_OPERAND_BITNO32PREFIXED :
382 print_normal (cd, info, fields->f_bitno32_prefixed, 0, pc, length);
383 break;
384 case M32C_OPERAND_BITNO32UNPREFIXED :
385 print_normal (cd, info, fields->f_bitno32_unprefixed, 0, pc, length);
386 break;
387 case M32C_OPERAND_DSP_10_U6 :
388 print_normal (cd, info, fields->f_dsp_10_u6, 0, pc, length);
389 break;
390 case M32C_OPERAND_DSP_16_S16 :
391 print_normal (cd, info, fields->f_dsp_16_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
392 break;
393 case M32C_OPERAND_DSP_16_S8 :
394 print_normal (cd, info, fields->f_dsp_16_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
395 break;
396 case M32C_OPERAND_DSP_16_U16 :
397 print_normal (cd, info, fields->f_dsp_16_u16, 0, pc, length);
398 break;
399 case M32C_OPERAND_DSP_16_U20 :
400 print_normal (cd, info, fields->f_dsp_16_u24, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
401 break;
402 case M32C_OPERAND_DSP_16_U24 :
403 print_normal (cd, info, fields->f_dsp_16_u24, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
404 break;
405 case M32C_OPERAND_DSP_16_U8 :
406 print_normal (cd, info, fields->f_dsp_16_u8, 0, pc, length);
407 break;
408 case M32C_OPERAND_DSP_24_S16 :
409 print_normal (cd, info, fields->f_dsp_24_s16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
410 break;
411 case M32C_OPERAND_DSP_24_S8 :
412 print_normal (cd, info, fields->f_dsp_24_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
413 break;
414 case M32C_OPERAND_DSP_24_U16 :
415 print_normal (cd, info, fields->f_dsp_24_u16, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
416 break;
417 case M32C_OPERAND_DSP_24_U20 :
418 print_normal (cd, info, fields->f_dsp_24_u24, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
419 break;
420 case M32C_OPERAND_DSP_24_U24 :
421 print_normal (cd, info, fields->f_dsp_24_u24, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
422 break;
423 case M32C_OPERAND_DSP_24_U8 :
424 print_normal (cd, info, fields->f_dsp_24_u8, 0, pc, length);
425 break;
426 case M32C_OPERAND_DSP_32_S16 :
427 print_normal (cd, info, fields->f_dsp_32_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
428 break;
429 case M32C_OPERAND_DSP_32_S8 :
430 print_normal (cd, info, fields->f_dsp_32_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
431 break;
432 case M32C_OPERAND_DSP_32_U16 :
433 print_normal (cd, info, fields->f_dsp_32_u16, 0, pc, length);
434 break;
435 case M32C_OPERAND_DSP_32_U20 :
436 print_normal (cd, info, fields->f_dsp_32_u24, 0, pc, length);
437 break;
438 case M32C_OPERAND_DSP_32_U24 :
439 print_normal (cd, info, fields->f_dsp_32_u24, 0, pc, length);
440 break;
441 case M32C_OPERAND_DSP_32_U8 :
442 print_normal (cd, info, fields->f_dsp_32_u8, 0, pc, length);
443 break;
444 case M32C_OPERAND_DSP_40_S16 :
445 print_normal (cd, info, fields->f_dsp_40_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
446 break;
447 case M32C_OPERAND_DSP_40_S8 :
448 print_normal (cd, info, fields->f_dsp_40_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
449 break;
450 case M32C_OPERAND_DSP_40_U16 :
451 print_normal (cd, info, fields->f_dsp_40_u16, 0, pc, length);
452 break;
453 case M32C_OPERAND_DSP_40_U24 :
454 print_normal (cd, info, fields->f_dsp_40_u24, 0, pc, length);
455 break;
456 case M32C_OPERAND_DSP_40_U8 :
457 print_normal (cd, info, fields->f_dsp_40_u8, 0, pc, length);
458 break;
459 case M32C_OPERAND_DSP_48_S16 :
460 print_normal (cd, info, fields->f_dsp_48_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
461 break;
462 case M32C_OPERAND_DSP_48_S8 :
463 print_normal (cd, info, fields->f_dsp_48_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
464 break;
465 case M32C_OPERAND_DSP_48_U16 :
466 print_normal (cd, info, fields->f_dsp_48_u16, 0, pc, length);
467 break;
468 case M32C_OPERAND_DSP_48_U24 :
469 print_normal (cd, info, fields->f_dsp_48_u24, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
470 break;
471 case M32C_OPERAND_DSP_48_U8 :
472 print_normal (cd, info, fields->f_dsp_48_u8, 0, pc, length);
473 break;
474 case M32C_OPERAND_DSP_8_S24 :
475 print_normal (cd, info, fields->f_dsp_8_s24, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
476 break;
477 case M32C_OPERAND_DSP_8_S8 :
478 print_normal (cd, info, fields->f_dsp_8_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
479 break;
480 case M32C_OPERAND_DSP_8_U16 :
481 print_normal (cd, info, fields->f_dsp_8_u16, 0, pc, length);
482 break;
483 case M32C_OPERAND_DSP_8_U24 :
484 print_normal (cd, info, fields->f_dsp_8_u24, 0, pc, length);
485 break;
486 case M32C_OPERAND_DSP_8_U6 :
487 print_normal (cd, info, fields->f_dsp_8_u6, 0, pc, length);
488 break;
489 case M32C_OPERAND_DSP_8_U8 :
490 print_normal (cd, info, fields->f_dsp_8_u8, 0, pc, length);
491 break;
492 case M32C_OPERAND_DST16AN :
493 print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst16_an, 0);
494 break;
495 case M32C_OPERAND_DST16AN_S :
496 print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_dst16_an_s, 0);
497 break;
498 case M32C_OPERAND_DST16ANHI :
499 print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_dst16_an, 0);
500 break;
501 case M32C_OPERAND_DST16ANQI :
502 print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_dst16_an, 0);
503 break;
504 case M32C_OPERAND_DST16ANQI_S :
505 print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_dst16_rn_QI_s, 0);
506 break;
507 case M32C_OPERAND_DST16ANSI :
508 print_keyword (cd, info, & m32c_cgen_opval_h_ar_SI, fields->f_dst16_an, 0);
509 break;
510 case M32C_OPERAND_DST16RNEXTQI :
511 print_keyword (cd, info, & m32c_cgen_opval_h_gr_ext_QI, fields->f_dst16_rn_ext, 0);
512 break;
513 case M32C_OPERAND_DST16RNHI :
514 print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_dst16_rn, 0);
515 break;
516 case M32C_OPERAND_DST16RNQI :
517 print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_dst16_rn, 0);
518 break;
519 case M32C_OPERAND_DST16RNQI_S :
520 print_keyword (cd, info, & m32c_cgen_opval_h_r0l_r0h, fields->f_dst16_rn_QI_s, 0);
521 break;
522 case M32C_OPERAND_DST16RNSI :
523 print_keyword (cd, info, & m32c_cgen_opval_h_gr_SI, fields->f_dst16_rn, 0);
524 break;
525 case M32C_OPERAND_DST32ANEXTUNPREFIXED :
526 print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_unprefixed, 0);
527 break;
528 case M32C_OPERAND_DST32ANPREFIXED :
529 print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_prefixed, 0);
530 break;
531 case M32C_OPERAND_DST32ANPREFIXEDHI :
532 print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_dst32_an_prefixed, 0);
533 break;
534 case M32C_OPERAND_DST32ANPREFIXEDQI :
535 print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_dst32_an_prefixed, 0);
536 break;
537 case M32C_OPERAND_DST32ANPREFIXEDSI :
538 print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_prefixed, 0);
539 break;
540 case M32C_OPERAND_DST32ANUNPREFIXED :
541 print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_unprefixed, 0);
542 break;
543 case M32C_OPERAND_DST32ANUNPREFIXEDHI :
544 print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_dst32_an_unprefixed, 0);
545 break;
546 case M32C_OPERAND_DST32ANUNPREFIXEDQI :
547 print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_dst32_an_unprefixed, 0);
548 break;
549 case M32C_OPERAND_DST32ANUNPREFIXEDSI :
550 print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_unprefixed, 0);
551 break;
552 case M32C_OPERAND_DST32R0HI_S :
553 print_keyword (cd, info, & m32c_cgen_opval_h_r0, 0, 0);
554 break;
555 case M32C_OPERAND_DST32R0QI_S :
556 print_keyword (cd, info, & m32c_cgen_opval_h_r0l, 0, 0);
557 break;
558 case M32C_OPERAND_DST32RNEXTUNPREFIXEDHI :
559 print_keyword (cd, info, & m32c_cgen_opval_h_gr_ext_HI, fields->f_dst32_rn_ext_unprefixed, 0);
560 break;
561 case M32C_OPERAND_DST32RNEXTUNPREFIXEDQI :
562 print_keyword (cd, info, & m32c_cgen_opval_h_gr_ext_QI, fields->f_dst32_rn_ext_unprefixed, 0);
563 break;
564 case M32C_OPERAND_DST32RNPREFIXEDHI :
565 print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_dst32_rn_prefixed_HI, 0);
566 break;
567 case M32C_OPERAND_DST32RNPREFIXEDQI :
568 print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_dst32_rn_prefixed_QI, 0);
569 break;
570 case M32C_OPERAND_DST32RNPREFIXEDSI :
571 print_keyword (cd, info, & m32c_cgen_opval_h_gr_SI, fields->f_dst32_rn_prefixed_SI, 0);
572 break;
573 case M32C_OPERAND_DST32RNUNPREFIXEDHI :
574 print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_dst32_rn_unprefixed_HI, 0);
575 break;
576 case M32C_OPERAND_DST32RNUNPREFIXEDQI :
577 print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_dst32_rn_unprefixed_QI, 0);
578 break;
579 case M32C_OPERAND_DST32RNUNPREFIXEDSI :
580 print_keyword (cd, info, & m32c_cgen_opval_h_gr_SI, fields->f_dst32_rn_unprefixed_SI, 0);
581 break;
582 case M32C_OPERAND_G :
583 print_G (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
584 break;
585 case M32C_OPERAND_IMM_12_S4 :
586 print_normal (cd, info, fields->f_imm_12_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
587 break;
588 case M32C_OPERAND_IMM_12_S4N :
589 print_signed4n (cd, info, fields->f_imm_12_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
590 break;
591 case M32C_OPERAND_IMM_13_U3 :
592 print_normal (cd, info, fields->f_imm_13_u3, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
593 break;
594 case M32C_OPERAND_IMM_16_HI :
595 print_normal (cd, info, fields->f_dsp_16_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
596 break;
597 case M32C_OPERAND_IMM_16_QI :
598 print_normal (cd, info, fields->f_dsp_16_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
599 break;
600 case M32C_OPERAND_IMM_16_SI :
601 print_normal (cd, info, fields->f_dsp_16_s32, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
602 break;
603 case M32C_OPERAND_IMM_20_S4 :
604 print_normal (cd, info, fields->f_imm_20_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
605 break;
606 case M32C_OPERAND_IMM_24_HI :
607 print_normal (cd, info, fields->f_dsp_24_s16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
608 break;
609 case M32C_OPERAND_IMM_24_QI :
610 print_normal (cd, info, fields->f_dsp_24_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
611 break;
612 case M32C_OPERAND_IMM_24_SI :
613 print_normal (cd, info, fields->f_dsp_24_s32, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
614 break;
615 case M32C_OPERAND_IMM_32_HI :
616 print_normal (cd, info, fields->f_dsp_32_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
617 break;
618 case M32C_OPERAND_IMM_32_QI :
619 print_normal (cd, info, fields->f_dsp_32_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
620 break;
621 case M32C_OPERAND_IMM_32_SI :
622 print_normal (cd, info, fields->f_dsp_32_s32, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
623 break;
624 case M32C_OPERAND_IMM_40_HI :
625 print_normal (cd, info, fields->f_dsp_40_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
626 break;
627 case M32C_OPERAND_IMM_40_QI :
628 print_normal (cd, info, fields->f_dsp_40_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
629 break;
630 case M32C_OPERAND_IMM_40_SI :
631 print_normal (cd, info, fields->f_dsp_40_s32, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
632 break;
633 case M32C_OPERAND_IMM_48_HI :
634 print_normal (cd, info, fields->f_dsp_48_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
635 break;
636 case M32C_OPERAND_IMM_48_QI :
637 print_normal (cd, info, fields->f_dsp_48_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
638 break;
639 case M32C_OPERAND_IMM_48_SI :
640 print_normal (cd, info, fields->f_dsp_48_s32, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
641 break;
642 case M32C_OPERAND_IMM_56_HI :
643 print_normal (cd, info, fields->f_dsp_56_s16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
644 break;
645 case M32C_OPERAND_IMM_56_QI :
646 print_normal (cd, info, fields->f_dsp_56_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
647 break;
648 case M32C_OPERAND_IMM_64_HI :
649 print_normal (cd, info, fields->f_dsp_64_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
650 break;
651 case M32C_OPERAND_IMM_8_HI :
652 print_normal (cd, info, fields->f_dsp_8_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
653 break;
654 case M32C_OPERAND_IMM_8_QI :
655 print_normal (cd, info, fields->f_dsp_8_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
656 break;
657 case M32C_OPERAND_IMM_8_S4 :
658 print_normal (cd, info, fields->f_imm_8_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
659 break;
660 case M32C_OPERAND_IMM_8_S4N :
661 print_normal (cd, info, fields->f_imm_8_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
662 break;
663 case M32C_OPERAND_IMM_SH_12_S4 :
664 print_keyword (cd, info, & m32c_cgen_opval_h_shimm, fields->f_imm_12_s4, 0);
665 break;
666 case M32C_OPERAND_IMM_SH_20_S4 :
667 print_keyword (cd, info, & m32c_cgen_opval_h_shimm, fields->f_imm_20_s4, 0);
668 break;
669 case M32C_OPERAND_IMM_SH_8_S4 :
670 print_keyword (cd, info, & m32c_cgen_opval_h_shimm, fields->f_imm_8_s4, 0);
671 break;
672 case M32C_OPERAND_IMM1_S :
673 print_normal (cd, info, fields->f_imm1_S, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
674 break;
675 case M32C_OPERAND_IMM3_S :
676 print_normal (cd, info, fields->f_imm3_S, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
677 break;
678 case M32C_OPERAND_LAB_16_8 :
679 print_address (cd, info, fields->f_lab_16_8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
680 break;
681 case M32C_OPERAND_LAB_24_8 :
682 print_address (cd, info, fields->f_lab_24_8, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
683 break;
684 case M32C_OPERAND_LAB_32_8 :
685 print_address (cd, info, fields->f_lab_32_8, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
686 break;
687 case M32C_OPERAND_LAB_40_8 :
688 print_address (cd, info, fields->f_lab_40_8, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
689 break;
690 case M32C_OPERAND_LAB_5_3 :
691 print_address (cd, info, fields->f_lab_5_3, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
692 break;
693 case M32C_OPERAND_LAB_8_16 :
694 print_address (cd, info, fields->f_lab_8_16, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
695 break;
696 case M32C_OPERAND_LAB_8_24 :
697 print_address (cd, info, fields->f_lab_8_24, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
698 break;
699 case M32C_OPERAND_LAB_8_8 :
700 print_address (cd, info, fields->f_lab_8_8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
701 break;
702 case M32C_OPERAND_LAB32_JMP_S :
703 print_address (cd, info, fields->f_lab32_jmp_s, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
704 break;
705 case M32C_OPERAND_Q :
706 print_Q (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
707 break;
708 case M32C_OPERAND_R0 :
709 print_keyword (cd, info, & m32c_cgen_opval_h_r0, 0, 0);
710 break;
711 case M32C_OPERAND_R0H :
712 print_keyword (cd, info, & m32c_cgen_opval_h_r0h, 0, 0);
713 break;
714 case M32C_OPERAND_R0L :
715 print_keyword (cd, info, & m32c_cgen_opval_h_r0l, 0, 0);
716 break;
717 case M32C_OPERAND_R1 :
718 print_keyword (cd, info, & m32c_cgen_opval_h_r1, 0, 0);
719 break;
720 case M32C_OPERAND_R1R2R0 :
721 print_keyword (cd, info, & m32c_cgen_opval_h_r1r2r0, 0, 0);
722 break;
723 case M32C_OPERAND_R2 :
724 print_keyword (cd, info, & m32c_cgen_opval_h_r2, 0, 0);
725 break;
726 case M32C_OPERAND_R2R0 :
727 print_keyword (cd, info, & m32c_cgen_opval_h_r2r0, 0, 0);
728 break;
729 case M32C_OPERAND_R3 :
730 print_keyword (cd, info, & m32c_cgen_opval_h_r3, 0, 0);
731 break;
732 case M32C_OPERAND_R3R1 :
733 print_keyword (cd, info, & m32c_cgen_opval_h_r3r1, 0, 0);
734 break;
735 case M32C_OPERAND_REGSETPOP :
736 print_pop_regset (cd, info, fields->f_8_8, 0, pc, length);
737 break;
738 case M32C_OPERAND_REGSETPUSH :
739 print_push_regset (cd, info, fields->f_8_8, 0, pc, length);
740 break;
741 case M32C_OPERAND_RN16_PUSH_S :
742 print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_4_1, 0);
743 break;
744 case M32C_OPERAND_S :
745 print_S (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
746 break;
747 case M32C_OPERAND_SRC16AN :
748 print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_src16_an, 0);
749 break;
750 case M32C_OPERAND_SRC16ANHI :
751 print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_src16_an, 0);
752 break;
753 case M32C_OPERAND_SRC16ANQI :
754 print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_src16_an, 0);
755 break;
756 case M32C_OPERAND_SRC16RNHI :
757 print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_src16_rn, 0);
758 break;
759 case M32C_OPERAND_SRC16RNQI :
760 print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_src16_rn, 0);
761 break;
762 case M32C_OPERAND_SRC32ANPREFIXED :
763 print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_src32_an_prefixed, 0);
764 break;
765 case M32C_OPERAND_SRC32ANPREFIXEDHI :
766 print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_src32_an_prefixed, 0);
767 break;
768 case M32C_OPERAND_SRC32ANPREFIXEDQI :
769 print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_src32_an_prefixed, 0);
770 break;
771 case M32C_OPERAND_SRC32ANPREFIXEDSI :
772 print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_src32_an_prefixed, 0);
773 break;
774 case M32C_OPERAND_SRC32ANUNPREFIXED :
775 print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_src32_an_unprefixed, 0);
776 break;
777 case M32C_OPERAND_SRC32ANUNPREFIXEDHI :
778 print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_src32_an_unprefixed, 0);
779 break;
780 case M32C_OPERAND_SRC32ANUNPREFIXEDQI :
781 print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_src32_an_unprefixed, 0);
782 break;
783 case M32C_OPERAND_SRC32ANUNPREFIXEDSI :
784 print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_src32_an_unprefixed, 0);
785 break;
786 case M32C_OPERAND_SRC32RNPREFIXEDHI :
787 print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_src32_rn_prefixed_HI, 0);
788 break;
789 case M32C_OPERAND_SRC32RNPREFIXEDQI :
790 print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_src32_rn_prefixed_QI, 0);
791 break;
792 case M32C_OPERAND_SRC32RNPREFIXEDSI :
793 print_keyword (cd, info, & m32c_cgen_opval_h_gr_SI, fields->f_src32_rn_prefixed_SI, 0);
794 break;
795 case M32C_OPERAND_SRC32RNUNPREFIXEDHI :
796 print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_src32_rn_unprefixed_HI, 0);
797 break;
798 case M32C_OPERAND_SRC32RNUNPREFIXEDQI :
799 print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_src32_rn_unprefixed_QI, 0);
800 break;
801 case M32C_OPERAND_SRC32RNUNPREFIXEDSI :
802 print_keyword (cd, info, & m32c_cgen_opval_h_gr_SI, fields->f_src32_rn_unprefixed_SI, 0);
803 break;
804 case M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL :
805 print_r0l_r0h (cd, info, fields->f_5_1, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
806 break;
807 case M32C_OPERAND_X :
808 print_X (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
809 break;
810 case M32C_OPERAND_Z :
811 print_Z (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
812 break;
813 case M32C_OPERAND_COND16_16 :
814 print_keyword (cd, info, & m32c_cgen_opval_h_cond16, fields->f_dsp_16_u8, 0);
815 break;
816 case M32C_OPERAND_COND16_24 :
817 print_keyword (cd, info, & m32c_cgen_opval_h_cond16, fields->f_dsp_24_u8, 0);
818 break;
819 case M32C_OPERAND_COND16_32 :
820 print_keyword (cd, info, & m32c_cgen_opval_h_cond16, fields->f_dsp_32_u8, 0);
821 break;
822 case M32C_OPERAND_COND16C :
823 print_keyword (cd, info, & m32c_cgen_opval_h_cond16c, fields->f_cond16, 0);
824 break;
825 case M32C_OPERAND_COND16J :
826 print_keyword (cd, info, & m32c_cgen_opval_h_cond16j, fields->f_cond16, 0);
827 break;
828 case M32C_OPERAND_COND16J5 :
829 print_keyword (cd, info, & m32c_cgen_opval_h_cond16j_5, fields->f_cond16j_5, 0);
830 break;
831 case M32C_OPERAND_COND32 :
832 print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_cond32, 0|(1<<CGEN_OPERAND_VIRTUAL));
833 break;
834 case M32C_OPERAND_COND32_16 :
835 print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_dsp_16_u8, 0);
836 break;
837 case M32C_OPERAND_COND32_24 :
838 print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_dsp_24_u8, 0);
839 break;
840 case M32C_OPERAND_COND32_32 :
841 print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_dsp_32_u8, 0);
842 break;
843 case M32C_OPERAND_COND32_40 :
844 print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_dsp_40_u8, 0);
845 break;
846 case M32C_OPERAND_COND32J :
847 print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_cond32j, 0|(1<<CGEN_OPERAND_VIRTUAL));
848 break;
849 case M32C_OPERAND_CR1_PREFIXED_32 :
850 print_keyword (cd, info, & m32c_cgen_opval_h_cr1_32, fields->f_21_3, 0);
851 break;
852 case M32C_OPERAND_CR1_UNPREFIXED_32 :
853 print_keyword (cd, info, & m32c_cgen_opval_h_cr1_32, fields->f_13_3, 0);
854 break;
855 case M32C_OPERAND_CR16 :
856 print_keyword (cd, info, & m32c_cgen_opval_h_cr_16, fields->f_9_3, 0);
857 break;
858 case M32C_OPERAND_CR2_32 :
859 print_keyword (cd, info, & m32c_cgen_opval_h_cr2_32, fields->f_13_3, 0);
860 break;
861 case M32C_OPERAND_CR3_PREFIXED_32 :
862 print_keyword (cd, info, & m32c_cgen_opval_h_cr3_32, fields->f_21_3, 0);
863 break;
864 case M32C_OPERAND_CR3_UNPREFIXED_32 :
865 print_keyword (cd, info, & m32c_cgen_opval_h_cr3_32, fields->f_13_3, 0);
866 break;
867 case M32C_OPERAND_FLAGS16 :
868 print_keyword (cd, info, & m32c_cgen_opval_h_flags, fields->f_9_3, 0);
869 break;
870 case M32C_OPERAND_FLAGS32 :
871 print_keyword (cd, info, & m32c_cgen_opval_h_flags, fields->f_13_3, 0);
872 break;
873 case M32C_OPERAND_SCCOND32 :
874 print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_cond16, 0);
875 break;
876 case M32C_OPERAND_SIZE :
877 print_size (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
878 break;
879
880 default :
881 /* xgettext:c-format */
882 fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
883 opindex);
884 abort ();
885 }
886 }
887
888 cgen_print_fn * const m32c_cgen_print_handlers[] =
889 {
890 print_insn_normal,
891 };
892
893
894 void
895 m32c_cgen_init_dis (CGEN_CPU_DESC cd)
896 {
897 m32c_cgen_init_opcode_table (cd);
898 m32c_cgen_init_ibld_table (cd);
899 cd->print_handlers = & m32c_cgen_print_handlers[0];
900 cd->print_operand = m32c_cgen_print_operand;
901 }
902
903 \f
904 /* Default print handler. */
905
906 static void
907 print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
908 void *dis_info,
909 long value,
910 unsigned int attrs,
911 bfd_vma pc ATTRIBUTE_UNUSED,
912 int length ATTRIBUTE_UNUSED)
913 {
914 disassemble_info *info = (disassemble_info *) dis_info;
915
916 #ifdef CGEN_PRINT_NORMAL
917 CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
918 #endif
919
920 /* Print the operand as directed by the attributes. */
921 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
922 ; /* nothing to do */
923 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
924 (*info->fprintf_func) (info->stream, "%ld", value);
925 else
926 (*info->fprintf_func) (info->stream, "0x%lx", value);
927 }
928
929 /* Default address handler. */
930
931 static void
932 print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
933 void *dis_info,
934 bfd_vma value,
935 unsigned int attrs,
936 bfd_vma pc ATTRIBUTE_UNUSED,
937 int length ATTRIBUTE_UNUSED)
938 {
939 disassemble_info *info = (disassemble_info *) dis_info;
940
941 #ifdef CGEN_PRINT_ADDRESS
942 CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
943 #endif
944
945 /* Print the operand as directed by the attributes. */
946 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
947 ; /* Nothing to do. */
948 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
949 (*info->print_address_func) (value, info);
950 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
951 (*info->print_address_func) (value, info);
952 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
953 (*info->fprintf_func) (info->stream, "%ld", (long) value);
954 else
955 (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
956 }
957
958 /* Keyword print handler. */
959
960 static void
961 print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
962 void *dis_info,
963 CGEN_KEYWORD *keyword_table,
964 long value,
965 unsigned int attrs ATTRIBUTE_UNUSED)
966 {
967 disassemble_info *info = (disassemble_info *) dis_info;
968 const CGEN_KEYWORD_ENTRY *ke;
969
970 ke = cgen_keyword_lookup_value (keyword_table, value);
971 if (ke != NULL)
972 (*info->fprintf_func) (info->stream, "%s", ke->name);
973 else
974 (*info->fprintf_func) (info->stream, "???");
975 }
976 \f
977 /* Default insn printer.
978
979 DIS_INFO is defined as `void *' so the disassembler needn't know anything
980 about disassemble_info. */
981
982 static void
983 print_insn_normal (CGEN_CPU_DESC cd,
984 void *dis_info,
985 const CGEN_INSN *insn,
986 CGEN_FIELDS *fields,
987 bfd_vma pc,
988 int length)
989 {
990 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
991 disassemble_info *info = (disassemble_info *) dis_info;
992 const CGEN_SYNTAX_CHAR_TYPE *syn;
993
994 CGEN_INIT_PRINT (cd);
995
996 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
997 {
998 if (CGEN_SYNTAX_MNEMONIC_P (*syn))
999 {
1000 (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
1001 continue;
1002 }
1003 if (CGEN_SYNTAX_CHAR_P (*syn))
1004 {
1005 (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
1006 continue;
1007 }
1008
1009 /* We have an operand. */
1010 m32c_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
1011 fields, CGEN_INSN_ATTRS (insn), pc, length);
1012 }
1013 }
1014 \f
1015 /* Subroutine of print_insn. Reads an insn into the given buffers and updates
1016 the extract info.
1017 Returns 0 if all is well, non-zero otherwise. */
1018
1019 static int
1020 read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
1021 bfd_vma pc,
1022 disassemble_info *info,
1023 bfd_byte *buf,
1024 int buflen,
1025 CGEN_EXTRACT_INFO *ex_info,
1026 unsigned long *insn_value)
1027 {
1028 int status = (*info->read_memory_func) (pc, buf, buflen, info);
1029
1030 if (status != 0)
1031 {
1032 (*info->memory_error_func) (status, pc, info);
1033 return -1;
1034 }
1035
1036 ex_info->dis_info = info;
1037 ex_info->valid = (1 << buflen) - 1;
1038 ex_info->insn_bytes = buf;
1039
1040 *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
1041 return 0;
1042 }
1043
1044 /* Utility to print an insn.
1045 BUF is the base part of the insn, target byte order, BUFLEN bytes long.
1046 The result is the size of the insn in bytes or zero for an unknown insn
1047 or -1 if an error occurs fetching data (memory_error_func will have
1048 been called). */
1049
1050 static int
1051 print_insn (CGEN_CPU_DESC cd,
1052 bfd_vma pc,
1053 disassemble_info *info,
1054 bfd_byte *buf,
1055 unsigned int buflen)
1056 {
1057 CGEN_INSN_INT insn_value;
1058 const CGEN_INSN_LIST *insn_list;
1059 CGEN_EXTRACT_INFO ex_info;
1060 int basesize;
1061
1062 /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
1063 basesize = cd->base_insn_bitsize < buflen * 8 ?
1064 cd->base_insn_bitsize : buflen * 8;
1065 insn_value = cgen_get_insn_value (cd, buf, basesize);
1066
1067
1068 /* Fill in ex_info fields like read_insn would. Don't actually call
1069 read_insn, since the incoming buffer is already read (and possibly
1070 modified a la m32r). */
1071 ex_info.valid = (1 << buflen) - 1;
1072 ex_info.dis_info = info;
1073 ex_info.insn_bytes = buf;
1074
1075 /* The instructions are stored in hash lists.
1076 Pick the first one and keep trying until we find the right one. */
1077
1078 insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
1079 while (insn_list != NULL)
1080 {
1081 const CGEN_INSN *insn = insn_list->insn;
1082 CGEN_FIELDS fields;
1083 int length;
1084 unsigned long insn_value_cropped;
1085
1086 #ifdef CGEN_VALIDATE_INSN_SUPPORTED
1087 /* Not needed as insn shouldn't be in hash lists if not supported. */
1088 /* Supported by this cpu? */
1089 if (! m32c_cgen_insn_supported (cd, insn))
1090 {
1091 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
1092 continue;
1093 }
1094 #endif
1095
1096 /* Basic bit mask must be correct. */
1097 /* ??? May wish to allow target to defer this check until the extract
1098 handler. */
1099
1100 /* Base size may exceed this instruction's size. Extract the
1101 relevant part from the buffer. */
1102 if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
1103 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
1104 insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
1105 info->endian == BFD_ENDIAN_BIG);
1106 else
1107 insn_value_cropped = insn_value;
1108
1109 if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
1110 == CGEN_INSN_BASE_VALUE (insn))
1111 {
1112 /* Printing is handled in two passes. The first pass parses the
1113 machine insn and extracts the fields. The second pass prints
1114 them. */
1115
1116 /* Make sure the entire insn is loaded into insn_value, if it
1117 can fit. */
1118 if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
1119 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
1120 {
1121 unsigned long full_insn_value;
1122 int rc = read_insn (cd, pc, info, buf,
1123 CGEN_INSN_BITSIZE (insn) / 8,
1124 & ex_info, & full_insn_value);
1125 if (rc != 0)
1126 return rc;
1127 length = CGEN_EXTRACT_FN (cd, insn)
1128 (cd, insn, &ex_info, full_insn_value, &fields, pc);
1129 }
1130 else
1131 length = CGEN_EXTRACT_FN (cd, insn)
1132 (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
1133
1134 /* Length < 0 -> error. */
1135 if (length < 0)
1136 return length;
1137 if (length > 0)
1138 {
1139 CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
1140 /* Length is in bits, result is in bytes. */
1141 return length / 8;
1142 }
1143 }
1144
1145 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
1146 }
1147
1148 return 0;
1149 }
1150
1151 /* Default value for CGEN_PRINT_INSN.
1152 The result is the size of the insn in bytes or zero for an unknown insn
1153 or -1 if an error occured fetching bytes. */
1154
1155 #ifndef CGEN_PRINT_INSN
1156 #define CGEN_PRINT_INSN default_print_insn
1157 #endif
1158
1159 static int
1160 default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
1161 {
1162 bfd_byte buf[CGEN_MAX_INSN_SIZE];
1163 int buflen;
1164 int status;
1165
1166 /* Attempt to read the base part of the insn. */
1167 buflen = cd->base_insn_bitsize / 8;
1168 status = (*info->read_memory_func) (pc, buf, buflen, info);
1169
1170 /* Try again with the minimum part, if min < base. */
1171 if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
1172 {
1173 buflen = cd->min_insn_bitsize / 8;
1174 status = (*info->read_memory_func) (pc, buf, buflen, info);
1175 }
1176
1177 if (status != 0)
1178 {
1179 (*info->memory_error_func) (status, pc, info);
1180 return -1;
1181 }
1182
1183 return print_insn (cd, pc, info, buf, buflen);
1184 }
1185
1186 /* Main entry point.
1187 Print one instruction from PC on INFO->STREAM.
1188 Return the size of the instruction (in bytes). */
1189
1190 typedef struct cpu_desc_list
1191 {
1192 struct cpu_desc_list *next;
1193 CGEN_BITSET *isa;
1194 int mach;
1195 int endian;
1196 CGEN_CPU_DESC cd;
1197 } cpu_desc_list;
1198
1199 int
1200 print_insn_m32c (bfd_vma pc, disassemble_info *info)
1201 {
1202 static cpu_desc_list *cd_list = 0;
1203 cpu_desc_list *cl = 0;
1204 static CGEN_CPU_DESC cd = 0;
1205 static CGEN_BITSET *prev_isa;
1206 static int prev_mach;
1207 static int prev_endian;
1208 int length;
1209 CGEN_BITSET *isa;
1210 int mach;
1211 int endian = (info->endian == BFD_ENDIAN_BIG
1212 ? CGEN_ENDIAN_BIG
1213 : CGEN_ENDIAN_LITTLE);
1214 enum bfd_architecture arch;
1215
1216 /* ??? gdb will set mach but leave the architecture as "unknown" */
1217 #ifndef CGEN_BFD_ARCH
1218 #define CGEN_BFD_ARCH bfd_arch_m32c
1219 #endif
1220 arch = info->arch;
1221 if (arch == bfd_arch_unknown)
1222 arch = CGEN_BFD_ARCH;
1223
1224 /* There's no standard way to compute the machine or isa number
1225 so we leave it to the target. */
1226 #ifdef CGEN_COMPUTE_MACH
1227 mach = CGEN_COMPUTE_MACH (info);
1228 #else
1229 mach = info->mach;
1230 #endif
1231
1232 #ifdef CGEN_COMPUTE_ISA
1233 {
1234 static CGEN_BITSET *permanent_isa;
1235
1236 if (!permanent_isa)
1237 permanent_isa = cgen_bitset_create (MAX_ISAS);
1238 isa = permanent_isa;
1239 cgen_bitset_clear (isa);
1240 cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
1241 }
1242 #else
1243 isa = info->insn_sets;
1244 #endif
1245
1246 /* If we've switched cpu's, try to find a handle we've used before */
1247 if (cd
1248 && (cgen_bitset_compare (isa, prev_isa) != 0
1249 || mach != prev_mach
1250 || endian != prev_endian))
1251 {
1252 cd = 0;
1253 for (cl = cd_list; cl; cl = cl->next)
1254 {
1255 if (cgen_bitset_compare (cl->isa, isa) == 0 &&
1256 cl->mach == mach &&
1257 cl->endian == endian)
1258 {
1259 cd = cl->cd;
1260 prev_isa = cd->isas;
1261 break;
1262 }
1263 }
1264 }
1265
1266 /* If we haven't initialized yet, initialize the opcode table. */
1267 if (! cd)
1268 {
1269 const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
1270 const char *mach_name;
1271
1272 if (!arch_type)
1273 abort ();
1274 mach_name = arch_type->printable_name;
1275
1276 prev_isa = cgen_bitset_copy (isa);
1277 prev_mach = mach;
1278 prev_endian = endian;
1279 cd = m32c_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
1280 CGEN_CPU_OPEN_BFDMACH, mach_name,
1281 CGEN_CPU_OPEN_ENDIAN, prev_endian,
1282 CGEN_CPU_OPEN_END);
1283 if (!cd)
1284 abort ();
1285
1286 /* Save this away for future reference. */
1287 cl = xmalloc (sizeof (struct cpu_desc_list));
1288 cl->cd = cd;
1289 cl->isa = prev_isa;
1290 cl->mach = mach;
1291 cl->endian = endian;
1292 cl->next = cd_list;
1293 cd_list = cl;
1294
1295 m32c_cgen_init_dis (cd);
1296 }
1297
1298 /* We try to have as much common code as possible.
1299 But at this point some targets need to take over. */
1300 /* ??? Some targets may need a hook elsewhere. Try to avoid this,
1301 but if not possible try to move this hook elsewhere rather than
1302 have two hooks. */
1303 length = CGEN_PRINT_INSN (cd, pc, info);
1304 if (length > 0)
1305 return length;
1306 if (length < 0)
1307 return -1;
1308
1309 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
1310 return cd->default_insn_bitsize / 8;
1311 }
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