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* elf32-ppc.c (LWZU_0_X_11): Delete.
[binutils.git] / gas / config / tc-m68k.c
blob927c701ad3b17082bf36a3981765e2bf9cd739d7
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
21
22 #include "as.h"
23 #include "safe-ctype.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
31
32 #if defined (OBJ_ELF)
33 #include "elf/m68k.h"
34 #endif
35
36 #ifdef M68KCOFF
37 #include "obj-coff.h"
38 #endif
39
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars = "|#";
46 #else
47 const char *m68k_comment_chars = "|";
48 #endif
49
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars[] = "#*";
58
59 const char line_separator_chars[] = ";";
60
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS[] = "eE";
63
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
66
67 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
68
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
72
73 const int md_reloc_size = 8; /* Size of relocation record. */
74
75 /* Are we trying to generate PIC code? If so, absolute references
76 ought to be made into linkage table references or pc-relative
77 references. Not implemented. For ELF there are other means
78 to denote pic relocations. */
79 int flag_want_pic;
80
81 static int flag_short_refs; /* -l option. */
82 static int flag_long_jumps; /* -S option. */
83 static int flag_keep_pcrel; /* --pcrel option. */
84
85 #ifdef REGISTER_PREFIX_OPTIONAL
86 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
87 #else
88 int flag_reg_prefix_optional;
89 #endif
90
91 /* Whether --register-prefix-optional was used on the command line. */
92 static int reg_prefix_optional_seen;
93
94 /* The floating point coprocessor to use by default. */
95 static enum m68k_register m68k_float_copnum = COP1;
96
97 /* If this is non-zero, then references to number(%pc) will be taken
98 to refer to number, rather than to %pc + number. */
99 static int m68k_abspcadd;
100
101 /* If this is non-zero, then the quick forms of the move, add, and sub
102 instructions are used when possible. */
103 static int m68k_quick = 1;
104
105 /* If this is non-zero, then if the size is not specified for a base
106 or outer displacement, the assembler assumes that the size should
107 be 32 bits. */
108 static int m68k_rel32 = 1;
109
110 /* This is non-zero if m68k_rel32 was set from the command line. */
111 static int m68k_rel32_from_cmdline;
112
113 /* The default width to use for an index register when using a base
114 displacement. */
115 static enum m68k_size m68k_index_width_default = SIZE_LONG;
116
117 /* We want to warn if any text labels are misaligned. In order to get
118 the right line number, we need to record the line number for each
119 label. */
120 struct label_line
121 {
122 struct label_line *next;
123 symbolS *label;
124 char *file;
125 unsigned int line;
126 int text;
127 };
128
129 /* The list of labels. */
130
131 static struct label_line *labels;
132
133 /* The current label. */
134
135 static struct label_line *current_label;
136
137 /* Pointer to list holding the opcodes sorted by name. */
138 static struct m68k_opcode const ** m68k_sorted_opcodes;
139
140 /* Its an arbitrary name: This means I don't approve of it.
141 See flames below. */
142 static struct obstack robyn;
143
144 struct m68k_incant
145 {
146 const char *m_operands;
147 unsigned long m_opcode;
148 short m_opnum;
149 short m_codenum;
150 int m_arch;
151 struct m68k_incant *m_next;
152 };
153
154 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
155 #define gettwo(x) (((x)->m_opcode)&0xffff)
156
157 static const enum m68k_register m68000_control_regs[] = { 0 };
158 static const enum m68k_register m68010_control_regs[] = {
159 SFC, DFC, USP, VBR,
160 0
161 };
162 static const enum m68k_register m68020_control_regs[] = {
163 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
164 0
165 };
166 static const enum m68k_register m68040_control_regs[] = {
167 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
168 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
169 0
170 };
171 static const enum m68k_register m68060_control_regs[] = {
172 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
173 USP, VBR, URP, SRP, PCR,
174 0
175 };
176 static const enum m68k_register mcf_control_regs[] = {
177 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
178 RAMBAR0, RAMBAR1, MBAR,
179 0
180 };
181 static const enum m68k_register mcf5249_control_regs[] = {
182 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR1, MBAR, MBAR2,
183 0
184 };
185 static const enum m68k_register mcf528x_control_regs[] = {
186 CACR, ACR0, ACR1, VBR, FLASHBAR, RAMBAR,
187 0
188 };
189 static const enum m68k_register mcfv4e_control_regs[] = {
190 CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, VBR, PC, ROMBAR,
191 ROMBAR1, RAMBAR0, RAMBAR1, MPCR, EDRAMBAR, SECMBAR, MBAR, MBAR0, MBAR1,
192 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
193 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
194 0
195 };
196 #define cpu32_control_regs m68010_control_regs
197
198 static const enum m68k_register *control_regs;
199
200 /* Internal form of a 68020 instruction. */
201 struct m68k_it
202 {
203 const char *error;
204 const char *args; /* List of opcode info. */
205 int numargs;
206
207 int numo; /* Number of shorts in opcode. */
208 short opcode[11];
209
210 struct m68k_op operands[6];
211
212 int nexp; /* Number of exprs in use. */
213 struct m68k_exp exprs[4];
214
215 int nfrag; /* Number of frags we have to produce. */
216 struct
217 {
218 int fragoff; /* Where in the current opcode the frag ends. */
219 symbolS *fadd;
220 offsetT foff;
221 int fragty;
222 }
223 fragb[4];
224
225 int nrel; /* Num of reloc strucs in use. */
226 struct
227 {
228 int n;
229 expressionS exp;
230 char wid;
231 char pcrel;
232 /* In a pc relative address the difference between the address
233 of the offset and the address that the offset is relative
234 to. This depends on the addressing mode. Basically this
235 is the value to put in the offset field to address the
236 first byte of the offset, without regarding the special
237 significance of some values (in the branch instruction, for
238 example). */
239 int pcrel_fix;
240 #ifdef OBJ_ELF
241 /* Whether this expression needs special pic relocation, and if
242 so, which. */
243 enum pic_relocation pic_reloc;
244 #endif
245 }
246 reloc[5]; /* Five is enough??? */
247 };
248
249 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a))
250 #define float_of_arch(x) ((x) & mfloat)
251 #define mmu_of_arch(x) ((x) & mmmu)
252 #define arch_coldfire_p(x) ((x) & mcfisa_a)
253 #define arch_coldfire_fpu(x) ((x) & cfloat)
254
255 /* Macros for determining if cpu supports a specific addressing mode. */
256 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b))
257
258 static struct m68k_it the_ins; /* The instruction being assembled. */
259
260 #define op(ex) ((ex)->exp.X_op)
261 #define adds(ex) ((ex)->exp.X_add_symbol)
262 #define subs(ex) ((ex)->exp.X_op_symbol)
263 #define offs(ex) ((ex)->exp.X_add_number)
264
265 /* Macros for adding things to the m68k_it struct. */
266 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
267
268 /* Like addword, but goes BEFORE general operands. */
269
270 static void
271 insop (int w, const struct m68k_incant *opcode)
272 {
273 int z;
274 for (z = the_ins.numo; z > opcode->m_codenum; --z)
275 the_ins.opcode[z] = the_ins.opcode[z - 1];
276 for (z = 0; z < the_ins.nrel; z++)
277 the_ins.reloc[z].n += 2;
278 for (z = 0; z < the_ins.nfrag; z++)
279 the_ins.fragb[z].fragoff++;
280 the_ins.opcode[opcode->m_codenum] = w;
281 the_ins.numo++;
282 }
283
284 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
285 Blecch. */
286 static void
287 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
288 {
289 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
290 ? the_ins.numo * 2 - 1
291 : (width == 'b'
292 ? the_ins.numo * 2 + 1
293 : the_ins.numo * 2));
294 the_ins.reloc[the_ins.nrel].exp = exp->exp;
295 the_ins.reloc[the_ins.nrel].wid = width;
296 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
297 #ifdef OBJ_ELF
298 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
299 #endif
300 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
301 }
302
303 /* Cause an extra frag to be generated here, inserting up to 10 bytes
304 (that value is chosen in the frag_var call in md_assemble). TYPE
305 is the subtype of the frag to be generated; its primary type is
306 rs_machine_dependent.
307
308 The TYPE parameter is also used by md_convert_frag_1 and
309 md_estimate_size_before_relax. The appropriate type of fixup will
310 be emitted by md_convert_frag_1.
311
312 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
313 static void
314 add_frag (symbolS *add, offsetT off, int type)
315 {
316 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
317 the_ins.fragb[the_ins.nfrag].fadd = add;
318 the_ins.fragb[the_ins.nfrag].foff = off;
319 the_ins.fragb[the_ins.nfrag++].fragty = type;
320 }
321
322 #define isvar(ex) \
323 (op (ex) != O_constant && op (ex) != O_big)
324
325 static char *crack_operand (char *str, struct m68k_op *opP);
326 static int get_num (struct m68k_exp *exp, int ok);
327 static int reverse_16_bits (int in);
328 static int reverse_8_bits (int in);
329 static void install_gen_operand (int mode, int val);
330 static void install_operand (int mode, int val);
331 static void s_bss (int);
332 static void s_data1 (int);
333 static void s_data2 (int);
334 static void s_even (int);
335 static void s_proc (int);
336 static void s_chip (int);
337 static void s_fopt (int);
338 static void s_opt (int);
339 static void s_reg (int);
340 static void s_restore (int);
341 static void s_save (int);
342 static void s_mri_if (int);
343 static void s_mri_else (int);
344 static void s_mri_endi (int);
345 static void s_mri_break (int);
346 static void s_mri_next (int);
347 static void s_mri_for (int);
348 static void s_mri_endf (int);
349 static void s_mri_repeat (int);
350 static void s_mri_until (int);
351 static void s_mri_while (int);
352 static void s_mri_endw (int);
353
354 static int current_architecture;
355 static int current_chip;
356
357 struct m68k_cpu
358 {
359 unsigned long arch;
360 unsigned long chip;
361 const char *name;
362 int alias;
363 };
364
365 static const struct m68k_cpu archs[] =
366 {
367 { m68000, m68000, "68000", 0 },
368 { m68010, m68010, "68010", 0 },
369 { m68020, m68020, "68020", 0 },
370 { m68030, m68030, "68030", 0 },
371 { m68040, m68040, "68040", 0 },
372 { m68060, m68060, "68060", 0 },
373 { cpu32, cpu32, "cpu32", 0 },
374 { m68881, m68881, "68881", 0 },
375 { m68851, m68851, "68851", 0 },
376 { mcfisa_a, mcf5200, "5200", 0 },
377 { mcfisa_a|mcfhwdiv|mcfmac, mcf5206e, "5206e", 0 },
378 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf521x, "521x", 0 },
379 { mcfisa_a|mcfhwdiv|mcfemac, mcf5249, "5249", 0 },
380 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf528x, "528x", 0 },
381 { mcfisa_a|mcfhwdiv|mcfmac, mcf5307, "5307", 0 },
382 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac, mcf5407, "5407", 0 },
383 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "547x", 0 },
384 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5480, "548x", 0 },
385 /* Aliases (effectively, so far as gas is concerned) for the above
386 cpus. */
387 { m68020, m68020, "68k", 1 },
388 { m68000, m68000, "68008", 1 },
389 { m68000, m68000, "68302", 1 },
390 { m68000, m68000, "68306", 1 },
391 { m68000, m68000, "68307", 1 },
392 { m68000, m68000, "68322", 1 },
393 { m68000, m68000, "68356", 1 },
394 { m68000, m68000, "68ec000", 1 },
395 { m68000, m68000, "68hc000", 1 },
396 { m68000, m68000, "68hc001", 1 },
397 { m68020, m68020, "68ec020", 1 },
398 { m68030, m68030, "68ec030", 1 },
399 { m68040, m68040, "68ec040", 1 },
400 { m68060, m68060, "68ec060", 1 },
401 { cpu32, cpu32, "68330", 1 },
402 { cpu32, cpu32, "68331", 1 },
403 { cpu32, cpu32, "68332", 1 },
404 { cpu32, cpu32, "68333", 1 },
405 { cpu32, cpu32, "68334", 1 },
406 { cpu32, cpu32, "68336", 1 },
407 { cpu32, cpu32, "68340", 1 },
408 { cpu32, cpu32, "68341", 1 },
409 { cpu32, cpu32, "68349", 1 },
410 { cpu32, cpu32, "68360", 1 },
411 { m68881, m68881, "68882", 1 },
412 { mcfisa_a, mcf5200, "5202", 1 },
413 { mcfisa_a, mcf5200, "5204", 1 },
414 { mcfisa_a, mcf5200, "5206", 1 },
415 { mcfisa_a|mcfhwdiv|mcfisa_aa|mcfemac, mcf521x, "5214", 1 },
416 { mcfisa_a|mcfhwdiv|mcfisa_aa|mcfemac, mcf521x, "5216", 1 },
417 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5280", 1 },
418 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5281", 1 },
419 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5282", 1 },
420 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac, mcf5407, "cfv4", 1 },
421 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5470", 1 },
422 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5471", 1 },
423 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5472", 1 },
424 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5473", 1 },
425 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5474", 1 },
426 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5475", 1 },
427 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5480", 1 },
428 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5481", 1 },
429 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5482", 1 },
430 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5483", 1 },
431 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5484", 1 },
432 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5485", 1 },
433 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "cfv4e", 1 },
434 };
435
436 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
437
438 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
439 architecture and we have a lot of relaxation modes. */
440
441 /* Macros used in the relaxation code. */
442 #define TAB(x,y) (((x) << 2) + (y))
443 #define TABTYPE(x) ((x) >> 2)
444
445 /* Relaxation states. */
446 #define BYTE 0
447 #define SHORT 1
448 #define LONG 2
449 #define SZ_UNDEF 3
450
451 /* Here are all the relaxation modes we support. First we can relax ordinary
452 branches. On 68020 and higher and on CPU32 all branch instructions take
453 three forms, so on these CPUs all branches always remain as such. When we
454 have to expand to the LONG form on a 68000, though, we substitute an
455 absolute jump instead. This is a direct replacement for unconditional
456 branches and a branch over a jump for conditional branches. However, if the
457 user requires PIC and disables this with --pcrel, we can only relax between
458 BYTE and SHORT forms, punting if that isn't enough. This gives us four
459 different relaxation modes for branches: */
460
461 #define BRANCHBWL 0 /* Branch byte, word, or long. */
462 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
463 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
464 #define BRANCHBW 3 /* Branch byte or word. */
465
466 /* We also relax coprocessor branches and DBcc's. All CPUs that support
467 coprocessor branches support them in word and long forms, so we have only
468 one relaxation mode for them. DBcc's are word only on all CPUs. We can
469 relax them to the LONG form with a branch-around sequence. This sequence
470 can use a long branch (if available) or an absolute jump (if acceptable).
471 This gives us two relaxation modes. If long branches are not available and
472 absolute jumps are not acceptable, we don't relax DBcc's. */
473
474 #define FBRANCH 4 /* Coprocessor branch. */
475 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
476 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
477
478 /* That's all for instruction relaxation. However, we also relax PC-relative
479 operands. Specifically, we have three operand relaxation modes. On the
480 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
481 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
482 two. Also PC+displacement+index operands in their simple form (with a non-
483 suppressed index without memory indirection) are supported on all CPUs, but
484 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
485 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
486 form of the PC+displacement+index operand. Finally, some absolute operands
487 can be relaxed down to 16-bit PC-relative. */
488
489 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
490 #define PCINDEX 8 /* PC + displacement + index. */
491 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
492
493 /* Note that calls to frag_var need to specify the maximum expansion
494 needed; this is currently 10 bytes for DBCC. */
495
496 /* The fields are:
497 How far Forward this mode will reach:
498 How far Backward this mode will reach:
499 How many bytes this mode will add to the size of the frag
500 Which mode to go to if the offset won't fit in this one
501
502 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
503 relax_typeS md_relax_table[] =
504 {
505 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
506 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
507 { 0, 0, 4, 0 },
508 { 1, 1, 0, 0 },
509
510 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
511 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
512 { 0, 0, 4, 0 },
513 { 1, 1, 0, 0 },
514
515 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
516 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
517 { 0, 0, 6, 0 },
518 { 1, 1, 0, 0 },
519
520 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
521 { 0, 0, 2, 0 },
522 { 1, 1, 0, 0 },
523 { 1, 1, 0, 0 },
524
525 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
526 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
527 { 0, 0, 4, 0 },
528 { 1, 1, 0, 0 },
529
530 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
531 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
532 { 0, 0, 10, 0 },
533 { 1, 1, 0, 0 },
534
535 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
536 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
537 { 0, 0, 10, 0 },
538 { 1, 1, 0, 0 },
539
540 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
541 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
542 { 0, 0, 6, 0 },
543 { 1, 1, 0, 0 },
544
545 { 125, -130, 0, TAB (PCINDEX, SHORT) },
546 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
547 { 0, 0, 4, 0 },
548 { 1, 1, 0, 0 },
549
550 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
551 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
552 { 0, 0, 4, 0 },
553 { 1, 1, 0, 0 },
554 };
555
556 /* These are the machine dependent pseudo-ops. These are included so
557 the assembler can work on the output from the SUN C compiler, which
558 generates these. */
559
560 /* This table describes all the machine specific pseudo-ops the assembler
561 has to support. The fields are:
562 pseudo-op name without dot
563 function to call to execute this pseudo-op
564 Integer arg to pass to the function. */
565 const pseudo_typeS md_pseudo_table[] =
566 {
567 {"data1", s_data1, 0},
568 {"data2", s_data2, 0},
569 {"bss", s_bss, 0},
570 {"even", s_even, 0},
571 {"skip", s_space, 0},
572 {"proc", s_proc, 0},
573 #if defined (TE_SUN3) || defined (OBJ_ELF)
574 {"align", s_align_bytes, 0},
575 #endif
576 #ifdef OBJ_ELF
577 {"swbeg", s_ignore, 0},
578 #endif
579 {"extend", float_cons, 'x'},
580 {"ldouble", float_cons, 'x'},
581
582 /* The following pseudo-ops are supported for MRI compatibility. */
583 {"chip", s_chip, 0},
584 {"comline", s_space, 1},
585 {"fopt", s_fopt, 0},
586 {"mask2", s_ignore, 0},
587 {"opt", s_opt, 0},
588 {"reg", s_reg, 0},
589 {"restore", s_restore, 0},
590 {"save", s_save, 0},
591
592 {"if", s_mri_if, 0},
593 {"if.b", s_mri_if, 'b'},
594 {"if.w", s_mri_if, 'w'},
595 {"if.l", s_mri_if, 'l'},
596 {"else", s_mri_else, 0},
597 {"else.s", s_mri_else, 's'},
598 {"else.l", s_mri_else, 'l'},
599 {"endi", s_mri_endi, 0},
600 {"break", s_mri_break, 0},
601 {"break.s", s_mri_break, 's'},
602 {"break.l", s_mri_break, 'l'},
603 {"next", s_mri_next, 0},
604 {"next.s", s_mri_next, 's'},
605 {"next.l", s_mri_next, 'l'},
606 {"for", s_mri_for, 0},
607 {"for.b", s_mri_for, 'b'},
608 {"for.w", s_mri_for, 'w'},
609 {"for.l", s_mri_for, 'l'},
610 {"endf", s_mri_endf, 0},
611 {"repeat", s_mri_repeat, 0},
612 {"until", s_mri_until, 0},
613 {"until.b", s_mri_until, 'b'},
614 {"until.w", s_mri_until, 'w'},
615 {"until.l", s_mri_until, 'l'},
616 {"while", s_mri_while, 0},
617 {"while.b", s_mri_while, 'b'},
618 {"while.w", s_mri_while, 'w'},
619 {"while.l", s_mri_while, 'l'},
620 {"endw", s_mri_endw, 0},
621
622 {0, 0, 0}
623 };
624
625 /* The mote pseudo ops are put into the opcode table, since they
626 don't start with a . they look like opcodes to gas. */
627
628 const pseudo_typeS mote_pseudo_table[] =
629 {
630
631 {"dcl", cons, 4},
632 {"dc", cons, 2},
633 {"dcw", cons, 2},
634 {"dcb", cons, 1},
635
636 {"dsl", s_space, 4},
637 {"ds", s_space, 2},
638 {"dsw", s_space, 2},
639 {"dsb", s_space, 1},
640
641 {"xdef", s_globl, 0},
642 #ifdef OBJ_ELF
643 {"align", s_align_bytes, 0},
644 #else
645 {"align", s_align_ptwo, 0},
646 #endif
647 #ifdef M68KCOFF
648 {"sect", obj_coff_section, 0},
649 {"section", obj_coff_section, 0},
650 #endif
651 {0, 0, 0}
652 };
653
654 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
655 gives identical results to a 32-bit host. */
656 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
657 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
658
659 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
660 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
661 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
662 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
663
664 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
665 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
666 #define islong(x) (1)
667
668 static char notend_table[256];
669 static char alt_notend_table[256];
670 #define notend(s) \
671 (! (notend_table[(unsigned char) *s] \
672 || (*s == ':' \
673 && alt_notend_table[(unsigned char) s[1]])))
674
675 /* Return a human readable string holding the list of chips that are
676 valid for a particular architecture, suppressing aliases (unless
677 there is only one of them). */
678
679 static char *
680 find_cf_chip (int architecture)
681 {
682 static char buf[1024];
683 int i, j, n_chips, n_alias;
684 char *cp;
685
686 strcpy (buf, " (");
687 cp = buf + strlen (buf);
688
689 for (i = 0, n_chips = 0, n_alias = 0; i < n_archs; ++i)
690 if (archs[i].arch & architecture)
691 {
692 n_chips++;
693 if (archs[i].alias)
694 n_alias++;
695 }
696
697 if (n_chips == 0)
698 as_fatal (_("no matching ColdFire architectures found"));
699
700 if (n_alias > 1)
701 n_chips -= n_alias;
702
703 for (i = 0, j = 0; i < n_archs && j < n_chips; ++i)
704 if (archs[i].arch & architecture)
705 {
706 if (j)
707 {
708 if ((j == n_chips - 1 && !(n_alias > 1)) || ! n_alias)
709 {
710 if (n_chips == 2)
711 {
712 strncpy (cp, _(" or "), (sizeof (buf) - (cp - buf)));
713 cp += strlen (cp);
714 }
715 else
716 {
717 strncpy (cp, _(", or "), (sizeof (buf) - (cp - buf)));
718 cp += strlen (cp);
719 }
720 }
721 else
722 {
723 strncpy (cp, ", ", (sizeof (buf) - (cp - buf)));
724 cp += strlen (cp);
725 }
726 }
727 strncpy (cp, archs[i].name, (sizeof (buf) - (cp - buf)));
728 cp += strlen (cp);
729 j++;
730 }
731
732 if (n_alias > 1)
733 {
734 strncpy (cp, _(", or aliases"), (sizeof (buf) - (cp - buf)));
735 cp += strlen (cp);
736 }
737
738 strncpy (cp, ")", (sizeof (buf) - (cp - buf)));
739
740 return buf;
741 }
742
743 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
744
745 #ifdef NO_PCREL_RELOCS
746
747 int
748 make_pcrel_absolute (fixS *fixP, long *add_number)
749 {
750 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
751
752 /* Rewrite the PC relative instructions to absolute address ones.
753 these are rumored to be faster, and the apollo linker refuses
754 to deal with the PC relative relocations. */
755 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP. */
756 {
757 if (flag_keep_pcrel)
758 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
759 opcode[0] = 0x4e;
760 opcode[1] = 0xf9;
761 }
762 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR. */
763 {
764 if (flag_keep_pcrel)
765 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
766 opcode[0] = 0x4e;
767 opcode[1] = 0xb9;
768 }
769 else
770 as_fatal (_("Unknown PC relative instruction"));
771 *add_number -= 4;
772 return 0;
773 }
774
775 #endif /* NO_PCREL_RELOCS */
776
777 short
778 tc_coff_fix2rtype (fixS *fixP)
779 {
780 if (fixP->fx_tcbit && fixP->fx_size == 4)
781 return R_RELLONG_NEG;
782 #ifdef NO_PCREL_RELOCS
783 know (fixP->fx_pcrel == 0);
784 return (fixP->fx_size == 1 ? R_RELBYTE
785 : fixP->fx_size == 2 ? R_DIR16
786 : R_DIR32);
787 #else
788 return (fixP->fx_pcrel
789 ? (fixP->fx_size == 1 ? R_PCRBYTE
790 : fixP->fx_size == 2 ? R_PCRWORD
791 : R_PCRLONG)
792 : (fixP->fx_size == 1 ? R_RELBYTE
793 : fixP->fx_size == 2 ? R_RELWORD
794 : R_RELLONG));
795 #endif
796 }
797
798 #endif
799
800 #ifdef OBJ_ELF
801
802 /* Return zero if the reference to SYMBOL from within the same segment may
803 be relaxed. */
804
805 /* On an ELF system, we can't relax an externally visible symbol,
806 because it may be overridden by a shared library. However, if
807 TARGET_OS is "elf", then we presume that we are assembling for an
808 embedded system, in which case we don't have to worry about shared
809 libraries, and we can relax any external sym. */
810
811 #define relaxable_symbol(symbol) \
812 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
813 || S_IS_WEAK (symbol)))
814
815 /* Compute the relocation code for a fixup of SIZE bytes, using pc
816 relative relocation if PCREL is non-zero. PIC says whether a special
817 pic relocation was requested. */
818
819 static bfd_reloc_code_real_type
820 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
821 {
822 switch (pic)
823 {
824 case pic_got_pcrel:
825 switch (size)
826 {
827 case 1:
828 return BFD_RELOC_8_GOT_PCREL;
829 case 2:
830 return BFD_RELOC_16_GOT_PCREL;
831 case 4:
832 return BFD_RELOC_32_GOT_PCREL;
833 }
834 break;
835
836 case pic_got_off:
837 switch (size)
838 {
839 case 1:
840 return BFD_RELOC_8_GOTOFF;
841 case 2:
842 return BFD_RELOC_16_GOTOFF;
843 case 4:
844 return BFD_RELOC_32_GOTOFF;
845 }
846 break;
847
848 case pic_plt_pcrel:
849 switch (size)
850 {
851 case 1:
852 return BFD_RELOC_8_PLT_PCREL;
853 case 2:
854 return BFD_RELOC_16_PLT_PCREL;
855 case 4:
856 return BFD_RELOC_32_PLT_PCREL;
857 }
858 break;
859
860 case pic_plt_off:
861 switch (size)
862 {
863 case 1:
864 return BFD_RELOC_8_PLTOFF;
865 case 2:
866 return BFD_RELOC_16_PLTOFF;
867 case 4:
868 return BFD_RELOC_32_PLTOFF;
869 }
870 break;
871
872 case pic_none:
873 if (pcrel)
874 {
875 switch (size)
876 {
877 case 1:
878 return BFD_RELOC_8_PCREL;
879 case 2:
880 return BFD_RELOC_16_PCREL;
881 case 4:
882 return BFD_RELOC_32_PCREL;
883 }
884 }
885 else
886 {
887 switch (size)
888 {
889 case 1:
890 return BFD_RELOC_8;
891 case 2:
892 return BFD_RELOC_16;
893 case 4:
894 return BFD_RELOC_32;
895 }
896 }
897 }
898
899 if (pcrel)
900 {
901 if (pic == pic_none)
902 as_bad (_("Can not do %d byte pc-relative relocation"), size);
903 else
904 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
905 }
906 else
907 {
908 if (pic == pic_none)
909 as_bad (_("Can not do %d byte relocation"), size);
910 else
911 as_bad (_("Can not do %d byte pic relocation"), size);
912 }
913
914 return BFD_RELOC_NONE;
915 }
916
917 /* Here we decide which fixups can be adjusted to make them relative
918 to the beginning of the section instead of the symbol. Basically
919 we need to make sure that the dynamic relocations are done
920 correctly, so in some cases we force the original symbol to be
921 used. */
922 int
923 tc_m68k_fix_adjustable (fixS *fixP)
924 {
925 /* Adjust_reloc_syms doesn't know about the GOT. */
926 switch (fixP->fx_r_type)
927 {
928 case BFD_RELOC_8_GOT_PCREL:
929 case BFD_RELOC_16_GOT_PCREL:
930 case BFD_RELOC_32_GOT_PCREL:
931 case BFD_RELOC_8_GOTOFF:
932 case BFD_RELOC_16_GOTOFF:
933 case BFD_RELOC_32_GOTOFF:
934 case BFD_RELOC_8_PLT_PCREL:
935 case BFD_RELOC_16_PLT_PCREL:
936 case BFD_RELOC_32_PLT_PCREL:
937 case BFD_RELOC_8_PLTOFF:
938 case BFD_RELOC_16_PLTOFF:
939 case BFD_RELOC_32_PLTOFF:
940 return 0;
941
942 case BFD_RELOC_VTABLE_INHERIT:
943 case BFD_RELOC_VTABLE_ENTRY:
944 return 0;
945
946 default:
947 return 1;
948 }
949 }
950
951 #else /* !OBJ_ELF */
952
953 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
954
955 #define relaxable_symbol(symbol) 1
956
957 #endif /* OBJ_ELF */
958
959 #ifdef BFD_ASSEMBLER
960
961 arelent *
962 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
963 {
964 arelent *reloc;
965 bfd_reloc_code_real_type code;
966
967 /* If the tcbit is set, then this was a fixup of a negative value
968 that was never resolved. We do not have a reloc to handle this,
969 so just return. We assume that other code will have detected this
970 situation and produced a helpful error message, so we just tell the
971 user that the reloc cannot be produced. */
972 if (fixp->fx_tcbit)
973 {
974 if (fixp->fx_addsy)
975 as_bad_where (fixp->fx_file, fixp->fx_line,
976 _("Unable to produce reloc against symbol '%s'"),
977 S_GET_NAME (fixp->fx_addsy));
978 return NULL;
979 }
980
981 if (fixp->fx_r_type != BFD_RELOC_NONE)
982 {
983 code = fixp->fx_r_type;
984
985 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
986 that fixup_segment converted a non-PC relative reloc into a
987 PC relative reloc. In such a case, we need to convert the
988 reloc code. */
989 if (fixp->fx_pcrel)
990 {
991 switch (code)
992 {
993 case BFD_RELOC_8:
994 code = BFD_RELOC_8_PCREL;
995 break;
996 case BFD_RELOC_16:
997 code = BFD_RELOC_16_PCREL;
998 break;
999 case BFD_RELOC_32:
1000 code = BFD_RELOC_32_PCREL;
1001 break;
1002 case BFD_RELOC_8_PCREL:
1003 case BFD_RELOC_16_PCREL:
1004 case BFD_RELOC_32_PCREL:
1005 case BFD_RELOC_8_GOT_PCREL:
1006 case BFD_RELOC_16_GOT_PCREL:
1007 case BFD_RELOC_32_GOT_PCREL:
1008 case BFD_RELOC_8_GOTOFF:
1009 case BFD_RELOC_16_GOTOFF:
1010 case BFD_RELOC_32_GOTOFF:
1011 case BFD_RELOC_8_PLT_PCREL:
1012 case BFD_RELOC_16_PLT_PCREL:
1013 case BFD_RELOC_32_PLT_PCREL:
1014 case BFD_RELOC_8_PLTOFF:
1015 case BFD_RELOC_16_PLTOFF:
1016 case BFD_RELOC_32_PLTOFF:
1017 break;
1018 default:
1019 as_bad_where (fixp->fx_file, fixp->fx_line,
1020 _("Cannot make %s relocation PC relative"),
1021 bfd_get_reloc_code_name (code));
1022 }
1023 }
1024 }
1025 else
1026 {
1027 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1028 switch (F (fixp->fx_size, fixp->fx_pcrel))
1029 {
1030 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1031 MAP (1, 0, BFD_RELOC_8);
1032 MAP (2, 0, BFD_RELOC_16);
1033 MAP (4, 0, BFD_RELOC_32);
1034 MAP (1, 1, BFD_RELOC_8_PCREL);
1035 MAP (2, 1, BFD_RELOC_16_PCREL);
1036 MAP (4, 1, BFD_RELOC_32_PCREL);
1037 default:
1038 abort ();
1039 }
1040 }
1041 #undef F
1042 #undef MAP
1043
1044 reloc = (arelent *) xmalloc (sizeof (arelent));
1045 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1046 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1047 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1048 #ifndef OBJ_ELF
1049 if (fixp->fx_pcrel)
1050 reloc->addend = fixp->fx_addnumber;
1051 else
1052 reloc->addend = 0;
1053 #else
1054 if (!fixp->fx_pcrel)
1055 reloc->addend = fixp->fx_addnumber;
1056 else
1057 reloc->addend = (section->vma
1058 /* Explicit sign extension in case char is
1059 unsigned. */
1060 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1061 + fixp->fx_addnumber
1062 + md_pcrel_from (fixp));
1063 #endif
1064
1065 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1066 assert (reloc->howto != 0);
1067
1068 return reloc;
1069 }
1070
1071 #endif /* BFD_ASSEMBLER */
1072
1073 /* Handle of the OPCODE hash table. NULL means any use before
1074 m68k_ip_begin() will crash. */
1075 static struct hash_control *op_hash;
1076 \f
1077 /* Assemble an m68k instruction. */
1078
1079 static void
1080 m68k_ip (char *instring)
1081 {
1082 register char *p;
1083 register struct m68k_op *opP;
1084 register const struct m68k_incant *opcode;
1085 register const char *s;
1086 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1087 char *pdot, *pdotmove;
1088 enum m68k_size siz1, siz2;
1089 char c;
1090 int losing;
1091 int opsfound;
1092 LITTLENUM_TYPE words[6];
1093 LITTLENUM_TYPE *wordp;
1094 unsigned long ok_arch = 0;
1095
1096 if (*instring == ' ')
1097 instring++; /* Skip leading whitespace. */
1098
1099 /* Scan up to end of operation-code, which MUST end in end-of-string
1100 or exactly 1 space. */
1101 pdot = 0;
1102 for (p = instring; *p != '\0'; p++)
1103 {
1104 if (*p == ' ')
1105 break;
1106 if (*p == '.')
1107 pdot = p;
1108 }
1109
1110 if (p == instring)
1111 {
1112 the_ins.error = _("No operator");
1113 return;
1114 }
1115
1116 /* p now points to the end of the opcode name, probably whitespace.
1117 Make sure the name is null terminated by clobbering the
1118 whitespace, look it up in the hash table, then fix it back.
1119 Remove a dot, first, since the opcode tables have none. */
1120 if (pdot != NULL)
1121 {
1122 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1123 *pdotmove = pdotmove[1];
1124 p--;
1125 }
1126
1127 c = *p;
1128 *p = '\0';
1129 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1130 *p = c;
1131
1132 if (pdot != NULL)
1133 {
1134 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1135 *pdotmove = pdotmove[-1];
1136 *pdot = '.';
1137 ++p;
1138 }
1139
1140 if (opcode == NULL)
1141 {
1142 the_ins.error = _("Unknown operator");
1143 return;
1144 }
1145
1146 /* Found a legitimate opcode, start matching operands. */
1147 while (*p == ' ')
1148 ++p;
1149
1150 if (opcode->m_operands == 0)
1151 {
1152 char *old = input_line_pointer;
1153 *old = '\n';
1154 input_line_pointer = p;
1155 /* Ahh - it's a motorola style psuedo op. */
1156 mote_pseudo_table[opcode->m_opnum].poc_handler
1157 (mote_pseudo_table[opcode->m_opnum].poc_val);
1158 input_line_pointer = old;
1159 *old = 0;
1160
1161 return;
1162 }
1163
1164 if (flag_mri && opcode->m_opnum == 0)
1165 {
1166 /* In MRI mode, random garbage is allowed after an instruction
1167 which accepts no operands. */
1168 the_ins.args = opcode->m_operands;
1169 the_ins.numargs = opcode->m_opnum;
1170 the_ins.numo = opcode->m_codenum;
1171 the_ins.opcode[0] = getone (opcode);
1172 the_ins.opcode[1] = gettwo (opcode);
1173 return;
1174 }
1175
1176 for (opP = &the_ins.operands[0]; *p; opP++)
1177 {
1178 p = crack_operand (p, opP);
1179
1180 if (opP->error)
1181 {
1182 the_ins.error = opP->error;
1183 return;
1184 }
1185 }
1186
1187 opsfound = opP - &the_ins.operands[0];
1188
1189 /* This ugly hack is to support the floating pt opcodes in their
1190 standard form. Essentially, we fake a first enty of type COP#1 */
1191 if (opcode->m_operands[0] == 'I')
1192 {
1193 int n;
1194
1195 for (n = opsfound; n > 0; --n)
1196 the_ins.operands[n] = the_ins.operands[n - 1];
1197
1198 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1199 the_ins.operands[0].mode = CONTROL;
1200 the_ins.operands[0].reg = m68k_float_copnum;
1201 opsfound++;
1202 }
1203
1204 /* We've got the operands. Find an opcode that'll accept them. */
1205 for (losing = 0;;)
1206 {
1207 /* If we didn't get the right number of ops, or we have no
1208 common model with this pattern then reject this pattern. */
1209
1210 ok_arch |= opcode->m_arch;
1211 if (opsfound != opcode->m_opnum
1212 || ((opcode->m_arch & current_architecture) == 0))
1213 ++losing;
1214 else
1215 {
1216 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1217 *s && !losing;
1218 s += 2, opP++)
1219 {
1220 /* Warning: this switch is huge! */
1221 /* I've tried to organize the cases into this order:
1222 non-alpha first, then alpha by letter. Lower-case
1223 goes directly before uppercase counterpart. */
1224 /* Code with multiple case ...: gets sorted by the lowest
1225 case ... it belongs to. I hope this makes sense. */
1226 switch (*s)
1227 {
1228 case '!':
1229 switch (opP->mode)
1230 {
1231 case IMMED:
1232 case DREG:
1233 case AREG:
1234 case FPREG:
1235 case CONTROL:
1236 case AINC:
1237 case ADEC:
1238 case REGLST:
1239 losing++;
1240 break;
1241 default:
1242 break;
1243 }
1244 break;
1245
1246 case '<':
1247 switch (opP->mode)
1248 {
1249 case DREG:
1250 case AREG:
1251 case FPREG:
1252 case CONTROL:
1253 case IMMED:
1254 case ADEC:
1255 case REGLST:
1256 losing++;
1257 break;
1258 default:
1259 break;
1260 }
1261 break;
1262
1263 case '>':
1264 switch (opP->mode)
1265 {
1266 case DREG:
1267 case AREG:
1268 case FPREG:
1269 case CONTROL:
1270 case IMMED:
1271 case AINC:
1272 case REGLST:
1273 losing++;
1274 break;
1275 case ABSL:
1276 break;
1277 default:
1278 if (opP->reg == PC
1279 || opP->reg == ZPC)
1280 losing++;
1281 break;
1282 }
1283 break;
1284
1285 case 'm':
1286 switch (opP->mode)
1287 {
1288 case DREG:
1289 case AREG:
1290 case AINDR:
1291 case AINC:
1292 case ADEC:
1293 break;
1294 default:
1295 losing++;
1296 }
1297 break;
1298
1299 case 'n':
1300 switch (opP->mode)
1301 {
1302 case DISP:
1303 break;
1304 default:
1305 losing++;
1306 }
1307 break;
1308
1309 case 'o':
1310 switch (opP->mode)
1311 {
1312 case BASE:
1313 case ABSL:
1314 case IMMED:
1315 break;
1316 default:
1317 losing++;
1318 }
1319 break;
1320
1321 case 'p':
1322 switch (opP->mode)
1323 {
1324 case DREG:
1325 case AREG:
1326 case AINDR:
1327 case AINC:
1328 case ADEC:
1329 break;
1330 case DISP:
1331 if (opP->reg == PC || opP->reg == ZPC)
1332 losing++;
1333 break;
1334 default:
1335 losing++;
1336 }
1337 break;
1338
1339 case 'q':
1340 switch (opP->mode)
1341 {
1342 case DREG:
1343 case AINDR:
1344 case AINC:
1345 case ADEC:
1346 break;
1347 case DISP:
1348 if (opP->reg == PC || opP->reg == ZPC)
1349 losing++;
1350 break;
1351 default:
1352 losing++;
1353 break;
1354 }
1355 break;
1356
1357 case 'v':
1358 switch (opP->mode)
1359 {
1360 case DREG:
1361 case AINDR:
1362 case AINC:
1363 case ADEC:
1364 case ABSL:
1365 break;
1366 case DISP:
1367 if (opP->reg == PC || opP->reg == ZPC)
1368 losing++;
1369 break;
1370 default:
1371 losing++;
1372 break;
1373 }
1374 break;
1375
1376 case '#':
1377 if (opP->mode != IMMED)
1378 losing++;
1379 else if (s[1] == 'b'
1380 && ! isvar (&opP->disp)
1381 && (opP->disp.exp.X_op != O_constant
1382 || ! isbyte (opP->disp.exp.X_add_number)))
1383 losing++;
1384 else if (s[1] == 'B'
1385 && ! isvar (&opP->disp)
1386 && (opP->disp.exp.X_op != O_constant
1387 || ! issbyte (opP->disp.exp.X_add_number)))
1388 losing++;
1389 else if (s[1] == 'w'
1390 && ! isvar (&opP->disp)
1391 && (opP->disp.exp.X_op != O_constant
1392 || ! isword (opP->disp.exp.X_add_number)))
1393 losing++;
1394 else if (s[1] == 'W'
1395 && ! isvar (&opP->disp)
1396 && (opP->disp.exp.X_op != O_constant
1397 || ! issword (opP->disp.exp.X_add_number)))
1398 losing++;
1399 break;
1400
1401 case '^':
1402 case 'T':
1403 if (opP->mode != IMMED)
1404 losing++;
1405 break;
1406
1407 case '$':
1408 if (opP->mode == AREG
1409 || opP->mode == CONTROL
1410 || opP->mode == FPREG
1411 || opP->mode == IMMED
1412 || opP->mode == REGLST
1413 || (opP->mode != ABSL
1414 && (opP->reg == PC
1415 || opP->reg == ZPC)))
1416 losing++;
1417 break;
1418
1419 case '%':
1420 if (opP->mode == CONTROL
1421 || opP->mode == FPREG
1422 || opP->mode == REGLST
1423 || opP->mode == IMMED
1424 || (opP->mode != ABSL
1425 && (opP->reg == PC
1426 || opP->reg == ZPC)))
1427 losing++;
1428 break;
1429
1430 case '&':
1431 switch (opP->mode)
1432 {
1433 case DREG:
1434 case AREG:
1435 case FPREG:
1436 case CONTROL:
1437 case IMMED:
1438 case AINC:
1439 case ADEC:
1440 case REGLST:
1441 losing++;
1442 break;
1443 case ABSL:
1444 break;
1445 default:
1446 if (opP->reg == PC
1447 || opP->reg == ZPC)
1448 losing++;
1449 break;
1450 }
1451 break;
1452
1453 case '*':
1454 if (opP->mode == CONTROL
1455 || opP->mode == FPREG
1456 || opP->mode == REGLST)
1457 losing++;
1458 break;
1459
1460 case '+':
1461 if (opP->mode != AINC)
1462 losing++;
1463 break;
1464
1465 case '-':
1466 if (opP->mode != ADEC)
1467 losing++;
1468 break;
1469
1470 case '/':
1471 switch (opP->mode)
1472 {
1473 case AREG:
1474 case CONTROL:
1475 case FPREG:
1476 case AINC:
1477 case ADEC:
1478 case IMMED:
1479 case REGLST:
1480 losing++;
1481 break;
1482 default:
1483 break;
1484 }
1485 break;
1486
1487 case ';':
1488 switch (opP->mode)
1489 {
1490 case AREG:
1491 case CONTROL:
1492 case FPREG:
1493 case REGLST:
1494 losing++;
1495 break;
1496 default:
1497 break;
1498 }
1499 break;
1500
1501 case '?':
1502 switch (opP->mode)
1503 {
1504 case AREG:
1505 case CONTROL:
1506 case FPREG:
1507 case AINC:
1508 case ADEC:
1509 case IMMED:
1510 case REGLST:
1511 losing++;
1512 break;
1513 case ABSL:
1514 break;
1515 default:
1516 if (opP->reg == PC || opP->reg == ZPC)
1517 losing++;
1518 break;
1519 }
1520 break;
1521
1522 case '@':
1523 switch (opP->mode)
1524 {
1525 case AREG:
1526 case CONTROL:
1527 case FPREG:
1528 case IMMED:
1529 case REGLST:
1530 losing++;
1531 break;
1532 default:
1533 break;
1534 }
1535 break;
1536
1537 case '~': /* For now! (JF FOO is this right?) */
1538 switch (opP->mode)
1539 {
1540 case DREG:
1541 case AREG:
1542 case CONTROL:
1543 case FPREG:
1544 case IMMED:
1545 case REGLST:
1546 losing++;
1547 break;
1548 case ABSL:
1549 break;
1550 default:
1551 if (opP->reg == PC
1552 || opP->reg == ZPC)
1553 losing++;
1554 break;
1555 }
1556 break;
1557
1558 case '3':
1559 if (opP->mode != CONTROL
1560 || (opP->reg != TT0 && opP->reg != TT1))
1561 losing++;
1562 break;
1563
1564 case 'A':
1565 if (opP->mode != AREG)
1566 losing++;
1567 break;
1568
1569 case 'a':
1570 if (opP->mode != AINDR)
1571 ++losing;
1572 break;
1573
1574 case '4':
1575 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1576 && (opP->mode != DISP
1577 || opP->reg < ADDR0
1578 || opP->reg > ADDR7))
1579 ++losing;
1580 break;
1581
1582 case 'B': /* FOO */
1583 if (opP->mode != ABSL
1584 || (flag_long_jumps
1585 && strncmp (instring, "jbsr", 4) == 0))
1586 losing++;
1587 break;
1588
1589 case 'b':
1590 switch (opP->mode)
1591 {
1592 case IMMED:
1593 case ABSL:
1594 case AREG:
1595 case FPREG:
1596 case CONTROL:
1597 case POST:
1598 case PRE:
1599 case REGLST:
1600 losing++;
1601 break;
1602 default:
1603 break;
1604 }
1605 break;
1606
1607 case 'C':
1608 if (opP->mode != CONTROL || opP->reg != CCR)
1609 losing++;
1610 break;
1611
1612 case 'd':
1613 if (opP->mode != DISP
1614 || opP->reg < ADDR0
1615 || opP->reg > ADDR7)
1616 losing++;
1617 break;
1618
1619 case 'D':
1620 if (opP->mode != DREG)
1621 losing++;
1622 break;
1623
1624 case 'E':
1625 if (opP->reg != ACC)
1626 losing++;
1627 break;
1628
1629 case 'e':
1630 if (opP->reg != ACC && opP->reg != ACC1
1631 && opP->reg != ACC2 && opP->reg != ACC3)
1632 losing++;
1633 break;
1634
1635 case 'F':
1636 if (opP->mode != FPREG)
1637 losing++;
1638 break;
1639
1640 case 'G':
1641 if (opP->reg != MACSR)
1642 losing++;
1643 break;
1644
1645 case 'g':
1646 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1647 losing++;
1648 break;
1649
1650 case 'H':
1651 if (opP->reg != MASK)
1652 losing++;
1653 break;
1654
1655 case 'I':
1656 if (opP->mode != CONTROL
1657 || opP->reg < COP0
1658 || opP->reg > COP7)
1659 losing++;
1660 break;
1661
1662 case 'i':
1663 if (opP->mode != LSH && opP->mode != RSH)
1664 losing++;
1665 break;
1666
1667 case 'J':
1668 if (opP->mode != CONTROL
1669 || opP->reg < USP
1670 || opP->reg > last_movec_reg)
1671 losing++;
1672 else
1673 {
1674 const enum m68k_register *rp;
1675 for (rp = control_regs; *rp; rp++)
1676 if (*rp == opP->reg)
1677 break;
1678 if (*rp == 0)
1679 losing++;
1680 }
1681 break;
1682
1683 case 'k':
1684 if (opP->mode != IMMED)
1685 losing++;
1686 break;
1687
1688 case 'l':
1689 case 'L':
1690 if (opP->mode == DREG
1691 || opP->mode == AREG
1692 || opP->mode == FPREG)
1693 {
1694 if (s[1] == '8')
1695 losing++;
1696 else
1697 {
1698 switch (opP->mode)
1699 {
1700 case DREG:
1701 opP->mask = 1 << (opP->reg - DATA0);
1702 break;
1703 case AREG:
1704 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1705 break;
1706 case FPREG:
1707 opP->mask = 1 << (opP->reg - FP0 + 16);
1708 break;
1709 default:
1710 abort ();
1711 }
1712 opP->mode = REGLST;
1713 }
1714 }
1715 else if (opP->mode == CONTROL)
1716 {
1717 if (s[1] != '8')
1718 losing++;
1719 else
1720 {
1721 switch (opP->reg)
1722 {
1723 case FPI:
1724 opP->mask = 1 << 24;
1725 break;
1726 case FPS:
1727 opP->mask = 1 << 25;
1728 break;
1729 case FPC:
1730 opP->mask = 1 << 26;
1731 break;
1732 default:
1733 losing++;
1734 break;
1735 }
1736 opP->mode = REGLST;
1737 }
1738 }
1739 else if (opP->mode != REGLST)
1740 losing++;
1741 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1742 losing++;
1743 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1744 losing++;
1745 break;
1746
1747 case 'M':
1748 if (opP->mode != IMMED)
1749 losing++;
1750 else if (opP->disp.exp.X_op != O_constant
1751 || ! issbyte (opP->disp.exp.X_add_number))
1752 losing++;
1753 else if (! m68k_quick
1754 && instring[3] != 'q'
1755 && instring[4] != 'q')
1756 losing++;
1757 break;
1758
1759 case 'O':
1760 if (opP->mode != DREG
1761 && opP->mode != IMMED
1762 && opP->mode != ABSL)
1763 losing++;
1764 break;
1765
1766 case 'Q':
1767 if (opP->mode != IMMED)
1768 losing++;
1769 else if (opP->disp.exp.X_op != O_constant
1770 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1771 losing++;
1772 else if (! m68k_quick
1773 && (strncmp (instring, "add", 3) == 0
1774 || strncmp (instring, "sub", 3) == 0)
1775 && instring[3] != 'q')
1776 losing++;
1777 break;
1778
1779 case 'R':
1780 if (opP->mode != DREG && opP->mode != AREG)
1781 losing++;
1782 break;
1783
1784 case 'r':
1785 if (opP->mode != AINDR
1786 && (opP->mode != BASE
1787 || (opP->reg != 0
1788 && opP->reg != ZADDR0)
1789 || opP->disp.exp.X_op != O_absent
1790 || ((opP->index.reg < DATA0
1791 || opP->index.reg > DATA7)
1792 && (opP->index.reg < ADDR0
1793 || opP->index.reg > ADDR7))
1794 || opP->index.size != SIZE_UNSPEC
1795 || opP->index.scale != 1))
1796 losing++;
1797 break;
1798
1799 case 's':
1800 if (opP->mode != CONTROL
1801 || ! (opP->reg == FPI
1802 || opP->reg == FPS
1803 || opP->reg == FPC))
1804 losing++;
1805 break;
1806
1807 case 'S':
1808 if (opP->mode != CONTROL || opP->reg != SR)
1809 losing++;
1810 break;
1811
1812 case 't':
1813 if (opP->mode != IMMED)
1814 losing++;
1815 else if (opP->disp.exp.X_op != O_constant
1816 || TRUNC (opP->disp.exp.X_add_number) > 7)
1817 losing++;
1818 break;
1819
1820 case 'U':
1821 if (opP->mode != CONTROL || opP->reg != USP)
1822 losing++;
1823 break;
1824
1825 case 'x':
1826 if (opP->mode != IMMED)
1827 losing++;
1828 else if (opP->disp.exp.X_op != O_constant
1829 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1830 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
1831 losing++;
1832 break;
1833
1834 /* JF these are out of order. We could put them
1835 in order if we were willing to put up with
1836 bunches of #ifdef m68851s in the code.
1837
1838 Don't forget that you need these operands
1839 to use 68030 MMU instructions. */
1840 #ifndef NO_68851
1841 /* Memory addressing mode used by pflushr. */
1842 case '|':
1843 if (opP->mode == CONTROL
1844 || opP->mode == FPREG
1845 || opP->mode == DREG
1846 || opP->mode == AREG
1847 || opP->mode == REGLST)
1848 losing++;
1849 /* We should accept immediate operands, but they
1850 supposedly have to be quad word, and we don't
1851 handle that. I would like to see what a Motorola
1852 assembler does before doing something here. */
1853 if (opP->mode == IMMED)
1854 losing++;
1855 break;
1856
1857 case 'f':
1858 if (opP->mode != CONTROL
1859 || (opP->reg != SFC && opP->reg != DFC))
1860 losing++;
1861 break;
1862
1863 case '0':
1864 if (opP->mode != CONTROL || opP->reg != TC)
1865 losing++;
1866 break;
1867
1868 case '1':
1869 if (opP->mode != CONTROL || opP->reg != AC)
1870 losing++;
1871 break;
1872
1873 case '2':
1874 if (opP->mode != CONTROL
1875 || (opP->reg != CAL
1876 && opP->reg != VAL
1877 && opP->reg != SCC))
1878 losing++;
1879 break;
1880
1881 case 'V':
1882 if (opP->mode != CONTROL
1883 || opP->reg != VAL)
1884 losing++;
1885 break;
1886
1887 case 'W':
1888 if (opP->mode != CONTROL
1889 || (opP->reg != DRP
1890 && opP->reg != SRP
1891 && opP->reg != CRP))
1892 losing++;
1893 break;
1894
1895 case 'w':
1896 switch (opP->mode)
1897 {
1898 case IMMED:
1899 case ABSL:
1900 case AREG:
1901 case DREG:
1902 case FPREG:
1903 case CONTROL:
1904 case POST:
1905 case PRE:
1906 case REGLST:
1907 losing++;
1908 break;
1909 default:
1910 break;
1911 }
1912 break;
1913
1914 case 'X':
1915 if (opP->mode != CONTROL
1916 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1917 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1918 losing++;
1919 break;
1920
1921 case 'Y':
1922 if (opP->mode != CONTROL || opP->reg != PSR)
1923 losing++;
1924 break;
1925
1926 case 'Z':
1927 if (opP->mode != CONTROL || opP->reg != PCSR)
1928 losing++;
1929 break;
1930 #endif
1931 case 'c':
1932 if (opP->mode != CONTROL
1933 || (opP->reg != NC
1934 && opP->reg != IC
1935 && opP->reg != DC
1936 && opP->reg != BC))
1937 losing++;
1938 break;
1939
1940 case '_':
1941 if (opP->mode != ABSL)
1942 ++losing;
1943 break;
1944
1945 case 'u':
1946 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1947 losing++;
1948 /* FIXME: kludge instead of fixing parser:
1949 upper/lower registers are *not* CONTROL
1950 registers, but ordinary ones. */
1951 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1952 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1953 opP->mode = DREG;
1954 else
1955 opP->mode = AREG;
1956 break;
1957
1958 case 'y':
1959 if (!(opP->mode == AINDR
1960 || (opP->mode == DISP
1961 && !(opP->reg == PC || opP->reg == ZPC))))
1962 losing++;
1963 break;
1964
1965 case 'z':
1966 if (!(opP->mode == AINDR || opP->mode == DISP))
1967 losing++;
1968 break;
1969
1970 default:
1971 abort ();
1972 }
1973
1974 if (losing)
1975 break;
1976 }
1977 }
1978
1979 if (!losing)
1980 break;
1981
1982 opcode = opcode->m_next;
1983
1984 if (!opcode)
1985 {
1986 if (ok_arch
1987 && !(ok_arch & current_architecture))
1988 {
1989 char buf[200], *cp;
1990
1991 strncpy (buf,
1992 _("invalid instruction for this architecture; needs "),
1993 sizeof (buf));
1994 cp = buf + strlen (buf);
1995 switch (ok_arch)
1996 {
1997 case mcfisa_a:
1998 strncpy (cp, _("ColdFire ISA_A"),
1999 sizeof (buf) - (cp - buf));
2000 cp += strlen (cp);
2001 strncpy (cp, find_cf_chip (ok_arch),
2002 sizeof (buf) - (cp - buf));
2003 cp += strlen (cp);
2004 break;
2005 case mcfhwdiv:
2006 strncpy (cp, _("ColdFire hardware divide"),
2007 sizeof (buf) - (cp - buf));
2008 cp += strlen (cp);
2009 strncpy (cp, find_cf_chip (ok_arch),
2010 sizeof (buf) - (cp - buf));
2011 cp += strlen (cp);
2012 break;
2013 case mcfisa_aa:
2014 strncpy (cp, _("ColdFire ISA_A+"),
2015 sizeof (buf) - (cp - buf));
2016 cp += strlen (cp);
2017 strncpy (cp, find_cf_chip (ok_arch),
2018 sizeof (buf) - (cp - buf));
2019 cp += strlen (cp);
2020 break;
2021 case mcfisa_b:
2022 strncpy (cp, _("ColdFire ISA_B"),
2023 sizeof (buf) - (cp - buf));
2024 cp += strlen (cp);
2025 strncpy (cp, find_cf_chip (ok_arch),
2026 sizeof (buf) - (cp - buf));
2027 cp += strlen (cp);
2028 break;
2029 case cfloat:
2030 strncpy (cp, _("ColdFire fpu"), sizeof (buf) - (cp - buf));
2031 cp += strlen (cp);
2032 strncpy (cp, find_cf_chip (ok_arch),
2033 sizeof (buf) - (cp - buf));
2034 cp += strlen (cp);
2035 break;
2036 case mfloat:
2037 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
2038 break;
2039 case mmmu:
2040 strcpy (cp, _("mmu (68030 or 68851)"));
2041 break;
2042 case m68020up:
2043 strcpy (cp, _("68020 or higher"));
2044 break;
2045 case m68000up:
2046 strcpy (cp, _("68000 or higher"));
2047 break;
2048 case m68010up:
2049 strcpy (cp, _("68010 or higher"));
2050 break;
2051 default:
2052 {
2053 int got_one = 0, idx;
2054
2055 for (idx = 0; idx < n_archs; idx++)
2056 {
2057 if ((archs[idx].arch & ok_arch)
2058 && ! archs[idx].alias)
2059 {
2060 if (got_one)
2061 {
2062 strcpy (cp, " or ");
2063 cp += strlen (cp);
2064 }
2065 got_one = 1;
2066 strcpy (cp, archs[idx].name);
2067 cp += strlen (cp);
2068 }
2069 }
2070 }
2071 }
2072 cp = xmalloc (strlen (buf) + 1);
2073 strcpy (cp, buf);
2074 the_ins.error = cp;
2075 }
2076 else
2077 the_ins.error = _("operands mismatch");
2078 return;
2079 }
2080
2081 losing = 0;
2082 }
2083
2084 /* Now assemble it. */
2085 the_ins.args = opcode->m_operands;
2086 the_ins.numargs = opcode->m_opnum;
2087 the_ins.numo = opcode->m_codenum;
2088 the_ins.opcode[0] = getone (opcode);
2089 the_ins.opcode[1] = gettwo (opcode);
2090
2091 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2092 {
2093 /* This switch is a doozy.
2094 Watch the first step; its a big one! */
2095 switch (s[0])
2096 {
2097
2098 case '*':
2099 case '~':
2100 case '%':
2101 case ';':
2102 case '@':
2103 case '!':
2104 case '&':
2105 case '$':
2106 case '?':
2107 case '/':
2108 case '<':
2109 case '>':
2110 case 'b':
2111 case 'm':
2112 case 'n':
2113 case 'o':
2114 case 'p':
2115 case 'q':
2116 case 'v':
2117 case 'w':
2118 case 'y':
2119 case 'z':
2120 case '4':
2121 #ifndef NO_68851
2122 case '|':
2123 #endif
2124 switch (opP->mode)
2125 {
2126 case IMMED:
2127 tmpreg = 0x3c; /* 7.4 */
2128 if (strchr ("bwl", s[1]))
2129 nextword = get_num (&opP->disp, 90);
2130 else
2131 nextword = get_num (&opP->disp, 0);
2132 if (isvar (&opP->disp))
2133 add_fix (s[1], &opP->disp, 0, 0);
2134 switch (s[1])
2135 {
2136 case 'b':
2137 if (!isbyte (nextword))
2138 opP->error = _("operand out of range");
2139 addword (nextword);
2140 baseo = 0;
2141 break;
2142 case 'w':
2143 if (!isword (nextword))
2144 opP->error = _("operand out of range");
2145 addword (nextword);
2146 baseo = 0;
2147 break;
2148 case 'W':
2149 if (!issword (nextword))
2150 opP->error = _("operand out of range");
2151 addword (nextword);
2152 baseo = 0;
2153 break;
2154 case 'l':
2155 addword (nextword >> 16);
2156 addword (nextword);
2157 baseo = 0;
2158 break;
2159
2160 case 'f':
2161 baseo = 2;
2162 outro = 8;
2163 break;
2164 case 'F':
2165 baseo = 4;
2166 outro = 11;
2167 break;
2168 case 'x':
2169 baseo = 6;
2170 outro = 15;
2171 break;
2172 case 'p':
2173 baseo = 6;
2174 outro = -1;
2175 break;
2176 default:
2177 abort ();
2178 }
2179 if (!baseo)
2180 break;
2181
2182 /* We gotta put out some float. */
2183 if (op (&opP->disp) != O_big)
2184 {
2185 valueT val;
2186 int gencnt;
2187
2188 /* Can other cases happen here? */
2189 if (op (&opP->disp) != O_constant)
2190 abort ();
2191
2192 val = (valueT) offs (&opP->disp);
2193 gencnt = 0;
2194 do
2195 {
2196 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2197 val >>= LITTLENUM_NUMBER_OF_BITS;
2198 ++gencnt;
2199 }
2200 while (val != 0);
2201 offs (&opP->disp) = gencnt;
2202 }
2203 if (offs (&opP->disp) > 0)
2204 {
2205 if (offs (&opP->disp) > baseo)
2206 {
2207 as_warn (_("Bignum too big for %c format; truncated"),
2208 s[1]);
2209 offs (&opP->disp) = baseo;
2210 }
2211 baseo -= offs (&opP->disp);
2212 while (baseo--)
2213 addword (0);
2214 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2215 offs (&opP->disp)--;
2216 --wordp)
2217 addword (*wordp);
2218 break;
2219 }
2220 gen_to_words (words, baseo, (long) outro);
2221 for (wordp = words; baseo--; wordp++)
2222 addword (*wordp);
2223 break;
2224 case DREG:
2225 tmpreg = opP->reg - DATA; /* 0.dreg */
2226 break;
2227 case AREG:
2228 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2229 break;
2230 case AINDR:
2231 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2232 break;
2233 case ADEC:
2234 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2235 break;
2236 case AINC:
2237 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2238 break;
2239 case DISP:
2240
2241 nextword = get_num (&opP->disp, 90);
2242
2243 /* Convert mode 5 addressing with a zero offset into
2244 mode 2 addressing to reduce the instruction size by a
2245 word. */
2246 if (! isvar (&opP->disp)
2247 && (nextword == 0)
2248 && (opP->disp.size == SIZE_UNSPEC)
2249 && (opP->reg >= ADDR0)
2250 && (opP->reg <= ADDR7))
2251 {
2252 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2253 break;
2254 }
2255
2256 if (opP->reg == PC
2257 && ! isvar (&opP->disp)
2258 && m68k_abspcadd)
2259 {
2260 opP->disp.exp.X_op = O_symbol;
2261 #ifndef BFD_ASSEMBLER
2262 opP->disp.exp.X_add_symbol = &abs_symbol;
2263 #else
2264 opP->disp.exp.X_add_symbol =
2265 section_symbol (absolute_section);
2266 #endif
2267 }
2268
2269 /* Force into index mode. Hope this works. */
2270
2271 /* We do the first bit for 32-bit displacements, and the
2272 second bit for 16 bit ones. It is possible that we
2273 should make the default be WORD instead of LONG, but
2274 I think that'd break GCC, so we put up with a little
2275 inefficiency for the sake of working output. */
2276
2277 if (!issword (nextword)
2278 || (isvar (&opP->disp)
2279 && ((opP->disp.size == SIZE_UNSPEC
2280 && flag_short_refs == 0
2281 && cpu_of_arch (current_architecture) >= m68020
2282 && ! arch_coldfire_p (current_architecture))
2283 || opP->disp.size == SIZE_LONG)))
2284 {
2285 if (cpu_of_arch (current_architecture) < m68020
2286 || arch_coldfire_p (current_architecture))
2287 opP->error =
2288 _("displacement too large for this architecture; needs 68020 or higher");
2289 if (opP->reg == PC)
2290 tmpreg = 0x3B; /* 7.3 */
2291 else
2292 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2293 if (isvar (&opP->disp))
2294 {
2295 if (opP->reg == PC)
2296 {
2297 if (opP->disp.size == SIZE_LONG
2298 #ifdef OBJ_ELF
2299 /* If the displacement needs pic
2300 relocation it cannot be relaxed. */
2301 || opP->disp.pic_reloc != pic_none
2302 #endif
2303 )
2304 {
2305 addword (0x0170);
2306 add_fix ('l', &opP->disp, 1, 2);
2307 }
2308 else
2309 {
2310 add_frag (adds (&opP->disp),
2311 SEXT (offs (&opP->disp)),
2312 TAB (PCREL1632, SZ_UNDEF));
2313 break;
2314 }
2315 }
2316 else
2317 {
2318 addword (0x0170);
2319 add_fix ('l', &opP->disp, 0, 0);
2320 }
2321 }
2322 else
2323 addword (0x0170);
2324 addword (nextword >> 16);
2325 }
2326 else
2327 {
2328 if (opP->reg == PC)
2329 tmpreg = 0x3A; /* 7.2 */
2330 else
2331 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2332
2333 if (isvar (&opP->disp))
2334 {
2335 if (opP->reg == PC)
2336 {
2337 add_fix ('w', &opP->disp, 1, 0);
2338 }
2339 else
2340 add_fix ('w', &opP->disp, 0, 0);
2341 }
2342 }
2343 addword (nextword);
2344 break;
2345
2346 case POST:
2347 case PRE:
2348 case BASE:
2349 nextword = 0;
2350 baseo = get_num (&opP->disp, 90);
2351 if (opP->mode == POST || opP->mode == PRE)
2352 outro = get_num (&opP->odisp, 90);
2353 /* Figure out the `addressing mode'.
2354 Also turn on the BASE_DISABLE bit, if needed. */
2355 if (opP->reg == PC || opP->reg == ZPC)
2356 {
2357 tmpreg = 0x3b; /* 7.3 */
2358 if (opP->reg == ZPC)
2359 nextword |= 0x80;
2360 }
2361 else if (opP->reg == 0)
2362 {
2363 nextword |= 0x80;
2364 tmpreg = 0x30; /* 6.garbage */
2365 }
2366 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2367 {
2368 nextword |= 0x80;
2369 tmpreg = 0x30 + opP->reg - ZADDR0;
2370 }
2371 else
2372 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2373
2374 siz1 = opP->disp.size;
2375 if (opP->mode == POST || opP->mode == PRE)
2376 siz2 = opP->odisp.size;
2377 else
2378 siz2 = SIZE_UNSPEC;
2379
2380 /* Index register stuff. */
2381 if (opP->index.reg != 0
2382 && opP->index.reg >= DATA
2383 && opP->index.reg <= ADDR7)
2384 {
2385 nextword |= (opP->index.reg - DATA) << 12;
2386
2387 if (opP->index.size == SIZE_LONG
2388 || (opP->index.size == SIZE_UNSPEC
2389 && m68k_index_width_default == SIZE_LONG))
2390 nextword |= 0x800;
2391
2392 if ((opP->index.scale != 1
2393 && cpu_of_arch (current_architecture) < m68020)
2394 || (opP->index.scale == 8
2395 && (arch_coldfire_p (current_architecture)
2396 && !arch_coldfire_fpu (current_architecture))))
2397 {
2398 opP->error =
2399 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2400 }
2401
2402 if (arch_coldfire_p (current_architecture)
2403 && opP->index.size == SIZE_WORD)
2404 opP->error = _("invalid index size for coldfire");
2405
2406 switch (opP->index.scale)
2407 {
2408 case 1:
2409 break;
2410 case 2:
2411 nextword |= 0x200;
2412 break;
2413 case 4:
2414 nextword |= 0x400;
2415 break;
2416 case 8:
2417 nextword |= 0x600;
2418 break;
2419 default:
2420 abort ();
2421 }
2422 /* IF its simple,
2423 GET US OUT OF HERE! */
2424
2425 /* Must be INDEX, with an index register. Address
2426 register cannot be ZERO-PC, and either :b was
2427 forced, or we know it will fit. For a 68000 or
2428 68010, force this mode anyways, because the
2429 larger modes aren't supported. */
2430 if (opP->mode == BASE
2431 && ((opP->reg >= ADDR0
2432 && opP->reg <= ADDR7)
2433 || opP->reg == PC))
2434 {
2435 if (siz1 == SIZE_BYTE
2436 || cpu_of_arch (current_architecture) < m68020
2437 || arch_coldfire_p (current_architecture)
2438 || (siz1 == SIZE_UNSPEC
2439 && ! isvar (&opP->disp)
2440 && issbyte (baseo)))
2441 {
2442 nextword += baseo & 0xff;
2443 addword (nextword);
2444 if (isvar (&opP->disp))
2445 {
2446 /* Do a byte relocation. If it doesn't
2447 fit (possible on m68000) let the
2448 fixup processing complain later. */
2449 if (opP->reg == PC)
2450 add_fix ('B', &opP->disp, 1, 1);
2451 else
2452 add_fix ('B', &opP->disp, 0, 0);
2453 }
2454 else if (siz1 != SIZE_BYTE)
2455 {
2456 if (siz1 != SIZE_UNSPEC)
2457 as_warn (_("Forcing byte displacement"));
2458 if (! issbyte (baseo))
2459 opP->error = _("byte displacement out of range");
2460 }
2461
2462 break;
2463 }
2464 else if (siz1 == SIZE_UNSPEC
2465 && opP->reg == PC
2466 && isvar (&opP->disp)
2467 && subs (&opP->disp) == NULL
2468 #ifdef OBJ_ELF
2469 /* If the displacement needs pic
2470 relocation it cannot be relaxed. */
2471 && opP->disp.pic_reloc == pic_none
2472 #endif
2473 )
2474 {
2475 /* The code in md_convert_frag_1 needs to be
2476 able to adjust nextword. Call frag_grow
2477 to ensure that we have enough space in
2478 the frag obstack to make all the bytes
2479 contiguous. */
2480 frag_grow (14);
2481 nextword += baseo & 0xff;
2482 addword (nextword);
2483 add_frag (adds (&opP->disp),
2484 SEXT (offs (&opP->disp)),
2485 TAB (PCINDEX, SZ_UNDEF));
2486
2487 break;
2488 }
2489 }
2490 }
2491 else
2492 {
2493 nextword |= 0x40; /* No index reg. */
2494 if (opP->index.reg >= ZDATA0
2495 && opP->index.reg <= ZDATA7)
2496 nextword |= (opP->index.reg - ZDATA0) << 12;
2497 else if (opP->index.reg >= ZADDR0
2498 || opP->index.reg <= ZADDR7)
2499 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2500 }
2501
2502 /* It isn't simple. */
2503
2504 if (cpu_of_arch (current_architecture) < m68020
2505 || arch_coldfire_p (current_architecture))
2506 opP->error =
2507 _("invalid operand mode for this architecture; needs 68020 or higher");
2508
2509 nextword |= 0x100;
2510 /* If the guy specified a width, we assume that it is
2511 wide enough. Maybe it isn't. If so, we lose. */
2512 switch (siz1)
2513 {
2514 case SIZE_UNSPEC:
2515 if (isvar (&opP->disp)
2516 ? m68k_rel32
2517 : ! issword (baseo))
2518 {
2519 siz1 = SIZE_LONG;
2520 nextword |= 0x30;
2521 }
2522 else if (! isvar (&opP->disp) && baseo == 0)
2523 nextword |= 0x10;
2524 else
2525 {
2526 nextword |= 0x20;
2527 siz1 = SIZE_WORD;
2528 }
2529 break;
2530 case SIZE_BYTE:
2531 as_warn (_(":b not permitted; defaulting to :w"));
2532 /* Fall through. */
2533 case SIZE_WORD:
2534 nextword |= 0x20;
2535 break;
2536 case SIZE_LONG:
2537 nextword |= 0x30;
2538 break;
2539 }
2540
2541 /* Figure out inner displacement stuff. */
2542 if (opP->mode == POST || opP->mode == PRE)
2543 {
2544 if (cpu_of_arch (current_architecture) & cpu32)
2545 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2546 switch (siz2)
2547 {
2548 case SIZE_UNSPEC:
2549 if (isvar (&opP->odisp)
2550 ? m68k_rel32
2551 : ! issword (outro))
2552 {
2553 siz2 = SIZE_LONG;
2554 nextword |= 0x3;
2555 }
2556 else if (! isvar (&opP->odisp) && outro == 0)
2557 nextword |= 0x1;
2558 else
2559 {
2560 nextword |= 0x2;
2561 siz2 = SIZE_WORD;
2562 }
2563 break;
2564 case 1:
2565 as_warn (_(":b not permitted; defaulting to :w"));
2566 /* Fall through. */
2567 case 2:
2568 nextword |= 0x2;
2569 break;
2570 case 3:
2571 nextword |= 0x3;
2572 break;
2573 }
2574 if (opP->mode == POST
2575 && (nextword & 0x40) == 0)
2576 nextword |= 0x04;
2577 }
2578 addword (nextword);
2579
2580 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2581 {
2582 if (opP->reg == PC || opP->reg == ZPC)
2583 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2584 else
2585 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2586 }
2587 if (siz1 == SIZE_LONG)
2588 addword (baseo >> 16);
2589 if (siz1 != SIZE_UNSPEC)
2590 addword (baseo);
2591
2592 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2593 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2594 if (siz2 == SIZE_LONG)
2595 addword (outro >> 16);
2596 if (siz2 != SIZE_UNSPEC)
2597 addword (outro);
2598
2599 break;
2600
2601 case ABSL:
2602 nextword = get_num (&opP->disp, 90);
2603 switch (opP->disp.size)
2604 {
2605 default:
2606 abort ();
2607 case SIZE_UNSPEC:
2608 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2609 {
2610 tmpreg = 0x38; /* 7.0 */
2611 addword (nextword);
2612 break;
2613 }
2614 if (isvar (&opP->disp)
2615 && !subs (&opP->disp)
2616 && adds (&opP->disp)
2617 #ifdef OBJ_ELF
2618 /* If the displacement needs pic relocation it
2619 cannot be relaxed. */
2620 && opP->disp.pic_reloc == pic_none
2621 #endif
2622 && !flag_long_jumps
2623 && !strchr ("~%&$?", s[0]))
2624 {
2625 tmpreg = 0x3A; /* 7.2 */
2626 add_frag (adds (&opP->disp),
2627 SEXT (offs (&opP->disp)),
2628 TAB (ABSTOPCREL, SZ_UNDEF));
2629 break;
2630 }
2631 /* Fall through into long. */
2632 case SIZE_LONG:
2633 if (isvar (&opP->disp))
2634 add_fix ('l', &opP->disp, 0, 0);
2635
2636 tmpreg = 0x39;/* 7.1 mode */
2637 addword (nextword >> 16);
2638 addword (nextword);
2639 break;
2640
2641 case SIZE_BYTE:
2642 as_bad (_("unsupported byte value; use a different suffix"));
2643 /* Fall through. */
2644
2645 case SIZE_WORD:
2646 if (isvar (&opP->disp))
2647 add_fix ('w', &opP->disp, 0, 0);
2648
2649 tmpreg = 0x38;/* 7.0 mode */
2650 addword (nextword);
2651 break;
2652 }
2653 break;
2654 case CONTROL:
2655 case FPREG:
2656 default:
2657 as_bad (_("unknown/incorrect operand"));
2658 /* abort (); */
2659 }
2660
2661 /* If s[0] is '4', then this is for the mac instructions
2662 that can have a trailing_ampersand set. If so, set 0x100
2663 bit on tmpreg so install_gen_operand can check for it and
2664 set the appropriate bit (word2, bit 5). */
2665 if (s[0] == '4')
2666 {
2667 if (opP->trailing_ampersand)
2668 tmpreg |= 0x100;
2669 }
2670 install_gen_operand (s[1], tmpreg);
2671 break;
2672
2673 case '#':
2674 case '^':
2675 switch (s[1])
2676 { /* JF: I hate floating point! */
2677 case 'j':
2678 tmpreg = 70;
2679 break;
2680 case '8':
2681 tmpreg = 20;
2682 break;
2683 case 'C':
2684 tmpreg = 50;
2685 break;
2686 case '3':
2687 default:
2688 tmpreg = 90;
2689 break;
2690 }
2691 tmpreg = get_num (&opP->disp, tmpreg);
2692 if (isvar (&opP->disp))
2693 add_fix (s[1], &opP->disp, 0, 0);
2694 switch (s[1])
2695 {
2696 case 'b': /* Danger: These do no check for
2697 certain types of overflow.
2698 user beware! */
2699 if (!isbyte (tmpreg))
2700 opP->error = _("out of range");
2701 insop (tmpreg, opcode);
2702 if (isvar (&opP->disp))
2703 the_ins.reloc[the_ins.nrel - 1].n =
2704 (opcode->m_codenum) * 2 + 1;
2705 break;
2706 case 'B':
2707 if (!issbyte (tmpreg))
2708 opP->error = _("out of range");
2709 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2710 if (isvar (&opP->disp))
2711 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2712 break;
2713 case 'w':
2714 if (!isword (tmpreg))
2715 opP->error = _("out of range");
2716 insop (tmpreg, opcode);
2717 if (isvar (&opP->disp))
2718 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2719 break;
2720 case 'W':
2721 if (!issword (tmpreg))
2722 opP->error = _("out of range");
2723 insop (tmpreg, opcode);
2724 if (isvar (&opP->disp))
2725 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2726 break;
2727 case 'l':
2728 /* Because of the way insop works, we put these two out
2729 backwards. */
2730 insop (tmpreg, opcode);
2731 insop (tmpreg >> 16, opcode);
2732 if (isvar (&opP->disp))
2733 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2734 break;
2735 case '3':
2736 tmpreg &= 0xFF;
2737 case '8':
2738 case 'C':
2739 case 'j':
2740 install_operand (s[1], tmpreg);
2741 break;
2742 default:
2743 abort ();
2744 }
2745 break;
2746
2747 case '+':
2748 case '-':
2749 case 'A':
2750 case 'a':
2751 install_operand (s[1], opP->reg - ADDR);
2752 break;
2753
2754 case 'B':
2755 tmpreg = get_num (&opP->disp, 90);
2756 switch (s[1])
2757 {
2758 case 'B':
2759 add_fix ('B', &opP->disp, 1, -1);
2760 break;
2761 case 'W':
2762 add_fix ('w', &opP->disp, 1, 0);
2763 addword (0);
2764 break;
2765 case 'L':
2766 long_branch:
2767 if (! HAVE_LONG_BRANCH (current_architecture))
2768 as_warn (_("Can't use long branches on 68000/68010/5200"));
2769 the_ins.opcode[0] |= 0xff;
2770 add_fix ('l', &opP->disp, 1, 0);
2771 addword (0);
2772 addword (0);
2773 break;
2774 case 'g':
2775 if (subs (&opP->disp)) /* We can't relax it. */
2776 goto long_branch;
2777
2778 #ifdef OBJ_ELF
2779 /* If the displacement needs pic relocation it cannot be
2780 relaxed. */
2781 if (opP->disp.pic_reloc != pic_none)
2782 goto long_branch;
2783 #endif
2784 /* This could either be a symbol, or an absolute
2785 address. If it's an absolute address, turn it into
2786 an absolute jump right here and keep it out of the
2787 relaxer. */
2788 if (adds (&opP->disp) == 0)
2789 {
2790 if (the_ins.opcode[0] == 0x6000) /* jbra */
2791 the_ins.opcode[0] = 0x4EF9;
2792 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2793 the_ins.opcode[0] = 0x4EB9;
2794 else /* jCC */
2795 {
2796 the_ins.opcode[0] ^= 0x0100;
2797 the_ins.opcode[0] |= 0x0006;
2798 addword (0x4EF9);
2799 }
2800 add_fix ('l', &opP->disp, 0, 0);
2801 addword (0);
2802 addword (0);
2803 break;
2804 }
2805
2806 /* Now we know it's going into the relaxer. Now figure
2807 out which mode. We try in this order of preference:
2808 long branch, absolute jump, byte/word branches only. */
2809 if (HAVE_LONG_BRANCH (current_architecture))
2810 add_frag (adds (&opP->disp),
2811 SEXT (offs (&opP->disp)),
2812 TAB (BRANCHBWL, SZ_UNDEF));
2813 else if (! flag_keep_pcrel)
2814 {
2815 if ((the_ins.opcode[0] == 0x6000)
2816 || (the_ins.opcode[0] == 0x6100))
2817 add_frag (adds (&opP->disp),
2818 SEXT (offs (&opP->disp)),
2819 TAB (BRABSJUNC, SZ_UNDEF));
2820 else
2821 add_frag (adds (&opP->disp),
2822 SEXT (offs (&opP->disp)),
2823 TAB (BRABSJCOND, SZ_UNDEF));
2824 }
2825 else
2826 add_frag (adds (&opP->disp),
2827 SEXT (offs (&opP->disp)),
2828 TAB (BRANCHBW, SZ_UNDEF));
2829 break;
2830 case 'w':
2831 if (isvar (&opP->disp))
2832 {
2833 /* Check for DBcc instructions. We can relax them,
2834 but only if we have long branches and/or absolute
2835 jumps. */
2836 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2837 && (HAVE_LONG_BRANCH (current_architecture)
2838 || (! flag_keep_pcrel)))
2839 {
2840 if (HAVE_LONG_BRANCH (current_architecture))
2841 add_frag (adds (&opP->disp),
2842 SEXT (offs (&opP->disp)),
2843 TAB (DBCCLBR, SZ_UNDEF));
2844 else
2845 add_frag (adds (&opP->disp),
2846 SEXT (offs (&opP->disp)),
2847 TAB (DBCCABSJ, SZ_UNDEF));
2848 break;
2849 }
2850 add_fix ('w', &opP->disp, 1, 0);
2851 }
2852 addword (0);
2853 break;
2854 case 'C': /* Fixed size LONG coproc branches. */
2855 add_fix ('l', &opP->disp, 1, 0);
2856 addword (0);
2857 addword (0);
2858 break;
2859 case 'c': /* Var size Coprocesssor branches. */
2860 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
2861 {
2862 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2863 add_fix ('l', &opP->disp, 1, 0);
2864 addword (0);
2865 addword (0);
2866 }
2867 else
2868 add_frag (adds (&opP->disp),
2869 SEXT (offs (&opP->disp)),
2870 TAB (FBRANCH, SZ_UNDEF));
2871 break;
2872 default:
2873 abort ();
2874 }
2875 break;
2876
2877 case 'C': /* Ignore it. */
2878 break;
2879
2880 case 'd': /* JF this is a kludge. */
2881 install_operand ('s', opP->reg - ADDR);
2882 tmpreg = get_num (&opP->disp, 90);
2883 if (!issword (tmpreg))
2884 {
2885 as_warn (_("Expression out of range, using 0"));
2886 tmpreg = 0;
2887 }
2888 addword (tmpreg);
2889 break;
2890
2891 case 'D':
2892 install_operand (s[1], opP->reg - DATA);
2893 break;
2894
2895 case 'e': /* EMAC ACCx, reg/reg. */
2896 install_operand (s[1], opP->reg - ACC);
2897 break;
2898
2899 case 'E': /* Ignore it. */
2900 break;
2901
2902 case 'F':
2903 install_operand (s[1], opP->reg - FP0);
2904 break;
2905
2906 case 'g': /* EMAC ACCEXTx. */
2907 install_operand (s[1], opP->reg - ACCEXT01);
2908 break;
2909
2910 case 'G': /* Ignore it. */
2911 case 'H':
2912 break;
2913
2914 case 'I':
2915 tmpreg = opP->reg - COP0;
2916 install_operand (s[1], tmpreg);
2917 break;
2918
2919 case 'i': /* MAC/EMAC scale factor. */
2920 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
2921 break;
2922
2923 case 'J': /* JF foo. */
2924 switch (opP->reg)
2925 {
2926 case SFC:
2927 tmpreg = 0x000;
2928 break;
2929 case DFC:
2930 tmpreg = 0x001;
2931 break;
2932 case CACR:
2933 tmpreg = 0x002;
2934 break;
2935 case TC:
2936 tmpreg = 0x003;
2937 break;
2938 case ACR0:
2939 case ITT0:
2940 tmpreg = 0x004;
2941 break;
2942 case ACR1:
2943 case ITT1:
2944 tmpreg = 0x005;
2945 break;
2946 case ACR2:
2947 case DTT0:
2948 tmpreg = 0x006;
2949 break;
2950 case ACR3:
2951 case DTT1:
2952 tmpreg = 0x007;
2953 break;
2954 case BUSCR:
2955 tmpreg = 0x008;
2956 break;
2957
2958 case USP:
2959 tmpreg = 0x800;
2960 break;
2961 case VBR:
2962 tmpreg = 0x801;
2963 break;
2964 case CAAR:
2965 tmpreg = 0x802;
2966 break;
2967 case MSP:
2968 tmpreg = 0x803;
2969 break;
2970 case ISP:
2971 tmpreg = 0x804;
2972 break;
2973 case MMUSR:
2974 tmpreg = 0x805;
2975 break;
2976 case URP:
2977 tmpreg = 0x806;
2978 break;
2979 case SRP:
2980 tmpreg = 0x807;
2981 break;
2982 case PCR:
2983 tmpreg = 0x808;
2984 break;
2985 case ROMBAR:
2986 tmpreg = 0xC00;
2987 break;
2988 case ROMBAR1:
2989 tmpreg = 0xC01;
2990 break;
2991 case FLASHBAR:
2992 case RAMBAR0:
2993 tmpreg = 0xC04;
2994 break;
2995 case RAMBAR:
2996 case RAMBAR1:
2997 tmpreg = 0xC05;
2998 break;
2999 case MPCR:
3000 tmpreg = 0xC0C;
3001 break;
3002 case EDRAMBAR:
3003 tmpreg = 0xC0D;
3004 break;
3005 case MBAR0:
3006 case MBAR2:
3007 case SECMBAR:
3008 tmpreg = 0xC0E;
3009 break;
3010 case MBAR1:
3011 case MBAR:
3012 tmpreg = 0xC0F;
3013 break;
3014 case PCR1U0:
3015 tmpreg = 0xD02;
3016 break;
3017 case PCR1L0:
3018 tmpreg = 0xD03;
3019 break;
3020 case PCR2U0:
3021 tmpreg = 0xD04;
3022 break;
3023 case PCR2L0:
3024 tmpreg = 0xD05;
3025 break;
3026 case PCR3U0:
3027 tmpreg = 0xD06;
3028 break;
3029 case PCR3L0:
3030 tmpreg = 0xD07;
3031 break;
3032 case PCR1L1:
3033 tmpreg = 0xD0A;
3034 break;
3035 case PCR1U1:
3036 tmpreg = 0xD0B;
3037 break;
3038 case PCR2L1:
3039 tmpreg = 0xD0C;
3040 break;
3041 case PCR2U1:
3042 tmpreg = 0xD0D;
3043 break;
3044 case PCR3L1:
3045 tmpreg = 0xD0E;
3046 break;
3047 case PCR3U1:
3048 tmpreg = 0xD0F;
3049 break;
3050 default:
3051 abort ();
3052 }
3053 install_operand (s[1], tmpreg);
3054 break;
3055
3056 case 'k':
3057 tmpreg = get_num (&opP->disp, 55);
3058 install_operand (s[1], tmpreg & 0x7f);
3059 break;
3060
3061 case 'l':
3062 tmpreg = opP->mask;
3063 if (s[1] == 'w')
3064 {
3065 if (tmpreg & 0x7FF0000)
3066 as_bad (_("Floating point register in register list"));
3067 insop (reverse_16_bits (tmpreg), opcode);
3068 }
3069 else
3070 {
3071 if (tmpreg & 0x700FFFF)
3072 as_bad (_("Wrong register in floating-point reglist"));
3073 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3074 }
3075 break;
3076
3077 case 'L':
3078 tmpreg = opP->mask;
3079 if (s[1] == 'w')
3080 {
3081 if (tmpreg & 0x7FF0000)
3082 as_bad (_("Floating point register in register list"));
3083 insop (tmpreg, opcode);
3084 }
3085 else if (s[1] == '8')
3086 {
3087 if (tmpreg & 0x0FFFFFF)
3088 as_bad (_("incorrect register in reglist"));
3089 install_operand (s[1], tmpreg >> 24);
3090 }
3091 else
3092 {
3093 if (tmpreg & 0x700FFFF)
3094 as_bad (_("wrong register in floating-point reglist"));
3095 else
3096 install_operand (s[1], tmpreg >> 16);
3097 }
3098 break;
3099
3100 case 'M':
3101 install_operand (s[1], get_num (&opP->disp, 60));
3102 break;
3103
3104 case 'O':
3105 tmpreg = ((opP->mode == DREG)
3106 ? 0x20 + (int) (opP->reg - DATA)
3107 : (get_num (&opP->disp, 40) & 0x1F));
3108 install_operand (s[1], tmpreg);
3109 break;
3110
3111 case 'Q':
3112 tmpreg = get_num (&opP->disp, 10);
3113 if (tmpreg == 8)
3114 tmpreg = 0;
3115 install_operand (s[1], tmpreg);
3116 break;
3117
3118 case 'R':
3119 /* This depends on the fact that ADDR registers are eight
3120 more than their corresponding DATA regs, so the result
3121 will have the ADDR_REG bit set. */
3122 install_operand (s[1], opP->reg - DATA);
3123 break;
3124
3125 case 'r':
3126 if (opP->mode == AINDR)
3127 install_operand (s[1], opP->reg - DATA);
3128 else
3129 install_operand (s[1], opP->index.reg - DATA);
3130 break;
3131
3132 case 's':
3133 if (opP->reg == FPI)
3134 tmpreg = 0x1;
3135 else if (opP->reg == FPS)
3136 tmpreg = 0x2;
3137 else if (opP->reg == FPC)
3138 tmpreg = 0x4;
3139 else
3140 abort ();
3141 install_operand (s[1], tmpreg);
3142 break;
3143
3144 case 'S': /* Ignore it. */
3145 break;
3146
3147 case 'T':
3148 install_operand (s[1], get_num (&opP->disp, 30));
3149 break;
3150
3151 case 'U': /* Ignore it. */
3152 break;
3153
3154 case 'c':
3155 switch (opP->reg)
3156 {
3157 case NC:
3158 tmpreg = 0;
3159 break;
3160 case DC:
3161 tmpreg = 1;
3162 break;
3163 case IC:
3164 tmpreg = 2;
3165 break;
3166 case BC:
3167 tmpreg = 3;
3168 break;
3169 default:
3170 as_fatal (_("failed sanity check"));
3171 } /* switch on cache token. */
3172 install_operand (s[1], tmpreg);
3173 break;
3174 #ifndef NO_68851
3175 /* JF: These are out of order, I fear. */
3176 case 'f':
3177 switch (opP->reg)
3178 {
3179 case SFC:
3180 tmpreg = 0;
3181 break;
3182 case DFC:
3183 tmpreg = 1;
3184 break;
3185 default:
3186 abort ();
3187 }
3188 install_operand (s[1], tmpreg);
3189 break;
3190
3191 case '0':
3192 case '1':
3193 case '2':
3194 switch (opP->reg)
3195 {
3196 case TC:
3197 tmpreg = 0;
3198 break;
3199 case CAL:
3200 tmpreg = 4;
3201 break;
3202 case VAL:
3203 tmpreg = 5;
3204 break;
3205 case SCC:
3206 tmpreg = 6;
3207 break;
3208 case AC:
3209 tmpreg = 7;
3210 break;
3211 default:
3212 abort ();
3213 }
3214 install_operand (s[1], tmpreg);
3215 break;
3216
3217 case 'V':
3218 if (opP->reg == VAL)
3219 break;
3220 abort ();
3221
3222 case 'W':
3223 switch (opP->reg)
3224 {
3225 case DRP:
3226 tmpreg = 1;
3227 break;
3228 case SRP:
3229 tmpreg = 2;
3230 break;
3231 case CRP:
3232 tmpreg = 3;
3233 break;
3234 default:
3235 abort ();
3236 }
3237 install_operand (s[1], tmpreg);
3238 break;
3239
3240 case 'X':
3241 switch (opP->reg)
3242 {
3243 case BAD:
3244 case BAD + 1:
3245 case BAD + 2:
3246 case BAD + 3:
3247 case BAD + 4:
3248 case BAD + 5:
3249 case BAD + 6:
3250 case BAD + 7:
3251 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3252 break;
3253
3254 case BAC:
3255 case BAC + 1:
3256 case BAC + 2:
3257 case BAC + 3:
3258 case BAC + 4:
3259 case BAC + 5:
3260 case BAC + 6:
3261 case BAC + 7:
3262 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3263 break;
3264
3265 default:
3266 abort ();
3267 }
3268 install_operand (s[1], tmpreg);
3269 break;
3270 case 'Y':
3271 know (opP->reg == PSR);
3272 break;
3273 case 'Z':
3274 know (opP->reg == PCSR);
3275 break;
3276 #endif /* m68851 */
3277 case '3':
3278 switch (opP->reg)
3279 {
3280 case TT0:
3281 tmpreg = 2;
3282 break;
3283 case TT1:
3284 tmpreg = 3;
3285 break;
3286 default:
3287 abort ();
3288 }
3289 install_operand (s[1], tmpreg);
3290 break;
3291 case 't':
3292 tmpreg = get_num (&opP->disp, 20);
3293 install_operand (s[1], tmpreg);
3294 break;
3295 case '_': /* used only for move16 absolute 32-bit address. */
3296 if (isvar (&opP->disp))
3297 add_fix ('l', &opP->disp, 0, 0);
3298 tmpreg = get_num (&opP->disp, 90);
3299 addword (tmpreg >> 16);
3300 addword (tmpreg & 0xFFFF);
3301 break;
3302 case 'u':
3303 install_operand (s[1], opP->reg - DATA0L);
3304 opP->reg -= (DATA0L);
3305 opP->reg &= 0x0F; /* remove upper/lower bit. */
3306 break;
3307 case 'x':
3308 tmpreg = get_num (&opP->disp, 80);
3309 if (tmpreg == -1)
3310 tmpreg = 0;
3311 install_operand (s[1], tmpreg);
3312 break;
3313 default:
3314 abort ();
3315 }
3316 }
3317
3318 /* By the time whe get here (FINALLY) the_ins contains the complete
3319 instruction, ready to be emitted. . . */
3320 }
3321
3322 static int
3323 reverse_16_bits (int in)
3324 {
3325 int out = 0;
3326 int n;
3327
3328 static int mask[16] =
3329 {
3330 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3331 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3332 };
3333 for (n = 0; n < 16; n++)
3334 {
3335 if (in & mask[n])
3336 out |= mask[15 - n];
3337 }
3338 return out;
3339 } /* reverse_16_bits() */
3340
3341 static int
3342 reverse_8_bits (int in)
3343 {
3344 int out = 0;
3345 int n;
3346
3347 static int mask[8] =
3348 {
3349 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3350 };
3351
3352 for (n = 0; n < 8; n++)
3353 {
3354 if (in & mask[n])
3355 out |= mask[7 - n];
3356 }
3357 return out;
3358 } /* reverse_8_bits() */
3359
3360 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3361 (that value is chosen in the frag_var call in md_assemble). TYPE
3362 is the subtype of the frag to be generated; its primary type is
3363 rs_machine_dependent.
3364
3365 The TYPE parameter is also used by md_convert_frag_1 and
3366 md_estimate_size_before_relax. The appropriate type of fixup will
3367 be emitted by md_convert_frag_1.
3368
3369 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3370 static void
3371 install_operand (int mode, int val)
3372 {
3373 switch (mode)
3374 {
3375 case 's':
3376 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3377 break;
3378 case 'd':
3379 the_ins.opcode[0] |= val << 9;
3380 break;
3381 case '1':
3382 the_ins.opcode[1] |= val << 12;
3383 break;
3384 case '2':
3385 the_ins.opcode[1] |= val << 6;
3386 break;
3387 case '3':
3388 the_ins.opcode[1] |= val;
3389 break;
3390 case '4':
3391 the_ins.opcode[2] |= val << 12;
3392 break;
3393 case '5':
3394 the_ins.opcode[2] |= val << 6;
3395 break;
3396 case '6':
3397 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3398 three words long! */
3399 the_ins.numo++;
3400 the_ins.opcode[2] |= val;
3401 break;
3402 case '7':
3403 the_ins.opcode[1] |= val << 7;
3404 break;
3405 case '8':
3406 the_ins.opcode[1] |= val << 10;
3407 break;
3408 #ifndef NO_68851
3409 case '9':
3410 the_ins.opcode[1] |= val << 5;
3411 break;
3412 #endif
3413
3414 case 't':
3415 the_ins.opcode[1] |= (val << 10) | (val << 7);
3416 break;
3417 case 'D':
3418 the_ins.opcode[1] |= (val << 12) | val;
3419 break;
3420 case 'g':
3421 the_ins.opcode[0] |= val = 0xff;
3422 break;
3423 case 'i':
3424 the_ins.opcode[0] |= val << 9;
3425 break;
3426 case 'C':
3427 the_ins.opcode[1] |= val;
3428 break;
3429 case 'j':
3430 the_ins.opcode[1] |= val;
3431 the_ins.numo++; /* What a hack. */
3432 break;
3433 case 'k':
3434 the_ins.opcode[1] |= val << 4;
3435 break;
3436 case 'b':
3437 case 'w':
3438 case 'W':
3439 case 'l':
3440 break;
3441 case 'e':
3442 the_ins.opcode[0] |= (val << 6);
3443 break;
3444 case 'L':
3445 the_ins.opcode[1] = (val >> 16);
3446 the_ins.opcode[2] = val & 0xffff;
3447 break;
3448 case 'm':
3449 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3450 the_ins.opcode[0] |= ((val & 0x7) << 9);
3451 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3452 break;
3453 case 'n': /* MAC/EMAC Rx on !load. */
3454 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3455 the_ins.opcode[0] |= ((val & 0x7) << 9);
3456 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3457 break;
3458 case 'o': /* MAC/EMAC Rx on load. */
3459 the_ins.opcode[1] |= val << 12;
3460 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3461 break;
3462 case 'M': /* MAC/EMAC Ry on !load. */
3463 the_ins.opcode[0] |= (val & 0xF);
3464 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3465 break;
3466 case 'N': /* MAC/EMAC Ry on load. */
3467 the_ins.opcode[1] |= (val & 0xF);
3468 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3469 break;
3470 case 'h':
3471 the_ins.opcode[1] |= ((val != 1) << 10);
3472 break;
3473 case 'F':
3474 the_ins.opcode[0] |= ((val & 0x3) << 9);
3475 break;
3476 case 'f':
3477 the_ins.opcode[0] |= ((val & 0x3) << 0);
3478 break;
3479 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3480 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3481 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3482 break;
3483 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3484 the_ins.opcode[0] |= ((val & 0x1) << 7);
3485 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3486 break;
3487 case 'I':
3488 the_ins.opcode[1] |= ((val & 0x3) << 9);
3489 break;
3490 case ']':
3491 the_ins.opcode[0] |= (val & 0x1) <<10;
3492 break;
3493 case 'c':
3494 default:
3495 as_fatal (_("failed sanity check."));
3496 }
3497 }
3498
3499 static void
3500 install_gen_operand (int mode, int val)
3501 {
3502 switch (mode)
3503 {
3504 case '/': /* Special for mask loads for mac/msac insns with
3505 possible mask; trailing_ampersend set in bit 8. */
3506 the_ins.opcode[0] |= (val & 0x3f);
3507 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3508 break;
3509 case 's':
3510 the_ins.opcode[0] |= val;
3511 break;
3512 case 'd':
3513 /* This is a kludge!!! */
3514 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3515 break;
3516 case 'b':
3517 case 'w':
3518 case 'l':
3519 case 'f':
3520 case 'F':
3521 case 'x':
3522 case 'p':
3523 the_ins.opcode[0] |= val;
3524 break;
3525 /* more stuff goes here. */
3526 default:
3527 as_fatal (_("failed sanity check."));
3528 }
3529 }
3530
3531 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3532 then deal with the bitfield hack. */
3533
3534 static char *
3535 crack_operand (char *str, struct m68k_op *opP)
3536 {
3537 register int parens;
3538 register int c;
3539 register char *beg_str;
3540 int inquote = 0;
3541
3542 if (!str)
3543 {
3544 return str;
3545 }
3546 beg_str = str;
3547 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3548 {
3549 if (! inquote)
3550 {
3551 if (*str == '(')
3552 parens++;
3553 else if (*str == ')')
3554 {
3555 if (!parens)
3556 { /* ERROR. */
3557 opP->error = _("Extra )");
3558 return str;
3559 }
3560 --parens;
3561 }
3562 }
3563 if (flag_mri && *str == '\'')
3564 inquote = ! inquote;
3565 }
3566 if (!*str && parens)
3567 { /* ERROR. */
3568 opP->error = _("Missing )");
3569 return str;
3570 }
3571 c = *str;
3572 *str = '\0';
3573 if (m68k_ip_op (beg_str, opP) != 0)
3574 {
3575 *str = c;
3576 return str;
3577 }
3578 *str = c;
3579 if (c == '}')
3580 c = *++str; /* JF bitfield hack. */
3581 if (c)
3582 {
3583 c = *++str;
3584 if (!c)
3585 as_bad (_("Missing operand"));
3586 }
3587
3588 /* Detect MRI REG symbols and convert them to REGLSTs. */
3589 if (opP->mode == CONTROL && (int)opP->reg < 0)
3590 {
3591 opP->mode = REGLST;
3592 opP->mask = ~(int)opP->reg;
3593 opP->reg = 0;
3594 }
3595
3596 return str;
3597 }
3598
3599 /* This is the guts of the machine-dependent assembler. STR points to a
3600 machine dependent instruction. This function is supposed to emit
3601 the frags/bytes it assembles to.
3602 */
3603
3604 static void
3605 insert_reg (const char *regname, int regnum)
3606 {
3607 char buf[100];
3608 int i;
3609
3610 #ifdef REGISTER_PREFIX
3611 if (!flag_reg_prefix_optional)
3612 {
3613 buf[0] = REGISTER_PREFIX;
3614 strcpy (buf + 1, regname);
3615 regname = buf;
3616 }
3617 #endif
3618
3619 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3620 &zero_address_frag));
3621
3622 for (i = 0; regname[i]; i++)
3623 buf[i] = TOUPPER (regname[i]);
3624 buf[i] = '\0';
3625
3626 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3627 &zero_address_frag));
3628 }
3629
3630 struct init_entry
3631 {
3632 const char *name;
3633 int number;
3634 };
3635
3636 static const struct init_entry init_table[] =
3637 {
3638 { "d0", DATA0 },
3639 { "d1", DATA1 },
3640 { "d2", DATA2 },
3641 { "d3", DATA3 },
3642 { "d4", DATA4 },
3643 { "d5", DATA5 },
3644 { "d6", DATA6 },
3645 { "d7", DATA7 },
3646 { "a0", ADDR0 },
3647 { "a1", ADDR1 },
3648 { "a2", ADDR2 },
3649 { "a3", ADDR3 },
3650 { "a4", ADDR4 },
3651 { "a5", ADDR5 },
3652 { "a6", ADDR6 },
3653 { "fp", ADDR6 },
3654 { "a7", ADDR7 },
3655 { "sp", ADDR7 },
3656 { "ssp", ADDR7 },
3657 { "fp0", FP0 },
3658 { "fp1", FP1 },
3659 { "fp2", FP2 },
3660 { "fp3", FP3 },
3661 { "fp4", FP4 },
3662 { "fp5", FP5 },
3663 { "fp6", FP6 },
3664 { "fp7", FP7 },
3665 { "fpi", FPI },
3666 { "fpiar", FPI },
3667 { "fpc", FPI },
3668 { "fps", FPS },
3669 { "fpsr", FPS },
3670 { "fpc", FPC },
3671 { "fpcr", FPC },
3672 { "control", FPC },
3673 { "status", FPS },
3674 { "iaddr", FPI },
3675
3676 { "cop0", COP0 },
3677 { "cop1", COP1 },
3678 { "cop2", COP2 },
3679 { "cop3", COP3 },
3680 { "cop4", COP4 },
3681 { "cop5", COP5 },
3682 { "cop6", COP6 },
3683 { "cop7", COP7 },
3684 { "pc", PC },
3685 { "zpc", ZPC },
3686 { "sr", SR },
3687
3688 { "ccr", CCR },
3689 { "cc", CCR },
3690
3691 { "acc", ACC },
3692 { "acc0", ACC },
3693 { "acc1", ACC1 },
3694 { "acc2", ACC2 },
3695 { "acc3", ACC3 },
3696 { "accext01", ACCEXT01 },
3697 { "accext23", ACCEXT23 },
3698 { "macsr", MACSR },
3699 { "mask", MASK },
3700
3701 /* Control registers. */
3702 { "sfc", SFC }, /* Source Function Code. */
3703 { "sfcr", SFC },
3704 { "dfc", DFC }, /* Destination Function Code. */
3705 { "dfcr", DFC },
3706 { "cacr", CACR }, /* Cache Control Register. */
3707 { "caar", CAAR }, /* Cache Address Register. */
3708
3709 { "usp", USP }, /* User Stack Pointer. */
3710 { "vbr", VBR }, /* Vector Base Register. */
3711 { "msp", MSP }, /* Master Stack Pointer. */
3712 { "isp", ISP }, /* Interrupt Stack Pointer. */
3713
3714 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3715 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3716 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3717 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
3718
3719 /* 68ec040 versions of same */
3720 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3721 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3722 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3723 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
3724
3725 /* mcf5200 versions of same. The ColdFire programmer's reference
3726 manual indicated that the order is 2,3,0,1, but Ken Rose
3727 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3728 { "acr0", ACR0 }, /* Access Control Unit 0. */
3729 { "acr1", ACR1 }, /* Access Control Unit 1. */
3730 { "acr2", ACR2 }, /* Access Control Unit 2. */
3731 { "acr3", ACR3 }, /* Access Control Unit 3. */
3732
3733 { "tc", TC }, /* MMU Translation Control Register. */
3734 { "tcr", TC },
3735
3736 { "mmusr", MMUSR }, /* MMU Status Register. */
3737 { "srp", SRP }, /* User Root Pointer. */
3738 { "urp", URP }, /* Supervisor Root Pointer. */
3739
3740 { "buscr", BUSCR },
3741 { "pcr", PCR },
3742
3743 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3744 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3745 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3746 { "mbar", MBAR }, /* Module Base Address Register. */
3747
3748 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3749 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3750 { "rombar0", ROMBAR }, /* mcfv4e registers. */
3751 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3752 { "mpcr", MPCR }, /* mcfv4e registers. */
3753 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3754 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3755 { "asid", TC }, /* mcfv4e registers. */
3756 { "mmubar", BUSCR }, /* mcfv4e registers. */
3757 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3758 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3759 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3760 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3761 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3762 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3763 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3764 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3765 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3766 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3767 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3768 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3769
3770 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3771 { "rambar", RAMBAR }, /* mcf528x registers. */
3772
3773 { "mbar2", MBAR2 }, /* mcf5249 registers. */
3774 /* End of control registers. */
3775
3776 { "ac", AC },
3777 { "bc", BC },
3778 { "cal", CAL },
3779 { "crp", CRP },
3780 { "drp", DRP },
3781 { "pcsr", PCSR },
3782 { "psr", PSR },
3783 { "scc", SCC },
3784 { "val", VAL },
3785 { "bad0", BAD0 },
3786 { "bad1", BAD1 },
3787 { "bad2", BAD2 },
3788 { "bad3", BAD3 },
3789 { "bad4", BAD4 },
3790 { "bad5", BAD5 },
3791 { "bad6", BAD6 },
3792 { "bad7", BAD7 },
3793 { "bac0", BAC0 },
3794 { "bac1", BAC1 },
3795 { "bac2", BAC2 },
3796 { "bac3", BAC3 },
3797 { "bac4", BAC4 },
3798 { "bac5", BAC5 },
3799 { "bac6", BAC6 },
3800 { "bac7", BAC7 },
3801
3802 { "ic", IC },
3803 { "dc", DC },
3804 { "nc", NC },
3805
3806 { "tt0", TT0 },
3807 { "tt1", TT1 },
3808 /* 68ec030 versions of same. */
3809 { "ac0", TT0 },
3810 { "ac1", TT1 },
3811 /* 68ec030 access control unit, identical to 030 MMU status reg. */
3812 { "acusr", PSR },
3813
3814 /* Suppressed data and address registers. */
3815 { "zd0", ZDATA0 },
3816 { "zd1", ZDATA1 },
3817 { "zd2", ZDATA2 },
3818 { "zd3", ZDATA3 },
3819 { "zd4", ZDATA4 },
3820 { "zd5", ZDATA5 },
3821 { "zd6", ZDATA6 },
3822 { "zd7", ZDATA7 },
3823 { "za0", ZADDR0 },
3824 { "za1", ZADDR1 },
3825 { "za2", ZADDR2 },
3826 { "za3", ZADDR3 },
3827 { "za4", ZADDR4 },
3828 { "za5", ZADDR5 },
3829 { "za6", ZADDR6 },
3830 { "za7", ZADDR7 },
3831
3832 /* Upper and lower data and address registers, used by macw and msacw. */
3833 { "d0l", DATA0L },
3834 { "d1l", DATA1L },
3835 { "d2l", DATA2L },
3836 { "d3l", DATA3L },
3837 { "d4l", DATA4L },
3838 { "d5l", DATA5L },
3839 { "d6l", DATA6L },
3840 { "d7l", DATA7L },
3841
3842 { "a0l", ADDR0L },
3843 { "a1l", ADDR1L },
3844 { "a2l", ADDR2L },
3845 { "a3l", ADDR3L },
3846 { "a4l", ADDR4L },
3847 { "a5l", ADDR5L },
3848 { "a6l", ADDR6L },
3849 { "a7l", ADDR7L },
3850
3851 { "d0u", DATA0U },
3852 { "d1u", DATA1U },
3853 { "d2u", DATA2U },
3854 { "d3u", DATA3U },
3855 { "d4u", DATA4U },
3856 { "d5u", DATA5U },
3857 { "d6u", DATA6U },
3858 { "d7u", DATA7U },
3859
3860 { "a0u", ADDR0U },
3861 { "a1u", ADDR1U },
3862 { "a2u", ADDR2U },
3863 { "a3u", ADDR3U },
3864 { "a4u", ADDR4U },
3865 { "a5u", ADDR5U },
3866 { "a6u", ADDR6U },
3867 { "a7u", ADDR7U },
3868
3869 { 0, 0 }
3870 };
3871
3872 static void
3873 init_regtable (void)
3874 {
3875 int i;
3876 for (i = 0; init_table[i].name; i++)
3877 insert_reg (init_table[i].name, init_table[i].number);
3878 }
3879
3880 static int no_68851, no_68881;
3881
3882 #ifdef OBJ_AOUT
3883 /* a.out machine type. Default to 68020. */
3884 int m68k_aout_machtype = 2;
3885 #endif
3886
3887 void
3888 md_assemble (char *str)
3889 {
3890 const char *er;
3891 short *fromP;
3892 char *toP = NULL;
3893 int m, n = 0;
3894 char *to_beg_P;
3895 int shorts_this_frag;
3896 fixS *fixP;
3897
3898 /* In MRI mode, the instruction and operands are separated by a
3899 space. Anything following the operands is a comment. The label
3900 has already been removed. */
3901 if (flag_mri)
3902 {
3903 char *s;
3904 int fields = 0;
3905 int infield = 0;
3906 int inquote = 0;
3907
3908 for (s = str; *s != '\0'; s++)
3909 {
3910 if ((*s == ' ' || *s == '\t') && ! inquote)
3911 {
3912 if (infield)
3913 {
3914 ++fields;
3915 if (fields >= 2)
3916 {
3917 *s = '\0';
3918 break;
3919 }
3920 infield = 0;
3921 }
3922 }
3923 else
3924 {
3925 if (! infield)
3926 infield = 1;
3927 if (*s == '\'')
3928 inquote = ! inquote;
3929 }
3930 }
3931 }
3932
3933 memset (&the_ins, '\0', sizeof (the_ins));
3934 m68k_ip (str);
3935 er = the_ins.error;
3936 if (!er)
3937 {
3938 for (n = 0; n < the_ins.numargs; n++)
3939 if (the_ins.operands[n].error)
3940 {
3941 er = the_ins.operands[n].error;
3942 break;
3943 }
3944 }
3945 if (er)
3946 {
3947 as_bad (_("%s -- statement `%s' ignored"), er, str);
3948 return;
3949 }
3950
3951 /* If there is a current label, record that it marks an instruction. */
3952 if (current_label != NULL)
3953 {
3954 current_label->text = 1;
3955 current_label = NULL;
3956 }
3957
3958 #ifdef OBJ_ELF
3959 /* Tie dwarf2 debug info to the address at the start of the insn. */
3960 dwarf2_emit_insn (0);
3961 #endif
3962
3963 if (the_ins.nfrag == 0)
3964 {
3965 /* No frag hacking involved; just put it out. */
3966 toP = frag_more (2 * the_ins.numo);
3967 fromP = &the_ins.opcode[0];
3968 for (m = the_ins.numo; m; --m)
3969 {
3970 md_number_to_chars (toP, (long) (*fromP), 2);
3971 toP += 2;
3972 fromP++;
3973 }
3974 /* Put out symbol-dependent info. */
3975 for (m = 0; m < the_ins.nrel; m++)
3976 {
3977 switch (the_ins.reloc[m].wid)
3978 {
3979 case 'B':
3980 n = 1;
3981 break;
3982 case 'b':
3983 n = 1;
3984 break;
3985 case '3':
3986 n = 1;
3987 break;
3988 case 'w':
3989 case 'W':
3990 n = 2;
3991 break;
3992 case 'l':
3993 n = 4;
3994 break;
3995 default:
3996 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3997 the_ins.reloc[m].wid);
3998 }
3999
4000 fixP = fix_new_exp (frag_now,
4001 ((toP - frag_now->fr_literal)
4002 - the_ins.numo * 2 + the_ins.reloc[m].n),
4003 n,
4004 &the_ins.reloc[m].exp,
4005 the_ins.reloc[m].pcrel,
4006 get_reloc_code (n, the_ins.reloc[m].pcrel,
4007 the_ins.reloc[m].pic_reloc));
4008 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4009 if (the_ins.reloc[m].wid == 'B')
4010 fixP->fx_signed = 1;
4011 }
4012 return;
4013 }
4014
4015 /* There's some frag hacking. */
4016 {
4017 /* Calculate the max frag size. */
4018 int wid;
4019
4020 wid = 2 * the_ins.fragb[0].fragoff;
4021 for (n = 1; n < the_ins.nfrag; n++)
4022 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4023 /* frag_var part. */
4024 wid += 10;
4025 /* Make sure the whole insn fits in one chunk, in particular that
4026 the var part is attached, as we access one byte before the
4027 variable frag for byte branches. */
4028 frag_grow (wid);
4029 }
4030
4031 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4032 {
4033 int wid;
4034
4035 if (n == 0)
4036 wid = 2 * the_ins.fragb[n].fragoff;
4037 else
4038 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4039 toP = frag_more (wid);
4040 to_beg_P = toP;
4041 shorts_this_frag = 0;
4042 for (m = wid / 2; m; --m)
4043 {
4044 md_number_to_chars (toP, (long) (*fromP), 2);
4045 toP += 2;
4046 fromP++;
4047 shorts_this_frag++;
4048 }
4049 for (m = 0; m < the_ins.nrel; m++)
4050 {
4051 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4052 {
4053 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4054 break;
4055 }
4056 wid = the_ins.reloc[m].wid;
4057 if (wid == 0)
4058 continue;
4059 the_ins.reloc[m].wid = 0;
4060 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4061
4062 fixP = fix_new_exp (frag_now,
4063 ((toP - frag_now->fr_literal)
4064 - the_ins.numo * 2 + the_ins.reloc[m].n),
4065 wid,
4066 &the_ins.reloc[m].exp,
4067 the_ins.reloc[m].pcrel,
4068 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4069 the_ins.reloc[m].pic_reloc));
4070 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4071 }
4072 (void) frag_var (rs_machine_dependent, 10, 0,
4073 (relax_substateT) (the_ins.fragb[n].fragty),
4074 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4075 }
4076 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4077 shorts_this_frag = 0;
4078 if (n)
4079 {
4080 toP = frag_more (n * 2);
4081 while (n--)
4082 {
4083 md_number_to_chars (toP, (long) (*fromP), 2);
4084 toP += 2;
4085 fromP++;
4086 shorts_this_frag++;
4087 }
4088 }
4089 for (m = 0; m < the_ins.nrel; m++)
4090 {
4091 int wid;
4092
4093 wid = the_ins.reloc[m].wid;
4094 if (wid == 0)
4095 continue;
4096 the_ins.reloc[m].wid = 0;
4097 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4098
4099 fixP = fix_new_exp (frag_now,
4100 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4101 - shorts_this_frag * 2),
4102 wid,
4103 &the_ins.reloc[m].exp,
4104 the_ins.reloc[m].pcrel,
4105 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4106 the_ins.reloc[m].pic_reloc));
4107 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4108 }
4109 }
4110
4111 /* Comparison function used by qsort to rank the opcode entries by name. */
4112
4113 static int
4114 m68k_compare_opcode (const void * v1, const void * v2)
4115 {
4116 struct m68k_opcode * op1, * op2;
4117 int ret;
4118
4119 op1 = *(struct m68k_opcode **) v1;
4120 op2 = *(struct m68k_opcode **) v2;
4121
4122 /* Compare the two names. If different, return the comparison.
4123 If the same, return the order they are in the opcode table. */
4124 ret = strcmp (op1->name, op2->name);
4125 if (ret)
4126 return ret;
4127 if (op1 < op2)
4128 return -1;
4129 return 0;
4130 }
4131
4132 void
4133 md_begin (void)
4134 {
4135 const struct m68k_opcode *ins;
4136 struct m68k_incant *hack, *slak;
4137 const char *retval = 0; /* Empty string, or error msg text. */
4138 int i;
4139
4140 /* Set up hash tables with 68000 instructions.
4141 similar to what the vax assembler does. */
4142 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4143 a copy of it at runtime, adding in the information we want but isn't
4144 there. I think it'd be better to have an awk script hack the table
4145 at compile time. Or even just xstr the table and use it as-is. But
4146 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4147 names. */
4148
4149 if (flag_mri)
4150 {
4151 flag_reg_prefix_optional = 1;
4152 m68k_abspcadd = 1;
4153 if (! m68k_rel32_from_cmdline)
4154 m68k_rel32 = 0;
4155 }
4156
4157 /* First sort the opcode table into alphabetical order to seperate
4158 the order that the assembler wants to see the opcodes from the
4159 order that the disassembler wants to see them. */
4160 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4161 if (!m68k_sorted_opcodes)
4162 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4163 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
4164
4165 for (i = m68k_numopcodes; i--;)
4166 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4167
4168 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4169 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4170
4171 op_hash = hash_new ();
4172
4173 obstack_begin (&robyn, 4000);
4174 for (i = 0; i < m68k_numopcodes; i++)
4175 {
4176 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4177 do
4178 {
4179 ins = m68k_sorted_opcodes[i];
4180
4181 /* We *could* ignore insns that don't match our
4182 arch here by just leaving them out of the hash. */
4183 slak->m_operands = ins->args;
4184 slak->m_opnum = strlen (slak->m_operands) / 2;
4185 slak->m_arch = ins->arch;
4186 slak->m_opcode = ins->opcode;
4187 /* This is kludgey. */
4188 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4189 if (i + 1 != m68k_numopcodes
4190 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4191 {
4192 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4193 i++;
4194 }
4195 else
4196 slak->m_next = 0;
4197 slak = slak->m_next;
4198 }
4199 while (slak);
4200
4201 retval = hash_insert (op_hash, ins->name, (char *) hack);
4202 if (retval)
4203 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4204 }
4205
4206 for (i = 0; i < m68k_numaliases; i++)
4207 {
4208 const char *name = m68k_opcode_aliases[i].primary;
4209 const char *alias = m68k_opcode_aliases[i].alias;
4210 PTR val = hash_find (op_hash, name);
4211
4212 if (!val)
4213 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4214 retval = hash_insert (op_hash, alias, val);
4215 if (retval)
4216 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4217 }
4218
4219 /* In MRI mode, all unsized branches are variable sized. Normally,
4220 they are word sized. */
4221 if (flag_mri)
4222 {
4223 static struct m68k_opcode_alias mri_aliases[] =
4224 {
4225 { "bhi", "jhi", },
4226 { "bls", "jls", },
4227 { "bcc", "jcc", },
4228 { "bcs", "jcs", },
4229 { "bne", "jne", },
4230 { "beq", "jeq", },
4231 { "bvc", "jvc", },
4232 { "bvs", "jvs", },
4233 { "bpl", "jpl", },
4234 { "bmi", "jmi", },
4235 { "bge", "jge", },
4236 { "blt", "jlt", },
4237 { "bgt", "jgt", },
4238 { "ble", "jle", },
4239 { "bra", "jra", },
4240 { "bsr", "jbsr", },
4241 };
4242
4243 for (i = 0;
4244 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4245 i++)
4246 {
4247 const char *name = mri_aliases[i].primary;
4248 const char *alias = mri_aliases[i].alias;
4249 PTR val = hash_find (op_hash, name);
4250
4251 if (!val)
4252 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4253 retval = hash_jam (op_hash, alias, val);
4254 if (retval)
4255 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4256 }
4257 }
4258
4259 for (i = 0; i < (int) sizeof (notend_table); i++)
4260 {
4261 notend_table[i] = 0;
4262 alt_notend_table[i] = 0;
4263 }
4264
4265 notend_table[','] = 1;
4266 notend_table['{'] = 1;
4267 notend_table['}'] = 1;
4268 alt_notend_table['a'] = 1;
4269 alt_notend_table['A'] = 1;
4270 alt_notend_table['d'] = 1;
4271 alt_notend_table['D'] = 1;
4272 alt_notend_table['#'] = 1;
4273 alt_notend_table['&'] = 1;
4274 alt_notend_table['f'] = 1;
4275 alt_notend_table['F'] = 1;
4276 #ifdef REGISTER_PREFIX
4277 alt_notend_table[REGISTER_PREFIX] = 1;
4278 #endif
4279
4280 /* We need to put '(' in alt_notend_table to handle
4281 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4282 alt_notend_table['('] = 1;
4283
4284 /* We need to put '@' in alt_notend_table to handle
4285 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4286 alt_notend_table['@'] = 1;
4287
4288 /* We need to put digits in alt_notend_table to handle
4289 bfextu %d0{24:1},%d0 */
4290 alt_notend_table['0'] = 1;
4291 alt_notend_table['1'] = 1;
4292 alt_notend_table['2'] = 1;
4293 alt_notend_table['3'] = 1;
4294 alt_notend_table['4'] = 1;
4295 alt_notend_table['5'] = 1;
4296 alt_notend_table['6'] = 1;
4297 alt_notend_table['7'] = 1;
4298 alt_notend_table['8'] = 1;
4299 alt_notend_table['9'] = 1;
4300
4301 #ifndef MIT_SYNTAX_ONLY
4302 /* Insert pseudo ops, these have to go into the opcode table since
4303 gas expects pseudo ops to start with a dot. */
4304 {
4305 int n = 0;
4306
4307 while (mote_pseudo_table[n].poc_name)
4308 {
4309 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4310 hash_insert (op_hash,
4311 mote_pseudo_table[n].poc_name, (char *) hack);
4312 hack->m_operands = 0;
4313 hack->m_opnum = n;
4314 n++;
4315 }
4316 }
4317 #endif
4318
4319 init_regtable ();
4320
4321 #ifdef OBJ_ELF
4322 record_alignment (text_section, 2);
4323 record_alignment (data_section, 2);
4324 record_alignment (bss_section, 2);
4325 #endif
4326 }
4327
4328 static void
4329 select_control_regs (void)
4330 {
4331 /* Note which set of "movec" control registers is available. */
4332 switch (current_chip)
4333 {
4334 case 0:
4335 if (verbose)
4336 as_warn (_("architecture not yet selected: defaulting to 68020"));
4337 control_regs = m68020_control_regs;
4338 break;
4339
4340 case m68000:
4341 control_regs = m68000_control_regs;
4342 break;
4343 case m68010:
4344 control_regs = m68010_control_regs;
4345 break;
4346 case m68020:
4347 case m68030:
4348 control_regs = m68020_control_regs;
4349 break;
4350 case m68040:
4351 control_regs = m68040_control_regs;
4352 break;
4353 case m68060:
4354 control_regs = m68060_control_regs;
4355 break;
4356 case cpu32:
4357 control_regs = cpu32_control_regs;
4358 break;
4359 case mcf5200:
4360 case mcf5206e:
4361 case mcf5307:
4362 case mcf5407:
4363 control_regs = mcf_control_regs;
4364 break;
4365 case mcf5249:
4366 control_regs = mcf5249_control_regs;
4367 break;
4368 case mcf528x:
4369 case mcf521x:
4370 control_regs = mcf528x_control_regs;
4371 break;
4372 case mcf5470:
4373 case mcf5480:
4374 control_regs = mcfv4e_control_regs;
4375 break;
4376 default:
4377 abort ();
4378 }
4379 }
4380
4381 void
4382 m68k_init_after_args (void)
4383 {
4384 if (cpu_of_arch (current_architecture) == 0)
4385 {
4386 int i;
4387 const char *default_cpu = TARGET_CPU;
4388
4389 if (*default_cpu == 'm')
4390 default_cpu++;
4391 for (i = 0; i < n_archs; i++)
4392 if (strcasecmp (default_cpu, archs[i].name) == 0)
4393 break;
4394 if (i == n_archs)
4395 {
4396 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
4397 current_architecture |= m68020;
4398 }
4399 else
4400 current_architecture |= archs[i].arch;
4401 }
4402 /* Permit m68881 specification with all cpus; those that can't work
4403 with a coprocessor could be doing emulation. */
4404 if (current_architecture & m68851)
4405 {
4406 if (current_architecture & m68040)
4407 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
4408 }
4409 /* What other incompatibilities could we check for? */
4410
4411 /* Toss in some default assumptions about coprocessors. */
4412 if (!no_68881
4413 && (cpu_of_arch (current_architecture)
4414 /* Can CPU32 have a 68881 coprocessor?? */
4415 & (m68020 | m68030 | cpu32)))
4416 current_architecture |= m68881;
4417
4418 if (!no_68851
4419 && (cpu_of_arch (current_architecture) & m68020up) != 0
4420 && (cpu_of_arch (current_architecture) & m68040up) == 0)
4421 current_architecture |= m68851;
4422
4423 if (no_68881 && (current_architecture & m68881))
4424 as_bad (_("options for 68881 and no-68881 both given"));
4425
4426 if (no_68851 && (current_architecture & m68851))
4427 as_bad (_("options for 68851 and no-68851 both given"));
4428
4429 #ifdef OBJ_AOUT
4430 /* Work out the magic number. This isn't very general. */
4431 if (current_architecture & m68000)
4432 m68k_aout_machtype = 0;
4433 else if (current_architecture & m68010)
4434 m68k_aout_machtype = 1;
4435 else if (current_architecture & m68020)
4436 m68k_aout_machtype = 2;
4437 else
4438 m68k_aout_machtype = 2;
4439 #endif
4440
4441 /* Note which set of "movec" control registers is available. */
4442 select_control_regs ();
4443
4444 if (cpu_of_arch (current_architecture) < m68020
4445 || arch_coldfire_p (current_architecture))
4446 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4447 }
4448 \f
4449 /* This is called when a label is defined. */
4450
4451 void
4452 m68k_frob_label (symbolS *sym)
4453 {
4454 struct label_line *n;
4455
4456 n = (struct label_line *) xmalloc (sizeof *n);
4457 n->next = labels;
4458 n->label = sym;
4459 as_where (&n->file, &n->line);
4460 n->text = 0;
4461 labels = n;
4462 current_label = n;
4463 }
4464
4465 /* This is called when a value that is not an instruction is emitted. */
4466
4467 void
4468 m68k_flush_pending_output (void)
4469 {
4470 current_label = NULL;
4471 }
4472
4473 /* This is called at the end of the assembly, when the final value of
4474 the label is known. We warn if this is a text symbol aligned at an
4475 odd location. */
4476
4477 void
4478 m68k_frob_symbol (symbolS *sym)
4479 {
4480 if (S_GET_SEGMENT (sym) == reg_section
4481 && (int) S_GET_VALUE (sym) < 0)
4482 {
4483 S_SET_SEGMENT (sym, absolute_section);
4484 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4485 }
4486 else if ((S_GET_VALUE (sym) & 1) != 0)
4487 {
4488 struct label_line *l;
4489
4490 for (l = labels; l != NULL; l = l->next)
4491 {
4492 if (l->label == sym)
4493 {
4494 if (l->text)
4495 as_warn_where (l->file, l->line,
4496 _("text label `%s' aligned to odd boundary"),
4497 S_GET_NAME (sym));
4498 break;
4499 }
4500 }
4501 }
4502 }
4503 \f
4504 /* This is called if we go in or out of MRI mode because of the .mri
4505 pseudo-op. */
4506
4507 void
4508 m68k_mri_mode_change (int on)
4509 {
4510 if (on)
4511 {
4512 if (! flag_reg_prefix_optional)
4513 {
4514 flag_reg_prefix_optional = 1;
4515 #ifdef REGISTER_PREFIX
4516 init_regtable ();
4517 #endif
4518 }
4519 m68k_abspcadd = 1;
4520 if (! m68k_rel32_from_cmdline)
4521 m68k_rel32 = 0;
4522 }
4523 else
4524 {
4525 if (! reg_prefix_optional_seen)
4526 {
4527 #ifdef REGISTER_PREFIX_OPTIONAL
4528 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4529 #else
4530 flag_reg_prefix_optional = 0;
4531 #endif
4532 #ifdef REGISTER_PREFIX
4533 init_regtable ();
4534 #endif
4535 }
4536 m68k_abspcadd = 0;
4537 if (! m68k_rel32_from_cmdline)
4538 m68k_rel32 = 1;
4539 }
4540 }
4541
4542 /* Equal to MAX_PRECISION in atof-ieee.c. */
4543 #define MAX_LITTLENUMS 6
4544
4545 /* Turn a string in input_line_pointer into a floating point constant
4546 of type TYPE, and store the appropriate bytes in *LITP. The number
4547 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4548 returned, or NULL on OK. */
4549
4550 char *
4551 md_atof (int type, char *litP, int *sizeP)
4552 {
4553 int prec;
4554 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4555 LITTLENUM_TYPE *wordP;
4556 char *t;
4557
4558 switch (type)
4559 {
4560 case 'f':
4561 case 'F':
4562 case 's':
4563 case 'S':
4564 prec = 2;
4565 break;
4566
4567 case 'd':
4568 case 'D':
4569 case 'r':
4570 case 'R':
4571 prec = 4;
4572 break;
4573
4574 case 'x':
4575 case 'X':
4576 prec = 6;
4577 break;
4578
4579 case 'p':
4580 case 'P':
4581 prec = 6;
4582 break;
4583
4584 default:
4585 *sizeP = 0;
4586 return _("Bad call to MD_ATOF()");
4587 }
4588 t = atof_ieee (input_line_pointer, type, words);
4589 if (t)
4590 input_line_pointer = t;
4591
4592 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4593 for (wordP = words; prec--;)
4594 {
4595 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4596 litP += sizeof (LITTLENUM_TYPE);
4597 }
4598 return 0;
4599 }
4600
4601 void
4602 md_number_to_chars (char *buf, valueT val, int n)
4603 {
4604 number_to_chars_bigendian (buf, val, n);
4605 }
4606
4607 void
4608 md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4609 {
4610 offsetT val = *valP;
4611 addressT upper_limit;
4612 offsetT lower_limit;
4613
4614 /* This is unnecessary but it convinces the native rs6000 compiler
4615 to generate the code we want. */
4616 char *buf = fixP->fx_frag->fr_literal;
4617 buf += fixP->fx_where;
4618 /* End ibm compiler workaround. */
4619
4620 val = SEXT (val);
4621
4622 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4623 fixP->fx_done = 1;
4624
4625 #ifdef OBJ_ELF
4626 if (fixP->fx_addsy)
4627 {
4628 memset (buf, 0, fixP->fx_size);
4629 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4630
4631 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4632 && !S_IS_DEFINED (fixP->fx_addsy)
4633 && !S_IS_WEAK (fixP->fx_addsy))
4634 S_SET_WEAK (fixP->fx_addsy);
4635 return;
4636 }
4637 #endif
4638
4639 #ifdef BFD_ASSEMBLER
4640 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4641 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4642 return;
4643 #endif
4644
4645 switch (fixP->fx_size)
4646 {
4647 /* The cast to offsetT below are necessary to make code
4648 correct for machines where ints are smaller than offsetT. */
4649 case 1:
4650 *buf++ = val;
4651 upper_limit = 0x7f;
4652 lower_limit = - (offsetT) 0x80;
4653 break;
4654 case 2:
4655 *buf++ = (val >> 8);
4656 *buf++ = val;
4657 upper_limit = 0x7fff;
4658 lower_limit = - (offsetT) 0x8000;
4659 break;
4660 case 4:
4661 *buf++ = (val >> 24);
4662 *buf++ = (val >> 16);
4663 *buf++ = (val >> 8);
4664 *buf++ = val;
4665 upper_limit = 0x7fffffff;
4666 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4667 break;
4668 default:
4669 BAD_CASE (fixP->fx_size);
4670 }
4671
4672 /* Fix up a negative reloc. */
4673 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4674 {
4675 fixP->fx_addsy = fixP->fx_subsy;
4676 fixP->fx_subsy = NULL;
4677 fixP->fx_tcbit = 1;
4678 }
4679
4680 /* For non-pc-relative values, it's conceivable we might get something
4681 like "0xff" for a byte field. So extend the upper part of the range
4682 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4683 so that we can do any range checking at all. */
4684 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4685 upper_limit = upper_limit * 2 + 1;
4686
4687 if ((addressT) val > upper_limit
4688 && (val > 0 || val < lower_limit))
4689 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4690
4691 /* A one byte PC-relative reloc means a short branch. We can't use
4692 a short branch with a value of 0 or -1, because those indicate
4693 different opcodes (branches with longer offsets). fixup_segment
4694 in write.c may have clobbered fx_pcrel, so we need to examine the
4695 reloc type. */
4696 if ((fixP->fx_pcrel
4697 #ifdef BFD_ASSEMBLER
4698 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4699 #endif
4700 )
4701 && fixP->fx_size == 1
4702 && (fixP->fx_addsy == NULL
4703 || S_IS_DEFINED (fixP->fx_addsy))
4704 && (val == 0 || val == -1))
4705 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4706 }
4707
4708 /* *fragP has been relaxed to its final size, and now needs to have
4709 the bytes inside it modified to conform to the new size There is UGLY
4710 MAGIC here. ..
4711 */
4712 static void
4713 md_convert_frag_1 (fragS *fragP)
4714 {
4715 long disp;
4716 fixS *fixP;
4717
4718 /* Address in object code of the displacement. */
4719 register int object_address = fragP->fr_fix + fragP->fr_address;
4720
4721 /* Address in gas core of the place to store the displacement. */
4722 /* This convinces the native rs6000 compiler to generate the code we
4723 want. */
4724 register char *buffer_address = fragP->fr_literal;
4725 buffer_address += fragP->fr_fix;
4726 /* End ibm compiler workaround. */
4727
4728 /* The displacement of the address, from current location. */
4729 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4730 disp = (disp + fragP->fr_offset) - object_address;
4731
4732 switch (fragP->fr_subtype)
4733 {
4734 case TAB (BRANCHBWL, BYTE):
4735 case TAB (BRABSJUNC, BYTE):
4736 case TAB (BRABSJCOND, BYTE):
4737 case TAB (BRANCHBW, BYTE):
4738 know (issbyte (disp));
4739 if (disp == 0)
4740 as_bad_where (fragP->fr_file, fragP->fr_line,
4741 _("short branch with zero offset: use :w"));
4742 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4743 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4744 fixP->fx_pcrel_adjust = -1;
4745 break;
4746 case TAB (BRANCHBWL, SHORT):
4747 case TAB (BRABSJUNC, SHORT):
4748 case TAB (BRABSJCOND, SHORT):
4749 case TAB (BRANCHBW, SHORT):
4750 fragP->fr_opcode[1] = 0x00;
4751 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4752 1, RELAX_RELOC_PC16);
4753 fragP->fr_fix += 2;
4754 break;
4755 case TAB (BRANCHBWL, LONG):
4756 fragP->fr_opcode[1] = (char) 0xFF;
4757 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4758 1, RELAX_RELOC_PC32);
4759 fragP->fr_fix += 4;
4760 break;
4761 case TAB (BRABSJUNC, LONG):
4762 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4763 {
4764 if (flag_keep_pcrel)
4765 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
4766 fragP->fr_opcode[0] = 0x4E;
4767 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4768 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4769 0, RELAX_RELOC_ABS32);
4770 fragP->fr_fix += 4;
4771 }
4772 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4773 {
4774 if (flag_keep_pcrel)
4775 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
4776 fragP->fr_opcode[0] = 0x4E;
4777 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4778 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4779 0, RELAX_RELOC_ABS32);
4780 fragP->fr_fix += 4;
4781 }
4782 else
4783 {
4784 /* This cannot happen, because jbsr and jbra are the only two
4785 unconditional branches. */
4786 abort ();
4787 }
4788 break;
4789 case TAB (BRABSJCOND, LONG):
4790 if (flag_keep_pcrel)
4791 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4792
4793 /* Only Bcc 68000 instructions can come here
4794 Change bcc into b!cc/jmp absl long. */
4795 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4796 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
4797
4798 /* JF: these used to be fr_opcode[2,3], but they may be in a
4799 different frag, in which case referring to them is a no-no.
4800 Only fr_opcode[0,1] are guaranteed to work. */
4801 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4802 *buffer_address++ = (char) 0xf9;
4803 fragP->fr_fix += 2; /* Account for jmp instruction. */
4804 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4805 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4806 fragP->fr_fix += 4;
4807 break;
4808 case TAB (FBRANCH, SHORT):
4809 know ((fragP->fr_opcode[1] & 0x40) == 0);
4810 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4811 1, RELAX_RELOC_PC16);
4812 fragP->fr_fix += 2;
4813 break;
4814 case TAB (FBRANCH, LONG):
4815 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
4816 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4817 1, RELAX_RELOC_PC32);
4818 fragP->fr_fix += 4;
4819 break;
4820 case TAB (DBCCLBR, SHORT):
4821 case TAB (DBCCABSJ, SHORT):
4822 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4823 1, RELAX_RELOC_PC16);
4824 fragP->fr_fix += 2;
4825 break;
4826 case TAB (DBCCLBR, LONG):
4827 /* Only DBcc instructions can come here.
4828 Change dbcc into dbcc/bral.
4829 JF: these used to be fr_opcode[2-7], but that's wrong. */
4830 if (flag_keep_pcrel)
4831 as_fatal (_("Tried to convert DBcc to absolute jump"));
4832
4833 *buffer_address++ = 0x00; /* Branch offset = 4. */
4834 *buffer_address++ = 0x04;
4835 *buffer_address++ = 0x60; /* Put in bra pc+6. */
4836 *buffer_address++ = 0x06;
4837 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4838 *buffer_address++ = (char) 0xff;
4839
4840 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4841 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
4842 RELAX_RELOC_PC32);
4843 fragP->fr_fix += 4;
4844 break;
4845 case TAB (DBCCABSJ, LONG):
4846 /* Only DBcc instructions can come here.
4847 Change dbcc into dbcc/jmp.
4848 JF: these used to be fr_opcode[2-7], but that's wrong. */
4849 if (flag_keep_pcrel)
4850 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4851
4852 *buffer_address++ = 0x00; /* Branch offset = 4. */
4853 *buffer_address++ = 0x04;
4854 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
4855 *buffer_address++ = 0x06;
4856 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4857 *buffer_address++ = (char) 0xf9;
4858
4859 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4860 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
4861 RELAX_RELOC_ABS32);
4862 fragP->fr_fix += 4;
4863 break;
4864 case TAB (PCREL1632, SHORT):
4865 fragP->fr_opcode[1] &= ~0x3F;
4866 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4867 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4868 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4869 fragP->fr_fix += 2;
4870 break;
4871 case TAB (PCREL1632, LONG):
4872 /* Already set to mode 7.3; this indicates: PC indirect with
4873 suppressed index, 32-bit displacement. */
4874 *buffer_address++ = 0x01;
4875 *buffer_address++ = 0x70;
4876 fragP->fr_fix += 2;
4877 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4878 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4879 fixP->fx_pcrel_adjust = 2;
4880 fragP->fr_fix += 4;
4881 break;
4882 case TAB (PCINDEX, BYTE):
4883 assert (fragP->fr_fix >= 2);
4884 buffer_address[-2] &= ~1;
4885 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4886 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4887 fixP->fx_pcrel_adjust = 1;
4888 break;
4889 case TAB (PCINDEX, SHORT):
4890 assert (fragP->fr_fix >= 2);
4891 buffer_address[-2] |= 0x1;
4892 buffer_address[-1] = 0x20;
4893 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4894 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4895 fixP->fx_pcrel_adjust = 2;
4896 fragP->fr_fix += 2;
4897 break;
4898 case TAB (PCINDEX, LONG):
4899 assert (fragP->fr_fix >= 2);
4900 buffer_address[-2] |= 0x1;
4901 buffer_address[-1] = 0x30;
4902 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4903 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4904 fixP->fx_pcrel_adjust = 2;
4905 fragP->fr_fix += 4;
4906 break;
4907 case TAB (ABSTOPCREL, SHORT):
4908 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4909 1, RELAX_RELOC_PC16);
4910 fragP->fr_fix += 2;
4911 break;
4912 case TAB (ABSTOPCREL, LONG):
4913 if (flag_keep_pcrel)
4914 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4915 /* The thing to do here is force it to ABSOLUTE LONG, since
4916 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
4917 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4918 abort ();
4919 fragP->fr_opcode[1] &= ~0x3F;
4920 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4921 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4922 0, RELAX_RELOC_ABS32);
4923 fragP->fr_fix += 4;
4924 break;
4925 }
4926 }
4927
4928 #ifndef BFD_ASSEMBLER
4929
4930 void
4931 md_convert_frag (object_headers *headers ATTRIBUTE_UNUSED,
4932 segT sec ATTRIBUTE_UNUSED,
4933 fragS *fragP)
4934 {
4935 md_convert_frag_1 (fragP);
4936 }
4937
4938 #else
4939
4940 void
4941 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
4942 segT sec ATTRIBUTE_UNUSED,
4943 fragS *fragP)
4944 {
4945 md_convert_frag_1 (fragP);
4946 }
4947 #endif
4948
4949 /* Force truly undefined symbols to their maximum size, and generally set up
4950 the frag list to be relaxed
4951 */
4952 int
4953 md_estimate_size_before_relax (fragS *fragP, segT segment)
4954 {
4955 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4956 switch (fragP->fr_subtype)
4957 {
4958 case TAB (BRANCHBWL, SZ_UNDEF):
4959 case TAB (BRABSJUNC, SZ_UNDEF):
4960 case TAB (BRABSJCOND, SZ_UNDEF):
4961 {
4962 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4963 && relaxable_symbol (fragP->fr_symbol))
4964 {
4965 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4966 }
4967 else if (flag_short_refs)
4968 {
4969 /* Symbol is undefined and we want short ref. */
4970 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4971 }
4972 else
4973 {
4974 /* Symbol is still undefined. Make it LONG. */
4975 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4976 }
4977 break;
4978 }
4979
4980 case TAB (BRANCHBW, SZ_UNDEF):
4981 {
4982 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4983 && relaxable_symbol (fragP->fr_symbol))
4984 {
4985 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4986 }
4987 else
4988 {
4989 /* Symbol is undefined and we don't have long branches. */
4990 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4991 }
4992 break;
4993 }
4994
4995 case TAB (FBRANCH, SZ_UNDEF):
4996 case TAB (DBCCLBR, SZ_UNDEF):
4997 case TAB (DBCCABSJ, SZ_UNDEF):
4998 case TAB (PCREL1632, SZ_UNDEF):
4999 {
5000 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5001 && relaxable_symbol (fragP->fr_symbol))
5002 || flag_short_refs)
5003 {
5004 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5005 }
5006 else
5007 {
5008 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5009 }
5010 break;
5011 }
5012
5013 case TAB (PCINDEX, SZ_UNDEF):
5014 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5015 && relaxable_symbol (fragP->fr_symbol)))
5016 {
5017 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5018 }
5019 else
5020 {
5021 fragP->fr_subtype = TAB (PCINDEX, LONG);
5022 }
5023 break;
5024
5025 case TAB (ABSTOPCREL, SZ_UNDEF):
5026 {
5027 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5028 && relaxable_symbol (fragP->fr_symbol)))
5029 {
5030 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5031 }
5032 else
5033 {
5034 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5035 }
5036 break;
5037 }
5038
5039 default:
5040 break;
5041 }
5042
5043 /* Now that SZ_UNDEF are taken care of, check others. */
5044 switch (fragP->fr_subtype)
5045 {
5046 case TAB (BRANCHBWL, BYTE):
5047 case TAB (BRABSJUNC, BYTE):
5048 case TAB (BRABSJCOND, BYTE):
5049 case TAB (BRANCHBW, BYTE):
5050 /* We can't do a short jump to the next instruction, so in that
5051 case we force word mode. If the symbol is at the start of a
5052 frag, and it is the next frag with any data in it (usually
5053 this is just the next frag, but assembler listings may
5054 introduce empty frags), we must use word mode. */
5055 if (fragP->fr_symbol)
5056 {
5057 fragS *sym_frag;
5058
5059 sym_frag = symbol_get_frag (fragP->fr_symbol);
5060 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5061 {
5062 fragS *l;
5063
5064 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5065 if (l->fr_fix != 0)
5066 break;
5067 if (l == sym_frag)
5068 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5069 }
5070 }
5071 break;
5072 default:
5073 break;
5074 }
5075 return md_relax_table[fragP->fr_subtype].rlx_length;
5076 }
5077
5078 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5079 /* the bit-field entries in the relocation_info struct plays hell
5080 with the byte-order problems of cross-assembly. So as a hack,
5081 I added this mach. dependent ri twiddler. Ugly, but it gets
5082 you there. -KWK */
5083 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5084 are symbolnum, most sig. byte first. Last byte is broken up with
5085 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5086 nibble as nuthin. (on Sun 3 at least) */
5087 /* Translate the internal relocation information into target-specific
5088 format. */
5089 #ifdef comment
5090 void
5091 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
5092 {
5093 /* This is easy. */
5094 md_number_to_chars (the_bytes, ri->r_address, 4);
5095 /* Now the fun stuff. */
5096 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5097 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5098 the_bytes[6] = ri->r_symbolnum & 0x0ff;
5099 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5100 | ((ri->r_length << 5) & 0x60)
5101 | ((ri->r_extern << 4) & 0x10));
5102 }
5103
5104 #endif
5105
5106 #ifndef BFD_ASSEMBLER
5107 void
5108 tc_aout_fix_to_chars (char *where, fixS *fixP,
5109 relax_addressT segment_address_in_file)
5110 {
5111 /*
5112 * In: length of relocation (or of address) in chars: 1, 2 or 4.
5113 * Out: GNU LD relocation length code: 0, 1, or 2.
5114 */
5115
5116 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
5117 long r_symbolnum;
5118
5119 know (fixP->fx_addsy != NULL);
5120
5121 md_number_to_chars (where,
5122 (fixP->fx_frag->fr_address
5123 + fixP->fx_where - segment_address_in_file), 4);
5124
5125 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
5126 ? S_GET_TYPE (fixP->fx_addsy)
5127 : fixP->fx_addsy->sy_number);
5128
5129 where[4] = (r_symbolnum >> 16) & 0x0ff;
5130 where[5] = (r_symbolnum >> 8) & 0x0ff;
5131 where[6] = r_symbolnum & 0x0ff;
5132 where[7] = (((fixP->fx_pcrel << 7) & 0x80)
5133 | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60)
5134 | ((!S_IS_DEFINED (fixP->fx_addsy) << 4) & 0x10));
5135 }
5136 #endif
5137
5138 #endif /* OBJ_AOUT or OBJ_BOUT */
5139
5140 #ifndef WORKING_DOT_WORD
5141 int md_short_jump_size = 4;
5142 int md_long_jump_size = 6;
5143
5144 void
5145 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5146 fragS *frag ATTRIBUTE_UNUSED,
5147 symbolS *to_symbol ATTRIBUTE_UNUSED)
5148 {
5149 valueT offset;
5150
5151 offset = to_addr - (from_addr + 2);
5152
5153 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5154 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5155 }
5156
5157 void
5158 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5159 fragS *frag, symbolS *to_symbol)
5160 {
5161 valueT offset;
5162
5163 if (!HAVE_LONG_BRANCH (current_architecture))
5164 {
5165 if (flag_keep_pcrel)
5166 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5167 offset = to_addr - S_GET_VALUE (to_symbol);
5168 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5169 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5170 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5171 0, NO_RELOC);
5172 }
5173 else
5174 {
5175 offset = to_addr - (from_addr + 2);
5176 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5177 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5178 }
5179 }
5180
5181 #endif
5182
5183 /* Different values of OK tell what its OK to return. Things that
5184 aren't OK are an error (what a shock, no?)
5185
5186 0: Everything is OK
5187 10: Absolute 1:8 only
5188 20: Absolute 0:7 only
5189 30: absolute 0:15 only
5190 40: Absolute 0:31 only
5191 50: absolute 0:127 only
5192 55: absolute -64:63 only
5193 60: absolute -128:127 only
5194 70: absolute 0:4095 only
5195 80: absolute -1, 1:7 only
5196 90: No bignums. */
5197
5198 static int
5199 get_num (struct m68k_exp *exp, int ok)
5200 {
5201 if (exp->exp.X_op == O_absent)
5202 {
5203 /* Do the same thing the VAX asm does. */
5204 op (exp) = O_constant;
5205 adds (exp) = 0;
5206 subs (exp) = 0;
5207 offs (exp) = 0;
5208 if (ok == 10)
5209 {
5210 as_warn (_("expression out of range: defaulting to 1"));
5211 offs (exp) = 1;
5212 }
5213 }
5214 else if (exp->exp.X_op == O_constant)
5215 {
5216 switch (ok)
5217 {
5218 case 10:
5219 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5220 {
5221 as_warn (_("expression out of range: defaulting to 1"));
5222 offs (exp) = 1;
5223 }
5224 break;
5225 case 20:
5226 if ((valueT) TRUNC (offs (exp)) > 7)
5227 goto outrange;
5228 break;
5229 case 30:
5230 if ((valueT) TRUNC (offs (exp)) > 15)
5231 goto outrange;
5232 break;
5233 case 40:
5234 if ((valueT) TRUNC (offs (exp)) > 32)
5235 goto outrange;
5236 break;
5237 case 50:
5238 if ((valueT) TRUNC (offs (exp)) > 127)
5239 goto outrange;
5240 break;
5241 case 55:
5242 if ((valueT) SEXT (offs (exp)) + 64 > 127)
5243 goto outrange;
5244 break;
5245 case 60:
5246 if ((valueT) SEXT (offs (exp)) + 128 > 255)
5247 goto outrange;
5248 break;
5249 case 70:
5250 if ((valueT) TRUNC (offs (exp)) > 4095)
5251 {
5252 outrange:
5253 as_warn (_("expression out of range: defaulting to 0"));
5254 offs (exp) = 0;
5255 }
5256 break;
5257 case 80:
5258 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5259 && (valueT) TRUNC (offs (exp)) - 1 > 6)
5260 {
5261 as_warn (_("expression out of range: defaulting to 1"));
5262 offs (exp) = 1;
5263 }
5264 break;
5265 default:
5266 break;
5267 }
5268 }
5269 else if (exp->exp.X_op == O_big)
5270 {
5271 if (offs (exp) <= 0 /* flonum. */
5272 && (ok == 90 /* no bignums */
5273 || (ok > 10 /* Small-int ranges including 0 ok. */
5274 /* If we have a flonum zero, a zero integer should
5275 do as well (e.g., in moveq). */
5276 && generic_floating_point_number.exponent == 0
5277 && generic_floating_point_number.low[0] == 0)))
5278 {
5279 /* HACK! Turn it into a long. */
5280 LITTLENUM_TYPE words[6];
5281
5282 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5283 op (exp) = O_constant;
5284 adds (exp) = 0;
5285 subs (exp) = 0;
5286 offs (exp) = words[1] | (words[0] << 16);
5287 }
5288 else if (ok != 0)
5289 {
5290 op (exp) = O_constant;
5291 adds (exp) = 0;
5292 subs (exp) = 0;
5293 offs (exp) = (ok == 10) ? 1 : 0;
5294 as_warn (_("Can't deal with expression; defaulting to %ld"),
5295 (long) offs (exp));
5296 }
5297 }
5298 else
5299 {
5300 if (ok >= 10 && ok <= 80)
5301 {
5302 op (exp) = O_constant;
5303 adds (exp) = 0;
5304 subs (exp) = 0;
5305 offs (exp) = (ok == 10) ? 1 : 0;
5306 as_warn (_("Can't deal with expression; defaulting to %ld"),
5307 (long) offs (exp));
5308 }
5309 }
5310
5311 if (exp->size != SIZE_UNSPEC)
5312 {
5313 switch (exp->size)
5314 {
5315 case SIZE_UNSPEC:
5316 case SIZE_LONG:
5317 break;
5318 case SIZE_BYTE:
5319 if (!isbyte (offs (exp)))
5320 as_warn (_("expression doesn't fit in BYTE"));
5321 break;
5322 case SIZE_WORD:
5323 if (!isword (offs (exp)))
5324 as_warn (_("expression doesn't fit in WORD"));
5325 break;
5326 }
5327 }
5328
5329 return offs (exp);
5330 }
5331
5332 /* These are the back-ends for the various machine dependent pseudo-ops. */
5333
5334 static void
5335 s_data1 (int ignore ATTRIBUTE_UNUSED)
5336 {
5337 subseg_set (data_section, 1);
5338 demand_empty_rest_of_line ();
5339 }
5340
5341 static void
5342 s_data2 (int ignore ATTRIBUTE_UNUSED)
5343 {
5344 subseg_set (data_section, 2);
5345 demand_empty_rest_of_line ();
5346 }
5347
5348 static void
5349 s_bss (int ignore ATTRIBUTE_UNUSED)
5350 {
5351 /* We don't support putting frags in the BSS segment, we fake it
5352 by marking in_bss, then looking at s_skip for clues. */
5353
5354 subseg_set (bss_section, 0);
5355 demand_empty_rest_of_line ();
5356 }
5357
5358 static void
5359 s_even (int ignore ATTRIBUTE_UNUSED)
5360 {
5361 register int temp;
5362 register long temp_fill;
5363
5364 temp = 1; /* JF should be 2? */
5365 temp_fill = get_absolute_expression ();
5366 if (!need_pass_2) /* Never make frag if expect extra pass. */
5367 frag_align (temp, (int) temp_fill, 0);
5368 demand_empty_rest_of_line ();
5369 record_alignment (now_seg, temp);
5370 }
5371
5372 static void
5373 s_proc (int ignore ATTRIBUTE_UNUSED)
5374 {
5375 demand_empty_rest_of_line ();
5376 }
5377 \f
5378 /* Pseudo-ops handled for MRI compatibility. */
5379
5380 /* This function returns non-zero if the argument is a conditional
5381 pseudo-op. This is called when checking whether a pending
5382 alignment is needed. */
5383
5384 int
5385 m68k_conditional_pseudoop (pseudo_typeS *pop)
5386 {
5387 return (pop->poc_handler == s_mri_if
5388 || pop->poc_handler == s_mri_else);
5389 }
5390
5391 /* Handle an MRI style chip specification. */
5392
5393 static void
5394 mri_chip (void)
5395 {
5396 char *s;
5397 char c;
5398 int i;
5399
5400 s = input_line_pointer;
5401 /* We can't use get_symbol_end since the processor names are not proper
5402 symbols. */
5403 while (is_part_of_name (c = *input_line_pointer++))
5404 ;
5405 *--input_line_pointer = 0;
5406 for (i = 0; i < n_archs; i++)
5407 if (strcasecmp (s, archs[i].name) == 0)
5408 break;
5409 if (i >= n_archs)
5410 {
5411 as_bad (_("%s: unrecognized processor name"), s);
5412 *input_line_pointer = c;
5413 ignore_rest_of_line ();
5414 return;
5415 }
5416 *input_line_pointer = c;
5417
5418 if (*input_line_pointer == '/')
5419 current_architecture = 0;
5420 else
5421 current_architecture &= m68881 | m68851;
5422 current_architecture |= archs[i].arch;
5423 current_chip = archs[i].chip;
5424
5425 while (*input_line_pointer == '/')
5426 {
5427 ++input_line_pointer;
5428 s = input_line_pointer;
5429 /* We can't use get_symbol_end since the processor names are not
5430 proper symbols. */
5431 while (is_part_of_name (c = *input_line_pointer++))
5432 ;
5433 *--input_line_pointer = 0;
5434 if (strcmp (s, "68881") == 0)
5435 current_architecture |= m68881;
5436 else if (strcmp (s, "68851") == 0)
5437 current_architecture |= m68851;
5438 *input_line_pointer = c;
5439 }
5440
5441 /* Update info about available control registers. */
5442 select_control_regs ();
5443 }
5444
5445 /* The MRI CHIP pseudo-op. */
5446
5447 static void
5448 s_chip (int ignore ATTRIBUTE_UNUSED)
5449 {
5450 char *stop = NULL;
5451 char stopc;
5452
5453 if (flag_mri)
5454 stop = mri_comment_field (&stopc);
5455 mri_chip ();
5456 if (flag_mri)
5457 mri_comment_end (stop, stopc);
5458 demand_empty_rest_of_line ();
5459 }
5460
5461 /* The MRI FOPT pseudo-op. */
5462
5463 static void
5464 s_fopt (int ignore ATTRIBUTE_UNUSED)
5465 {
5466 SKIP_WHITESPACE ();
5467
5468 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5469 {
5470 int temp;
5471
5472 input_line_pointer += 3;
5473 temp = get_absolute_expression ();
5474 if (temp < 0 || temp > 7)
5475 as_bad (_("bad coprocessor id"));
5476 else
5477 m68k_float_copnum = COP0 + temp;
5478 }
5479 else
5480 {
5481 as_bad (_("unrecognized fopt option"));
5482 ignore_rest_of_line ();
5483 return;
5484 }
5485
5486 demand_empty_rest_of_line ();
5487 }
5488
5489 /* The structure used to handle the MRI OPT pseudo-op. */
5490
5491 struct opt_action
5492 {
5493 /* The name of the option. */
5494 const char *name;
5495
5496 /* If this is not NULL, just call this function. The first argument
5497 is the ARG field of this structure, the second argument is
5498 whether the option was negated. */
5499 void (*pfn) (int arg, int on);
5500
5501 /* If this is not NULL, and the PFN field is NULL, set the variable
5502 this points to. Set it to the ARG field if the option was not
5503 negated, and the NOTARG field otherwise. */
5504 int *pvar;
5505
5506 /* The value to pass to PFN or to assign to *PVAR. */
5507 int arg;
5508
5509 /* The value to assign to *PVAR if the option is negated. If PFN is
5510 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5511 the option may not be negated. */
5512 int notarg;
5513 };
5514
5515 /* The table used to handle the MRI OPT pseudo-op. */
5516
5517 static void skip_to_comma (int, int);
5518 static void opt_nest (int, int);
5519 static void opt_chip (int, int);
5520 static void opt_list (int, int);
5521 static void opt_list_symbols (int, int);
5522
5523 static const struct opt_action opt_table[] =
5524 {
5525 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5526
5527 /* We do relaxing, so there is little use for these options. */
5528 { "b", 0, 0, 0, 0 },
5529 { "brs", 0, 0, 0, 0 },
5530 { "brb", 0, 0, 0, 0 },
5531 { "brl", 0, 0, 0, 0 },
5532 { "brw", 0, 0, 0, 0 },
5533
5534 { "c", 0, 0, 0, 0 },
5535 { "cex", 0, 0, 0, 0 },
5536 { "case", 0, &symbols_case_sensitive, 1, 0 },
5537 { "cl", 0, 0, 0, 0 },
5538 { "cre", 0, 0, 0, 0 },
5539 { "d", 0, &flag_keep_locals, 1, 0 },
5540 { "e", 0, 0, 0, 0 },
5541 { "f", 0, &flag_short_refs, 1, 0 },
5542 { "frs", 0, &flag_short_refs, 1, 0 },
5543 { "frl", 0, &flag_short_refs, 0, 1 },
5544 { "g", 0, 0, 0, 0 },
5545 { "i", 0, 0, 0, 0 },
5546 { "m", 0, 0, 0, 0 },
5547 { "mex", 0, 0, 0, 0 },
5548 { "mc", 0, 0, 0, 0 },
5549 { "md", 0, 0, 0, 0 },
5550 { "nest", opt_nest, 0, 0, 0 },
5551 { "next", skip_to_comma, 0, 0, 0 },
5552 { "o", 0, 0, 0, 0 },
5553 { "old", 0, 0, 0, 0 },
5554 { "op", skip_to_comma, 0, 0, 0 },
5555 { "pco", 0, 0, 0, 0 },
5556 { "p", opt_chip, 0, 0, 0 },
5557 { "pcr", 0, 0, 0, 0 },
5558 { "pcs", 0, 0, 0, 0 },
5559 { "r", 0, 0, 0, 0 },
5560 { "quick", 0, &m68k_quick, 1, 0 },
5561 { "rel32", 0, &m68k_rel32, 1, 0 },
5562 { "s", opt_list, 0, 0, 0 },
5563 { "t", opt_list_symbols, 0, 0, 0 },
5564 { "w", 0, &flag_no_warnings, 0, 1 },
5565 { "x", 0, 0, 0, 0 }
5566 };
5567
5568 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5569
5570 /* The MRI OPT pseudo-op. */
5571
5572 static void
5573 s_opt (int ignore ATTRIBUTE_UNUSED)
5574 {
5575 do
5576 {
5577 int t;
5578 char *s;
5579 char c;
5580 int i;
5581 const struct opt_action *o;
5582
5583 SKIP_WHITESPACE ();
5584
5585 t = 1;
5586 if (*input_line_pointer == '-')
5587 {
5588 ++input_line_pointer;
5589 t = 0;
5590 }
5591 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5592 {
5593 input_line_pointer += 2;
5594 t = 0;
5595 }
5596
5597 s = input_line_pointer;
5598 c = get_symbol_end ();
5599
5600 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5601 {
5602 if (strcasecmp (s, o->name) == 0)
5603 {
5604 if (o->pfn)
5605 {
5606 /* Restore input_line_pointer now in case the option
5607 takes arguments. */
5608 *input_line_pointer = c;
5609 (*o->pfn) (o->arg, t);
5610 }
5611 else if (o->pvar != NULL)
5612 {
5613 if (! t && o->arg == o->notarg)
5614 as_bad (_("option `%s' may not be negated"), s);
5615 *input_line_pointer = c;
5616 *o->pvar = t ? o->arg : o->notarg;
5617 }
5618 else
5619 *input_line_pointer = c;
5620 break;
5621 }
5622 }
5623 if (i >= OPTCOUNT)
5624 {
5625 as_bad (_("option `%s' not recognized"), s);
5626 *input_line_pointer = c;
5627 }
5628 }
5629 while (*input_line_pointer++ == ',');
5630
5631 /* Move back to terminating character. */
5632 --input_line_pointer;
5633 demand_empty_rest_of_line ();
5634 }
5635
5636 /* Skip ahead to a comma. This is used for OPT options which we do
5637 not support and which take arguments. */
5638
5639 static void
5640 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5641 {
5642 while (*input_line_pointer != ','
5643 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5644 ++input_line_pointer;
5645 }
5646
5647 /* Handle the OPT NEST=depth option. */
5648
5649 static void
5650 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5651 {
5652 if (*input_line_pointer != '=')
5653 {
5654 as_bad (_("bad format of OPT NEST=depth"));
5655 return;
5656 }
5657
5658 ++input_line_pointer;
5659 max_macro_nest = get_absolute_expression ();
5660 }
5661
5662 /* Handle the OPT P=chip option. */
5663
5664 static void
5665 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5666 {
5667 if (*input_line_pointer != '=')
5668 {
5669 /* This is just OPT P, which we do not support. */
5670 return;
5671 }
5672
5673 ++input_line_pointer;
5674 mri_chip ();
5675 }
5676
5677 /* Handle the OPT S option. */
5678
5679 static void
5680 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5681 {
5682 listing_list (on);
5683 }
5684
5685 /* Handle the OPT T option. */
5686
5687 static void
5688 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5689 {
5690 if (on)
5691 listing |= LISTING_SYMBOLS;
5692 else
5693 listing &= ~LISTING_SYMBOLS;
5694 }
5695
5696 /* Handle the MRI REG pseudo-op. */
5697
5698 static void
5699 s_reg (int ignore ATTRIBUTE_UNUSED)
5700 {
5701 char *s;
5702 int c;
5703 struct m68k_op rop;
5704 int mask;
5705 char *stop = NULL;
5706 char stopc;
5707
5708 if (line_label == NULL)
5709 {
5710 as_bad (_("missing label"));
5711 ignore_rest_of_line ();
5712 return;
5713 }
5714
5715 if (flag_mri)
5716 stop = mri_comment_field (&stopc);
5717
5718 SKIP_WHITESPACE ();
5719
5720 s = input_line_pointer;
5721 while (ISALNUM (*input_line_pointer)
5722 #ifdef REGISTER_PREFIX
5723 || *input_line_pointer == REGISTER_PREFIX
5724 #endif
5725 || *input_line_pointer == '/'
5726 || *input_line_pointer == '-')
5727 ++input_line_pointer;
5728 c = *input_line_pointer;
5729 *input_line_pointer = '\0';
5730
5731 if (m68k_ip_op (s, &rop) != 0)
5732 {
5733 if (rop.error == NULL)
5734 as_bad (_("bad register list"));
5735 else
5736 as_bad (_("bad register list: %s"), rop.error);
5737 *input_line_pointer = c;
5738 ignore_rest_of_line ();
5739 return;
5740 }
5741
5742 *input_line_pointer = c;
5743
5744 if (rop.mode == REGLST)
5745 mask = rop.mask;
5746 else if (rop.mode == DREG)
5747 mask = 1 << (rop.reg - DATA0);
5748 else if (rop.mode == AREG)
5749 mask = 1 << (rop.reg - ADDR0 + 8);
5750 else if (rop.mode == FPREG)
5751 mask = 1 << (rop.reg - FP0 + 16);
5752 else if (rop.mode == CONTROL
5753 && rop.reg == FPI)
5754 mask = 1 << 24;
5755 else if (rop.mode == CONTROL
5756 && rop.reg == FPS)
5757 mask = 1 << 25;
5758 else if (rop.mode == CONTROL
5759 && rop.reg == FPC)
5760 mask = 1 << 26;
5761 else
5762 {
5763 as_bad (_("bad register list"));
5764 ignore_rest_of_line ();
5765 return;
5766 }
5767
5768 S_SET_SEGMENT (line_label, reg_section);
5769 S_SET_VALUE (line_label, ~mask);
5770 symbol_set_frag (line_label, &zero_address_frag);
5771
5772 if (flag_mri)
5773 mri_comment_end (stop, stopc);
5774
5775 demand_empty_rest_of_line ();
5776 }
5777
5778 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5779
5780 struct save_opts
5781 {
5782 struct save_opts *next;
5783 int abspcadd;
5784 int symbols_case_sensitive;
5785 int keep_locals;
5786 int short_refs;
5787 int architecture;
5788 int chip;
5789 int quick;
5790 int rel32;
5791 int listing;
5792 int no_warnings;
5793 /* FIXME: We don't save OPT S. */
5794 };
5795
5796 /* This variable holds the stack of saved options. */
5797
5798 static struct save_opts *save_stack;
5799
5800 /* The MRI SAVE pseudo-op. */
5801
5802 static void
5803 s_save (int ignore ATTRIBUTE_UNUSED)
5804 {
5805 struct save_opts *s;
5806
5807 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5808 s->abspcadd = m68k_abspcadd;
5809 s->symbols_case_sensitive = symbols_case_sensitive;
5810 s->keep_locals = flag_keep_locals;
5811 s->short_refs = flag_short_refs;
5812 s->architecture = current_architecture;
5813 s->chip = current_chip;
5814 s->quick = m68k_quick;
5815 s->rel32 = m68k_rel32;
5816 s->listing = listing;
5817 s->no_warnings = flag_no_warnings;
5818
5819 s->next = save_stack;
5820 save_stack = s;
5821
5822 demand_empty_rest_of_line ();
5823 }
5824
5825 /* The MRI RESTORE pseudo-op. */
5826
5827 static void
5828 s_restore (int ignore ATTRIBUTE_UNUSED)
5829 {
5830 struct save_opts *s;
5831
5832 if (save_stack == NULL)
5833 {
5834 as_bad (_("restore without save"));
5835 ignore_rest_of_line ();
5836 return;
5837 }
5838
5839 s = save_stack;
5840 save_stack = s->next;
5841
5842 m68k_abspcadd = s->abspcadd;
5843 symbols_case_sensitive = s->symbols_case_sensitive;
5844 flag_keep_locals = s->keep_locals;
5845 flag_short_refs = s->short_refs;
5846 current_architecture = s->architecture;
5847 current_chip = s->chip;
5848 m68k_quick = s->quick;
5849 m68k_rel32 = s->rel32;
5850 listing = s->listing;
5851 flag_no_warnings = s->no_warnings;
5852
5853 free (s);
5854
5855 demand_empty_rest_of_line ();
5856 }
5857
5858 /* Types of MRI structured control directives. */
5859
5860 enum mri_control_type
5861 {
5862 mri_for,
5863 mri_if,
5864 mri_repeat,
5865 mri_while
5866 };
5867
5868 /* This structure is used to stack the MRI structured control
5869 directives. */
5870
5871 struct mri_control_info
5872 {
5873 /* The directive within which this one is enclosed. */
5874 struct mri_control_info *outer;
5875
5876 /* The type of directive. */
5877 enum mri_control_type type;
5878
5879 /* Whether an ELSE has been in an IF. */
5880 int else_seen;
5881
5882 /* The add or sub statement at the end of a FOR. */
5883 char *incr;
5884
5885 /* The label of the top of a FOR or REPEAT loop. */
5886 char *top;
5887
5888 /* The label to jump to for the next iteration, or the else
5889 expression of a conditional. */
5890 char *next;
5891
5892 /* The label to jump to to break out of the loop, or the label past
5893 the end of a conditional. */
5894 char *bottom;
5895 };
5896
5897 /* The stack of MRI structured control directives. */
5898
5899 static struct mri_control_info *mri_control_stack;
5900
5901 /* The current MRI structured control directive index number, used to
5902 generate label names. */
5903
5904 static int mri_control_index;
5905
5906 /* Assemble an instruction for an MRI structured control directive. */
5907
5908 static void
5909 mri_assemble (char *str)
5910 {
5911 char *s;
5912
5913 /* md_assemble expects the opcode to be in lower case. */
5914 for (s = str; *s != ' ' && *s != '\0'; s++)
5915 *s = TOLOWER (*s);
5916
5917 md_assemble (str);
5918 }
5919
5920 /* Generate a new MRI label structured control directive label name. */
5921
5922 static char *
5923 mri_control_label (void)
5924 {
5925 char *n;
5926
5927 n = (char *) xmalloc (20);
5928 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5929 ++mri_control_index;
5930 return n;
5931 }
5932
5933 /* Create a new MRI structured control directive. */
5934
5935 static struct mri_control_info *
5936 push_mri_control (enum mri_control_type type)
5937 {
5938 struct mri_control_info *n;
5939
5940 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5941
5942 n->type = type;
5943 n->else_seen = 0;
5944 if (type == mri_if || type == mri_while)
5945 n->top = NULL;
5946 else
5947 n->top = mri_control_label ();
5948 n->next = mri_control_label ();
5949 n->bottom = mri_control_label ();
5950
5951 n->outer = mri_control_stack;
5952 mri_control_stack = n;
5953
5954 return n;
5955 }
5956
5957 /* Pop off the stack of MRI structured control directives. */
5958
5959 static void
5960 pop_mri_control (void)
5961 {
5962 struct mri_control_info *n;
5963
5964 n = mri_control_stack;
5965 mri_control_stack = n->outer;
5966 if (n->top != NULL)
5967 free (n->top);
5968 free (n->next);
5969 free (n->bottom);
5970 free (n);
5971 }
5972
5973 /* Recognize a condition code in an MRI structured control expression. */
5974
5975 static int
5976 parse_mri_condition (int *pcc)
5977 {
5978 char c1, c2;
5979
5980 know (*input_line_pointer == '<');
5981
5982 ++input_line_pointer;
5983 c1 = *input_line_pointer++;
5984 c2 = *input_line_pointer++;
5985
5986 if (*input_line_pointer != '>')
5987 {
5988 as_bad (_("syntax error in structured control directive"));
5989 return 0;
5990 }
5991
5992 ++input_line_pointer;
5993 SKIP_WHITESPACE ();
5994
5995 c1 = TOLOWER (c1);
5996 c2 = TOLOWER (c2);
5997
5998 *pcc = (c1 << 8) | c2;
5999
6000 return 1;
6001 }
6002
6003 /* Parse a single operand in an MRI structured control expression. */
6004
6005 static int
6006 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6007 char **rightstart, char **rightstop)
6008 {
6009 char *s;
6010
6011 SKIP_WHITESPACE ();
6012
6013 *pcc = -1;
6014 *leftstart = NULL;
6015 *leftstop = NULL;
6016 *rightstart = NULL;
6017 *rightstop = NULL;
6018
6019 if (*input_line_pointer == '<')
6020 {
6021 /* It's just a condition code. */
6022 return parse_mri_condition (pcc);
6023 }
6024
6025 /* Look ahead for the condition code. */
6026 for (s = input_line_pointer; *s != '\0'; ++s)
6027 {
6028 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6029 break;
6030 }
6031 if (*s == '\0')
6032 {
6033 as_bad (_("missing condition code in structured control directive"));
6034 return 0;
6035 }
6036
6037 *leftstart = input_line_pointer;
6038 *leftstop = s;
6039 if (*leftstop > *leftstart
6040 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6041 --*leftstop;
6042
6043 input_line_pointer = s;
6044 if (! parse_mri_condition (pcc))
6045 return 0;
6046
6047 /* Look ahead for AND or OR or end of line. */
6048 for (s = input_line_pointer; *s != '\0'; ++s)
6049 {
6050 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6051 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6052 ^^^ ^^ */
6053 if ((s == input_line_pointer
6054 || *(s-1) == ' '
6055 || *(s-1) == '\t')
6056 && ((strncasecmp (s, "AND", 3) == 0
6057 && (s[3] == '.' || ! is_part_of_name (s[3])))
6058 || (strncasecmp (s, "OR", 2) == 0
6059 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6060 break;
6061 }
6062
6063 *rightstart = input_line_pointer;
6064 *rightstop = s;
6065 if (*rightstop > *rightstart
6066 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6067 --*rightstop;
6068
6069 input_line_pointer = s;
6070
6071 return 1;
6072 }
6073
6074 #define MCC(b1, b2) (((b1) << 8) | (b2))
6075
6076 /* Swap the sense of a condition. This changes the condition so that
6077 it generates the same result when the operands are swapped. */
6078
6079 static int
6080 swap_mri_condition (int cc)
6081 {
6082 switch (cc)
6083 {
6084 case MCC ('h', 'i'): return MCC ('c', 's');
6085 case MCC ('l', 's'): return MCC ('c', 'c');
6086 /* <HS> is an alias for <CC>. */
6087 case MCC ('h', 's'):
6088 case MCC ('c', 'c'): return MCC ('l', 's');
6089 /* <LO> is an alias for <CS>. */
6090 case MCC ('l', 'o'):
6091 case MCC ('c', 's'): return MCC ('h', 'i');
6092 case MCC ('p', 'l'): return MCC ('m', 'i');
6093 case MCC ('m', 'i'): return MCC ('p', 'l');
6094 case MCC ('g', 'e'): return MCC ('l', 'e');
6095 case MCC ('l', 't'): return MCC ('g', 't');
6096 case MCC ('g', 't'): return MCC ('l', 't');
6097 case MCC ('l', 'e'): return MCC ('g', 'e');
6098 /* Issue a warning for conditions we can not swap. */
6099 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6100 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6101 case MCC ('v', 'c'):
6102 case MCC ('v', 's'):
6103 default :
6104 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6105 (char) (cc >> 8), (char) (cc));
6106 break;
6107 }
6108 return cc;
6109 }
6110
6111 /* Reverse the sense of a condition. */
6112
6113 static int
6114 reverse_mri_condition (int cc)
6115 {
6116 switch (cc)
6117 {
6118 case MCC ('h', 'i'): return MCC ('l', 's');
6119 case MCC ('l', 's'): return MCC ('h', 'i');
6120 /* <HS> is an alias for <CC> */
6121 case MCC ('h', 's'): return MCC ('l', 'o');
6122 case MCC ('c', 'c'): return MCC ('c', 's');
6123 /* <LO> is an alias for <CS> */
6124 case MCC ('l', 'o'): return MCC ('h', 's');
6125 case MCC ('c', 's'): return MCC ('c', 'c');
6126 case MCC ('n', 'e'): return MCC ('e', 'q');
6127 case MCC ('e', 'q'): return MCC ('n', 'e');
6128 case MCC ('v', 'c'): return MCC ('v', 's');
6129 case MCC ('v', 's'): return MCC ('v', 'c');
6130 case MCC ('p', 'l'): return MCC ('m', 'i');
6131 case MCC ('m', 'i'): return MCC ('p', 'l');
6132 case MCC ('g', 'e'): return MCC ('l', 't');
6133 case MCC ('l', 't'): return MCC ('g', 'e');
6134 case MCC ('g', 't'): return MCC ('l', 'e');
6135 case MCC ('l', 'e'): return MCC ('g', 't');
6136 }
6137 return cc;
6138 }
6139
6140 /* Build an MRI structured control expression. This generates test
6141 and branch instructions. It goes to TRUELAB if the condition is
6142 true, and to FALSELAB if the condition is false. Exactly one of
6143 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6144 is the size qualifier for the expression. EXTENT is the size to
6145 use for the branch. */
6146
6147 static void
6148 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6149 char *rightstart, char *rightstop,
6150 const char *truelab, const char *falselab,
6151 int extent)
6152 {
6153 char *buf;
6154 char *s;
6155
6156 if (leftstart != NULL)
6157 {
6158 struct m68k_op leftop, rightop;
6159 char c;
6160
6161 /* Swap the compare operands, if necessary, to produce a legal
6162 m68k compare instruction. Comparing a register operand with
6163 a non-register operand requires the register to be on the
6164 right (cmp, cmpa). Comparing an immediate value with
6165 anything requires the immediate value to be on the left
6166 (cmpi). */
6167
6168 c = *leftstop;
6169 *leftstop = '\0';
6170 (void) m68k_ip_op (leftstart, &leftop);
6171 *leftstop = c;
6172
6173 c = *rightstop;
6174 *rightstop = '\0';
6175 (void) m68k_ip_op (rightstart, &rightop);
6176 *rightstop = c;
6177
6178 if (rightop.mode == IMMED
6179 || ((leftop.mode == DREG || leftop.mode == AREG)
6180 && (rightop.mode != DREG && rightop.mode != AREG)))
6181 {
6182 char *temp;
6183
6184 /* Correct conditional handling:
6185 if #1 <lt> d0 then ;means if (1 < d0)
6186 ...
6187 endi
6188
6189 should assemble to:
6190
6191 cmp #1,d0 if we do *not* swap the operands
6192 bgt true we need the swapped condition!
6193 ble false
6194 true:
6195 ...
6196 false:
6197 */
6198 temp = leftstart;
6199 leftstart = rightstart;
6200 rightstart = temp;
6201 temp = leftstop;
6202 leftstop = rightstop;
6203 rightstop = temp;
6204 }
6205 else
6206 {
6207 cc = swap_mri_condition (cc);
6208 }
6209 }
6210
6211 if (truelab == NULL)
6212 {
6213 cc = reverse_mri_condition (cc);
6214 truelab = falselab;
6215 }
6216
6217 if (leftstart != NULL)
6218 {
6219 buf = (char *) xmalloc (20
6220 + (leftstop - leftstart)
6221 + (rightstop - rightstart));
6222 s = buf;
6223 *s++ = 'c';
6224 *s++ = 'm';
6225 *s++ = 'p';
6226 if (qual != '\0')
6227 *s++ = TOLOWER (qual);
6228 *s++ = ' ';
6229 memcpy (s, leftstart, leftstop - leftstart);
6230 s += leftstop - leftstart;
6231 *s++ = ',';
6232 memcpy (s, rightstart, rightstop - rightstart);
6233 s += rightstop - rightstart;
6234 *s = '\0';
6235 mri_assemble (buf);
6236 free (buf);
6237 }
6238
6239 buf = (char *) xmalloc (20 + strlen (truelab));
6240 s = buf;
6241 *s++ = 'b';
6242 *s++ = cc >> 8;
6243 *s++ = cc & 0xff;
6244 if (extent != '\0')
6245 *s++ = TOLOWER (extent);
6246 *s++ = ' ';
6247 strcpy (s, truelab);
6248 mri_assemble (buf);
6249 free (buf);
6250 }
6251
6252 /* Parse an MRI structured control expression. This generates test
6253 and branch instructions. STOP is where the expression ends. It
6254 goes to TRUELAB if the condition is true, and to FALSELAB if the
6255 condition is false. Exactly one of TRUELAB and FALSELAB will be
6256 NULL, meaning to fall through. QUAL is the size qualifier for the
6257 expression. EXTENT is the size to use for the branch. */
6258
6259 static void
6260 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6261 const char *falselab, int extent)
6262 {
6263 int c;
6264 int cc;
6265 char *leftstart;
6266 char *leftstop;
6267 char *rightstart;
6268 char *rightstop;
6269
6270 c = *stop;
6271 *stop = '\0';
6272
6273 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6274 &rightstart, &rightstop))
6275 {
6276 *stop = c;
6277 return;
6278 }
6279
6280 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6281 {
6282 const char *flab;
6283
6284 if (falselab != NULL)
6285 flab = falselab;
6286 else
6287 flab = mri_control_label ();
6288
6289 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6290 rightstop, (const char *) NULL, flab, extent);
6291
6292 input_line_pointer += 3;
6293 if (*input_line_pointer != '.'
6294 || input_line_pointer[1] == '\0')
6295 qual = '\0';
6296 else
6297 {
6298 qual = input_line_pointer[1];
6299 input_line_pointer += 2;
6300 }
6301
6302 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6303 &rightstart, &rightstop))
6304 {
6305 *stop = c;
6306 return;
6307 }
6308
6309 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6310 rightstop, truelab, falselab, extent);
6311
6312 if (falselab == NULL)
6313 colon (flab);
6314 }
6315 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6316 {
6317 const char *tlab;
6318
6319 if (truelab != NULL)
6320 tlab = truelab;
6321 else
6322 tlab = mri_control_label ();
6323
6324 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6325 rightstop, tlab, (const char *) NULL, extent);
6326
6327 input_line_pointer += 2;
6328 if (*input_line_pointer != '.'
6329 || input_line_pointer[1] == '\0')
6330 qual = '\0';
6331 else
6332 {
6333 qual = input_line_pointer[1];
6334 input_line_pointer += 2;
6335 }
6336
6337 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6338 &rightstart, &rightstop))
6339 {
6340 *stop = c;
6341 return;
6342 }
6343
6344 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6345 rightstop, truelab, falselab, extent);
6346
6347 if (truelab == NULL)
6348 colon (tlab);
6349 }
6350 else
6351 {
6352 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6353 rightstop, truelab, falselab, extent);
6354 }
6355
6356 *stop = c;
6357 if (input_line_pointer != stop)
6358 as_bad (_("syntax error in structured control directive"));
6359 }
6360
6361 /* Handle the MRI IF pseudo-op. This may be a structured control
6362 directive, or it may be a regular assembler conditional, depending
6363 on its operands. */
6364
6365 static void
6366 s_mri_if (int qual)
6367 {
6368 char *s;
6369 int c;
6370 struct mri_control_info *n;
6371
6372 /* A structured control directive must end with THEN with an
6373 optional qualifier. */
6374 s = input_line_pointer;
6375 /* We only accept '*' as introduction of comments if preceded by white space
6376 or at first column of a line (I think this can't actually happen here?)
6377 This is important when assembling:
6378 if d0 <ne> 12(a0,d0*2) then
6379 if d0 <ne> #CONST*20 then. */
6380 while (! (is_end_of_line[(unsigned char) *s]
6381 || (flag_mri
6382 && *s == '*'
6383 && (s == input_line_pointer
6384 || *(s-1) == ' '
6385 || *(s-1) == '\t'))))
6386 ++s;
6387 --s;
6388 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6389 --s;
6390
6391 if (s - input_line_pointer > 1
6392 && s[-1] == '.')
6393 s -= 2;
6394
6395 if (s - input_line_pointer < 3
6396 || strncasecmp (s - 3, "THEN", 4) != 0)
6397 {
6398 if (qual != '\0')
6399 {
6400 as_bad (_("missing then"));
6401 ignore_rest_of_line ();
6402 return;
6403 }
6404
6405 /* It's a conditional. */
6406 s_if (O_ne);
6407 return;
6408 }
6409
6410 /* Since this might be a conditional if, this pseudo-op will be
6411 called even if we are supported to be ignoring input. Double
6412 check now. Clobber *input_line_pointer so that ignore_input
6413 thinks that this is not a special pseudo-op. */
6414 c = *input_line_pointer;
6415 *input_line_pointer = 0;
6416 if (ignore_input ())
6417 {
6418 *input_line_pointer = c;
6419 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6420 ++input_line_pointer;
6421 demand_empty_rest_of_line ();
6422 return;
6423 }
6424 *input_line_pointer = c;
6425
6426 n = push_mri_control (mri_if);
6427
6428 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6429 n->next, s[1] == '.' ? s[2] : '\0');
6430
6431 if (s[1] == '.')
6432 input_line_pointer = s + 3;
6433 else
6434 input_line_pointer = s + 1;
6435
6436 if (flag_mri)
6437 {
6438 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6439 ++input_line_pointer;
6440 }
6441
6442 demand_empty_rest_of_line ();
6443 }
6444
6445 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6446 structured IF, associate the ELSE with the IF. Otherwise, assume
6447 it is a conditional else. */
6448
6449 static void
6450 s_mri_else (int qual)
6451 {
6452 int c;
6453 char *buf;
6454 char q[2];
6455
6456 if (qual == '\0'
6457 && (mri_control_stack == NULL
6458 || mri_control_stack->type != mri_if
6459 || mri_control_stack->else_seen))
6460 {
6461 s_else (0);
6462 return;
6463 }
6464
6465 c = *input_line_pointer;
6466 *input_line_pointer = 0;
6467 if (ignore_input ())
6468 {
6469 *input_line_pointer = c;
6470 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6471 ++input_line_pointer;
6472 demand_empty_rest_of_line ();
6473 return;
6474 }
6475 *input_line_pointer = c;
6476
6477 if (mri_control_stack == NULL
6478 || mri_control_stack->type != mri_if
6479 || mri_control_stack->else_seen)
6480 {
6481 as_bad (_("else without matching if"));
6482 ignore_rest_of_line ();
6483 return;
6484 }
6485
6486 mri_control_stack->else_seen = 1;
6487
6488 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6489 q[0] = TOLOWER (qual);
6490 q[1] = '\0';
6491 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6492 mri_assemble (buf);
6493 free (buf);
6494
6495 colon (mri_control_stack->next);
6496
6497 if (flag_mri)
6498 {
6499 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6500 ++input_line_pointer;
6501 }
6502
6503 demand_empty_rest_of_line ();
6504 }
6505
6506 /* Handle the MRI ENDI pseudo-op. */
6507
6508 static void
6509 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6510 {
6511 if (mri_control_stack == NULL
6512 || mri_control_stack->type != mri_if)
6513 {
6514 as_bad (_("endi without matching if"));
6515 ignore_rest_of_line ();
6516 return;
6517 }
6518
6519 /* ignore_input will not return true for ENDI, so we don't need to
6520 worry about checking it again here. */
6521
6522 if (! mri_control_stack->else_seen)
6523 colon (mri_control_stack->next);
6524 colon (mri_control_stack->bottom);
6525
6526 pop_mri_control ();
6527
6528 if (flag_mri)
6529 {
6530 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6531 ++input_line_pointer;
6532 }
6533
6534 demand_empty_rest_of_line ();
6535 }
6536
6537 /* Handle the MRI BREAK pseudo-op. */
6538
6539 static void
6540 s_mri_break (int extent)
6541 {
6542 struct mri_control_info *n;
6543 char *buf;
6544 char ex[2];
6545
6546 n = mri_control_stack;
6547 while (n != NULL
6548 && n->type != mri_for
6549 && n->type != mri_repeat
6550 && n->type != mri_while)
6551 n = n->outer;
6552 if (n == NULL)
6553 {
6554 as_bad (_("break outside of structured loop"));
6555 ignore_rest_of_line ();
6556 return;
6557 }
6558
6559 buf = (char *) xmalloc (20 + strlen (n->bottom));
6560 ex[0] = TOLOWER (extent);
6561 ex[1] = '\0';
6562 sprintf (buf, "bra%s %s", ex, n->bottom);
6563 mri_assemble (buf);
6564 free (buf);
6565
6566 if (flag_mri)
6567 {
6568 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6569 ++input_line_pointer;
6570 }
6571
6572 demand_empty_rest_of_line ();
6573 }
6574
6575 /* Handle the MRI NEXT pseudo-op. */
6576
6577 static void
6578 s_mri_next (int extent)
6579 {
6580 struct mri_control_info *n;
6581 char *buf;
6582 char ex[2];
6583
6584 n = mri_control_stack;
6585 while (n != NULL
6586 && n->type != mri_for
6587 && n->type != mri_repeat
6588 && n->type != mri_while)
6589 n = n->outer;
6590 if (n == NULL)
6591 {
6592 as_bad (_("next outside of structured loop"));
6593 ignore_rest_of_line ();
6594 return;
6595 }
6596
6597 buf = (char *) xmalloc (20 + strlen (n->next));
6598 ex[0] = TOLOWER (extent);
6599 ex[1] = '\0';
6600 sprintf (buf, "bra%s %s", ex, n->next);
6601 mri_assemble (buf);
6602 free (buf);
6603
6604 if (flag_mri)
6605 {
6606 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6607 ++input_line_pointer;
6608 }
6609
6610 demand_empty_rest_of_line ();
6611 }
6612
6613 /* Handle the MRI FOR pseudo-op. */
6614
6615 static void
6616 s_mri_for (int qual)
6617 {
6618 const char *varstart, *varstop;
6619 const char *initstart, *initstop;
6620 const char *endstart, *endstop;
6621 const char *bystart, *bystop;
6622 int up;
6623 int by;
6624 int extent;
6625 struct mri_control_info *n;
6626 char *buf;
6627 char *s;
6628 char ex[2];
6629
6630 /* The syntax is
6631 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6632 */
6633
6634 SKIP_WHITESPACE ();
6635 varstart = input_line_pointer;
6636
6637 /* Look for the '='. */
6638 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6639 && *input_line_pointer != '=')
6640 ++input_line_pointer;
6641 if (*input_line_pointer != '=')
6642 {
6643 as_bad (_("missing ="));
6644 ignore_rest_of_line ();
6645 return;
6646 }
6647
6648 varstop = input_line_pointer;
6649 if (varstop > varstart
6650 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6651 --varstop;
6652
6653 ++input_line_pointer;
6654
6655 initstart = input_line_pointer;
6656
6657 /* Look for TO or DOWNTO. */
6658 up = 1;
6659 initstop = NULL;
6660 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6661 {
6662 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6663 && ! is_part_of_name (input_line_pointer[2]))
6664 {
6665 initstop = input_line_pointer;
6666 input_line_pointer += 2;
6667 break;
6668 }
6669 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6670 && ! is_part_of_name (input_line_pointer[6]))
6671 {
6672 initstop = input_line_pointer;
6673 up = 0;
6674 input_line_pointer += 6;
6675 break;
6676 }
6677 ++input_line_pointer;
6678 }
6679 if (initstop == NULL)
6680 {
6681 as_bad (_("missing to or downto"));
6682 ignore_rest_of_line ();
6683 return;
6684 }
6685 if (initstop > initstart
6686 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6687 --initstop;
6688
6689 SKIP_WHITESPACE ();
6690 endstart = input_line_pointer;
6691
6692 /* Look for BY or DO. */
6693 by = 0;
6694 endstop = NULL;
6695 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6696 {
6697 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6698 && ! is_part_of_name (input_line_pointer[2]))
6699 {
6700 endstop = input_line_pointer;
6701 by = 1;
6702 input_line_pointer += 2;
6703 break;
6704 }
6705 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6706 && (input_line_pointer[2] == '.'
6707 || ! is_part_of_name (input_line_pointer[2])))
6708 {
6709 endstop = input_line_pointer;
6710 input_line_pointer += 2;
6711 break;
6712 }
6713 ++input_line_pointer;
6714 }
6715 if (endstop == NULL)
6716 {
6717 as_bad (_("missing do"));
6718 ignore_rest_of_line ();
6719 return;
6720 }
6721 if (endstop > endstart
6722 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6723 --endstop;
6724
6725 if (! by)
6726 {
6727 bystart = "#1";
6728 bystop = bystart + 2;
6729 }
6730 else
6731 {
6732 SKIP_WHITESPACE ();
6733 bystart = input_line_pointer;
6734
6735 /* Look for DO. */
6736 bystop = NULL;
6737 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6738 {
6739 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6740 && (input_line_pointer[2] == '.'
6741 || ! is_part_of_name (input_line_pointer[2])))
6742 {
6743 bystop = input_line_pointer;
6744 input_line_pointer += 2;
6745 break;
6746 }
6747 ++input_line_pointer;
6748 }
6749 if (bystop == NULL)
6750 {
6751 as_bad (_("missing do"));
6752 ignore_rest_of_line ();
6753 return;
6754 }
6755 if (bystop > bystart
6756 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6757 --bystop;
6758 }
6759
6760 if (*input_line_pointer != '.')
6761 extent = '\0';
6762 else
6763 {
6764 extent = input_line_pointer[1];
6765 input_line_pointer += 2;
6766 }
6767
6768 /* We have fully parsed the FOR operands. Now build the loop. */
6769 n = push_mri_control (mri_for);
6770
6771 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6772
6773 /* Move init,var. */
6774 s = buf;
6775 *s++ = 'm';
6776 *s++ = 'o';
6777 *s++ = 'v';
6778 *s++ = 'e';
6779 if (qual != '\0')
6780 *s++ = TOLOWER (qual);
6781 *s++ = ' ';
6782 memcpy (s, initstart, initstop - initstart);
6783 s += initstop - initstart;
6784 *s++ = ',';
6785 memcpy (s, varstart, varstop - varstart);
6786 s += varstop - varstart;
6787 *s = '\0';
6788 mri_assemble (buf);
6789
6790 colon (n->top);
6791
6792 /* cmp end,var. */
6793 s = buf;
6794 *s++ = 'c';
6795 *s++ = 'm';
6796 *s++ = 'p';
6797 if (qual != '\0')
6798 *s++ = TOLOWER (qual);
6799 *s++ = ' ';
6800 memcpy (s, endstart, endstop - endstart);
6801 s += endstop - endstart;
6802 *s++ = ',';
6803 memcpy (s, varstart, varstop - varstart);
6804 s += varstop - varstart;
6805 *s = '\0';
6806 mri_assemble (buf);
6807
6808 /* bcc bottom. */
6809 ex[0] = TOLOWER (extent);
6810 ex[1] = '\0';
6811 if (up)
6812 sprintf (buf, "blt%s %s", ex, n->bottom);
6813 else
6814 sprintf (buf, "bgt%s %s", ex, n->bottom);
6815 mri_assemble (buf);
6816
6817 /* Put together the add or sub instruction used by ENDF. */
6818 s = buf;
6819 if (up)
6820 strcpy (s, "add");
6821 else
6822 strcpy (s, "sub");
6823 s += 3;
6824 if (qual != '\0')
6825 *s++ = TOLOWER (qual);
6826 *s++ = ' ';
6827 memcpy (s, bystart, bystop - bystart);
6828 s += bystop - bystart;
6829 *s++ = ',';
6830 memcpy (s, varstart, varstop - varstart);
6831 s += varstop - varstart;
6832 *s = '\0';
6833 n->incr = buf;
6834
6835 if (flag_mri)
6836 {
6837 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6838 ++input_line_pointer;
6839 }
6840
6841 demand_empty_rest_of_line ();
6842 }
6843
6844 /* Handle the MRI ENDF pseudo-op. */
6845
6846 static void
6847 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
6848 {
6849 if (mri_control_stack == NULL
6850 || mri_control_stack->type != mri_for)
6851 {
6852 as_bad (_("endf without for"));
6853 ignore_rest_of_line ();
6854 return;
6855 }
6856
6857 colon (mri_control_stack->next);
6858
6859 mri_assemble (mri_control_stack->incr);
6860
6861 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6862 mri_assemble (mri_control_stack->incr);
6863
6864 free (mri_control_stack->incr);
6865
6866 colon (mri_control_stack->bottom);
6867
6868 pop_mri_control ();
6869
6870 if (flag_mri)
6871 {
6872 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6873 ++input_line_pointer;
6874 }
6875
6876 demand_empty_rest_of_line ();
6877 }
6878
6879 /* Handle the MRI REPEAT pseudo-op. */
6880
6881 static void
6882 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
6883 {
6884 struct mri_control_info *n;
6885
6886 n = push_mri_control (mri_repeat);
6887 colon (n->top);
6888 if (flag_mri)
6889 {
6890 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6891 ++input_line_pointer;
6892 }
6893 demand_empty_rest_of_line ();
6894 }
6895
6896 /* Handle the MRI UNTIL pseudo-op. */
6897
6898 static void
6899 s_mri_until (int qual)
6900 {
6901 char *s;
6902
6903 if (mri_control_stack == NULL
6904 || mri_control_stack->type != mri_repeat)
6905 {
6906 as_bad (_("until without repeat"));
6907 ignore_rest_of_line ();
6908 return;
6909 }
6910
6911 colon (mri_control_stack->next);
6912
6913 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6914 ;
6915
6916 parse_mri_control_expression (s, qual, (const char *) NULL,
6917 mri_control_stack->top, '\0');
6918
6919 colon (mri_control_stack->bottom);
6920
6921 input_line_pointer = s;
6922
6923 pop_mri_control ();
6924
6925 if (flag_mri)
6926 {
6927 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6928 ++input_line_pointer;
6929 }
6930
6931 demand_empty_rest_of_line ();
6932 }
6933
6934 /* Handle the MRI WHILE pseudo-op. */
6935
6936 static void
6937 s_mri_while (int qual)
6938 {
6939 char *s;
6940
6941 struct mri_control_info *n;
6942
6943 s = input_line_pointer;
6944 /* We only accept '*' as introduction of comments if preceded by white space
6945 or at first column of a line (I think this can't actually happen here?)
6946 This is important when assembling:
6947 while d0 <ne> 12(a0,d0*2) do
6948 while d0 <ne> #CONST*20 do. */
6949 while (! (is_end_of_line[(unsigned char) *s]
6950 || (flag_mri
6951 && *s == '*'
6952 && (s == input_line_pointer
6953 || *(s-1) == ' '
6954 || *(s-1) == '\t'))))
6955 s++;
6956 --s;
6957 while (*s == ' ' || *s == '\t')
6958 --s;
6959 if (s - input_line_pointer > 1
6960 && s[-1] == '.')
6961 s -= 2;
6962 if (s - input_line_pointer < 2
6963 || strncasecmp (s - 1, "DO", 2) != 0)
6964 {
6965 as_bad (_("missing do"));
6966 ignore_rest_of_line ();
6967 return;
6968 }
6969
6970 n = push_mri_control (mri_while);
6971
6972 colon (n->next);
6973
6974 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6975 s[1] == '.' ? s[2] : '\0');
6976
6977 input_line_pointer = s + 1;
6978 if (*input_line_pointer == '.')
6979 input_line_pointer += 2;
6980
6981 if (flag_mri)
6982 {
6983 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6984 ++input_line_pointer;
6985 }
6986
6987 demand_empty_rest_of_line ();
6988 }
6989
6990 /* Handle the MRI ENDW pseudo-op. */
6991
6992 static void
6993 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
6994 {
6995 char *buf;
6996
6997 if (mri_control_stack == NULL
6998 || mri_control_stack->type != mri_while)
6999 {
7000 as_bad (_("endw without while"));
7001 ignore_rest_of_line ();
7002 return;
7003 }
7004
7005 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
7006 sprintf (buf, "bra %s", mri_control_stack->next);
7007 mri_assemble (buf);
7008 free (buf);
7009
7010 colon (mri_control_stack->bottom);
7011
7012 pop_mri_control ();
7013
7014 if (flag_mri)
7015 {
7016 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7017 ++input_line_pointer;
7018 }
7019
7020 demand_empty_rest_of_line ();
7021 }
7022 \f
7023 /* md_parse_option
7024 Invocation line includes a switch not recognized by the base assembler.
7025 See if it's a processor-specific option. These are:
7026
7027 -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
7028 -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
7029 Select the architecture. Instructions or features not
7030 supported by the selected architecture cause fatal
7031 errors. More than one may be specified. The default is
7032 -m68020 -m68851 -m68881. Note that -m68008 is a synonym
7033 for -m68000, and -m68882 is a synonym for -m68881.
7034 -[A]m[c]no-68851, -[A]m[c]no-68881
7035 Don't accept 688?1 instructions. (The "c" is kind of silly,
7036 so don't use or document it, but that's the way the parsing
7037 works).
7038
7039 -pic Indicates PIC.
7040 -k Indicates PIC. (Sun 3 only.)
7041 --pcrel
7042 Never turn PC-relative branches into absolute jumps.
7043 --bitwise-or
7044 Permit `|' to be used in expressions. */
7045
7046 #ifdef OBJ_ELF
7047 const char *md_shortopts = "lSA:m:kQ:V";
7048 #else
7049 const char *md_shortopts = "lSA:m:k";
7050 #endif
7051
7052 struct option md_longopts[] = {
7053 #define OPTION_PIC (OPTION_MD_BASE)
7054 {"pic", no_argument, NULL, OPTION_PIC},
7055 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7056 {"register-prefix-optional", no_argument, NULL,
7057 OPTION_REGISTER_PREFIX_OPTIONAL},
7058 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7059 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7060 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7061 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7062 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7063 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7064 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7065 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7066 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7067 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7068 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7069 {"pcrel", no_argument, NULL, OPTION_PCREL},
7070 {NULL, no_argument, NULL, 0}
7071 };
7072 size_t md_longopts_size = sizeof (md_longopts);
7073
7074 int
7075 md_parse_option (int c, char *arg)
7076 {
7077 switch (c)
7078 {
7079 case 'l': /* -l means keep external to 2 bit offset
7080 rather than 16 bit one. */
7081 flag_short_refs = 1;
7082 break;
7083
7084 case 'S': /* -S means that jbsr's always turn into
7085 jsr's. */
7086 flag_long_jumps = 1;
7087 break;
7088
7089 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7090 branches into absolute jumps. */
7091 flag_keep_pcrel = 1;
7092 break;
7093
7094 case 'A':
7095 if (*arg == 'm')
7096 arg++;
7097 /* Intentional fall-through. */
7098 case 'm':
7099
7100 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7101 {
7102 int i;
7103 unsigned long arch;
7104
7105 arg += 3;
7106 if (*arg == 'm')
7107 {
7108 arg++;
7109 if (arg[0] == 'c' && arg[1] == '6')
7110 arg++;
7111 }
7112 for (i = 0; i < n_archs; i++)
7113 if (!strcmp (arg, archs[i].name))
7114 break;
7115 if (i == n_archs)
7116 return 0;
7117
7118 arch = archs[i].arch;
7119 if (arch == m68881)
7120 no_68881 = 1;
7121 else if (arch == m68851)
7122 no_68851 = 1;
7123 else
7124 return 0;
7125 }
7126 else
7127 {
7128 int i;
7129
7130 if (arg[0] == 'c' && arg[1] == '6')
7131 arg++;
7132
7133 for (i = 0; i < n_archs; i++)
7134 if (!strcmp (arg, archs[i].name))
7135 {
7136 unsigned long arch = archs[i].arch;
7137
7138 if (cpu_of_arch (arch))
7139 /* It's a cpu spec. */
7140 {
7141 current_architecture &= ~m68000up;
7142 current_architecture |= arch;
7143 current_chip = archs[i].chip;
7144 }
7145 else if (arch == m68881)
7146 {
7147 current_architecture |= m68881;
7148 no_68881 = 0;
7149 }
7150 else if (arch == m68851)
7151 {
7152 current_architecture |= m68851;
7153 no_68851 = 0;
7154 }
7155 else
7156 /* ??? */
7157 abort ();
7158 break;
7159 }
7160 if (i == n_archs)
7161 {
7162 as_bad (_("unrecognized architecture specification `%s'"), arg);
7163 return 0;
7164 }
7165 }
7166 break;
7167
7168 case OPTION_PIC:
7169 case 'k':
7170 flag_want_pic = 1;
7171 break; /* -pic, Position Independent Code. */
7172
7173 case OPTION_REGISTER_PREFIX_OPTIONAL:
7174 flag_reg_prefix_optional = 1;
7175 reg_prefix_optional_seen = 1;
7176 break;
7177
7178 /* -V: SVR4 argument to print version ID. */
7179 case 'V':
7180 print_version_id ();
7181 break;
7182
7183 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7184 should be emitted or not. FIXME: Not implemented. */
7185 case 'Q':
7186 break;
7187
7188 case OPTION_BITWISE_OR:
7189 {
7190 char *n, *t;
7191 const char *s;
7192
7193 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7194 t = n;
7195 for (s = m68k_comment_chars; *s != '\0'; s++)
7196 if (*s != '|')
7197 *t++ = *s;
7198 *t = '\0';
7199 m68k_comment_chars = n;
7200 }
7201 break;
7202
7203 case OPTION_BASE_SIZE_DEFAULT_16:
7204 m68k_index_width_default = SIZE_WORD;
7205 break;
7206
7207 case OPTION_BASE_SIZE_DEFAULT_32:
7208 m68k_index_width_default = SIZE_LONG;
7209 break;
7210
7211 case OPTION_DISP_SIZE_DEFAULT_16:
7212 m68k_rel32 = 0;
7213 m68k_rel32_from_cmdline = 1;
7214 break;
7215
7216 case OPTION_DISP_SIZE_DEFAULT_32:
7217 m68k_rel32 = 1;
7218 m68k_rel32_from_cmdline = 1;
7219 break;
7220
7221 default:
7222 return 0;
7223 }
7224
7225 return 1;
7226 }
7227
7228 void
7229 md_show_usage (FILE *stream)
7230 {
7231 const char *default_cpu = TARGET_CPU;
7232 int i;
7233 unsigned int default_arch;
7234
7235 /* Get the canonical name for the default target CPU. */
7236 if (*default_cpu == 'm')
7237 default_cpu++;
7238 for (i = 0; i < n_archs; i++)
7239 {
7240 if (strcasecmp (default_cpu, archs[i].name) == 0)
7241 {
7242 default_arch = archs[i].arch;
7243 for (i = 0; i < n_archs; i++)
7244 {
7245 if (archs[i].arch == default_arch
7246 && !archs[i].alias)
7247 {
7248 default_cpu = archs[i].name;
7249 break;
7250 }
7251 }
7252 }
7253 }
7254
7255 fprintf (stream, _("\
7256 680X0 options:\n\
7257 -l use 1 word for refs to undefined symbols [default 2]\n\
7258 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
7259 -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
7260 -m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m521x | -m5249 |\n\
7261 -m528x | -m5307 | -m5407 | -m547x | -m548x | -mcfv4 | -mcfv4e\n\
7262 specify variant of 680X0 architecture [default %s]\n\
7263 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
7264 target has/lacks floating-point coprocessor\n\
7265 [default yes for 68020, 68030, and cpu32]\n"),
7266 default_cpu);
7267 fprintf (stream, _("\
7268 -m68851 | -mno-68851\n\
7269 target has/lacks memory-management unit coprocessor\n\
7270 [default yes for 68020 and up]\n\
7271 -pic, -k generate position independent code\n\
7272 -S turn jbsr into jsr\n\
7273 --pcrel never turn PC-relative branches into absolute jumps\n\
7274 --register-prefix-optional\n\
7275 recognize register names without prefix character\n\
7276 --bitwise-or do not treat `|' as a comment character\n"));
7277 fprintf (stream, _("\
7278 --base-size-default-16 base reg without size is 16 bits\n\
7279 --base-size-default-32 base reg without size is 32 bits (default)\n\
7280 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7281 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
7282 }
7283 \f
7284 #ifdef TEST2
7285
7286 /* TEST2: Test md_assemble() */
7287 /* Warning, this routine probably doesn't work anymore. */
7288 int
7289 main (void)
7290 {
7291 struct m68k_it the_ins;
7292 char buf[120];
7293 char *cp;
7294 int n;
7295
7296 m68k_ip_begin ();
7297 for (;;)
7298 {
7299 if (!gets (buf) || !*buf)
7300 break;
7301 if (buf[0] == '|' || buf[1] == '.')
7302 continue;
7303 for (cp = buf; *cp; cp++)
7304 if (*cp == '\t')
7305 *cp = ' ';
7306 if (is_label (buf))
7307 continue;
7308 memset (&the_ins, '\0', sizeof (the_ins));
7309 m68k_ip (&the_ins, buf);
7310 if (the_ins.error)
7311 {
7312 printf (_("Error %s in %s\n"), the_ins.error, buf);
7313 }
7314 else
7315 {
7316 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7317 for (n = 0; n < the_ins.numo; n++)
7318 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7319 printf (" ");
7320 print_the_insn (&the_ins.opcode[0], stdout);
7321 (void) putchar ('\n');
7322 }
7323 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7324 {
7325 if (the_ins.operands[n].error)
7326 {
7327 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7328 continue;
7329 }
7330 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7331 the_ins.operands[n].reg);
7332 if (the_ins.operands[n].b_const)
7333 printf ("Constant: '%.*s', ",
7334 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7335 the_ins.operands[n].b_const);
7336 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7337 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7338 if (the_ins.operands[n].b_iadd)
7339 printf ("Iadd: '%.*s',",
7340 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7341 the_ins.operands[n].b_iadd);
7342 putchar ('\n');
7343 }
7344 }
7345 m68k_ip_end ();
7346 return 0;
7347 }
7348
7349 int
7350 is_label (char *str)
7351 {
7352 while (*str == ' ')
7353 str++;
7354 while (*str && *str != ' ')
7355 str++;
7356 if (str[-1] == ':' || str[1] == '=')
7357 return 1;
7358 return 0;
7359 }
7360
7361 #endif
7362
7363 /* Possible states for relaxation:
7364
7365 0 0 branch offset byte (bra, etc)
7366 0 1 word
7367 0 2 long
7368
7369 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7370 1 1 word
7371 1 2 long
7372
7373 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7374 2 1 word-long
7375 2 2 long-word
7376 2 3 long-long
7377
7378 */
7379
7380 /* We have no need to default values of symbols. */
7381
7382 symbolS *
7383 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7384 {
7385 return 0;
7386 }
7387
7388 /* Round up a section size to the appropriate boundary. */
7389 valueT
7390 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7391 {
7392 #ifdef OBJ_AOUT
7393 #ifdef BFD_ASSEMBLER
7394 /* For a.out, force the section size to be aligned. If we don't do
7395 this, BFD will align it for us, but it will not write out the
7396 final bytes of the section. This may be a bug in BFD, but it is
7397 easier to fix it here since that is how the other a.out targets
7398 work. */
7399 int align;
7400
7401 align = bfd_get_section_alignment (stdoutput, segment);
7402 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7403 #endif
7404 #endif
7405
7406 return size;
7407 }
7408
7409 /* Exactly what point is a PC-relative offset relative TO?
7410 On the 68k, it is relative to the address of the first extension
7411 word. The difference between the addresses of the offset and the
7412 first extension word is stored in fx_pcrel_adjust. */
7413 long
7414 md_pcrel_from (fixS *fixP)
7415 {
7416 int adjust;
7417
7418 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7419 sign extend the value here. */
7420 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7421 if (adjust == 64)
7422 adjust = -1;
7423 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7424 }
7425
7426 #ifndef BFD_ASSEMBLER
7427 #ifdef OBJ_COFF
7428
7429 void
7430 tc_coff_symbol_emit_hook (symbolS *ignore ATTRIBUTE_UNUSED)
7431 {
7432 }
7433
7434 int
7435 tc_coff_sizemachdep (fragS *frag)
7436 {
7437 switch (frag->fr_subtype & 0x3)
7438 {
7439 case BYTE:
7440 return 1;
7441 case SHORT:
7442 return 2;
7443 case LONG:
7444 return 4;
7445 default:
7446 abort ();
7447 return 0;
7448 }
7449 }
7450
7451 #endif
7452 #endif
7453
7454 #ifdef OBJ_ELF
7455 void
7456 m68k_elf_final_processing (void)
7457 {
7458 /* Set file-specific flags if this is a cpu32 processor. */
7459 if (arch_coldfire_fpu (current_architecture))
7460 elf_elfheader (stdoutput)->e_flags |= EF_CFV4E;
7461 if (cpu_of_arch (current_architecture) & cpu32)
7462 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7463 else if ((cpu_of_arch (current_architecture) & m68000up)
7464 && !(cpu_of_arch (current_architecture) & m68020up))
7465 elf_elfheader (stdoutput)->e_flags |= EF_M68000;
7466 }
7467 #endif
7468
7469 int
7470 tc_m68k_regname_to_dw2regnum (const char *regname)
7471 {
7472 unsigned int regnum;
7473 static const char *const regnames[] =
7474 {
7475 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7476 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7477 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7478 "pc"
7479 };
7480
7481 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7482 if (strcmp (regname, regnames[regnum]) == 0)
7483 return regnum;
7484
7485 return -1;
7486 }
7487
7488 void
7489 tc_m68k_frame_initial_instructions (void)
7490 {
7491 static int sp_regno = -1;
7492
7493 if (sp_regno < 0)
7494 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7495
7496 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7497 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7498 }
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