| blob | 7e2c14ea676756afe95c6bac21ab4af5d901d610 |
1 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
3 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
4 (XRELEASE_PREFIX_OPCODE): Likewise.
6 2011-12-08 Andrew Pinski <apinski@cavium.com>
7 Adam Nemet <anemet@caviumnetworks.com>
9 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
10 (INSN_OCTEON2): New macro.
11 (CPU_OCTEON2): New macro.
12 (OPCODE_IS_MEMBER): Add Octeon2.
14 2011-11-29 Andrew Pinski <apinski@cavium.com>
16 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
17 (INSN_OCTEONP): New macro.
18 (CPU_OCTEONP): New macro.
19 (OPCODE_IS_MEMBER): Add Octeon+.
20 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
22 2011-11-01 DJ Delorie <dj@redhat.com>
24 * rl78.h: New file.
26 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
28 * mips.h: Fix a typo in description.
30 2011-09-21 David S. Miller <davem@davemloft.net>
32 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
33 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
34 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
35 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
37 2011-08-09 Chao-ying Fu <fu@mips.com>
38 Maciej W. Rozycki <macro@codesourcery.com>
40 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
41 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
42 (INSN_ASE_MASK): Add the MCU bit.
43 (INSN_MCU): New macro.
44 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
45 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
47 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
49 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
50 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
51 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
52 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
53 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
54 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
55 (INSN2_READ_GPR_MMN): Likewise.
56 (INSN2_READ_FPR_D): Change the bit used.
57 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
58 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
59 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
60 (INSN2_COND_BRANCH): Likewise.
61 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
62 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
63 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
64 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
65 (INSN2_MOD_GPR_MN): Likewise.
67 2011-08-05 David S. Miller <davem@davemloft.net>
69 * sparc.h: Document new format codes '4', '5', and '('.
70 (OPF_LOW4, RS3): New macros.
72 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
74 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
75 order of flags documented.
77 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
79 * mips.h: Clarify the description of microMIPS instruction
80 manipulation macros.
81 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
83 2011-07-24 Chao-ying Fu <fu@mips.com>
84 Maciej W. Rozycki <macro@codesourcery.com>
86 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
87 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
88 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
89 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
90 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
91 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
92 (OP_MASK_RS3, OP_SH_RS3): Likewise.
93 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
94 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
95 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
96 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
97 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
98 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
99 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
100 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
101 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
102 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
103 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
104 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
105 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
106 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
107 (INSN_WRITE_GPR_S): New macro.
108 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
109 (INSN2_READ_FPR_D): Likewise.
110 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
111 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
112 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
113 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
114 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
115 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
116 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
117 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
118 (CPU_MICROMIPS): New macro.
119 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
120 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
121 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
122 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
123 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
124 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
125 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
126 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
127 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
128 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
129 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
130 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
131 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
132 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
133 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
134 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
135 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
136 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
137 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
138 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
139 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
140 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
141 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
142 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
143 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
144 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
145 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
146 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
147 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
148 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
149 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
150 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
151 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
152 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
153 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
154 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
155 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
156 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
157 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
158 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
159 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
160 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
161 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
162 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
163 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
164 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
165 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
166 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
167 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
168 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
169 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
170 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
171 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
172 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
173 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
174 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
175 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
176 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
177 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
178 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
179 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
180 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
181 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
182 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
183 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
184 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
185 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
186 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
187 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
188 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
189 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
190 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
191 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
192 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
193 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
194 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
195 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
196 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
197 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
198 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
199 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
200 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
201 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
202 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
203 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
204 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
205 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
206 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
207 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
208 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
209 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
210 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
211 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
212 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
213 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
214 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
215 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
216 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
217 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
218 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
219 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
220 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
221 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
222 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
223 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
224 (micromips_opcodes): New declaration.
225 (bfd_micromips_num_opcodes): Likewise.
227 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
229 * mips.h (INSN_TRAP): Rename to...
230 (INSN_NO_DELAY_SLOT): ... this.
231 (INSN_SYNC): Remove macro.
233 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
235 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
236 a duplicate of AVR_ISA_SPM.
238 2011-07-01 Nick Clifton <nickc@redhat.com>
240 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
242 2011-06-18 Robin Getz <robin.getz@analog.com>
244 * bfin.h (is_macmod_signed): New func
246 2011-06-18 Mike Frysinger <vapier@gentoo.org>
248 * bfin.h (is_macmod_pmove): Add missing space before func args.
249 (is_macmod_hmove): Likewise.
251 2011-06-13 Walter Lee <walt@tilera.com>
253 * tilegx.h: New file.
254 * tilepro.h: New file.
256 2011-05-31 Paul Brook <paul@codesourcery.com>
258 * arm.h (ARM_ARCH_V7R_IDIV): Define.
260 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
262 * s390.h: Replace S390_OPERAND_REG_EVEN with
263 S390_OPERAND_REG_PAIR.
265 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
267 * s390.h: Add S390_OPCODE_REG_EVEN flag.
269 2011-04-18 Julian Brown <julian@codesourcery.com>
271 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
273 2011-04-11 Dan McDonald <dan@wellkeeper.com>
275 PR gas/12296
276 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
278 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
280 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
281 New instruction set flags.
282 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
284 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
286 * mips.h (M_PREF_AB): New enum value.
288 2011-02-12 Mike Frysinger <vapier@gentoo.org>
290 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
291 M_IU): Define.
292 (is_macmod_pmove, is_macmod_hmove): New functions.
294 2011-02-11 Mike Frysinger <vapier@gentoo.org>
296 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
298 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
300 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
301 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
303 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
305 PR gas/11395
306 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
307 "bb" entries.
309 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
311 PR gas/11395
312 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
314 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
316 * mips.h: Update commentary after last commit.
318 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
320 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
321 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
322 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
324 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
326 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
328 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
330 * mips.h: Fix previous commit.
332 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
334 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
335 (INSN_LOONGSON_3A): Clear bit 31.
337 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
339 PR gas/12198
340 * arm.h (ARM_AEXT_V6M_ONLY): New define.
341 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
342 (ARM_ARCH_V6M_ONLY): New define.
344 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
346 * mips.h (INSN_LOONGSON_3A): Defined.
347 (CPU_LOONGSON_3A): Defined.
348 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
350 2010-10-09 Matt Rice <ratmice@gmail.com>
352 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
353 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
355 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
357 * arm.h (ARM_EXT_VIRT): New define.
358 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
359 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
360 Extensions.
362 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
364 * arm.h (ARM_AEXT_ADIV): New define.
365 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
367 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
369 * arm.h (ARM_EXT_OS): New define.
370 (ARM_AEXT_V6SM): Likewise.
371 (ARM_ARCH_V6SM): Likewise.
373 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
375 * arm.h (ARM_EXT_MP): Add.
376 (ARM_ARCH_V7A_MP): Likewise.
378 2010-09-22 Mike Frysinger <vapier@gentoo.org>
380 * bfin.h: Declare pseudoChr structs/defines.
382 2010-09-21 Mike Frysinger <vapier@gentoo.org>
384 * bfin.h: Strip trailing whitespace.
386 2010-07-29 DJ Delorie <dj@redhat.com>
388 * rx.h (RX_Operand_Type): Add TwoReg.
389 (RX_Opcode_ID): Remove ediv and ediv2.
391 2010-07-27 DJ Delorie <dj@redhat.com>
393 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
395 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
396 Ina Pandit <ina.pandit@kpitcummins.com>
398 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
399 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
400 PROCESSOR_V850E2_ALL.
401 Remove PROCESSOR_V850EA support.
402 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
403 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
404 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
405 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
406 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
407 V850_OPERAND_PERCENT.
408 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
409 V850_NOT_R0.
410 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
411 and V850E_PUSH_POP
413 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
415 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
416 (MIPS16_INSN_BRANCH): Rename to...
417 (MIPS16_INSN_COND_BRANCH): ... this.
419 2010-07-03 Alan Modra <amodra@gmail.com>
421 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
422 Renumber other PPC_OPCODE defines.
424 2010-07-03 Alan Modra <amodra@gmail.com>
426 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
428 2010-06-29 Alan Modra <amodra@gmail.com>
430 * maxq.h: Delete file.
432 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
434 * ppc.h (PPC_OPCODE_E500): Define.
436 2010-05-26 Catherine Moore <clm@codesourcery.com>
438 * opcode/mips.h (INSN_MIPS16): Remove.
440 2010-04-21 Joseph Myers <joseph@codesourcery.com>
442 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
444 2010-04-15 Nick Clifton <nickc@redhat.com>
446 * alpha.h: Update copyright notice to use GPLv3.
447 * arc.h: Likewise.
448 * arm.h: Likewise.
449 * avr.h: Likewise.
450 * bfin.h: Likewise.
451 * cgen.h: Likewise.
452 * convex.h: Likewise.
453 * cr16.h: Likewise.
454 * cris.h: Likewise.
455 * crx.h: Likewise.
456 * d10v.h: Likewise.
457 * d30v.h: Likewise.
458 * dlx.h: Likewise.
459 * h8300.h: Likewise.
460 * hppa.h: Likewise.
461 * i370.h: Likewise.
462 * i386.h: Likewise.
463 * i860.h: Likewise.
464 * i960.h: Likewise.
465 * ia64.h: Likewise.
466 * m68hc11.h: Likewise.
467 * m68k.h: Likewise.
468 * m88k.h: Likewise.
469 * maxq.h: Likewise.
470 * mips.h: Likewise.
471 * mmix.h: Likewise.
472 * mn10200.h: Likewise.
473 * mn10300.h: Likewise.
474 * msp430.h: Likewise.
475 * np1.h: Likewise.
476 * ns32k.h: Likewise.
477 * or32.h: Likewise.
478 * pdp11.h: Likewise.
479 * pj.h: Likewise.
480 * pn.h: Likewise.
481 * ppc.h: Likewise.
482 * pyr.h: Likewise.
483 * rx.h: Likewise.
484 * s390.h: Likewise.
485 * score-datadep.h: Likewise.
486 * score-inst.h: Likewise.
487 * sparc.h: Likewise.
488 * spu-insns.h: Likewise.
489 * spu.h: Likewise.
490 * tic30.h: Likewise.
491 * tic4x.h: Likewise.
492 * tic54x.h: Likewise.
493 * tic80.h: Likewise.
494 * v850.h: Likewise.
495 * vax.h: Likewise.
497 2010-03-25 Joseph Myers <joseph@codesourcery.com>
499 * tic6x-control-registers.h, tic6x-insn-formats.h,
500 tic6x-opcode-table.h, tic6x.h: New.
502 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
504 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
506 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
508 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
510 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
512 * ia64.h (ia64_find_opcode): Remove argument name.
513 (ia64_find_next_opcode): Likewise.
514 (ia64_dis_opcode): Likewise.
515 (ia64_free_opcode): Likewise.
516 (ia64_find_dependency): Likewise.
518 2009-11-22 Doug Evans <dje@sebabeach.org>
520 * cgen.h: Include bfd_stdint.h.
521 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
523 2009-11-18 Paul Brook <paul@codesourcery.com>
525 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
527 2009-11-17 Paul Brook <paul@codesourcery.com>
528 Daniel Jacobowitz <dan@codesourcery.com>
530 * arm.h (ARM_EXT_V6_DSP): Define.
531 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
532 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
534 2009-11-04 DJ Delorie <dj@redhat.com>
536 * rx.h (rx_decode_opcode) (mvtipl): Add.
537 (mvtcp, mvfcp, opecp): Remove.
539 2009-11-02 Paul Brook <paul@codesourcery.com>
541 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
542 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
543 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
544 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
545 FPU_ARCH_NEON_VFP_V4): Define.
547 2009-10-23 Doug Evans <dje@sebabeach.org>
549 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
550 * cgen.h: Update. Improve multi-inclusion macro name.
552 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
554 * ppc.h (PPC_OPCODE_476): Define.
556 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
558 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
560 2009-09-29 DJ Delorie <dj@redhat.com>
562 * rx.h: New file.
564 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
566 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
568 2009-09-21 Ben Elliston <bje@au.ibm.com>
570 * ppc.h (PPC_OPCODE_PPCA2): New.
572 2009-09-05 Martin Thuresson <martin@mtme.org>
574 * ia64.h (struct ia64_operand): Renamed member class to op_class.
576 2009-08-29 Martin Thuresson <martin@mtme.org>
578 * tic30.h (template): Rename type template to
579 insn_template. Updated code to use new name.
580 * tic54x.h (template): Rename type template to
581 insn_template.
583 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
585 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
587 2009-06-11 Anthony Green <green@moxielogic.com>
589 * moxie.h (MOXIE_F3_PCREL): Define.
590 (moxie_form3_opc_info): Grow.
592 2009-06-06 Anthony Green <green@moxielogic.com>
594 * moxie.h (MOXIE_F1_M): Define.
596 2009-04-15 Anthony Green <green@moxielogic.com>
598 * moxie.h: Created.
600 2009-04-06 DJ Delorie <dj@redhat.com>
602 * h8300.h: Add relaxation attributes to MOVA opcodes.
604 2009-03-10 Alan Modra <amodra@bigpond.net.au>
606 * ppc.h (ppc_parse_cpu): Declare.
608 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
610 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
611 and _IMM11 for mbitclr and mbitset.
612 * score-datadep.h: Update dependency information.
614 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
616 * ppc.h (PPC_OPCODE_POWER7): New.
618 2009-02-06 Doug Evans <dje@google.com>
620 * i386.h: Add comment regarding sse* insns and prefixes.
622 2009-02-03 Sandip Matte <sandip@rmicorp.com>
624 * mips.h (INSN_XLR): Define.
625 (INSN_CHIP_MASK): Update.
626 (CPU_XLR): Define.
627 (OPCODE_IS_MEMBER): Update.
628 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
630 2009-01-28 Doug Evans <dje@google.com>
632 * opcode/i386.h: Add multiple inclusion protection.
633 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
634 (EDI_REG_NUM): New macros.
635 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
636 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
637 (REX_PREFIX_P): New macro.
639 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
641 * ppc.h (struct powerpc_opcode): New field "deprecated".
642 (PPC_OPCODE_NOPOWER4): Delete.
644 2008-11-28 Joshua Kinard <kumba@gentoo.org>
646 * mips.h: Define CPU_R14000, CPU_R16000.
647 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
649 2008-11-18 Catherine Moore <clm@codesourcery.com>
651 * arm.h (FPU_NEON_FP16): New.
652 (FPU_ARCH_NEON_FP16): New.
654 2008-11-06 Chao-ying Fu <fu@mips.com>
656 * mips.h: Doucument '1' for 5-bit sync type.
658 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
660 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
661 IA64_RS_CR.
663 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
665 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
667 2008-07-30 Michael J. Eager <eager@eagercon.com>
669 * ppc.h (PPC_OPCODE_405): Define.
670 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
672 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
674 * ppc.h (ppc_cpu_t): New typedef.
675 (struct powerpc_opcode <flags>): Use it.
676 (struct powerpc_operand <insert, extract>): Likewise.
677 (struct powerpc_macro <flags>): Likewise.
679 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
681 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
682 Update comment before MIPS16 field descriptors to mention MIPS16.
683 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
684 BBIT.
685 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
686 New bit masks and shift counts for cins and exts.
688 * mips.h: Document new field descriptors +Q.
689 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
691 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
693 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
694 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
696 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
698 * ppc.h: (PPC_OPCODE_E500MC): New.
700 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
702 * i386.h (MAX_OPERANDS): Set to 5.
703 (MAX_MNEM_SIZE): Changed to 20.
705 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
707 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
709 2008-03-09 Paul Brook <paul@codesourcery.com>
711 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
713 2008-03-04 Paul Brook <paul@codesourcery.com>
715 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
716 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
717 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
719 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
720 Nick Clifton <nickc@redhat.com>
722 PR 3134
723 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
724 with a 32-bit displacement but without the top bit of the 4th byte
725 set.
727 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
729 * cr16.h (cr16_num_optab): Declared.
731 2008-02-14 Hakan Ardo <hakan@debian.org>
733 PR gas/2626
734 * avr.h (AVR_ISA_2xxe): Define.
736 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
738 * mips.h: Update copyright.
739 (INSN_CHIP_MASK): New macro.
740 (INSN_OCTEON): New macro.
741 (CPU_OCTEON): New macro.
742 (OPCODE_IS_MEMBER): Handle Octeon instructions.
744 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
746 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
748 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
750 * avr.h (AVR_ISA_USB162): Add new opcode set.
751 (AVR_ISA_AVR3): Likewise.
753 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
755 * mips.h (INSN_LOONGSON_2E): New.
756 (INSN_LOONGSON_2F): New.
757 (CPU_LOONGSON_2E): New.
758 (CPU_LOONGSON_2F): New.
759 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
761 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
763 * mips.h (INSN_ISA*): Redefine certain values as an
764 enumeration. Update comments.
765 (mips_isa_table): New.
766 (ISA_MIPS*): Redefine to match enumeration.
767 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
768 values.
770 2007-08-08 Ben Elliston <bje@au.ibm.com>
772 * ppc.h (PPC_OPCODE_PPCPS): New.
774 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
776 * m68k.h: Document j K & E.
778 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
780 * cr16.h: New file for CR16 target.
782 2007-05-02 Alan Modra <amodra@bigpond.net.au>
784 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
786 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
788 * m68k.h (mcfisa_c): New.
789 (mcfusp, mcf_mask): Adjust.
791 2007-04-20 Alan Modra <amodra@bigpond.net.au>
793 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
794 (num_powerpc_operands): Declare.
795 (PPC_OPERAND_SIGNED et al): Redefine as hex.
796 (PPC_OPERAND_PLUS1): Define.
798 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
800 * i386.h (REX_MODE64): Renamed to ...
801 (REX_W): This.
802 (REX_EXTX): Renamed to ...
803 (REX_R): This.
804 (REX_EXTY): Renamed to ...
805 (REX_X): This.
806 (REX_EXTZ): Renamed to ...
807 (REX_B): This.
809 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
811 * i386.h: Add entries from config/tc-i386.h and move tables
812 to opcodes/i386-opc.h.
814 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
816 * i386.h (FloatDR): Removed.
817 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
819 2007-03-01 Alan Modra <amodra@bigpond.net.au>
821 * spu-insns.h: Add soma double-float insns.
823 2007-02-20 Thiemo Seufer <ths@mips.com>
824 Chao-Ying Fu <fu@mips.com>
826 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
827 (INSN_DSPR2): Add flag for DSP R2 instructions.
828 (M_BALIGN): New macro.
830 2007-02-14 Alan Modra <amodra@bigpond.net.au>
832 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
833 and Seg3ShortFrom with Shortform.
835 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
837 PR gas/4027
838 * i386.h (i386_optab): Put the real "test" before the pseudo
839 one.
841 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
843 * m68k.h (m68010up): OR fido_a.
845 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
847 * m68k.h (fido_a): New.
849 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
851 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
852 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
853 values.
855 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
857 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
859 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
861 * score-inst.h (enum score_insn_type): Add Insn_internal.
863 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
864 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
865 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
866 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
867 Alan Modra <amodra@bigpond.net.au>
869 * spu-insns.h: New file.
870 * spu.h: New file.
872 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
874 * ppc.h (PPC_OPCODE_CELL): Define.
876 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
878 * i386.h : Modify opcode to support for the change in POPCNT opcode
879 in amdfam10 architecture.
881 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
883 * i386.h: Replace CpuMNI with CpuSSSE3.
885 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
886 Joseph Myers <joseph@codesourcery.com>
887 Ian Lance Taylor <ian@wasabisystems.com>
888 Ben Elliston <bje@wasabisystems.com>
890 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
892 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
894 * score-datadep.h: New file.
895 * score-inst.h: New file.
897 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
899 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
900 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
901 movdq2q and movq2dq.
903 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
904 Michael Meissner <michael.meissner@amd.com>
906 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
908 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
910 * i386.h (i386_optab): Add "nop" with memory reference.
912 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
914 * i386.h (i386_optab): Update comment for 64bit NOP.
916 2006-06-06 Ben Elliston <bje@au.ibm.com>
917 Anton Blanchard <anton@samba.org>
919 * ppc.h (PPC_OPCODE_POWER6): Define.
920 Adjust whitespace.
922 2006-06-05 Thiemo Seufer <ths@mips.com>
924 * mips.h: Improve description of MT flags.
926 2006-05-25 Richard Sandiford <richard@codesourcery.com>
928 * m68k.h (mcf_mask): Define.
930 2006-05-05 Thiemo Seufer <ths@mips.com>
931 David Ung <davidu@mips.com>
933 * mips.h (enum): Add macro M_CACHE_AB.
935 2006-05-04 Thiemo Seufer <ths@mips.com>
936 Nigel Stephens <nigel@mips.com>
937 David Ung <davidu@mips.com>
939 * mips.h: Add INSN_SMARTMIPS define.
941 2006-04-30 Thiemo Seufer <ths@mips.com>
942 David Ung <davidu@mips.com>
944 * mips.h: Defines udi bits and masks. Add description of
945 characters which may appear in the args field of udi
946 instructions.
948 2006-04-26 Thiemo Seufer <ths@networkno.de>
950 * mips.h: Improve comments describing the bitfield instruction
951 fields.
953 2006-04-26 Julian Brown <julian@codesourcery.com>
955 * arm.h (FPU_VFP_EXT_V3): Define constant.
956 (FPU_NEON_EXT_V1): Likewise.
957 (FPU_VFP_HARD): Update.
958 (FPU_VFP_V3): Define macro.
959 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
961 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
963 * avr.h (AVR_ISA_PWMx): New.
965 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
967 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
968 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
969 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
970 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
971 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
973 2006-03-10 Paul Brook <paul@codesourcery.com>
975 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
977 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
979 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
980 first. Correct mask of bb "B" opcode.
982 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
984 * i386.h (i386_optab): Support Intel Merom New Instructions.
986 2006-02-24 Paul Brook <paul@codesourcery.com>
988 * arm.h: Add V7 feature bits.
990 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
992 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
994 2006-01-31 Paul Brook <paul@codesourcery.com>
995 Richard Earnshaw <rearnsha@arm.com>
997 * arm.h: Use ARM_CPU_FEATURE.
998 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
999 (arm_feature_set): Change to a structure.
1000 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1001 ARM_FEATURE): New macros.
1003 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1005 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1006 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1007 (ADD_PC_INCR_OPCODE): Don't define.
1009 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1011 PR gas/1874
1012 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1014 2005-11-14 David Ung <davidu@mips.com>
1016 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1017 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1018 save/restore encoding of the args field.
1020 2005-10-28 Dave Brolley <brolley@redhat.com>
1022 Contribute the following changes:
1023 2005-02-16 Dave Brolley <brolley@redhat.com>
1025 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1026 cgen_isa_mask_* to cgen_bitset_*.
1027 * cgen.h: Likewise.
1029 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1031 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1032 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1033 (CGEN_CPU_TABLE): Make isas a ponter.
1035 2003-09-29 Dave Brolley <brolley@redhat.com>
1037 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1038 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1039 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1041 2002-12-13 Dave Brolley <brolley@redhat.com>
1043 * cgen.h (symcat.h): #include it.
1044 (cgen-bitset.h): #include it.
1045 (CGEN_ATTR_VALUE_TYPE): Now a union.
1046 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1047 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1048 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1049 * cgen-bitset.h: New file.
1051 2005-09-30 Catherine Moore <clm@cm00re.com>
1053 * bfin.h: New file.
1055 2005-10-24 Jan Beulich <jbeulich@novell.com>
1057 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1058 indirect operands.
1060 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1062 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1063 Add FLAG_STRICT to pa10 ftest opcode.
1065 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1067 * hppa.h (pa_opcodes): Remove lha entries.
1069 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1071 * hppa.h (FLAG_STRICT): Revise comment.
1072 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1073 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1074 entries for "fdc".
1076 2005-09-30 Catherine Moore <clm@cm00re.com>
1078 * bfin.h: New file.
1080 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1082 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1084 2005-09-06 Chao-ying Fu <fu@mips.com>
1086 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1087 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1088 define.
1089 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1090 (INSN_ASE_MASK): Update to include INSN_MT.
1091 (INSN_MT): New define for MT ASE.
1093 2005-08-25 Chao-ying Fu <fu@mips.com>
1095 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1096 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1097 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1098 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1099 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1100 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1101 instructions.
1102 (INSN_DSP): New define for DSP ASE.
1104 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1106 * a29k.h: Delete.
1108 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1110 * ppc.h (PPC_OPCODE_E300): Define.
1112 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1114 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1116 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1118 PR gas/336
1119 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1120 and pitlb.
1122 2005-07-27 Jan Beulich <jbeulich@novell.com>
1124 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1125 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1126 Add movq-s as 64-bit variants of movd-s.
1128 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1130 * hppa.h: Fix punctuation in comment.
1132 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1133 implicit space-register addressing. Set space-register bits on opcodes
1134 using implicit space-register addressing. Add various missing pa20
1135 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1136 space-register addressing. Use "fE" instead of "fe" in various
1137 fstw opcodes.
1139 2005-07-18 Jan Beulich <jbeulich@novell.com>
1141 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1143 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1145 * i386.h (i386_optab): Support Intel VMX Instructions.
1147 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1149 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1151 2005-07-05 Jan Beulich <jbeulich@novell.com>
1153 * i386.h (i386_optab): Add new insns.
1155 2005-07-01 Nick Clifton <nickc@redhat.com>
1157 * sparc.h: Add typedefs to structure declarations.
1159 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1161 PR 1013
1162 * i386.h (i386_optab): Update comments for 64bit addressing on
1163 mov. Allow 64bit addressing for mov and movq.
1165 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1167 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1168 respectively, in various floating-point load and store patterns.
1170 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1172 * hppa.h (FLAG_STRICT): Correct comment.
1173 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1174 PA 2.0 mneumonics when equivalent. Entries with cache control
1175 completers now require PA 1.1. Adjust whitespace.
1177 2005-05-19 Anton Blanchard <anton@samba.org>
1179 * ppc.h (PPC_OPCODE_POWER5): Define.
1181 2005-05-10 Nick Clifton <nickc@redhat.com>
1183 * Update the address and phone number of the FSF organization in
1184 the GPL notices in the following files:
1185 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1186 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1187 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1188 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1189 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1190 tic54x.h, tic80.h, v850.h, vax.h
1192 2005-05-09 Jan Beulich <jbeulich@novell.com>
1194 * i386.h (i386_optab): Add ht and hnt.
1196 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1198 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1199 Add xcrypt-ctr. Provide aliases without hyphens.
1201 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1203 Moved from ../ChangeLog
1205 2005-04-12 Paul Brook <paul@codesourcery.com>
1206 * m88k.h: Rename psr macros to avoid conflicts.
1208 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1209 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1210 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1211 and ARM_ARCH_V6ZKT2.
1213 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1214 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1215 Remove redundant instruction types.
1216 (struct argument): X_op - new field.
1217 (struct cst4_entry): Remove.
1218 (no_op_insn): Declare.
1220 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1221 * crx.h (enum argtype): Rename types, remove unused types.
1223 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1224 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1225 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1226 (enum operand_type): Rearrange operands, edit comments.
1227 replace us<N> with ui<N> for unsigned immediate.
1228 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1229 displacements (respectively).
1230 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1231 (instruction type): Add NO_TYPE_INS.
1232 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1233 (operand_entry): New field - 'flags'.
1234 (operand flags): New.
1236 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1237 * crx.h (operand_type): Remove redundant types i3, i4,
1238 i5, i8, i12.
1239 Add new unsigned immediate types us3, us4, us5, us16.
1241 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1243 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1244 adjust them accordingly.
1246 2005-04-01 Jan Beulich <jbeulich@novell.com>
1248 * i386.h (i386_optab): Add rdtscp.
1250 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1252 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1253 between memory and segment register. Allow movq for moving between
1254 general-purpose register and segment register.
1256 2005-02-09 Jan Beulich <jbeulich@novell.com>
1258 PR gas/707
1259 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1260 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1261 fnstsw.
1263 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1265 * m68k.h (m68008, m68ec030, m68882): Remove.
1266 (m68k_mask): New.
1267 (cpu_m68k, cpu_cf): New.
1268 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1269 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1271 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1273 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1274 * cgen.h (enum cgen_parse_operand_type): Add
1275 CGEN_PARSE_OPERAND_SYMBOLIC.
1277 2005-01-21 Fred Fish <fnf@specifixinc.com>
1279 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1280 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1281 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1283 2005-01-19 Fred Fish <fnf@specifixinc.com>
1285 * mips.h (struct mips_opcode): Add new pinfo2 member.
1286 (INSN_ALIAS): New define for opcode table entries that are
1287 specific instances of another entry, such as 'move' for an 'or'
1288 with a zero operand.
1289 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1290 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1292 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1294 * mips.h (CPU_RM9000): Define.
1295 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1297 2004-11-25 Jan Beulich <jbeulich@novell.com>
1299 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1300 to/from test registers are illegal in 64-bit mode. Add missing
1301 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1302 (previously one had to explicitly encode a rex64 prefix). Re-enable
1303 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1304 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1306 2004-11-23 Jan Beulich <jbeulich@novell.com>
1308 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1309 available only with SSE2. Change the MMX additions introduced by SSE
1310 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1311 instructions by their now designated identifier (since combining i686
1312 and 3DNow! does not really imply 3DNow!A).
1314 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1316 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1317 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1319 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1320 Vineet Sharma <vineets@noida.hcltech.com>
1322 * maxq.h: New file: Disassembly information for the maxq port.
1324 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1326 * i386.h (i386_optab): Put back "movzb".
1328 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1330 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1331 comments. Remove member cris_ver_sim. Add members
1332 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1333 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1334 (struct cris_support_reg, struct cris_cond15): New types.
1335 (cris_conds15): Declare.
1336 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1337 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1338 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1339 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1340 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1341 SIZE_FIELD_UNSIGNED.
1343 2004-11-04 Jan Beulich <jbeulich@novell.com>
1345 * i386.h (sldx_Suf): Remove.
1346 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1347 (q_FP): Define, implying no REX64.
1348 (x_FP, sl_FP): Imply FloatMF.
1349 (i386_optab): Split reg and mem forms of moving from segment registers
1350 so that the memory forms can ignore the 16-/32-bit operand size
1351 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1352 all non-floating-point instructions. Unite 32- and 64-bit forms of
1353 movsx, movzx, and movd. Adjust floating point operations for the above
1354 changes to the *FP macros. Add DefaultSize to floating point control
1355 insns operating on larger memory ranges. Remove left over comments
1356 hinting at certain insns being Intel-syntax ones where the ones
1357 actually meant are already gone.
1359 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1361 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1362 instruction type.
1364 2004-09-30 Paul Brook <paul@codesourcery.com>
1366 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1367 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1369 2004-09-11 Theodore A. Roth <troth@openavr.org>
1371 * avr.h: Add support for
1372 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1374 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1376 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1378 2004-08-24 Dmitry Diky <diwil@spec.ru>
1380 * msp430.h (msp430_opc): Add new instructions.
1381 (msp430_rcodes): Declare new instructions.
1382 (msp430_hcodes): Likewise..
1384 2004-08-13 Nick Clifton <nickc@redhat.com>
1386 PR/301
1387 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1388 processors.
1390 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1392 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1394 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1396 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1398 2004-07-21 Jan Beulich <jbeulich@novell.com>
1400 * i386.h: Adjust instruction descriptions to better match the
1401 specification.
1403 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1405 * arm.h: Remove all old content. Replace with architecture defines
1406 from gas/config/tc-arm.c.
1408 2004-07-09 Andreas Schwab <schwab@suse.de>
1410 * m68k.h: Fix comment.
1412 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1414 * crx.h: New file.
1416 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1418 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1420 2004-05-24 Peter Barada <peter@the-baradas.com>
1422 * m68k.h: Add 'size' to m68k_opcode.
1424 2004-05-05 Peter Barada <peter@the-baradas.com>
1426 * m68k.h: Switch from ColdFire chip name to core variant.
1428 2004-04-22 Peter Barada <peter@the-baradas.com>
1430 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1431 descriptions for new EMAC cases.
1432 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1433 handle Motorola MAC syntax.
1434 Allow disassembly of ColdFire V4e object files.
1436 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1438 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1440 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1442 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1444 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1446 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1448 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1450 * i386.h (i386_optab): Added xstore/xcrypt insns.
1452 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1454 * h8300.h (32bit ldc/stc): Add relaxing support.
1456 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1458 * h8300.h (BITOP): Pass MEMRELAX flag.
1460 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1462 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1463 except for the H8S.
1465 For older changes see ChangeLog-9103
1466 \f
1467 Local Variables:
1468 mode: change-log
1469 left-margin: 8
1470 fill-column: 74
1471 version-control: never
1472 End: