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[binutils.git] / include / opcode / tic4x.h
blob6f16fcb404ee03b02e191ae268bf8f0f81e58638
1 /* Table of opcodes for the Texas Instruments TMS320C[34]X family.
2
3 Copyright (C) 2002, 2003, 2010 Free Software Foundation.
4
5 Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
22 #define IS_CPU_TIC3X(v) ((v) == 30 || (v) == 31 || (v) == 32 || (v) == 33)
23 #define IS_CPU_TIC4X(v) ((v) == 0 || (v) == 40 || (v) == 44)
24
25 /* Define some bitfield extraction/insertion macros. */
26 #define EXTR(inst, m, l) ((inst) << (31 - (m)) >> (31 - ((m) - (l))))
27 #define EXTRU(inst, m, l) EXTR ((unsigned long)(inst), (m), (l))
28 #define EXTRS(inst, m, l) EXTR ((long)(inst), (m), (l))
29 #define INSERTU(inst, val, m, l) (inst |= ((val) << (l)))
30 #define INSERTS(inst, val, m, l) INSERTU (inst, ((val) & ((1 << ((m) - (l) + 1)) - 1)), m, l)
31
32 /* Define register numbers. */
33 typedef enum
34 {
35 REG_R0, REG_R1, REG_R2, REG_R3,
36 REG_R4, REG_R5, REG_R6, REG_R7,
37 REG_AR0, REG_AR1, REG_AR2, REG_AR3,
38 REG_AR4, REG_AR5, REG_AR6, REG_AR7,
39 REG_DP, REG_IR0, REG_IR1, REG_BK,
40 REG_SP, REG_ST, REG_DIE, REG_IIE,
41 REG_IIF, REG_RS, REG_RE, REG_RC,
42 REG_R8, REG_R9, REG_R10, REG_R11,
43 REG_IVTP, REG_TVTP
44 }
45 c4x_reg_t;
46
47 /* Note that the actual register numbers for IVTP is 0 and TVTP is 1. */
48
49 #define REG_IE REG_DIE /* C3x only */
50 #define REG_IF REG_IIE /* C3x only */
51 #define REG_IOF REG_IIF /* C3x only */
52
53 #define TIC3X_REG_MAX REG_RC
54 #define TIC4X_REG_MAX REG_TVTP
55
56 /* Register table size including C4x expansion regs. */
57 #define REG_TABLE_SIZE (TIC4X_REG_MAX + 1)
58
59 struct tic4x_register
60 {
61 char * name;
62 unsigned long regno;
63 };
64
65 typedef struct tic4x_register tic4x_register_t;
66
67 /* We could store register synonyms here. */
68 static const tic4x_register_t tic3x_registers[] =
69 {
70 {"f0", REG_R0},
71 {"r0", REG_R0},
72 {"f1", REG_R1},
73 {"r1", REG_R1},
74 {"f2", REG_R2},
75 {"r2", REG_R2},
76 {"f3", REG_R3},
77 {"r3", REG_R3},
78 {"f4", REG_R4},
79 {"r4", REG_R4},
80 {"f5", REG_R5},
81 {"r5", REG_R5},
82 {"f6", REG_R6},
83 {"r6", REG_R6},
84 {"f7", REG_R7},
85 {"r7", REG_R7},
86 {"ar0", REG_AR0},
87 {"ar1", REG_AR1},
88 {"ar2", REG_AR2},
89 {"ar3", REG_AR3},
90 {"ar4", REG_AR4},
91 {"ar5", REG_AR5},
92 {"ar6", REG_AR6},
93 {"ar7", REG_AR7},
94 {"dp", REG_DP},
95 {"ir0", REG_IR0},
96 {"ir1", REG_IR1},
97 {"bk", REG_BK},
98 {"sp", REG_SP},
99 {"st", REG_ST},
100 {"ie", REG_IE},
101 {"if", REG_IF},
102 {"iof", REG_IOF},
103 {"rs", REG_RS},
104 {"re", REG_RE},
105 {"rc", REG_RC},
106 {"", 0}
107 };
108
109 const unsigned int tic3x_num_registers = (((sizeof tic3x_registers) / (sizeof tic3x_registers[0])) - 1);
110
111 /* Define C4x registers in addition to C3x registers. */
112 static const tic4x_register_t tic4x_registers[] =
113 {
114 {"die", REG_DIE}, /* Clobbers C3x REG_IE */
115 {"iie", REG_IIE}, /* Clobbers C3x REG_IF */
116 {"iif", REG_IIF}, /* Clobbers C3x REG_IOF */
117 {"f8", REG_R8},
118 {"r8", REG_R8},
119 {"f9", REG_R9},
120 {"r9", REG_R9},
121 {"f10", REG_R10},
122 {"r10", REG_R10},
123 {"f11", REG_R11},
124 {"r11", REG_R11},
125 {"ivtp", REG_IVTP},
126 {"tvtp", REG_TVTP},
127 {"", 0}
128 };
129
130 const unsigned int tic4x_num_registers = (((sizeof tic4x_registers) / (sizeof tic4x_registers[0])) - 1);
131
132 struct tic4x_cond
133 {
134 char * name;
135 unsigned long cond;
136 };
137
138 typedef struct tic4x_cond tic4x_cond_t;
139
140 /* Define conditional branch/load suffixes. Put desired form for
141 disassembler last. */
142 static const tic4x_cond_t tic4x_conds[] =
143 {
144 { "u", 0x00 },
145 { "c", 0x01 }, { "lo", 0x01 },
146 { "ls", 0x02 },
147 { "hi", 0x03 },
148 { "nc", 0x04 }, { "hs", 0x04 },
149 { "z", 0x05 }, { "eq", 0x05 },
150 { "nz", 0x06 }, { "ne", 0x06 },
151 { "n", 0x07 }, { "l", 0x07 }, { "lt", 0x07 },
152 { "le", 0x08 },
153 { "p", 0x09 }, { "gt", 0x09 },
154 { "nn", 0x0a }, { "ge", 0x0a },
155 { "nv", 0x0c },
156 { "v", 0x0d },
157 { "nuf", 0x0e },
158 { "uf", 0x0f },
159 { "nlv", 0x10 },
160 { "lv", 0x11 },
161 { "nluf", 0x12 },
162 { "luf", 0x13 },
163 { "zuf", 0x14 },
164 /* Dummy entry, not included in num_conds. This
165 lets code examine entry i+1 without checking
166 if we've run off the end of the table. */
167 { "", 0x0}
168 };
169
170 const unsigned int tic4x_num_conds = (((sizeof tic4x_conds) / (sizeof tic4x_conds[0])) - 1);
171
172 struct tic4x_indirect
173 {
174 char * name;
175 unsigned long modn;
176 };
177
178 typedef struct tic4x_indirect tic4x_indirect_t;
179
180 /* Define indirect addressing modes where:
181 d displacement (signed)
182 y ir0
183 z ir1 */
184
185 static const tic4x_indirect_t tic4x_indirects[] =
186 {
187 { "*+a(d)", 0x00 },
188 { "*-a(d)", 0x01 },
189 { "*++a(d)", 0x02 },
190 { "*--a(d)", 0x03 },
191 { "*a++(d)", 0x04 },
192 { "*a--(d)", 0x05 },
193 { "*a++(d)%", 0x06 },
194 { "*a--(d)%", 0x07 },
195 { "*+a(y)", 0x08 },
196 { "*-a(y)", 0x09 },
197 { "*++a(y)", 0x0a },
198 { "*--a(y)", 0x0b },
199 { "*a++(y)", 0x0c },
200 { "*a--(y)", 0x0d },
201 { "*a++(y)%", 0x0e },
202 { "*a--(y)%", 0x0f },
203 { "*+a(z)", 0x10 },
204 { "*-a(z)", 0x11 },
205 { "*++a(z)", 0x12 },
206 { "*--a(z)", 0x13 },
207 { "*a++(z)", 0x14 },
208 { "*a--(z)", 0x15 },
209 { "*a++(z)%", 0x16 },
210 { "*a--(z)%", 0x17 },
211 { "*a", 0x18 },
212 { "*a++(y)b", 0x19 },
213 /* Dummy entry, not included in num_indirects. This
214 lets code examine entry i+1 without checking
215 if we've run off the end of the table. */
216 { "", 0x0}
217 };
218
219 #define TIC3X_MODN_MAX 0x19
220
221 const unsigned int tic4x_num_indirects = (((sizeof tic4x_indirects) / (sizeof tic4x_indirects[0])) - 1);
222
223 /* Instruction template. */
224 struct tic4x_inst
225 {
226 char * name;
227 unsigned long opcode;
228 unsigned long opmask;
229 char * args;
230 unsigned long oplevel;
231 };
232
233 typedef struct tic4x_inst tic4x_inst_t;
234
235 /* Opcode infix
236 B condition 16--20 U,C,Z,LO,HI, etc.
237 C condition 23--27 U,C,Z,LO,HI, etc.
238
239 Arguments
240 , required arg follows
241 ; optional arg follows
242
243 Argument types bits [classes] - example
244 -----------------------------------------------------------
245 * indirect (all) 0--15 [A,AB,AU,AF,A2,A3,A6,A7,AY,B,BA,BB,BI,B6,B7] - *+AR0(5), *++AR0(IR0)
246 # direct (for LDP) 0--15 [Z] - @start, start
247 @ direct 0--15 [A,AB,AU,AF,A3,A6,A7,AY,B,BA,BB,BI,B6,B7] - @start, start
248 A address register 22--24 [D] - AR0, AR7
249 B unsigned integer 0--23 [I,I2] - @start, start (absolute on C3x, relative on C4x)
250 C indirect (disp - C4x) 0--7 [S,SC,S2,T,TC,T2,T2C] - *+AR0(5)
251 E register (all) 0--7 [T,TC,T2,T2C] - R0, R7, R11, AR0, DP
252 e register (0-11) 0--7 [S,SC,S2] - R0, R7, R11
253 F short float immediate 0--15 [AF,B,BA,BB] - 3.5, 0e-3.5e-1
254 G register (all) 8--15 [T,TC,T2,T2C] - R0, R7, R11, AR0, DP
255 g register (0-11) 0--7 [S,SC,S2] - R0, R7, R11
256 H register (0-7) 18--16 [LS,M,P,Q] - R0, R7
257 I indirect (no disp) 0--7 [S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0)
258 i indirect (enhanced) 0--7 [LL,LS,M,P,Q,QC] - *+AR0(1), R5
259 J indirect (no disp) 8--15 [LL,LS,P,Q,QC,S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0)
260 j indirect (enhanced) 8--15 [M] - *+AR0(1), R5
261 K register 19--21 [LL,M,Q,QC] - R0, R7
262 L register 22--24 [LL,LS,P,Q,QC] - R0, R7
263 M register (R2,R3) 22--22 [M] R2, R3
264 N register (R0,R1) 23--23 [M] R0, R1
265 O indirect(disp - C4x) 8--15 [S,SC,S2,T,TC,T2] - *+AR0(5)
266 P displacement (PC Rel) 0--15 [D,J,JS] - @start, start
267 Q register (all) 0--15 [A,AB,AU,A2,A3,AY,BA,BI,D,I2,J,JS] - R0, AR0, DP, SP
268 q register (0-11) 0--15 [AF,B,BB] - R0, R7, R11
269 R register (all) 16--20 [A,AB,AU,AF,A6,A7,R,T,TC] - R0, AR0, DP, SP
270 r register (0-11) 16--20 [B,BA,BB,BI,B6,B7,RF,S,SC] - R0, R1, R11
271 S short int immediate 0--15 [A,AB,AY,BI] - -5, 5
272 T integer (C4x) 16--20 [Z] - -5, 12
273 U unsigned integer 0--15 [AU,A3] - 0, 65535
274 V vector (C4x: 0--8) 0--4 [Z] - 25, 7
275 W short int (C4x) 0--7 [T,TC,T2,T2C] - -3, 5
276 X expansion reg (C4x) 0--4 [Z] - IVTP, TVTP
277 Y address reg (C4x) 16--20 [Z] - AR0, DP, SP, IR0
278 Z expansion reg (C4x) 16--20 [Z] - IVTP, TVTP
279 */
280
281 #define TIC4X_OPERANDS_MAX 7 /* Max number of operands for an inst. */
282 #define TIC4X_NAME_MAX 16 /* Max number of chars in parallel name. */
283
284 /* Define the instruction level */
285 #define OP_C3X 0x1 /* C30 support - supported by all */
286 #define OP_C4X 0x2 /* C40 support - C40, C44 */
287 #define OP_ENH 0x4 /* Class LL,LS,M,P,Q,QC enhancements. Argument type
288 I and J is enhanced in these classes - C31>=6.0,
289 C32>=2.0, C33 */
290 #define OP_LPWR 0x8 /* Low power support (LOPOWER, MAXSPEED) - C30>=7.0,
291 LC31, C31>=5.0, C32 */
292 #define OP_IDLE2 0x10 /* Idle2 support (IDLE2) - C30>=7.0, LC31, C31>=5.0,
293 C32, C33, C40>=5.0, C44 */
294
295 /* The following class definition is a classification scheme for
296 putting instructions with similar type of arguments together. It
297 simplifies the op-code definitions significantly, as we then only
298 need to use the class macroes for 95% of the DSP's opcodes.
299 */
300
301 /* A: General 2-operand integer operations
302 Syntax: <i> src, dst
303 src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
304 dst = Register (R)
305 Instr: 15/8 - ABSI, ADDC, ADDI, ASH, CMPI, LDI, LSH, MPYI, NEGB, NEGI,
306 SUBB, SUBC, SUBI, SUBRB, SUBRI, C4x: LBn, LHn, LWLn, LWRn,
307 MBn, MHn, MPYSHI, MPYUHI
308 */
309 #define A_CLASS_INSN(name, opcode, level) \
310 { name, opcode|0x00000000, 0xffe00000, "Q;R", level }, \
311 { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
312 { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \
313 { name, opcode|0x00600000, 0xffe00000, "S,R", level }
314
315 /* AB: General 2-operand integer operation with condition
316 Syntax: <i>c src, dst
317 c = Condition
318 src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
319 dst = Register (R)
320 Instr: 1/0 - LDIc
321 */
322 #define AB_CLASS_INSN(name, opcode, level) \
323 { name, opcode|0x40000000, 0xf0600000, "Q;R", level }, \
324 { name, opcode|0x40200000, 0xf0600000, "@,R", level }, \
325 { name, opcode|0x40400000, 0xf0600000, "*,R", level }, \
326 { name, opcode|0x40600000, 0xf0600000, "S,R", level }
327
328 /* AU: General 2-operand unsigned integer operation
329 Syntax: <i> src, dst
330 src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U)
331 dst = Register (R)
332 Instr: 6/2 - AND, ANDN, NOT, OR, TSTB, XOR, C4x: LBUn, LHUn
333 */
334 #define AU_CLASS_INSN(name, opcode, level) \
335 { name, opcode|0x00000000, 0xffe00000, "Q;R", level }, \
336 { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
337 { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \
338 { name, opcode|0x00600000, 0xffe00000, "U,R", level }
339
340 /* AF: General 2-operand float to integer operation
341 Syntax: <i> src, dst
342 src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F)
343 dst = Register (R)
344 Instr: 1/0 - FIX
345 */
346 #define AF_CLASS_INSN(name, opcode, level) \
347 { name, opcode|0x00000000, 0xffe00000, "q;R", level }, \
348 { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
349 { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \
350 { name, opcode|0x00600000, 0xffe00000, "F,R", level }
351
352 /* A2: Limited 1-operand (integer) operation
353 Syntax: <i> src
354 src = Register (Q), Indirect (*), None
355 Instr: 1/0 - NOP
356 */
357 #define A2_CLASS_INSN(name, opcode, level) \
358 { name, opcode|0x00000000, 0xffe00000, "Q", level }, \
359 { name, opcode|0x00400000, 0xffe00000, "*", level }, \
360 { name, opcode|0x00000000, 0xffe00000, "" , level }
361
362 /* A3: General 1-operand unsigned integer operation
363 Syntax: <i> src
364 src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U)
365 Instr: 1/0 - RPTS
366 */
367 #define A3_CLASS_INSN(name, opcode, level) \
368 { name, opcode|0x00000000, 0xffff0000, "Q", level }, \
369 { name, opcode|0x00200000, 0xffff0000, "@", level }, \
370 { name, opcode|0x00400000, 0xffff0000, "*", level }, \
371 { name, opcode|0x00600000, 0xffff0000, "U", level }
372
373 /* A6: Limited 2-operand integer operation
374 Syntax: <i> src, dst
375 src = Direct (@), Indirect (*)
376 dst = Register (R)
377 Instr: 1/1 - LDII, C4x: SIGI
378 */
379 #define A6_CLASS_INSN(name, opcode, level) \
380 { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
381 { name, opcode|0x00400000, 0xffe00000, "*,R", level }
382
383 /* A7: Limited 2-operand integer store operation
384 Syntax: <i> src, dst
385 src = Register (R)
386 dst = Direct (@), Indirect (*)
387 Instr: 2/0 - STI, STII
388 */
389 #define A7_CLASS_INSN(name, opcode, level) \
390 { name, opcode|0x00200000, 0xffe00000, "R,@", level }, \
391 { name, opcode|0x00400000, 0xffe00000, "R,*", level }
392
393 /* AY: General 2-operand signed address load operation
394 Syntax: <i> src, dst
395 src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
396 dst = Address register - ARx, IRx, DP, BK, SP (Y)
397 Instr: 0/1 - C4x: LDA
398 Note: Q and Y should *never* be the same register
399 */
400 #define AY_CLASS_INSN(name, opcode, level) \
401 { name, opcode|0x00000000, 0xffe00000, "Q,Y", level }, \
402 { name, opcode|0x00200000, 0xffe00000, "@,Y", level }, \
403 { name, opcode|0x00400000, 0xffe00000, "*,Y", level }, \
404 { name, opcode|0x00600000, 0xffe00000, "S,Y", level }
405
406 /* B: General 2-operand float operation
407 Syntax: <i> src, dst
408 src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F)
409 dst = Register 0-11 (r)
410 Instr: 12/2 - ABSF, ADDF, CMPF, LDE, LDF, LDM, MPYF, NEGF, NORM, RND,
411 SUBF, SUBRF, C4x: RSQRF, TOIEEE
412 */
413 #define B_CLASS_INSN(name, opcode, level) \
414 { name, opcode|0x00000000, 0xffe00000, "q;r", level }, \
415 { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \
416 { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \
417 { name, opcode|0x00600000, 0xffe00000, "F,r", level }
418
419 /* BA: General 2-operand integer to float operation
420 Syntax: <i> src, dst
421 src = Register (Q), Direct (@), Indirect (*), Float immediate (F)
422 dst = Register 0-11 (r)
423 Instr: 0/1 - C4x: CRCPF
424 */
425 #define BA_CLASS_INSN(name, opcode, level) \
426 { name, opcode|0x00000000, 0xffe00000, "Q;r", level }, \
427 { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \
428 { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \
429 { name, opcode|0x00600000, 0xffe00000, "F,r", level }
430
431 /* BB: General 2-operand conditional float operation
432 Syntax: <i>c src, dst
433 c = Condition
434 src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F)
435 dst = Register 0-11 (r)
436 Instr: 1/0 - LDFc
437 */
438 #define BB_CLASS_INSN(name, opcode, level) \
439 { name, opcode|0x40000000, 0xf0600000, "q;r", level }, \
440 { name, opcode|0x40200000, 0xf0600000, "@,r", level }, \
441 { name, opcode|0x40400000, 0xf0600000, "*,r", level }, \
442 { name, opcode|0x40600000, 0xf0600000, "F,r", level }
443
444 /* BI: General 2-operand integer to float operation (yet different to BA)
445 Syntax: <i> src, dst
446 src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
447 dst = Register 0-11 (r)
448 Instr: 1/0 - FLOAT
449 */
450 #define BI_CLASS_INSN(name, opcode, level) \
451 { name, opcode|0x00000000, 0xffe00000, "Q;r", level }, \
452 { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \
453 { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \
454 { name, opcode|0x00600000, 0xffe00000, "S,r", level }
455
456 /* B6: Limited 2-operand float operation
457 Syntax: <i> src, dst
458 src = Direct (@), Indirect (*)
459 dst = Register 0-11 (r)
460 Instr: 1/1 - LDFI, C4x: FRIEEE
461 */
462 #define B6_CLASS_INSN(name, opcode, level) \
463 { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \
464 { name, opcode|0x00400000, 0xffe00000, "*,r", level }
465
466 /* B7: Limited 2-operand float store operation
467 Syntax: <i> src, dst
468 src = Register 0-11 (r)
469 dst = Direct (@), Indirect (*)
470 Instr: 2/0 - STF, STFI
471 */
472 #define B7_CLASS_INSN(name, opcode, level) \
473 { name, opcode|0x00200000, 0xffe00000, "r,@", level }, \
474 { name, opcode|0x00400000, 0xffe00000, "r,*", level }
475
476 /* D: Decrement and brach operations
477 Syntax: <i>c ARn, dst
478 c = condition
479 ARn = AR register 0-7 (A)
480 dst = Register (Q), PC-relative (P)
481 Instr: 2/0 - DBc, DBcD
482 Alias: <name1> <name2>
483 */
484 #define D_CLASS_INSN(name1, name2, opcode, level) \
485 { name1, opcode|0x00000000, 0xfe200000, "A,Q", level }, \
486 { name1, opcode|0x02000000, 0xfe200000, "A,P", level }, \
487 { name2, opcode|0x00000000, 0xfe200000, "A,Q", level }, \
488 { name2, opcode|0x02000000, 0xfe200000, "A,P", level }
489
490 /* I: General branch operations
491 Syntax: <i> dst
492 dst = Address (B)
493 Instr: 3/1 - BR, BRD, CALL, C4x: LAJ
494 */
495
496 /* I2: General branch operations (C4x addition)
497 Syntax: <i> dst
498 dst = Address (B), C4x: Register (Q)
499 Instr: 2/0 - RPTB, RPTBD
500 */
501
502 /* J: General conditional branch operations
503 Syntax: <i>c dst
504 c = Condition
505 dst = Register (Q), PC-relative (P)
506 Instr: 2/3 - Bc, BcD, C4x: BcAF, BcAT, LAJc
507 Alias: <name1> <name2>
508 */
509 #define J_CLASS_INSN(name1, name2, opcode, level) \
510 { name1, opcode|0x00000000, 0xffe00000, "Q", level }, \
511 { name1, opcode|0x02000000, 0xffe00000, "P", level }, \
512 { name2, opcode|0x00000000, 0xffe00000, "Q", level }, \
513 { name2, opcode|0x02000000, 0xffe00000, "P", level }
514
515 /* JS: General conditional branch operations
516 Syntax: <i>c dst
517 c = Condition
518 dst = Register (Q), PC-relative (P)
519 Instr: 1/1 - CALLc, C4X: LAJc
520 */
521
522 /* LL: Load-load parallell operation
523 Syntax: <i> src2, dst2 || <i> src1, dst1
524 src1 = Indirect 0,1,IR0,IR1 (J)
525 dst1 = Register 0-7 (K)
526 src2 = Indirect 0,1,IR0,IR1, ENH: Register (i)
527 dst2 = Register 0-7 (L)
528 Instr: 2/0 - LDF||LDF, LDI||LDI
529 Alias: i||i, i1||i2, i2||i1
530 */
531 #define LL_CLASS_INSN(name, opcode, level) \
532 { name "_" name , opcode, 0xfe000000, "i;L|J,K", level }, \
533 { name "2_" name "1", opcode, 0xfe000000, "i;L|J,K", level }, \
534 { name "1_" name "2", opcode, 0xfe000000, "J,K|i;L", level }
535
536 /* LS: Store-store parallell operation
537 Syntax: <i> src2, dst2 || <i> src1, dst1
538 src1 = Register 0-7 (H)
539 dst1 = Indirect 0,1,IR0,IR1 (J)
540 src2 = Register 0-7 (L)
541 dst2 = Indirect 0,1,IR0,IR1, ENH: register (i)
542 Instr: 2/0 - STF||STF, STI||STI
543 Alias: i||i, i1||i2, i2||i1.
544 */
545 #define LS_CLASS_INSN(name, opcode, level) \
546 { name "_" name , opcode, 0xfe000000, "L;i|H,J", level }, \
547 { name "2_" name "1", opcode, 0xfe000000, "L;i|H,J", level }, \
548 { name "1_" name "2", opcode, 0xfe000000, "H,J|L;i", level }
549
550 /* M: General multiply and add/sub operations
551 Syntax: <ia> src3,src4,dst1 || <ib> src2,src1,dst2 [00] - Manual
552 <ia> src3,src1,dst1 || <ib> src2,src4,dst2 [01] - Manual
553 <ia> src1,src3,dst1 || <ib> src2,src4,dst2 [01]
554 <ia> src1,src2,dst1 || <ib> src4,src3,dst2 [02] - Manual
555 <ia> src3,src1,dst1 || <ib> src4,src2,dst2 [03] - Manual
556 <ia> src1,src3,dst1 || <ib> src4,src2,dst2 [03]
557 src1 = Register 0-7 (K)
558 src2 = Register 0-7 (H)
559 src3 = Indirect 0,1,IR0,IR1, ENH: register (j)
560 src4 = Indirect 0,1,IR0,IR1, ENH: register (i)
561 dst1 = Register 0-1 (N)
562 dst2 = Register 2-3 (M)
563 Instr: 4/0 - MPYF3||ADDF3, MPYF3||SUBF3, MPYI3||ADDI3, MPYI3||SUBI3
564 Alias: a||b, a3||n, a||b3, a3||b3, b||a, b3||a, b||a3, b3||a3
565 */
566 #define M_CLASS_INSN(namea, nameb, opcode, level) \
567 { namea "_" nameb, opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \
568 { namea "_" nameb, opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \
569 { namea "_" nameb, opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \
570 { namea "_" nameb, opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \
571 { namea "_" nameb, opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \
572 { namea "_" nameb, opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \
573 { namea "3_" nameb, opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \
574 { namea "3_" nameb, opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \
575 { namea "3_" nameb, opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \
576 { namea "3_" nameb, opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \
577 { namea "3_" nameb, opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \
578 { namea "3_" nameb, opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \
579 { namea "_" nameb "3", opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \
580 { namea "_" nameb "3", opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \
581 { namea "_" nameb "3", opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \
582 { namea "_" nameb "3", opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \
583 { namea "_" nameb "3", opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \
584 { namea "_" nameb "3", opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \
585 { namea "3_" nameb "3", opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \
586 { namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \
587 { namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \
588 { namea "3_" nameb "3", opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \
589 { namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \
590 { namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \
591 { nameb "_" namea, opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \
592 { nameb "_" namea, opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \
593 { nameb "_" namea, opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \
594 { nameb "_" namea, opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \
595 { nameb "_" namea, opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \
596 { nameb "_" namea, opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \
597 { nameb "3_" namea, opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \
598 { nameb "3_" namea, opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \
599 { nameb "3_" namea, opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \
600 { nameb "3_" namea, opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \
601 { nameb "3_" namea, opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \
602 { nameb "3_" namea, opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \
603 { nameb "_" namea "3", opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \
604 { nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \
605 { nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \
606 { nameb "_" namea "3", opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \
607 { nameb "_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \
608 { nameb "_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \
609 { nameb "3_" namea "3", opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \
610 { nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \
611 { nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \
612 { nameb "3_" namea "3", opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \
613 { nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \
614 { nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }
615
616 /* P: General 2-operand operation with parallell store
617 Syntax: <ia> src2, dst1 || <ib> src3, dst2
618 src2 = Indirect 0,1,IR0,IR1, ENH: register (i)
619 dst1 = Register 0-7 (L)
620 src3 = Register 0-7 (H)
621 dst2 = Indirect 0,1,IR0,IR1 (J)
622 Instr: 9/2 - ABSF||STF, ABSI||STI, FIX||STI, FLOAT||STF, LDF||STF,
623 LDI||STI, NEGF||STF, NEGI||STI, NOT||STI, C4x: FRIEEE||STF,
624 TOIEEE||STF
625 Alias: a||b, b||a
626 */
627 #define P_CLASS_INSN(namea, nameb, opcode, level) \
628 { namea "_" nameb, opcode, 0xfe000000, "i;L|H,J", level }, \
629 { nameb "_" namea, opcode, 0xfe000000, "H,J|i;L", level }
630
631 /* Q: General 3-operand operation with parallell store
632 Syntax: <ia> src1, src2, dst1 || <ib> src3, dst2
633 src1 = Register 0-7 (K)
634 src2 = Indirect 0,1,IR0,IR1, ENH: register (i)
635 dst1 = Register 0-7 (L)
636 src3 = Register 0-7 (H)
637 dst2 = Indirect 0,1,IR0,IR1 (J)
638 Instr: 4/0 - ASH3||STI, LSH3||STI, SUBF3||STF, SUBI3||STI
639 Alias: a||b, b||a, a3||b, b||a3
640 */
641 #define Q_CLASS_INSN(namea, nameb, opcode, level) \
642 { namea "_" nameb , opcode, 0xfe000000, "K,i;L|H,J", level }, \
643 { nameb "_" namea , opcode, 0xfe000000, "H,J|K,i;L", level }, \
644 { namea "3_" nameb , opcode, 0xfe000000, "K,i;L|H,J", level }, \
645 { nameb "_" namea "3", opcode, 0xfe000000, "H,J|K,i;L", level }
646
647 /* QC: General commutative 3-operand operation with parallell store
648 Syntax: <ia> src2, src1, dst1 || <ib> src3, dst2
649 <ia> src1, src2, dst1 || <ib> src3, dst2 - Manual
650 src1 = Register 0-7 (K)
651 src2 = Indirect 0,1,IR0,IR1, ENH: register (i)
652 dst1 = Register 0-7 (L)
653 src3 = Register 0-7 (H)
654 dst2 = Indirect 0,1,IR0,IR1 (J)
655 Instr: 7/0 - ADDF3||STF, ADDI3||STI, AND3||STI, MPYF3||STF, MPYI3||STI,
656 OR3||STI, XOR3||STI
657 Alias: a||b, b||a, a3||b, b||a3
658 */
659 #define QC_CLASS_INSN(namea, nameb, opcode, level) \
660 { namea "_" nameb , opcode, 0xfe000000, "i;K;L|H,J", level }, \
661 { namea "_" nameb , opcode, 0xfe000000, "K;i;L|H,J", level }, \
662 { nameb "_" namea , opcode, 0xfe000000, "H,J|i;K;L", level }, \
663 { nameb "_" namea , opcode, 0xfe000000, "H,J|K;i;L", level }, \
664 { namea "3_" nameb , opcode, 0xfe000000, "i;K;L|H,J", level }, \
665 { namea "3_" nameb , opcode, 0xfe000000, "K;i;L|H,J", level }, \
666 { nameb "_" namea "3", opcode, 0xfe000000, "H,J|i;K;L", level }, \
667 { nameb "_" namea "3", opcode, 0xfe000000, "H,J|K;i;L", level }
668
669 /* R: General register integer operation
670 Syntax: <i> dst
671 dst = Register (R)
672 Instr: 6/0 - POP, PUSH, ROL, ROLC, ROR, RORC
673 */
674 #define R_CLASS_INSN(name, opcode, level) \
675 { name, opcode, 0xffe0ffff, "R", level }
676
677 /* RF: General register float operation
678 Syntax: <i> dst
679 dst = Register 0-11 (r)
680 Instr: 2/0 - POPF, PUSHF
681 */
682 #define RF_CLASS_INSN(name, opcode, level) \
683 { name, opcode, 0xffe0ffff, "r", level }
684
685 /* S: General 3-operand float operation
686 Syntax: <i> src2, src1, dst
687 src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
688 src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
689 dst = Register 0-11 (r)
690 Instr: 1/0 - SUBF3
691 Alias: i, i3
692 */
693 #define S_CLASS_INSN(name, opcode, level) \
694 { name, opcode|0x20000000, 0xffe00000, "e,g;r", level }, \
695 { name, opcode|0x20200000, 0xffe00000, "e,J,r", level }, \
696 { name, opcode|0x20400000, 0xffe00000, "I,g;r", level }, \
697 { name, opcode|0x20600000, 0xffe00000, "I,J,r", level }, \
698 { name, opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \
699 { name, opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }, \
700 { name "3", opcode|0x20000000, 0xffe00000, "e,g;r", level }, \
701 { name "3", opcode|0x20200000, 0xffe00000, "e,J,r", level }, \
702 { name "3", opcode|0x20400000, 0xffe00000, "I,g;r", level }, \
703 { name "3", opcode|0x20600000, 0xffe00000, "I,J,r", level }, \
704 { name "3", opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \
705 { name "3", opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }
706
707 /* SC: General commutative 3-operand float operation
708 Syntax: <i> src2, src1, dst - Manual
709 <i> src1, src2, dst
710 src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
711 src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
712 dst = Register 0-11 (r)
713 Instr: 2/0 - ADDF3, MPYF3
714 Alias: i, i3
715 */
716 #define SC_CLASS_INSN(name, opcode, level) \
717 { name, opcode|0x20000000, 0xffe00000, "e,g;r", level }, \
718 { name, opcode|0x20200000, 0xffe00000, "e,J,r", level }, \
719 { name, opcode|0x20400000, 0xffe00000, "I,g;r", level }, \
720 { name, opcode|0x20600000, 0xffe00000, "I,J,r", level }, \
721 { name, opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \
722 { name, opcode|0x30200000, 0xffe00000, "g,C,r", OP_C4X }, \
723 { name, opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }, \
724 { name "3", opcode|0x20000000, 0xffe00000, "e,g;r", level }, \
725 { name "3", opcode|0x20200000, 0xffe00000, "e,J,r", level }, \
726 { name "3", opcode|0x20400000, 0xffe00000, "I,g;r", level }, \
727 { name "3", opcode|0x20600000, 0xffe00000, "I,J,r", level }, \
728 { name "3", opcode|0x30200000, 0xffe00000, "g,C,r", OP_C4X }, \
729 { name "3", opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \
730 { name "3", opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }
731
732 /* S2: General 3-operand float operation with 2 args
733 Syntax: <i> src2, src1
734 src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
735 src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
736 Instr: 1/0 - CMPF3
737 Alias: i, i3
738 */
739 #define S2_CLASS_INSN(name, opcode, level) \
740 { name, opcode|0x20000000, 0xffe00000, "e,g", level }, \
741 { name, opcode|0x20200000, 0xffe00000, "e,J", level }, \
742 { name, opcode|0x20400000, 0xffe00000, "I,g", level }, \
743 { name, opcode|0x20600000, 0xffe00000, "I,J", level }, \
744 { name, opcode|0x30200000, 0xffe00000, "C,g", OP_C4X }, \
745 { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \
746 { name "3", opcode|0x20000000, 0xffe00000, "e,g", level }, \
747 { name "3", opcode|0x20200000, 0xffe00000, "e,J", level }, \
748 { name "3", opcode|0x20400000, 0xffe00000, "I,g", level }, \
749 { name "3", opcode|0x20600000, 0xffe00000, "I,J", level }, \
750 { name "3", opcode|0x30200000, 0xffe00000, "C,g", OP_C4X }, \
751 { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }
752
753 /* T: General 3-operand integer operand
754 Syntax: <i> src2, src1, dst
755 src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
756 src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
757 dst = Register (R)
758 Instr: 5/0 - ANDN3, ASH3, LSH3, SUBB3, SUBI3
759 Alias: i, i3
760 */
761 #define T_CLASS_INSN(name, opcode, level) \
762 { name, opcode|0x20000000, 0xffe00000, "E,G;R", level }, \
763 { name, opcode|0x20200000, 0xffe00000, "E,J,R", level }, \
764 { name, opcode|0x20400000, 0xffe00000, "I,G;R", level }, \
765 { name, opcode|0x20600000, 0xffe00000, "I,J,R", level }, \
766 { name, opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \
767 { name, opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \
768 { name, opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \
769 { name, opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }, \
770 { name "3", opcode|0x20000000, 0xffe00000, "E,G;R", level }, \
771 { name "3", opcode|0x20200000, 0xffe00000, "E,J,R", level }, \
772 { name "3", opcode|0x20400000, 0xffe00000, "I,G;R", level }, \
773 { name "3", opcode|0x20600000, 0xffe00000, "I,J,R", level }, \
774 { name "3", opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \
775 { name "3", opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \
776 { name "3", opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \
777 { name "3", opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }
778
779 /* TC: General commutative 3-operand integer operation
780 Syntax: <i> src2, src1, dst
781 <i> src1, src2, dst
782 src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
783 src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
784 dst = Register (R)
785 Instr: 6/2 - ADDC3, ADDI3, AND3, MPYI3, OR3, XOR3, C4x: MPYSHI, MPYUHI
786 Alias: i, i3
787 */
788 #define TC_CLASS_INSN(name, opcode, level) \
789 { name, opcode|0x20000000, 0xffe00000, "E,G;R", level }, \
790 { name, opcode|0x20200000, 0xffe00000, "E,J,R", level }, \
791 { name, opcode|0x20400000, 0xffe00000, "I,G;R", level }, \
792 { name, opcode|0x20600000, 0xffe00000, "I,J,R", level }, \
793 { name, opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \
794 { name, opcode|0x30000000, 0xffe00000, "G,W,R", OP_C4X }, \
795 { name, opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \
796 { name, opcode|0x30200000, 0xffe00000, "G,C,R", OP_C4X }, \
797 { name, opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \
798 { name, opcode|0x30400000, 0xffe00000, "O,W,R", OP_C4X }, \
799 { name, opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }, \
800 { name "3", opcode|0x20000000, 0xffe00000, "E,G;R", level }, \
801 { name "3", opcode|0x20200000, 0xffe00000, "E,J,R", level }, \
802 { name "3", opcode|0x20400000, 0xffe00000, "I,G;R", level }, \
803 { name "3", opcode|0x20600000, 0xffe00000, "I,J,R", level }, \
804 { name "3", opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \
805 { name "3", opcode|0x30000000, 0xffe00000, "G,W,R", OP_C4X }, \
806 { name "3", opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \
807 { name "3", opcode|0x30200000, 0xffe00000, "G,C,R", OP_C4X }, \
808 { name "3", opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \
809 { name "3", opcode|0x30400000, 0xffe00000, "O,W,R", OP_C4X }, \
810 { name "3", opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }
811
812 /* T2: General 3-operand integer operation with 2 args
813 Syntax: <i> src2, src1
814 src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
815 src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
816 Instr: 1/0 - CMPI3
817 Alias: i, i3
818 */
819 #define T2_CLASS_INSN(name, opcode, level) \
820 { name, opcode|0x20000000, 0xffe00000, "E,G", level }, \
821 { name, opcode|0x20200000, 0xffe00000, "E,J", level }, \
822 { name, opcode|0x20400000, 0xffe00000, "I,G", level }, \
823 { name, opcode|0x20600000, 0xffe00000, "I,J", level }, \
824 { name, opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \
825 { name, opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \
826 { name, opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \
827 { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \
828 { name "3", opcode|0x20000000, 0xffe00000, "E,G", level }, \
829 { name "3", opcode|0x20200000, 0xffe00000, "E,J", level }, \
830 { name "3", opcode|0x20400000, 0xffe00000, "I,G", level }, \
831 { name "3", opcode|0x20600000, 0xffe00000, "I,J", level }, \
832 { name "3", opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \
833 { name "3", opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \
834 { name "3", opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \
835 { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }
836
837 /* T2C: General commutative 3-operand integer operation with 2 args
838 Syntax: <i> src2, src1 - Manual
839 <i> src1, src2
840 src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
841 src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (0)
842 Instr: 1/0 - TSTB3
843 Alias: i, i3
844 */
845 #define T2C_CLASS_INSN(name, opcode, level) \
846 { name, opcode|0x20000000, 0xffe00000, "E,G", level }, \
847 { name, opcode|0x20200000, 0xffe00000, "E,J", level }, \
848 { name, opcode|0x20400000, 0xffe00000, "I,G", level }, \
849 { name, opcode|0x20600000, 0xffe00000, "I,J", level }, \
850 { name, opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \
851 { name, opcode|0x30000000, 0xffe00000, "G,W", OP_C4X }, \
852 { name, opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \
853 { name, opcode|0x30200000, 0xffe00000, "G,C", OP_C4X }, \
854 { name, opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \
855 { name, opcode|0x30400000, 0xffe00000, "O,W", OP_C4X }, \
856 { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \
857 { name "3", opcode|0x20000000, 0xffe00000, "E,G", level }, \
858 { name "3", opcode|0x20200000, 0xffe00000, "E,J", level }, \
859 { name "3", opcode|0x20400000, 0xffe00000, "I,G", level }, \
860 { name "3", opcode|0x20600000, 0xffe00000, "I,J", level }, \
861 { name "3", opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \
862 { name "3", opcode|0x30000000, 0xffe00000, "G,W", OP_C4X }, \
863 { name "3", opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \
864 { name "3", opcode|0x30200000, 0xffe00000, "G,C", OP_C4X }, \
865 { name "3", opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \
866 { name "3", opcode|0x30400000, 0xffe00000, "O,W", OP_C4X }, \
867 { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }
868
869 /* Z: Misc operations with or without arguments
870 Syntax: <i> <arg1>,...
871 Instr: 16 - RETIc, RETSc, SIGI(c3X), SWI, IDLE, IDLE2, RETIcD,
872 TRAPc, LATc, LDEP, LDEHI, LDEPE, LDPK, STIK, LDP, IACK
873 */
874
875
876 /* Define tic4x opcodes for assembler and disassembler. */
877 static const tic4x_inst_t tic4x_insts[] =
878 {
879 /* Put synonyms after the desired forms in table so that they get
880 overwritten in the lookup table. The disassembler will thus
881 print the `proper' mnemonics. Note that the disassembler
882 only decodes the 11 MSBs, so instructions like ldp @0x500 will
883 be printed as ldiu 5, dp. Note that with parallel instructions,
884 the second part is executed before the first part, unless
885 the sti1||sti2 form is used. We also allow sti2||sti1
886 which is equivalent to the default sti||sti form.
887 */
888 B_CLASS_INSN( "absf", 0x00000000, OP_C3X ),
889 P_CLASS_INSN( "absf", "stf", 0xc8000000, OP_C3X ),
890 A_CLASS_INSN( "absi", 0x00800000, OP_C3X ),
891 P_CLASS_INSN( "absi", "sti", 0xca000000, OP_C3X ),
892 A_CLASS_INSN( "addc", 0x01000000, OP_C3X ),
893 TC_CLASS_INSN( "addc", 0x00000000, OP_C3X ),
894 B_CLASS_INSN( "addf", 0x01800000, OP_C3X ),
895 SC_CLASS_INSN( "addf", 0x00800000, OP_C3X ),
896 QC_CLASS_INSN( "addf", "stf", 0xcc000000, OP_C3X ),
897 A_CLASS_INSN( "addi", 0x02000000, OP_C3X ),
898 TC_CLASS_INSN( "addi", 0x01000000, OP_C3X ),
899 QC_CLASS_INSN( "addi", "sti", 0xce000000, OP_C3X ),
900 AU_CLASS_INSN( "and", 0x02800000, OP_C3X ),
901 TC_CLASS_INSN( "and", 0x01800000, OP_C3X ),
902 QC_CLASS_INSN( "and", "sti", 0xd0000000, OP_C3X ),
903 AU_CLASS_INSN( "andn", 0x03000000, OP_C3X ),
904 T_CLASS_INSN( "andn", 0x02000000, OP_C3X ),
905 A_CLASS_INSN( "ash", 0x03800000, OP_C3X ),
906 T_CLASS_INSN( "ash", 0x02800000, OP_C3X ),
907 Q_CLASS_INSN( "ash", "sti", 0xd2000000, OP_C3X ),
908 J_CLASS_INSN( "bB", "b", 0x68000000, OP_C3X ),
909 J_CLASS_INSN( "bBd", "bd", 0x68200000, OP_C3X ),
910 J_CLASS_INSN( "bBaf", "baf", 0x68a00000, OP_C4X ),
911 J_CLASS_INSN( "bBat", "bat", 0x68600000, OP_C4X ),
912 { "br", 0x60000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */
913 { "brd", 0x61000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */
914 { "call", 0x62000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */
915 { "callB", 0x70000000, 0xffe00000, "Q" , OP_C3X }, /* JS_CLASS */
916 { "callB", 0x72000000, 0xffe00000, "P" , OP_C3X }, /* JS_CLASS */
917 B_CLASS_INSN( "cmpf", 0x04000000, OP_C3X ),
918 S2_CLASS_INSN( "cmpf", 0x03000000, OP_C3X ),
919 A_CLASS_INSN( "cmpi", 0x04800000, OP_C3X ),
920 T2_CLASS_INSN( "cmpi", 0x03800000, OP_C3X ),
921 D_CLASS_INSN( "dbB", "db", 0x6c000000, OP_C3X ),
922 D_CLASS_INSN( "dbBd", "dbd", 0x6c200000, OP_C3X ),
923 AF_CLASS_INSN( "fix", 0x05000000, OP_C3X ),
924 P_CLASS_INSN( "fix", "sti", 0xd4000000, OP_C3X ),
925 BI_CLASS_INSN( "float", 0x05800000, OP_C3X ),
926 P_CLASS_INSN( "float", "stf", 0xd6000000, OP_C3X ),
927 B6_CLASS_INSN( "frieee", 0x1c000000, OP_C4X ),
928 P_CLASS_INSN( "frieee","stf", 0xf2000000, OP_C4X ),
929 { "iack", 0x1b200000, 0xffe00000, "@" , OP_C3X }, /* Z_CLASS */
930 { "iack", 0x1b400000, 0xffe00000, "*" , OP_C3X }, /* Z_CLASS */
931 { "idle", 0x06000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */
932 { "idlez", 0x06000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */
933 { "idle2", 0x06000001, 0xffffffff, "" , OP_IDLE2 }, /* Z_CLASS */
934 { "laj", 0x63000000, 0xff000000, "B" , OP_C4X }, /* I_CLASS */
935 { "lajB", 0x70200000, 0xffe00000, "Q" , OP_C4X }, /* JS_CLASS */
936 { "lajB", 0x72200000, 0xffe00000, "P" , OP_C4X }, /* JS_CLASS */
937 { "latB", 0x74800000, 0xffe00000, "V" , OP_C4X }, /* Z_CLASS */
938 A_CLASS_INSN( "lb0", 0xb0000000, OP_C4X ),
939 A_CLASS_INSN( "lb1", 0xb0800000, OP_C4X ),
940 A_CLASS_INSN( "lb2", 0xb1000000, OP_C4X ),
941 A_CLASS_INSN( "lb3", 0xb1800000, OP_C4X ),
942 AU_CLASS_INSN( "lbu0", 0xb2000000, OP_C4X ),
943 AU_CLASS_INSN( "lbu1", 0xb2800000, OP_C4X ),
944 AU_CLASS_INSN( "lbu2", 0xb3000000, OP_C4X ),
945 AU_CLASS_INSN( "lbu3", 0xb3800000, OP_C4X ),
946 AY_CLASS_INSN( "lda", 0x1e800000, OP_C4X ),
947 B_CLASS_INSN( "lde", 0x06800000, OP_C3X ),
948 { "ldep", 0x76000000, 0xffe00000, "X,R" , OP_C4X }, /* Z_CLASS */
949 B_CLASS_INSN( "ldf", 0x07000000, OP_C3X ),
950 LL_CLASS_INSN( "ldf", 0xc4000000, OP_C3X ),
951 P_CLASS_INSN( "ldf", "stf", 0xd8000000, OP_C3X ),
952 BB_CLASS_INSN( "ldfC", 0x00000000, OP_C3X ),
953 B6_CLASS_INSN( "ldfi", 0x07800000, OP_C3X ),
954 { "ldhi", 0x1fe00000, 0xffe00000, "U,R" , OP_C4X }, /* Z_CLASS */
955 { "ldhi", 0x1fe00000, 0xffe00000, "#,R" , OP_C4X }, /* Z_CLASS */
956 A_CLASS_INSN( "ldi", 0x08000000, OP_C3X ),
957 LL_CLASS_INSN( "ldi", 0xc6000000, OP_C3X ),
958 P_CLASS_INSN( "ldi", "sti", 0xda000000, OP_C3X ),
959 AB_CLASS_INSN( "ldiC", 0x10000000, OP_C3X ),
960 A6_CLASS_INSN( "ldii", 0x08800000, OP_C3X ),
961 { "ldp", 0x50700000, 0xffff0000, "#" , OP_C3X }, /* Z_CLASS - synonym for ldiu #,dp */
962 B_CLASS_INSN( "ldm", 0x09000000, OP_C3X ),
963 { "ldpe", 0x76800000, 0xffe00000, "Q,Z" , OP_C4X }, /* Z_CLASS */
964 { "ldpk", 0x1F700000, 0xffff0000, "#" , OP_C4X }, /* Z_CLASS */
965 A_CLASS_INSN( "lh0", 0xba000000, OP_C4X ),
966 A_CLASS_INSN( "lh1", 0xba800000, OP_C4X ),
967 AU_CLASS_INSN( "lhu0", 0xbb000000, OP_C4X ),
968 AU_CLASS_INSN( "lhu1", 0xbb800000, OP_C4X ),
969 { "lopower", 0x10800001,0xffffffff, "" , OP_LPWR }, /* Z_CLASS */
970 A_CLASS_INSN( "lsh", 0x09800000, OP_C3X ),
971 T_CLASS_INSN( "lsh", 0x04000000, OP_C3X ),
972 Q_CLASS_INSN( "lsh", "sti", 0xdc000000, OP_C3X ),
973 A_CLASS_INSN( "lwl0", 0xb4000000, OP_C4X ),
974 A_CLASS_INSN( "lwl1", 0xb4800000, OP_C4X ),
975 A_CLASS_INSN( "lwl2", 0xb5000000, OP_C4X ),
976 A_CLASS_INSN( "lwl3", 0xb5800000, OP_C4X ),
977 A_CLASS_INSN( "lwr0", 0xb6000000, OP_C4X ),
978 A_CLASS_INSN( "lwr1", 0xb6800000, OP_C4X ),
979 A_CLASS_INSN( "lwr2", 0xb7000000, OP_C4X ),
980 A_CLASS_INSN( "lwr3", 0xb7800000, OP_C4X ),
981 { "maxspeed",0x10800000,0xffffffff, "" , OP_LPWR }, /* Z_CLASS */
982 A_CLASS_INSN( "mb0", 0xb8000000, OP_C4X ),
983 A_CLASS_INSN( "mb1", 0xb8800000, OP_C4X ),
984 A_CLASS_INSN( "mb2", 0xb9000000, OP_C4X ),
985 A_CLASS_INSN( "mb3", 0xb9800000, OP_C4X ),
986 A_CLASS_INSN( "mh0", 0xbc000000, OP_C4X ),
987 A_CLASS_INSN( "mh1", 0xbc800000, OP_C4X ),
988 A_CLASS_INSN( "mh2", 0xbd000000, OP_C4X ),
989 A_CLASS_INSN( "mh3", 0xbd800000, OP_C4X ),
990 B_CLASS_INSN( "mpyf", 0x0a000000, OP_C3X ),
991 SC_CLASS_INSN( "mpyf", 0x04800000, OP_C3X ),
992 M_CLASS_INSN( "mpyf", "addf", 0x80000000, OP_C3X ),
993 QC_CLASS_INSN( "mpyf", "stf", 0xde000000, OP_C3X ),
994 M_CLASS_INSN( "mpyf", "subf", 0x84000000, OP_C3X ),
995 A_CLASS_INSN( "mpyi", 0x0a800000, OP_C3X ),
996 TC_CLASS_INSN( "mpyi", 0x05000000, OP_C3X ),
997 M_CLASS_INSN( "mpyi", "addi", 0x88000000, OP_C3X ),
998 QC_CLASS_INSN( "mpyi", "sti", 0xe0000000, OP_C3X ),
999 M_CLASS_INSN( "mpyi", "subi", 0x8c000000, OP_C3X ),
1000 A_CLASS_INSN( "mpyshi", 0x1d800000, OP_C4X ),
1001 TC_CLASS_INSN( "mpyshi", 0x28800000, OP_C4X ),
1002 A_CLASS_INSN( "mpyuhi", 0x1e000000, OP_C4X ),
1003 TC_CLASS_INSN( "mpyuhi", 0x29000000, OP_C4X ),
1004 A_CLASS_INSN( "negb", 0x0b000000, OP_C3X ),
1005 B_CLASS_INSN( "negf", 0x0b800000, OP_C3X ),
1006 P_CLASS_INSN( "negf", "stf", 0xe2000000, OP_C3X ),
1007 A_CLASS_INSN( "negi", 0x0c000000, OP_C3X ),
1008 P_CLASS_INSN( "negi", "sti", 0xe4000000, OP_C3X ),
1009 A2_CLASS_INSN( "nop", 0x0c800000, OP_C3X ),
1010 B_CLASS_INSN( "norm", 0x0d000000, OP_C3X ),
1011 AU_CLASS_INSN( "not", 0x0d800000, OP_C3X ),
1012 P_CLASS_INSN( "not", "sti", 0xe6000000, OP_C3X ),
1013 AU_CLASS_INSN( "or", 0x10000000, OP_C3X ),
1014 TC_CLASS_INSN( "or", 0x05800000, OP_C3X ),
1015 QC_CLASS_INSN( "or", "sti", 0xe8000000, OP_C3X ),
1016 R_CLASS_INSN( "pop", 0x0e200000, OP_C3X ),
1017 RF_CLASS_INSN( "popf", 0x0ea00000, OP_C3X ),
1018 R_CLASS_INSN( "push", 0x0f200000, OP_C3X ),
1019 RF_CLASS_INSN( "pushf", 0x0fa00000, OP_C3X ),
1020 BA_CLASS_INSN( "rcpf", 0x1d000000, OP_C4X ),
1021 { "retiB", 0x78000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */
1022 { "reti", 0x78000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS - Alias for retiu */
1023 { "retiBd", 0x78200000, 0xffe00000, "" , OP_C4X }, /* Z_CLASS */
1024 { "retid", 0x78200000, 0xffe00000, "" , OP_C4X }, /* Z_CLASS - Alias for retiud */
1025 { "retsB", 0x78800000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */
1026 { "rets", 0x78800000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS - Alias for retsu */
1027 B_CLASS_INSN( "rnd", 0x11000000, OP_C3X ),
1028 R_CLASS_INSN( "rol", 0x11e00001, OP_C3X ),
1029 R_CLASS_INSN( "rolc", 0x12600001, OP_C3X ),
1030 R_CLASS_INSN( "ror", 0x12e0ffff, OP_C3X ),
1031 R_CLASS_INSN( "rorc", 0x1360ffff, OP_C3X ),
1032 { "rptb", 0x64000000, 0xff000000, "B" , OP_C3X }, /* I2_CLASS */
1033 { "rptb", 0x79000000, 0xff000000, "Q" , OP_C4X }, /* I2_CLASS */
1034 { "rptbd", 0x65000000, 0xff000000, "B" , OP_C4X }, /* I2_CLASS */
1035 { "rptbd", 0x79800000, 0xff000000, "Q" , OP_C4X }, /* I2_CLASS */
1036 A3_CLASS_INSN( "rpts", 0x139b0000, OP_C3X ),
1037 B_CLASS_INSN( "rsqrf", 0x1c800000, OP_C4X ),
1038 { "sigi", 0x16000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */
1039 A6_CLASS_INSN( "sigi", 0x16000000, OP_C4X ),
1040 B7_CLASS_INSN( "stf", 0x14000000, OP_C3X ),
1041 LS_CLASS_INSN( "stf", 0xc0000000, OP_C3X ),
1042 B7_CLASS_INSN( "stfi", 0x14800000, OP_C3X ),
1043 A7_CLASS_INSN( "sti", 0x15000000, OP_C3X ),
1044 { "sti", 0x15000000, 0xffe00000, "T,@" , OP_C4X }, /* Class A7 - Alias for stik */
1045 { "sti", 0x15600000, 0xffe00000, "T,*" , OP_C4X }, /* Class A7 */
1046 LS_CLASS_INSN( "sti", 0xc2000000, OP_C3X ),
1047 A7_CLASS_INSN( "stii", 0x15800000, OP_C3X ),
1048 { "stik", 0x15000000, 0xffe00000, "T,@" , OP_C4X }, /* Z_CLASS */
1049 { "stik", 0x15600000, 0xffe00000, "T,*" , OP_C4X }, /* Z_CLASS */
1050 A_CLASS_INSN( "subb", 0x16800000, OP_C3X ),
1051 T_CLASS_INSN( "subb", 0x06000000, OP_C3X ),
1052 A_CLASS_INSN( "subc", 0x17000000, OP_C3X ),
1053 B_CLASS_INSN( "subf", 0x17800000, OP_C3X ),
1054 S_CLASS_INSN( "subf", 0x06800000, OP_C3X ),
1055 Q_CLASS_INSN( "subf", "stf", 0xea000000, OP_C3X ),
1056 A_CLASS_INSN( "subi", 0x18000000, OP_C3X ),
1057 T_CLASS_INSN( "subi", 0x07000000, OP_C3X ),
1058 Q_CLASS_INSN( "subi", "sti", 0xec000000, OP_C3X ),
1059 A_CLASS_INSN( "subrb", 0x18800000, OP_C3X ),
1060 B_CLASS_INSN( "subrf", 0x19000000, OP_C3X ),
1061 A_CLASS_INSN( "subri", 0x19800000, OP_C3X ),
1062 { "swi", 0x66000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */
1063 B_CLASS_INSN( "toieee", 0x1b800000, OP_C4X ),
1064 P_CLASS_INSN( "toieee","stf", 0xf0000000, OP_C4X ),
1065 { "trapB", 0x74000000, 0xffe00000, "V" , OP_C3X }, /* Z_CLASS */
1066 { "trap", 0x74000000, 0xffe00000, "V" , OP_C3X }, /* Z_CLASS - Alias for trapu */
1067 AU_CLASS_INSN( "tstb", 0x1a000000, OP_C3X ),
1068 T2C_CLASS_INSN("tstb", 0x07800000, OP_C3X ),
1069 AU_CLASS_INSN( "xor", 0x1a800000, OP_C3X ),
1070 TC_CLASS_INSN( "xor", 0x08000000, OP_C3X ),
1071 QC_CLASS_INSN( "xor", "sti", 0xee000000, OP_C3X ),
1072
1073 /* Dummy entry, not included in tic4x_num_insts. This
1074 lets code examine entry i + 1 without checking
1075 if we've run off the end of the table. */
1076 { "", 0x0, 0x00, "", 0 }
1077 };
1078
1079 const unsigned int tic4x_num_insts = (((sizeof tic4x_insts) / (sizeof tic4x_insts[0])) - 1);
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